diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index de667687cc..32af171417 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -22,6 +22,13 @@ #include "hal/gpio_hal.h" #include "esp_rom_gpio.h" #include "esp_private/esp_gpio_reserve.h" +#include "esp_private/periph_ctrl.h" + +#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT +#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define RTCIO_RCC_ATOMIC() +#endif #if (SOC_RTCIO_PIN_COUNT > 0) #include "hal/rtc_io_hal.h" @@ -59,6 +66,9 @@ typedef struct { gpio_isr_func_t *gpio_isr_func; gpio_isr_handle_t gpio_isr_handle; uint64_t isr_clr_on_entry_mask; // for edge-triggered interrupts, interrupt status bits should be cleared before entering per-pin handlers +#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_LP_IO_CLOCK_IS_INDEPENDENT + uint32_t gpio_wakeup_mask; +#endif } gpio_context_t; static gpio_hal_context_t _gpio_hal = { @@ -71,6 +81,9 @@ static gpio_context_t gpio_context = { .isr_core_id = GPIO_ISR_CORE_ID_UNINIT, .gpio_isr_func = NULL, .isr_clr_on_entry_mask = 0, +#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_LP_IO_CLOCK_IS_INDEPENDENT + .gpio_wakeup_mask = 0, +#endif }; esp_err_t gpio_pullup_en(gpio_num_t gpio_num) @@ -978,6 +991,14 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int return ESP_ERR_INVALID_ARG; } portENTER_CRITICAL(&gpio_context.gpio_spinlock); +#if SOC_LP_IO_CLOCK_IS_INDEPENDENT + if (gpio_context.gpio_wakeup_mask == 0) { + RTCIO_RCC_ATOMIC() { + rtcio_ll_enable_io_clock(true); + } + } + gpio_context.gpio_wakeup_mask |= (1ULL << gpio_num); +#endif gpio_hal_deepsleep_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type); #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num); @@ -996,6 +1017,14 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num) gpio_hal_deepsleep_wakeup_disable(gpio_context.gpio_hal, gpio_num); #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num); +#endif +#if SOC_LP_IO_CLOCK_IS_INDEPENDENT + gpio_context.gpio_wakeup_mask &= ~(1ULL << gpio_num); + if (gpio_context.gpio_wakeup_mask == 0) { + RTCIO_RCC_ATOMIC() { + rtcio_ll_enable_io_clock(false); + } + } #endif portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; diff --git a/components/esp_driver_gpio/src/rtc_io.c b/components/esp_driver_gpio/src/rtc_io.c index 29ee26d299..62d5269d97 100644 --- a/components/esp_driver_gpio/src/rtc_io.c +++ b/components/esp_driver_gpio/src/rtc_io.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,7 @@ #include "esp_log.h" #include "esp_err.h" #include "esp_check.h" +#include "esp_private/periph_ctrl.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/timers.h" @@ -17,6 +18,16 @@ #include "soc/rtc_io_periph.h" #include "soc/soc_caps.h" +#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT +// For `rtcio_hal_function_select` using, clock reg option is inlined in it, +// so remove the declaration check of __DECLARE_RCC_RC_ATOMIC_ENV +#define RTCIO_RCC_ATOMIC() \ + for (int i = 1; i ? (periph_rcc_enter(), 1) : 0; \ + periph_rcc_exit(), i--) +#else +#define RTCIO_RCC_ATOMIC() +#endif + static const char __attribute__((__unused__)) *RTCIO_TAG = "RTCIO"; extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished. @@ -45,7 +56,9 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num) { ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error"); RTCIO_ENTER_CRITICAL(); - rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_RTC); + RTCIO_RCC_ATOMIC() { + rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_RTC); + } RTCIO_EXIT_CRITICAL(); return ESP_OK; @@ -55,8 +68,10 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num) { ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error"); RTCIO_ENTER_CRITICAL(); - // Select Gpio as Digital Gpio - rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL); + RTCIO_RCC_ATOMIC() { + // Select Gpio as Digital Gpio + rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL); + } RTCIO_EXIT_CRITICAL(); return ESP_OK; diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 314c2253dd..0ee6232995 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -14,6 +14,7 @@ #include "esp_sleep.h" #include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_timer_private.h" +#include "esp_private/periph_ctrl.h" #include "esp_private/sleep_event.h" #include "esp_private/system_internal.h" #include "esp_log.h" @@ -106,6 +107,16 @@ #include "esp_private/sleep_retention.h" #endif +#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT +// For `rtcio_hal_function_select` using, clock reg option is inlined in it, +// so remove the declaration check of __DECLARE_RCC_RC_ATOMIC_ENV +#define RTCIO_RCC_ATOMIC() \ + for (int i = 1; i ? (periph_rcc_enter(), 1) : 0; \ + periph_rcc_exit(), i--) +#else +#define RTCIO_RCC_ATOMIC() +#endif + // If light sleep time is less than that, don't power down flash #define FLASH_PD_MIN_SLEEP_TIME_US 2000 @@ -1500,7 +1511,9 @@ static void ext0_wakeup_prepare(void) { int rtc_gpio_num = s_config.ext0_rtc_gpio_num; rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level); - rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC); + RTCIO_RCC_ATOMIC() { + rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC); + } rtcio_hal_input_enable(rtc_gpio_num); } @@ -1631,7 +1644,9 @@ static void ext1_wakeup_prepare(void) } #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED // Route pad to RTC - rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_RTC); + RTCIO_RCC_ATOMIC() { + rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_RTC); + } // set input enable in sleep mode rtcio_hal_input_enable(rtc_pin); #if SOC_PM_SUPPORT_RTC_PERIPH_PD @@ -1646,7 +1661,9 @@ static void ext1_wakeup_prepare(void) * a pathway to EXT1. */ // Route pad to DIGITAL - rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_DIGITAL); + RTCIO_RCC_ATOMIC() { + rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_DIGITAL); + } // set input enable gpio_ll_input_enable(&GPIO, gpio); // hold rtc_pin to use it during sleep state diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/hal/esp32c6/include/hal/rtc_io_ll.h index 0daa850c82..550d6accf0 100644 --- a/components/hal/esp32c6/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c6/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,7 @@ #include "soc/pcr_struct.h" #include "soc/lp_io_struct.h" #include "soc/lp_aon_struct.h" +#include "soc/lpperi_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" #include "hal/assert.h" @@ -55,6 +56,18 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) LP_IO.gpio[rtcio_num].mcu_sel = func; } +/** + * @brief Enable/Disable LP_IO peripheral clock. + * + * @param enable true to enable the clock / false to enable the clock + */ +static inline void _rtcio_ll_enable_io_clock(bool enable) +{ + LPPERI.clk_en.lp_io_ck_en = enable; +} + +#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__) + /** * @brief Select the rtcio function. * @@ -70,6 +83,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) if (func == RTCIO_LL_FUNC_RTC) { // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) { + _rtcio_ll_enable_io_clock(true); + } sel_mask |= BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); //0:RTC FUNCTION 1,2,3:Reserved @@ -79,6 +95,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); sel_mask &= ~BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) { + _rtcio_ll_enable_io_clock(false); + } } } diff --git a/components/hal/esp32h2/include/hal/rtc_io_ll.h b/components/hal/esp32h2/include/hal/rtc_io_ll.h index dcd32b2239..5899ce63ad 100644 --- a/components/hal/esp32h2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,10 @@ #pragma once +#include +#include "soc/soc_caps.h" #include "soc/lp_aon_struct.h" +#include "soc/lpperi_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" @@ -27,6 +30,19 @@ typedef enum { RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ } rtcio_ll_func_t; + +/** + * @brief Enable/Disable LP_IO peripheral clock. + * + * @param enable true to enable the clock / false to enable the clock + */ +static inline void _rtcio_ll_enable_io_clock(bool enable) +{ + LPPERI.clk_en.lp_io_ck_en = enable; +} + +#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__) + /** * @brief Select the rtcio function. * @@ -40,6 +56,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) if (func == RTCIO_LL_FUNC_RTC) { // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) { + _rtcio_ll_enable_io_clock(true); + } sel_mask |= BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); } else if (func == RTCIO_LL_FUNC_DIGITAL) { @@ -47,6 +66,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); sel_mask &= ~BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + if((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) { + _rtcio_ll_enable_io_clock(false); + } } } diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index ca4a8f5cec..b20960ed1d 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -475,6 +475,10 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y +config SOC_LP_IO_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_GPIO_IN_RANGE_MAX int default 30 @@ -523,6 +527,10 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y +config SOC_RTCIO_VALID_RTCIO_MASK + hex + default 0xFF + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index fb75998b07..ab1a4379b3 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -191,6 +191,8 @@ #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C6 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) +// LP IO peripherals have independent clock gating to manage +#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_GPIO_VALID_GPIO_MASK ((1U<