From 0cf11e5b873b9ff797a185a328d43181946fea2b Mon Sep 17 00:00:00 2001 From: wanlei Date: Tue, 20 Feb 2024 20:40:19 +0800 Subject: [PATCH] feat(spi): add esp32c5 spi support --- .../esp_driver_spi/src/gpspi/spi_common.c | 21 +- components/hal/esp32c5/include/hal/spi_ll.h | 1052 ++++++++--------- components/hal/esp32c6/include/hal/spi_ll.h | 10 +- components/idf_test/include/esp32c5/.gitkeep | 0 .../include/esp32c5/idf_performance_target.h | 6 + components/soc/esp32c2/spi_periph.c | 2 +- components/soc/esp32c3/spi_periph.c | 2 +- .../beta3/include/soc/Kconfig.soc_caps.in | 40 + .../esp32c5/beta3/include/soc/clk_tree_defs.h | 8 +- .../soc/esp32c5/beta3/include/soc/soc_caps.h | 22 +- .../soc/esp32c5/beta3/include/soc/spi_pins.h | 15 +- .../esp32c5/beta3/include/soc/spi_struct.h | 199 +--- components/soc/esp32c5/beta3/spi_periph.c | 64 + components/soc/esp32c6/spi_periph.c | 2 +- components/soc/esp32h2/spi_periph.c | 2 +- components/soc/esp32p4/spi_periph.c | 2 +- components/soc/esp32s2/spi_periph.c | 2 +- components/soc/esp32s3/spi_periph.c | 2 +- .../api-reference/peripherals/spi_master.rst | 20 +- .../api-reference/peripherals/spi_master.rst | 20 +- 20 files changed, 638 insertions(+), 853 deletions(-) delete mode 100644 components/idf_test/include/esp32c5/.gitkeep create mode 100644 components/soc/esp32c5/beta3/spi_periph.c diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index b10c9a9b8e..f78559f925 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,8 +15,9 @@ #include "esp_heap_caps.h" #include "soc/spi_periph.h" #include "soc/ext_mem_defs.h" -#include "driver/gpio.h" #include "driver/spi_master.h" +#include "driver/gpio.h" +#include "esp_private/gpio.h" #include "esp_private/periph_ctrl.h" #include "esp_private/spi_common_internal.h" #include "esp_private/spi_share_hw_ctrl.h" @@ -645,7 +646,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->mosi_io_num, FUNC_GPIO); } if (bus_config->miso_io_num >= 0) { if (miso_need_output || (temp_flag & SPICOMMON_BUSFLAG_DUAL)) { @@ -658,7 +659,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->miso_io_num, FUNC_GPIO); } if (bus_config->quadwp_io_num >= 0) { gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -667,7 +668,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->quadwp_io_num, FUNC_GPIO); } if (bus_config->quadhd_io_num >= 0) { gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -676,7 +677,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->quadhd_io_num, FUNC_GPIO); } if (bus_config->sclk_io_num >= 0) { if (sclk_need_output) { @@ -689,7 +690,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->sclk_io_num, FUNC_GPIO); } #if SOC_SPI_SUPPORT_OCT if ((flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL) { @@ -707,7 +708,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_nums[i]]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_nums[i]], FUNC_GPIO); + gpio_func_sel(io_nums[i], FUNC_GPIO); } } } @@ -755,8 +756,10 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, if (cs_num == 0) { esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false); } +#if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO); +#endif + gpio_func_sel(cs_io_num, FUNC_GPIO); } } diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index bb04567705..3187bc1144 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,11 @@ #include //for abs() #include -#include "esp_attr.h" #include "esp_types.h" #include "soc/spi_periph.h" #include "soc/spi_struct.h" #include "soc/lldesc.h" +#include "soc/clk_tree_defs.h" #include "hal/assert.h" #include "hal/misc.h" #include "hal/spi_types.h" @@ -42,6 +42,8 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized +#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral +#define SPI_LL_CLK_SRC_PRE_DIV_MAX 256//div1(8bit) /** * The data structure holding calculated clock configuration. Since the @@ -97,20 +99,15 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (host_id) - // { - // case SPI1_HOST: - // PCR.mspi_conf.mspi_clk_en = enable; - // break; - // case SPI2_HOST: - // PCR.spi2_conf.spi2_clk_en = enable; - // break; - // default: HAL_ASSERT(false); - // } - abort(); +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { + switch (host_id) + { + case SPI2_HOST: + PCR.spi2_conf.spi2_clk_en = enable; + break; + default: + HAL_ASSERT(false); + } } /** @@ -118,22 +115,16 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (host_id) - // { - // case SPI1_HOST: - // PCR.mspi_conf.mspi_rst_en = 1; - // PCR.mspi_conf.mspi_rst_en = 0; - // break; - // case SPI2_HOST: - // PCR.spi2_conf.spi2_rst_en = 1; - // PCR.spi2_conf.spi2_rst_en = 0; - // break; - // default: HAL_ASSERT(false); - // } - abort(); +static inline void spi_ll_reset_register(spi_host_device_t host_id) { + switch (host_id) + { + case SPI2_HOST: + PCR.spi2_conf.spi2_rst_en = 1; + PCR.spi2_conf.spi2_rst_en = 0; + break; + default: + HAL_ASSERT(false); + } } /** @@ -144,10 +135,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) */ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // (void) host_id; - // PCR.spi2_clkm_conf.spi2_clkm_en = enable; - abort(); + PCR.spi2_clkm_conf.spi2_clkm_en = enable; } /** @@ -159,20 +147,40 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) __attribute__((always_inline)) static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (clk_source) - // { - // case SPI_CLK_SRC_RC_FAST: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 2; - // break; - // case SPI_CLK_SRC_XTAL: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 0; - // break; - // default: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - // break; - // } - abort(); + uint32_t clk_id = 0; + switch (clk_source) { + case SOC_MOD_CLK_PLL_F160M: + clk_id = 1; + break; + case SOC_MOD_CLK_RC_FAST: + clk_id = 2; + break; + case SOC_MOD_CLK_XTAL: + clk_id = 0; + break; + default: + HAL_ASSERT(false); + } + + PCR.spi2_clkm_conf.spi2_clkm_sel = clk_id; +} + +/** + * Config clock source integrate pre_div before it enter GPSPI peripheral + * + * @note 1. For timing turning(e.g. input_delay) feature available, should be (mst_div >= 2) + * 2. From peripheral limitation: (sour_freq/hs_div <= 160M) and (sour_freq/hs_div/mst_div <= 80M) + * + * @param hw Beginning address of the peripheral registers. + * @param hs_div Timing turning clock divider: (hs_clk_o = sour_freq/hs_div) + * @param mst_div Functional output clock divider: (mst_clk_o = sour_freq/hs_div/mst_div) + */ +__attribute__((always_inline)) +static inline void spi_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div) +{ + // In IDF master driver 'mst_div' will be const 2 and 'hs_div' is actually pre_div temporally + (void) hs_div; + PCR.spi2_clkm_conf.spi2_clkm_div_num = mst_div - 1; } /** @@ -182,22 +190,22 @@ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_s */ static inline void spi_ll_master_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Reset timing - // hw->user1.cs_setup_time = 0; - // hw->user1.cs_hold_time = 0; - // // //use all 64 bytes of the buffer - // hw->user.usr_miso_highpart = 0; - // hw->user.usr_mosi_highpart = 0; - // // //Disable unneeded ints - // hw->slave.val = 0; - // hw->user.val = 0; - // // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - // // hw->dma_conf.val = 0; - // hw->dma_conf.slv_tx_seg_trans_clr_en = 1; - // hw->dma_conf.slv_rx_seg_trans_clr_en = 1; - // hw->dma_conf.dma_slv_seg_trans_en = 0; - abort(); + //Reset timing + hw->user1.cs_setup_time = 0; + hw->user1.cs_hold_time = 0; + + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + //Disable unneeded ints + hw->slave.val = 0; + hw->user.val = 0; + + hw->dma_conf.val = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -207,25 +215,25 @@ static inline void spi_ll_master_init(spi_dev_t *hw) */ static inline void spi_ll_slave_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Configure slave - // hw->clock.val = 0; - // hw->user.val = 0; - // hw->ctrl.val = 0; - // hw->user.doutdin = 1; //we only support full duplex - // hw->user.sio = 0; - // hw->slave.slave_mode = 1; - // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - // //use all 64 bytes of the buffer - // hw->user.usr_miso_highpart = 0; - // hw->user.usr_mosi_highpart = 0; - // // // Configure DMA In-Link to not be terminated when transaction bit counter exceeds - // hw->dma_conf.rx_eof_en = 0; - // hw->dma_conf.dma_slv_seg_trans_en = 0; - // // //Disable unneeded ints - // hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; - abort(); + //Configure slave + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 1; //we only support full duplex + hw->user.sio = 0; + hw->slave.slave_mode = 1; + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + // Configure DMA In-Link to not be terminated when transaction bit counter exceeds + hw->dma_conf.rx_eof_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; + + //Disable unneeded ints + hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; } /** @@ -235,41 +243,15 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) */ static inline void spi_ll_slave_hd_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->clock.val = 0; - // hw->user.val = 0; - // hw->ctrl.val = 0; - // hw->user.doutdin = 0; - // hw->user.sio = 0; - // // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - // hw->slave.slave_mode = 1; - abort(); -} + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 0; + hw->user.sio = 0; -/** - * Determine and unify the default level of mosi line when bus free - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state - abort(); -} - -/** - * Apply the register configurations and wait until it's done - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_apply_config(spi_dev_t *hw) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->cmd.update = 1; - // while (hw->cmd.update); //waiting config applied - abort(); + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + hw->slave.slave_mode = 1; } /** @@ -281,10 +263,18 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) */ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->dma_int_raw.trans_done; - abort(); - return (bool)0; + return hw->dma_int_raw.trans_done_int_raw; +} + +/** + * Apply the register configurations and wait until it's done + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_apply_config(spi_dev_t *hw) +{ + hw->cmd.update = 1; + while (hw->cmd.update); //waiting config applied } /** @@ -294,9 +284,7 @@ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) */ static inline void spi_ll_user_start(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->cmd.usr = 1; - abort(); + hw->cmd.usr = 1; } /** @@ -308,10 +296,7 @@ static inline void spi_ll_user_start(spi_dev_t *hw) */ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->cmd.val; - abort(); - return (uint32_t)0; + return hw->cmd.usr; } /** @@ -321,40 +306,34 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) */ static inline void spi_ll_slave_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - abort(); + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; } /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not seperated + * On esp32c5, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.buf_afifo_rst = 1; - // hw->dma_conf.buf_afifo_rst = 0; - abort(); + hw->dma_conf.buf_afifo_rst = 1; + hw->dma_conf.buf_afifo_rst = 0; } /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not seperated + * On esp32c5, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_afifo_rst = 1; - // hw->dma_conf.rx_afifo_rst = 0; - abort(); + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; } /** @@ -364,10 +343,8 @@ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_afifo_rst = 1; - // hw->dma_conf.dma_afifo_rst = 0; - abort(); + hw->dma_conf.dma_afifo_rst = 1; + hw->dma_conf.dma_afifo_rst = 0; } /** @@ -377,10 +354,8 @@ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_afifo_rst = 1; - // hw->dma_conf.rx_afifo_rst = 0; - abort(); + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; } /** @@ -390,9 +365,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.dma_infifo_full_err = 1; - abort(); + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; } /** @@ -402,9 +375,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.dma_outfifo_empty_err = 1; - abort(); + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; } /*------------------------------------------------------------------------------ @@ -418,9 +389,7 @@ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) */ static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_rx_ena = enable; - abort(); + hw->dma_conf.dma_rx_ena = enable; } /** @@ -431,9 +400,7 @@ static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) */ static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_tx_ena = enable; - abort(); + hw->dma_conf.dma_tx_ena = enable; } /** @@ -444,9 +411,7 @@ static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) */ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_eof_en = enable; - abort(); + hw->dma_conf.rx_eof_en = enable; } /*------------------------------------------------------------------------------ @@ -461,14 +426,12 @@ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) */ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // for (int x = 0; x < bitlen; x += 32) { - // //Use memcpy to get around alignment issues for txdata - // uint32_t word; - // memcpy(&word, &buffer_to_send[x / 8], 4); - // hw->data_buf[(x / 32)].buf = word; - // } - abort(); + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)].buf = word; + } } /** @@ -481,28 +444,29 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s */ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // HAL_ASSERT(byte_id + len <= 64); - // HAL_ASSERT(len > 0); - // HAL_ASSERT(byte_id >= 0); - // // while (len > 0) { - // uint32_t word; - // int offset = byte_id % 4; - // int copy_len = 4 - offset; - // if (copy_len > len) { - // copy_len = len; - // } - // // //read-modify-write - // if (copy_len != 4) { - // word = hw->data_buf[byte_id / 4].buf; //read - // } - // memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify - // hw->data_buf[byte_id / 4].buf = word; //write - // // data += copy_len; - // byte_id += copy_len; - // len -= copy_len; - // } - abort(); + HAL_ASSERT(byte_id + len <= 64); + HAL_ASSERT(len > 0); + HAL_ASSERT(byte_id >= 0); + + while (len > 0) { + uint32_t word; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + //read-modify-write + if (copy_len != 4) { + word = hw->data_buf[byte_id / 4].buf; //read + } + memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + hw->data_buf[byte_id / 4].buf = word; //write + + data += copy_len; + byte_id += copy_len; + len -= copy_len; + } } /** @@ -514,17 +478,15 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t */ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // for (int x = 0; x < bitlen; x += 32) { - // //Do a memcpy to get around possible alignment issues in rx_buffer - // uint32_t word = hw->data_buf[x / 32].buf; - // int len = bitlen - x; - // if (len > 32) { - // len = 32; - // } - // memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); - // } - abort(); + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32].buf; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } } /** @@ -537,20 +499,19 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz */ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // while (len > 0) { - // uint32_t word = hw->data_buf[byte_id / 4].buf; - // int offset = byte_id % 4; - // int copy_len = 4 - offset; - // if (copy_len > len) { - // copy_len = len; - // } - // // memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); - // byte_id += copy_len; - // out_data += copy_len; - // len -= copy_len; - // } - abort(); + while (len > 0) { + uint32_t word = hw->data_buf[byte_id / 4].buf; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + byte_id += copy_len; + out_data += copy_len; + len -= copy_len; + } } /*------------------------------------------------------------------------------ @@ -565,13 +526,11 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t * */ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (pos_cs) { - // hw->misc.master_cs_pol |= (1 << cs); - // } else { - // hw->misc.master_cs_pol &= ~(1 << cs); - // } - abort(); + if (pos_cs) { + hw->misc.master_cs_pol |= (1 << cs); + } else { + hw->misc.master_cs_pol &= ~(1 << cs); + } } /** @@ -582,9 +541,7 @@ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_ */ static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.wr_bit_order = lsbfirst; - abort(); + hw->ctrl.wr_bit_order = lsbfirst; } /** @@ -595,9 +552,7 @@ static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) */ static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.rd_bit_order = lsbfirst; - abort(); + hw->ctrl.rd_bit_order = lsbfirst; } /** @@ -608,22 +563,20 @@ static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) */ static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Configure polarity - // if (mode == 0) { - // hw->misc.ck_idle_edge = 0; - // hw->user.ck_out_edge = 0; - // } else if (mode == 1) { - // hw->misc.ck_idle_edge = 0; - // hw->user.ck_out_edge = 1; - // } else if (mode == 2) { - // hw->misc.ck_idle_edge = 1; - // hw->user.ck_out_edge = 1; - // } else if (mode == 3) { - // hw->misc.ck_idle_edge = 1; - // hw->user.ck_out_edge = 0; - // } - abort(); + //Configure polarity + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 1; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 0; + } } /** @@ -634,30 +587,28 @@ static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) */ static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (mode == 0) { - // hw->misc.ck_idle_edge = 0; - // hw->user.rsck_i_edge = 0; - // hw->user.tsck_i_edge = 0; - // hw->slave.clk_mode_13 = 0; - // } else if (mode == 1) { - // hw->misc.ck_idle_edge = 0; - // hw->user.rsck_i_edge = 1; - // hw->user.tsck_i_edge = 1; - // hw->slave.clk_mode_13 = 1; - // } else if (mode == 2) { - // hw->misc.ck_idle_edge = 1; - // hw->user.rsck_i_edge = 1; - // hw->user.tsck_i_edge = 1; - // hw->slave.clk_mode_13 = 0; - // } else if (mode == 3) { - // hw->misc.ck_idle_edge = 1; - // hw->user.rsck_i_edge = 0; - // hw->user.tsck_i_edge = 0; - // hw->slave.clk_mode_13 = 1; - // } - // hw->slave.rsck_data_out = 0; - abort(); + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 0; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 1; + } + hw->slave.rsck_data_out = 0; } /** @@ -668,9 +619,7 @@ static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma */ static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.doutdin = !half_duplex; - abort(); + hw->user.doutdin = !half_duplex; } /** @@ -683,9 +632,7 @@ static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) */ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.sio = sio_mode; - abort(); + hw->user.sio = sio_mode; } /** @@ -696,18 +643,16 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) */ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; - // hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; - // hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); - // hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); - // hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); - // hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); - // hw->ctrl.fread_dual = (line_mode.data_lines == 2); - // hw->user.fwrite_dual = (line_mode.data_lines == 2); - // hw->ctrl.fread_quad = (line_mode.data_lines == 4); - // hw->user.fwrite_quad = (line_mode.data_lines == 4); - abort(); + hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; + hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; + hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); + hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); + hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); + hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); + hw->ctrl.fread_dual = (line_mode.data_lines == 2); + hw->user.fwrite_dual = (line_mode.data_lines == 2); + hw->ctrl.fread_quad = (line_mode.data_lines == 4); + hw->user.fwrite_quad = (line_mode.data_lines == 4); } /** @@ -718,9 +663,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li */ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_slv_seg_trans_en = seg_trans; - abort(); + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -731,14 +674,12 @@ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) */ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; - // hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; - // hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; - // hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; - // hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; - // hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; - abort(); + hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; } /** @@ -749,9 +690,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) */ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; - abort(); + hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; } /*------------------------------------------------------------------------------ @@ -765,9 +704,7 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) */ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->clock.val = *(uint32_t *)val; - abort(); + hw->clock.val = *(uint32_t *)val; } /** @@ -781,10 +718,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl */ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return (fapb / (pre * n)); - abort(); - return (int)0; + return (fapb / (pre * n)); } /** @@ -799,66 +733,66 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) */ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // typeof(GPSPI2.clock) reg; - // int eff_clk; - // // //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. - // if (hz > ((fapb / 4) * 3)) { - // //Using Fapb directly will give us the best result here. - // reg.clkcnt_l = 0; - // reg.clkcnt_h = 0; - // reg.clkcnt_n = 0; - // reg.clkdiv_pre = 0; - // reg.clk_equ_sysclk = 1; - // eff_clk = fapb; - // } else { - // //For best duty cycle resolution, we want n to be as close to 32 as possible, but - // //we also need a pre/n combo that gets us as close as possible to the intended freq. - // //To do this, we bruteforce n and calculate the best pre to go along with that. - // //If there's a choice between pre/n combos that give the same result, use the one - // //with the higher n. - // int pre, n, h, l; - // int bestn = -1; - // int bestpre = -1; - // int besterr = 0; - // int errval; - // for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. - // //Effectively, this does pre=round((fapb/n)/hz). - // pre = ((fapb / n) + (hz / 2)) / hz; - // if (pre <= 0) { - // pre = 1; - // } - // if (pre > 16) { - // pre = 16; - // } - // errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); - // if (bestn == -1 || errval <= besterr) { - // besterr = errval; - // bestn = n; - // bestpre = pre; - // } - // } - // // n = bestn; - // pre = bestpre; - // l = n; - // //This effectively does round((duty_cycle*n)/256) - // h = (duty_cycle * n + 127) / 256; - // if (h <= 0) { - // h = 1; - // } - // // reg.clk_equ_sysclk = 0; - // reg.clkcnt_n = n - 1; - // reg.clkdiv_pre = pre - 1; - // reg.clkcnt_h = h - 1; - // reg.clkcnt_l = l - 1; - // eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); - // } - // if (out_reg != NULL) { - // *(uint32_t *)out_reg = reg.val; - // } - // return eff_clk; - abort(); - return (int)0; + typeof(GPSPI2.clock) reg; + int eff_clk; + + //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + if (hz > ((fapb / 4) * 3)) { + //Using Fapb directly will give us the best result here. + reg.clkcnt_l = 0; + reg.clkcnt_h = 0; + reg.clkcnt_n = 0; + reg.clkdiv_pre = 0; + reg.clk_equ_sysclk = 1; + eff_clk = fapb; + } else { + //For best duty cycle resolution, we want n to be as close to 32 as possible, but + //we also need a pre/n combo that gets us as close as possible to the intended freq. + //To do this, we bruteforce n and calculate the best pre to go along with that. + //If there's a choice between pre/n combos that give the same result, use the one + //with the higher n. + int pre, n, h, l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + //Effectively, this does pre=round((fapb/n)/hz). + pre = ((fapb / n) + (hz / 2)) / hz; + if (pre <= 0) { + pre = 1; + } + if (pre > 16) { + pre = 16; + } + errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + if (bestn == -1 || errval <= besterr) { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + //This effectively does round((duty_cycle*n)/256) + h = (duty_cycle * n + 127) / 256; + if (h <= 0) { + h = 1; + } + + reg.clk_equ_sysclk = 0; + reg.clkcnt_n = n - 1; + reg.clkdiv_pre = pre - 1; + reg.clkcnt_h = h - 1; + reg.clkcnt_l = l - 1; + eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + } + if (out_reg != NULL) { + *(uint32_t *)out_reg = reg.val; + } + return eff_clk; } /** @@ -878,13 +812,10 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ */ static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // spi_ll_clock_val_t reg_val; - // int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); - // spi_ll_master_set_clock_by_reg(hw, ®_val); - // return freq; - abort(); - return (int)0; + spi_ll_clock_val_t reg_val; + int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + spi_ll_master_set_clock_by_reg(hw, ®_val); + return freq; } /** @@ -898,8 +829,6 @@ static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int d */ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - abort(); } /** @@ -913,8 +842,6 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela */ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - abort(); } /** @@ -925,10 +852,8 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela */ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.cs_hold_time = hold; - // hw->user.cs_hold = hold ? 1 : 0; - abort(); + hw->user1.cs_hold_time = hold; + hw->user.cs_hold = hold ? 1 : 0; } /** @@ -942,10 +867,18 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) */ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.cs_setup_time = setup - 1; - // hw->user.cs_setup = setup ? 1 : 0; - abort(); + hw->user1.cs_setup_time = setup - 1; + hw->user.cs_setup = setup ? 1 : 0; +} + +/** + * Determine and unify the default level of mosi line when bus free + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) +{ + hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state } /*------------------------------------------------------------------------------ @@ -960,11 +893,9 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) */ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (bitlen > 0) { - // hw->ms_dlen.ms_data_bitlen = bitlen - 1; - // } - abort(); + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** @@ -975,11 +906,9 @@ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (bitlen > 0) { - // hw->ms_dlen.ms_data_bitlen = bitlen - 1; - // } - abort(); + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** @@ -990,9 +919,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //This is not used in esp32c3 - abort(); + //This is not used in esp32c5 } /** @@ -1003,9 +930,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //This is not used in esp32c3 - abort(); + //This is not used in esp32c5 } /** @@ -1019,10 +944,8 @@ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user2.usr_command_bitlen = bitlen - 1; - // hw->user.usr_command = bitlen ? 1 : 0; - abort(); + hw->user2.usr_command_bitlen = bitlen - 1; + hw->user.usr_command = bitlen ? 1 : 0; } /** @@ -1036,10 +959,8 @@ static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) */ static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.usr_addr_bitlen = bitlen - 1; - // hw->user.usr_addr = bitlen ? 1 : 0; - abort(); + hw->user1.usr_addr_bitlen = bitlen - 1; + hw->user.usr_addr = bitlen ? 1 : 0; } /** @@ -1054,23 +975,21 @@ static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) */ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (lsbfirst) { - // /* The output address start from the LSB of the highest byte, i.e. - // * addr[24] -> addr[31] - // * ... - // * addr[0] -> addr[7] - // * So swap the byte order to let the LSB sent first. - // */ - // addr = HAL_SWAP32(addr); - // //otherwise only addr register is sent - // hw->addr.val = addr; - // } else { - // // shift the address to MSB of addr register. - // // output address will be sent from MSB to LSB of addr register - // hw->addr.val = addr << (32 - addrlen); - // } - abort(); + if (lsbfirst) { + /* The output address start from the LSB of the highest byte, i.e. + * addr[24] -> addr[31] + * ... + * addr[0] -> addr[7] + * So swap the byte order to let the LSB sent first. + */ + addr = HAL_SWAP32(addr); + //otherwise only addr register is sent + hw->addr.val = addr; + } else { + // shift the address to MSB of addr register. + // output address will be sent from MSB to LSB of addr register + hw->addr.val = addr << (32 - addrlen); + } } /** @@ -1085,18 +1004,16 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (lsbfirst) { - // // The output command start from bit0 to bit 15, kept as is. - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); - // } else { - // /* Output command will be sent from bit 7 to 0 of command_value, and - // * then bit 15 to 8 of the same register field. Shift and swap to send - // * more straightly. - // */ - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); - // } - abort(); + if (lsbfirst) { + // The output command start from bit0 to bit 15, kept as is. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); + } else { + /* Output command will be sent from bit 7 to 0 of command_value, and + * then bit 15 to 8 of the same register field. Shift and swap to send + * more straightly. + */ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); + } } /** @@ -1110,10 +1027,8 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b */ static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_dummy = dummy_n ? 1 : 0; - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); - abort(); + hw->user.usr_dummy = dummy_n ? 1 : 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); } /** @@ -1124,9 +1039,7 @@ static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) */ static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_miso = enable; - abort(); + hw->user.usr_miso = enable; } /** @@ -1137,9 +1050,7 @@ static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) */ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_mosi = enable; - abort(); + hw->user.usr_mosi = enable; } /** @@ -1151,10 +1062,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_data_bitlen; - abort(); - return (uint32_t)0; + return hw->slave1.slv_data_bitlen; } /*------------------------------------------------------------------------------ @@ -1163,63 +1071,52 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done, dma_int_raw.slv_rd_buf_done, dma_int_clr.slv_rd_buf_done, dma_int_set.slv_rd_buf_done_int_set) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done, dma_int_raw.slv_wr_buf_done, dma_int_clr.slv_wr_buf_done, dma_int_set.slv_wr_buf_done_int_set) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done, dma_int_raw.slv_rd_dma_done, dma_int_clr.slv_rd_dma_done, dma_int_set.slv_rd_dma_done_int_set) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done, dma_int_raw.slv_wr_dma_done, dma_int_clr.slv_wr_dma_done, dma_int_set.slv_wr_dma_done_int_set) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7, dma_int_raw.slv_cmd7, dma_int_clr.slv_cmd7, dma_int_set.slv_cmd7_int_set) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8, dma_int_raw.slv_cmd8, dma_int_clr.slv_cmd8, dma_int_set.slv_cmd8_int_set) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9, dma_int_raw.slv_cmd9, dma_int_clr.slv_cmd9, dma_int_set.slv_cmd9_int_set) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda, dma_int_raw.slv_cmda, dma_int_clr.slv_cmda, dma_int_set.slv_cmda_int_set) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; - // FOR_EACH_ITEM(ENA_INTR, INTR_LIST); - // ef ENA_INTR - abort(); +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR } static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; - // FOR_EACH_ITEM(DIS_INTR, INTR_LIST); - // ef DIS_INTR - abort(); +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR } static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; - // FOR_EACH_ITEM(SET_INTR, INTR_LIST); - // ef SET_INTR - abort(); +#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR } static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; - // FOR_EACH_ITEM(CLR_INTR, INTR_LIST); - // ef CLR_INTR - abort(); +#define CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR } static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; - // FOR_EACH_ITEM(GET_INTR, INTR_LIST); - // return false; - // ef GET_INTR - abort(); - return (bool)0; +#define GET_INTR(intr_bit, _, sta_reg, ...) if (intr_mask & (intr_bit) && hw->sta_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR } #undef FOR_EACH_ITEM @@ -1232,9 +1129,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_ena.trans_done = 0; - abort(); + hw->dma_int_ena.trans_done_int_ena = 0; } /** @@ -1244,9 +1139,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.trans_done = 1; - abort(); + hw->dma_int_clr.trans_done_int_clr = 1; } /** @@ -1256,9 +1149,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) */ static inline void spi_ll_set_int_stat(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_set.trans_done_int_set = 1; - abort(); + hw->dma_int_set.trans_done_int_set = 1; } /** @@ -1268,9 +1159,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_ena.trans_done = 1; - abort(); + hw->dma_int_ena.trans_done_int_ena = 1; } /*------------------------------------------------------------------------------ @@ -1278,28 +1167,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - // hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - // hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - // hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; - abort(); + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_data_bitlen / 8; - abort(); - return (int)0; + return hw->slave1.slv_data_bitlen / 8; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_last_addr; - abort(); - return (uint32_t)0; + return hw->slave1.slv_last_addr; } #undef SPI_LL_RST_MASK @@ -1312,46 +1193,43 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // uint8_t cmd_base = 0x00; - // switch (cmd_t) - // { - // case SPI_CMD_HD_WRBUF: - // cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; - // break; - // case SPI_CMD_HD_RDBUF: - // cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; - // break; - // case SPI_CMD_HD_WRDMA: - // cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; - // break; - // case SPI_CMD_HD_RDDMA: - // cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; - // break; - // case SPI_CMD_HD_SEG_END: - // cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; - // break; - // case SPI_CMD_HD_EN_QPI: - // cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; - // break; - // case SPI_CMD_HD_WR_END: - // cmd_base = SPI_LL_BASE_CMD_HD_WR_END; - // break; - // case SPI_CMD_HD_INT0: - // cmd_base = SPI_LL_BASE_CMD_HD_INT0; - // break; - // case SPI_CMD_HD_INT1: - // cmd_base = SPI_LL_BASE_CMD_HD_INT1; - // break; - // case SPI_CMD_HD_INT2: - // cmd_base = SPI_LL_BASE_CMD_HD_INT2; - // break; - // default: - // HAL_ASSERT(cmd_base); - // } - // return cmd_base; - abort(); - return (uint8_t)0; + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; } /** @@ -1362,28 +1240,27 @@ static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) */ static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); - // uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit - // // if (line_mode.data_lines == 2) { - // if (line_mode.addr_lines == 2) { - // cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit - // } else { - // cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit - // } - // } else if (line_mode.data_lines == 4) { - // if (line_mode.addr_lines == 4) { - // cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit - // } else { - // cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit - // } - // } - // if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { - // cmd_mod = 0x00; - // } - // // return cmd_base | cmd_mod; - abort(); - return (uint16_t)0; + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; } /** @@ -1393,10 +1270,7 @@ static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line */ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return 8; - abort(); - return (int)0; + return 8; } #ifdef __cplusplus diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index b253d7e45d..05de203fc3 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -307,7 +307,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32C6, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ @@ -320,7 +320,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32C6, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ @@ -903,7 +903,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) { - //This is not used in esp32c3 + //This is not used in esp32c6 } /** @@ -914,7 +914,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) { - //This is not used in esp32c3 + //This is not used in esp32c6 } /** diff --git a/components/idf_test/include/esp32c5/.gitkeep b/components/idf_test/include/esp32c5/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/idf_test/include/esp32c5/idf_performance_target.h b/components/idf_test/include/esp32c5/idf_performance_target.h index dd3f635e54..c6a6eb8979 100644 --- a/components/idf_test/include/esp32c5/idf_performance_target.h +++ b/components/idf_test/include/esp32c5/idf_performance_target.h @@ -5,3 +5,9 @@ */ #pragma once + +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 27 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 16 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 24 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 13 diff --git a/components/soc/esp32c2/spi_periph.c b/components/soc/esp32c2/spi_periph.c index b2f7e416b2..5ae7aed529 100644 --- a/components/soc/esp32c2/spi_periph.c +++ b/components/soc/esp32c2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c index b2f7e416b2..5ae7aed529 100644 --- a/components/soc/esp32c3/spi_periph.c +++ b/components/soc/esp32c3/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index f8d4368a55..c74b0d8ce4 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -39,6 +39,10 @@ config SOC_RTC_MEM_SUPPORTED bool default y +config SOC_GPSPI_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -279,6 +283,42 @@ config SOC_SPI_MAX_CS_NUM int default 6 +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 256 + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h index d461f87967..325c0cc51b 100644 --- a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h @@ -359,16 +359,16 @@ typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6) /** * @brief Array initializer for all supported clock sources of SPI */ -#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} /** * @brief Type of SPI clock source. */ -typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) - SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ - SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ +typedef enum { SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */ SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */ } soc_periph_spi_clk_src_t; //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index df6b6db7a2..28b1b67bb7 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -41,7 +41,7 @@ // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 // #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 // #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 -// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 +#define SOC_GPSPI_SUPPORTED 1 // #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 @@ -379,23 +379,23 @@ #define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_MAX_CS_NUM 6 -// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -// #define SOC_SPI_SUPPORT_DDRCLK 1 -// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -// #define SOC_SPI_SUPPORT_CD_SIG 1 -// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -// #define SOC_SPI_SUPPORT_CLK_XTAL 1 -// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 +// #define SOC_SPI_SUPPORT_CLK_PLL_F160M 1 // #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) -// #define SOC_MEMSPI_IS_INDEPENDENT 1 -// #define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 256 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ // #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) diff --git a/components/soc/esp32c5/beta3/include/soc/spi_pins.h b/components/soc/esp32c5/beta3/include/soc/spi_pins.h index e50f1b1c43..918fc1ef66 100644 --- a/components/soc/esp32c5/beta3/include/soc/spi_pins.h +++ b/components/soc/esp32c5/beta3/include/soc/spi_pins.h @@ -1,25 +1,18 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// TODO: [ESP32C5] IDF-8698 (inherit from C6) - -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_CS 24 -#define SPI_IOMUX_PIN_NUM_CLK 29 -#define SPI_IOMUX_PIN_NUM_MOSI 30 -#define SPI_IOMUX_PIN_NUM_MISO 25 -#define SPI_IOMUX_PIN_NUM_WP 26 -#define SPI_IOMUX_PIN_NUM_HD 28 +// MSPI pin defined in io_mux_reg.h +// IOMUX pin for GPSPI2 #define SPI2_FUNC_NUM 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 #define SPI2_IOMUX_PIN_NUM_CLK 6 #define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 16 +#define SPI2_IOMUX_PIN_NUM_CS 12 diff --git a/components/soc/esp32c5/beta3/include/soc/spi_struct.h b/components/soc/esp32c5/beta3/include/soc/spi_struct.h index 6ff9c1e942..b9fdba155a 100644 --- a/components/soc/esp32c5/beta3/include/soc/spi_struct.h +++ b/components/soc/esp32c5/beta3/include/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1348,201 +1348,6 @@ typedef union { uint32_t val; } spi_wn_reg_t; -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - /** Group: Version register */ /** Type of date register @@ -1577,7 +1382,7 @@ typedef struct spi_dev_t { volatile spi_dma_int_ena_reg_t dma_int_ena; volatile spi_dma_int_clr_reg_t dma_int_clr; volatile spi_dma_int_raw_reg_t dma_int_raw; - volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_st_reg_t dma_int_sta; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; volatile spi_wn_reg_t data_buf[16]; diff --git a/components/soc/esp32c5/beta3/spi_periph.c b/components/soc/esp32c5/beta3/spi_periph.c new file mode 100644 index 0000000000..934cc24500 --- /dev/null +++ b/components/soc/esp32c5/beta3/spi_periph.c @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/spi_periph.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { + // MSPI on P4 has dedicated iomux pins + .spiclk_out = -1, + .spiclk_in = -1, + .spid_out = -1, + .spiq_out = -1, + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = -1, + .spiq_in = -1, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {-1}, + .spics_in = -1, + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = -1, + .irq_dma = -1, + .module = -1, + .hw = NULL, + .func = -1, + }, { + .spiclk_out = FSPICLK_OUT_MUX_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_GPSPI2_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_GPSPI2_MODULE, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM, + }, +}; diff --git a/components/soc/esp32c6/spi_periph.c b/components/soc/esp32c6/spi_periph.c index 4969841aec..ea10937f58 100644 --- a/components/soc/esp32c6/spi_periph.c +++ b/components/soc/esp32c6/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c index 8a9fe4d781..213bed6def 100644 --- a/components/soc/esp32h2/spi_periph.c +++ b/components/soc/esp32h2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c index 90f30522d9..5a629b6604 100644 --- a/components/soc/esp32p4/spi_periph.c +++ b/components/soc/esp32p4/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32s2/spi_periph.c b/components/soc/esp32s2/spi_periph.c index 0ba9613602..7bf01d0e32 100644 --- a/components/soc/esp32s2/spi_periph.c +++ b/components/soc/esp32s2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index a1098d035f..91fdc87355 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/docs/en/api-reference/peripherals/spi_master.rst b/docs/en/api-reference/peripherals/spi_master.rst index fadf01d781..8ce1b85d58 100644 --- a/docs/en/api-reference/peripherals/spi_master.rst +++ b/docs/en/api-reference/peripherals/spi_master.rst @@ -473,12 +473,12 @@ GPIO Matrix and IO_MUX .. only:: not esp32 - {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} - {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} - {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} - {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} - {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} - {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} + {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} + {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} + {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} + {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} + {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} + {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. @@ -524,10 +524,10 @@ The main parameter that determines the transfer speed for large transactions is Transaction Duration ^^^^^^^^^^^^^^^^^^^^ -{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} -{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} -{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} -{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} +{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} +{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} +{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} +{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions. diff --git a/docs/zh_CN/api-reference/peripherals/spi_master.rst b/docs/zh_CN/api-reference/peripherals/spi_master.rst index 7589032e36..656d3b7378 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_master.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_master.rst @@ -473,12 +473,12 @@ GPIO 矩阵与 IO_MUX 管脚 .. only:: not esp32 - {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} - {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} - {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} - {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} - {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} - {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} + {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} + {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} + {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} + {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} + {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} + {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} 芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。 @@ -524,10 +524,10 @@ GPIO 矩阵与 IO_MUX 管脚 传输事务持续时间 ^^^^^^^^^^^^^^^^^^^^ -{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} -{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} -{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} -{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} +{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} +{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} +{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} +{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。