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refactor(esp_psram): reformat code with astyle_py 2

pull/12486/head
Armando 2023-10-09 15:28:42 +08:00
rodzic fc4b9d9507
commit 0beb637563
14 zmienionych plików z 325 dodań i 353 usunięć
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59
components/esp_psram/device/esp_psram_impl_ap_hex.c
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@ -16,7 +16,6 @@
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define AP_HEX_PSRAM_SYNC_READ 0x0000
#define AP_HEX_PSRAM_SYNC_WRITE 0x8080
#define AP_HEX_PSRAM_BURST_READ 0x2020
@ -35,7 +34,6 @@
#define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4
#define AP_HEX_PSRAM_CS_HOLD_DELAY 3
typedef struct {
union {
struct {
@ -96,7 +94,6 @@ typedef struct {
static const char* TAG = "hex_psram";
static uint32_t s_psram_size; //this stands for physical psram size in bytes
/**
* Common psram transaction
*/
@ -192,55 +189,54 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
false);
//Read MR2~3 register
s_psram_common_transaction(spi_num,
AP_HEX_PSRAM_REG_READ, cmd_len,
0x2, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr2.val, data_bit_len,
false);
AP_HEX_PSRAM_REG_READ, cmd_len,
0x2, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr2.val, data_bit_len,
false);
data_bit_len = 8;
//Read MR4 register
s_psram_common_transaction(spi_num,
AP_HEX_PSRAM_REG_READ, cmd_len,
0x4, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr4.val, data_bit_len,
false);
AP_HEX_PSRAM_REG_READ, cmd_len,
0x4, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr4.val, data_bit_len,
false);
//Read MR8 register
s_psram_common_transaction(spi_num,
AP_HEX_PSRAM_REG_READ, cmd_len,
0x8, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr8.val, data_bit_len,
false);
AP_HEX_PSRAM_REG_READ, cmd_len,
0x8, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr8.val, data_bit_len,
false);
}
static void s_print_psram_info(hex_psram_mode_reg_t *reg_val)
{
ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN");
ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
ESP_EARLY_LOGI(TAG, "DriveStr. : 0x%02x (%d Ohm)", reg_val->mr0.drive_str, reg_val->mr0.drive_str < 2 ? 25*(reg_val->mr0.drive_str + 1): 100*(reg_val->mr0.drive_str-1));
ESP_EARLY_LOGI(TAG, "DriveStr. : 0x%02x (%d Ohm)", reg_val->mr0.drive_str, reg_val->mr0.drive_str < 2 ? 25 * (reg_val->mr0.drive_str + 1) : 100 * (reg_val->mr0.drive_str - 1));
ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id + 1);
ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == 0x1 ? 32 :
reg_val->mr2.density == 0X3 ? 64 :
reg_val->mr2.density == 0x5 ? 128 :
reg_val->mr2.density == 0x7 ? 256 : 0);
reg_val->mr2.density == 0X3 ? 64 :
reg_val->mr2.density == 0x5 ? 128 :
reg_val->mr2.density == 0x7 ? 256 : 0);
ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.kgd, reg_val->mr2.kgd == 6 ? "Pass" : "Fail");
ESP_EARLY_LOGI(TAG, "SRF : 0x%02x (%s Refresh)", reg_val->mr3.srf, reg_val->mr3.srf == 0x1 ? "Fast" : "Slow");
ESP_EARLY_LOGI(TAG, "BurstType : 0x%02x (%s Wrap)", reg_val->mr8.bt, reg_val->mr8.bt == 1 && reg_val->mr8.bl != 3 ? "Hybrid" : "");
ESP_EARLY_LOGI(TAG, "BurstLen : 0x%02x (%d Byte)", reg_val->mr8.bl, reg_val->mr8.bl == 0x00 ? 16 :
reg_val->mr8.bl == 0x01 ? 32 :
reg_val->mr8.bl == 0x10 ? 64 : 2048);
reg_val->mr8.bl == 0x01 ? 32 :
reg_val->mr8.bl == 0x10 ? 64 : 2048);
ESP_EARLY_LOGI(TAG, "BitMode : 0x%02x (%s Mode)", reg_val->mr8.x16, reg_val->mr8.x16 == 1 ? "X16" : "X8");
ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6,
reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 :
reg_val->mr0.drive_str == 0x01 ? 2 :
reg_val->mr0.drive_str == 0x02 ? 4 : 8);
reg_val->mr0.drive_str == 0x01 ? 2 :
reg_val->mr0.drive_str == 0x02 ? 4 : 8);
}
static void s_config_mspi_for_psram(void)
@ -326,7 +322,6 @@ static void s_configure_psram_ecc(void)
}
#endif //#if CONFIG_SPIRAM_ECC_ENABLE
esp_err_t esp_psram_impl_enable(void)
{
PSRAM_RCC_ATOMIC() {

32
components/esp_psram/esp32/esp_himem.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -104,9 +104,9 @@ static inline int rangeblock_idx_valid(int rangeblock_idx)
static void set_bank(int virt_bank, int phys_bank, int ct)
{
int r __attribute__((unused));
r = cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct );
r = cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct);
assert(r == 0);
r = cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct );
r = cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct);
assert(r == 0);
}
@ -120,28 +120,32 @@ size_t esp_himem_get_phys_size(void)
size_t esp_himem_get_free_size(void)
{
size_t ret=0;
size_t ret = 0;
for (int i = 0; i < s_ramblockcnt; i++) {
if (!s_ram_descriptor[i].is_alloced) ret+=CACHE_BLOCKSIZE;
if (!s_ram_descriptor[i].is_alloced) {
ret += CACHE_BLOCKSIZE;
}
}
return ret;
}
size_t esp_himem_reserved_area_size(void) {
size_t esp_himem_reserved_area_size(void)
{
return CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE;
}
void __attribute__((constructor)) esp_himem_init(void)
{
if (SPIRAM_BANKSWITCH_RESERVE == 0) return;
if (SPIRAM_BANKSWITCH_RESERVE == 0) {
return;
}
uint32_t maxram = 0;
esp_psram_impl_get_available_size(&maxram);
//catch double init
ESP_RETURN_ON_FALSE(s_ram_descriptor == NULL, , TAG, "already initialized"); //Looks weird; last arg is empty so it expands to 'return ;'
ESP_RETURN_ON_FALSE(s_range_descriptor == NULL, , TAG, "already initialized");
ESP_RETURN_ON_FALSE(s_ram_descriptor == NULL,, TAG, "already initialized"); //Looks weird; last arg is empty so it expands to 'return ;'
ESP_RETURN_ON_FALSE(s_range_descriptor == NULL,, TAG, "already initialized");
//need to have some reserved banks
ESP_RETURN_ON_FALSE(SPIRAM_BANKSWITCH_RESERVE != 0, , TAG, "No banks reserved for himem");
ESP_RETURN_ON_FALSE(SPIRAM_BANKSWITCH_RESERVE != 0,, TAG, "No banks reserved for himem");
//Start and end of physical reserved memory. Note it starts slightly under
//the 4MiB mark as the reserved banks can't have an unity mapping to be used by malloc
//anymore; we treat them as himem instead.
@ -158,10 +162,9 @@ void __attribute__((constructor)) esp_himem_init(void)
return;
}
ESP_EARLY_LOGI(TAG, "Initialized. Using last %d 32KB address blocks for bank switching on %d KB of physical memory.",
SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start)/1024);
SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start) / 1024);
}
//Allocate count not-necessarily consecutive physical RAM blocks, return numbers in blocks[]. Return
//true if blocks can be allocated, false if not.
static bool allocate_blocks(int count, uint16_t *blocks_out)
@ -186,7 +189,6 @@ static bool allocate_blocks(int count, uint16_t *blocks_out)
}
}
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out)
{
if (size % CACHE_BLOCKSIZE != 0) {
@ -238,7 +240,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle)
return ESP_OK;
}
esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out)
{
ESP_RETURN_ON_FALSE(s_ram_descriptor != NULL, ESP_ERR_INVALID_STATE, TAG, "Himem not available!");
@ -296,7 +297,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle)
return ESP_OK;
}
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr)
{
int ram_block = ram_offset / CACHE_BLOCKSIZE;

35
components/esp_psram/esp32/esp_psram_extram_cache.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,7 +15,6 @@
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
#endif
/*
Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
@ -25,21 +24,23 @@
void IRAM_ATTR esp_psram_extram_writeback_cache(void)
{
int x;
volatile int i=0;
volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
int cache_was_disabled=0;
volatile int i = 0;
volatile uint8_t *psram = (volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
int cache_was_disabled = 0;
if (!esp_psram_is_initialized()) return;
if (!esp_psram_is_initialized()) {
return;
}
//We need cache enabled for this to work. Re-enable it if needed; make sure we
//disable it again on exit as well.
if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) {
cache_was_disabled|=(1<<0);
if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) == 0) {
cache_was_disabled |= (1 << 0);
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
}
#ifndef CONFIG_FREERTOS_UNICORE
if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
cache_was_disabled|=(1<<1);
if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) {
cache_was_disabled |= (1 << 1);
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
}
#endif
@ -49,8 +50,8 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
Single-core and even/odd mode only have 32K of cache evenly distributed over the address lines. We can clear
the cache by just reading 64K worth of cache lines.
*/
for (x=0; x<1024*64; x+=32) {
i+=psram[x];
for (x = 0; x < 1024 * 64; x += 32) {
i += psram[x];
}
#else
/*
@ -59,18 +60,18 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If
we ever support external RAM chips of 2M or smaller, this may need adjusting.
*/
for (x=0; x<1024*64; x+=32) {
i+=psram[x];
i+=psram[x+(1024*1024*2)];
for (x = 0; x < 1024 * 64; x += 32) {
i += psram[x];
i += psram[x + (1024 * 1024 * 2)];
}
#endif
if (cache_was_disabled&(1<<0)) {
if (cache_was_disabled & (1 << 0)) {
while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
}
#ifndef CONFIG_FREERTOS_UNICORE
if (cache_was_disabled&(1<<1)) {
if (cache_was_disabled & (1 << 1)) {
while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
}

11
components/esp_psram/esp32/esp_psram_impl_quad.c
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@ -8,7 +8,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -291,10 +290,9 @@ static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
}
//start sending cmd/addr and optionally, receiving data
static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t *pRxData, uint16_t rxByteLen,
psram_cmd_mode_t cmd_mode)
psram_cmd_mode_t cmd_mode)
{
//get cs1
CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
@ -311,7 +309,7 @@ static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t *pR
}
//Wait for SPI0 to idle
while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
while (READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
// Start send data
@ -838,7 +836,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_
BIT64(psram_io->psram_spiq_sd0_io) |
BIT64(psram_io->psram_spid_sd1_io) |
BIT64(psram_io->psram_spihd_sd2_io) |
BIT64(psram_io->psram_spiwp_sd3_io) );
BIT64(psram_io->psram_spiwp_sd3_io));
}
//used in UT only
@ -871,7 +869,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
abort();
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
ESP_EARLY_LOGI(TAG, "This chip is %s",
(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)? "ESP32-PICO": "ESP32-U4WDH");
(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) ? "ESP32-PICO" : "ESP32-U4WDH");
// We have better alternatives, though it's possible to use U4WDH together with PSRAM.
// U4WDH shares the same pin config with PICO for historical reasons.
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
@ -1148,7 +1146,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
{
if (!out_size_bytes) {

207
components/esp_psram/esp32s2/esp_psram_impl_quad.c
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@ -8,7 +8,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -105,7 +104,6 @@ typedef enum {
PSRAM_CLK_MODE_MAX,
} psram_clk_mode_t;
typedef enum {
PSRAM_EID_SIZE_16MBITS = 0,
PSRAM_EID_SIZE_32MBITS = 1,
@ -138,7 +136,7 @@ typedef enum {
PSRAM_SPI_1 = 0x1,
/* PSRAM_SPI_2, */
/* PSRAM_SPI_3, */
PSRAM_SPI_MAX ,
PSRAM_SPI_MAX,
} psram_spi_num_t;
typedef enum {
@ -168,7 +166,7 @@ static uint32_t s_psram_id = 0;
static void psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
static uint8_t s_psram_cs_io = (uint8_t)-1;
static uint8_t s_psram_cs_io = (uint8_t) -1;
uint8_t esp_psram_impl_get_cs_io(void)
{
@ -185,11 +183,11 @@ static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
}
}
static void _psram_exec_cmd(int spi_num,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len)
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len)
{
esp_rom_spi_cmd_t conf;
uint32_t _addr = addr;
@ -206,13 +204,13 @@ static void _psram_exec_cmd(int spi_num,
}
void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation)
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation)
{
uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
@ -220,7 +218,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
psram_set_op_mode(spi_num, mode);
_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
@ -233,13 +231,13 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
static void psram_disable_qio_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//switch psram burst length(32 bytes or 1024 bytes)
@ -247,35 +245,35 @@ static void psram_disable_qio_mode(int spi_num)
static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
{
psram_exec_cmd(spi_num, mode,
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//send reset command to psram, in spi mode
static void psram_reset_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_RESET_EN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_RESET_EN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_RESET, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_RESET, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
esp_err_t psram_enable_wrap(uint32_t wrap_size)
@ -285,28 +283,28 @@ esp_err_t psram_enable_wrap(uint32_t wrap_size)
return ESP_OK;
}
switch (wrap_size) {
case 32:
case 0:
psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI);
current_wrap_size = wrap_size;
return ESP_OK;
case 16:
case 64:
default:
return ESP_FAIL;
case 32:
case 0:
psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI);
current_wrap_size = wrap_size;
return ESP_OK;
case 16:
case 64:
default:
return ESP_FAIL;
}
}
bool psram_support_wrap_size(uint32_t wrap_size)
{
switch (wrap_size) {
case 0:
case 32:
return true;
case 16:
case 64:
default:
return false;
case 0:
case 32:
return true;
case 16:
case 64:
default:
return false;
}
}
@ -315,26 +313,26 @@ bool psram_support_wrap_size(uint32_t wrap_size)
static void psram_read_id(int spi_num, uint32_t* dev_id)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//enter QPI mode
static void IRAM_ATTR psram_enable_qio_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode)
@ -392,7 +390,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_speed_t mode)
BIT64(psram_io.psram_spiq_sd0_io) |
BIT64(psram_io.psram_spid_sd1_io) |
BIT64(psram_io.psram_spihd_sd2_io) |
BIT64(psram_io.psram_spiwp_sd3_io) );
BIT64(psram_io.psram_spiwp_sd3_io));
}
//used in UT only
@ -456,7 +454,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
/* SPI1: send psram reset command */
/* SPI1: send QPI enable command */
psram_reset_mode(PSRAM_SPI_1);
psram_reset_mode(PSRAM_SPI_1);
psram_enable_qio_mode(PSRAM_SPI_1);
// after sending commands, set spi1 clock mode and cs timing to normal mode.
@ -483,7 +481,7 @@ static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv)
if (1 >= freqdiv) {
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
} else {
freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
freqbits = (((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
}
}
@ -493,25 +491,25 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
{
int extra_dummy = 0;
switch (psram_cache_mode) {
case PSRAM_CACHE_S80M:
psram_clock_set(0, 1);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
break;
case PSRAM_CACHE_S40M:
psram_clock_set(0, 2);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
break;
case PSRAM_CACHE_S26M:
psram_clock_set(0, 3);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
break;
case PSRAM_CACHE_S20M:
psram_clock_set(0, 4);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
break;
default:
psram_clock_set(0, 2);
break;
case PSRAM_CACHE_S80M:
psram_clock_set(0, 1);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
break;
case PSRAM_CACHE_S40M:
psram_clock_set(0, 2);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
break;
case PSRAM_CACHE_S26M:
psram_clock_set(0, 3);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
break;
case PSRAM_CACHE_S20M:
psram_clock_set(0, 4);
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
break;
default:
psram_clock_set(0, 2);
break;
}
CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
@ -523,19 +521,19 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
//config sram cache r/w command
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
#if !CONFIG_FREERTOS_UNICORE
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT);
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT);
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
@ -548,7 +546,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

132
components/esp_psram/esp32s3/esp_psram_impl_octal.c
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -43,7 +43,6 @@
#define OCT_PSRAM_PAGE_SIZE 2 //2 for 1024B
#define OCT_PSRAM_ECC_ENABLE_MASK BIT(8)
typedef struct {
union {
struct {
@ -122,13 +121,13 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
//read
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
addr, addr_bit_len,
dummy,
NULL, 0,
&mode_reg.mr0.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
addr, addr_bit_len,
dummy,
NULL, 0,
&mode_reg.mr0.val, data_bit_len,
BIT(1),
false);
//modify
mode_reg.mr0.lt = mode_reg_config->mr0.lt;
@ -137,26 +136,26 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
//write
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_WRITE, cmd_len,
addr, addr_bit_len,
0,
&mode_reg.mr0.val, 16,
NULL, 0,
BIT(1),
false);
OPI_PSRAM_REG_WRITE, cmd_len,
addr, addr_bit_len,
0,
&mode_reg.mr0.val, 16,
NULL, 0,
BIT(1),
false);
#if CONFIG_SPIRAM_ECC_ENABLE
addr = 0x8; //0x8 is the MR8 register
data_bit_len = 8;
//read
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
addr, addr_bit_len,
dummy,
NULL, 0,
&mode_reg.mr8.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
addr, addr_bit_len,
dummy,
NULL, 0,
&mode_reg.mr8.val, data_bit_len,
BIT(1),
false);
//modify
mode_reg.mr8.bt = mode_reg_config->mr8.bt;
@ -164,13 +163,13 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
//write
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_WRITE, cmd_len,
addr, addr_bit_len,
0,
&mode_reg.mr8.val, 16,
NULL, 0,
BIT(1),
false);
OPI_PSRAM_REG_WRITE, cmd_len,
addr, addr_bit_len,
0,
&mode_reg.mr8.val, 16,
NULL, 0,
BIT(1),
false);
#endif
}
@ -184,41 +183,41 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
//Read MR0~1 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x0, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr0.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
0x0, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr0.val, data_bit_len,
BIT(1),
false);
//Read MR2~3 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x2, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr2.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
0x2, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr2.val, data_bit_len,
BIT(1),
false);
data_bit_len = 8;
//Read MR4 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x4, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr4.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
0x4, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr4.val, data_bit_len,
BIT(1),
false);
//Read MR8 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x8, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr8.val, data_bit_len,
BIT(1),
false);
OPI_PSRAM_REG_READ, cmd_len,
0x8, addr_bit_len,
dummy,
NULL, 0,
&out_reg->mr8.val, data_bit_len,
BIT(1),
false);
}
static void s_print_psram_info(opi_psram_mode_reg_t *reg_val)
@ -226,22 +225,22 @@ static void s_print_psram_info(opi_psram_mode_reg_t *reg_val)
ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN");
ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id + 1);
ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == 0x1 ? 32 :
reg_val->mr2.density == 0X3 ? 64 :
reg_val->mr2.density == 0x5 ? 128 :
reg_val->mr2.density == 0x7 ? 256 : 0);
reg_val->mr2.density == 0X3 ? 64 :
reg_val->mr2.density == 0x5 ? 128 :
reg_val->mr2.density == 0x7 ? 256 : 0);
ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.gb, reg_val->mr2.gb == 1 ? "Pass" : "Fail");
ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
ESP_EARLY_LOGI(TAG, "VCC : 0x%02x (%s)", reg_val->mr3.vcc, reg_val->mr3.vcc == 1 ? "3V" : "1.8V");
ESP_EARLY_LOGI(TAG, "SRF : 0x%02x (%s Refresh)", reg_val->mr3.srf, reg_val->mr3.srf == 0x1 ? "Fast" : "Slow");
ESP_EARLY_LOGI(TAG, "BurstType : 0x%02x (%s Wrap)", reg_val->mr8.bt, reg_val->mr8.bt == 1 && reg_val->mr8.bl != 3 ? "Hybrid" : "");
ESP_EARLY_LOGI(TAG, "BurstLen : 0x%02x (%d Byte)", reg_val->mr8.bl, reg_val->mr8.bl == 0x00 ? 16 :
reg_val->mr8.bl == 0x01 ? 32 :
reg_val->mr8.bl == 0x10 ? 64 : 1024);
reg_val->mr8.bl == 0x01 ? 32 :
reg_val->mr8.bl == 0x10 ? 64 : 1024);
ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6,
reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 :
reg_val->mr0.drive_str == 0x01 ? 2 :
reg_val->mr0.drive_str == 0x02 ? 4 : 8);
reg_val->mr0.drive_str == 0x01 ? 2 :
reg_val->mr0.drive_str == 0x02 ? 4 : 8);
}
static void s_set_psram_cs_timing(void)
@ -377,7 +376,6 @@ static void s_config_psram_spi_phases(void)
Cache_Resume_DCache(0);
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

148
components/esp_psram/esp32s3/esp_psram_impl_quad.c
Wyświetl plik

@ -1,10 +1,9 @@
/*
* SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2013-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -96,7 +95,7 @@ static uint32_t s_psram_size = 0; //this stands for physical psram size in byt
static void config_psram_spi_phases(void);
extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
static uint8_t s_psram_cs_io = (uint8_t)-1;
static uint8_t s_psram_cs_io = (uint8_t) -1;
uint8_t esp_psram_impl_get_cs_io(void)
{
@ -113,11 +112,11 @@ static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
}
}
static void _psram_exec_cmd(int spi_num,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len)
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len)
{
esp_rom_spi_cmd_t conf;
uint32_t _addr = addr;
@ -134,13 +133,13 @@ static void _psram_exec_cmd(int spi_num,
}
void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation)
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation)
{
uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
@ -148,7 +147,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
psram_set_op_mode(spi_num, mode);
_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
@ -161,13 +160,13 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
static void psram_disable_qio_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//TODO IDF-4307
@ -176,35 +175,35 @@ static void psram_disable_qio_mode(int spi_num)
static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
{
psram_exec_cmd(spi_num, mode,
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//send reset command to psram, in spi mode
static void psram_reset_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_RESET_EN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_RESET_EN, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_RESET, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_RESET, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
esp_err_t psram_enable_wrap(uint32_t wrap_size)
@ -215,28 +214,28 @@ esp_err_t psram_enable_wrap(uint32_t wrap_size)
return ESP_OK;
}
switch (wrap_size) {
case 32:
case 0:
psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
current_wrap_size = wrap_size;
return ESP_OK;
case 16:
case 64:
default:
return ESP_FAIL;
case 32:
case 0:
psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
current_wrap_size = wrap_size;
return ESP_OK;
case 16:
case 64:
default:
return ESP_FAIL;
}
}
bool psram_support_wrap_size(uint32_t wrap_size)
{
switch (wrap_size) {
case 0:
case 32:
return true;
case 16:
case 64:
default:
return false;
case 0:
case 32:
return true;
case 16:
case 64:
default:
return false;
}
}
@ -245,26 +244,26 @@ bool psram_support_wrap_size(uint32_t wrap_size)
static void psram_read_id(int spi_num, uint32_t* dev_id)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
//enter QPI mode
static void psram_enable_qio_mode(int spi_num)
{
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
0, 0, /* address and address bit len*/
0, /* dummy bit len */
NULL, 0, /* tx data and tx bit len*/
NULL, 0, /* rx data and rx bit len*/
CS_PSRAM_SEL, /* cs bit mask*/
false); /* whether is program/erase operation */
}
static void psram_set_cs_timing(void)
@ -378,7 +377,6 @@ static void config_psram_spi_phases(void)
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

10
components/esp_psram/include/esp32/himem.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,7 +40,6 @@ typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t;
*/
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out);
/**
* @brief Allocate a memory region to map blocks into
*
@ -79,7 +78,6 @@ esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle
*/
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr);
/**
* @brief Free a block of physical memory
*
@ -92,8 +90,6 @@ esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range
*/
esp_err_t esp_himem_free(esp_himem_handle_t handle);
/**
* @brief Free a mapping range
*
@ -106,7 +102,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle);
*/
esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
/**
* @brief Unmap a region
*
@ -118,7 +113,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
*/
esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
/**
* @brief Get total amount of memory under control of himem API
*
@ -133,7 +127,6 @@ size_t esp_himem_get_phys_size(void);
*/
size_t esp_himem_get_free_size(void);
/**
* @brief Get amount of SPI memory address space needed for bankswitching
*
@ -144,7 +137,6 @@ size_t esp_himem_get_free_size(void);
*/
size_t esp_himem_reserved_area_size(void);
#ifdef __cplusplus
}
#endif

2
components/esp_psram/include/esp_private/esp_psram_io.h
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@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* @brief get psram CS IO
*
@ -25,7 +24,6 @@ extern "C" {
*/
uint8_t esp_psram_io_get_cs_io(void);
#ifdef __cplusplus
}
#endif

2
components/esp_psram/include/esp_private/mmu_psram_flash.h
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@ -60,7 +60,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page);
#endif //#if CONFIG_SPIRAM_RODATA
/*----------------------------------------------------------------------------
Part 2 APIs (See @Backgrounds on top of this file)
-------------------------------------------------------------------------------*/
@ -132,7 +131,6 @@ uint32_t rodata_flash_end_page_get(void);
int rodata_flash2spiram_offset(void);
#endif // #if CONFIG_SPIRAM_RODATA
#ifdef __cplusplus
}
#endif

1
components/esp_psram/include/esp_psram.h
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@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stddef.h>

30
components/esp_psram/test_apps/psram/main/test_4mpsram.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,20 +20,22 @@ static void test_psram_content(void)
uint32_t *test_area = heap_caps_malloc(test_size, MALLOC_CAP_SPIRAM);
size_t p;
size_t s=test_size;
int errct=0;
int initial_err=-1;
for (p=0; p<(s/sizeof(int)); p+=4) {
test_area[p]=p^0xAAAAAAAA;
size_t s = test_size;
int errct = 0;
int initial_err = -1;
for (p = 0; p < (s / sizeof(int)); p += 4) {
test_area[p] = p ^ 0xAAAAAAAA;
}
for (p=0; p<(s/sizeof(int)); p+=4) {
if (test_area[p]!=(p^0xAAAAAAAA)) {
for (p = 0; p < (s / sizeof(int)); p += 4) {
if (test_area[p] != (p ^ 0xAAAAAAAA)) {
errct++;
if (errct==1) initial_err=p*4;
if (errct == 1) {
initial_err = p * 4;
}
}
}
if (errct) {
ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p", errct, s/32, initial_err+test_area);
ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p", errct, s / 32, initial_err + test_area);
TEST_FAIL();
} else {
ESP_LOGI(TAG, "SPI SRAM memory test OK");
@ -48,10 +50,14 @@ bool psram_is_32mbit_ver0(void);
static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host)
{
bool claim_hspi = spicommon_periph_claim(HSPI_HOST, "ut-hspi");
if (claim_hspi) ESP_LOGI(TAG, "HSPI claimed.");
if (claim_hspi) {
ESP_LOGI(TAG, "HSPI claimed.");
}
bool claim_vspi = spicommon_periph_claim(VSPI_HOST, "ut-vspi");
if (claim_vspi) ESP_LOGI(TAG, "VSPI claimed.");
if (claim_vspi) {
ESP_LOGI(TAG, "VSPI claimed.");
}
if (expected_occupied_host == HSPI_HOST) {
TEST_ASSERT_FALSE(claim_hspi);

3
components/esp_psram/test_apps/psram/main/test_himem.c
Wyświetl plik

@ -75,7 +75,6 @@ static bool test_region(int check_size, int seed)
return ret;
}
static volatile int testsDone;
static void memtest_thread(void *arg)
@ -90,7 +89,6 @@ static void memtest_thread(void *arg)
vTaskDelete(NULL);
}
TEST_CASE("high psram memory test", "[himem]")
{
printf("Doing single-core test\n");
@ -108,7 +106,6 @@ TEST_CASE("high psram memory test", "[himem]")
vTaskDelay(100);
}
#endif
#endif // CONFIG_IDF_TARGET_ESP32

6
components/esp_psram/test_apps/psram/main/test_psram.c
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@ -22,8 +22,7 @@
__attribute__((unused)) const static char *TAG = "PSRAM";
TEST_CASE("test psram heap allocable","[psram]")
TEST_CASE("test psram heap allocable", "[psram]")
{
size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
ESP_LOGI(TAG, "largest size is %zu", largest_size);
@ -47,7 +46,6 @@ TEST_CASE("test psram heap allocable","[psram]")
free(ext_buffer);
}
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
#include "esp_partition.h"
#include "driver/gptimer.h"
@ -132,7 +130,6 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram"
}
#endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
TEST_CASE("test psram unaligned access", "[psram]")
{
size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
@ -174,7 +171,6 @@ TEST_CASE("test psram unaligned access", "[psram]")
uint32_t val_32bit = *(uint32_t *)unaligned_ptr;
ESP_LOGV(TAG, "i is %d, j is %d, val_32bit val is 0x%"PRIx32, i, j, val_32bit);
uint8_t second_byte = ((i + j) & 0xff) + 1;
uint8_t third_byte = ((i + j) & 0xff) + 2;
uint8_t fourth_byte = ((i + j) & 0xff) + 3;