kopia lustrzana https://github.com/espressif/esp-idf
esp_flash: enable unit tests for ESP32-S2 external flash
Michael (XIAO Xufeng)
rodzic
30fa716376
commit
0a65911df2
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@ -30,9 +30,10 @@ static uint8_t sector_buf[4096];
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#define TEST_SPI_READ_MODE SPI_FLASH_FASTRD
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// #define FORCE_GPIO_MATRIX
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#define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk
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#if CONFIG_IDF_TARGET_ESP32
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#define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk
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#define SPI1_CS_IO 16 //the pin which is usually used by the PSRAM cs
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#define HSPI_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
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#define HSPI_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
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#define HSPI_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
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@ -46,28 +47,26 @@ static uint8_t sector_buf[4096];
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#define VSPI_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
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#define VSPI_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
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#define VSPI_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define FSPI_PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
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#define FSPI_PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
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#define FSPI_PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
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#define FSPI_PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
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#define FSPI_PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
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#define FSPI_PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
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// Just use the same pins for HSPI and VSPI
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs
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#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd
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#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp
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#define FSPI_PIN_NUM_MOSI 35
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#define FSPI_PIN_NUM_MISO 37
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#define FSPI_PIN_NUM_CLK 36
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#define FSPI_PIN_NUM_HD 33
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#define FSPI_PIN_NUM_WP 38
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#define FSPI_PIN_NUM_CS 34
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// Just use the same pins for HSPI
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#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
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#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
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#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
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#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
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#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
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#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
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#define VSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
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#define VSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
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#define VSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
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#define VSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
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#define VSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
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#define VSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
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#endif
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#define TEST_CONFIG_NUM (sizeof(config_list)/sizeof(flashtest_config_t))
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@ -87,11 +86,10 @@ typedef void (*flash_test_func_t)(esp_flash_t* chip);
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These tests run for all the flash chip configs shown in config_list, below (internal and external).
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*/
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#if defined(CONFIG_SPIRAM_SUPPORT) || TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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#if defined(CONFIG_SPIRAM_SUPPORT)
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#define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN)
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#define FLASH_TEST_CASE_3_IGNORE(STR, FUNCT_TO_RUN)
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#else
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// Disabled for ESP32-S2 due to lack of runners
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#define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \
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TEST_CASE(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);}
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@ -109,14 +107,15 @@ static const char TAG[] = "test_esp_flash";
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{ \
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/* no need to init */ \
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.host_id = -1, \
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}, \
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} \
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, \
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{ \
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.io_mode = TEST_SPI_READ_MODE,\
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.speed = TEST_SPI_SPEED, \
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.host_id = SPI_HOST, \
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.cs_id = 1, \
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/* the pin which is usually used by the PSRAM */ \
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.cs_io_num = 16, \
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.cs_io_num = SPI1_CS_IO, \
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.input_delay_ns = 0, \
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}
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@ -146,14 +145,14 @@ flashtest_config_t config_list[] = {
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flashtest_config_t config_list[] = {
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FLASHTEST_CONFIG_COMMON,
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/* No runners for esp32s2 for these config yet */
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// {
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// .io_mode = TEST_SPI_READ_MODE,
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// .speed = TEST_SPI_SPEED,
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// .host_id = FSPI_HOST,
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// .cs_id = 0,
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// .cs_io_num = FSPI_PIN_NUM_CS,
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// .input_delay_ns = 0,
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// },
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{
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.io_mode = TEST_SPI_READ_MODE,
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.speed = TEST_SPI_SPEED,
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.host_id = FSPI_HOST,
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.cs_id = 0,
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.cs_io_num = FSPI_PIN_NUM_CS,
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.input_delay_ns = 0,
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},
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// /* current runner doesn't have a flash on HSPI */
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// {
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// .io_mode = TEST_SPI_READ_MODE,
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@ -195,6 +194,19 @@ static void setup_bus(spi_host_device_t host_id)
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#ifdef EXTRA_SPI1_CLK_IO
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esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
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#endif
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#if !DISABLED_FOR_TARGETS(ESP32)
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#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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//Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2.
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int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin;
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int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin;
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gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in);
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gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false);
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gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in);
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gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false);
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#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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#endif //!DISABLED_FOR_TARGETS(ESP32)
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#if !DISABLED_FOR_TARGETS(ESP32)
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} else if (host_id == FSPI_HOST) {
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ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1);
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@ -293,6 +305,11 @@ static void setup_new_chip(const flashtest_config_t* test_cfg, esp_flash_t** out
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TEST_ESP_OK(err);
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err = esp_flash_init(init_chip);
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TEST_ESP_OK(err);
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uint32_t size;
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err = esp_flash_get_size(init_chip, &size);
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TEST_ESP_OK(err);
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ESP_LOGI(TAG, "Flash size: 0x%08X", size);
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*out_chip = init_chip;
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}
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@ -679,8 +696,6 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash
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}
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#ifndef CONFIG_SPIRAM_SUPPORT
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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// No runners
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TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]")
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{
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for (int i = 0; i < TEST_CONFIG_NUM; i++) {
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@ -688,7 +703,6 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[
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}
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}
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#endif
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#endif
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static void test_write_large_const_buffer(esp_flash_t* chip)
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{
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@ -1,4 +1,3 @@
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# for parallel jobs, CI_JOB_NAME will be "job_name index/total" (for example, "IT_001 1/2")
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# we need to convert to pattern "job_name_index.yml"
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.define_config_file_name: &define_config_file_name |
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@ -588,6 +587,13 @@ UT_037:
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# - ESP32S2_IDF
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# - UT_T1_LEDC
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UT_038:
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extends: .unit_test_s2_template
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parallel: 2
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tags:
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- ESP32S2_IDF
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- UT_T1_ESP_FLASH
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UT_041:
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extends: .unit_test_template
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tags:
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