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esp-idf/components/soc/esp32s3/include/soc/soc_caps.h

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soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
// The long term plan is to have a single soc_caps.h for all peripherals.
soc: add soc descriptions for esp32s3
2020-06-18 09:13:19 +00:00
// During the refactoring and multichip support development process, we
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
soc: add soc descriptions for esp32s3
2020-06-18 09:13:19 +00:00
#pragma once
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- COMMON CAPS ---------------------------------------*/
uart: add uart support on esp32s3
2020-11-19 09:03:10 +00:00
#define SOC_PCNT_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_CPU_CORES_NUM 2
soc: Add initial ESP32-C3 support From internal commit 7761d6e8
2020-11-26 04:39:49 +00:00
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_ULP_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
unit_test: Refactor all performance tests that rely on cache compensated timer There is no ccomp timer on C3, which means our performance tests will start failing again due to variance caused by cache misses. This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail performance test if CCOMP timer is supported on the target
2020-12-04 03:35:21 +00:00
#define SOC_CCOMP_TIMER_SUPPORTED 1
soc: Adds a soc_caps define for all chips to define the number of boot key digests
2021-01-05 15:09:24 +00:00
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
unit_test: Refactor all performance tests that rely on cache compensated timer There is no ccomp timer on C3, which means our performance tests will start failing again due to variance caused by cache misses. This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail performance test if CCOMP timer is supported on the target
2020-12-04 03:35:21 +00:00
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 12:17:18 +00:00
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- ADC CAPS ----------------------------------------*/
#include "adc_caps.h"
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#include "brownout_caps.h"
/*-------------------------- CPU CAPS ----------------------------------------*/
#include "cpu_caps.h"
/*-------------------------- DAC CAPS ----------------------------------------*/
#include "dac_caps.h"
/*-------------------------- GDMA CAPS ---------------------------------------*/
#include "gdma_caps.h"
/*-------------------------- GPIO CAPS ---------------------------------------*/
#include "gpio_caps.h"
dedicated gpio: add driver
2020-05-11 11:50:17 +00:00
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (4) /*!< 4 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (4) /*!< 4 inward channels on each CPU core */
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- I2C CAPS ----------------------------------------*/
#include "i2c_caps.h"
/*-------------------------- I2S CAPS ----------------------------------------*/
#include "i2s_caps.h"
/*-------------------------- LEDC CAPS ---------------------------------------*/
#include "ledc_caps.h"
/*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h"
/*-------------------------- PCNT CAPS ---------------------------------------*/
pcnt: add pcnt peripheral signal connections pcnt: fix bug in clear interrupt status
2020-09-18 09:22:59 +00:00
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4)
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- RMT CAPS ----------------------------------------*/
rmt: distinguish group and channel in HAL layer
2021-02-07 09:18:39 +00:00
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
rmt: split TX and RX in LL driver Split TX and RX function in LL driver. Channel number is encoded in driver layer. Added channel signal list in periph.c
2020-10-09 08:41:41 +00:00
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
rmt: distinguish group and channel in HAL layer
2021-02-07 09:18:39 +00:00
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
rmt: split TX and RX in LL driver Split TX and RX function in LL driver. Channel number is encoded in driver layer. Added channel signal list in periph.c
2020-10-09 08:41:41 +00:00
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h"
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
sigma_delta: add periph signal list and support esp32-s3
2020-10-22 05:16:49 +00:00
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- SPI CAPS ----------------------------------------*/
#include "spi_caps.h"
soc: Add initial ESP32-C3 support From internal commit 7761d6e8
2020-11-26 04:39:49 +00:00
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
#define SOC_SPIRAM_SUPPORTED 1
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
#include "systimer_caps.h"
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
timergroup: move interrupt index into peripheral description file 1. Added timer_group_periph.c file, describing module global signals (e.g. interrupt index) 2. Added more caps in soc_caps.h
2020-10-14 03:46:30 +00:00
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
soc: Add initial ESP32-C3 support From internal commit 7761d6e8
2020-11-26 04:39:49 +00:00
#define SOC_TIMER_GROUP_LAYOUT {2,2}
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-10 02:37:58 +00:00
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#include "touch_sensor_caps.h"
/*-------------------------- TWAI CAPS ---------------------------------------*/
#include "twai_caps.h"
/*-------------------------- UART CAPS ---------------------------------------*/
#include "uart_caps.h"
uart: add uart support on esp32s3
2020-11-19 09:03:10 +00:00
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
SHA/RSA: moved all caps to soc_caps.h
2020-10-29 02:51:36 +00:00
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user supplied context */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
AES/SHA: use GDMA driver instead of LL
2021-01-14 07:25:06 +00:00
#define SOC_SHA_GDMA (1)
SHA/RSA: moved all caps to soc_caps.h
2020-10-29 02:51:36 +00:00
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA384 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA512 (1)
#define SOC_SHA_SUPPORT_SHA512_224 (1)
#define SOC_SHA_SUPPORT_SHA512_256 (1)
#define SOC_SHA_SUPPORT_SHA512_T (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA384 (1)
#define SOC_SHA_SUPPORT_SHA512 (1)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (4096)
AES: refactor and add HAL layer Refactor the AES driver and add HAL, LL and caps. Add better support for running AES-GCM fully in hardware.
2020-11-12 07:11:38 +00:00
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
light sleep: light sleep support for esp32c3
2021-01-12 11:10:21 +00:00
/*-------------------------- Power Management CAPS ---------------------------*/
#define SOC_PM_SUPPORT_EXT_WAKEUP (1)
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
AES: refactor and add HAL layer Refactor the AES driver and add HAL, LL and caps. Add better support for running AES-GCM fully in hardware.
2020-11-12 07:11:38 +00:00
/* Has a centralized DMA, which is shared with all peripherals */
AES/SHA: use GDMA driver instead of LL
2021-01-14 07:25:06 +00:00
#define SOC_AES_GDMA (1)
AES: refactor and add HAL layer Refactor the AES driver and add HAL, LL and caps. Add better support for running AES-GCM fully in hardware.
2020-11-12 07:11:38 +00:00
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 12:17:18 +00:00
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
// Remove them when GDMA driver API is ready
Support ESP32S3 (beta2) WiFi
2021-01-24 16:18:42 +00:00
#define SOC_GDMA_SHA_DMA_CHANNEL (3)
#define SOC_GDMA_AES_DMA_CHANNEL (4)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
esp_wifi: store PHY digital registers before disabling PHY and load them after enabling PHY
2021-01-19 11:36:06 +00:00
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
spi_flash: Add auto suspend mode on esp32c3
2020-12-18 04:57:55 +00:00
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
Support ESP32S3 (beta2) WiFi
2021-01-24 16:18:42 +00:00
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)