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/*
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* SPDX - FileCopyrightText : 2022 - 2024 Espressif Systems ( Shanghai ) CO LTD
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*
* SPDX - License - Identifier : Apache - 2.0
*/
# pragma once
# ifdef __cplusplus
extern " C " {
# endif
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/*
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* * * * * * * * * * * * * * * * * * * * * * * * * ESP32S2 Root Clock Source * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* 1 ) Internal 8 MHz RC Oscillator : RC_FAST ( usually referred as FOSC or CK8M / CLK8M in TRM and reg . description )
*
* This RC oscillator generates a ~ 8.5 MHz clock signal output as the RC_FAST_CLK .
* The ~ 8.5 MHz signal output is also passed into a configurable divider , which by default divides the input clock
* frequency by 256 , to generate a RC_FAST_D256_CLK ( usually referred as 8 md256 or simply d256 in reg . description ) .
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK .
*
* 2 ) External 40 MHz Crystal Clock : XTAL
*
* 3 ) Internal 90 kHz RC Oscillator : RC_SLOW ( usually referrred as RTC in TRM or reg . description )
*
* This RC oscillator generates a ~ 90 kHz clock signal output as the RC_SLOW_CLK . The exact frequency of this clock
* can be computed in runtime through calibration .
*
* 4 ) External 32 kHz Crystal Clock ( optional ) : XTAL32K
*
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* The clock source for this XTAL32K_CLK can be either a 32 kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins or a 32 kHz clock signal generated by an external circuit . The external signal must be connected to the
* XTAL_32K_P pin .
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*
* XTAL32K_CLK can also be calibrated to get its exact frequency .
*/
/* With the default value of CK8M_DFREQ = 172, RC_FAST clock frequency is 8.5 MHz +/- 7% */
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# define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
# define SOC_CLK_RC_SLOW_FREQ_APPROX 90000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
# define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
# define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
// {loc}: EXT, INT
// {type}: XTAL, RC
// [attr] - optional: [frequency], FAST, SLOW
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/**
* @ brief Root clock
*/
typedef enum {
SOC_ROOT_CLK_INT_RC_FAST , /*!< Internal 8MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW , /*!< Internal 90kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL , /*!< External 40MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K , /*!< External 32kHz crystal/clock signal */
} soc_root_clk_t ;
/**
* @ brief CPU_CLK mux inputs , which are the supported clock sources for the CPU_CLK
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* @ note Enum values are matched with the register field values on purpose
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*/
typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0 , /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1 , /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2 , /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_APLL = 3 , /*!< Select APLL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_INVALID , /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t ;
/**
* @ brief RTC_SLOW_CLK mux inputs , which are the supported clock sources for the RTC_SLOW_CLK
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* @ note Enum values are matched with the register field values on purpose
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*/
typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0 , /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1 , /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2 , /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID , /*!< Invalid RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t ;
/**
* @ brief RTC_FAST_CLK mux inputs , which are the supported clock sources for the RTC_FAST_CLK
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* @ note Enum values are matched with the register field values on purpose
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*/
typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0 , /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4 , /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 1 , /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID , /*!< Invalid RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t ;
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// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: APB, APLL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
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/**
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* @ brief Supported clock sources for modules ( CPU , peripherals , RTC , etc . )
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*
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* @ note enum starts from 1 , to save 0 for special purpose
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*/
typedef enum {
// For CPU domain
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SOC_MOD_CLK_CPU = 1 , /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or APLL by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST , /*!< RTC_FAST_CLK can be sourced from XTAL_D4 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW , /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_APB , /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F160M , /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
SOC_MOD_CLK_XTAL32K , /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST , /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST_D256 , /*!< RC_FAST_D256_CLK is derived from the internal 8MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL , /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_REF_TICK , /*!< REF_TICK is derived from XTAL or RC_FAST via a divider, it has a fixed frequency of 1MHz by default */
SOC_MOD_CLK_APLL , /*!< APLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
SOC_MOD_CLK_TEMP_SENSOR , /*!< TEMP_SENSOR_CLK comes directly from the internal 8MHz rc oscillator */
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SOC_MOD_CLK_INVALID , /*!< Indication of the end of the available module clock sources */
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} soc_module_clk_t ;
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//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
/**
* @ brief Type of SYSTIMER clock source
*/
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL , /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL , /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t ;
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//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
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/**
* @ brief Array initializer for all supported clock sources of GPTimer
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*
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* The following code can be used to iterate all possible clocks :
* @ code { c }
* soc_periph_gptimer_clk_src_t gptimer_clks [ ] = ( soc_periph_gptimer_clk_src_t ) SOC_GPTIMER_CLKS ;
* for ( size_t i = 0 ; i < sizeof ( gptimer_clks ) / sizeof ( gptimer_clks [ 0 ] ) ; i + + ) {
* soc_periph_gptimer_clk_src_t clk = gptimer_clks [ i ] ;
* // Test GPTimer with the clock `clk`
* }
* @ endcode
*/
# define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
/**
* @ brief Type of GPTimer clock source
*/
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typedef enum {
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GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL , /*!< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default choice */
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} soc_periph_gptimer_clk_src_t ;
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/**
* @ brief Type of Timer Group clock source , reserved for the legacy timer group driver
*/
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typedef enum {
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TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB , /*!< Timer group source clock is APB */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL , /*!< Timer group source clock is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB , /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t ;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
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/**
* @ brief Array initializer for all supported clock sources of LCD
*/
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# define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M}
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/**
* @ brief Type of LCD clock source
*/
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typedef enum {
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LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M , /*!< Select PLL_F160M as the source clock */
LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M , /*!< Select PLL_F160M as the default choice */
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} soc_periph_lcd_clk_src_t ;
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//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of RMT
*/
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# define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK}
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/**
* @ brief Type of RMT clock source
*/
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typedef enum {
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RMT_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
RMT_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK , /*!< Select REF_TICK as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default choice */
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} soc_periph_rmt_clk_src_t ;
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/**
* @ brief Type of RMT clock source , reserved for the legacy RMT driver
*/
typedef enum {
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RMT_BASECLK_APB = SOC_MOD_CLK_APB , /*!< RMT source clock is APB CLK */
RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK , /*!< RMT source clock is REF_TICK */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB , /*!< RMT source clock default choice is APB */
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} soc_periph_rmt_clk_src_legacy_t ;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of Temperature Sensor
*/
# define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_TEMP_SENSOR}
/**
* @ brief Type of Temp Sensor clock source
*/
typedef enum {
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR , /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR , /*!< Select RC_FAST as the default choice */
} soc_periph_temperature_sensor_clk_src_t ;
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///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
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/**
* @ brief Array initializer for all supported clock sources of UART
*/
# define SOC_UART_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK}
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/**
* @ brief Type of UART clock source , reserved for the legacy UART driver
*/
typedef enum {
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UART_SCLK_APB = SOC_MOD_CLK_APB , /*!< UART source clock is APB CLK */
UART_SCLK_REF_TICK = SOC_MOD_CLK_REF_TICK , /*!< UART source clock is REF_TICK */
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB , /*!< UART source clock default choice is APB */
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} soc_periph_uart_clk_src_legacy_t ;
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///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
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* @ brief Array initializer for all supported clock sources of I2S
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*/
# define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL}
/**
* @ brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M , /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M , /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL , /*!< Select APLL as the source clock */
} soc_periph_i2s_clk_src_t ;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of I2C
*/
# define SOC_I2C_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK}
/**
* @ brief Type of I2C clock source .
*/
typedef enum {
I2C_CLK_SRC_APB = SOC_MOD_CLK_APB ,
I2C_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK ,
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB ,
} soc_periph_i2c_clk_src_t ;
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of SPI
*/
# define SOC_SPI_CLKS {SOC_MOD_CLK_APB}
/**
* @ brief Type of SPI clock source .
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as SPI source clock */
SPI_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t ;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
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/**
* @ brief Array initializer for all supported clock sources of SDM
*/
# define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
/**
* @ brief Sigma Delta Modulator clock source
*/
typedef enum {
SDM_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t ;
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//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of Glitch Filter
*/
# define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @ brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t ;
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////////////////////////////////////////////////////DAC/////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of DAC digital controller
*/
# define SOC_DAC_DIGI_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APLL}
/**
* @ brief DAC digital controller clock source
*
*/
typedef enum {
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DAC_DIGI_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
DAC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL , /*!< Select APLL as the source clock */
DAC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default source clock */
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} soc_periph_dac_digi_clk_src_t ;
/**
* @ brief Array initializer for all supported clock sources of DAC cosine wave generator
*/
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# define SOC_DAC_COSINE_CLKS {SOC_MOD_CLK_RTC_FAST}
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/**
* @ brief DAC cosine wave generator clock source
*
*/
typedef enum {
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DAC_COSINE_CLK_SRC_RTC_FAST = SOC_MOD_CLK_RTC_FAST , /*!< Select RTC FAST as the source clock */
DAC_COSINE_CLK_SRC_DEFAULT = SOC_MOD_CLK_RTC_FAST , /*!< Select RTC FAST as the default source clock */
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} soc_periph_dac_cosine_clk_src_t ;
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//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of TWAI
*/
# define SOC_TWAI_CLKS {SOC_MOD_CLK_APB}
/**
* @ brief TWAI clock source
*/
typedef enum {
TWAI_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default clock choice */
} soc_periph_twai_clk_src_t ;
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//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of ADC digital controller
*/
# define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APLL}
/**
* @ brief ADC digital controller clock source
*/
typedef enum {
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ADC_DIGI_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
ADC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL , /*!< Select APLL as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default clock choice */
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} soc_periph_adc_digi_clk_src_t ;
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/**
* @ brief Array initializer for all supported clock sources of ADC RTC controller
*/
# define SOC_ADC_RTC_CLKS {SOC_MOD_CLK_RC_FAST}
/**
* @ brief ADC RTC controller clock source
*/
typedef enum {
ADC_RTC_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST , /*!< Select RC_FAST as the source clock */
ADC_RTC_CLK_SRC_DEFAULT = SOC_MOD_CLK_RC_FAST , /*!< Select RC_FAST as the default clock choice */
} soc_periph_adc_rtc_clk_src_t ;
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//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of MWDT
*/
# define SOC_MWDT_CLKS {SOC_MOD_CLK_APB}
/**
* @ brief MWDT clock source
*/
typedef enum {
MWDT_CLK_SRC_APB = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB , /*!< Select APB as the default clock choice */
} soc_periph_mwdt_clk_src_t ;
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//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @ brief Array initializer for all supported clock sources of LEDC
*/
# define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_REF_TICK}
/**
* @ brief Type of LEDC clock source , reserved for the legacy LEDC driver
*/
typedef enum {
LEDC_AUTO_CLK = 0 , /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB , /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST , /*!< Select RC_FAST as the source clock */
LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK , /*!< Select REF_TICK as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL , /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__ ( ( deprecated ( " please use 'LEDC_USE_RC_FAST_CLK' instead " ) ) ) = LEDC_USE_RC_FAST_CLK , /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t ;
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//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKOUT_SIG_PLL = 1 , /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_RC_SLOW = 4 , /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_XTAL = 5 , /*!< Main crystal oscillator clock */
CLKOUT_SIG_APLL = 6 , /*!< Divided by PLL, frequency is configurable */
CLKOUT_SIG_REF_TICK = 12 , /*!< Divided by APB clock, usually be 1MHz */
CLKOUT_SIG_PLL_F80M = 13 , /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_RC_FAST = 14 , /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_INVALID = 0xFF ,
} soc_clkout_sig_id_t ;
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# ifdef __cplusplus
}
# endif