kopia lustrzana https://github.com/cariboulabs/cariboulite
619 wiersze
20 KiB
C
619 wiersze
20 KiB
C
/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_at86rf215
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* @{
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*
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* @file
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* @brief Register Definitions for the AT86RF215 chip
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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* @}
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*/
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#ifndef AT86RF215_REGISTERS_H
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#define AT86RF215_REGISTERS_H
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#include <stdint.h>
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#include "at86rf215_regs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Radio Frontend registers
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* @{
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*/
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struct at86rf215_RF_regs {
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uint16_t RG_IRQS; /**< see datasheet */
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uint16_t RG_IRQM; /**< see datasheet */
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uint16_t RG_AUXS; /**< see datasheet */
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uint16_t RG_STATE; /**< see datasheet */
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uint16_t RG_CMD; /**< see datasheet */
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uint16_t RG_CS; /**< see datasheet */
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uint16_t RG_CCF0L; /**< see datasheet */
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uint16_t RG_CCF0H; /**< see datasheet */
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uint16_t RG_CNL; /**< see datasheet */
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uint16_t RG_CNM; /**< see datasheet */
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uint16_t RG_RXBWC; /**< see datasheet */
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uint16_t RG_RXDFE; /**< see datasheet */
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uint16_t RG_AGCC; /**< see datasheet */
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uint16_t RG_AGCS; /**< see datasheet */
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uint16_t RG_RSSI; /**< see datasheet */
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uint16_t RG_EDC; /**< see datasheet */
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uint16_t RG_EDD; /**< see datasheet */
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uint16_t RG_EDV; /**< see datasheet */
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uint16_t RG_RNDV; /**< see datasheet */
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uint16_t RG_TXCUTC; /**< see datasheet */
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uint16_t RG_TXDFE; /**< see datasheet */
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uint16_t RG_PAC; /**< see datasheet */
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uint16_t RG_PADFE; /**< see datasheet */
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uint16_t RG_PLL; /**< see datasheet */
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uint16_t RG_PLLCF; /**< see datasheet */
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uint16_t RG_TXCI; /**< see datasheet */
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uint16_t RG_TXCQ; /**< see datasheet */
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uint16_t RG_TXDACI; /**< see datasheet */
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uint16_t RG_TXDACQ; /**< see datasheet */
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};
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/** @} */
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/**
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* @brief Base Band Controller registers
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* @{
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*/
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struct at86rf215_BBC_regs {
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uint16_t RG_IRQS; /**< see datasheet */
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uint16_t RG_FBRXS; /**< see datasheet */
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uint16_t RG_FBRXE; /**< see datasheet */
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uint16_t RG_FBTXS; /**< see datasheet */
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uint16_t RG_FBTXE; /**< see datasheet */
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uint16_t RG_IRQM; /**< see datasheet */
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uint16_t RG_PC; /**< see datasheet */
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uint16_t RG_PS; /**< see datasheet */
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uint16_t RG_RXFLL; /**< see datasheet */
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uint16_t RG_RXFLH; /**< see datasheet */
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uint16_t RG_TXFLL; /**< see datasheet */
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uint16_t RG_TXFLH; /**< see datasheet */
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uint16_t RG_FBLL; /**< see datasheet */
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uint16_t RG_FBLH; /**< see datasheet */
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uint16_t RG_FBLIL; /**< see datasheet */
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uint16_t RG_FBLIH; /**< see datasheet */
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uint16_t RG_OFDMPHRTX; /**< see datasheet */
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uint16_t RG_OFDMPHRRX; /**< see datasheet */
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uint16_t RG_OFDMC; /**< see datasheet */
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uint16_t RG_OFDMSW; /**< see datasheet */
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uint16_t RG_OQPSKC0; /**< see datasheet */
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uint16_t RG_OQPSKC1; /**< see datasheet */
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uint16_t RG_OQPSKC2; /**< see datasheet */
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uint16_t RG_OQPSKC3; /**< see datasheet */
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uint16_t RG_OQPSKPHRTX; /**< see datasheet */
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uint16_t RG_OQPSKPHRRX; /**< see datasheet */
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uint16_t RG_AFC0; /**< see datasheet */
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uint16_t RG_AFC1; /**< see datasheet */
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uint16_t RG_AFFTM; /**< see datasheet */
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uint16_t RG_AFFVM; /**< see datasheet */
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uint16_t RG_AFS; /**< see datasheet */
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uint16_t RG_MACEA0; /**< see datasheet */
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uint16_t RG_MACEA1; /**< see datasheet */
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uint16_t RG_MACEA2; /**< see datasheet */
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uint16_t RG_MACEA3; /**< see datasheet */
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uint16_t RG_MACEA4; /**< see datasheet */
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uint16_t RG_MACEA5; /**< see datasheet */
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uint16_t RG_MACEA6; /**< see datasheet */
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uint16_t RG_MACEA7; /**< see datasheet */
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uint16_t RG_MACPID0F0; /**< see datasheet */
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uint16_t RG_MACPID1F0; /**< see datasheet */
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uint16_t RG_MACSHA0F0; /**< see datasheet */
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uint16_t RG_MACSHA1F0; /**< see datasheet */
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uint16_t RG_MACPID0F1; /**< see datasheet */
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uint16_t RG_MACPID1F1; /**< see datasheet */
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uint16_t RG_MACSHA0F1; /**< see datasheet */
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uint16_t RG_MACSHA1F1; /**< see datasheet */
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uint16_t RG_MACPID0F2; /**< see datasheet */
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uint16_t RG_MACPID1F2; /**< see datasheet */
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uint16_t RG_MACSHA0F2; /**< see datasheet */
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uint16_t RG_MACSHA1F2; /**< see datasheet */
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uint16_t RG_MACPID0F3; /**< see datasheet */
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uint16_t RG_MACPID1F3; /**< see datasheet */
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uint16_t RG_MACSHA0F3; /**< see datasheet */
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uint16_t RG_MACSHA1F3; /**< see datasheet */
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uint16_t RG_AMCS; /**< see datasheet */
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uint16_t RG_AMEDT; /**< see datasheet */
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uint16_t RG_AMAACKPD; /**< see datasheet */
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uint16_t RG_AMAACKTL; /**< see datasheet */
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uint16_t RG_AMAACKTH; /**< see datasheet */
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uint16_t RG_FSKC0; /**< see datasheet */
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uint16_t RG_FSKC1; /**< see datasheet */
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uint16_t RG_FSKC2; /**< see datasheet */
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uint16_t RG_FSKC3; /**< see datasheet */
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uint16_t RG_FSKC4; /**< see datasheet */
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uint16_t RG_FSKPLL; /**< see datasheet */
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uint16_t RG_FSKSFD0L; /**< see datasheet */
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uint16_t RG_FSKSFD0H; /**< see datasheet */
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uint16_t RG_FSKSFD1L; /**< see datasheet */
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uint16_t RG_FSKSFD1H; /**< see datasheet */
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uint16_t RG_FSKPHRTX; /**< see datasheet */
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uint16_t RG_FSKPHRRX; /**< see datasheet */
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uint16_t RG_FSKRPC; /**< see datasheet */
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uint16_t RG_FSKRPCONT; /**< see datasheet */
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uint16_t RG_FSKRPCOFFT; /**< see datasheet */
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uint16_t RG_FSKRRXFLL; /**< see datasheet */
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uint16_t RG_FSKRRXFLH; /**< see datasheet */
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uint16_t RG_FSKDM; /**< see datasheet */
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uint16_t RG_FSKPE0; /**< see datasheet */
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uint16_t RG_FSKPE1; /**< see datasheet */
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uint16_t RG_FSKPE2; /**< see datasheet */
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uint16_t RG_PMUC; /**< see datasheet */
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uint16_t RG_PMUVAL; /**< see datasheet */
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uint16_t RG_PMUQF; /**< see datasheet */
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uint16_t RG_PMUI; /**< see datasheet */
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uint16_t RG_PMUQ; /**< see datasheet */
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uint16_t RG_CNTC; /**< see datasheet */
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uint16_t RG_CNT0; /**< see datasheet */
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uint16_t RG_CNT1; /**< see datasheet */
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uint16_t RG_CNT2; /**< see datasheet */
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uint16_t RG_CNT3; /**< see datasheet */
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};
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/** @} */
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/**
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* @name sub-GHz Radio Frontend register map
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* @{
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*/
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static const struct at86rf215_RF_regs RF09_regs = {
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.RG_IRQS = 0x00,
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.RG_IRQM = 0x100,
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.RG_AUXS = 0x101,
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.RG_STATE = 0x102,
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.RG_CMD = 0x103,
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.RG_CS = 0x104,
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.RG_CCF0L = 0x105,
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.RG_CCF0H = 0x106,
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.RG_CNL = 0x107,
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.RG_CNM = 0x108,
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.RG_RXBWC = 0x109,
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.RG_RXDFE = 0x10A,
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.RG_AGCC = 0x10B,
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.RG_AGCS = 0x10C,
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.RG_RSSI = 0x10D,
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.RG_EDC = 0x10E,
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.RG_EDD = 0x10F,
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.RG_EDV = 0x110,
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.RG_RNDV = 0x111,
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.RG_TXCUTC = 0x112,
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.RG_TXDFE = 0x113,
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.RG_PAC = 0x114,
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.RG_PADFE = 0x116,
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.RG_PLL = 0x121,
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.RG_PLLCF = 0x122,
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.RG_TXCI = 0x125,
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.RG_TXCQ = 0x126,
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.RG_TXDACI = 0x127,
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.RG_TXDACQ = 0x128,
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};
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/** @} */
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/**
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* @name 2.4 GHz Radio Frontend register map
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* @{
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*/
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static const struct at86rf215_RF_regs RF24_regs = {
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.RG_IRQS = 0x01,
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.RG_IRQM = 0x200,
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.RG_AUXS = 0x201,
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.RG_STATE = 0x202,
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.RG_CMD = 0x203,
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.RG_CS = 0x204,
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.RG_CCF0L = 0x205,
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.RG_CCF0H = 0x206,
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.RG_CNL = 0x207,
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.RG_CNM = 0x208,
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.RG_RXBWC = 0x209,
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.RG_RXDFE = 0x20A,
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.RG_AGCC = 0x20B,
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.RG_AGCS = 0x20C,
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.RG_RSSI = 0x20D,
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.RG_EDC = 0x20E,
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.RG_EDD = 0x20F,
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.RG_EDV = 0x210,
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.RG_RNDV = 0x211,
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.RG_TXCUTC = 0x212,
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.RG_TXDFE = 0x213,
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.RG_PAC = 0x214,
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.RG_PADFE = 0x216,
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.RG_PLL = 0x221,
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.RG_PLLCF = 0x222,
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.RG_TXCI = 0x225,
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.RG_TXCQ = 0x226,
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.RG_TXDACI = 0x227,
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.RG_TXDACQ = 0x228,
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};
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/** @} */
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/**
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* @name sub-GHz Radio Frontend register map
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* @{
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*/
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static const struct at86rf215_BBC_regs BBC0_regs = {
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.RG_IRQS = 0x02,
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.RG_FBRXS = 0x2000,
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.RG_FBRXE = 0x27FE,
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.RG_FBTXS = 0x2800,
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.RG_FBTXE = 0x2FFE,
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.RG_IRQM = 0x300,
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.RG_PC = 0x301,
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.RG_PS = 0x302,
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.RG_RXFLL = 0x304,
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.RG_RXFLH = 0x305,
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.RG_TXFLL = 0x306,
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.RG_TXFLH = 0x307,
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.RG_FBLL = 0x308,
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.RG_FBLH = 0x309,
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.RG_FBLIL = 0x30A,
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.RG_FBLIH = 0x30B,
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.RG_OFDMPHRTX = 0x30C,
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.RG_OFDMPHRRX = 0x30D,
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.RG_OFDMC = 0x30E,
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.RG_OFDMSW = 0x30F,
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.RG_OQPSKC0 = 0x310,
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.RG_OQPSKC1 = 0x311,
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.RG_OQPSKC2 = 0x312,
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.RG_OQPSKC3 = 0x313,
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.RG_OQPSKPHRTX = 0x314,
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.RG_OQPSKPHRRX = 0x315,
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.RG_AFC0 = 0x320,
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.RG_AFC1 = 0x321,
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.RG_AFFTM = 0x322,
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.RG_AFFVM = 0x323,
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.RG_AFS = 0x324,
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.RG_MACEA0 = 0x325,
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.RG_MACEA1 = 0x326,
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.RG_MACEA2 = 0x327,
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.RG_MACEA3 = 0x328,
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.RG_MACEA4 = 0x329,
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.RG_MACEA5 = 0x32A,
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.RG_MACEA6 = 0x32B,
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.RG_MACEA7 = 0x32C,
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.RG_MACPID0F0 = 0x32D,
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.RG_MACPID1F0 = 0x32E,
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.RG_MACSHA0F0 = 0x32F,
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.RG_MACSHA1F0 = 0x330,
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.RG_MACPID0F1 = 0x331,
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.RG_MACPID1F1 = 0x332,
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.RG_MACSHA0F1 = 0x333,
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.RG_MACSHA1F1 = 0x334,
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.RG_MACPID0F2 = 0x335,
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.RG_MACPID1F2 = 0x336,
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.RG_MACSHA0F2 = 0x337,
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.RG_MACSHA1F2 = 0x338,
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.RG_MACPID0F3 = 0x339,
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.RG_MACPID1F3 = 0x33A,
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.RG_MACSHA0F3 = 0x33B,
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.RG_MACSHA1F3 = 0x33C,
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.RG_AMCS = 0x340,
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.RG_AMEDT = 0x341,
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.RG_AMAACKPD = 0x342,
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.RG_AMAACKTL = 0x343,
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.RG_AMAACKTH = 0x344,
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.RG_FSKC0 = 0x360,
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.RG_FSKC1 = 0x361,
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.RG_FSKC2 = 0x362,
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.RG_FSKC3 = 0x363,
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.RG_FSKC4 = 0x364,
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.RG_FSKPLL = 0x365,
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.RG_FSKSFD0L = 0x366,
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.RG_FSKSFD0H = 0x367,
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.RG_FSKSFD1L = 0x368,
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.RG_FSKSFD1H = 0x369,
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.RG_FSKPHRTX = 0x36A,
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.RG_FSKPHRRX = 0x36B,
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.RG_FSKRPC = 0x36C,
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.RG_FSKRPCONT = 0x36D,
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.RG_FSKRPCOFFT = 0x36E,
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.RG_FSKRRXFLL = 0x370,
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.RG_FSKRRXFLH = 0x371,
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.RG_FSKDM = 0x372,
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.RG_FSKPE0 = 0x373,
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.RG_FSKPE1 = 0x374,
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.RG_FSKPE2 = 0x375,
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.RG_PMUC = 0x380,
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.RG_PMUVAL = 0x381,
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.RG_PMUQF = 0x382,
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.RG_PMUI = 0x383,
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.RG_PMUQ = 0x384,
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.RG_CNTC = 0x390,
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.RG_CNT0 = 0x391,
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.RG_CNT1 = 0x392,
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.RG_CNT2 = 0x393,
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.RG_CNT3 = 0x394,
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};
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/** @} */
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/**
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* @name 2.4 GHz Radio Frontend register map
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* @{
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*/
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static const struct at86rf215_BBC_regs BBC1_regs = {
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.RG_IRQS = 0x03,
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.RG_FBRXS = 0x3000,
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.RG_FBRXE = 0x37FE,
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.RG_FBTXS = 0x3800,
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.RG_FBTXE = 0x3FFE,
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.RG_IRQM = 0x400,
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.RG_PC = 0x401,
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.RG_PS = 0x402,
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.RG_RXFLL = 0x404,
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.RG_RXFLH = 0x405,
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.RG_TXFLL = 0x406,
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.RG_TXFLH = 0x407,
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.RG_FBLL = 0x408,
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.RG_FBLH = 0x409,
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.RG_FBLIL = 0x40A,
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.RG_FBLIH = 0x40B,
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.RG_OFDMPHRTX = 0x40C,
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.RG_OFDMPHRRX = 0x40D,
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.RG_OFDMC = 0x40E,
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.RG_OFDMSW = 0x40F,
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.RG_OQPSKC0 = 0x410,
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.RG_OQPSKC1 = 0x411,
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.RG_OQPSKC2 = 0x412,
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.RG_OQPSKC3 = 0x413,
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.RG_OQPSKPHRTX = 0x414,
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.RG_OQPSKPHRRX = 0x415,
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.RG_AFC0 = 0x420,
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.RG_AFC1 = 0x421,
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.RG_AFFTM = 0x422,
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.RG_AFFVM = 0x423,
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.RG_AFS = 0x424,
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.RG_MACEA0 = 0x425,
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.RG_MACEA1 = 0x426,
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.RG_MACEA2 = 0x427,
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.RG_MACEA3 = 0x428,
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.RG_MACEA4 = 0x429,
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.RG_MACEA5 = 0x42A,
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.RG_MACEA6 = 0x42B,
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.RG_MACEA7 = 0x42C,
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.RG_MACPID0F0 = 0x42D,
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.RG_MACPID1F0 = 0x42E,
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.RG_MACSHA0F0 = 0x42F,
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.RG_MACSHA1F0 = 0x430,
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.RG_MACPID0F1 = 0x431,
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.RG_MACPID1F1 = 0x432,
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.RG_MACSHA0F1 = 0x433,
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.RG_MACSHA1F1 = 0x434,
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.RG_MACPID0F2 = 0x435,
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.RG_MACPID1F2 = 0x436,
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.RG_MACSHA0F2 = 0x437,
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.RG_MACSHA1F2 = 0x438,
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.RG_MACPID0F3 = 0x439,
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.RG_MACPID1F3 = 0x43A,
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.RG_MACSHA0F3 = 0x43B,
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.RG_MACSHA1F3 = 0x43C,
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.RG_AMCS = 0x440,
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.RG_AMEDT = 0x441,
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.RG_AMAACKPD = 0x442,
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.RG_AMAACKTL = 0x443,
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.RG_AMAACKTH = 0x444,
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.RG_FSKC0 = 0x460,
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.RG_FSKC1 = 0x461,
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.RG_FSKC2 = 0x462,
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.RG_FSKC3 = 0x463,
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.RG_FSKC4 = 0x464,
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.RG_FSKPLL = 0x465,
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.RG_FSKSFD0L = 0x466,
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.RG_FSKSFD0H = 0x467,
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.RG_FSKSFD1L = 0x468,
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.RG_FSKSFD1H = 0x469,
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.RG_FSKPHRTX = 0x46A,
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.RG_FSKPHRRX = 0x46B,
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.RG_FSKRPC = 0x46C,
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.RG_FSKRPCONT = 0x46D,
|
|
.RG_FSKRPCOFFT = 0x46E,
|
|
.RG_FSKRRXFLL = 0x470,
|
|
.RG_FSKRRXFLH = 0x471,
|
|
.RG_FSKDM = 0x472,
|
|
.RG_FSKPE0 = 0x473,
|
|
.RG_FSKPE1 = 0x474,
|
|
.RG_FSKPE2 = 0x475,
|
|
.RG_PMUC = 0x480,
|
|
.RG_PMUVAL = 0x481,
|
|
.RG_PMUQF = 0x482,
|
|
.RG_PMUI = 0x483,
|
|
.RG_PMUQ = 0x484,
|
|
.RG_CNTC = 0x490,
|
|
.RG_CNT0 = 0x491,
|
|
.RG_CNT1 = 0x492,
|
|
.RG_CNT2 = 0x493,
|
|
.RG_CNT3 = 0x494,
|
|
};
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Part Numbers
|
|
* @{
|
|
*/
|
|
#define AT86RF215_PN (0x34) /* sub-GHz & 2.4 GHz */
|
|
#define AT86RF215IQ_PN (0x35) /* I/Q radio only */
|
|
#define AT86RF215M_PN (0x36) /* sub-GHz only */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI command prefixes
|
|
* @{
|
|
*/
|
|
#define FLAG_WRITE 0x8000
|
|
#define FLAG_READ 0x0000
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Radio Commands written to RF->RG_CMD
|
|
* @{
|
|
*/
|
|
#define CMD_RF_NOP 0x0
|
|
#define CMD_RF_SLEEP 0x1
|
|
#define CMD_RF_TRXOFF 0x2
|
|
#define CMD_RF_TXPREP 0x3
|
|
#define CMD_RF_TX 0x4
|
|
#define CMD_RF_RX 0x5
|
|
#define CMD_RF_RESET 0x7 /* transceiver reset, the transceiver state
|
|
will automatically end up in state TRXOFF */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Radio States, read from RF->RG_STATE
|
|
* @{
|
|
*/
|
|
#define RF_STATE_TRXOFF 0x2 /* Transceiver off, SPI active */
|
|
#define RF_STATE_TXPREP 0x3 /* Transmit preparation */
|
|
#define RF_STATE_TX 0x4 /* Transmit */
|
|
#define RF_STATE_RX 0x5 /* Receive */
|
|
#define RF_STATE_TRANSITION 0x6 /* State transition in progress */
|
|
#define RF_STATE_RESET 0x7 /* Transceiver is in state RESET or SLEEP */
|
|
/** @} */
|
|
|
|
/** offset (in Hz) for CCF0 in 2.4 GHz mode */
|
|
#define CCF0_24G_OFFSET 1500000U
|
|
|
|
/** The sub-register configures the sampling frequency of the received signal.
|
|
* Undefined values are mapped to default setting fS=4000kHz
|
|
* @{
|
|
*/
|
|
#define RF_SR_4000K 0x1
|
|
#define RF_SR_2000K 0x2
|
|
#define RF_SR_1333K 0x3
|
|
#define RF_SR_1000K 0x4
|
|
#define RF_SR_800K 0x5
|
|
#define RF_SR_666K 0x6
|
|
#define RF_SR_500K 0x8
|
|
#define RF_SR_400K 0xA
|
|
/** @} */
|
|
|
|
/* The sub-register configures the relative cut-off frequency fCUT
|
|
where 1.0 refers to half the sample frequency fS. */
|
|
/** Fcut = 0.25 * Fs/2 */
|
|
#define RF_RCUT_FS_BY_8 (0x0 << RXDFE_RCUT_SHIFT)
|
|
/** Fcut = 0.375 * Fs/2 */
|
|
#define RF_RCUT_FS_BY_5P3 (0x1 << RXDFE_RCUT_SHIFT)
|
|
/** Fcut = 0.5 * Fs/2 */
|
|
#define RF_RCUT_FS_BY_4 (0x2 << RXDFE_RCUT_SHIFT)
|
|
/** Fcut = 0.75 * Fs/2 */
|
|
#define RF_RCUT_FS_BY_2P6 (0x3 << RXDFE_RCUT_SHIFT)
|
|
/** Fcut = 1.0 * Fs/2 */
|
|
#define RF_RCUT_FS_BY_2 (0x4 << RXDFE_RCUT_SHIFT)
|
|
|
|
/** The averaging time is calculated by T[μs]=DF*DTB.
|
|
* @{
|
|
*/
|
|
#define RF_DTB_2_US 0x0
|
|
#define RF_DTB_8_US 0x1
|
|
#define RF_DTB_32_US 0x2
|
|
#define RF_DTB_128_US 0x3
|
|
/** @} */
|
|
|
|
/** BPSK, rate ½, 4 x frequency repetition */
|
|
#define BB_MCS_BPSK_REP4 0
|
|
/** BPSK, rate ½, 2 x frequency repetition */
|
|
#define BB_MCS_BPSK_REP2 1
|
|
/** QPSK, rate ½, 2 x frequency repetition */
|
|
#define BB_MCS_QPSK_REP2 2
|
|
/** QPSK, rate ½ */
|
|
#define BB_MCS_QPSK_1BY2 3
|
|
/** QPSK, rate ¾ */
|
|
#define BB_MCS_QPSK_3BY4 4
|
|
/** 16-QAM, rate ½ */
|
|
#define BB_MCS_16QAM_1BY2 5
|
|
/** 16-QAM, rate ¾ */
|
|
#define BB_MCS_16QAM_3BY4 6
|
|
|
|
/** receive only MR-O-QPSK */
|
|
#define RXM_MR_OQPSK 0x0
|
|
/** receive only legacy O-QPSK */
|
|
#define RXM_LEGACY_OQPSK 0x1
|
|
/** receive both legacy & MR-O-QPSK */
|
|
#define RXM_BOTH_OQPSK 0x2
|
|
/** receive nothing */
|
|
#define RXM_DISABLE 0x3
|
|
|
|
/** Modulation Order 2-FSK */
|
|
#define FSK_MORD_2SFK (0 << FSKC0_MORD_SHIFT)
|
|
/** Modulation Order 4-FSK */
|
|
#define FSK_MORD_4SFK (1 << FSKC0_MORD_SHIFT)
|
|
|
|
/**
|
|
* FSK modulation index
|
|
* @{
|
|
*/
|
|
#define FSK_MIDX_3_BY_8 (0 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_4_BY_8 (1 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_6_BY_8 (2 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_8_BY_8 (3 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_10_BY_8 (4 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_12_BY_8 (5 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_14_BY_8 (6 << FSKC0_MIDX_SHIFT)
|
|
#define FSK_MIDX_16_BY_8 (7 << FSKC0_MIDX_SHIFT)
|
|
/** @} */
|
|
|
|
/**
|
|
* FSK modulation index scale
|
|
* @{
|
|
*/
|
|
#define FSK_MIDXS_SCALE_7_BY_8 (0 << FSKC0_MIDXS_SHIFT)
|
|
#define FSK_MIDXS_SCALE_8_BY_8 (1 << FSKC0_MIDXS_SHIFT)
|
|
#define FSK_MIDXS_SCALE_9_BY_8 (2 << FSKC0_MIDXS_SHIFT)
|
|
#define FSK_MIDXS_SCALE_10_BY_8 (3 << FSKC0_MIDXS_SHIFT)
|
|
/** @} */
|
|
|
|
/**
|
|
* FSK bandwidth time product
|
|
* @{
|
|
*/
|
|
#define FSK_BT_05 (0 << FSKC0_BT_SHIFT)
|
|
#define FSK_BT_10 (1 << FSKC0_BT_SHIFT)
|
|
#define FSK_BT_15 (2 << FSKC0_BT_SHIFT)
|
|
#define FSK_BT_20 (3 << FSKC0_BT_SHIFT)
|
|
/** @} */
|
|
|
|
/**
|
|
* FSK symbol rate (kHz)
|
|
* @{
|
|
*/
|
|
#define FSK_SRATE_50K 0x0
|
|
#define FSK_SRATE_100K 0x1
|
|
#define FSK_SRATE_150K 0x2
|
|
#define FSK_SRATE_200K 0x3
|
|
#define FSK_SRATE_300K 0x4
|
|
#define FSK_SRATE_400K 0x5
|
|
/** @} */
|
|
|
|
/**
|
|
* FSK channel spacing (kHz)
|
|
* @{
|
|
*/
|
|
#define FSK_CHANNEL_SPACING_200K 0x0
|
|
#define FSK_CHANNEL_SPACING_400K 0x1
|
|
/** @} */
|
|
|
|
/** Lower values increase the SFD detector sensitivity.
|
|
Higher values increase the SFD selectivity.
|
|
The default value 8 is recommended for simultaneous sensing
|
|
of the SFD pairs according to IEEE 802.15.4g. */
|
|
#define FSKC3_SFDT(n) (((n) << FSKC3_SFDT_SHIFT) & FSKC3_SFDT_MASK)
|
|
|
|
/** Lower values increase the preamble detector sensitivity. */
|
|
#define FSKC3_PDT(n) (((n) << FSKC3_PDT_SHIFT) & FSKC3_PDT_MASK)
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* AT86RF215_REGISTERS_H */
|