kopia lustrzana https://github.com/cariboulabs/cariboulite
3287 wiersze
225 KiB
Plaintext
3287 wiersze
225 KiB
Plaintext
yosys -p 'synth_ice40 -top top -json top.json -blif top.blif' -p 'ice40_opt' -p 'fsm_opt' top.v
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.26+1 (git sha1 b1a011138, gcc 10.2.1-6 -fPIC -Os)
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-- Parsing `top.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: top.v
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Parsing Verilog input from `top.v' to AST representation.
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Warning: Yosys has only limited support for tri-state logic at the moment. (top.v:129)
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Warning: Yosys has only limited support for tri-state logic at the moment. (top.v:540)
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Storing AST representation for module `$abstract\spi_slave'.
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Storing AST representation for module `$abstract\spi_if'.
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Storing AST representation for module `$abstract\sys_ctrl'.
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Storing AST representation for module `$abstract\io_ctrl'.
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Storing AST representation for module `$abstract\smi_ctrl'.
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Storing AST representation for module `$abstract\lvds_rx'.
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Storing AST representation for module `$abstract\lvds_tx'.
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Storing AST representation for module `$abstract\complex_fifo'.
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Storing AST representation for module `$abstract\top'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ice40 -top top -json top.json -blif top.blif' --
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2. Executing SYNTH_ICE40 pass.
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2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\SB_IO'.
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Generating RTLIL representation for module `\SB_GB_IO'.
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Generating RTLIL representation for module `\SB_GB'.
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Generating RTLIL representation for module `\SB_LUT4'.
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Generating RTLIL representation for module `\SB_CARRY'.
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Generating RTLIL representation for module `\SB_DFF'.
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Generating RTLIL representation for module `\SB_DFFE'.
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Generating RTLIL representation for module `\SB_DFFSR'.
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Generating RTLIL representation for module `\SB_DFFR'.
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Generating RTLIL representation for module `\SB_DFFSS'.
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Generating RTLIL representation for module `\SB_DFFS'.
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Generating RTLIL representation for module `\SB_DFFESR'.
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Generating RTLIL representation for module `\SB_DFFER'.
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Generating RTLIL representation for module `\SB_DFFESS'.
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Generating RTLIL representation for module `\SB_DFFES'.
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Generating RTLIL representation for module `\SB_DFFN'.
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Generating RTLIL representation for module `\SB_DFFNE'.
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Generating RTLIL representation for module `\SB_DFFNSR'.
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Generating RTLIL representation for module `\SB_DFFNR'.
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Generating RTLIL representation for module `\SB_DFFNSS'.
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Generating RTLIL representation for module `\SB_DFFNS'.
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Generating RTLIL representation for module `\SB_DFFNESR'.
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Generating RTLIL representation for module `\SB_DFFNER'.
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Generating RTLIL representation for module `\SB_DFFNESS'.
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Generating RTLIL representation for module `\SB_DFFNES'.
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Generating RTLIL representation for module `\SB_RAM40_4K'.
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Generating RTLIL representation for module `\SB_RAM40_4KNR'.
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Generating RTLIL representation for module `\SB_RAM40_4KNW'.
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Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
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Generating RTLIL representation for module `\ICESTORM_LC'.
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Generating RTLIL representation for module `\SB_PLL40_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
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Generating RTLIL representation for module `\SB_WARMBOOT'.
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Generating RTLIL representation for module `\SB_SPRAM256KA'.
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Generating RTLIL representation for module `\SB_HFOSC'.
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Generating RTLIL representation for module `\SB_LFOSC'.
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Generating RTLIL representation for module `\SB_RGBA_DRV'.
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Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
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Generating RTLIL representation for module `\SB_RGB_DRV'.
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Generating RTLIL representation for module `\SB_I2C'.
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Generating RTLIL representation for module `\SB_SPI'.
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Generating RTLIL representation for module `\SB_LEDDA_IP'.
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Generating RTLIL representation for module `\SB_FILTER_50NS'.
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Generating RTLIL representation for module `\SB_IO_I3C'.
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Generating RTLIL representation for module `\SB_IO_OD'.
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Generating RTLIL representation for module `\SB_MAC16'.
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Generating RTLIL representation for module `\ICESTORM_RAM'.
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Successfully finished Verilog frontend.
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2.2. Executing HIERARCHY pass (managing design hierarchy).
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2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
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Generating RTLIL representation for module `\top'.
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2.3.1. Analyzing design hierarchy..
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Top module: \top
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2.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\smi_ctrl'.
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Generating RTLIL representation for module `\smi_ctrl'.
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Warning: wire '\w_fifo_pull_trigger' is assigned in a block at smi_ctrl.v:122.13-122.71.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:181.13-181.40.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:197.25-197.52.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:205.25-205.52.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:217.21-217.48.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:231.21-231.48.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:241.25-241.52.
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Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:245.25-245.52.
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smi_ctrl.v:174: Warning: Identifier `\swe_and_reset' is implicitly declared.
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Parameter \ADDR_WIDTH = 10
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Parameter \DATA_WIDTH = 16
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2.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\complex_fifo'.
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Parameter \ADDR_WIDTH = 10
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Parameter \DATA_WIDTH = 16
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Generating RTLIL representation for module `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo'.
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2.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\lvds_tx'.
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Generating RTLIL representation for module `\lvds_tx'.
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Warning: wire '\o_ddr_data' is assigned in a block at lvds_tx.v:47.7-47.63.
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Parameter \ADDR_WIDTH = 10
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Parameter \DATA_WIDTH = 16
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Found cached RTLIL representation for module `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo'.
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2.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\lvds_rx'.
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Generating RTLIL representation for module `\lvds_rx'.
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Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:40.7-40.26.
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Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:52.11-52.32.
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Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:67.11-67.30.
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Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:73.13-73.40.
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Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:77.13-77.34.
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2.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\io_ctrl'.
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Generating RTLIL representation for module `\io_ctrl'.
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2.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sys_ctrl'.
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Generating RTLIL representation for module `\sys_ctrl'.
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2.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_if'.
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Generating RTLIL representation for module `\spi_if'.
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2.3.9. Analyzing design hierarchy..
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Top module: \top
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Used module: \smi_ctrl
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Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo
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Used module: \lvds_tx
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Used module: \lvds_rx
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Used module: \io_ctrl
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Used module: \sys_ctrl
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Used module: \spi_if
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2.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_slave'.
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Generating RTLIL representation for module `\spi_slave'.
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2.3.11. Analyzing design hierarchy..
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Top module: \top
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Used module: \smi_ctrl
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Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo
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Used module: \lvds_tx
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Used module: \lvds_rx
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Used module: \io_ctrl
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Used module: \sys_ctrl
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Used module: \spi_if
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Used module: \spi_slave
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2.3.12. Analyzing design hierarchy..
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Top module: \top
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Used module: \smi_ctrl
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Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo
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Used module: \lvds_tx
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Used module: \lvds_rx
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Used module: \io_ctrl
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Used module: \sys_ctrl
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Used module: \spi_if
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Used module: \spi_slave
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Removing unused module `$abstract\top'.
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Removing unused module `$abstract\complex_fifo'.
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Removing unused module `$abstract\lvds_tx'.
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Removing unused module `$abstract\lvds_rx'.
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Removing unused module `$abstract\smi_ctrl'.
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Removing unused module `$abstract\io_ctrl'.
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Removing unused module `$abstract\sys_ctrl'.
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Removing unused module `$abstract\spi_if'.
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Removing unused module `$abstract\spi_slave'.
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Removed 9 unused modules.
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2.4. Executing PROC pass (convert processes to netlists).
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2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 1 empty switch in `\io_ctrl.$proc$io_ctrl.v:111$577'.
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Cleaned up 1 empty switch.
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2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
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Marked 1 switch rules as full_case in process $proc$spi_slave.v:68$609 in module spi_slave.
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Marked 1 switch rules as full_case in process $proc$spi_slave.v:48$603 in module spi_slave.
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Marked 2 switch rules as full_case in process $proc$spi_slave.v:27$599 in module spi_slave.
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Marked 7 switch rules as full_case in process $proc$spi_if.v:56$592 in module spi_if.
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Marked 2 switch rules as full_case in process $proc$sys_ctrl.v:49$587 in module sys_ctrl.
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Marked 2 switch rules as full_case in process $proc$io_ctrl.v:209$583 in module io_ctrl.
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Marked 2 switch rules as full_case in process $proc$io_ctrl.v:111$577 in module io_ctrl.
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Marked 4 switch rules as full_case in process $proc$lvds_rx.v:37$567 in module lvds_rx.
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Marked 4 switch rules as full_case in process $proc$lvds_tx.v:28$558 in module lvds_tx.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:105$521 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:94$512 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:84$492 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:67$480 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:57$459 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 2 switch rules as full_case in process $proc$complex_fifo.v:41$447 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
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Marked 1 switch rules as full_case in process $proc$smi_ctrl.v:253$433 in module smi_ctrl.
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Marked 6 switch rules as full_case in process $proc$smi_ctrl.v:177$427 in module smi_ctrl.
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Marked 1 switch rules as full_case in process $proc$smi_ctrl.v:144$419 in module smi_ctrl.
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Marked 3 switch rules as full_case in process $proc$smi_ctrl.v:114$408 in module smi_ctrl.
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Marked 2 switch rules as full_case in process $proc$smi_ctrl.v:58$396 in module smi_ctrl.
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Marked 1 switch rules as full_case in process $proc$top.v:190$382 in module top.
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Removed a total of 0 dead cases.
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2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 20 redundant assignments.
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Promoted 60 assignments to connections.
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2.4.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
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Set init value: \Q = 1'0
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Found init rule in `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
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Set init value: \Q = 1'0
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Found init rule in `\spi_if.$proc$spi_if.v:0$598'.
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Set init value: \state_if = 3'000
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Found init rule in `\lvds_rx.$proc$lvds_rx.v:0$576'.
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Set init value: \r_state_if = 2'00
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Set init value: \r_phase_count = 3'111
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Found init rule in `\lvds_tx.$proc$lvds_tx.v:0$566'.
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Set init value: \r_phase_count = 5'11111
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2.4.5. Executing PROC_ARST pass (detect async resets in processes).
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Found async reset \S in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
|
|
Found async reset \R in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
|
|
Found async reset \S in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
|
|
Found async reset \R in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
|
|
Found async reset \S in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'.
|
|
Found async reset \R in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'.
|
|
Found async reset \S in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'.
|
|
Found async reset \R in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'.
|
|
Found async reset \i_rst_b in `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
Found async reset \i_rst_b in `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
Found async reset \i_rst_b in `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
Found async reset \i_rst_b in `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
Found async reset \i_rst_b in `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
|
|
2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~85 debug messages>
|
|
|
|
2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
|
|
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
|
|
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
|
|
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
|
|
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
|
|
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
|
|
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
|
|
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
|
|
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
|
|
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
|
|
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'.
|
|
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
|
|
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
|
|
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
|
|
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
|
|
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
|
|
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
|
|
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
|
|
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
|
|
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
|
|
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
|
|
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'.
|
|
Creating decoders for process `\spi_slave.$proc$spi_slave.v:68$609'.
|
|
1/3: $0\r_tx_bit_count[2:0]
|
|
2/3: $0\r_tx_byte[7:0]
|
|
3/3: $0\o_spi_miso[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$spi_slave.v:62$607'.
|
|
Creating decoders for process `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
1/2: $0\o_rx_data_valid[0:0]
|
|
2/2: $0\o_rx_byte[7:0]
|
|
Creating decoders for process `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
1/4: $0\r_rx_bit_count[2:0]
|
|
2/4: $0\r_rx_done[0:0]
|
|
3/4: $0\r_rx_byte[7:0]
|
|
4/4: $0\r_temp_rx_byte[7:0]
|
|
Creating decoders for process `\spi_if.$proc$spi_if.v:0$598'.
|
|
Creating decoders for process `\spi_if.$proc$spi_if.v:56$592'.
|
|
1/10: $3\o_ioc[4:0]
|
|
2/10: $2\o_ioc[4:0]
|
|
3/10: $1\o_ioc[4:0]
|
|
4/10: $0\r_tx_byte[7:0]
|
|
5/10: $0\r_tx_data_valid[0:0]
|
|
6/10: $0\state_if[2:0]
|
|
7/10: $0\o_load_cmd[0:0]
|
|
8/10: $0\o_fetch_cmd[0:0]
|
|
9/10: $0\o_cs[3:0]
|
|
10/10: $0\o_data_in[7:0]
|
|
Creating decoders for process `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
1/4: $0\debug_smi_test[0:0]
|
|
2/4: $0\debug_fifo_pull[0:0]
|
|
3/4: $0\debug_fifo_push[0:0]
|
|
4/4: $0\o_data_out[7:0]
|
|
Creating decoders for process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
1/8: $0\tr_vc_2_state[0:0]
|
|
2/8: $0\tr_vc_1_b_state[0:0]
|
|
3/8: $0\tr_vc_1_state[0:0]
|
|
4/8: $0\rx_h_b_state[0:0]
|
|
5/8: $0\rx_h_state[0:0]
|
|
6/8: $0\lna_tx_shutdown_state[0:0]
|
|
7/8: $0\lna_rx_shutdown_state[0:0]
|
|
8/8: $0\mixer_en_state[0:0]
|
|
Creating decoders for process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
1/15: $0\o_data_out[7:0] [6]
|
|
2/15: $0\o_data_out[7:0] [5]
|
|
3/15: $0\o_data_out[7:0] [3]
|
|
4/15: $0\o_data_out[7:0] [2]
|
|
5/15: $0\o_data_out[7:0] [0]
|
|
6/15: $0\o_data_out[7:0] [7]
|
|
7/15: $0\o_data_out[7:0] [4]
|
|
8/15: $0\o_data_out[7:0] [1]
|
|
9/15: $0\pmod_state[7:0]
|
|
10/15: $0\pmod_dir_state[7:0]
|
|
11/15: $0\led1_state[0:0]
|
|
12/15: $0\led0_state[0:0]
|
|
13/15: $0\rf_mode[2:0]
|
|
14/15: $0\debug_mode[1:0]
|
|
15/15: $0\rf_pin_state[7:0]
|
|
Creating decoders for process `\lvds_rx.$proc$lvds_rx.v:0$576'.
|
|
Creating decoders for process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
1/5: $0\r_sync_input[0:0]
|
|
2/5: $0\r_phase_count[2:0]
|
|
3/5: $0\r_state_if[1:0]
|
|
4/5: $0\o_fifo_data[31:0]
|
|
5/5: $0\o_fifo_push[0:0]
|
|
Creating decoders for process `\lvds_tx.$proc$lvds_tx.v:0$566'.
|
|
Creating decoders for process `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
1/4: $0\r_phase_count[4:0]
|
|
2/4: $0\o_fifo_pull[0:0]
|
|
3/4: $0\r_fifo_data[31:0]
|
|
4/4: $0\o_ddr_data[1:0]
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
1/24: $2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551
|
|
2/24: $2$memwr$\mem_i$complex_fifo.v:109$444_DATA[15:0]$550
|
|
3/24: $2$memwr$\mem_i$complex_fifo.v:109$444_ADDR[9:0]$549
|
|
4/24: $2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548
|
|
5/24: $2$memwr$\mem_q$complex_fifo.v:108$443_DATA[15:0]$547
|
|
6/24: $2$memwr$\mem_q$complex_fifo.v:108$443_ADDR[9:0]$546
|
|
7/24: $2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557
|
|
8/24: $2$memwr$\mem_i$complex_fifo.v:112$446_DATA[15:0]$556
|
|
9/24: $2$memwr$\mem_i$complex_fifo.v:112$446_ADDR[9:0]$555
|
|
10/24: $2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554
|
|
11/24: $2$memwr$\mem_q$complex_fifo.v:111$445_DATA[15:0]$553
|
|
12/24: $2$memwr$\mem_q$complex_fifo.v:111$445_ADDR[9:0]$552
|
|
13/24: $1$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$545
|
|
14/24: $1$memwr$\mem_i$complex_fifo.v:112$446_DATA[15:0]$544
|
|
15/24: $1$memwr$\mem_i$complex_fifo.v:112$446_ADDR[9:0]$543
|
|
16/24: $1$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$542
|
|
17/24: $1$memwr$\mem_q$complex_fifo.v:111$445_DATA[15:0]$541
|
|
18/24: $1$memwr$\mem_q$complex_fifo.v:111$445_ADDR[9:0]$540
|
|
19/24: $1$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$539
|
|
20/24: $1$memwr$\mem_i$complex_fifo.v:109$444_DATA[15:0]$538
|
|
21/24: $1$memwr$\mem_i$complex_fifo.v:109$444_ADDR[9:0]$537
|
|
22/24: $1$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$536
|
|
23/24: $1$memwr$\mem_q$complex_fifo.v:108$443_DATA[15:0]$535
|
|
24/24: $1$memwr$\mem_q$complex_fifo.v:108$443_ADDR[9:0]$534
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
1/6: $0\rd_data_o[31:0] [31:16]
|
|
2/6: $0\rd_data_o[31:0] [15:0]
|
|
3/6: $2$mem2bits$\mem_q$complex_fifo.v:99$441[15:0]$517
|
|
4/6: $1$mem2bits$\mem_i$complex_fifo.v:100$442[15:0]$516
|
|
5/6: $1$mem2bits$\mem_q$complex_fifo.v:99$441[15:0]$515
|
|
6/6: $2$mem2bits$\mem_i$complex_fifo.v:100$442[15:0]$518
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
1/9: $2\gray_conv$func$complex_fifo.v:88$439.$result[9:0]$502
|
|
2/9: $2\gray_conv$func$complex_fifo.v:88$439.in[9:0]$503
|
|
3/9: $2\gray_conv$func$complex_fifo.v:90$440.in[9:0]$505
|
|
4/9: $2\gray_conv$func$complex_fifo.v:90$440.$result[9:0]$504
|
|
5/9: $0\empty_o[0:0]
|
|
6/9: $1\gray_conv$func$complex_fifo.v:90$440.in[9:0]$501
|
|
7/9: $1\gray_conv$func$complex_fifo.v:90$440.$result[9:0]$500
|
|
8/9: $1\gray_conv$func$complex_fifo.v:88$439.in[9:0]$499
|
|
9/9: $1\gray_conv$func$complex_fifo.v:88$439.$result[9:0]$498
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'.
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
1/7: $2\gray_conv$func$complex_fifo.v:74$438.$result[9:0]$486
|
|
2/7: $2\gray_conv$func$complex_fifo.v:74$438.in[9:0]$487
|
|
3/7: $1\gray_conv$func$complex_fifo.v:74$438.in[9:0]$485
|
|
4/7: $1\gray_conv$func$complex_fifo.v:74$438.$result[9:0]$484
|
|
5/7: $0\debug_buffer[31:0]
|
|
6/7: $0\rd_addr_gray[9:0]
|
|
7/7: $0\rd_addr[9:0]
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
1/9: $2\gray_conv$func$complex_fifo.v:61$436.$result[9:0]$469
|
|
2/9: $2\gray_conv$func$complex_fifo.v:61$436.in[9:0]$470
|
|
3/9: $2\gray_conv$func$complex_fifo.v:63$437.in[9:0]$472
|
|
4/9: $2\gray_conv$func$complex_fifo.v:63$437.$result[9:0]$471
|
|
5/9: $0\full_o[0:0]
|
|
6/9: $1\gray_conv$func$complex_fifo.v:63$437.in[9:0]$468
|
|
7/9: $1\gray_conv$func$complex_fifo.v:63$437.$result[9:0]$467
|
|
8/9: $1\gray_conv$func$complex_fifo.v:61$436.in[9:0]$466
|
|
9/9: $1\gray_conv$func$complex_fifo.v:61$436.$result[9:0]$465
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'.
|
|
Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
1/6: $2\gray_conv$func$complex_fifo.v:47$435.$result[9:0]$453
|
|
2/6: $2\gray_conv$func$complex_fifo.v:47$435.in[9:0]$454
|
|
3/6: $1\gray_conv$func$complex_fifo.v:47$435.in[9:0]$452
|
|
4/6: $1\gray_conv$func$complex_fifo.v:47$435.$result[9:0]$451
|
|
5/6: $0\wr_addr_gray[9:0]
|
|
6/6: $0\wr_addr[9:0]
|
|
Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:253$433'.
|
|
1/2: $0\r_fifo_push_1[0:0]
|
|
2/2: $0\r_fifo_push[0:0]
|
|
Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
1/14: $0\r_fifo_pushed_data[31:0] [13:8]
|
|
2/14: $0\r_fifo_pushed_data[31:0] [7:0]
|
|
3/14: $0\r_fifo_pushed_data[31:0] [15:14]
|
|
4/14: $0\r_fifo_pushed_data[31:0] [16]
|
|
5/14: $0\r_fifo_pushed_data[31:0] [17]
|
|
6/14: $0\r_fifo_pushed_data[31:0] [24:18]
|
|
7/14: $0\r_fifo_pushed_data[31:0] [29:25]
|
|
8/14: $0\r_fifo_pushed_data[31:0] [31:30]
|
|
9/14: $0\cond_tx_ctrl[0:0]
|
|
10/14: $0\modem_tx_ctrl[0:0]
|
|
11/14: $0\tx_reg_state[1:0]
|
|
12/14: $0\w_fifo_push_trigger[0:0]
|
|
13/14: $0\o_cond_tx[0:0]
|
|
14/14: $0\o_tx_fifo_pushed_data[31:0]
|
|
Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:144$419'.
|
|
1/2: $0\r_fifo_pull_1[0:0]
|
|
2/2: $0\r_fifo_pull[0:0]
|
|
Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
1/5: $0\r_fifo_pulled_data[31:0]
|
|
2/5: $0\w_fifo_pull_trigger[0:0]
|
|
3/5: $0\r_smi_test_count[7:0]
|
|
4/5: $0\int_cnt_rx[4:0]
|
|
5/5: $0\o_smi_data_out[7:0]
|
|
Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
1/7: $0\o_data_out[7:0] [7:4]
|
|
2/7: $0\o_data_out[7:0] [3]
|
|
3/7: $0\o_data_out[7:0] [2]
|
|
4/7: $0\o_data_out[7:0] [1]
|
|
5/7: $0\o_data_out[7:0] [0]
|
|
6/7: $0\o_address_error[0:0]
|
|
7/7: $0\r_channel[0:0]
|
|
Creating decoders for process `\top.$proc$top.v:190$382'.
|
|
1/2: $0\r_counter[0:0]
|
|
2/2: $0\r_tx_data[7:0]
|
|
|
|
2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
|
|
2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
|
|
created $adff cell `$procdff$1747' with negative edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
|
|
created $dff cell `$procdff$1748' with negative edge clock.
|
|
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
|
|
created $adff cell `$procdff$1749' with negative edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
|
|
created $dff cell `$procdff$1750' with negative edge clock.
|
|
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
|
|
created $adff cell `$procdff$1751' with negative edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
|
|
created $dff cell `$procdff$1752' with negative edge clock.
|
|
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
|
|
created $adff cell `$procdff$1753' with negative edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'.
|
|
created $dff cell `$procdff$1754' with negative edge clock.
|
|
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'.
|
|
created $dff cell `$procdff$1755' with negative edge clock.
|
|
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'.
|
|
created $dff cell `$procdff$1756' with negative edge clock.
|
|
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'.
|
|
created $adff cell `$procdff$1757' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'.
|
|
created $dff cell `$procdff$1758' with positive edge clock.
|
|
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'.
|
|
created $adff cell `$procdff$1759' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'.
|
|
created $dff cell `$procdff$1760' with positive edge clock.
|
|
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'.
|
|
created $adff cell `$procdff$1761' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'.
|
|
created $dff cell `$procdff$1762' with positive edge clock.
|
|
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'.
|
|
created $adff cell `$procdff$1763' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'.
|
|
created $dff cell `$procdff$1764' with positive edge clock.
|
|
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'.
|
|
created $dff cell `$procdff$1765' with positive edge clock.
|
|
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'.
|
|
created $dff cell `$procdff$1766' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\o_spi_miso' using process `\spi_slave.$proc$spi_slave.v:68$609'.
|
|
created $dff cell `$procdff$1767' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_tx_byte' using process `\spi_slave.$proc$spi_slave.v:68$609'.
|
|
created $dff cell `$procdff$1768' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_tx_bit_count' using process `\spi_slave.$proc$spi_slave.v:68$609'.
|
|
created $dff cell `$procdff$1769' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\SCKr' using process `\spi_slave.$proc$spi_slave.v:62$607'.
|
|
created $dff cell `$procdff$1770' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\o_rx_data_valid' using process `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
created $dff cell `$procdff$1771' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\o_rx_byte' using process `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
created $dff cell `$procdff$1772' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r2_rx_done' using process `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
created $dff cell `$procdff$1773' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r3_rx_done' using process `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
created $dff cell `$procdff$1774' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_rx_bit_count' using process `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
created $dff cell `$procdff$1775' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_temp_rx_byte' using process `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
created $dff cell `$procdff$1776' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_rx_byte' using process `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
created $dff cell `$procdff$1777' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\r_rx_done' using process `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
created $dff cell `$procdff$1778' with positive edge clock.
|
|
Creating register for signal `\spi_if.\o_ioc' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1779' with positive edge clock.
|
|
Creating register for signal `\spi_if.\o_data_in' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1780' with positive edge clock.
|
|
Creating register for signal `\spi_if.\o_cs' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1781' with positive edge clock.
|
|
Creating register for signal `\spi_if.\o_fetch_cmd' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1782' with positive edge clock.
|
|
Creating register for signal `\spi_if.\o_load_cmd' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1783' with positive edge clock.
|
|
Creating register for signal `\spi_if.\state_if' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1784' with positive edge clock.
|
|
Creating register for signal `\spi_if.\r_tx_data_valid' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1785' with positive edge clock.
|
|
Creating register for signal `\spi_if.\r_tx_byte' using process `\spi_if.$proc$spi_if.v:56$592'.
|
|
created $dff cell `$procdff$1786' with positive edge clock.
|
|
Creating register for signal `\sys_ctrl.\o_data_out' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
created $adff cell `$procdff$1787' with positive edge clock and negative level reset.
|
|
Creating register for signal `\sys_ctrl.\debug_fifo_push' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
created $adff cell `$procdff$1788' with positive edge clock and negative level reset.
|
|
Creating register for signal `\sys_ctrl.\debug_fifo_pull' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
created $adff cell `$procdff$1789' with positive edge clock and negative level reset.
|
|
Creating register for signal `\sys_ctrl.\debug_smi_test' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
created $adff cell `$procdff$1790' with positive edge clock and negative level reset.
|
|
Creating register for signal `\io_ctrl.\mixer_en_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1793' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\lna_rx_shutdown_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1796' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\lna_tx_shutdown_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1799' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\rx_h_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1802' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\rx_h_b_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1805' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\tr_vc_1_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1808' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\tr_vc_1_b_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1811' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\tr_vc_2_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
created $dff cell `$procdff$1814' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\o_data_out' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $dff cell `$procdff$1817' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\debug_mode' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $adff cell `$procdff$1818' with positive edge clock and negative level reset.
|
|
Creating register for signal `\io_ctrl.\rf_mode' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $adff cell `$procdff$1819' with positive edge clock and negative level reset.
|
|
Creating register for signal `\io_ctrl.\led0_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $adff cell `$procdff$1820' with positive edge clock and negative level reset.
|
|
Creating register for signal `\io_ctrl.\led1_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $adff cell `$procdff$1821' with positive edge clock and negative level reset.
|
|
Creating register for signal `\io_ctrl.\pmod_dir_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $dff cell `$procdff$1824' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\pmod_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $dff cell `$procdff$1827' with positive edge clock.
|
|
Creating register for signal `\io_ctrl.\rf_pin_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
created $dff cell `$procdff$1830' with positive edge clock.
|
|
Creating register for signal `\lvds_rx.\o_fifo_push' using process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
created $adff cell `$procdff$1831' with positive edge clock and negative level reset.
|
|
Creating register for signal `\lvds_rx.\o_fifo_data' using process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
created $dff cell `$procdff$1834' with positive edge clock.
|
|
Creating register for signal `\lvds_rx.\r_state_if' using process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
created $adff cell `$procdff$1835' with positive edge clock and negative level reset.
|
|
Creating register for signal `\lvds_rx.\r_phase_count' using process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
created $adff cell `$procdff$1836' with positive edge clock and negative level reset.
|
|
Creating register for signal `\lvds_rx.\r_sync_input' using process `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
created $adff cell `$procdff$1837' with positive edge clock and negative level reset.
|
|
Creating register for signal `\lvds_tx.\o_ddr_data' using process `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
created $dff cell `$procdff$1838' with positive edge clock.
|
|
Creating register for signal `\lvds_tx.\o_fifo_pull' using process `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
created $dff cell `$procdff$1839' with positive edge clock.
|
|
Creating register for signal `\lvds_tx.\r_phase_count' using process `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
created $dff cell `$procdff$1840' with positive edge clock.
|
|
Creating register for signal `\lvds_tx.\r_fifo_data' using process `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
created $dff cell `$procdff$1841' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1842' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1843' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1844' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1845' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1846' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1847' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1848' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1849' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1850' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1851' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1852' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
created $dff cell `$procdff$1853' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_data_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
created $dff cell `$procdff$1854' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$mem2bits$\mem_q$complex_fifo.v:99$441' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
created $dff cell `$procdff$1855' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$mem2bits$\mem_i$complex_fifo.v:100$442' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
created $dff cell `$procdff$1856' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\empty_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
created $dff cell `$procdff$1857' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:88$439.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
created $dff cell `$procdff$1858' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:88$439.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
created $dff cell `$procdff$1859' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:90$440.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
created $dff cell `$procdff$1860' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:90$440.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
created $dff cell `$procdff$1861' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray_rd' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'.
|
|
created $dff cell `$procdff$1862' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray_rd_r' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'.
|
|
created $dff cell `$procdff$1863' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
created $dff cell `$procdff$1864' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
created $dff cell `$procdff$1865' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\debug_buffer' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
created $dff cell `$procdff$1866' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:74$438.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
created $dff cell `$procdff$1867' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:74$438.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
created $dff cell `$procdff$1868' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\full_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
created $dff cell `$procdff$1869' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:61$436.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
created $dff cell `$procdff$1870' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:61$436.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
created $dff cell `$procdff$1871' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:63$437.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
created $dff cell `$procdff$1872' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:63$437.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
created $dff cell `$procdff$1873' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray_wr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'.
|
|
created $dff cell `$procdff$1874' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray_wr_r' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'.
|
|
created $dff cell `$procdff$1875' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
created $dff cell `$procdff$1876' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
created $dff cell `$procdff$1877' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:47$435.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
created $dff cell `$procdff$1878' with positive edge clock.
|
|
Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:47$435.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
created $dff cell `$procdff$1879' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_push' using process `\smi_ctrl.$proc$smi_ctrl.v:253$433'.
|
|
created $dff cell `$procdff$1880' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_push_1' using process `\smi_ctrl.$proc$smi_ctrl.v:253$433'.
|
|
created $dff cell `$procdff$1881' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\o_tx_fifo_pushed_data' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1882' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\o_cond_tx' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1883' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_pushed_data' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1884' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\tx_reg_state' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1885' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\modem_tx_ctrl' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1886' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\cond_tx_ctrl' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1887' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\w_fifo_push_trigger' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
created $dff cell `$procdff$1888' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_pull' using process `\smi_ctrl.$proc$smi_ctrl.v:144$419'.
|
|
created $dff cell `$procdff$1889' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_pull_1' using process `\smi_ctrl.$proc$smi_ctrl.v:144$419'.
|
|
created $dff cell `$procdff$1890' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\o_smi_data_out' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
created $dff cell `$procdff$1891' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\int_cnt_rx' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
created $dff cell `$procdff$1892' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_smi_test_count' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
created $dff cell `$procdff$1893' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\w_fifo_pull_trigger' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
created $dff cell `$procdff$1894' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\r_fifo_pulled_data' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
created $dff cell `$procdff$1895' with negative edge clock.
|
|
Creating register for signal `\smi_ctrl.\o_data_out' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
created $dff cell `$procdff$1898' with positive edge clock.
|
|
Creating register for signal `\smi_ctrl.\o_address_error' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
created $adff cell `$procdff$1899' with positive edge clock and negative level reset.
|
|
Creating register for signal `\smi_ctrl.\r_channel' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
created $dff cell `$procdff$1902' with positive edge clock.
|
|
Creating register for signal `\top.\r_counter' using process `\top.$proc$top.v:190$382'.
|
|
created $dff cell `$procdff$1903' with positive edge clock.
|
|
Creating register for signal `\top.\r_tx_data' using process `\top.$proc$top.v:190$382'.
|
|
created $dff cell `$procdff$1904' with positive edge clock.
|
|
|
|
2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
|
|
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
|
|
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'.
|
|
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
|
|
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
|
|
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
|
|
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
|
|
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'.
|
|
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
|
|
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
|
|
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'.
|
|
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
|
|
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
|
|
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
|
|
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'.
|
|
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
|
|
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'.
|
|
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'.
|
|
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'.
|
|
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'.
|
|
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'.
|
|
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'.
|
|
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'.
|
|
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'.
|
|
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'.
|
|
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'.
|
|
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'.
|
|
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'.
|
|
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'.
|
|
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'.
|
|
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'.
|
|
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'.
|
|
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'.
|
|
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'.
|
|
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'.
|
|
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'.
|
|
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'.
|
|
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'.
|
|
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'.
|
|
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'.
|
|
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'.
|
|
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'.
|
|
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'.
|
|
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'.
|
|
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'.
|
|
Found and cleaned up 3 empty switches in `\spi_slave.$proc$spi_slave.v:68$609'.
|
|
Removing empty process `spi_slave.$proc$spi_slave.v:68$609'.
|
|
Removing empty process `spi_slave.$proc$spi_slave.v:62$607'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$spi_slave.v:48$603'.
|
|
Removing empty process `spi_slave.$proc$spi_slave.v:48$603'.
|
|
Found and cleaned up 3 empty switches in `\spi_slave.$proc$spi_slave.v:27$599'.
|
|
Removing empty process `spi_slave.$proc$spi_slave.v:27$599'.
|
|
Removing empty process `spi_if.$proc$spi_if.v:0$598'.
|
|
Found and cleaned up 7 empty switches in `\spi_if.$proc$spi_if.v:56$592'.
|
|
Removing empty process `spi_if.$proc$spi_if.v:56$592'.
|
|
Found and cleaned up 5 empty switches in `\sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
Removing empty process `sys_ctrl.$proc$sys_ctrl.v:49$587'.
|
|
Found and cleaned up 3 empty switches in `\io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
Removing empty process `io_ctrl.$proc$io_ctrl.v:209$583'.
|
|
Found and cleaned up 5 empty switches in `\io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
Removing empty process `io_ctrl.$proc$io_ctrl.v:111$577'.
|
|
Removing empty process `lvds_rx.$proc$lvds_rx.v:0$576'.
|
|
Found and cleaned up 5 empty switches in `\lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
Removing empty process `lvds_rx.$proc$lvds_rx.v:37$567'.
|
|
Removing empty process `lvds_tx.$proc$lvds_tx.v:0$566'.
|
|
Found and cleaned up 4 empty switches in `\lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
Removing empty process `lvds_tx.$proc$lvds_tx.v:28$558'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'.
|
|
Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'.
|
|
Found and cleaned up 1 empty switch in `\smi_ctrl.$proc$smi_ctrl.v:253$433'.
|
|
Removing empty process `smi_ctrl.$proc$smi_ctrl.v:253$433'.
|
|
Found and cleaned up 6 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
Removing empty process `smi_ctrl.$proc$smi_ctrl.v:177$427'.
|
|
Found and cleaned up 1 empty switch in `\smi_ctrl.$proc$smi_ctrl.v:144$419'.
|
|
Removing empty process `smi_ctrl.$proc$smi_ctrl.v:144$419'.
|
|
Found and cleaned up 4 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
Removing empty process `smi_ctrl.$proc$smi_ctrl.v:114$408'.
|
|
Found and cleaned up 5 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
Removing empty process `smi_ctrl.$proc$smi_ctrl.v:58$396'.
|
|
Found and cleaned up 2 empty switches in `\top.$proc$top.v:190$382'.
|
|
Removing empty process `top.$proc$top.v:190$382'.
|
|
Cleaned up 85 empty switches.
|
|
|
|
2.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_slave.
|
|
<suppressed ~3 debug messages>
|
|
Optimizing module spi_if.
|
|
<suppressed ~20 debug messages>
|
|
Optimizing module sys_ctrl.
|
|
<suppressed ~5 debug messages>
|
|
Optimizing module io_ctrl.
|
|
<suppressed ~23 debug messages>
|
|
Optimizing module lvds_rx.
|
|
<suppressed ~8 debug messages>
|
|
Optimizing module lvds_tx.
|
|
<suppressed ~5 debug messages>
|
|
Optimizing module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
|
|
<suppressed ~35 debug messages>
|
|
Optimizing module smi_ctrl.
|
|
<suppressed ~59 debug messages>
|
|
Optimizing module top.
|
|
<suppressed ~10 debug messages>
|
|
|
|
2.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module spi_slave.
|
|
Deleting now unused module spi_if.
|
|
Deleting now unused module sys_ctrl.
|
|
Deleting now unused module io_ctrl.
|
|
Deleting now unused module lvds_rx.
|
|
Deleting now unused module lvds_tx.
|
|
Deleting now unused module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.
|
|
Deleting now unused module smi_ctrl.
|
|
<suppressed ~10 debug messages>
|
|
|
|
2.6. Executing TRIBUF pass.
|
|
|
|
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
Demoting inout port top.io_pmod to input.
|
|
|
|
2.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~57 debug messages>
|
|
|
|
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 208 unused cells and 969 unused wires.
|
|
<suppressed ~235 debug messages>
|
|
|
|
2.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module top...
|
|
Found and reported 0 problems.
|
|
|
|
2.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~474 debug messages>
|
|
Removed a total of 158 cells.
|
|
|
|
2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1214.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1232.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1250.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1256.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1262.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1268.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1274.
|
|
dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1280.
|
|
dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$707.
|
|
dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$710.
|
|
dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$716.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1214.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1232.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1250.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1256.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1262.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1268.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1274.
|
|
dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1280.
|
|
Removed 19 multiplexer ports.
|
|
<suppressed ~105 debug messages>
|
|
|
|
2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
New ctrl vector for $pmux cell $flatten\lvds_rx_09_inst.$procmux$1180: { $auto$opt_reduce.cc:134:opt_pmux$1912 $flatten\lvds_rx_09_inst.$procmux$1144_CMP }
|
|
New ctrl vector for $pmux cell $flatten\lvds_rx_24_inst.$procmux$1180: { $auto$opt_reduce.cc:134:opt_pmux$1914 $flatten\lvds_rx_24_inst.$procmux$1144_CMP }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$869: { $auto$opt_reduce.cc:134:opt_pmux$1918 $auto$opt_reduce.cc:134:opt_pmux$1916 }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$941: { $auto$opt_reduce.cc:134:opt_pmux$1922 $auto$opt_reduce.cc:134:opt_pmux$1920 }
|
|
Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1283:
|
|
Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533
|
|
New ports: A=1'0, B=1'1, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0]
|
|
New connections: $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [15:1] = { $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1292:
|
|
Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530
|
|
New ports: A=1'0, B=1'1, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0]
|
|
New connections: $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [15:1] = { $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1301:
|
|
Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527
|
|
New connections: $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 = 16'0000000000000000
|
|
Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1310:
|
|
Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524
|
|
New connections: $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 = 16'0000000000000000
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$881: { $auto$opt_reduce.cc:134:opt_pmux$1926 $auto$opt_reduce.cc:134:opt_pmux$1924 }
|
|
New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1614: { $flatten\smi_ctrl_ins.$procmux$1557_CMP $auto$opt_reduce.cc:134:opt_pmux$1928 $flatten\smi_ctrl_ins.$procmux$1595_CMP }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$893: { $auto$opt_reduce.cc:134:opt_pmux$1932 $auto$opt_reduce.cc:134:opt_pmux$1930 }
|
|
New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1687: $auto$opt_reduce.cc:134:opt_pmux$1934
|
|
New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1695: $auto$opt_reduce.cc:134:opt_pmux$1936
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$905: { $auto$opt_reduce.cc:134:opt_pmux$1940 $auto$opt_reduce.cc:134:opt_pmux$1938 }
|
|
New ctrl vector for $pmux cell $flatten\spi_if_ins.$procmux$758: { $flatten\spi_if_ins.$procmux$706_CMP $auto$opt_reduce.cc:134:opt_pmux$1942 }
|
|
New ctrl vector for $pmux cell $flatten\spi_if_ins.$procmux$778: { $flatten\spi_if_ins.$procmux$760_CMP $auto$opt_reduce.cc:134:opt_pmux$1944 }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$917: { $auto$opt_reduce.cc:134:opt_pmux$1948 $auto$opt_reduce.cc:134:opt_pmux$1946 }
|
|
New ctrl vector for $pmux cell $flatten\sys_ctrl_ins.$procmux$857: { $auto$opt_reduce.cc:134:opt_pmux$1950 $flatten\io_ctrl_ins.$procmux$1000_CMP }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$929: { $auto$opt_reduce.cc:134:opt_pmux$1954 $auto$opt_reduce.cc:134:opt_pmux$1952 }
|
|
New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$953: { $auto$opt_reduce.cc:134:opt_pmux$1958 $auto$opt_reduce.cc:134:opt_pmux$1956 }
|
|
Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1283:
|
|
Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533
|
|
New ports: A=1'0, B=1'1, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0]
|
|
New connections: $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [15:1] = { $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1292:
|
|
Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530
|
|
New ports: A=1'0, B=1'1, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0]
|
|
New connections: $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [15:1] = { $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1301:
|
|
Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527
|
|
New connections: $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 = 16'0000000000000000
|
|
Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1310:
|
|
Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524
|
|
New connections: $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 = 16'0000000000000000
|
|
Optimizing cells in module \top.
|
|
Performed a total of 24 changes.
|
|
|
|
2.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~36 debug messages>
|
|
Removed a total of 12 cells.
|
|
|
|
2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 202 unused wires.
|
|
<suppressed ~10 debug messages>
|
|
|
|
2.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~97 debug messages>
|
|
|
|
2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1614: { $auto$opt_reduce.cc:134:opt_pmux$1928 $auto$opt_reduce.cc:134:opt_pmux$1960 }
|
|
Optimizing cells in module \top.
|
|
Performed a total of 1 changes.
|
|
|
|
2.11.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.11.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.11.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~97 debug messages>
|
|
|
|
2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.11.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.11.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.11.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking top.lvds_rx_09_inst.r_state_if as FSM state register:
|
|
Register has an initialization value.
|
|
Not marking top.lvds_rx_24_inst.r_state_if as FSM state register:
|
|
Register has an initialization value.
|
|
Found FSM state register top.smi_ctrl_ins.tx_reg_state.
|
|
Not marking top.spi_if_ins.o_cs as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking top.spi_if_ins.state_if as FSM state register:
|
|
Register has an initialization value.
|
|
Not marking top.sys_ctrl_ins.o_data_out as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\smi_ctrl_ins.tx_reg_state' from module `\top'.
|
|
found $dff cell for state register: $flatten\smi_ctrl_ins.$procdff$1885
|
|
root of input selection tree: $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \i_rst_b
|
|
found state code: 2'00
|
|
found ctrl input: $flatten\smi_ctrl_ins.$procmux$1595_CMP
|
|
found ctrl input: $flatten\smi_ctrl_ins.$procmux$1506_CMP
|
|
found ctrl input: $flatten\smi_ctrl_ins.$procmux$1546_CMP
|
|
found ctrl input: $flatten\smi_ctrl_ins.$procmux$1557_CMP
|
|
found ctrl input: \smi_ctrl_ins.i_smi_data_in [7]
|
|
found state code: 2'11
|
|
found state code: 2'10
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\smi_ctrl_ins.$procmux$1595_CMP
|
|
found ctrl output: $flatten\smi_ctrl_ins.$procmux$1557_CMP
|
|
found ctrl output: $flatten\smi_ctrl_ins.$procmux$1546_CMP
|
|
found ctrl output: $flatten\smi_ctrl_ins.$procmux$1506_CMP
|
|
ctrl inputs: { \smi_ctrl_ins.i_smi_data_in [7] \i_rst_b }
|
|
ctrl outputs: { $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] $flatten\smi_ctrl_ins.$procmux$1506_CMP $flatten\smi_ctrl_ins.$procmux$1546_CMP $flatten\smi_ctrl_ins.$procmux$1557_CMP $flatten\smi_ctrl_ins.$procmux$1595_CMP }
|
|
transition: 2'00 2'-0 -> 2'00 6'000010
|
|
transition: 2'00 2'01 -> 2'00 6'000010
|
|
transition: 2'00 2'11 -> 2'01 6'010010
|
|
transition: 2'10 2'-0 -> 2'00 6'001000
|
|
transition: 2'10 2'01 -> 2'11 6'111000
|
|
transition: 2'10 2'11 -> 2'00 6'001000
|
|
transition: 2'01 2'-0 -> 2'00 6'000100
|
|
transition: 2'01 2'01 -> 2'10 6'100100
|
|
transition: 2'01 2'11 -> 2'00 6'000100
|
|
transition: 2'11 2'-0 -> 2'00 6'000001
|
|
transition: 2'11 2'-1 -> 2'00 6'000001
|
|
|
|
2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'.
|
|
Merging pattern 2'-0 and 2'-1 from group (3 0 6'000001).
|
|
Merging pattern 2'-1 and 2'-0 from group (3 0 6'000001).
|
|
|
|
2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 10 unused cells and 10 unused wires.
|
|
<suppressed ~11 debug messages>
|
|
|
|
2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'.
|
|
Removing unused output signal $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] [0].
|
|
Removing unused output signal $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] [1].
|
|
|
|
2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> ---1
|
|
10 -> --1-
|
|
01 -> -1--
|
|
11 -> 1---
|
|
|
|
2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\smi_ctrl_ins.tx_reg_state$1961 (\smi_ctrl_ins.tx_reg_state):
|
|
|
|
Number of input signals: 2
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: \i_rst_b
|
|
1: \smi_ctrl_ins.i_smi_data_in [7]
|
|
|
|
Output signals:
|
|
0: $flatten\smi_ctrl_ins.$procmux$1595_CMP
|
|
1: $flatten\smi_ctrl_ins.$procmux$1557_CMP
|
|
2: $flatten\smi_ctrl_ins.$procmux$1546_CMP
|
|
3: $flatten\smi_ctrl_ins.$procmux$1506_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 2'-0 -> 0 4'0010
|
|
1: 0 2'01 -> 0 4'0010
|
|
2: 0 2'11 -> 2 4'0010
|
|
3: 1 2'-0 -> 0 4'1000
|
|
4: 1 2'11 -> 0 4'1000
|
|
5: 1 2'01 -> 3 4'1000
|
|
6: 2 2'-0 -> 0 4'0100
|
|
7: 2 2'11 -> 0 4'0100
|
|
8: 2 2'01 -> 1 4'0100
|
|
9: 3 2'-- -> 0 4'0001
|
|
|
|
-------------------------------------
|
|
|
|
2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~96 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $procdff$1904 ($dff) from module top (D = $procmux$1738_Y, Q = \r_tx_data).
|
|
Adding SRST signal on $procdff$1903 ($dff) from module top (D = $logic_not$top.v:194$384_Y, Q = \r_counter, rval = 1'0).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1877 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1484_Y, Q = \tx_fifo.wr_addr_gray, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2002 ($sdff) from module top (D = { $flatten\tx_fifo.$add$complex_fifo.v:46$455_Y [9] $flatten\tx_fifo.$xor$complex_fifo.v:37$457_Y }, Q = \tx_fifo.wr_addr_gray).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1876 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1490_Y, Q = \tx_fifo.wr_addr, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2004 ($sdff) from module top (D = $flatten\tx_fifo.$add$complex_fifo.v:46$455_Y, Q = \tx_fifo.wr_addr).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1869 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1448_Y, Q = \tx_fifo.full_o, rval = 1'0).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1865 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1412_Y, Q = \tx_fifo.rd_addr_gray, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2007 ($sdff) from module top (D = { $flatten\tx_fifo.$add$complex_fifo.v:73$488_Y [9] $flatten\tx_fifo.$xor$complex_fifo.v:37$490_Y }, Q = \tx_fifo.rd_addr_gray).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1864 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1418_Y, Q = \tx_fifo.rd_addr, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2009 ($sdff) from module top (D = $flatten\tx_fifo.$add$complex_fifo.v:73$488_Y, Q = \tx_fifo.rd_addr).
|
|
Adding SRST signal on $flatten\tx_fifo.$procdff$1857 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1373_Y, Q = \tx_fifo.empty_o, rval = 1'1).
|
|
Adding EN signal on $flatten\tx_fifo.$procdff$1854 ($dff) from module top (D = { $flatten\tx_fifo.$memrd$\mem_i$complex_fifo.v:100$520_DATA $flatten\tx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA }, Q = \tx_fifo.rd_data_o).
|
|
Adding EN signal on $flatten\sys_ctrl_ins.$procdff$1787 ($adff) from module top (D = $flatten\sys_ctrl_ins.$procmux$857_Y, Q = \sys_ctrl_ins.o_data_out).
|
|
Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1778 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$687_Y, Q = \spi_if_ins.spi.r_rx_done, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2018 ($sdff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$687_Y, Q = \spi_if_ins.spi.r_rx_done).
|
|
Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1777 ($dff) from module top (D = { \spi_if_ins.spi.r_temp_rx_byte [6:0] \i_mosi }, Q = \spi_if_ins.spi.r_rx_byte).
|
|
Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1776 ($dff) from module top (D = { \spi_if_ins.spi.r_temp_rx_byte [6:0] \i_mosi }, Q = \spi_if_ins.spi.r_temp_rx_byte).
|
|
Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1775 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600_Y [2:0], Q = \spi_if_ins.spi.r_rx_bit_count, rval = 3'000).
|
|
Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1772 ($dff) from module top (D = \spi_if_ins.spi.r_rx_byte, Q = \spi_if_ins.spi.o_rx_byte).
|
|
Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1769 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$658_Y, Q = \spi_if_ins.spi.r_tx_bit_count, rval = 3'110).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2030 ($sdff) from module top (D = $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611_Y [2:0], Q = \spi_if_ins.spi.r_tx_bit_count).
|
|
Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1768 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$0\r_tx_byte[7:0], Q = \spi_if_ins.spi.r_tx_byte).
|
|
Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1767 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$0\o_spi_miso[0:0], Q = \spi_if_ins.spi.o_spi_miso).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1786 ($dff) from module top (D = \r_tx_data, Q = \spi_if_ins.r_tx_byte).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1785 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$745_Y, Q = \spi_if_ins.r_tx_data_valid).
|
|
Adding SRST signal on $flatten\spi_if_ins.$procdff$1784 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$765_Y, Q = \spi_if_ins.state_if, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2056 ($sdff) from module top (D = $flatten\spi_if_ins.$procmux$765_Y, Q = \spi_if_ins.state_if).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1783 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$782_Y, Q = \spi_if_ins.o_load_cmd).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1782 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$798_Y, Q = \spi_if_ins.o_fetch_cmd).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1781 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$807_Y, Q = \spi_if_ins.o_cs).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1780 ($dff) from module top (D = \spi_if_ins.spi.o_rx_byte, Q = \spi_if_ins.o_data_in).
|
|
Adding EN signal on $flatten\spi_if_ins.$procdff$1779 ($dff) from module top (D = \spi_if_ins.spi.o_rx_byte [4:0], Q = \spi_if_ins.o_ioc).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1902 ($dff) from module top (D = \spi_if_ins.o_data_in [0], Q = \smi_ctrl_ins.r_channel).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1898 ($dff) from module top (D = 5'00000, Q = \smi_ctrl_ins.o_data_out [7:3]).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1898 ($dff) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1703_Y $flatten\smi_ctrl_ins.$procmux$1711_Y $flatten\smi_ctrl_ins.$procmux$1719_Y }, Q = \smi_ctrl_ins.o_data_out [2:0]).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1895 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1651_Y, Q = \smi_ctrl_ins.r_fifo_pulled_data, rval = 0).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2104 ($sdff) from module top (D = \rx_fifo.rd_data_o, Q = \smi_ctrl_ins.r_fifo_pulled_data).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1894 ($dff) from module top (D = $flatten\smi_ctrl_ins.$eq$smi_ctrl.v:122$410_Y, Q = \smi_ctrl_ins.w_fifo_pull_trigger).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1892 ($dff) from module top (D = $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416_Y [4:0], Q = \smi_ctrl_ins.int_cnt_rx, rval = 5'00000).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1891 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1681_Y, Q = \smi_ctrl_ins.o_smi_data_out).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1890 ($dff) from module top (D = \smi_ctrl_ins.r_fifo_pull, Q = \smi_ctrl_ins.r_fifo_pull_1, rval = 1'0).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1889 ($dff) from module top (D = \smi_ctrl_ins.w_fifo_pull_trigger, Q = \smi_ctrl_ins.r_fifo_pull, rval = 1'0).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1888 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1614_Y, Q = \smi_ctrl_ins.w_fifo_push_trigger, rval = 1'0).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1886 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1589_Y, Q = \smi_ctrl_ins.modem_tx_ctrl, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2112 ($sdff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1587_Y, Q = \smi_ctrl_ins.modem_tx_ctrl).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1884 ($dff) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1567_Y $flatten\smi_ctrl_ins.$procmux$1556_Y $flatten\smi_ctrl_ins.$procmux$1545_Y $flatten\smi_ctrl_ins.$procmux$1535_Y $flatten\smi_ctrl_ins.$procmux$1526_Y $flatten\smi_ctrl_ins.$procmux$1517_Y $flatten\smi_ctrl_ins.$procmux$1505_Y }, Q = \smi_ctrl_ins.r_fifo_pushed_data [31:8], rval = 24'000000000000000000000000).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1884 ($dff) from module top (D = 8'00000000, Q = \smi_ctrl_ins.r_fifo_pushed_data [7:0]).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = { 2'10 \smi_ctrl_ins.i_smi_data_in [4:0] }, Q = \smi_ctrl_ins.r_fifo_pushed_data [31:25]).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = \smi_ctrl_ins.i_smi_data_in [6:0], Q = \smi_ctrl_ins.r_fifo_pushed_data [24:18]).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = { \smi_ctrl_ins.i_smi_data_in [6] \smi_ctrl_ins.modem_tx_ctrl 2'01 \smi_ctrl_ins.i_smi_data_in [5:0] }, Q = \smi_ctrl_ins.r_fifo_pushed_data [17:8]).
|
|
Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1882 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1636_Y, Q = \smi_ctrl_ins.o_tx_fifo_pushed_data).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1881 ($dff) from module top (D = \smi_ctrl_ins.r_fifo_push, Q = \smi_ctrl_ins.r_fifo_push_1, rval = 1'0).
|
|
Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1880 ($dff) from module top (D = \smi_ctrl_ins.w_fifo_push_trigger, Q = \smi_ctrl_ins.r_fifo_push, rval = 1'0).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1877 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1484_Y, Q = \rx_fifo.wr_addr_gray, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2139 ($sdff) from module top (D = { $flatten\rx_fifo.$add$complex_fifo.v:46$455_Y [9] $flatten\rx_fifo.$xor$complex_fifo.v:37$457_Y }, Q = \rx_fifo.wr_addr_gray).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1876 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1490_Y, Q = \rx_fifo.wr_addr, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2141 ($sdff) from module top (D = $flatten\rx_fifo.$add$complex_fifo.v:46$455_Y, Q = \rx_fifo.wr_addr).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1869 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1448_Y, Q = \rx_fifo.full_o, rval = 1'0).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1865 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1412_Y, Q = \rx_fifo.rd_addr_gray, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2144 ($sdff) from module top (D = { $flatten\rx_fifo.$add$complex_fifo.v:73$488_Y [9] $flatten\rx_fifo.$xor$complex_fifo.v:37$490_Y }, Q = \rx_fifo.rd_addr_gray).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1864 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1418_Y, Q = \rx_fifo.rd_addr, rval = 10'0000000000).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2146 ($sdff) from module top (D = $flatten\rx_fifo.$add$complex_fifo.v:73$488_Y, Q = \rx_fifo.rd_addr).
|
|
Adding SRST signal on $flatten\rx_fifo.$procdff$1857 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1373_Y, Q = \rx_fifo.empty_o, rval = 1'1).
|
|
Adding EN signal on $flatten\rx_fifo.$procdff$1854 ($dff) from module top (D = { $flatten\rx_fifo.$memrd$\mem_i$complex_fifo.v:100$520_DATA $flatten\rx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA }, Q = \rx_fifo.rd_data_o).
|
|
Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1841 ($dff) from module top (D = $flatten\lvds_tx_inst.$procmux$1202_Y, Q = \lvds_tx_inst.r_fifo_data, rval = 0).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2150 ($sdff) from module top (D = $flatten\lvds_tx_inst.$procmux$1197_Y, Q = \lvds_tx_inst.r_fifo_data).
|
|
Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1840 ($dff) from module top (D = $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565_Y [4:0], Q = \lvds_tx_inst.r_phase_count, rval = 5'11111).
|
|
Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1839 ($dff) from module top (D = $flatten\lvds_tx_inst.$not$lvds_tx.v:35$561_Y, Q = \lvds_tx_inst.o_fifo_pull, rval = 1'0).
|
|
Adding EN signal on $flatten\lvds_tx_inst.$procdff$1838 ($dff) from module top (D = $flatten\lvds_tx_inst.$shiftx$lvds_tx.v:0$564_Y, Q = \lvds_tx_inst.o_ddr_data).
|
|
Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1836 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\r_phase_count[2:0], Q = \lvds_rx_24_inst.r_phase_count).
|
|
Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1835 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\r_state_if[1:0], Q = \lvds_rx_24_inst.r_state_if).
|
|
Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1834 ($dff) from module top (D = $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0], Q = \lvds_rx_24_inst.o_fifo_data).
|
|
Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1831 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\o_fifo_push[0:0], Q = \lvds_rx_24_inst.o_fifo_push).
|
|
Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1836 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\r_phase_count[2:0], Q = \lvds_rx_09_inst.r_phase_count).
|
|
Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1835 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\r_state_if[1:0], Q = \lvds_rx_09_inst.r_state_if).
|
|
Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1834 ($dff) from module top (D = $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0], Q = \lvds_rx_09_inst.o_fifo_data).
|
|
Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1831 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\o_fifo_push[0:0], Q = \lvds_rx_09_inst.o_fifo_push).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1830 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.rf_pin_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1827 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.pmod_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1824 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.pmod_dir_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1821 ($adff) from module top (D = \spi_if_ins.o_data_in [1], Q = \io_ctrl_ins.led1_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1820 ($adff) from module top (D = \spi_if_ins.o_data_in [0], Q = \io_ctrl_ins.led0_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1819 ($adff) from module top (D = \spi_if_ins.o_data_in [4:2], Q = \io_ctrl_ins.rf_mode).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1818 ($adff) from module top (D = \spi_if_ins.o_data_in [1:0], Q = \io_ctrl_ins.debug_mode).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = { $flatten\io_ctrl_ins.$procmux$1031_Y $flatten\io_ctrl_ins.$procmux$985_Y $flatten\io_ctrl_ins.$procmux$1043_Y $flatten\io_ctrl_ins.$procmux$1008_Y }, Q = { \io_ctrl_ins.o_data_out [4:3] \io_ctrl_ins.o_data_out [1:0] }).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = { $flatten\io_ctrl_ins.$procmux$1020_Y $flatten\io_ctrl_ins.$procmux$963_Y $flatten\io_ctrl_ins.$procmux$974_Y }, Q = \io_ctrl_ins.o_data_out [7:5]).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = $flatten\io_ctrl_ins.$procmux$997_Y, Q = \io_ctrl_ins.o_data_out [2]).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1814 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_2_state[0:0], Q = \io_ctrl_ins.tr_vc_2_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1811 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_1_b_state[0:0], Q = \io_ctrl_ins.tr_vc_1_b_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1808 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_1_state[0:0], Q = \io_ctrl_ins.tr_vc_1_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1805 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\rx_h_b_state[0:0], Q = \io_ctrl_ins.rx_h_b_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1802 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\rx_h_state[0:0], Q = \io_ctrl_ins.rx_h_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1799 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\lna_tx_shutdown_state[0:0], Q = \io_ctrl_ins.lna_tx_shutdown_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1796 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\lna_rx_shutdown_state[0:0], Q = \io_ctrl_ins.lna_rx_shutdown_state).
|
|
Adding EN signal on $flatten\io_ctrl_ins.$procdff$1793 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\mixer_en_state[0:0], Q = \io_ctrl_ins.mixer_en_state).
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2117 ($sdffe) from module top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2125 ($sdffe) from module top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2096 ($dffe) from module top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2096 ($dffe) from module top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2096 ($dffe) from module top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2096 ($dffe) from module top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2096 ($dffe) from module top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2116 ($dffe) from module top.
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 173 unused cells and 164 unused wires.
|
|
<suppressed ~174 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~28 debug messages>
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~57 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~102 debug messages>
|
|
Removed a total of 34 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 34 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.13.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~58 debug messages>
|
|
|
|
2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.13.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.13.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 1 bits (of 4) from port B of cell top.$procmux$1741_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell top.$procmux$1742_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell top.$procmux$1743_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.\spi.$eq$spi_slave.v:38$602 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\spi_if_ins.\spi.$eq$spi_slave.v:63$608 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub).
|
|
Removed top 29 bits (of 32) from port Y of cell top.$flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub).
|
|
Removed top 1 bits (of 8) from FF cell top.$auto$ff.cc:266:slice$2027 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\spi_if_ins.$procmux$810_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from mux cell top.$flatten\spi_if_ins.$procmux$762 ($mux).
|
|
Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$procmux$760_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$eq$spi_if.v:99$597 ($eq).
|
|
Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$eq$spi_if.v:96$596 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add).
|
|
Removed top 29 bits (of 32) from port Y of cell top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2036 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$1993 ($eq).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2079 ($ne).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2070 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2066 ($ne).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2061 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2053 ($ne).
|
|
Removed top 3 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1012_CMP0 ($eq).
|
|
Removed top 2 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1010_CMP0 ($eq).
|
|
Removed top 2 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1009_CMP0 ($eq).
|
|
Removed top 4 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1001_CMP0 ($eq).
|
|
Removed top 3 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1000_CMP0 ($eq).
|
|
Removed top 2 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$874_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$873_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$872_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\io_ctrl_ins.$eq$io_ctrl.v:297$586 ($eq).
|
|
Removed top 31 bits (of 32) from mux cell top.$flatten\lvds_rx_09_inst.$procmux$1169 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_09_inst.$procmux$1151_CMP0 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
Removed top 29 bits (of 32) from port Y of cell top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_09_inst.$eq$lvds_rx.v:57$571 ($eq).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2310 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2315 ($ne).
|
|
Removed top 31 bits (of 32) from mux cell top.$flatten\lvds_rx_24_inst.$procmux$1169 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_24_inst.$procmux$1151_CMP0 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
Removed top 29 bits (of 32) from port Y of cell top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_24_inst.$eq$lvds_rx.v:57$571 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2178 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2176 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2174 ($ne).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2275 ($ne).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
Removed top 22 bits (of 32) from port Y of cell top.$flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell top.$flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
Removed top 22 bits (of 32) from port Y of cell top.$flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub).
|
|
Removed top 27 bits (of 32) from port Y of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub).
|
|
Removed top 26 bits (of 32) from port Y of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub).
|
|
Removed top 4 bits (of 5) from port B of cell top.$flatten\lvds_tx_inst.$eq$lvds_tx.v:36$562 ($eq).
|
|
Removed top 3 bits (of 5) from port B of cell top.$flatten\lvds_tx_inst.$eq$lvds_tx.v:34$560 ($eq).
|
|
Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2282 ($ne).
|
|
Removed top 31 bits (of 32) from port B of cell top.$flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
Removed top 22 bits (of 32) from port Y of cell top.$flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell top.$flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
Removed top 22 bits (of 32) from port Y of cell top.$flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2208 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2206 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2204 ($ne).
|
|
Removed top 28 bits (of 32) from port B of cell top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add).
|
|
Removed top 27 bits (of 32) from port Y of cell top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add).
|
|
Removed top 1 bits (of 5) from port B of cell top.$flatten\smi_ctrl_ins.$eq$smi_ctrl.v:122$410 ($eq).
|
|
Removed top 29 bits (of 32) from wire top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572_Y.
|
|
Removed top 29 bits (of 32) from wire top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572_Y.
|
|
Removed top 27 bits (of 32) from wire top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565_Y.
|
|
Removed top 22 bits (of 32) from wire top.$flatten\rx_fifo.$add$complex_fifo.v:61$473_Y.
|
|
Removed top 22 bits (of 32) from wire top.$flatten\rx_fifo.$add$complex_fifo.v:88$506_Y.
|
|
Removed top 10 bits (of 16) from wire top.$flatten\rx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA.
|
|
Removed top 27 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416_Y.
|
|
Removed top 22 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$procmux$1636_Y.
|
|
Removed top 2 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$procmux$1639_Y.
|
|
Removed top 6 bits (of 8) from wire top.$flatten\smi_ctrl_ins.$procmux$1681_Y.
|
|
Removed top 1 bits (of 3) from wire top.$flatten\spi_if_ins.$procmux$762_Y.
|
|
Removed top 29 bits (of 32) from wire top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600_Y.
|
|
Removed top 22 bits (of 32) from wire top.$flatten\tx_fifo.$add$complex_fifo.v:61$473_Y.
|
|
Removed top 22 bits (of 32) from wire top.$flatten\tx_fifo.$add$complex_fifo.v:88$506_Y.
|
|
Removed top 1 bits (of 32) from wire top.w_rx_09_fifo_data.
|
|
Removed top 7 bits (of 32) from wire top.w_rx_fifo_pulled_data.
|
|
Removed top 5 bits (of 8) from wire top.w_tx_data_smi.
|
|
|
|
2.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 17 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.17. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.21. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module top:
|
|
creating $macc model for $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
creating $macc model for $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub).
|
|
creating $macc model for $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub).
|
|
creating $macc model for $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub).
|
|
creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:46$455 ($add).
|
|
creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:73$488 ($add).
|
|
creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
creating $macc model for $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add).
|
|
creating $macc model for $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add).
|
|
creating $macc model for $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub).
|
|
creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:46$455 ($add).
|
|
creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add).
|
|
creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:73$488 ($add).
|
|
creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add).
|
|
creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:88$506.
|
|
creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:73$488.
|
|
creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:61$473.
|
|
creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:46$455.
|
|
creating $alu model for $macc $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611.
|
|
creating $alu model for $macc $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600.
|
|
creating $alu model for $macc $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416.
|
|
creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:88$506.
|
|
creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:73$488.
|
|
creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:61$473.
|
|
creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:46$455.
|
|
creating $alu model for $macc $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565.
|
|
creating $alu model for $macc $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563.
|
|
creating $alu model for $macc $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572.
|
|
creating $alu model for $macc $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572.
|
|
creating $alu cell for $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572: $auto$alumacc.cc:485:replace_alu$2347
|
|
creating $alu cell for $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572: $auto$alumacc.cc:485:replace_alu$2350
|
|
creating $alu cell for $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563: $auto$alumacc.cc:485:replace_alu$2353
|
|
creating $alu cell for $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565: $auto$alumacc.cc:485:replace_alu$2356
|
|
creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:46$455: $auto$alumacc.cc:485:replace_alu$2359
|
|
creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:61$473: $auto$alumacc.cc:485:replace_alu$2362
|
|
creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:73$488: $auto$alumacc.cc:485:replace_alu$2365
|
|
creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:88$506: $auto$alumacc.cc:485:replace_alu$2368
|
|
creating $alu cell for $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416: $auto$alumacc.cc:485:replace_alu$2371
|
|
creating $alu cell for $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600: $auto$alumacc.cc:485:replace_alu$2374
|
|
creating $alu cell for $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611: $auto$alumacc.cc:485:replace_alu$2377
|
|
creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:46$455: $auto$alumacc.cc:485:replace_alu$2380
|
|
creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:61$473: $auto$alumacc.cc:485:replace_alu$2383
|
|
creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:73$488: $auto$alumacc.cc:485:replace_alu$2386
|
|
creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:88$506: $auto$alumacc.cc:485:replace_alu$2389
|
|
created 15 $alu and 0 $macc cells.
|
|
|
|
2.22. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.22.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.22.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~16 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~58 debug messages>
|
|
|
|
2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.22.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 8 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.22.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~58 debug messages>
|
|
|
|
2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.22.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.22.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.22.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.23. Executing MEMORY pass.
|
|
|
|
2.23.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 4 transformations.
|
|
|
|
2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing top.rx_fifo.mem_i write port 0.
|
|
Analyzing top.rx_fifo.mem_q write port 0.
|
|
Analyzing top.tx_fifo.mem_i write port 0.
|
|
Analyzing top.tx_fifo.mem_q write port 0.
|
|
|
|
2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\rx_fifo.mem_i'[0] in module `\top': merging output FF to cell.
|
|
Checking read port `\rx_fifo.mem_q'[0] in module `\top': merging output FF to cell.
|
|
Checking read port `\tx_fifo.mem_i'[0] in module `\top': merging output FF to cell.
|
|
Checking read port `\tx_fifo.mem_q'[0] in module `\top': merging output FF to cell.
|
|
|
|
2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 2 unused cells and 68 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory top.rx_fifo.mem_i via $__ICE40_RAM4K_
|
|
mapping memory top.rx_fifo.mem_q via $__ICE40_RAM4K_
|
|
mapping memory top.tx_fifo.mem_i via $__ICE40_RAM4K_
|
|
mapping memory top.tx_fifo.mem_q via $__ICE40_RAM4K_
|
|
<suppressed ~208 debug messages>
|
|
|
|
2.26. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.26.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.26.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/spram_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/spram_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.26.3. Continuing TECHMAP pass.
|
|
Using template $paramod$152405ab8834e0c4f35bd7e4e60c34790a6f81fa\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
|
|
No more expansions possible.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.27. Executing ICE40_BRAMINIT pass.
|
|
|
|
2.28. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.28.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~180 debug messages>
|
|
|
|
2.28.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2049 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$737_Y, Q = \spi_if_ins.r_tx_data_valid, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2032 ($dffe) from module top (D = \spi_if_ins.r_tx_byte, Q = \spi_if_ins.spi.r_tx_byte, rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2130 ($dffe) from module top (D = { \smi_ctrl_ins.r_fifo_pushed_data [31] \smi_ctrl_ins.r_fifo_pushed_data [29:16] \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] }, Q = { \smi_ctrl_ins.o_tx_fifo_pushed_data [31] \smi_ctrl_ins.o_tx_fifo_pushed_data [29:16] \smi_ctrl_ins.o_tx_fifo_pushed_data [14:1] }, rval = 29'00000000000000000000000000000).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2130 ($dffe) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1634_Y [30] $flatten\smi_ctrl_ins.$procmux$1634_Y [15] $flatten\smi_ctrl_ins.$procmux$1634_Y [0] }, Q = { \smi_ctrl_ins.o_tx_fifo_pushed_data [30] \smi_ctrl_ins.o_tx_fifo_pushed_data [15] \smi_ctrl_ins.o_tx_fifo_pushed_data [0] }, rval = 3'000).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2111 ($sdff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1612_Y, Q = \smi_ctrl_ins.w_fifo_push_trigger, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2099 ($dffe) from module top (D = { \smi_ctrl_ins.r_channel \tx_fifo.full_o \rx_fifo.empty_o }, Q = \smi_ctrl_ins.o_data_out [2:0], rval = 3'001).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2073 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$792_Y, Q = \spi_if_ins.o_fetch_cmd, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$2064 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$778_Y, Q = \spi_if_ins.o_load_cmd, rval = 1'0).
|
|
|
|
2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 11 unused cells and 281 unused wires.
|
|
<suppressed ~12 debug messages>
|
|
|
|
2.28.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.28.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.28.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.28.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2156 ($sdff) from module top (D = \lvds_tx_inst.r_phase_count [0], Q = \lvds_tx_inst.r_phase_count [0]).
|
|
Handling D = Q on $auto$ff.cc:266:slice$2546 ($sdffe) from module top (conecting SRST instead).
|
|
Adding EN signal on $auto$ff.cc:266:slice$2107 ($sdff) from module top (D = \smi_ctrl_ins.int_cnt_rx [2:0], Q = \smi_ctrl_ins.int_cnt_rx [2:0]).
|
|
Handling D = Q on $auto$ff.cc:266:slice$2550 ($sdffe) from module top (conecting SRST instead).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2550 ($dffe) from module top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2550 ($dffe) from module top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2550 ($dffe) from module top.
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$2546 ($dffe) from module top.
|
|
|
|
2.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 2 unused cells and 3 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.28.10. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.28.11. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~16 debug messages>
|
|
|
|
2.28.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.28.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 1 unused cells and 9 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.28.15. Finished fast OPT passes.
|
|
|
|
2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
2.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~42 debug messages>
|
|
|
|
2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Consolidated identical input bits for $mux cell $flatten\lvds_rx_09_inst.$procmux$1160:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\lvds_rx_09_inst.$procmux$1160_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\lvds_rx_09_inst.$procmux$1160_Y [0]
|
|
New connections: $flatten\lvds_rx_09_inst.$procmux$1160_Y [1] = $flatten\lvds_rx_09_inst.$procmux$1160_Y [0]
|
|
Consolidated identical input bits for $pmux cell $flatten\lvds_rx_09_inst.$procmux$1171:
|
|
Old ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_09_d0 \w_lvds_rx_09_d1 }, B={ \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d0 \w_lvds_rx_09_d1 \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d0 $flatten\lvds_rx_09_inst.$procmux$1169_Y [0] }, Y=$flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0]
|
|
New ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_09_d1 }, B={ \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d1 \lvds_rx_09_inst.o_fifo_data [29:0] $flatten\lvds_rx_09_inst.$procmux$1169_Y [0] }, Y={ $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [31:2] $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [0] }
|
|
New connections: $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [1] = \w_lvds_rx_09_d0
|
|
Consolidated identical input bits for $mux cell $flatten\lvds_rx_24_inst.$procmux$1160:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\lvds_rx_24_inst.$procmux$1160_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\lvds_rx_24_inst.$procmux$1160_Y [0]
|
|
New connections: $flatten\lvds_rx_24_inst.$procmux$1160_Y [1] = $flatten\lvds_rx_24_inst.$procmux$1160_Y [0]
|
|
Consolidated identical input bits for $pmux cell $flatten\lvds_rx_24_inst.$procmux$1171:
|
|
Old ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_24_d0 \w_lvds_rx_24_d1 }, B={ \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d0 \w_lvds_rx_24_d1 \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d0 $flatten\lvds_rx_24_inst.$procmux$1169_Y [0] }, Y=$flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0]
|
|
New ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_24_d1 }, B={ \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d1 \lvds_rx_24_inst.o_fifo_data [29:0] $flatten\lvds_rx_24_inst.$procmux$1169_Y [0] }, Y={ $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [31:2] $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [0] }
|
|
New connections: $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [1] = \w_lvds_rx_24_d0
|
|
Consolidated identical input bits for $mux cell $flatten\smi_ctrl_ins.$procmux$1634:
|
|
Old ports: A={ \smi_ctrl_ins.r_fifo_pushed_data [31] 1'0 \smi_ctrl_ins.r_fifo_pushed_data [29:16] 1'0 \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] 1'0 }, B=0, Y=$flatten\smi_ctrl_ins.$procmux$1634_Y
|
|
New ports: A={ \smi_ctrl_ins.r_fifo_pushed_data [31] \smi_ctrl_ins.r_fifo_pushed_data [29:16] \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] }, B=29'00000000000000000000000000000, Y={ $flatten\smi_ctrl_ins.$procmux$1634_Y [31] $flatten\smi_ctrl_ins.$procmux$1634_Y [29:16] $flatten\smi_ctrl_ins.$procmux$1634_Y [14:1] }
|
|
New connections: { $flatten\smi_ctrl_ins.$procmux$1634_Y [30] $flatten\smi_ctrl_ins.$procmux$1634_Y [15] $flatten\smi_ctrl_ins.$procmux$1634_Y [0] } = 3'000
|
|
Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$754:
|
|
Old ports: A=3'100, B=3'010, Y=$flatten\spi_if_ins.$procmux$754_Y
|
|
New ports: A=2'10, B=2'01, Y=$flatten\spi_if_ins.$procmux$754_Y [2:1]
|
|
New connections: $flatten\spi_if_ins.$procmux$754_Y [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$758:
|
|
Old ports: A={ 1'0 $auto$wreduce.cc:455:run$2339 [1:0] }, B=3'000, Y=$flatten\spi_if_ins.$procmux$758_Y
|
|
New ports: A=$auto$wreduce.cc:455:run$2339 [1:0], B=2'00, Y=$flatten\spi_if_ins.$procmux$758_Y [1:0]
|
|
New connections: $flatten\spi_if_ins.$procmux$758_Y [2] = 1'0
|
|
Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$762:
|
|
Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:455:run$2339 [1:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:455:run$2339 [1]
|
|
New connections: $auto$wreduce.cc:455:run$2339 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\sys_ctrl_ins.$procmux$857:
|
|
Old ports: A=8'00000001, B=8'00000000, Y=$flatten\sys_ctrl_ins.$procmux$857_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\sys_ctrl_ins.$procmux$857_Y [0]
|
|
New connections: $flatten\sys_ctrl_ins.$procmux$857_Y [7:1] = 7'0000000
|
|
Optimizing cells in module \top.
|
|
Performed a total of 9 changes.
|
|
|
|
2.30.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 1 unused cells and 1 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.30.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.30.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.30.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.30.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2013 ($adffe) from module top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top.
|
|
|
|
2.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.30.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.30.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
2.30.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.30.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.30.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.30.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
|
|
|
|
2.32. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.32.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ice40_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.32.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $tribuf.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using template $paramod$ee721315a7b0169d82611b9aea01747035b97792\_90_pmux for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod$754650b284649a026620fc6856e5b6886cbfe794\_80_ice40_alu for cells of type $alu.
|
|
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_80_ice40_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $adffe.
|
|
Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_pmux for cells of type $pmux.
|
|
Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux.
|
|
Using template $paramod$f08cf4b531f7b2bd95251b79857dfb970a6679fc\_90_pmux for cells of type $pmux.
|
|
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
|
|
Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
|
|
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu.
|
|
Using template $paramod$constmap:c39c2a14b34c884b1bdd5cf6ea238257f5452db9$paramod$dacef1a7b1be4e3e06ba737eb7b1f6b44c4ce930\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_80_ice40_alu for cells of type $alu.
|
|
Using template $paramod$constmap:ad62432dc588384ac9e4502cee6ddae521345b24$paramod$8ae51266ce98bc5533551c59a6aa22584269889d\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_80_ice40_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
Using extmapper simplemap for cells of type $or.
|
|
No more expansions possible.
|
|
<suppressed ~1589 debug messages>
|
|
|
|
2.33. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.33.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~760 debug messages>
|
|
|
|
2.33.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~411 debug messages>
|
|
Removed a total of 137 cells.
|
|
|
|
2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 206 unused cells and 999 unused wires.
|
|
<suppressed ~207 debug messages>
|
|
|
|
2.33.5. Finished fast OPT passes.
|
|
|
|
2.34. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.34.1. Running ICE40 specific optimizations.
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2347.slice[0].carry: CO=\lvds_rx_09_inst.r_phase_count [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2350.slice[0].carry: CO=\lvds_rx_24_inst.r_phase_count [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2356.slice[0].carry: CO=\lvds_tx_inst.r_phase_count [1]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2359.slice[0].carry: CO=\rx_fifo.wr_addr [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2362.slice[0].carry: CO=\rx_fifo.wr_addr [1]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2365.slice[0].carry: CO=\rx_fifo.rd_addr [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2374.slice[0].carry: CO=\spi_if_ins.spi.r_rx_bit_count [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2377.slice[0].carry: CO=\spi_if_ins.spi.r_tx_bit_count [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2380.slice[0].carry: CO=\tx_fifo.wr_addr [0]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2383.slice[0].carry: CO=\tx_fifo.wr_addr [1]
|
|
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2386.slice[0].carry: CO=\tx_fifo.rd_addr [0]
|
|
|
|
2.34.2. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.34.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$4423 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1020.Y_B, Q = \io_ctrl_ins.o_data_out [7], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$4422 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$963.Y_B, Q = \io_ctrl_ins.o_data_out [6], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$4421 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$974.Y_B, Q = \io_ctrl_ins.o_data_out [5], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3986 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [7], Q = \r_tx_data [7], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3985 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [30], Q = \r_tx_data [6], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3984 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [5], Q = \r_tx_data [5], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3983 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [28], Q = \r_tx_data [4], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3982 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [27], Q = \r_tx_data [3], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3981 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [2], Q = \r_tx_data [2], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3980 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [1], Q = \r_tx_data [1], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3762 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [30], Q = \lvds_rx_24_inst.o_fifo_data [31], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3761 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [29], Q = \lvds_rx_24_inst.o_fifo_data [30], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3760 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [28], Q = \lvds_rx_24_inst.o_fifo_data [29], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3759 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [27], Q = \lvds_rx_24_inst.o_fifo_data [28], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3758 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [26], Q = \lvds_rx_24_inst.o_fifo_data [27], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3757 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [25], Q = \lvds_rx_24_inst.o_fifo_data [26], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3756 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [24], Q = \lvds_rx_24_inst.o_fifo_data [25], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3755 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [23], Q = \lvds_rx_24_inst.o_fifo_data [24], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3754 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [22], Q = \lvds_rx_24_inst.o_fifo_data [23], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3753 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [21], Q = \lvds_rx_24_inst.o_fifo_data [22], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3752 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [20], Q = \lvds_rx_24_inst.o_fifo_data [21], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3751 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [19], Q = \lvds_rx_24_inst.o_fifo_data [20], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3750 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [18], Q = \lvds_rx_24_inst.o_fifo_data [19], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3749 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [17], Q = \lvds_rx_24_inst.o_fifo_data [18], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3748 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [16], Q = \lvds_rx_24_inst.o_fifo_data [17], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3747 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [15], Q = \lvds_rx_24_inst.o_fifo_data [16], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3746 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [14], Q = \lvds_rx_24_inst.o_fifo_data [15], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3745 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [13], Q = \lvds_rx_24_inst.o_fifo_data [14], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3744 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [12], Q = \lvds_rx_24_inst.o_fifo_data [13], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3743 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [11], Q = \lvds_rx_24_inst.o_fifo_data [12], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3742 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [10], Q = \lvds_rx_24_inst.o_fifo_data [11], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3741 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [9], Q = \lvds_rx_24_inst.o_fifo_data [10], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3740 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [8], Q = \lvds_rx_24_inst.o_fifo_data [9], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3739 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [7], Q = \lvds_rx_24_inst.o_fifo_data [8], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3738 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [6], Q = \lvds_rx_24_inst.o_fifo_data [7], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3737 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [5], Q = \lvds_rx_24_inst.o_fifo_data [6], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3736 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [4], Q = \lvds_rx_24_inst.o_fifo_data [5], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3735 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [3], Q = \lvds_rx_24_inst.o_fifo_data [4], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3734 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [2], Q = \lvds_rx_24_inst.o_fifo_data [3], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3733 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [1], Q = \lvds_rx_24_inst.o_fifo_data [2], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3592 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [30], Q = \lvds_rx_09_inst.o_fifo_data [31], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3591 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [29], Q = \lvds_rx_09_inst.o_fifo_data [30], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3590 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [28], Q = \lvds_rx_09_inst.o_fifo_data [29], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3589 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [27], Q = \lvds_rx_09_inst.o_fifo_data [28], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3588 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [26], Q = \lvds_rx_09_inst.o_fifo_data [27], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3587 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [25], Q = \lvds_rx_09_inst.o_fifo_data [26], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3586 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [24], Q = \lvds_rx_09_inst.o_fifo_data [25], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3585 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [23], Q = \lvds_rx_09_inst.o_fifo_data [24], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3584 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [22], Q = \lvds_rx_09_inst.o_fifo_data [23], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3583 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [21], Q = \lvds_rx_09_inst.o_fifo_data [22], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3582 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [20], Q = \lvds_rx_09_inst.o_fifo_data [21], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3581 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [19], Q = \lvds_rx_09_inst.o_fifo_data [20], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3580 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [18], Q = \lvds_rx_09_inst.o_fifo_data [19], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3579 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [17], Q = \lvds_rx_09_inst.o_fifo_data [18], rval = 1'0).
|
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Adding SRST signal on $auto$ff.cc:266:slice$3578 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [16], Q = \lvds_rx_09_inst.o_fifo_data [17], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3577 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [15], Q = \lvds_rx_09_inst.o_fifo_data [16], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3576 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [14], Q = \lvds_rx_09_inst.o_fifo_data [15], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3575 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [13], Q = \lvds_rx_09_inst.o_fifo_data [14], rval = 1'0).
|
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Adding SRST signal on $auto$ff.cc:266:slice$3574 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [12], Q = \lvds_rx_09_inst.o_fifo_data [13], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3573 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [11], Q = \lvds_rx_09_inst.o_fifo_data [12], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3572 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [10], Q = \lvds_rx_09_inst.o_fifo_data [11], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3571 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [9], Q = \lvds_rx_09_inst.o_fifo_data [10], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:266:slice$3570 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [8], Q = \lvds_rx_09_inst.o_fifo_data [9], rval = 1'0).
|
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Adding SRST signal on $auto$ff.cc:266:slice$3569 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [7], Q = \lvds_rx_09_inst.o_fifo_data [8], rval = 1'0).
|
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Adding SRST signal on $auto$ff.cc:266:slice$3568 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [6], Q = \lvds_rx_09_inst.o_fifo_data [7], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3567 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [5], Q = \lvds_rx_09_inst.o_fifo_data [6], rval = 1'0).
|
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Adding SRST signal on $auto$ff.cc:266:slice$3566 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [4], Q = \lvds_rx_09_inst.o_fifo_data [5], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3565 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [3], Q = \lvds_rx_09_inst.o_fifo_data [4], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3564 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [2], Q = \lvds_rx_09_inst.o_fifo_data [3], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3563 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [1], Q = \lvds_rx_09_inst.o_fifo_data [2], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3310 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1031.Y_B, Q = \io_ctrl_ins.o_data_out [4], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3309 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$985.Y_B, Q = \io_ctrl_ins.o_data_out [3], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3308 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1043.Y_B, Q = \io_ctrl_ins.o_data_out [1], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$3307 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1008.Y_B, Q = \io_ctrl_ins.o_data_out [0], rval = 1'1).
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Adding SRST signal on $auto$ff.cc:266:slice$3095 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$997.Y_B, Q = \io_ctrl_ins.o_data_out [2], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$2944 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [3], Q = \spi_if_ins.o_cs [3], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$2943 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [6], Q = \spi_if_ins.o_cs [2], rval = 1'0).
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Adding SRST signal on $auto$ff.cc:266:slice$2942 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [9], Q = \spi_if_ins.o_cs [1], rval = 1'0).
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2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 78 unused cells and 8 unused wires.
|
|
<suppressed ~79 debug messages>
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|
|
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2.34.6. Rerunning OPT passes. (Removed registers in this run.)
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|
|
2.34.7. Running ICE40 specific optimizations.
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2.34.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.34.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.34.12. Finished OPT passes. (There is nothing left to do.)
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|
|
|
2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
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2.36. Executing TECHMAP pass (map to technology primitives).
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2.36.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.36.2. Continuing TECHMAP pass.
|
|
Using template \$_SDFFCE_NP0P_ for cells of type $_SDFFCE_NP0P_.
|
|
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
|
|
Using template \$_DFF_P_ for cells of type $_DFF_P_.
|
|
Using template \$_DFFE_NP_ for cells of type $_DFFE_NP_.
|
|
Using template \$_SDFF_NP0_ for cells of type $_SDFF_NP0_.
|
|
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
|
|
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
|
|
Using template \$_DFF_N_ for cells of type $_DFF_N_.
|
|
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
|
|
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
No more expansions possible.
|
|
<suppressed ~538 debug messages>
|
|
|
|
2.37. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2350.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2356.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2359.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2362.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2365.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2374.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2377.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2380.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2383.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2386.slice[0].carry ($lut).
|
|
Mapping top.$auto$alumacc.cc:485:replace_alu$2347.slice[0].carry ($lut).
|
|
|
|
2.39. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
2.39.1. Running ICE40 specific optimizations.
|
|
|
|
2.39.2. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~170 debug messages>
|
|
|
|
2.39.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~1464 debug messages>
|
|
Removed a total of 488 cells.
|
|
|
|
2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 3329 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.39.6. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.39.7. Running ICE40 specific optimizations.
|
|
|
|
2.39.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
2.39.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
2.39.12. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.40. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.40.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.41. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 1114 gates and 1540 wires to a netlist network with 424 inputs and 328 outputs.
|
|
|
|
2.41.1.1. Executing ABC.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + &get -n
|
|
ABC: + &fraig -x
|
|
ABC: + &put
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + lutpack -S 1
|
|
ABC: + dress <abc-temp-dir>/input.blif
|
|
ABC: Total number of equiv classes = 384.
|
|
ABC: Participating nodes from both networks = 829.
|
|
ABC: Participating nodes from the first network = 389. ( 77.96 % of nodes)
|
|
ABC: Participating nodes from the second network = 440. ( 88.18 % of nodes)
|
|
ABC: Node pairs (any polarity) = 389. ( 77.96 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 351. ( 70.34 % of names can be moved)
|
|
ABC: Total runtime = 0.11 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.41.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 498
|
|
ABC RESULTS: internal signals: 788
|
|
ABC RESULTS: input signals: 424
|
|
ABC RESULTS: output signals: 328
|
|
Removing temp directory.
|
|
|
|
2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
|
|
|
|
2.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~22 debug messages>
|
|
Removed 11 unused cells and 1083 unused wires.
|
|
|
|
2.44. Executing OPT_LUT pass (optimize LUTs).
|
|
Discovering LUTs.
|
|
Number of LUTs: 556
|
|
1-LUT 32
|
|
2-LUT 197
|
|
3-LUT 172
|
|
4-LUT 155
|
|
with \SB_CARRY (#0) 52
|
|
with \SB_CARRY (#1) 52
|
|
|
|
Eliminating LUTs.
|
|
Number of LUTs: 556
|
|
1-LUT 32
|
|
2-LUT 197
|
|
3-LUT 172
|
|
4-LUT 155
|
|
with \SB_CARRY (#0) 52
|
|
with \SB_CARRY (#1) 52
|
|
|
|
Combining LUTs.
|
|
Number of LUTs: 550
|
|
1-LUT 26
|
|
2-LUT 197
|
|
3-LUT 172
|
|
4-LUT 155
|
|
with \SB_CARRY (#0) 52
|
|
with \SB_CARRY (#1) 52
|
|
|
|
Eliminated 0 LUTs.
|
|
Combined 6 LUTs.
|
|
<suppressed ~2476 debug messages>
|
|
|
|
2.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.45.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9\$lut for cells of type $lut.
|
|
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut.
|
|
Using template $paramod$34c84a38a1bc6aa36f1daa52808ce6e0746a068c\$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
|
|
Using template $paramod$7a9d9396461df152f697894fa3b294ad1b285e08\$lut for cells of type $lut.
|
|
Using template $paramod$7ffac03cd0abd3a28c1c30cc28dbcbcc23ba7457\$lut for cells of type $lut.
|
|
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
|
|
Using template $paramod$80cbd08923107235732b36a5d5a7181977144217\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod$d6d3aaeac1b9aa2c4b652c48e0deb565040dda72\$lut for cells of type $lut.
|
|
Using template $paramod$de3d8c0ac9a85f776878d56395b6e0bf04ae72e7\$lut for cells of type $lut.
|
|
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
|
|
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
|
|
Using template $paramod$e96de5e9fcce737e52eacf39c70c8f533dc27d63\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
|
|
Using template $paramod$2d8ecce5c907513cebcd38ab5efe0fc26fc03464\$lut for cells of type $lut.
|
|
Using template $paramod$a3cdc1eb771a2c6a16f64da161e11100ac409d2b\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut.
|
|
Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod$977b7e79e3ba9c774a867eb4017ef67f55786548\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod$82ac4228e04c92c7b8c133bfa256dd480e0cef1d\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$22295481aee48631dc0088cef4e5f102b07c1986\$lut for cells of type $lut.
|
|
Using template $paramod$cde3aa23c1efa60a470cf0f0281347d6ba585afa\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut.
|
|
Using template $paramod$50666a8f9d622ca1f027a4587dfd5f2a7d8810c9\$lut for cells of type $lut.
|
|
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
|
|
Using template $paramod$d6cf0a4b6f6ccd87588da28c41b5b6c258da2509\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod$c3d2b1ca136b61a4c0de563fc4d3f82c9bc2587b\$lut for cells of type $lut.
|
|
Using template $paramod$8ec29827d94e80e773a6f636dfcf3e1591527264\$lut for cells of type $lut.
|
|
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
|
|
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut.
|
|
Using template $paramod$298b370b0ed6e6727b735e07db069bd52561f3c3\$lut for cells of type $lut.
|
|
Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8\$lut for cells of type $lut.
|
|
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut.
|
|
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut.
|
|
Using template $paramod$7ad6771b9b40fd01d98988c39e9c94d34bc85f74\$lut for cells of type $lut.
|
|
Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut.
|
|
Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704\$lut for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
|
|
Using template $paramod$bdb7f9ed72fd4f5c7ad81c376f2d8a5c72a0098d\$lut for cells of type $lut.
|
|
Using template $paramod$3d3394a2dba7636f2df80deb551dae557f28c000\$lut for cells of type $lut.
|
|
Using template $paramod$84d027b8e91897c1e09c2fa4152cf39e28672ceb\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
|
|
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
|
|
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\$lut for cells of type $lut.
|
|
Using template $paramod$eb053f45c2a9f7396900cdb1dbe99a65c219c0a6\$lut for cells of type $lut.
|
|
Using template $paramod$175104ad114973f30397e1a69eae08cff730fc58\$lut for cells of type $lut.
|
|
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut.
|
|
Using template $paramod$26e2df3ec51b730bb541c0780f84ea91c3db55ae\$lut for cells of type $lut.
|
|
Using template $paramod$40f3a0e76bf7979db02f9dd35e4ad0450372f384\$lut for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~1762 debug messages>
|
|
Removed 0 unused cells and 1192 unused wires.
|
|
|
|
2.46. Executing AUTONAME pass.
|
|
Renamed 15185 objects in module top (45 iterations).
|
|
<suppressed ~1436 debug messages>
|
|
|
|
2.47. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.47.1. Analyzing design hierarchy..
|
|
Top module: \top
|
|
|
|
2.47.2. Analyzing design hierarchy..
|
|
Top module: \top
|
|
Removed 0 unused modules.
|
|
|
|
2.48. Printing statistics.
|
|
|
|
=== top ===
|
|
|
|
Number of wires: 584
|
|
Number of wire bits: 2425
|
|
Number of public wires: 584
|
|
Number of public wire bits: 2425
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 1148
|
|
$_TBUF_ 1
|
|
SB_CARRY 52
|
|
SB_DFF 86
|
|
SB_DFFE 86
|
|
SB_DFFER 20
|
|
SB_DFFESR 203
|
|
SB_DFFESS 4
|
|
SB_DFFN 4
|
|
SB_DFFNE 9
|
|
SB_DFFNESR 84
|
|
SB_DFFNSR 3
|
|
SB_DFFSR 15
|
|
SB_DFFSS 2
|
|
SB_IO 13
|
|
SB_LUT4 550
|
|
SB_RAM40_4K 16
|
|
|
|
2.49. Executing CHECK pass (checking for obvious problems).
|
|
Checking module top...
|
|
Found and reported 0 problems.
|
|
|
|
2.50. Executing BLIF backend.
|
|
|
|
2.51. Executing JSON backend.
|
|
|
|
-- Running command `ice40_opt' --
|
|
|
|
3. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
3.1. Running ICE40 specific optimizations.
|
|
|
|
3.2. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~85 debug messages>
|
|
|
|
3.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.4. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.6. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
3.7. Running ICE40 specific optimizations.
|
|
|
|
3.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.9. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.10. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.12. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
-- Running command `fsm_opt' --
|
|
|
|
4. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
Warnings: 17 unique messages, 17 total
|
|
End of script. Logfile hash: d11a7ddf2c, CPU: user 10.77s system 0.10s, MEM: 33.59 MB peak
|
|
Yosys 0.26+1 (git sha1 b1a011138, gcc 10.2.1-6 -fPIC -Os)
|
|
Time spent: 18% 37x opt_expr (2 sec), 16% 7x techmap (2 sec), ...
|
|
nextpnr-ice40 --lp1k --package qn84 --json top.json --pcf ./io.pcf --asc top.asc
|
|
Info: constraining clock net 'w_clock_sys' to 64.00 MHz
|
|
Info: constraining clock net 'smi_ctrl_ins.soe_and_reset' to 16.00 MHz
|
|
Info: constraining clock net 'i_smi_swe_srw' to 16.00 MHz
|
|
Info: constraining clock net 'i_sck' to 5.00 MHz
|
|
Info: constrained 'i_glob_clock' to bel 'X13/Y8/io1'
|
|
Info: constrained 'i_rst_b' to bel 'X7/Y17/io0'
|
|
Info: constrained 'io_pmod[0]' to bel 'X13/Y12/io0'
|
|
Info: constrained 'io_pmod[1]' to bel 'X13/Y11/io1'
|
|
Info: constrained 'io_pmod[2]' to bel 'X13/Y11/io0'
|
|
Info: constrained 'io_pmod[3]' to bel 'X13/Y7/io0'
|
|
Info: constrained 'io_pmod[4]' to bel 'X13/Y4/io0'
|
|
Info: constrained 'io_pmod[5]' to bel 'X13/Y6/io0'
|
|
Info: constrained 'io_pmod[6]' to bel 'X13/Y7/io1'
|
|
Info: constrained 'io_pmod[7]' to bel 'X13/Y6/io1'
|
|
Info: constrained 'o_mixer_fm' to bel 'X13/Y12/io1'
|
|
Info: constrained 'o_mixer_en' to bel 'X13/Y9/io0'
|
|
Info: constrained 'o_rx_h_tx_l' to bel 'X13/Y13/io1'
|
|
Info: constrained 'o_rx_h_tx_l_b' to bel 'X13/Y15/io0'
|
|
Info: constrained 'o_tr_vc1' to bel 'X13/Y14/io0'
|
|
Info: constrained 'o_tr_vc1_b' to bel 'X13/Y15/io1'
|
|
Info: constrained 'o_tr_vc2' to bel 'X13/Y14/io1'
|
|
Info: constrained 'o_shdn_rx_lna' to bel 'X4/Y17/io0'
|
|
Info: constrained 'o_shdn_tx_lna' to bel 'X2/Y17/io1'
|
|
Info: constrained 'o_iq_tx_p' to bel 'X0/Y10/io1'
|
|
Info: constrained 'o_iq_tx_n' to bel 'X0/Y10/io0'
|
|
Info: constrained 'o_iq_tx_clk_p' to bel 'X0/Y5/io1'
|
|
Info: constrained 'o_iq_tx_clk_n' to bel 'X0/Y5/io0'
|
|
Info: constrained 'i_iq_rx_09_p' to bel 'X0/Y11/io0'
|
|
Info: constrained 'i_iq_rx_24_n' to bel 'X0/Y13/io0'
|
|
Info: constrained 'i_iq_rx_clk_p' to bel 'X0/Y12/io0'
|
|
Info: constrained 'i_config[0]' to bel 'X10/Y17/io1'
|
|
Info: constrained 'i_config[1]' to bel 'X9/Y17/io0'
|
|
Info: constrained 'i_config[2]' to bel 'X9/Y17/io1'
|
|
Info: constrained 'i_config[3]' to bel 'X8/Y17/io0'
|
|
Info: constrained 'i_button' to bel 'X8/Y17/io1'
|
|
Info: constrained 'o_led0' to bel 'X11/Y17/io0'
|
|
Info: constrained 'o_led1' to bel 'X10/Y17/io0'
|
|
Info: constrained 'o_smi_write_req' to bel 'X9/Y0/io1'
|
|
Info: constrained 'o_smi_read_req' to bel 'X13/Y3/io1'
|
|
Info: constrained 'i_smi_a2' to bel 'X1/Y17/io1'
|
|
Info: constrained 'i_smi_a3' to bel 'X3/Y17/io0'
|
|
Info: constrained 'i_smi_soe_se' to bel 'X10/Y0/io0'
|
|
Info: constrained 'i_smi_swe_srw' to bel 'X8/Y0/io0'
|
|
Info: constrained 'io_smi_data[0]' to bel 'X6/Y0/io0'
|
|
Info: constrained 'io_smi_data[1]' to bel 'X5/Y0/io1'
|
|
Info: constrained 'io_smi_data[2]' to bel 'X5/Y0/io0'
|
|
Info: constrained 'io_smi_data[3]' to bel 'X7/Y0/io0'
|
|
Info: constrained 'io_smi_data[4]' to bel 'X9/Y0/io0'
|
|
Info: constrained 'io_smi_data[5]' to bel 'X10/Y0/io1'
|
|
Info: constrained 'io_smi_data[6]' to bel 'X4/Y0/io0'
|
|
Info: constrained 'io_smi_data[7]' to bel 'X6/Y0/io1'
|
|
Info: constrained 'i_mosi' to bel 'X11/Y0/io1'
|
|
Info: constrained 'i_sck' to bel 'X12/Y0/io0'
|
|
Info: constrained 'i_ss' to bel 'X12/Y0/io1'
|
|
Info: constrained 'o_miso' to bel 'X11/Y0/io0'
|
|
|
|
Info: Packing constants..
|
|
Info: Packing IOs..
|
|
Info: io_smi_data[7] feeds SB_IO smi_io7, removing $nextpnr_iobuf io_smi_data[7].
|
|
Info: io_smi_data[6] feeds SB_IO smi_io6, removing $nextpnr_iobuf io_smi_data[6].
|
|
Info: o_iq_tx_p feeds SB_IO iq_tx_p, removing $nextpnr_obuf o_iq_tx_p.
|
|
Info: o_iq_tx_n feeds SB_IO iq_tx_n, removing $nextpnr_obuf o_iq_tx_n.
|
|
Info: i_iq_rx_clk_p feeds SB_IO iq_rx_clk, removing $nextpnr_ibuf i_iq_rx_clk_p.
|
|
Info: i_iq_rx_24_n feeds SB_IO iq_rx_24, removing $nextpnr_ibuf i_iq_rx_24_n.
|
|
Info: i_iq_rx_09_p feeds SB_IO iq_rx_09, removing $nextpnr_ibuf i_iq_rx_09_p.
|
|
Info: io_smi_data[5] feeds SB_IO smi_io5, removing $nextpnr_iobuf io_smi_data[5].
|
|
Info: io_smi_data[4] feeds SB_IO smi_io4, removing $nextpnr_iobuf io_smi_data[4].
|
|
Info: io_smi_data[3] feeds SB_IO smi_io3, removing $nextpnr_iobuf io_smi_data[3].
|
|
Info: io_smi_data[2] feeds SB_IO smi_io2, removing $nextpnr_iobuf io_smi_data[2].
|
|
Info: io_smi_data[1] feeds SB_IO smi_io1, removing $nextpnr_iobuf io_smi_data[1].
|
|
Info: io_smi_data[0] feeds SB_IO smi_io0, removing $nextpnr_iobuf io_smi_data[0].
|
|
Info: Packing LUT-FFs..
|
|
Info: 367 LCs used as LUT4 only
|
|
Info: 183 LCs used as LUT4 and DFF
|
|
Info: Packing non-LUT FFs..
|
|
Info: 333 LCs used as DFF only
|
|
Info: Packing carries..
|
|
Info: 3 LCs used as CARRY only
|
|
Info: Packing indirect carry+LUT pairs...
|
|
Info: 1 LUTs merged into carry LCs
|
|
Info: Packing RAMs..
|
|
Info: Placing PLLs..
|
|
Info: Packing special functions..
|
|
Info: Packing PLLs..
|
|
Info: Promoting globals..
|
|
Info: promoting o_iq_tx_clk_p$SB_IO_OUT (fanout 215)
|
|
Info: promoting r_counter (fanout 209)
|
|
Info: promoting i_rst_b_SB_LUT4_I3_O [reset] (fanout 201)
|
|
Info: promoting smi_ctrl_ins.swe_and_reset (fanout 57)
|
|
Info: promoting smi_ctrl_ins.soe_and_reset (fanout 43)
|
|
Info: promoting lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R [reset] (fanout 30)
|
|
Info: promoting lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R [reset] (fanout 30)
|
|
Info: promoting smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O [reset] (fanout 29)
|
|
Info: Constraining chains...
|
|
Info: 11 LCs used to legalise carry chains.
|
|
Info: Checksum: 0x0610fd56
|
|
|
|
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
|
|
Info: Checksum: 0xa3c42850
|
|
|
|
Info: Device utilisation:
|
|
Info: ICESTORM_LC: 898/ 1280 70%
|
|
Info: ICESTORM_RAM: 16/ 16 100%
|
|
Info: SB_IO: 51/ 112 45%
|
|
Info: SB_GB: 8/ 8 100%
|
|
Info: ICESTORM_PLL: 0/ 1 0%
|
|
Info: SB_WARMBOOT: 0/ 1 0%
|
|
|
|
Info: Placed 51 cells based on constraints.
|
|
Info: Creating initial analytic placement for 859 cells, random placement wirelen = 12699.
|
|
Info: at initial placer iter 0, wirelen = 558
|
|
Info: at initial placer iter 1, wirelen = 762
|
|
Info: at initial placer iter 2, wirelen = 789
|
|
Info: at initial placer iter 3, wirelen = 706
|
|
Info: Running main analytical placer.
|
|
Info: at iteration #1, type ICESTORM_LC: wirelen solved = 815, spread = 3956, legal = 5325; time = 0.18s
|
|
Info: at iteration #1, type SB_GB: wirelen solved = 5294, spread = 5338, legal = 5369; time = 0.02s
|
|
Info: at iteration #1, type ICESTORM_RAM: wirelen solved = 4968, spread = 5914, legal = 6193; time = 0.03s
|
|
Info: at iteration #1, type ALL: wirelen solved = 657, spread = 4189, legal = 7577; time = 2.03s
|
|
Info: at iteration #2, type ICESTORM_LC: wirelen solved = 2271, spread = 4012, legal = 5909; time = 0.61s
|
|
Info: at iteration #2, type SB_GB: wirelen solved = 5865, spread = 5898, legal = 5911; time = 0.02s
|
|
Info: at iteration #2, type ICESTORM_RAM: wirelen solved = 5601, spread = 5734, legal = 5899; time = 0.03s
|
|
Info: at iteration #2, type ALL: wirelen solved = 645, spread = 4234, legal = 7204; time = 0.77s
|
|
Info: at iteration #3, type ICESTORM_LC: wirelen solved = 2501, spread = 4092, legal = 5817; time = 0.71s
|
|
Info: at iteration #3, type SB_GB: wirelen solved = 5796, spread = 5858, legal = 5863; time = 0.02s
|
|
Info: at iteration #3, type ICESTORM_RAM: wirelen solved = 5684, spread = 5806, legal = 6097; time = 0.03s
|
|
Info: at iteration #3, type ALL: wirelen solved = 717, spread = 4054, legal = 7225; time = 0.53s
|
|
Info: at iteration #4, type ICESTORM_LC: wirelen solved = 2534, spread = 4085, legal = 5514; time = 0.82s
|
|
Info: at iteration #4, type SB_GB: wirelen solved = 5487, spread = 5525, legal = 5550; time = 0.02s
|
|
Info: at iteration #4, type ICESTORM_RAM: wirelen solved = 5157, spread = 5359, legal = 5837; time = 0.03s
|
|
Info: at iteration #4, type ALL: wirelen solved = 845, spread = 3706, legal = 6577; time = 0.97s
|
|
Info: at iteration #5, type ICESTORM_LC: wirelen solved = 2461, spread = 4002, legal = 5489; time = 0.37s
|
|
Info: at iteration #5, type SB_GB: wirelen solved = 5436, spread = 5487, legal = 5479; time = 0.02s
|
|
Info: at iteration #5, type ICESTORM_RAM: wirelen solved = 5216, spread = 5479, legal = 5851; time = 0.03s
|
|
Info: at iteration #5, type ALL: wirelen solved = 873, spread = 3768, legal = 6264; time = 0.89s
|
|
Info: at iteration #6, type ICESTORM_LC: wirelen solved = 2662, spread = 3924, legal = 5776; time = 0.23s
|
|
Info: at iteration #6, type SB_GB: wirelen solved = 5741, spread = 5777, legal = 5798; time = 0.02s
|
|
Info: at iteration #6, type ICESTORM_RAM: wirelen solved = 5373, spread = 5615, legal = 5804; time = 0.03s
|
|
Info: at iteration #6, type ALL: wirelen solved = 985, spread = 3702, legal = 6646; time = 0.68s
|
|
Info: at iteration #7, type ICESTORM_LC: wirelen solved = 2653, spread = 3911, legal = 5688; time = 0.20s
|
|
Info: at iteration #7, type SB_GB: wirelen solved = 5663, spread = 5723, legal = 5732; time = 0.02s
|
|
Info: at iteration #7, type ICESTORM_RAM: wirelen solved = 5313, spread = 5481, legal = 5709; time = 0.03s
|
|
Info: at iteration #7, type ALL: wirelen solved = 1017, spread = 3610, legal = 6825; time = 0.57s
|
|
Info: at iteration #8, type ICESTORM_LC: wirelen solved = 2763, spread = 4064, legal = 5700; time = 0.32s
|
|
Info: at iteration #8, type SB_GB: wirelen solved = 5643, spread = 5695, legal = 5690; time = 0.02s
|
|
Info: at iteration #8, type ICESTORM_RAM: wirelen solved = 5414, spread = 5627, legal = 5945; time = 0.03s
|
|
Info: at iteration #8, type ALL: wirelen solved = 1101, spread = 3911, legal = 7705; time = 0.74s
|
|
Info: at iteration #9, type ICESTORM_LC: wirelen solved = 2753, spread = 3980, legal = 5663; time = 0.15s
|
|
Info: at iteration #9, type SB_GB: wirelen solved = 5634, spread = 5660, legal = 5701; time = 0.02s
|
|
Info: at iteration #9, type ICESTORM_RAM: wirelen solved = 5109, spread = 5478, legal = 5802; time = 0.03s
|
|
Info: at iteration #9, type ALL: wirelen solved = 1006, spread = 3743, legal = 6631; time = 0.69s
|
|
Info: at iteration #10, type ICESTORM_LC: wirelen solved = 2759, spread = 3814, legal = 5567; time = 0.20s
|
|
Info: at iteration #10, type SB_GB: wirelen solved = 5523, spread = 5560, legal = 5593; time = 0.02s
|
|
Info: at iteration #10, type ICESTORM_RAM: wirelen solved = 5167, spread = 5483, legal = 5782; time = 0.03s
|
|
Info: at iteration #10, type ALL: wirelen solved = 1139, spread = 3597, legal = 6489; time = 0.47s
|
|
Info: HeAP Placer Time: 13.01s
|
|
Info: of which solving equations: 1.35s
|
|
Info: of which spreading cells: 0.13s
|
|
Info: of which strict legalisation: 11.27s
|
|
|
|
Info: Running simulated annealing placer for refinement.
|
|
Info: at iteration #1: temp = 0.000000, timing cost = 528, wirelen = 6264
|
|
Info: at iteration #5: temp = 0.000000, timing cost = 398, wirelen = 5227
|
|
Info: at iteration #10: temp = 0.000000, timing cost = 417, wirelen = 4858
|
|
Info: at iteration #15: temp = 0.000000, timing cost = 415, wirelen = 4546
|
|
Info: at iteration #20: temp = 0.000000, timing cost = 419, wirelen = 4408
|
|
Info: at iteration #25: temp = 0.000000, timing cost = 396, wirelen = 4307
|
|
Info: at iteration #26: temp = 0.000000, timing cost = 365, wirelen = 4299
|
|
Info: SA placement time 2.92s
|
|
|
|
Info: Max frequency for clock 'r_counter_$glb_clk': 91.19 MHz (PASS at 64.00 MHz)
|
|
Info: Max frequency for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk': 126.92 MHz (PASS at 12.00 MHz)
|
|
Info: Max frequency for clock 'i_sck$SB_IO_IN': 219.78 MHz (PASS at 5.00 MHz)
|
|
Info: Max frequency for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk': 168.10 MHz (PASS at 16.00 MHz)
|
|
Info: Max frequency for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': 62.38 MHz (PASS at 12.00 MHz)
|
|
Info: Max frequency for clock 'i_glob_clock$SB_IO_IN': 463.61 MHz (PASS at 12.00 MHz)
|
|
|
|
Info: Max delay <async> -> <async> : 5.93 ns
|
|
Info: Max delay <async> -> posedge i_glob_clock$SB_IO_IN : 7.95 ns
|
|
Info: Max delay <async> -> posedge i_sck$SB_IO_IN : 4.91 ns
|
|
Info: Max delay <async> -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 9.07 ns
|
|
Info: Max delay <async> -> posedge r_counter_$glb_clk : 8.64 ns
|
|
Info: Max delay <async> -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 9.15 ns
|
|
Info: Max delay <async> -> negedge smi_ctrl_ins.swe_and_reset_$glb_clk: 8.89 ns
|
|
Info: Max delay posedge i_glob_clock$SB_IO_IN -> posedge r_counter_$glb_clk : 3.53 ns
|
|
Info: Max delay posedge i_sck$SB_IO_IN -> posedge r_counter_$glb_clk : 2.35 ns
|
|
Info: Max delay posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -> posedge r_counter_$glb_clk : 3.44 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> <async> : 5.70 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> posedge i_glob_clock$SB_IO_IN : 7.15 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 9.08 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.41 ns
|
|
Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> <async> : 3.36 ns
|
|
Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 3.61 ns
|
|
Info: Max delay negedge smi_ctrl_ins.swe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 4.14 ns
|
|
|
|
Info: Slack histogram:
|
|
Info: legend: * represents 20 endpoint(s)
|
|
Info: + represents [1,20) endpoint(s)
|
|
Info: [ 3667, 13376) |****************************************+
|
|
Info: [ 13376, 23085) |**+
|
|
Info: [ 23085, 32794) |***+
|
|
Info: [ 32794, 42503) |***********+
|
|
Info: [ 42503, 52212) |
|
|
Info: [ 52212, 61921) |***+
|
|
Info: [ 61921, 71630) |+
|
|
Info: [ 71630, 81339) |************************************************************
|
|
Info: [ 81339, 91048) |+
|
|
Info: [ 91048, 100757) |
|
|
Info: [100757, 110466) |
|
|
Info: [110466, 120175) |
|
|
Info: [120175, 129884) |
|
|
Info: [129884, 139593) |
|
|
Info: [139593, 149302) |
|
|
Info: [149302, 159011) |
|
|
Info: [159011, 168720) |
|
|
Info: [168720, 178429) |
|
|
Info: [178429, 188138) |
|
|
Info: [188138, 197847) |**+
|
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Info: Checksum: 0x9ea9b6cc
|
|
|
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Info: Routing..
|
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Info: Setting up routing queue.
|
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Info: Routing 2787 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
|
|
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
|
Info: 1000 | 161 824 | 161 824 | 1969| 0.88 0.88|
|
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Info: 2000 | 435 1522 | 274 698 | 1303| 0.54 1.42|
|
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Info: 3000 | 835 2119 | 400 597 | 834| 0.90 2.32|
|
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Info: 4000 | 1118 2833 | 283 714 | 186| 0.74 3.07|
|
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Info: 4336 | 1225 3063 | 107 230 | 0| 0.41 3.48|
|
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Info: Routing complete.
|
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Info: Router1 time 3.48s
|
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Info: Checksum: 0xd1a3ff27
|
|
|
|
Info: Critical path report for clock 'r_counter_$glb_clk' (posedge -> posedge):
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_8_LC.O
|
|
Info: 0.9 1.7 Net rx_fifo.rd_addr[0] budget 2.072000 ns (4,9) -> (5,9)
|
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Info: Sink $nextpnr_ICESTORM_LC_3.I1
|
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Info: Defined in:
|
|
Info: top.v:354.5-367.4
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Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.4 2.0 Source $nextpnr_ICESTORM_LC_3.COUT
|
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Info: 0.0 2.0 Net $nextpnr_ICESTORM_LC_3$O budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_7_LC.CIN
|
|
Info: 0.2 2.2 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_7_LC.COUT
|
|
Info: 0.0 2.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_6_LC.CIN
|
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Info: Defined in:
|
|
Info: top.v:354.5-367.4
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Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 2.4 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_6_LC.COUT
|
|
Info: 0.0 2.4 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_5_LC.CIN
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|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 2.6 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_5_LC.COUT
|
|
Info: 0.0 2.6 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_4_LC.CIN
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 2.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_4_LC.COUT
|
|
Info: 0.0 2.8 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_3_LC.CIN
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 3.0 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_3_LC.COUT
|
|
Info: 0.0 3.0 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_2_LC.CIN
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 3.2 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_2_LC.COUT
|
|
Info: 0.0 3.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] budget 0.000000 ns (5,9) -> (5,9)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_1_LC.CIN
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 3.3 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_1_LC.COUT
|
|
Info: 0.3 3.6 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] budget 0.290000 ns (5,9) -> (5,10)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_LC.CIN
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.2 3.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_LC.COUT
|
|
Info: 0.4 4.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] budget 0.380000 ns (5,10) -> (5,10)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.5 4.7 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_LC.O
|
|
Info: 0.9 5.5 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] budget 2.084000 ns (5,10) -> (5,11)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_O_LC.I2
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:73.15-73.29
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27
|
|
Info: 0.6 6.1 Source rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 7.0 Net rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] budget 2.084000 ns (5,11) -> (5,11)
|
|
Info: Sink rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_O_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 7.4 Source rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 8.3 Net rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] budget 2.084000 ns (5,11) -> (4,11)
|
|
Info: Sink rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 8.8 Source rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.O
|
|
Info: 2.0 10.7 Net rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] budget 2.083000 ns (4,11) -> (4,6)
|
|
Info: Sink rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 11.3 Setup rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.I2
|
|
Info: 5.2 ns logic, 6.1 ns routing
|
|
|
|
Info: Critical path report for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk' (negedge -> negedge):
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D_SB_LUT4_O_LC.O
|
|
Info: 1.9 2.7 Net smi_ctrl_ins.tx_reg_state[3] budget 27.108000 ns (11,2) -> (7,2)
|
|
Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.I3
|
|
Info: 0.5 3.1 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.O
|
|
Info: 1.9 5.0 Net smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] budget 27.107000 ns (7,2) -> (5,3)
|
|
Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 5.6 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.O
|
|
Info: 2.9 8.5 Net smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O budget 13.514000 ns (5,3) -> (9,4)
|
|
Info: Sink smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN
|
|
Info: 0.1 8.6 Setup smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN
|
|
Info: 1.9 ns logic, 6.7 ns routing
|
|
|
|
Info: Critical path report for clock 'i_sck$SB_IO_IN' (posedge -> posedge):
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 1.7 Net spi_if_ins.spi.r_rx_bit_count[0] budget 41.667000 ns (9,8) -> (9,9)
|
|
Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1
|
|
Info: Defined in:
|
|
Info: top.v:111.10-126.4
|
|
Info: spi_slave.v:32.25-32.43
|
|
Info: spi_if.v:43.13-54.4
|
|
Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
|
|
Info: 0.6 2.3 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 3.1 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] budget 41.666000 ns (9,9) -> (9,10)
|
|
Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 3.6 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.O
|
|
Info: 1.9 5.5 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O budget 66.016998 ns (9,10) -> (9,11)
|
|
Info: Sink spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN
|
|
Info: 0.1 5.6 Setup spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN
|
|
Info: 1.9 ns logic, 3.7 ns routing
|
|
|
|
Info: Critical path report for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk' (negedge -> negedge):
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 1.7 Net smi_ctrl_ins.int_cnt_rx[3] budget 30.507999 ns (2,6) -> (1,7)
|
|
Info: Sink smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.I1
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 2.3 Source smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.O
|
|
Info: 2.9 5.2 Net smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E budget 15.342000 ns (1,7) -> (4,8)
|
|
Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN
|
|
Info: 0.1 5.3 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN
|
|
Info: 1.5 ns logic, 3.8 ns routing
|
|
|
|
Info: Critical path report for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk' (negedge -> posedge):
|
|
Info: curr total
|
|
Info: 0.2 0.2 Source iq_rx_24.D_IN_1
|
|
Info: 1.9 2.1 Net w_lvds_rx_24_d1 budget 13.403000 ns (0,13) -> (2,11)
|
|
Info: Sink w_lvds_rx_24_d1_SB_LUT4_I1_LC.I1
|
|
Info: Defined in:
|
|
Info: top.v:300.8-300.23
|
|
Info: 0.6 2.7 Source w_lvds_rx_24_d1_SB_LUT4_I1_LC.O
|
|
Info: 1.9 4.6 Net w_lvds_rx_24_d1_SB_LUT4_I1_O[2] budget 13.403000 ns (2,11) -> (6,8)
|
|
Info: Sink w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 5.1 Source w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_LC.O
|
|
Info: 3.6 8.7 Net w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O budget 13.403000 ns (6,8) -> (12,6)
|
|
Info: Sink lvds_rx_24_inst.r_state_if_SB_LUT4_I2_11_LC.CEN
|
|
Info: 0.1 8.8 Setup lvds_rx_24_inst.r_state_if_SB_LUT4_I2_11_LC.CEN
|
|
Info: 1.5 ns logic, 7.4 ns routing
|
|
|
|
Info: Critical path report for clock 'i_glob_clock$SB_IO_IN' (posedge -> posedge):
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.O
|
|
Info: 0.9 1.7 Net r_counter budget 82.042999 ns (12,5) -> (12,5)
|
|
Info: Sink r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:393.8-393.23
|
|
Info: 0.5 2.2 Setup r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I3
|
|
Info: 1.3 ns logic, 0.9 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> '<async>':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_smi_a2$sb_io.D_IN_0
|
|
Info: 3.4 3.4 Net i_smi_a2$SB_IO_IN budget 41.433998 ns (1,17) -> (5,3)
|
|
Info: Sink o_smi_read_req_SB_LUT4_O_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:74.11-74.19
|
|
Info: 0.5 3.9 Source o_smi_read_req_SB_LUT4_O_LC.O
|
|
Info: 2.3 6.2 Net o_smi_read_req$SB_IO_OUT budget 40.973999 ns (5,3) -> (13,3)
|
|
Info: Sink o_smi_read_req$sb_io.D_OUT_0
|
|
Info: Defined in:
|
|
Info: top.v:81.12-81.26
|
|
Info: 0.5 ns logic, 5.7 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'posedge i_glob_clock$SB_IO_IN':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0
|
|
Info: 2.5 2.5 Net i_rst_b$SB_IO_IN budget 4.717000 ns (7,17) -> (11,9)
|
|
Info: Sink i_rst_b_SB_LUT4_I3_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:401.5-417.4
|
|
Info: complex_fifo.v:6.28-6.38
|
|
Info: 0.5 2.9 Source i_rst_b_SB_LUT4_I3_LC.O
|
|
Info: 0.9 3.9 Net i_rst_b_SB_LUT4_I3_O budget 4.717000 ns (11,9) -> (13,9)
|
|
Info: Sink $gbuf_i_rst_b_SB_LUT4_I3_O_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER
|
|
Info: 0.9 4.8 Source $gbuf_i_rst_b_SB_LUT4_I3_O_$glb_sr.GLOBAL_BUFFER_OUTPUT
|
|
Info: 0.7 5.5 Net i_rst_b_SB_LUT4_I3_O_$glb_sr budget 27.285999 ns (13,9) -> (12,5)
|
|
Info: Sink r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR
|
|
Info: 0.1 5.6 Setup r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR
|
|
Info: 1.5 ns logic, 4.1 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'posedge i_sck$SB_IO_IN':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_ss$sb_io.D_IN_0
|
|
Info: 2.9 2.9 Net i_ss$SB_IO_IN budget 83.333000 ns (12,0) -> (9,10)
|
|
Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 3.5 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.O
|
|
Info: 1.9 5.4 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O budget 66.016998 ns (9,10) -> (9,11)
|
|
Info: Sink spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN
|
|
Info: 0.1 5.5 Setup spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN
|
|
Info: 0.7 ns logic, 4.8 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0
|
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Info: 2.9 2.9 Net i_rst_b$SB_IO_IN budget 27.362000 ns (7,17) -> (5,7)
|
|
Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2_SB_LUT4_O_LC.I1
|
|
Info: Defined in:
|
|
Info: top.v:401.5-417.4
|
|
Info: complex_fifo.v:6.28-6.38
|
|
Info: 0.6 3.5 Source lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2_SB_LUT4_O_LC.O
|
|
Info: 0.9 4.4 Net lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] budget 27.107000 ns (5,7) -> (6,8)
|
|
Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 4.9 Source lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_LC.O
|
|
Info: 2.3 7.2 Net lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R budget 27.107000 ns (6,8) -> (7,13)
|
|
Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR
|
|
Info: 0.1 7.3 Setup lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR
|
|
Info: 1.2 ns logic, 6.0 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_ss$sb_io.D_IN_0
|
|
Info: 3.3 3.3 Net i_ss$SB_IO_IN budget 4.834000 ns (12,0) -> (6,9)
|
|
Info: Sink spi_if_ins.r_tx_data_valid_SB_LUT4_I3_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 3.9 Source spi_if_ins.r_tx_data_valid_SB_LUT4_I3_LC.O
|
|
Info: 0.9 4.7 Net spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O budget 4.600000 ns (6,9) -> (7,9)
|
|
Info: Sink spi_if_ins.spi.SCKr_SB_LUT4_I1_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 5.2 Source spi_if_ins.spi.SCKr_SB_LUT4_I1_LC.O
|
|
Info: 2.8 8.0 Net spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E budget 4.600000 ns (7,9) -> (11,9)
|
|
Info: Sink spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_LC.CEN
|
|
Info: 0.1 8.1 Setup spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_LC.CEN
|
|
Info: 1.1 ns logic, 7.0 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0
|
|
Info: 3.4 3.4 Net i_rst_b$SB_IO_IN budget 15.343000 ns (7,17) -> (1,7)
|
|
Info: Sink smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:401.5-417.4
|
|
Info: complex_fifo.v:6.28-6.38
|
|
Info: 0.5 3.9 Source smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.O
|
|
Info: 2.9 6.8 Net smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E budget 15.342000 ns (1,7) -> (4,8)
|
|
Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN
|
|
Info: 0.1 6.9 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN
|
|
Info: 0.6 ns logic, 6.4 ns routing
|
|
|
|
Info: Critical path report for cross-domain path '<async>' -> 'negedge smi_ctrl_ins.swe_and_reset_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0
|
|
Info: 2.9 2.9 Net i_rst_b$SB_IO_IN budget 13.515000 ns (7,17) -> (6,2)
|
|
Info: Sink smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E_SB_LUT4_O_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:401.5-417.4
|
|
Info: complex_fifo.v:6.28-6.38
|
|
Info: 0.5 3.3 Source smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E_SB_LUT4_O_LC.O
|
|
Info: 0.9 4.2 Net smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] budget 13.514000 ns (6,2) -> (5,3)
|
|
Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 4.7 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.O
|
|
Info: 2.9 7.6 Net smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O budget 13.514000 ns (5,3) -> (9,4)
|
|
Info: Sink smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN
|
|
Info: 0.1 7.7 Setup smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN
|
|
Info: 1.0 ns logic, 6.7 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge i_glob_clock$SB_IO_IN' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.O
|
|
Info: 1.7 2.5 Net r_tx_data[3] budget 14.139000 ns (12,12) -> (7,12)
|
|
Info: Sink spi_if_ins.r_tx_byte_SB_DFFE_Q_4_DFFLC.I0
|
|
Info: Defined in:
|
|
Info: top.v:111.10-126.4
|
|
Info: spi_if.v:9.22-9.32
|
|
Info: 0.7 3.1 Setup spi_if_ins.r_tx_byte_SB_DFFE_Q_4_DFFLC.I0
|
|
Info: 1.5 ns logic, 1.7 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge i_sck$SB_IO_IN' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_4_DFFLC.O
|
|
Info: 0.9 1.7 Net spi_if_ins.spi.r_rx_byte[3] budget 14.139000 ns (9,11) -> (8,11)
|
|
Info: Sink spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4_DFFLC.I0
|
|
Info: Defined in:
|
|
Info: top.v:111.10-126.4
|
|
Info: spi_slave.v:19.13-19.22
|
|
Info: spi_if.v:43.13-54.4
|
|
Info: 0.7 2.4 Setup spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4_DFFLC.I0
|
|
Info: 1.5 ns logic, 0.9 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source rx_fifo.wr_addr_gray_SB_DFFESR_Q_DFFLC.O
|
|
Info: 1.9 2.7 Net rx_fifo.wr_addr[9] budget 14.139000 ns (2,14) -> (4,15)
|
|
Info: Sink rx_fifo.wr_addr_gray_rd_SB_DFF_Q_DFFLC.I0
|
|
Info: Defined in:
|
|
Info: top.v:354.5-367.4
|
|
Info: complex_fifo.v:24.23-24.35
|
|
Info: 0.7 3.4 Setup rx_fifo.wr_addr_gray_rd_SB_DFF_Q_DFFLC.I0
|
|
Info: 1.5 ns logic, 1.9 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> '<async>':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.O
|
|
Info: 2.0 2.8 Net w_rx_fifo_empty budget 40.974998 ns (4,6) -> (5,3)
|
|
Info: Sink o_smi_read_req_SB_LUT4_O_LC.I1
|
|
Info: Defined in:
|
|
Info: top.v:347.8-347.23
|
|
Info: 0.6 3.3 Source o_smi_read_req_SB_LUT4_O_LC.O
|
|
Info: 2.3 5.6 Net o_smi_read_req$SB_IO_OUT budget 40.973999 ns (5,3) -> (13,3)
|
|
Info: Sink o_smi_read_req$sb_io.D_OUT_0
|
|
Info: Defined in:
|
|
Info: top.v:81.12-81.26
|
|
Info: 1.4 ns logic, 4.2 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'posedge i_glob_clock$SB_IO_IN':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source spi_if_ins.o_cs_SB_DFFESR_Q_D_SB_LUT4_O_2_LC.O
|
|
Info: 1.9 2.7 Net w_cs[3] budget 27.073000 ns (2,10) -> (6,12)
|
|
Info: Sink spi_if_ins.o_cs_SB_LUT4_I0_2_LC.I0
|
|
Info: Defined in:
|
|
Info: top.v:100.14-100.18
|
|
Info: 0.7 3.3 Source spi_if_ins.o_cs_SB_LUT4_I0_2_LC.O
|
|
Info: 0.9 4.2 Net spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] budget 27.073000 ns (6,12) -> (7,12)
|
|
Info: Sink r_tx_data_SB_DFFE_Q_E_SB_LUT4_O_LC.I2
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 4.8 Source r_tx_data_SB_DFFE_Q_E_SB_LUT4_O_LC.O
|
|
Info: 2.3 7.1 Net r_tx_data_SB_DFFE_Q_E budget 27.073000 ns (7,12) -> (12,12)
|
|
Info: Sink r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.CEN
|
|
Info: 0.1 7.2 Setup r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.CEN
|
|
Info: 2.1 ns logic, 5.0 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.r_channel_SB_DFFE_Q_DFFLC.O
|
|
Info: 1.4 2.2 Net channel budget 20.082001 ns (4,11) -> (4,14)
|
|
Info: Sink rx_fifo.wr_en_i_SB_LUT4_O_LC.I3
|
|
Info: Defined in:
|
|
Info: top.v:419.12-451.4
|
|
Info: smi_ctrl.v:106.9-106.18
|
|
Info: 0.5 2.7 Source rx_fifo.wr_en_i_SB_LUT4_O_LC.O
|
|
Info: 0.9 3.5 Net w_rx_fifo_push budget 20.082001 ns (4,14) -> (4,15)
|
|
Info: Sink rx_fifo.full_o_SB_LUT4_I3_LC.I0
|
|
Info: Defined in:
|
|
Info: top.v:342.8-342.22
|
|
Info: 0.7 4.2 Source rx_fifo.full_o_SB_LUT4_I3_LC.O
|
|
Info: 0.9 5.1 Net rx_fifo.full_o_SB_LUT4_I3_O[3] budget 20.082001 ns (4,15) -> (4,15)
|
|
Info: Sink rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_LC.I3
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.5 5.5 Source rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_LC.O
|
|
Info: 2.5 8.0 Net rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] budget 15.561000 ns (4,15) -> (4,5)
|
|
Info: Sink rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_LC.I1
|
|
Info: Defined in:
|
|
Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
|
|
Info: 0.6 8.6 Setup rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_LC.I1
|
|
Info: 3.0 ns logic, 5.6 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk':
|
|
Info: curr total
|
|
Info: 3.2 3.2 Source rx_fifo.mem_q.0.2_RAM.RDATA_13
|
|
Info: 3.0 6.1 Net w_rx_fifo_pulled_data[11] budget 27.396000 ns (3,15) -> (1,7)
|
|
Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_20_DFFLC.I0
|
|
Info: Defined in:
|
|
Info: top.v:419.12-451.4
|
|
Info: smi_ctrl.v:16.25-16.46
|
|
Info: 0.7 6.8 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_20_DFFLC.I0
|
|
Info: 3.9 ns logic, 3.0 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk' -> '<async>':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_LC.O
|
|
Info: 2.5 3.3 Net w_smi_data_output[3] budget 40.870998 ns (8,4) -> (7,0)
|
|
Info: Sink smi_io3.D_OUT_0
|
|
Info: Defined in:
|
|
Info: top.v:453.14-453.31
|
|
Info: 0.8 ns logic, 2.5 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D_SB_LUT4_O_LC.O
|
|
Info: 1.9 2.7 Net smi_ctrl_ins.w_fifo_pull_trigger budget 6.326000 ns (8,4) -> (4,6)
|
|
Info: Sink smi_ctrl_ins.r_fifo_pull_SB_DFFSR_Q_DFFLC.I0
|
|
Info: Defined in:
|
|
Info: top.v:419.12-451.4
|
|
Info: smi_ctrl.v:105.10-105.29
|
|
Info: 0.7 3.4 Setup smi_ctrl_ins.r_fifo_pull_SB_DFFSR_Q_DFFLC.I0
|
|
Info: 1.5 ns logic, 1.9 ns routing
|
|
|
|
Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.swe_and_reset_$glb_clk' -> 'posedge r_counter_$glb_clk':
|
|
Info: curr total
|
|
Info: 0.8 0.8 Source smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_17_DFFLC.O
|
|
Info: 3.5 4.3 Net w_tx_fifo_data[12] budget 6.917000 ns (6,2) -> (10,15)
|
|
Info: Sink tx_fifo.mem_q.0.3_RAM.WDATA_1
|
|
Info: Defined in:
|
|
Info: top.v:394.15-394.29
|
|
Info: 0.1 4.4 Setup tx_fifo.mem_q.0.3_RAM.WDATA_1
|
|
Info: 0.9 ns logic, 3.5 ns routing
|
|
|
|
Info: Max frequency for clock 'r_counter_$glb_clk': 88.45 MHz (PASS at 64.00 MHz)
|
|
Info: Max frequency for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk': 116.17 MHz (PASS at 12.00 MHz)
|
|
Info: Max frequency for clock 'i_sck$SB_IO_IN': 178.48 MHz (PASS at 5.00 MHz)
|
|
Info: Max frequency for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk': 189.29 MHz (PASS at 16.00 MHz)
|
|
Info: Max frequency for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': 56.50 MHz (PASS at 12.00 MHz)
|
|
Info: Max frequency for clock 'i_glob_clock$SB_IO_IN': 463.61 MHz (PASS at 12.00 MHz)
|
|
|
|
Info: Max delay <async> -> <async> : 6.18 ns
|
|
Info: Max delay <async> -> posedge i_glob_clock$SB_IO_IN : 5.56 ns
|
|
Info: Max delay <async> -> posedge i_sck$SB_IO_IN : 5.49 ns
|
|
Info: Max delay <async> -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 7.28 ns
|
|
Info: Max delay <async> -> posedge r_counter_$glb_clk : 8.12 ns
|
|
Info: Max delay <async> -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.95 ns
|
|
Info: Max delay <async> -> negedge smi_ctrl_ins.swe_and_reset_$glb_clk: 7.70 ns
|
|
Info: Max delay posedge i_glob_clock$SB_IO_IN -> posedge r_counter_$glb_clk : 3.15 ns
|
|
Info: Max delay posedge i_sck$SB_IO_IN -> posedge r_counter_$glb_clk : 2.35 ns
|
|
Info: Max delay posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -> posedge r_counter_$glb_clk : 3.37 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> <async> : 5.61 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> posedge i_glob_clock$SB_IO_IN : 7.16 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 8.61 ns
|
|
Info: Max delay posedge r_counter_$glb_clk -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.83 ns
|
|
Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> <async> : 3.25 ns
|
|
Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 3.37 ns
|
|
Info: Max delay negedge smi_ctrl_ins.swe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 4.41 ns
|
|
|
|
Info: Slack histogram:
|
|
Info: legend: * represents 20 endpoint(s)
|
|
Info: + represents [1,20) endpoint(s)
|
|
Info: [ 3397, 13120) |************************************+
|
|
Info: [ 13120, 22843) |****+
|
|
Info: [ 22843, 32566) |*****+
|
|
Info: [ 32566, 42289) |***********+
|
|
Info: [ 42289, 52012) |
|
|
Info: [ 52012, 61735) |***+
|
|
Info: [ 61735, 71458) |+
|
|
Info: [ 71458, 81181) |************************************************************
|
|
Info: [ 81181, 90904) |+
|
|
Info: [ 90904, 100627) |
|
|
Info: [100627, 110350) |
|
|
Info: [110350, 120073) |
|
|
Info: [120073, 129796) |
|
|
Info: [129796, 139519) |
|
|
Info: [139519, 149242) |
|
|
Info: [149242, 158965) |
|
|
Info: [158965, 168688) |
|
|
Info: [168688, 178411) |
|
|
Info: [178411, 188134) |
|
|
Info: [188134, 197857) |**+
|
|
|
|
Info: Program finished normally.
|
|
icepack top.asc top.bin
|