kopia lustrzana https://github.com/cariboulabs/cariboulite
5282 wiersze
447 KiB
Plaintext
5282 wiersze
447 KiB
Plaintext
# Generated by Yosys 0.39+0 (git sha1 18cec2d9a, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
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.model top
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.inputs i_glob_clock i_rst_b i_iq_rx_09_p i_iq_rx_24_n i_iq_rx_clk_p i_config[0] i_config[1] i_config[2] i_config[3] i_button io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] i_smi_a2 i_smi_a3 i_smi_soe_se i_smi_swe_srw io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] i_mosi i_sck i_ss
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.outputs o_rx_h_tx_l o_rx_h_tx_l_b o_tr_vc1 o_tr_vc1_b o_tr_vc2 o_shdn_rx_lna o_shdn_tx_lna o_iq_tx_p o_iq_tx_n o_iq_tx_clk_p o_iq_tx_clk_n o_mixer_fm o_mixer_en io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] o_led0 o_led1 io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] o_smi_write_req o_smi_read_req o_miso
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.names $false
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.names $true
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1
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.names $undef
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.gate SB_LUT4 I0=$false I1=i_button I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 1100000011111111
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.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 0001010100111111
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.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=i_config_SB_LUT4_I0_1_O[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 0001010100111111
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.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=i_config_SB_LUT4_I0_1_O[1]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
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.param LUT_INIT 1111000000000000
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.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=i_config_SB_LUT4_I0_1_O[3]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 0000110000000000
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.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 1111001100110011
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.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_rst_b O=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
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.param LUT_INIT 0000000011111111
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.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_ss O=o_miso_$_TBUF__Y_E
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
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.param LUT_INIT 0000000011111111
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.gate SB_DFFESR C=r_counter D=io_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=io_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
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.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=io_ctrl_ins.i_cs_SB_DFFESR_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
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.param LUT_INIT 0000111100000000
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.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 0000111111001100
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.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 1111001110101010
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.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 1011100000000000
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.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 0000000000111111
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.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
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.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
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.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
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.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] R=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
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.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] R=i_rst_b_SB_LUT4_I3_O
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
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.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
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.param LUT_INIT 0000000000001111
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.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 0011000000000000
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.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 0000000000001100
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.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 0000000000001000
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.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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.param LUT_INIT 1100111111111111
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.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 0011110010101010
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.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_ctrl_ins.pmod_state[0] I2=io_ctrl_ins.mixer_en_state I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led0_SB_LUT4_I1_O[2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 1110010000000000
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.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
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.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
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.gate SB_LUT4 I0=i_config[0] I1=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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.param LUT_INIT 1111100011111111
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.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
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.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110011111111
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111001100000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000111111
|
|
.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111001011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111001011111111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=i_config[2] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000011111111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000010001000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000100010000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000010000000
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000011111100
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=i_config_SB_LUT4_I0_1_O[1] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000011111111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111111100001100
|
|
.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001100000000000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001010100111111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[4] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000011111100
|
|
.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=i_config_SB_LUT4_I0_1_O[1] I2=i_config_SB_LUT4_I0_1_O[2] I3=i_config_SB_LUT4_I0_1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111111110001111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[5] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111111100001100
|
|
.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000111000000000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001010100111111
|
|
.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0011110010101010
|
|
.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1011100000000000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101111100010011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=io_pmod[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:293.7-298.4"
|
|
.param IO_STANDARD "SB_LVDS_INPUT"
|
|
.param NEG_TRIGGER 0
|
|
.param PIN_TYPE 000000
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_24_n
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:278.7-284.4"
|
|
.param IO_STANDARD "SB_LVDS_INPUT"
|
|
.param NEG_TRIGGER 0
|
|
.param PIN_TYPE 000000
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=lvds_clock PACKAGE_PIN=i_iq_rx_clk_p
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:260.7-263.4"
|
|
.param IO_STANDARD "SB_LVDS_INPUT"
|
|
.param PIN_TYPE 000001
|
|
.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=io_pmod[0] PACKAGE_PIN=o_iq_tx_clk_n
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:339.5-342.4"
|
|
.param IO_STANDARD "SB_LVCMOS"
|
|
.param PIN_TYPE 011001
|
|
.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=lvds_clock PACKAGE_PIN=o_iq_tx_clk_p
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:330.5-333.4"
|
|
.param IO_STANDARD "SB_LVCMOS"
|
|
.param PIN_TYPE 011001
|
|
.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_n
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:319.5-324.4"
|
|
.param IO_STANDARD "SB_LVCMOS"
|
|
.param PIN_TYPE 010000
|
|
.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_p
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:308.5-313.4"
|
|
.param IO_STANDARD "SB_LVCMOS"
|
|
.param PIN_TYPE 010000
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100010000010
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0111001101010000
|
|
.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001000101000
|
|
.gate SB_CARRY CI=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 CO=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I1=$true
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101000011011101
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011000000000000
|
|
.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000000010
|
|
.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1100101010101010
|
|
.gate SB_LUT4 I0=$false I1=io_pmod[7] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] O=lvds_rx_09_inst.i_sync_input
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=sys_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000000000
|
|
.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0111011100100000
|
|
.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010011010101111
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.i_cs I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100000000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFE C=lvds_clock D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011111100001111
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d1 I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000000010
|
|
.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000000110011
|
|
.gate SB_LUT4 I0=$false I1=io_pmod[6] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100111111000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFNESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_tx.v:58.5-128.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.empty_o O=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110000001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000110000
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[6] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1001000000000000
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr[8] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr[6] I2=tx_fifo.wr_addr_gray_rd_r[6] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[8] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0011101010100011
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1001100111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000001111
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[6] I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[5] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100000111100
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=lvds_tx_inst.r_pulled O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led0 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led0_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001101011111
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_DFFER_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000000000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001101011111
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led1_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1011100000000000
|
|
.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso
|
|
.attr src "top.v:150.19-150.43"
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=rx_fifo.empty_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000111100110011
|
|
.gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010111000001100
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] O=r_tx_data_SB_DFFE_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110011111111
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010111000001100
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010111000001100
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111001011111111
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[2] I1=io_ctrl_ins.o_data_out[2] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001101011111
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110011111111
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001101011111
|
|
.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_7_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111001011111111
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001101011111
|
|
.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000000100
|
|
.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110011111111
|
|
.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000111111
|
|
.gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105"
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1110110011001100
|
|
.gate SB_LUT4 I0=rx_fifo.empty_o I1=rx_fifo.wr_addr_gray_rd_r[0] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.empty_o_SB_LUT4_I0_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000010000010
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100110000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1110011101111110
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000001101001
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.rd_addr[6] I2=rx_fifo.wr_addr_gray_rd_r[6] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001010011010111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr[5] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000001111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000001111
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] O=rx_fifo.empty_o_SB_LUT4_I0_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000011111001
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001010000111100
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000001101111
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110000000000110
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100001100000000
|
|
.gate SB_DFFSR C=lvds_clock D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111111110000000
|
|
.gate SB_LUT4 I0=rx_fifo.full_o I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000101000000010
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O[0] I2=rx_fifo.full_o_SB_LUT4_I0_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[7] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000001001
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010000000000000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000001001
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.wr_addr[1] I2=rx_fifo.rd_addr_gray_wr_r[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100000111100
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011000000000000
|
|
.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=rx_fifo.full_o_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101000011011101
|
|
.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010101000101010
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O CO=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I1=$true
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100010000010
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001000101000
|
|
.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.mem_i.0.0_WCLKE O=rx_fifo.wr_addr_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100111111000000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[20] I2=lvds_rx_09_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[23] I2=lvds_rx_09_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[24] I2=lvds_rx_09_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[30] I2=lvds_rx_09_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[31] I2=lvds_rx_09_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[1] I2=lvds_rx_24_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[2] I2=lvds_rx_24_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[3] I2=lvds_rx_09_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[5] I2=lvds_rx_09_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[7] I2=lvds_rx_09_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[8] I2=lvds_rx_24_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
|
|
.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
|
.param READ_MODE 10
|
|
.param WRITE_MODE 10
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111000011001100
|
|
.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[7]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[5]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[4]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000000001000000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[3]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[5] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=rx_fifo.empty_o_SB_LUT4_I0_O[0] I1=rx_fifo.empty_o_SB_LUT4_I0_O[1] I2=rx_fifo.empty_o_SB_LUT4_I0_O[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000110000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1001000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[1]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100000111100
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110000000000000
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[5] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 I0=$false I1=rx_fifo.wr_addr[3]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[2]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000010010
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[6]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[7]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000001100
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000001111
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[8] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000111100
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[5]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000001100
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000001100
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[7]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[1]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0001001100110001
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010001011110011
|
|
.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000011101011
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[4] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[9] Q=rx_fifo.wr_addr_gray_rd[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[8] Q=rx_fifo.wr_addr_gray_rd[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[7] Q=rx_fifo.wr_addr_gray_rd[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[6] Q=rx_fifo.wr_addr_gray_rd[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[5] Q=rx_fifo.wr_addr_gray_rd[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[4] Q=rx_fifo.wr_addr_gray_rd[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[3] Q=rx_fifo.wr_addr_gray_rd[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[2] Q=rx_fifo.wr_addr_gray_rd[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[1] Q=rx_fifo.wr_addr_gray_rd[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[0] Q=rx_fifo.wr_addr_gray_rd[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[9] Q=rx_fifo.wr_addr_gray_rd_r[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[8] Q=rx_fifo.wr_addr_gray_rd_r[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[7] Q=rx_fifo.wr_addr_gray_rd_r[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[6] Q=rx_fifo.wr_addr_gray_rd_r[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[5] Q=rx_fifo.wr_addr_gray_rd_r[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[4] Q=rx_fifo.wr_addr_gray_rd_r[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[3] Q=rx_fifo.wr_addr_gray_rd_r[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[2] Q=rx_fifo.wr_addr_gray_rd_r[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[1] Q=rx_fifo.wr_addr_gray_rd_r[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[0] Q=rx_fifo.wr_addr_gray_rd_r[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFFESR C=r_counter D=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
|
|
.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010000000000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000000011
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[14] I1=smi_ctrl_ins.r_fifo_pulled_data[6] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000101000001100
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[30] I1=smi_ctrl_ins.r_fifo_pulled_data[22] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[13] I1=smi_ctrl_ins.r_fifo_pulled_data[5] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000101000001100
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[29] I1=smi_ctrl_ins.r_fifo_pulled_data[21] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[12] I1=smi_ctrl_ins.r_fifo_pulled_data[4] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000101000001100
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[28] I1=smi_ctrl_ins.r_fifo_pulled_data[20] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010001100100000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[27] I1=smi_ctrl_ins.r_fifo_pulled_data[19] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[10] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[2] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010001100100000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[26] I1=smi_ctrl_ins.r_fifo_pulled_data[18] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[9] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010001100100000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[25] I1=smi_ctrl_ins.r_fifo_pulled_data[17] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[8] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[0] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010001100100000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[24] I1=smi_ctrl_ins.r_fifo_pulled_data[16] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[15] I1=smi_ctrl_ins.r_fifo_pulled_data[7] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000101000001100
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[31] I1=smi_ctrl_ins.r_fifo_pulled_data[23] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010000011000000
|
|
.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I2[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000000000
|
|
.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=smi_ctrl_ins.r_fifo_pull_1 I3=smi_ctrl_ins.r_fifo_pull O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_pull_trigger Q=smi_ctrl_ins.r_fifo_pull R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[31] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[31] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[30] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[30] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[21] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[21] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[20] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[20] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[19] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[19] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[18] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[18] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[17] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[17] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[16] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[16] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[15] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[15] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[14] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[14] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[13] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[13] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[12] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[12] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[29] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[29] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[11] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[11] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[10] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[10] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[9] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[9] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[8] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[7] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[6] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[5] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[4] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[3] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[2] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[28] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[28] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[1] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[0] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[27] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[27] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[26] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[26] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[25] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[25] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[24] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[24] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[23] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[23] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[22] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[22] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_push Q=smi_ctrl_ins.r_fifo_push_1 R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push I3=smi_ctrl_ins.r_fifo_push_1 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr[2] I2=tx_fifo.rd_addr_gray_wr_r[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110000000000
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100000111100
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0011001101011010
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010000000000000
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000000000
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0010100000111100
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011110011000011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[5]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[7]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 I0=$false I1=tx_fifo.wr_addr[8]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001010111110
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2]
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000001111011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_push_trigger Q=smi_ctrl_ins.r_fifo_push R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_smi_soe_se I3=i_rst_b O=smi_ctrl_ins.soe_and_reset
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_smi_swe_srw I3=i_rst_b O=smi_ctrl_ins.swe_and_reset
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D Q=smi_ctrl_ins.tx_reg_state[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D Q=smi_ctrl_ins.tx_reg_state[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D Q=smi_ctrl_ins.tx_reg_state[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D Q=smi_ctrl_ins.tx_reg_state[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_LUT4 I0=i_rst_b I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000100000001010
|
|
.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[2] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011000000
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.w_fifo_pull_trigger
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_DFFNSR C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D Q=smi_ctrl_ins.w_fifo_push_trigger R=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "smi_ctrl.v:189.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.i_smi_data_in[7] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011001100111111
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:526.5-531.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:535.5-540.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:544.5-549.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:553.5-558.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:562.5-567.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:571.5-576.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:580.5-585.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:589.5-594.4"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 0
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111000000000000
|
|
.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1111111011101000
|
|
.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000010111
|
|
.gate SB_DFFER C=r_counter D=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
|
|
.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000111111
|
|
.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000000010
|
|
.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000010000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_cs_SB_LUT4_I0_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[7] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[6] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[5] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_fetch_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111100001111
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0011000000000000
|
|
.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010100000100000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000011110011
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_load_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101011100000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 1111111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000000001111
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] O=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111110000000000
|
|
.gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[1] Q=spi_if_ins.spi.SCKr[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[0] Q=spi_if_ins.spi.SCKr[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=i_sck Q=spi_if_ins.spi.SCKr[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.SCKr[2] I2=spi_if_ins.spi.SCKr[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111111100110000
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[7] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[6] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[5] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[4] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[3] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[2] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[1] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[0] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFF C=r_counter D=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_data_valid
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000001000
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.o_spi_miso
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000011001111
|
|
.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010100011111101
|
|
.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[7] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101001100000000
|
|
.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[6] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000001010011
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1111110000110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_byte[0] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000000011
|
|
.gate SB_DFF C=r_counter D=spi_if_ins.spi.r_rx_done Q=spi_if_ins.spi.r2_rx_done
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=spi_if_ins.spi.r2_rx_done Q=spi_if_ins.spi.r3_rx_done
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r3_rx_done I3=spi_if_ins.spi.r2_rx_done O=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D Q=spi_if_ins.spi.r_rx_bit_count[2] R=i_ss
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D Q=spi_if_ins.spi.r_rx_bit_count[1] R=i_ss
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D Q=spi_if_ins.spi.r_rx_bit_count[0] R=i_ss
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=spi_if_ins.spi.r_rx_bit_count[0] CO=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1]
|
|
.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[6] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=i_mosi E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFESR C=i_sck D=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_rx_done R=i_ss
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111100000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=i_ss I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1110101010111010
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFE C=i_sck D=i_mosi E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[2] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
|
|
.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[1] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=$true I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=$true I3=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=spi_if_ins.spi.r_tx_bit_count[0] CO=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 I0=spi_if_ins.spi.r_tx_bit_count[1] I1=$true
|
|
.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[7] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[7] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[6] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[6] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[5] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[5] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[4] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[4] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[3] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[3] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[2] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[2] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[1] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[1] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110011110000
|
|
.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000110000000000
|
|
.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=spi_if_ins.state_if_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000000000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000000001111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000000110000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000000011000000
|
|
.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 0000001100000000
|
|
.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D[2] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.state_if_SB_DFFESR_Q_E
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0101010111011111
|
|
.gate SB_DFFE C=r_counter D=sys_ctrl_ins.i_cs_SB_DFFE_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=sys_ctrl_ins.i_cs
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000000001111
|
|
.gate SB_DFFNSS C=lvds_clock D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105"
|
|
.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1110101010101010
|
|
.gate SB_LUT4 I0=lvds_tx_inst.r_pulled I1=tx_fifo.empty_o I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_gray[9] O=tx_fifo.empty_o_SB_LUT4_I1_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0100010000000100
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.empty_o_SB_LUT4_I1_O[1] I2=tx_fifo.empty_o_SB_LUT4_I1_O[2] I3=tx_fifo.empty_o_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000010010000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.empty_o_SB_LUT4_I1_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_LUT4_I1_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100001100000000
|
|
.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
|
|
.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1110101011000000
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100110000001100
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1010001011110011
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[7] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.empty_o_SB_LUT4_I1_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[7]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[8]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[5]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[4]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[3]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[2]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[1]
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.empty_o_SB_LUT4_I1_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1100111101000101
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[8] Q=tx_fifo.rd_addr_gray_wr[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[7] Q=tx_fifo.rd_addr_gray_wr[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[6] Q=tx_fifo.rd_addr_gray_wr[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[5] Q=tx_fifo.rd_addr_gray_wr[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[4] Q=tx_fifo.rd_addr_gray_wr[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[3] Q=tx_fifo.rd_addr_gray_wr[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[2] Q=tx_fifo.rd_addr_gray_wr[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[1] Q=tx_fifo.rd_addr_gray_wr[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[0] Q=tx_fifo.rd_addr_gray_wr[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[9] Q=tx_fifo.rd_addr_gray_wr_r[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[8] Q=tx_fifo.rd_addr_gray_wr_r[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[7] Q=tx_fifo.rd_addr_gray_wr_r[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[6] Q=tx_fifo.rd_addr_gray_wr_r[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[5] Q=tx_fifo.rd_addr_gray_wr_r[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[4] Q=tx_fifo.rd_addr_gray_wr_r[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[3] Q=tx_fifo.rd_addr_gray_wr_r[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[2] Q=tx_fifo.rd_addr_gray_wr_r[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[1] Q=tx_fifo.rd_addr_gray_wr_r[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100001100111100
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100000000001100
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[5]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[3]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[1]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1000001001000001
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 1100111101000101
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100001100111100
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000001101001
|
|
.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
|
|
.param LUT_INIT 1100001100111100
|
|
.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000000100011
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000111111110000
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
|
|
.param LUT_INIT 0000000011111111
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7]
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
|
|
.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000011111101
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
|
|
.param LUT_INIT 0000000011111101
|
|
.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] O=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
|
|
.param LUT_INIT 0000000011110000
|
|
.names tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
|
|
1 1
|
|
.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[0]
|
|
1 1
|
|
.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
|
|
1 1
|
|
.names i_rst_b io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
|
|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[2]
|
|
1 1
|
|
.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
|
|
1 1
|
|
.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1]
|
|
1 1
|
|
.names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[3]
|
|
1 1
|
|
.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names lvds_tx_inst.r_pulled tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
|
|
1 1
|
|
.names io_ctrl_ins.rf_pin_state[0] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
|
|
1 1
|
|
.names i_rst_b w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr[7] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0]
|
|
1 1
|
|
.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
1 1
|
|
.names tx_fifo.rd_addr[4] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[1]
|
|
1 1
|
|
.names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[5] spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[1]
|
|
1 1
|
|
.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
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1 1
|
|
.names rx_fifo.wr_addr[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1]
|
|
1 1
|
|
.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
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1 1
|
|
.names rx_fifo.rd_addr[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
|
|
1 1
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|
.names rx_fifo.rd_addr[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
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|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
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|
1 1
|
|
.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
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|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[0]
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|
1 1
|
|
.names $true rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[2]
|
|
1 1
|
|
.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[3]
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|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names rx_fifo.empty_o rx_fifo.empty_o_SB_LUT4_I0_I3[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.empty_o_SB_LUT4_I0_I3[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.empty_o_SB_LUT4_I0_I3[2]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names $true lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1]
|
|
1 1
|
|
.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
1 1
|
|
.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
|
|
1 1
|
|
.names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led1_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led1_SB_LUT4_I1_O[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names i_button io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
|
|
1 1
|
|
.names io_ctrl_ins.rf_pin_state[5] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names io_pmod[6] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
1 1
|
|
.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0]
|
|
1 1
|
|
.names i_config_SB_LUT4_I0_1_O[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr[8] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[8] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names i_config[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
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1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0]
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|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2]
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1 1
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|
.names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0]
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|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
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1 1
|
|
.names spi_if_ins.o_ioc[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[0]
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|
1 1
|
|
.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[1]
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|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
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|
1 1
|
|
.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
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|
1 1
|
|
.names spi_if_ins.o_load_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[1]
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|
1 1
|
|
.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
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1 1
|
|
.names io_ctrl_ins.tr_vc_1_b_state i_config_SB_LUT4_I0_1_O[0]
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|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
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|
1 1
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|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
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|
1 1
|
|
.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
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|
1 1
|
|
.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[0]
|
|
1 1
|
|
.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[0]
|
|
1 1
|
|
.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[1]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[3]
|
|
1 1
|
|
.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0]
|
|
1 1
|
|
.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
1 1
|
|
.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] spi_if_ins.state_if_SB_DFFESR_Q_D[1]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names i_config[1] o_led1_SB_LUT4_I1_I2[0]
|
|
1 1
|
|
.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I2[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] o_led1_SB_LUT4_I1_I2[3]
|
|
1 1
|
|
.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[0]
|
|
1 1
|
|
.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] o_led0_SB_LUT4_I1_O[0]
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led0_SB_LUT4_I1_O[1]
|
|
1 1
|
|
.names i_config[0] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
1 1
|
|
.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
|
|
1 1
|
|
.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[1]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
|
|
1 1
|
|
.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[1]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[1]
|
|
1 1
|
|
.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[2] rx_fifo.mem_q.0.0_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[1] rx_fifo.mem_q.0.0_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[3] rx_fifo.mem_q.0.0_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[10] rx_fifo.mem_q.0.2_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[9] rx_fifo.mem_q.0.2_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[5] rx_fifo.mem_q.0.1_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[30] rx_fifo.mem_i.0.3_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[29] rx_fifo.mem_i.0.3_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[25] rx_fifo.mem_i.0.2_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[27] rx_fifo.mem_i.0.2_RDATA[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[20] rx_fifo.mem_i.0.1_RDATA[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[22] rx_fifo.mem_i.0.1_RDATA[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[21] rx_fifo.mem_i.0.1_RDATA[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13]
|
|
1 1
|
|
.names smi_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
|
|
1 1
|
|
.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
1 1
|
|
.names spi_if_ins.spi.o_spi_miso int_miso
|
|
1 1
|
|
.names i_button io_ctrl_ins.i_button
|
|
1 1
|
|
.names i_config[0] io_ctrl_ins.i_config[0]
|
|
1 1
|
|
.names i_config[1] io_ctrl_ins.i_config[1]
|
|
1 1
|
|
.names i_config[2] io_ctrl_ins.i_config[2]
|
|
1 1
|
|
.names i_config[3] io_ctrl_ins.i_config[3]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[0] io_ctrl_ins.i_data_in[0]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[1] io_ctrl_ins.i_data_in[1]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[2] io_ctrl_ins.i_data_in[2]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[3] io_ctrl_ins.i_data_in[3]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[4] io_ctrl_ins.i_data_in[4]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[5] io_ctrl_ins.i_data_in[5]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[6] io_ctrl_ins.i_data_in[6]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[7] io_ctrl_ins.i_data_in[7]
|
|
1 1
|
|
.names spi_if_ins.o_fetch_cmd io_ctrl_ins.i_fetch_cmd
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] io_ctrl_ins.i_ioc[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] io_ctrl_ins.i_ioc[1]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[2] io_ctrl_ins.i_ioc[2]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[3] io_ctrl_ins.i_ioc[3]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[4] io_ctrl_ins.i_ioc[4]
|
|
1 1
|
|
.names spi_if_ins.o_load_cmd io_ctrl_ins.i_load_cmd
|
|
1 1
|
|
.names i_rst_b io_ctrl_ins.i_rst_b
|
|
1 1
|
|
.names r_counter io_ctrl_ins.i_sys_clk
|
|
1 1
|
|
.names o_led0 io_ctrl_ins.led0_state
|
|
1 1
|
|
.names o_led1 io_ctrl_ins.led1_state
|
|
1 1
|
|
.names o_led0 io_ctrl_ins.o_led0
|
|
1 1
|
|
.names o_led1 io_ctrl_ins.o_led1
|
|
1 1
|
|
.names $true io_ctrl_ins.o_mixer_en
|
|
1 1
|
|
.names $false io_ctrl_ins.o_mixer_fm
|
|
1 1
|
|
.names io_ctrl_ins.pmod_state[0] io_ctrl_ins.o_pmod[0]
|
|
1 1
|
|
.names io_ctrl_ins.pmod_state[1] io_ctrl_ins.o_pmod[1]
|
|
1 1
|
|
.names io_ctrl_ins.pmod_state[2] io_ctrl_ins.o_pmod[2]
|
|
1 1
|
|
.names io_ctrl_ins.pmod_state[3] io_ctrl_ins.o_pmod[3]
|
|
1 1
|
|
.names io_ctrl_ins.rx_h_state io_ctrl_ins.o_rx_h_tx_l
|
|
1 1
|
|
.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.o_rx_h_tx_l_b
|
|
1 1
|
|
.names io_ctrl_ins.lna_rx_shutdown_state io_ctrl_ins.o_shdn_rx_lna
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state io_ctrl_ins.o_shdn_tx_lna
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.o_tr_vc1
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_1_b_state io_ctrl_ins.o_tr_vc1_b
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_2_state io_ctrl_ins.o_tr_vc2
|
|
1 1
|
|
.names $false io_pmod[1]
|
|
1 1
|
|
.names $false io_pmod[2]
|
|
1 1
|
|
.names i_smi_swe_srw io_pmod[3]
|
|
1 1
|
|
.names lvds_clock lvds_clock_buf
|
|
1 1
|
|
.names lvds_clock lvds_rx_09_inst.i_ddr_clk
|
|
1 1
|
|
.names w_lvds_rx_09_d1 lvds_rx_09_inst.i_ddr_data[0]
|
|
1 1
|
|
.names w_lvds_rx_09_d0 lvds_rx_09_inst.i_ddr_data[1]
|
|
1 1
|
|
.names rx_fifo.full_o lvds_rx_09_inst.i_fifo_full
|
|
1 1
|
|
.names i_rst_b lvds_rx_09_inst.i_rst_b
|
|
1 1
|
|
.names lvds_clock lvds_rx_09_inst.o_fifo_write_clk
|
|
1 1
|
|
.names lvds_clock lvds_rx_24_inst.i_ddr_clk
|
|
1 1
|
|
.names rx_fifo.full_o lvds_rx_24_inst.i_fifo_full
|
|
1 1
|
|
.names i_rst_b lvds_rx_24_inst.i_rst_b
|
|
1 1
|
|
.names lvds_clock lvds_rx_24_inst.o_fifo_write_clk
|
|
1 1
|
|
.names $undef lvds_tx_inst.i_debug_lb
|
|
1 1
|
|
.names tx_fifo.empty_o lvds_tx_inst.i_fifo_empty
|
|
1 1
|
|
.names i_rst_b lvds_tx_inst.i_rst_b
|
|
1 1
|
|
.names $undef lvds_tx_inst.i_sample_gap[0]
|
|
1 1
|
|
.names $undef lvds_tx_inst.i_sample_gap[1]
|
|
1 1
|
|
.names $undef lvds_tx_inst.i_sample_gap[2]
|
|
1 1
|
|
.names $undef lvds_tx_inst.i_sample_gap[3]
|
|
1 1
|
|
.names $false lvds_tx_inst.o_ddr_data[0]
|
|
1 1
|
|
.names $false lvds_tx_inst.o_ddr_data[1]
|
|
1 1
|
|
.names lvds_tx_inst.r_pulled lvds_tx_inst.o_fifo_pull
|
|
1 1
|
|
.names $false lvds_tx_inst.o_sync_state_bit
|
|
1 1
|
|
.names $false lvds_tx_inst.o_tx_state_bit
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[0]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[1]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[2]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[3]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[4]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[5]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[6]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[7]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[8]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[9]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[10]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[11]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[12]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[13]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[14]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[15]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[16]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[17]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[18]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[19]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[20]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[21]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[22]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[23]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[24]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[25]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[26]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[27]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[28]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[29]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[30]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_fifo_data[31]
|
|
1 1
|
|
.names $false lvds_tx_inst.r_state
|
|
1 1
|
|
.names $undef o_mixer_en
|
|
1 1
|
|
.names $undef o_mixer_fm
|
|
1 1
|
|
.names io_ctrl_ins.rx_h_state o_rx_h_tx_l
|
|
1 1
|
|
.names io_ctrl_ins.rx_h_b_state o_rx_h_tx_l_b
|
|
1 1
|
|
.names io_ctrl_ins.lna_rx_shutdown_state o_shdn_rx_lna
|
|
1 1
|
|
.names io_ctrl_ins.lna_tx_shutdown_state o_shdn_tx_lna
|
|
1 1
|
|
.names $undef o_smi_write_req
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_1_state o_tr_vc1
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_1_b_state o_tr_vc1_b
|
|
1 1
|
|
.names io_ctrl_ins.tr_vc_2_state o_tr_vc2
|
|
1 1
|
|
.names $false rx_fifo.debug_pull
|
|
1 1
|
|
.names $false rx_fifo.debug_push
|
|
1 1
|
|
.names rx_fifo.rd_addr_gray[9] rx_fifo.rd_addr[9]
|
|
1 1
|
|
.names r_counter rx_fifo.rd_clk_i
|
|
1 1
|
|
.names i_rst_b rx_fifo.rd_rst_b_i
|
|
1 1
|
|
.names rx_fifo.wr_addr_gray[9] rx_fifo.wr_addr[9]
|
|
1 1
|
|
.names lvds_clock rx_fifo.wr_clk_i
|
|
1 1
|
|
.names i_rst_b rx_fifo.wr_rst_b_i
|
|
1 1
|
|
.names spi_if_ins.o_data_in[0] smi_ctrl_ins.i_data_in[0]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[1] smi_ctrl_ins.i_data_in[1]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[2] smi_ctrl_ins.i_data_in[2]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[3] smi_ctrl_ins.i_data_in[3]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[4] smi_ctrl_ins.i_data_in[4]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[5] smi_ctrl_ins.i_data_in[5]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[6] smi_ctrl_ins.i_data_in[6]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[7] smi_ctrl_ins.i_data_in[7]
|
|
1 1
|
|
.names spi_if_ins.o_fetch_cmd smi_ctrl_ins.i_fetch_cmd
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] smi_ctrl_ins.i_ioc[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] smi_ctrl_ins.i_ioc[1]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[2] smi_ctrl_ins.i_ioc[2]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[3] smi_ctrl_ins.i_ioc[3]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[4] smi_ctrl_ins.i_ioc[4]
|
|
1 1
|
|
.names spi_if_ins.o_load_cmd smi_ctrl_ins.i_load_cmd
|
|
1 1
|
|
.names i_rst_b smi_ctrl_ins.i_rst_b
|
|
1 1
|
|
.names rx_fifo.empty_o smi_ctrl_ins.i_rx_fifo_empty
|
|
1 1
|
|
.names rx_fifo.rd_data_o[0] smi_ctrl_ins.i_rx_fifo_pulled_data[0]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[1] smi_ctrl_ins.i_rx_fifo_pulled_data[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[2] smi_ctrl_ins.i_rx_fifo_pulled_data[2]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[3] smi_ctrl_ins.i_rx_fifo_pulled_data[3]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[4] smi_ctrl_ins.i_rx_fifo_pulled_data[4]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[5] smi_ctrl_ins.i_rx_fifo_pulled_data[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[6] smi_ctrl_ins.i_rx_fifo_pulled_data[6]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[7] smi_ctrl_ins.i_rx_fifo_pulled_data[7]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[8] smi_ctrl_ins.i_rx_fifo_pulled_data[8]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[9] smi_ctrl_ins.i_rx_fifo_pulled_data[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[10] smi_ctrl_ins.i_rx_fifo_pulled_data[10]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[11] smi_ctrl_ins.i_rx_fifo_pulled_data[11]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[12] smi_ctrl_ins.i_rx_fifo_pulled_data[12]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[13] smi_ctrl_ins.i_rx_fifo_pulled_data[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[14] smi_ctrl_ins.i_rx_fifo_pulled_data[14]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[15] smi_ctrl_ins.i_rx_fifo_pulled_data[15]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[16] smi_ctrl_ins.i_rx_fifo_pulled_data[16]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[17] smi_ctrl_ins.i_rx_fifo_pulled_data[17]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[18] smi_ctrl_ins.i_rx_fifo_pulled_data[18]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[19] smi_ctrl_ins.i_rx_fifo_pulled_data[19]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[20] smi_ctrl_ins.i_rx_fifo_pulled_data[20]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[21] smi_ctrl_ins.i_rx_fifo_pulled_data[21]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[22] smi_ctrl_ins.i_rx_fifo_pulled_data[22]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[23] smi_ctrl_ins.i_rx_fifo_pulled_data[23]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[24] smi_ctrl_ins.i_rx_fifo_pulled_data[24]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[25] smi_ctrl_ins.i_rx_fifo_pulled_data[25]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[26] smi_ctrl_ins.i_rx_fifo_pulled_data[26]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[27] smi_ctrl_ins.i_rx_fifo_pulled_data[27]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[28] smi_ctrl_ins.i_rx_fifo_pulled_data[28]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[29] smi_ctrl_ins.i_rx_fifo_pulled_data[29]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[30] smi_ctrl_ins.i_rx_fifo_pulled_data[30]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[31] smi_ctrl_ins.i_rx_fifo_pulled_data[31]
|
|
1 1
|
|
.names w_smi_data_input[0] smi_ctrl_ins.i_smi_data_in[0]
|
|
1 1
|
|
.names w_smi_data_input[1] smi_ctrl_ins.i_smi_data_in[1]
|
|
1 1
|
|
.names w_smi_data_input[2] smi_ctrl_ins.i_smi_data_in[2]
|
|
1 1
|
|
.names w_smi_data_input[3] smi_ctrl_ins.i_smi_data_in[3]
|
|
1 1
|
|
.names w_smi_data_input[4] smi_ctrl_ins.i_smi_data_in[4]
|
|
1 1
|
|
.names w_smi_data_input[5] smi_ctrl_ins.i_smi_data_in[5]
|
|
1 1
|
|
.names w_smi_data_input[6] smi_ctrl_ins.i_smi_data_in[6]
|
|
1 1
|
|
.names i_smi_soe_se smi_ctrl_ins.i_smi_soe_se
|
|
1 1
|
|
.names i_smi_swe_srw smi_ctrl_ins.i_smi_swe_srw
|
|
1 1
|
|
.names $false smi_ctrl_ins.i_smi_test
|
|
1 1
|
|
.names r_counter smi_ctrl_ins.i_sys_clk
|
|
1 1
|
|
.names tx_fifo.full_o smi_ctrl_ins.i_tx_fifo_full
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_rx[0]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_rx[1]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_rx[2]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[0]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[1]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[2]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[3]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[4]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[5]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[6]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[7]
|
|
1 1
|
|
.names $false smi_ctrl_ins.int_cnt_tx[8]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.int_cnt_tx[9]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.int_cnt_tx[10]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.int_cnt_tx[11]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.int_cnt_tx[12]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_data_out[3]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_data_out[4]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_data_out[5]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_data_out[6]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_data_out[7]
|
|
1 1
|
|
.names smi_ctrl_ins.r_dir smi_ctrl_ins.o_dir
|
|
1 1
|
|
.names r_counter smi_ctrl_ins.o_tx_fifo_clock
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[0]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[1]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[2]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[3]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[4]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[5]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[6]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[7]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[8]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[9]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[10]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[11]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[12]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[13]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[14]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[15]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[16]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[17]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[18]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[19]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[20]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[21]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[22]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[23]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[24]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[25]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[26]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[27]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[28]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[29]
|
|
1 1
|
|
.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[30]
|
|
1 1
|
|
.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[31]
|
|
1 1
|
|
.names r_tx_data[0] spi_if_ins.i_data_out[0]
|
|
1 1
|
|
.names r_tx_data[1] spi_if_ins.i_data_out[1]
|
|
1 1
|
|
.names r_tx_data[2] spi_if_ins.i_data_out[2]
|
|
1 1
|
|
.names r_tx_data[3] spi_if_ins.i_data_out[3]
|
|
1 1
|
|
.names r_tx_data[4] spi_if_ins.i_data_out[4]
|
|
1 1
|
|
.names r_tx_data[5] spi_if_ins.i_data_out[5]
|
|
1 1
|
|
.names r_tx_data[6] spi_if_ins.i_data_out[6]
|
|
1 1
|
|
.names r_tx_data[7] spi_if_ins.i_data_out[7]
|
|
1 1
|
|
.names i_rst_b spi_if_ins.i_rst_b
|
|
1 1
|
|
.names i_ss spi_if_ins.i_spi_cs_b
|
|
1 1
|
|
.names i_mosi spi_if_ins.i_spi_mosi
|
|
1 1
|
|
.names i_sck spi_if_ins.i_spi_sck
|
|
1 1
|
|
.names r_counter spi_if_ins.i_sys_clk
|
|
1 1
|
|
.names sys_ctrl_ins.i_cs spi_if_ins.o_cs[0]
|
|
1 1
|
|
.names io_ctrl_ins.i_cs spi_if_ins.o_cs[1]
|
|
1 1
|
|
.names smi_ctrl_ins.i_cs spi_if_ins.o_cs[2]
|
|
1 1
|
|
.names spi_if_ins.spi.o_spi_miso spi_if_ins.o_spi_miso
|
|
1 1
|
|
.names i_ss spi_if_ins.spi.i_spi_cs_b
|
|
1 1
|
|
.names i_mosi spi_if_ins.spi.i_spi_mosi
|
|
1 1
|
|
.names i_sck spi_if_ins.spi.i_spi_sck
|
|
1 1
|
|
.names r_counter spi_if_ins.spi.i_sys_clk
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[0] spi_if_ins.spi.i_tx_byte[0]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[1] spi_if_ins.spi.i_tx_byte[1]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[2] spi_if_ins.spi.i_tx_byte[2]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[3] spi_if_ins.spi.i_tx_byte[3]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[4] spi_if_ins.spi.i_tx_byte[4]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[5] spi_if_ins.spi.i_tx_byte[5]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[6] spi_if_ins.spi.i_tx_byte[6]
|
|
1 1
|
|
.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.i_tx_byte[7]
|
|
1 1
|
|
.names spi_if_ins.r_tx_data_valid spi_if_ins.spi.i_tx_data_valid
|
|
1 1
|
|
.names $undef spi_if_ins.spi.r_temp_rx_byte[7]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[0] spi_if_ins.w_rx_data[0]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[1] spi_if_ins.w_rx_data[1]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[2] spi_if_ins.w_rx_data[2]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[3] spi_if_ins.w_rx_data[3]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[4] spi_if_ins.w_rx_data[4]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[5] spi_if_ins.w_rx_data[5]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[6] spi_if_ins.w_rx_data[6]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.w_rx_data[7]
|
|
1 1
|
|
.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.w_rx_data_valid
|
|
1 1
|
|
.names spi_if_ins.o_data_in[0] sys_ctrl_ins.i_data_in[0]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[1] sys_ctrl_ins.i_data_in[1]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[2] sys_ctrl_ins.i_data_in[2]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[3] sys_ctrl_ins.i_data_in[3]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[4] sys_ctrl_ins.i_data_in[4]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[5] sys_ctrl_ins.i_data_in[5]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[6] sys_ctrl_ins.i_data_in[6]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[7] sys_ctrl_ins.i_data_in[7]
|
|
1 1
|
|
.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_fetch_cmd
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] sys_ctrl_ins.i_ioc[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] sys_ctrl_ins.i_ioc[1]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[2] sys_ctrl_ins.i_ioc[2]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[3] sys_ctrl_ins.i_ioc[3]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[4] sys_ctrl_ins.i_ioc[4]
|
|
1 1
|
|
.names spi_if_ins.o_load_cmd sys_ctrl_ins.i_load_cmd
|
|
1 1
|
|
.names i_rst_b sys_ctrl_ins.i_rst_b
|
|
1 1
|
|
.names r_counter sys_ctrl_ins.i_sys_clk
|
|
1 1
|
|
.names $undef sys_ctrl_ins.o_debug_loopback_tx
|
|
1 1
|
|
.names $undef sys_ctrl_ins.o_tx_sample_gap[0]
|
|
1 1
|
|
.names $undef sys_ctrl_ins.o_tx_sample_gap[1]
|
|
1 1
|
|
.names $undef sys_ctrl_ins.o_tx_sample_gap[2]
|
|
1 1
|
|
.names $undef sys_ctrl_ins.o_tx_sample_gap[3]
|
|
1 1
|
|
.names $false tx_fifo.debug_pull
|
|
1 1
|
|
.names $false tx_fifo.debug_push
|
|
1 1
|
|
.names tx_fifo.rd_addr_gray[9] tx_fifo.rd_addr[9]
|
|
1 1
|
|
.names lvds_tx_inst.r_pulled tx_fifo.rd_en_i
|
|
1 1
|
|
.names i_rst_b tx_fifo.rd_rst_b_i
|
|
1 1
|
|
.names tx_fifo.wr_addr_gray[9] tx_fifo.wr_addr[9]
|
|
1 1
|
|
.names r_counter tx_fifo.wr_clk_i
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[0]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[1]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[2]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[3]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[4]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[5]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[6]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[7]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[8]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[9]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[10]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[11]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[12]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[13]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[14]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[15]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[16]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[17]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[18]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[19]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[20]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[21]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[22]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[23]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[24]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[25]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[26]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[27]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[28]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[29]
|
|
1 1
|
|
.names $false tx_fifo.wr_data_i[30]
|
|
1 1
|
|
.names $undef tx_fifo.wr_data_i[31]
|
|
1 1
|
|
.names i_rst_b tx_fifo.wr_rst_b_i
|
|
1 1
|
|
.names $undef tx_sample_gap[0]
|
|
1 1
|
|
.names $undef tx_sample_gap[1]
|
|
1 1
|
|
.names $undef tx_sample_gap[2]
|
|
1 1
|
|
.names $undef tx_sample_gap[3]
|
|
1 1
|
|
.names r_counter w_clock_sys
|
|
1 1
|
|
.names sys_ctrl_ins.i_cs w_cs[0]
|
|
1 1
|
|
.names io_ctrl_ins.i_cs w_cs[1]
|
|
1 1
|
|
.names smi_ctrl_ins.i_cs w_cs[2]
|
|
1 1
|
|
.names spi_if_ins.o_cs[3] w_cs[3]
|
|
1 1
|
|
.names $undef w_debug_lb_tx
|
|
1 1
|
|
.names spi_if_ins.o_fetch_cmd w_fetch
|
|
1 1
|
|
.names spi_if_ins.o_ioc[0] w_ioc[0]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[1] w_ioc[1]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[2] w_ioc[2]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[3] w_ioc[3]
|
|
1 1
|
|
.names spi_if_ins.o_ioc[4] w_ioc[4]
|
|
1 1
|
|
.names spi_if_ins.o_load_cmd w_load
|
|
1 1
|
|
.names $false w_lvds_tx_d0
|
|
1 1
|
|
.names $false w_lvds_tx_d1
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[0] w_rx_09_fifo_data[0]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[1] w_rx_09_fifo_data[1]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[2] w_rx_09_fifo_data[2]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[3] w_rx_09_fifo_data[3]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[4] w_rx_09_fifo_data[4]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[5] w_rx_09_fifo_data[5]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[6] w_rx_09_fifo_data[6]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[7] w_rx_09_fifo_data[7]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[8] w_rx_09_fifo_data[8]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[9] w_rx_09_fifo_data[9]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[10] w_rx_09_fifo_data[10]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[11] w_rx_09_fifo_data[11]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[12] w_rx_09_fifo_data[12]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[13] w_rx_09_fifo_data[13]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[14] w_rx_09_fifo_data[14]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[15] w_rx_09_fifo_data[15]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[16] w_rx_09_fifo_data[16]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[17] w_rx_09_fifo_data[17]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[18] w_rx_09_fifo_data[18]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[19] w_rx_09_fifo_data[19]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[20] w_rx_09_fifo_data[20]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[21] w_rx_09_fifo_data[21]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[22] w_rx_09_fifo_data[22]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[23] w_rx_09_fifo_data[23]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[24] w_rx_09_fifo_data[24]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[25] w_rx_09_fifo_data[25]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[26] w_rx_09_fifo_data[26]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[27] w_rx_09_fifo_data[27]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[28] w_rx_09_fifo_data[28]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[29] w_rx_09_fifo_data[29]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[30] w_rx_09_fifo_data[30]
|
|
1 1
|
|
.names lvds_rx_09_inst.o_fifo_data[31] w_rx_09_fifo_data[31]
|
|
1 1
|
|
.names lvds_clock w_rx_09_fifo_write_clk
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[0] w_rx_24_fifo_data[0]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[1] w_rx_24_fifo_data[1]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[2] w_rx_24_fifo_data[2]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[3] w_rx_24_fifo_data[3]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[4] w_rx_24_fifo_data[4]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[5] w_rx_24_fifo_data[5]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[6] w_rx_24_fifo_data[6]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[7] w_rx_24_fifo_data[7]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[8] w_rx_24_fifo_data[8]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[9] w_rx_24_fifo_data[9]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[10] w_rx_24_fifo_data[10]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[11] w_rx_24_fifo_data[11]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[12] w_rx_24_fifo_data[12]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[13] w_rx_24_fifo_data[13]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[14] w_rx_24_fifo_data[14]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[15] w_rx_24_fifo_data[15]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[16] w_rx_24_fifo_data[16]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[17] w_rx_24_fifo_data[17]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[18] w_rx_24_fifo_data[18]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[19] w_rx_24_fifo_data[19]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[20] w_rx_24_fifo_data[20]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[21] w_rx_24_fifo_data[21]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[22] w_rx_24_fifo_data[22]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[23] w_rx_24_fifo_data[23]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[24] w_rx_24_fifo_data[24]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[25] w_rx_24_fifo_data[25]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[26] w_rx_24_fifo_data[26]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[27] w_rx_24_fifo_data[27]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[28] w_rx_24_fifo_data[28]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[29] w_rx_24_fifo_data[29]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[30] w_rx_24_fifo_data[30]
|
|
1 1
|
|
.names lvds_rx_24_inst.o_fifo_data[31] w_rx_24_fifo_data[31]
|
|
1 1
|
|
.names lvds_clock w_rx_24_fifo_write_clk
|
|
1 1
|
|
.names spi_if_ins.o_data_in[0] w_rx_data[0]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[1] w_rx_data[1]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[2] w_rx_data[2]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[3] w_rx_data[3]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[4] w_rx_data[4]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[5] w_rx_data[5]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[6] w_rx_data[6]
|
|
1 1
|
|
.names spi_if_ins.o_data_in[7] w_rx_data[7]
|
|
1 1
|
|
.names rx_fifo.empty_o w_rx_fifo_empty
|
|
1 1
|
|
.names rx_fifo.full_o w_rx_fifo_full
|
|
1 1
|
|
.names rx_fifo.rd_data_o[0] w_rx_fifo_pulled_data[0]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[1] w_rx_fifo_pulled_data[1]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[2] w_rx_fifo_pulled_data[2]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[3] w_rx_fifo_pulled_data[3]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[4] w_rx_fifo_pulled_data[4]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[5] w_rx_fifo_pulled_data[5]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[6] w_rx_fifo_pulled_data[6]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[7] w_rx_fifo_pulled_data[7]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[8] w_rx_fifo_pulled_data[8]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[9] w_rx_fifo_pulled_data[9]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[10] w_rx_fifo_pulled_data[10]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[11] w_rx_fifo_pulled_data[11]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[12] w_rx_fifo_pulled_data[12]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[13] w_rx_fifo_pulled_data[13]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[14] w_rx_fifo_pulled_data[14]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[15] w_rx_fifo_pulled_data[15]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[16] w_rx_fifo_pulled_data[16]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[17] w_rx_fifo_pulled_data[17]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[18] w_rx_fifo_pulled_data[18]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[19] w_rx_fifo_pulled_data[19]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[20] w_rx_fifo_pulled_data[20]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[21] w_rx_fifo_pulled_data[21]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[22] w_rx_fifo_pulled_data[22]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[23] w_rx_fifo_pulled_data[23]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[24] w_rx_fifo_pulled_data[24]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[25] w_rx_fifo_pulled_data[25]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[26] w_rx_fifo_pulled_data[26]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[27] w_rx_fifo_pulled_data[27]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[28] w_rx_fifo_pulled_data[28]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[29] w_rx_fifo_pulled_data[29]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[30] w_rx_fifo_pulled_data[30]
|
|
1 1
|
|
.names rx_fifo.rd_data_o[31] w_rx_fifo_pulled_data[31]
|
|
1 1
|
|
.names lvds_clock w_rx_fifo_write_clk
|
|
1 1
|
|
.names lvds_rx_09_inst.i_sync_input w_rx_sync_input_09
|
|
1 1
|
|
.names lvds_rx_24_inst.i_sync_input w_rx_sync_input_24
|
|
1 1
|
|
.names smi_ctrl_ins.r_dir w_smi_data_direction
|
|
1 1
|
|
.names smi_ctrl_ins.i_smi_data_in[7] w_smi_data_input[7]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[0] w_smi_data_output[0]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[1] w_smi_data_output[1]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[2] w_smi_data_output[2]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[3] w_smi_data_output[3]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[4] w_smi_data_output[4]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[5] w_smi_data_output[5]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[6] w_smi_data_output[6]
|
|
1 1
|
|
.names smi_ctrl_ins.o_smi_data_out[7] w_smi_data_output[7]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[0] w_tx_data_io[0]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[1] w_tx_data_io[1]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[2] w_tx_data_io[2]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[3] w_tx_data_io[3]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[4] w_tx_data_io[4]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[5] w_tx_data_io[5]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[6] w_tx_data_io[6]
|
|
1 1
|
|
.names io_ctrl_ins.o_data_out[7] w_tx_data_io[7]
|
|
1 1
|
|
.names smi_ctrl_ins.o_data_out[0] w_tx_data_smi[0]
|
|
1 1
|
|
.names smi_ctrl_ins.o_data_out[1] w_tx_data_smi[1]
|
|
1 1
|
|
.names smi_ctrl_ins.o_data_out[2] w_tx_data_smi[2]
|
|
1 1
|
|
.names r_counter w_tx_fifo_clock
|
|
1 1
|
|
.names $false w_tx_fifo_data[0]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[1]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[2]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[3]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[4]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[5]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[6]
|
|
1 1
|
|
.names $false w_tx_fifo_data[7]
|
|
1 1
|
|
.names $false w_tx_fifo_data[8]
|
|
1 1
|
|
.names $false w_tx_fifo_data[9]
|
|
1 1
|
|
.names $false w_tx_fifo_data[10]
|
|
1 1
|
|
.names $false w_tx_fifo_data[11]
|
|
1 1
|
|
.names $false w_tx_fifo_data[12]
|
|
1 1
|
|
.names $false w_tx_fifo_data[13]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[14]
|
|
1 1
|
|
.names $false w_tx_fifo_data[15]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[16]
|
|
1 1
|
|
.names $false w_tx_fifo_data[17]
|
|
1 1
|
|
.names $false w_tx_fifo_data[18]
|
|
1 1
|
|
.names $false w_tx_fifo_data[19]
|
|
1 1
|
|
.names $false w_tx_fifo_data[20]
|
|
1 1
|
|
.names $false w_tx_fifo_data[21]
|
|
1 1
|
|
.names $false w_tx_fifo_data[22]
|
|
1 1
|
|
.names $false w_tx_fifo_data[23]
|
|
1 1
|
|
.names $false w_tx_fifo_data[24]
|
|
1 1
|
|
.names $false w_tx_fifo_data[25]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[26]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[27]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[28]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[29]
|
|
1 1
|
|
.names $false w_tx_fifo_data[30]
|
|
1 1
|
|
.names $undef w_tx_fifo_data[31]
|
|
1 1
|
|
.names tx_fifo.empty_o w_tx_fifo_empty
|
|
1 1
|
|
.names tx_fifo.full_o w_tx_fifo_full
|
|
1 1
|
|
.names lvds_tx_inst.r_pulled w_tx_fifo_pull
|
|
1 1
|
|
.end
|