cariboulabs-cariboulite/firmware/top.asc

12561 wiersze
579 KiB
Plaintext

.comment from next-pnr
.device 1k
.io_tile 1 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 2 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 3 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 0
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000000000001110001
000000000001110000
001100000000000000
000000000000000000
000000000000000000
000111010000000000
000010000000000100
000010110000001100
000000000000000000
000000000000010000
000001010000000000
000000001000000000
.io_tile 5 0
000000000000000010
000100000000000000
000010000000000000
000010110000000001
000000000011110001
000011010001110000
001101010000000000
000000001000000000
000000000000000000
000100000000000000
000000000010010110
000000000001111000
000000000000000000
000011010000000001
000001010000000001
000000000000000000
.io_tile 6 0
000001110000000010
000100001000000000
000000000000000000
000001010000000001
000000000001100101
000000000011010000
001100111000000000
000000000000000000
000000111000000000
100000000000000000
000000000000011110
010001010011111100
000001110000000000
000000000000000001
000000000000000001
000000000000000000
.io_tile 7 0
000000000000000010
000000000000000000
000010000000000000
000011110000000001
000000000001000101
000000000011111000
001100000000000000
000000000000011000
000010000000000000
000101110000000000
000000000000001100
000000110000001100
000001010001100000
000000001000000000
000000000000000000
000000000000000000
.io_tile 8 0
010000000000100000
000000000000010000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 9 0
000000000000000010
000100000000000000
000010000000000000
000001010000000001
000000000011000001
000000000001110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000100
000010110000001100
000000000000000000
000011010000000001
000000000000000000
000000000000000000
.io_tile 10 0
000000000000000000
000100000000000000
000000000000100000
100000000000000001
000000000000000000
000000000000000000
001100000000000000
000000000001000000
000000000000000000
000000000000000000
000011111001101110
000001110011111100
000000111000000000
000000001000000001
000000000000000001
000000000000000000
.io_tile 11 0
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000010100001
000000000011110000
001001111000000000
000000001000000000
000000000000000000
000100000000000001
010000110000000000
000000001000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 12 0
000000000000000000
001100000000000000
000000000000000000
100000000000000001
000000000000000000
000000000000000001
001000000000000000
000000000000000000
100000000000000000
000000000000000000
100000000000000000
100000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 1
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000100000010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramb_tile 3 1
000000000000000000000110101000000000000000
000000000000000000000100000111001101000000
101000000000000111100000011111000001000000
000000000000000000000011111101101000000000
010000000000000111100011101000000000000000
110010000000000000100100001001000000000000
000000000000000000000000001000000000000000
000000000000000000000011110111000000000000
000001000000000000000000000000000000000000
000000000000000000000011100101000000000000
000000000000000000000111011111000000000000
000000000000001111000111011011000000000000
000000000000000101000010101000000000000000
000000000000000000100100001011000000000000
110000000000000011100000000000000000000000
010000000000000111100000001001000000000000
.logic_tile 4 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
.logic_tile 5 1
100000000000000000000010100000001000010101010000000000
000000000000000000000110111001010000101010100000000100
101000000000000000000000000101001000010101010000000000
000000000000001101000000000000010000010101010000000100
110000000000000101000000001000000000000000000100000000
110000000000000000100011110001000000000010000000000001
000000001000000000000110000101100000111111110000000000
000000000000000000000000001101100000000000000000000000
000000000000000000000000000000001001001100110000000000
000000000000000000000000000000011000001100110000000001
000000000000000000000000000000011110000011110100000000
000000000000000000000000000000000000000011110000000000
000000000000000000000111000001000000000000000100000000
000000001000000000000000000000100000000001000000000000
010000000001010001100000000000001000000100000100000000
000000000000100000000000000000010000000000000000000000
.logic_tile 6 1
100000000000000000000000000011000000000000000110000000
000000000100000000000000000000000000000001000010000000
101010000000000000000000000000000001000000100100000000
000001000000000000000000000000001111000000000000000000
110000001100001000000000000000000000000000000000000000
110000000000000101000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000000000101000000001101101011111111000000000000
000000000100000000100000000011001110010110000000000000
000000000000001101000000001000000000000000000100000000
000000000000000101100000000011000000000010000000000001
000000000000000000000011100011111110010101010000000000
000000000000000000000100000000010000010101010000000001
010000000000000101100000000000000001000000100000000000
000000000000001001000010110000001110000000000000000000
.logic_tile 7 1
100000000000000000000110000000001100000100000100000000
000000000000000000000000000000010000000000000000000000
101000000000000000000000000111011100010101010000000000
000000000000000000000000000000100000010101010000000000
000000000000000000000000000000001110000100000000000000
000000000000000000000000000000010000000000000000000000
000000000000000000000000001000000000000000000100000000
000000000000000000000000000111000000000010000000000000
000000000000000000000010100000001000000100000100000000
000000000000000000000010100000010000000000000001000000
000000000000001000000000000000000000000000100110000000
000000000000000101000000000000001110000000000000000000
000000000000001000000110100000000000000000100100000000
000000000000000001000011000000001101000000000000000000
000000000000000000000000011000000000000000000100000000
000000000000000101000010001111000000000010000000000000
.logic_tile 8 1
000000000000000111000000000000000001000000001000000000
000000000000000000100000000000001111000000000000001000
000000000000000000000000000101111110001100111000000000
000000000000000000000000000000110000110011000010000100
000000000000000000000000000111101000001100111000000000
000000000000000000000000000000100000110011000000000001
000000000000000000000010100000001001001100111000000000
000000000000000000000100000000001110110011000000000000
000000000000000101000010100001001000001100111000000000
000000000000000000000000000000000000110011000010000000
000000000001010000000000000000001000001100111000000000
000000000000100000000000000000001100110011000000000000
000000000000000000000000000011001000001100111000000000
000000000000000000000000000000100000110011000000000000
000000001100000101000010100111101000001100111000000000
000000000000000101000010100000000000110011000000100001
.logic_tile 9 1
000000000000000000000010100011100000000000001000000000
000000000000000000000100000000100000000000000000001000
000000000000001101000000000000011111001100111000000000
000000000000000111100000000000011011110011000000000100
000000000000000101000000000101101000001100111000000000
000000000000000000100010110000000000110011000000000100
000000001110000000000000000001101000001100111000000000
000000000000001101000010110000000000110011000000000100
000000000000000000000000000000001000001100111000000101
000000000000000000000000000000001010110011000000000000
000000000000000000000010100000001000001100111000000100
000000000000000000000100000000001001110011000000000000
000000000000000000000000000001101000001100111000000101
000000000000000000000000000000000000110011000000000000
000000001100000000000010100000001000001100111000000000
000000000000000000000100000000001011110011000000000001
.ramb_tile 10 1
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010001000000000000000011100000011100000100000100000000
110000000000000000000100000000000000000000000001000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000111100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 2
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 2
000000000000000000000010100001101101110100010000000000
000000000000000000000100000000101100110100010010000000
101000000000001000000010000000011001110000000100000000
000000000000000001000100000000001110110000000000000000
010000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001100000000111101000101000000100000000
000000000000000000000000000000010000101000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
110000000000000000000000000000000001100000010100000000
100000000000000111000000000011001110010000100000000000
.logic_tile 2 2
000000000000000000000000011101000001111001110000000000
000000000000000000000010001111001000100000010000000000
101000000000001000000110000011111110101001010000000000
000000000000000101000000001111110000010101010000000000
010000000000001000000000000000011100101000000100000000
100000000000000111000000001011000000010100000000000100
000000000000000000000000000011111111110001010000000000
000000000000000000000000000000011101110001010000000000
000000000000000000000000000000011100101000000100000000
000000000000010000000010111001000000010100000000000000
000000000000001111000010011000000001100000010100000000
000000000000000001000110000011001001010000100000000000
000000000000000000000000011000011100101000000100000000
000000000000000000000011010011000000010100000000000000
110000000000000000000111001011100000101001010100000000
100000000000000000000000000011100000000000000000000000
.ramt_tile 3 2
000000010000001000000011101000000000000000
000000000000000101000010010101001111000000
001000010000001000000000001001000000000000
100000000000001111000000000101001001000000
010000000000000001000000000000000000000000
010000000000000000100000000101000000000000
000000000000000001000000001000000000000000
000000000000001001100011011111000000000000
000000000000000000000000000000000000000000
000000000000001111000000000111000000000000
000000000000000001000000001011000000000000
000000000000000000000000000011000000000000
000000000000000001000010001000000000000000
000000000000000000000000000111000000000000
010000000000000001000000001000000000000000
010000000000000000100010001101000000000000
.logic_tile 4 2
100000000000000000000110010000011100000100000100000000
000000000000000000000110010000000000000000000000000001
111000000000000000000000010000000000000000000100000000
100000000000000000000010010011000000000010000000000010
110000000000000101100000001001011110100001000000000000
000000000000000000000000001001111001110111100000000000
000000000000000101100000000101000000000000000110000000
000000000000000000000000000000000000000001000000000000
000000000000000001100111000000000000000000000100000100
000000000000000000100100001111000000000010000000000000
000100000000000001100000000111000000000000000100000001
000000000000000000100000000000000000000001000000000000
000000000000000101000111000011000000000000000100000000
000000000000000000100000000000100000000001000000000001
010000000000000000000000000000011010000100000100000000
000000000000000000000011100000000000000000000010000000
.logic_tile 5 2
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001010000000000000001000
000000000000000001100000000000011010001100111000000000
000000000000000000100000000000001010110011000000000000
000000000000001001100000000000001001001100111000000000
000000000000001001100010100000001011110011000000000000
000000000000000101000010100000001001001100111000000000
000000000000000000000010100000001011110011000000000000
000000000000000000000000000101001000001100111000000000
000000000000000000000000000000100000110011000000000000
000000000000000000000000000000001001001100111000000000
000000000000000000000010110000001000110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001010110011000000000000
000000000001010000000000000011101000001100111000000000
000000000000000000000000000000100000110011000000000000
.logic_tile 6 2
000000000000000001100000000001001111001000010000000000
000000000000000101000000000101011011100001000000000000
000000000000001101000110111001000000001111000000000000
000000000000001001000010101011001100110000110000000000
000000000000000101000000001111100000100000010000000000
000000000000000000000010110001101101001001000000100000
000000000000000001100110000000011001001100110000000000
000000000000000101100110100000011001001100110000000001
000000000001000101000000011011011010100010000000000000
000000000000000000000010011111011110000100010000000000
000000000000000000000110001001111010111111000000000000
000000000000000000000100000111001110010110000000000100
000000000000001001100110000000011001011010010000000000
000000000000001001100010000101001111100101100000000000
000000000000001000000011110101101111100000000000000000
000000100000001001000010011101111010000000100000000000
.logic_tile 7 2
100010100000000000000110010001100001110000110000000000
000000000000000001000110010001101001001111000000000000
101000000000001000000110010000000000011001100000000000
000000001110001001000110011101001001100110010000000000
110000000000000101000000011011011010110110100000000000
110000000000000111000010011011011010111000100000000000
000000000000011001100000000001111010010101010000000000
000000000000100001100011100000100000010101010000000001
000000100000000001100000000101101000100001000000000000
000001000000000000000000000000111001100001000000000000
000000000001000000000000000001111010111100000000000000
000000000000000000000010010101000000000011110000000000
000000000000001000000011001111011010000010000000000000
000000000000000001000000001011001010000010100000000000
010010100000000101000000000000011110000011110100000000
000001000000100000100000000000000000000011110000100000
.logic_tile 8 2
000000000000000101000000000000001000001100111010000000
000000000000000000000000000000001101110011000000010000
001000000000000101000010100011101000001100110010000000
100000000000000000000000000000100000110011000000000100
010001000000000101100011100001111010010101010100000000
110000000000000000000100000000110000010101010000000000
000000000000000000000000000000001010000100000100000000
000000000000000101000010100000000000000000000000000000
000000000000000001100000010000000000000000000100000000
000000000000000000000010100111000000000010000000000000
000000100000000000000000011000000001011001100100000000
000001000000000000000010000001001010100110010000000000
000000000000000001100000000011000000000000000100000000
000000000000000000100000000000000000000001000000000000
010000000000000000000000000000000000000000000100000100
000000000000000000000000000001000000000010000000000000
.logic_tile 9 2
000000000000100000000000001000001000001100110000000000
000000000000000000000011111001000000110011000000010000
001010000000000000000000011000000000000000000100000000
100001000000000000000010100011000000000010000000000000
010000000000001000000000000000001010000100000100000000
010000000000000101000000000000000000000000000000000000
000000000000000000000110000000011100000100000100000000
000000000000000000000000000000010000000000000000000000
000000000000000000000110010000001100000100000100000000
000000000000000000000110010000010000000000000000000000
000000000000000001100110010000000001000000100100000000
000000000000000000100110010000001101000000000000000000
000000000000000000000000000000000000000000100100000100
000000000000000000000000000000001101000000000000000000
010000000000000000000000000101100000010110100100000000
000000000000000000000000000000100000010110100000000000
.ramt_tile 10 2
000000100000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000010100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000100000000000000000000000000000000000
.logic_tile 11 2
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 2
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 2
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000100000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 3
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 3
000000000000000000000000000001101110110001010000000001
000000000000001101000000000000011000110001010000000000
101000000000001001100010101101000000101001010000000001
000000000000001011000000001001001111100110010000000000
010000000000000101000000000011101100101000000100000000
100000000000000000100000000000000000101000000000000000
000000000000000000000010110000000001100000010100000000
000000000000000000000110000011001000010000100000000000
000000000000000011100110000001101100101000000100000000
000000000000000000100000000000100000101000000000000001
000000000000000011100000001000000000100000010100000000
000000000000000000100000001101001100010000100000000000
000000000000000000000000000000001101110000000100000001
000000000000000000000010000000001000110000000000000000
110000000000000000000000000000011010111001000000000000
100000000000000000000000001011011111110110000000000010
.logic_tile 2 3
000000000000001101000000000000000001100000010100000000
000000000000000001100011100011001010010000100010000000
101000000001010001100010100001101001101000110000000000
000000000000101101000010110000111001101000110010000000
010001000100000000000000010101100000100000010100000000
100000000000000000000010100000101100100000010000000100
000000000000000101000000010001011000111000100000000000
000000000000000000000010000000101011111000100000000000
000000000000001000000000010000000000100000010100000000
000000000000001011000010001011001100010000100010000010
000010100000000000000000000001001100101000000100000000
000001000000000000000000000000000000101000000000000001
000000000000000000000000000000011000110000000100000001
000000000000000000000000000000001100110000000000000000
110000000000000000000000000101101000101001010000000000
100000000000000000000000000001010000010101010010000000
.ramb_tile 3 3
010000000000000111100000001000000000000000
001000000000000111100011100101001001000000
101000000000001111000111011101000001000000
000000000000000111000111101111101000000000
110000000000000000000110101000000000000000
011000000000000000000000001101000000000000
000000000001010011100011101000000000000000
001000000000000111100000000101000000000000
000000100000000000000000011000000000000000
001001000000000000000011011001000000000000
000000000000000000000000001001000000000010
001000000000000000000000001001000000000000
000000000000000011100000000000000000000000
001000000000000000000000000111000000000000
010000000000000000000000010000000000000000
011000000000000000000011000001000000000000
.logic_tile 4 3
100010000000000000000000000000000000000000000100000000
000010000000000000000010101011000000000010000000000000
101000000000000000000110010101011000111110100000000000
000000000000000000000111100000010000111110100010000110
010000000000000111100010000000000001100000010000000000
110000000100000000100000001001001101010000100000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000001110000100000100000000
000000000000000001000010000000010000000000000000000000
000000000000000000000000000011000000000000000100000000
000000000000000000000010100000000000000001000000000000
000000000001000000000000010000011000000100000100000000
000000000000100000000010100000010000000000000010000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 5 3
000000000000001000000010000000001001001100111000000000
000000000000001001000100000000001011110011000000010000
001000000000000101000011111000001000001100110000000000
100000000000000101000010011001000000110011000000000000
000000000000000000000010110001100001011001100000000000
000000000000000000000110100000001000011001100000000000
000000000000001101100010110101111001001100000000000000
000000000000000101000110101001111011110000000000000000
000001000000000101100000000111111100111100000000000000
000010000000000000000000001101110000000000000000000000
000000100000000000000010000101100000000000000100000000
000001000000000000000000000000000000000001000010000000
000000000000000000000110000101001100100000000000000000
000000000000000000000000000001101111000000000000000000
000000000000000000000000001000000000000000000100000000
000000000000000000000010010101000000000010000010000000
.logic_tile 6 3
100000000000000101100011100111001100000100000000000000
000000000100000000000110110101111110100000000000000000
101000001000001011100110011111011100000000110000000000
000000000000000101100110000001111110110000000000000000
000000000000101011100011110111101011110011000000000000
000000000000010101100110100011011101000000000000000000
000000000000000001100010110111111011001100000000000000
000000000000000101000010101001001001001000000000000000
000000000000001000000110000000001011001100110000000000
000000000000001011000000000000001111001100110000000000
000000000000000000000110011001111011101001010100000000
000000000000000000000010101101011101110110101000000000
000000000000001001100010000001011000111100000000000000
000000000000000001100010011101010000101000000000000000
010000000000001101000110001001101000101000000000000000
000000000000000001100100000101110000000000000000000000
.logic_tile 7 3
100000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000001100000000000011110000100000100000000
000000000000000000100000000000000000000000000000000000
000000000001000000000000000000011010000100000100000000
000000000000000000000000000000010000000000000000000000
000001001110000000000000010111100000000000000000000000
000000000000000000000010010000100000000001000000000000
000000000110000000000000001000000000010110100000000010
000000001110000000000000000011000000101001010000100000
000000000000001001100000000000000001000000100100000000
000000000000001101000000000000001000000000000000000000
000000000001000000000000010011100000000000000100000000
000000000000000000000010000000000000000001000000000000
000000000000000011100111100000000000000000100100000000
000000000000000000100000000000001111000000000010000010
.logic_tile 8 3
100001000000001101000011110000000000000000000000000000
000000100100001001100011110000000000000000000000000000
111000000000000000000000000011101011000000010000000000
100000000000000000000000001111111101000000000010000000
010000000000000101000110010000000000000000000000000000
010000000000000101000011010000000000000000000000000000
000000000000000111000011100101000000110000110000000000
000000000000000000000111101001001010001111000000000000
000001000010000000000000000000000000000000000000000000
000010000001010000000000000000000000000000000000000000
000000000001010000000110011001011010001100110000000000
000000000000100000000010011101001011000100100000000001
000000000000000000000000010111000001111001110110000000
000000000000001101000010010000001011111001110000000000
000000000000000001100010000111111110000011000000000000
000000000000000000100000000101101000000000110000000000
.logic_tile 9 3
000000000110000111000111101101000001001111000000000000
000000000000000000100100000001101011110000110000000000
001000000000001111100000001001101101001100000000000000
100000000000001011100000001011001011110000000000000000
000000000000000001000000010101111110011010010000000000
000000000000000101000011010000101010011010010000000000
000000000000000001000110010111111010001000010000000000
000000000000000000000011011111101100010010000000000000
000000000000001101000110000000001000000100000110000000
000000100000000001100000000000010000000000000000000000
000000000000000000000010100000001110101000000000000100
000000000000000000000100001011000000010100000000000000
000000000000000001100000011001101011100001110000000000
000000000000000000000010001111001110001011010000000000
000000000000001001000010000000000000000000000110000000
000000000000000001000000000001000000000010000000000000
.ramb_tile 10 3
010001000000000000000000000000000000000000
001000000000000000000010011111001010000000
101000001110001000000000000101100000000000
000000000000001011000011101101001110000000
010000000000000111000111101000000000000000
011000000001001111000111101001000000000000
000000000000000111000000001000000000000000
001000000000000000100000000011000000000000
000000000000000000000000001000000000000000
001000000100000000000000000001000000000000
000000000000000001000000001101000000000100
001000000000000111000000001111100000000000
000000000000011000000010001000000000000000
001000001110000011000000000111000000000000
110000000000000001000000010000000000000000
011000000000000000000011010101000000000000
.logic_tile 11 3
100000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
111000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110000000000000101100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000000000101000000000000000100000000
000000000000000000000000000000000000000001000000000100
000000000000000000000000000011000000000000000100000100
000000000000000000000000000000000000000001000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 3
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 3
000000000000000000
000100000000000000
000001011000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000010
000000000000110000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 4
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 4
010000000000000000000000000001100000101001010100000000
001000000100010000000011110011100000000000000000000000
101000000000000000000010100011001100101000000100000000
000000000000000101000100000000100000101000000000000000
010000000000000001100000000000000001100000010100100000
011000000000000000000000000011001010010000100000000000
000000000000000001100010000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000100000010100000000
001000000000000011000010000101001100010000100000000000
000000000000000000000110001000001100101000000100000001
001000000000000000000000001011000000010100000000000000
000000000000001000000000001000011111111001000001000000
001000000000000001000000000001001011110110000000000000
110000000000001000000000000011000000100000010100000000
001000000000000001000000000000001110100000010000000000
.logic_tile 2 4
010001000000100000000111100000000000000000000000000000
001010100001000000000000000000000000000000000000000000
101000000000001001100000001000011100101000000100000000
000000000000001011000000000011010000010100000000000000
010001001100000000000111001001001100101000000000000000
111000000000000000000110110001110000111110100000000010
000000000000000000000110001000000001100000010100000000
001000000000000000000000000011001110010000100000000000
000000000010000000000110000011101010101000000100000000
001000000110000000000000000000010000101000000000000000
000000000000000111000000011000011010101000000100000000
001000000000000000000010000011010000010100000000100000
000000000011100000000000000011111000101000000100000000
001000000000100000000000000000000000101000000000000000
110000000000001000000000001000000000100000010100000000
001000000000000001000000000011001101010000100000000010
.ramt_tile 3 4
000000110000011000000000010000000000000000
000001000000001111000011110001001111000000
001000010000000001000000001101000000000000
100000000000000000100000000101001110000001
110010000000000111100000000000000000000000
010000000000000000100000001001000000000000
000000000000001000000111101000000000000000
000000000000000111000000000001000000000000
000000000000010000000000000000000000000000
000010000110010000000010010111000000000000
000000000000000001000010001101100000000000
000000000000000001100100000011100000000001
000011100000001001000010001000000000000000
000000000100000111100100000111000000000000
110000000000000001000000001000000000000000
010000000000000000000000001011000000000000
.logic_tile 4 4
010000000000000000000000000000000001000000100100000000
001000000100000101000000000000001000000000000011000000
001000000000001000000000000111000000000000000100000000
100000000000000001000000000000100000000001000010000000
000001000001010000000000000000000001000000100100000000
001000000100000000000000000000001110000000000000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000000000011000000000010000000000000
000000000000000101100000010111000000000000000100000000
001001000000000000000010000000000000000001000000000000
000000000000000000000000010000001100000100000100000100
001000000000000000000010000000010000000000000010000100
000000100000001000000110000000000000000000100100000000
001000000000000101000000000000001000000000000000000000
000000000000000101100000000000011100000100000100000000
001000000000000000000000000000010000000000000000000010
.logic_tile 5 4
110000000010000011100110000000001000000100000100000000
001000000000011101100011110000010000000000000000000000
101000000000000000000000001000000000010110100100000000
000000000000000000000000001101000000101001010000000000
110000000000000101000111010111011110000001110000000000
111010000000000101000011111101101001000000100000000000
000000000000000001100000000101000000011001100000000000
001000000000000000000011100000001010011001100000000000
000000000010000000000010110001011110000001010000000000
001000000000000000000011010001001101000010010000000000
000000000000100000000000000000001010000100000100000000
001000000001010000000000000000000000000000000000100000
000000000000000000000011111101001101001011010000000000
001010000000000000000011011111111010101101000000000000
010000000000001000000110000000000000000000100100000000
001000000000000011000000000000001010000000000000000000
.logic_tile 6 4
110000000110000000000000000111011101100000000000000000
001000100000000000000010001101101011111000000000000000
111000001110000000000110000011001110111101010100000000
100000000000000000000100000000010000111101010000100000
010001001100001101000011111001111110000101010000000000
011000000000000001100110100101111110101010000000000000
000000000000101011100111000111100000101001010100000000
001000000001000101100100001011100000111111110000000010
000000000100001000000010101000000001111001110100000000
001000000001001011000100001011001100110110110000000010
000000000000000011100010001000000001111001110100000001
001000000000001101000110001011001010110110110000000000
000000000000000001100110100101001010111101010100000000
001000000001010001100010000000010000111101010000100000
000000000000000000000010100101000000101001010110000000
001000000000000000000111100111000000111111110000000000
.logic_tile 7 4
110001000000001000000000001101101100000000010000000000
001010000000001011000010010001101111000010110000000000
101000000000000000000111000000000000000000000000000000
000000000000000111000100000000000000000000000000000000
010000000000000111100010100000000000000000000100000000
111000000000000000100000000101000000000010000000000000
000000000000000000000000011011001001000001010000000000
001000000000000000000011100111011011000010010000000000
000000000000001001000000000000011000000100000100000000
001000100001001011100010000000010000000000000000000000
000000000000001000000111100001000000000000000100000000
001000000000001001000100000000000000000001000000000000
000000000000000000000111000000000001000000100100000000
001000000000000000000100000000001100000000000000000000
010000000000000000000111101111101101001001100000000000
001000000000000001000010001011111111010001100000000000
.logic_tile 8 4
010000000000000000000000001000000000000000000100100000
001000000000000000000000001011000000000010000000000000
001000000000000101100000001000000000000000000100000000
100000000000000000000000000111000000000010000000000000
000000000000000000000000011000001010010101010000000000
001000000000000001000010100101000000101010100000000000
000000001110001111000000011000000000000000000100000000
001000000000000101000010100001000000000010000000000000
000010100001010000000000000101100000000000000100000000
001011100000100000000000000000100000000001000000000000
000000000010000000000000010000000000000000100100000000
001000000000000000000010000000001011000000000000000000
000000000101000000000000000101100000000000000100000000
001000000001010000000000000000000000000001000000000000
000000000000001001100000000111100000000000000100000000
001000000000000001000000000000000000000001000000100000
.logic_tile 9 4
010000001000001000000000000000000001000000001000000000
001000000000001111000000000000001101000000000000001000
001010000000001011100111000111011100001100111100000000
001001000000001111000010100000010000110011000000000000
000000000000001011100000000111001000001100110100000000
001000100001010101100000000000100000110011000000000000
000000000000000000000000001000000001011001100000000000
001000000000000000000000000001001100100110010000000000
000000001000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000101000000011111001010000100100000000000
001000000000000000100010001001101010101101110000000000
000000000000000001100110010000000001001111000100000000
001000000000000000000010000000001101001111000000000000
010000000000000000000000001001101010010110100000000000
011000000000000000000000001001101010000100100000000000
.ramt_tile 10 4
000000010000000000000000000000000001000000
000000001100000111000011101001001001000000
001000010000001000000011111101000000000000
100000000000000111000111101001101011000000
110001000000001000000011110000000000000000
010010001010001111000111110001000000000000
000000000000010000000011001000000000000000
000000000000000000000100000011000000000000
000001001000010000000111111000000000000000
000010101010100000000011100001000000000000
000000000000000111000000000101100000001000
000000000000000111000000000101100000000000
000000000000010001000000000000000000000000
000000000000100000000000000111000000000000
110000000000000000000000000000000000000000
010000000000000000000000001011000000000000
.logic_tile 11 4
110010100000000000000111101000011011010111100000000000
001001000000000000000100000101001101101011010000000100
101000000000000111000110001101011101001001000000000000
101000000000000000000000000001111010000010000000000000
000000000000000001100111100000011000001000000100000000
001000000000000000000100001111001011000100000000000000
000000000000001111000000000011111010101000000100000000
001000000000000001000000001001100000000000000000000000
000010100000010001000000000000001111010000000100000000
001001000000100000010000001101011010100000000000000000
000010100000000000000000010000000000010110100000000000
001000000000000000000010000011000000101001010000100000
000000000000000011100110010001100000111111110100000000
001000000000000000000010000101100000101001010000000000
000000000000000000000000000101001110101001010000000000
001000000000000000000000001111110000101000000000000000
.logic_tile 12 4
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000001110000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 4
000000000100000000
000000000100000000
000000000100000000
000000000100000001
000000000100000000
000000000100000000
001100000100000000
000000000100100000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 5
000010000100000010
000100110100000000
000000000100000000
000000000100000001
000000000100000010
000000000100010000
001100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000111110
000000000000011100
000011111000000000
000001011000000001
000000000000000010
000000000000000000
.logic_tile 1 5
010000000000000111000110001011100000101001010100000000
001000000000000000000000001111000000000000000000000000
101000000000000000000000000000011101101100010000000001
000000000000000011000000001001001111011100100000000000
010000000000000000000010001111100001100000010000000001
111000000000000000000000000101101011110110110000000000
000000000000000001000110001111100000101001010100000000
001000000000000101000000000111100000000000000000000000
000000000000000000000000001111000000101001010100000000
001000000000000000000000001111000000000000000000000000
000000000000101001100000000000011111110000000100000000
001000000000011011000000000000011010110000000000000000
000010000000001000000000000001000001010000100000000100
001000000000000001000000000000001000010000100011100001
110000000000000000000110100000011110101000000100000000
001000000000000101000110011001010000010100000000000000
.logic_tile 2 5
010000000010000101000000001011011110101001010000000000
001000000000000000000000001001110000010101010010000000
101000000000001000000111011000011001101100010000000000
000000000000001011000110001001001111011100100000000000
010010100100000000000111000111000001100000010100000000
111001000000000000000000000000001001100000010000000000
000000000000001000000000001111000001100000010000000000
001000000000000101000010111111001010111001110000000000
000011000001010000000111010111100000100000010000000000
001000001010001101000110000011101101110110110010000000
000000000000000000000000001000000000100000010100000000
001000000000000000000000000101001110010000100000000000
000000000001001101000000000111011010101000000100000000
001000000000101011100000000000010000101000000000000000
110000000000000000000000000000000000100000010100000000
001000000000000000000011100001001110010000100000000000
.ramb_tile 3 5
010000000000000111100000011000000001000000
001000000100000000100011100011001101000000
101000000000001000000000001111000000000000
000000000000000111000011111101101000000000
010000000000000101100111100000000000000000
011000000000000000000100001101000000000000
000000000000000000000000011000000000000000
001000000000000000000011000111000000000000
000010000000000111000000001000000000000000
001010000000000000000000000001000000000000
000000000000000000000111001101000000000000
001000000000000111000111101011000000000000
000000000100100000000110101000000000000000
001000000101010000000000001001000000000000
110000000000001111000000000000000000000000
111000000000001011100000000011000000000000
.logic_tile 4 5
110000000000000101000000001011101110001101000010000000
001000001000000000100000000101001101000100000000000000
111000000000001101100000010111100000000000000100000000
100000100000000001000011110000000000000001000000000000
110000000000000101100111000000001100000100000100000000
001000000000000000000000000000000000000000000010000000
000000000000000011100000000111111000111101010000000000
001000000000000000000000000001110000010100000000000000
000000000001010101000000000000000000000000000100000000
001000000000000000100010101101000000000010000000000000
000000100000000101000011100000001010000100000110000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000011000000100000100000000
001000000000001001000000000000000000000000000000000000
010000000000000101000111001001101101000001010000000000
001000000000000000100100001011011100000010010010000000
.logic_tile 5 5
110000000000000101100000000000011000000100000100000000
001000000000000000100010110000010000000000000000000000
111000000000000101000111101001011001010000100000000001
100000000000000000100011100001111111010100000000000000
110000000000001101100000010000001110000100000100000000
001000000000001011000010000000010000000000000000000000
000000000000100101000000010001001011101001000000000000
001000000000010000100010101101101000100000000000000000
000000000000100000000000001101111000100000010000000000
001000000001010000000000000111101001100000100000000000
000000000000000001000000000000000001000000100100000000
001000000000000000000000000000001100000000000000000000
000000000000000000000000000001000000000000000100000000
001000000000000000000010000000000000000001000000000000
010000000000001001100000010001011011000000100000000000
001000000000001011000010000101101110010100100000000000
.logic_tile 6 5
110000000010011000000000000000011110000100000100000000
001010100000100001000000000000010000000000000000000000
101000000000000000000110001011011101101001000000000000
000000000000000000000000000111101100100000000000000000
000001001010000000000000000000000000000000000100000000
001010000000010000000000000011000000000010000000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000000001111000000000010000000100000
000000000000001000000000000000000000000000000100000000
001000100000000101000010110001000000000010000000100000
000000000000000101000000001000000000000000000100000000
001000000000001111100000001001000000000010000000100000
000000000000000101100110110000000000000000000100000000
001010100000000000000010001111000000000010000000000010
000000000000000000000000010000001110000100000100000000
001000000000000001000010100000000000000000000000000000
.logic_tile 7 5
010100000100000000000000010101011010010101010100000000
001000000000000000000010010000000000010101010000000000
001100000000000000000010100000000000000000000100000000
100000000000000000000000001101000000000010000000000000
010110000000010000000011100101001111100010000000000000
111001000000100111000110001001101110000100010000000000
000000000000001000000000000000001000000100000100000000
001000000000001011000000000000010000000000000000000000
000000000000100000000010000101111100101001010000000000
001010101000000000000010101011010000000010100000000000
000000000000001000000010001011100000100000010000000000
001000000000000001000000001001001111000000000000000000
000001100010001000000010010000001010010101010100000000
001010000000000111000010001111000000101010100000000000
010000000000000101100000000000000000010110100100000000
001000000000000000000000001011000000101001010000000000
.logic_tile 8 5
010000000000000000000010101011000000000000000000000000
001000000000000000000010110111001011110000110000000000
001000001110001111100110000000000000000000000000000000
100010100001000111100100000000000000000000000000000000
000000000000000000000010100000000000000000000000000000
001000000000000000000100000000000000000000000000000000
000000000000000001100000000001101001010011100000000000
001000000000000000100000000000011111010011100001000000
000000000000000001000000000001101111001000000000000000
001000000000000000000000001111101010000000000000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000000001001000000000010000000000000
000000000000001000000010000000000000000000000000000000
001001001010000001000000000000000000000000000000000000
000000000000000111100000010000001011111111000000000000
001000000000000000100011000000011000111111000010100010
.logic_tile 9 5
110000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
111000000000100000000000000000000000000000000000000000
100000000001000000000000000000000000000000000000000000
110000000000000101000000001000000000000000000110000000
001000000000000000000010100111000000000010000000000000
000000000000000011100000001101000000100000010000000001
001000000000000000100010101101001011000000000000000000
000001000000000000000000000000000000000000000000000000
001010000000000000000000000000000000000000000000000000
000000000000000000000000001101011010111100010010000000
001000000000000000000000001101001011111101000000000000
000000000000000101000000000000000000000000000110000000
001000000110000000000000000111000000000010000000000000
010000000000000101000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.ramb_tile 10 5
010010000000000000000011101000000000000000
001001000001010000000111110111001101000000
101000000000000000000000000001100000010000
000000001000000111000011110011101001000000
110001000000010111100000000000000000000000
111010000000100000000000001001000000000000
000000000000000000000011111000000000000000
001000000000000000000111010011000000000000
000001000110000111000000000000000000000000
001010001110000000000011100101000000000000
000000000000001011100000001101100000000000
001000000000001111100000001101100000010000
000000001110001000000111101000000000000000
001000100000000011000100000011000000000000
010000000000000111000000000000000000000000
011000000000000000000000000111000000000000
.logic_tile 11 5
110000000000000000000000000000000000000000000000000000
001000000000000011000000000000000000000000000000000000
101000000000000000000000000000011010000011110100000000
101000000000000000000000000000010000000011110000100000
000010000000000000000000000000000000000000000000000000
001001001110000000000000000000000000000000000000000000
000000000000000111000111100000000000000000000000000000
001000000000000000000100000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
001000000000100101000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
001000000010000000000000000000000000000000000000000000
000000000000000101000000000000000000100000010000000000
001000000000000000000000000001001100010000100000100000
010000000000000000000000000000000000000000000000000000
111000000000000000000000000000000000000000000000000000
.logic_tile 12 5
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 5
000000000100001000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000010000
000000000000000000
000000000000000000
.io_tile 0 6
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 6
000000000000000000000000000111111110101000000100100000
000000000000000101000000000000100000101000000000000000
101000000000000001100000001000000000100000010100000000
000000000000000000100000000111001111010000100000000000
010000000000000000000000000111111010101000000100000000
100000001010000000000000000000010000101000000000000000
000000000000000101000110010001000000101001010000000000
000000000000000001000010001111001101100110010000000000
000000001110000000000010000101101101110001010000000000
000000000000000000000100000000111010110001010000000100
000000000000000000000000000000011011110100010000000000
000000000000000000000000001011011000111000100010000000
000000000000000001100000010111111010101000000100000000
000000000000000000000010000000000000101000000000000000
110000000000000000000000000111000001100000010100000000
100000000000000111000010000000001110100000010000000000
.logic_tile 2 6
000001000000000000000011111000011000101000000100000000
000010100000100000000011110101000000010100000000000000
101000000000000111000010111000001110110001010000000000
000000000000000000000011111101011011110010100000000000
010001000000000000000000010001111000101000000100000000
010000000000000000000010000000010000101000000010000000
000000000000001101000010001111000000111001110000000000
000000000000001111000110001001101001010000100000000000
000000000000101000000000000000011001110000000100000000
000000000001000001000000000000001001110000000000000000
000000000000000000000000000000001101110000000100000000
000000000000000000000000000000001000110000000000000000
000000000000000000000111001001100000101001010100000000
000000000000000000000100001101000000000000000000000000
110000000000000000000000001000000001100000010100000000
000000000000000000000000000101001000010000100000000000
.ramt_tile 3 6
000000010000000000000010000000000000000000
000000000000001001000010011001001000000000
001000010000000000000000011111000001000000
100000000000000000000011111111101101000000
010000000000000000000111101000000000000000
110000000000000000000100001001000000000000
000000000000000000000000001000000000000000
000000000000000000000000000111000000000000
000000000000000000000000010000000000000000
000000000000000000000011100111000000000000
000000000000000000000010100011000000000000
000000000000001111000000000111100000000000
000000000000000001000110001000000000000000
000000000000000101000100000011000000000000
110000000000000001000000000000000000000000
110000000000000101100010101001000000000000
.logic_tile 4 6
000000000000100000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
101000000000000000000000001011100000101001010100000000
000000000000000000000000000111100000000000000000000000
110000000000010000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000011100000101001010110000000
000000000000000000000010000011100000000000000000000000
000000000000000000000011101000000001100000010100000000
000000001000000000000000000101001101010000100001000000
110000000000000000000000000000000000000000000000000000
000000001100001111000000000000000000000000000000000000
.logic_tile 5 6
100000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
111000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
000000000000100000000000001000000000011001100110100000
000000000000000000000000000111001101100110010010000010
000000001100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000011110000011110100000001
000000000000000000000000000000000000000011110010100000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
010000000000100001100000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
.logic_tile 6 6
100000100000000000000000010000000000000000000000000000
000000000000000000000010100000000000000000000000000000
101000000000000101000110001000000000000000000100000000
000000000000000000100100001001000000000010000000000000
000000000000100000000000010000000000000000000000000000
000000100000000000000010100000000000000000000000000000
000100000000000101100000000000000000000000000100000000
000100001110000000000010110011000000000010000000100010
000001000000000001100000001101011010100000010000000000
000000100011010000000000000101111110101000000000100000
000000000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
000000000000100101000000001101000001110110110000000000
000000000000010101000000001111101010101001010000100000
000000000000100000000010000001011011101000010000000000
000000000001010000000000000111101000000000010000000010
.logic_tile 7 6
100000000001000000000111100111100000010000100100000000
000000000000100000000100000000001101010000100000000000
111000000000000001100000000000000000000000000000000000
100000000000001101000000000000000000000000000000000000
110000000100000000000010100001011000111101010100100000
110000000000000000000100000000100000111101010000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000100000000000000000000010000000000000000000000000000
000000000000000000000011100000000000000000000000000000
000000000000000111010000000101001101100000010000000000
000000000000000000100000001111111110100000100000000000
000000000000000000000011110000000000000000000000000000
000000000000000000000010110000000000000000000000000000
000010000000000000000000001011011001101000000000000000
000001000000001111000000000111101100010000100000000010
.logic_tile 8 6
000000000000010111100000010000000001000000100100000000
000000000000100000100011110000001100000000000000000000
001000000000000111000110010000011100000100000000000000
100000000000000000000010000001001110001000000011000100
000000000000001000000000011001111011101000010110000000
000000000000000101000010001101001110110100010000000000
000000000000000000000010000001100001010000100000000000
000000000000000101000000001101101001000000000000000000
000000000000000000000000000000001010000100000100000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000010000000001000000000000001100000000000000100000000
000001000000000001000000000000100000000001000000000000
010000001010000001100000000000001000000100000100000000
000000000000000000100000000000010000000000000000000000
.logic_tile 9 6
000000000000000111100000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
001000000000000000000000000000001010010100000000000001
100000000000000000000000000101010000101000000000000000
000000000000001000000010100000000000000000000000000000
000000000001011111000000000000000000000000000000000000
000010100000000000000000000000000000000000100110000000
000001000000000000000000000000001000000000000000000101
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 10 6
000000011010101111000000001000000001000000
000000000000011111000011110011001110000000
001000010000100111000111001101000001000000
100000000000000000000100001001101111000000
110010000000000111000111100000000000000000
010001000000000000100000000101000000000000
000000000000000111100000001000000000000000
000000000000000000000000000001000000000000
000000000000000000000000000000000000000000
000000000000000000000011111111000000000000
000000000100001000000000000001000000000000
000000000000001011000000000001100000000000
000000101100100000000010000000000000000000
000001000000010111000000000001000000000000
010000000000000001000000000000000000000000
110000001000000000000010000111000000000000
.logic_tile 11 6
000000000000000000000000000001100000000000000100000000
000000000000000000000000000000100000000001000000000000
101000000000000000000111100000000000000000000000000000
101000000000000000000100000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011100000000000000000000000000000
000000000100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
.logic_tile 12 6
000000000000000000000000000000001110000100000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000001000000000000000000000000000
100000000000000000000000001111000000000010000000000000
000000000000001000000000000101000000000000000100000000
000000000000000101000000000000000000000001000000000000
000000000000100000000000000000000000000000000100000000
000000000010000000000000001111000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000110010000001110001100000000000000
000000000000000101000010000000011111001100000001100000
000000000000000000000000010000000000000000000000000000
000000000000000000000010010000000000000000000000000000
.io_tile 13 6
000000000000000000
000100000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000000000000
000000000000000000
000000000000000000
000100000000000001
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 7
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 7
000000000100000000000000010000001100110000000100000000
000000000000000000000010000000001010110000000000000000
101000000000000000000000000000011010101000000100000000
000000000000000000000000000011010000010100000000000000
010000000000000001100110000111001100101000000100000000
100000000000000000000010000000000000101000000000000000
000000000000000000000010100111000000100000010100000000
000000000000000000000000000000101100100000010000000000
000000000000000011100000000011001010101000000100000000
000000000000000000100000000000010000101000000000000000
000000000000000000000000000001000000100000010100000000
000000000000000000000000000000101100100000010000000010
000000000000000000000010000000001100101000000100000000
000010000000001001000100001101000000010100000000100000
110000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.logic_tile 2 7
100000000000000101100110101000001001110100010000000000
000000000000000101000000001001011000111000100000000010
111000000000000101000010100000000000000000000000000000
100000000000000101000011100000000000000000000000000000
110000100000001000000000011101111000101000000000000000
000001000100010101000010101001010000111101010010000000
000000000000001000000000000111000000000000000101000000
000000000000000101000010100000000000000001000000000000
000001000000010000000000000000000000000000100000000000
000000000000000000000000000000001111000000000000000000
000000000000000000000000000000011001110001010000000000
000000000000000000000000000101011000110010100010000000
000000000000000101100110000001000001101001010000000000
000010000000000000000100000001001001011001100000000010
010000000000000000000000001000011000101000110000000000
000000000000000000000000001101011011010100110000000001
.ramb_tile 3 7
000000000000001000000000001000000001000000
000010000000001111000000000011001110000000
101000000000001111000111010111000001000000
000000000100000111000111010011101000000000
110000000000100000000000001000000000000000
010001000001000000000000001101000000000000
000010000000001000000011100000000000000000
000001000000001111000000000111000000000000
000000000000000101000000010000000000000000
000000000000000000100011010001000000000000
000000000000000000000000001111000000000000
000000000000001101000000001001000000100000
000000000000000001100110001000000000000000
000000000000001101100100001001000000000000
010000000000000101000000001000000000000000
010000000000000000100000000101000000000000
.logic_tile 4 7
000000000000010000000000000011100000000000000100100001
000000000000000000000000000000100000000001000011000000
001010000000000111100000001001100000111001110000000000
100001000000000000000010100001101010100000010010000000
110000000000001000000011100111100000000000000110100001
010000000000001111000000000000100000000001000000000100
000000000000000000000000000000000000000000000110100001
000000001110000000000000000011000000000010000000100001
000000000000000101100000000011100000000000000110000100
000000000000000000000010000000000000000001000000100000
000000000000000101100110100101000000000000000100000000
000000000000000000000000000000100000000001000010000000
000000000000000000000010100000000000000000100000000000
000000000000000000000000000000001111000000000000000000
010000000001000000000110010111100000010110100100000000
000000000000100000000010100000100000010110100010000010
.logic_tile 5 7
000000000000000000000010110000000001000000001000000000
000000000000000000000110100000001011000000000000001000
000000000000000000000000000101011010001100111000000000
000000000000000000000000000000110000110011000010000000
000010100110101000000110100101001000001100111000000000
000001000000000101000010110000100000110011000000000000
000000000000001000000110100000001000001100111000000000
000000000000000101000010110000001001110011000000000000
000000000000000000000000000101101000001100111000000000
000000000000000000000000000000100000110011000000000000
000000000001010000000000000000001001001100111000000000
000000000000100000000000000000001010110011000000000000
000000000000000000000000000000001000001100111000000000
000000000010000000000000000000001001110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001010110011000000000000
.logic_tile 6 7
100001000000100000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
111000001010000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110000001010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000111101000000000000000000100000000
000000000000000000000100001011000000000010000000000000
000001001000000000000000000000000001000000100100000000
000010000000000000000000000000001111000000000000000000
010000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 7
100001000000100000000000001000000000000000000100000000
000010000000010000000011101101000000000010000000000000
111000000000000000000000000000001000000100000100000000
100000000000000000000000000000010000000000000000000000
110000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011100000001010000100000100000000
000000000000000000000100000000010000000000000000000000
000000000000000000000000001000000000000000000100000000
000100000000000000000000001011000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 8 7
000000000000000000000000000011000000000000000100000000
000000001010000000000000000000000000000001000010000100
001010000000000000000000000000000000000000000000000000
100001000000000000000000000000000000000000000000000000
010000100000100000000111000111100000000000000100000000
110000000000010000000100000000000000000001000000000100
000000000000000000000000000000000001000000100100000000
000000000000000000000000000000001111000000000000000001
000010100000000101100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000100
000000000000000000000000000111000000000010000000000000
000000000001001000000110100000000001000000100100000100
000000000000000101000000000000001110000000000000000000
000000000000001101100000010111000000000000000100000100
000000000000000101000010100000100000000001000000000000
.logic_tile 9 7
000000000000001000000000000000001010000100000100000000
000000000000000111000011110000000000000000000000000000
001000000000001011100000010000000001000000100100000000
101000000000000111100011110000001011000000000000000000
110000001000000111100000000000000000000000100100000000
110000000000001111100000000000001000000000000000000000
000000000000001000000000011000000000000000000100000000
000000000000001111000011100001000000000010000000000000
000000000000000000000000000000011010000100000100000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000001100000000000000100000000
000000000000000000000000000000100000000001000000000000
000000000000000000000111100000000000000000000100000000
000000000000000000000100001001000000000010000000000000
000000000000000000000000000001100000000000000100000000
000000000000000000000000000000000000000001000000000000
.ramb_tile 10 7
000010000000010111100000001000000000000000
000001100000100000000011100101001001000000
101000000000000011100011101111100001100000
000000000010001111100000001001001100000000
110000000010000111100011101000000000000000
110010101100001111100100000011000000000000
000000000000100111000111001000000000000000
000000000001010000000100000001000000000000
000000000000010000000000000000000000000000
000000000110100000000000000101000000000000
000001000000000001000000000101000000100000
000000000000000001000000000001100000000000
000000100001000000000111001000000000000000
000000100000100000000000001101000000000000
010000000000000111000000000000000000000000
010000001000000000100000000101000000000000
.logic_tile 11 7
000000000000000000000110000001100000000000000100000000
000000000000000000000000000000100000000001000001000000
101000000000000000000110000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
010000000000000000000011100000011010000100000100000000
110000000000000000000000000000010000000000000001000000
000000000000000001100000010000000000000000100100000000
000000000000000000000010000000001110000000000001000000
000010100001010000000000000000000001000000100110000000
000001000000100001000000000000001010000000000000000000
000000000000001000000000000000000000000000000110000000
000000000000000001000000001111000000000010000000000000
000000000000011000000000010001000000000000000100000000
000000000000101101000010000000100000000001000001000000
000010000000000000000000000000011100000100000100000000
000001000000100000000000000000000000000000000001000000
.logic_tile 12 7
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000001000000000000000000100000000
000000000000001101000000000111000000000010000000000000
.io_tile 13 7
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000000110010
000000000000010000
001000000000000000
000000000000000000
100000000000000000
000000000000000000
000000000000000000
000000000000000000
000000111000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 8
000000000000000000
000000000000001000
000000000000000000
000000000000000000
000000000000001100
000000000000001100
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000010000000000000
000010010000000000
.logic_tile 1 8
000100000000000000000000000000001010000011110100000001
000000000000000000000000000000000000000011110001000000
101000000000000000000000001000000000000000000100000001
000000000000000000000000000111000000000010000001000010
010000000000001000000011100111100000000000000100000001
110000000000000001000100000000100000000001000000000111
000000000000000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
000000000000000000000000000111100000000000000110000001
000000000000000000000000000000100000000001000000000001
000000000000000000000000000101100000010110100000000000
000000000000000000000000000000000000010110100000000000
010000000000000000000010100000000000000000000000000000
000000000000000101000010100000000000000000000000000000
.logic_tile 2 8
000000000001000000000111010001100000000000000100000000
000000000000000000000111110000000000000001000010000010
101000000000000101000000000000001010000100000100000001
000000000000001101100000000000010000000000000010000000
010000000000000101000010100101101001101000110000000000
010000000000000000100110110000011101101000110000000001
000000000000001000000000000001101010010101010000000010
000000000000001111000011100000010000010101010000000000
000000000000000000000110000000001010000100000100000101
000010000000000000000000000000010000000000000010000010
000000000000000000000010010101000000000000000100000010
000000000000000000000011000000000000000001000010000011
000000000001000000000000000011000000000000000100000000
000000000000100000000000000000100000000001000000000010
010000000000000000000000001000000001101111010000000000
000000000000000000000000001101001101011111100010100001
.ramt_tile 3 8
000000010110011000000000011000000000000000
000000000000101101000010010001001011000000
001000010000001000000110001011100001000000
100000000000000111000100001101101001000000
110000101010001000000110000000000000000000
010001000110001001000100000001000000000000
000000000000001000000000011000000000000000
000000000000001001000011100101000000000000
000001000000010000000000000000000000000000
000010101010100101000010011001000000000000
000000000000001101000000000011100000000000
000000000010001001000011110101000000100000
000000000000000000000000000000000000000000
000000001100000000000000000011000000000000
110000000000000001000000001000000000000000
110000000000000000000000000011000000000000
.logic_tile 4 8
100000000001010000000000000011000000000000000100000000
000000001000000000000000000000100000000001000000000010
111000000001001000000110001000000001011001100000000000
100000000000101001000100001001001011100110010000000000
110010100000000101100000000000000000000000100100000000
000000000010000000000000000000001111000000000000000010
000010100000000001100000010000000000000000000000000000
000001000000000000100010010000000000000000000000000000
000000000000000000000111000000000000000000100100000000
000001000000000000000100000000001110000000000000000010
000000000000000101000000000000000001000000100100000000
000000000000000000100000000000001100000000000000100000
000000000000000101000011100000000000000000000100000001
000001000000000000100000000101000000000010000000000000
010000000000010000000000000101111000010101010000000000
000000000000100000000000000000000000010101010000000001
.logic_tile 5 8
000000000000100101000010100111001000001100111000000000
000000000001010000000000000000000000110011000000010000
001000000001010101000000001000001000001100110000000000
100000000000100000000010100011000000110011000000000000
010000001110001000000111000000001010000100000110000001
110000000000000001000110100000010000000000000001000110
000000000000000000000010100000000000000000100110000000
000000000000000101000000000000001001000000000011000011
000000000000000000000000000001100001011001100000000000
000000000000000000000000000000001001011001100000000001
000000001010000101000000000000011010001100110000000100
000000001100000000100000000000011010001100110000000000
000000001111000000000000000101100000000000000101000101
000000000001111101000000000000000000000001000011000010
010001000000000000000000000000000000011001100000000100
000010100000000000000000000001001011100110010000000000
.logic_tile 6 8
000000000110000000000000000011100000000000000100000000
000000100001010000000000000000000000000001000101000000
001000000000000000000000000111000000011001100010000000
100000000000000000000000000000101111011001100000000000
010000000000000000000111000000000000000000000000000000
110000000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000100100000001
000000000001000101000000000000001100000000000100000000
000000000000000101100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001011000000000110010000000000000000000000000000
000000000000100000000110010000000000000000000000000000
010000000000001000000000001111000000000000000010000000
000000000000001001000000000111100000111111110000000000
.logic_tile 7 8
000000001000000000000000000001100000000000000100000011
000010100000000000000000000000100000000001000001000100
001000000000000001100110000000000000000000000000000000
100000000000000000100100000000000000000000000000000000
010000000000000000000110110000000000000000000000000000
110000000000000000000110010000000000000000000000000000
000000000000000000000000000000000001000000100100000001
000000000000000000000000000000001000000000000000000001
000000000000000000010000000000000000000000000000000000
000000101000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000100100000101
000000000000000000000000000000001011000000000000000001
000000000000000000000011000000000000000000000000000000
000000001100000000000100001111000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 8 8
000001000000000000000000000011101100010000000000000000
000010000000000000000000000000111110010000000000000000
001000000000000000000110000000000001000000100100000000
100000000000000000000100000000001001000000000000000100
010000100000001000000010010101000000000000000100000000
110000000000000001000110010000100000000001000000000000
000000000000000000000000010000000000000000000000000000
000000001100000000000010100000000000000000000000000000
000000000000001000000110101101100000100000010000000010
000000000001000101000000001111101100000000000001000000
000000000000000000000110100011100000000000000000000000
000000000000000000000010000101101111100000010000000000
000000000000000101100000010101101011100000000001000010
000010100000000000000010100000101101100000000000000000
000000000000000000000110000000001111000001000000000000
000000000000000000000000001011001101000010000010000000
.logic_tile 9 8
000000000000001000000000010101111100000010100000000000
000000000001000101000010100000100000000010100000000000
001000000000000000000110100000000001000000100100000000
100000000000000111000000000000001110000000000000000000
010000001000001001100010000011000000101001010000000001
110000000000000001000000000101100000111111110000000000
000000000000000101100000011000001001111000100100000000
000000000000000000000011010111011100110100010000000000
000000000000000000000110000000011010001000000000000000
000000100000000000000000001111011000000100000000000000
000010100000000001100110000101000001000000000010000000
000001000000000000000000001011001101001001000000000000
000000001000000000000010101001101011011111100000000000
000000000000000000000100000001101010101011010001000000
010000000000001000000000000000000000000000000100000000
000000000010000001000000000101000000000010000000000000
.ramt_tile 10 8
000010010000010000000111100000000000000000
000001001100100000000100000011001010000000
001000010000000000000111100111000001100000
100000000000000000000100001001101111000000
110010100000100111100000000000000000000000
010001001111000111100000000111000000000000
000010100001010000000111101000000000000000
000001001100100000000000000111000000000000
000000000010010000000000011000000000000000
000000001110101111000011011101000000000000
000000000000000000000000001111100000100000
000000000000000001000000001001100000000000
000000000000000111100111101000000000000000
000000001100000000000100000111000000000000
110000000000001001000011100000000000000000
010000000000001011000010010101000000000000
.logic_tile 11 8
000010000000000000000000010101011010101000000000000000
000001001100000000000011110000010000101000000010000000
001000000000000000000000000001100000000000000100000000
100000000000001001000011110000100000000001000000000000
010000000000001000000000001000000000111001110010000001
010000000000001111000000000101001110110110110000000001
000000000000000001000000010111011010000010100010000000
000000000000000000000011010000000000000010100000000001
000001000000000101100000000011001111111100100010000001
000010000000000000000000000000011111111100100000000000
000000000000000000000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
000000000000000001100000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
010000000000000000000110100000000000000000000000000000
010000000000000000000000000000000000000000000000000000
.logic_tile 12 8
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000111100000000000000100000000
100000000010000000000000000000100000000001000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001000000000000010100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000110000101100000000000000100000000
000000000000000000000000000000100000000001000000000000
.io_tile 13 8
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000111000000100
000000001000000100
000000000000000000
000000000000000000
010000000000000000
100100000000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 9
000001111000000000
000000001000000000
000000000001100000
000000000000000000
000000000000000100
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 9
000000000000000001100000000000000001000000001000000000
000000000000000000100010100000001010000000000000001000
000000000000001101000000000001111010001100111000000000
000000000000001001000000000000000000110011000000000000
000000000000001101000000000001001000001100111000000000
000000000000001001000000000000000000110011000000000000
000000001110000001100000000101001000001100111000000000
000000000000000000100000000000000000110011000000000000
000000000000000000000000000101001000001100111000000000
000000000000000000000000000000000000110011000000000000
000000000000000000000000000001001000001100111000000000
000000000000001001000000000000100000110011000000000000
000010100000000000000000000001101000001100111000000100
000000000000000000000000000000000000110011000000000000
000000000000000000000000000011101000001100111000000100
000000000000000000000000000000000000110011000000000000
.logic_tile 2 9
000010000000000000000000000111000000000000001000000000
000000000000000101000000000000000000000000000000001000
000000000000000000000000000101101100001100111000000000
000000000000000101000000000000000000110011000000000001
000001000100000101000000000000001001001100111010000000
000000000000000000000000000000001000110011000000000000
000000000000000101000000000101001000001100111010000000
000000000000000000000000000000000000110011000000000000
000001000000101001100000010011001000001100111000000100
000000100001001001100010010000000000110011000000000000
000000000000000000000000000001001000001100111000000100
000000000000000000000000000000000000110011000000000000
000000001111011000000000000000001000001100111000000000
000000000000001001000000000000001101110011000000000000
000000000001010001100000000111101000001100111000000100
000000000000000000100000000000000000110011000000000000
.ramb_tile 3 9
000001000001100000000000001000000001000000
000000100110000000000011110001001110000000
101000000000001000000111100011000001000000
000000000000001011000100000011001001000000
010000000000000111100111100000000000000000
010000000000000000100100001101000000000000
000000000000000111100011100000000000000000
000000000000000000100000000111000000000000
000000000000000001100000001000000000000000
000000000000000111100000000101000000000000
000000000000001111000000000101100000000000
000000000000000111000000001111100000000000
000000000000001000000000000000000000000000
000000000110001001000011100101000000000000
110000000000000001100000001000000000000000
010000000000000000100000000011000000000000
.logic_tile 4 9
000000000000000101000110000101000000000000000110100001
000000000000000000000111100000000000000001000000000000
001000000110000001100000010000000000000000100100000000
100000001110000000100010010000001000000000000000000000
010000000000001001100000010000000000000000000100000000
010000000000001001100010011011000000000010000000000001
000000000000000000000111000111111101010010100000000000
000000000000000000000100001101111101010100100000000000
000000000001000000000000011101011111001000100000000000
000000000000000000000010100111101001100010000000000000
000010001000000000000010000101000000000000000110000111
000000000000000000000010100000000000000001000000000100
000000000000000000000111001001011000110011000000000000
000000000000000000000000001101001111000000000000000000
010000000000001101100110000111111000101000000000000000
000000001100000101000000001001010000000010100000000000
.logic_tile 5 9
000000000000001101000010100000000000000000000100000000
000000000000000111000100000011000000000010000000000000
001000000000000000000010110001100001110000110000000000
100000000000001111000010101111001111000000000000000000
000000000100000001100000000001001010010101010000000000
000000000000000101100000000000000000010101010000000000
000000000000000000000000000011101110100000000000000000
000000000000000111000010110001101001001000000000000000
000000000000100000000000000000000000000000000100000000
000000000000001111000000000001000000000010000000000000
000000000000001000000110000000000000000000100100000000
000000000000000001000110000000001110000000000000000000
000000000000001001000110011001111010100010000000000000
000000000000000001000010000011111010001000100000000000
000000000000000000000000011111011001100000000000000000
000001000000100000000010001011111010001000000000000000
.logic_tile 6 9
000000000000000000000000001011111110111100010100000001
000000000000000000000000001101001010111100001010000010
001010000000000000000010100000000000000000000000000000
100001000000000000000000000000000000000000000000000000
000000000000100101100000000000000000000000000000000000
000000100000010000000000000000000000000000000000000000
000000000000001101100110100000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000000000000000110010000000000000000000000000000
000000000000000000000110010000000000000000000000000000
000000000001011001100000001101111100110011000000000000
000000000000101001000000001001001111000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010110000000000000000000000000000
010000000000000000000000000011000001010000100000000000
000000000000001101000000001011101010001001000000000000
.logic_tile 7 9
000000000000000000000010100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000010000000000000011000000000000000100100000
100000000000100000000000000000100000000001000100000000
010001000000010000000111100000011110000100000000000000
110000000000100000000000000000000000000000000000000000
000000000001000000000000000000000001000000100100000000
000000000000100000000000000000001101000000000100000100
000000100000100000000000010000000001000000100100000100
000001000000010000000010100000001110000000000100000000
000000000000000000000110100000000000000000100100000101
000000000000000000000000000000001001000000000100000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
010001000000001101100000000000000000000000000000000000
000010100000000101000000000000000000000000000000000000
.logic_tile 8 9
000000000000000101000000001000001010000011010000000000
000000000000000000000010101101011001000011100010000000
001000000000000000000000001000000000000000000100000011
100000000000000111000000001011000000000010000000000001
110000001100001000000010010000000000000000100100000011
110000000000001011000010010000001001000000000000000000
000000000000010000000110010101100000111111110000000000
000010100100100000000111101101100000010110100010000000
000000000000000000000000000101011011000000000000000000
000000001000000000000000001101111011000100000000000000
000000001000000000000010000000000000000000000110000111
000000000000000000000000000001000000000010000000000000
000000000000000000000011000000001010000100000100000101
000000000000000000000000000000000000000000000010000010
000000000110000000000000000000011000000100000100000010
000000000100000000000000000000000000000000000000000000
.logic_tile 9 9
000000000000000000000111000001100000000000001000000000
000000000000000000000010100000100000000000000000001000
001010000000001001100110000111000001000010101010100101
100001000000000111000000000000001111000001010001100001
110000000000000000000000000111001000001100110100000000
110000000000000000000000000000101110110011001000000000
000010000000000101000010101001011010001001000000000000
000001000000000000000000000001111001000110100000000001
000000000000000000000011101011111000010100000000000000
000000000000000000000100000111100000000000000000000010
000000000000000000000110000101100000010000100000000000
000000000000000000000100000000001101010000100000000000
000010000000000001100011110001111110001100110100000000
000000000000000000000010000111110000110011001000000000
010000000000000001100000010000000001001111000100000100
010000000000000000100010000000001001001111000000000000
.ramb_tile 10 9
000000000000100000000000000000000000000000
000000010001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000011000000010000000000000000000000000000
000011100000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 9
000000000110000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
001000000000100111100000000000000000000000000000000000
100000000000010000100011110000000000000000000000000000
010010000000000000000010000000000000000000000000000000
110001000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000010000000000000000000000000000000110000000
000010000000100000000000001111000000000010000001000100
000000100000000000000000001000000000010110100000000000
000000000000000000000000000001000000101001010000000000
000000000000000000000111101001101111100000010000000000
000000000000000000000111101001011110010100000001000000
010000000000000111100000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
.logic_tile 12 9
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000010000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110010100000000000000000000000000001000000100000000000
110001000000000000000000000000001100000000000000000000
000000000000000101100000000000000000000000100110000000
000000000000000000000000000000001111000000000001100000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000001001000000000000000000000000000000000000
000000000000000000000011100000000000000000000000000000
000000000000000000000111110000000000000000000000000000
010000100000000000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
.io_tile 13 9
000000000000000000
000000000000001000
000000000000000000
000000000000000001
000000000000001100
000000000000001100
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000010000000000000
000001010000000000
.io_tile 0 10
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000001010000010010
000011011000010000
001110000000000000
000011010000000000
000000000010000000
000100000001000000
000000000000111100
000000000000111100
000001110000000000
000011111000000000
000010000010110010
000011010011100100
.logic_tile 1 10
000000000000000101000000010000001000001100110000000000
000000000100000111000010000000001101110011000000010000
101000000000000101000011110001100000001111000000000000
000000000000001101000110011101001000110000110000000000
000000000000000001100010100001100000000000000100000000
000000000000001101000010100000100000000001000010000000
000000000000000101000110001101011110001100000000000000
000000000000000101000110100101111010110000000000000000
000000000000000000000000001101111110000000110000000000
000000000000000000000010100101001010110000000000000000
000000000000000000000000001000001001011010010000000000
000000000000000000000000000001011011100101100000000100
000000000000000000000000001000000001011001100000000000
000000000000000000000000001101001001100110010010000000
000000000000000000000110000001001010000011110000000000
000000000000000001000000001101010000111100000000000000
.logic_tile 2 10
000000000000000111100000000101101000001100111010000000
000000000000000000100010100000100000110011000000010001
001000000000000101000011100000001000001100110000000000
100000000000000101000010100000001011110011000001000101
000000000001000101000010100000011001000001100000000000
000000000000100000000010111101011000000010010000000000
000000001000100000000010100001001011100000100000000000
000000000000010000000010110000111110100000100000000000
000010000000000000000000000000000000011001100000000000
000000000000000000000000000101001001100110010000000001
000000000000000000000000000000011001001100110000000000
000000000000000000000000000000011000001100110000000001
000000000000000000000000001001000001100000010000000000
000000000000000000000000001001001011001001000000000000
000000000000000000000000000000000000000000000100000000
000000000000001101000000001101000000000010000010000000
.ramt_tile 3 10
000000010000001000000000000000000000000000
000000000000001001000010001101001001000000
001000010000001001100000000101100001000010
100000000000001011100000001011001011000000
110000000000000001000010001000000000000000
010000000000000000000100001101000000000000
000000000000000011100111111000000000000000
000000000000000000100111011111000000000000
000000000000000000000010000000000000000000
000000000000000000000110000101000000000000
000000000000000001000000001001100000000000
000000000000001001000000000011000000000001
000000000000000000000000000000000000000000
000000000000000000000000000001000000000000
110000000000000000000000001000000000000000
010000000000000000000010000001000000000000
.logic_tile 4 10
000000000000010011100000001000000000100110010000000000
000000000000000101000000001001001000011001100000000000
101000000000001011100110010101101101000011110000000000
000000001000000001100011010001101000001111000000000000
000000000000001101000010100000011001100000000000000000
000000000000000111000010001101011000010000000000000000
000000000000000011100011101111011010010010000000000000
000000000000000101000100000111001010000100100000000000
000000000010101000000000010001111110010101000000000000
000000000110000001000010101011011100001010100000000000
000000000000000000000000010000001010000100000100000000
000000000000000001000010100000000000000000000001000000
000000000000000001100000000001000001100110010000000000
000000000000000000000000000000001010100110010000000000
000000000001010000000000011011111100010110000000000000
000000001000100001000010000101101011001001010000000000
.logic_tile 5 10
000000000000001000000011110101101110101011110010100000
000000000000001001000111000000010000101011110010100100
001000000000000111000110000001001110010101010000000000
100000000000000000000100000000110000010101010000000010
000000000000000000000110111000000000000000000100000000
000000100000000000000010101111000000000010000000000000
000000100001000001100000000000000000000000100100000000
000001000000100001000000000000001001000000000000000000
000000000000001111000110000101011101000000010000000000
000000000000001001000010001101111010000000000000000000
000010100000000000000110001001001111000000000000000000
000001000000000000000000001001011000100001000000000000
000010000000010000000011100000000000000000000100000000
000000000000000000000011111011000000000010000000000000
000000000000000001100011100111101100111101100000000000
000000000010000000100000000011001101011011110000000000
.logic_tile 6 10
000000000000001000000111101000001100100000000000000000
000000000000000111000111111001011001010000000000000100
001010100000101000000000010000000000000000100100000000
100001000000010111000010110000001010000000000100000000
110000000000001000000000010000000000000000100100000000
010000000000001111000011100000001100000000000100000000
000000000110000000000000001001011001000000000000000000
000000000000000000000000000011001110100000000000000000
000000000000000000000110000111000000000000000100000000
000000000000000001000011110000100000000001000100000000
000000000001010001000000000000001000000000010010000000
000000000000100000000000001101011101000000100000000001
000000000000000000000000000001000000000000000100000000
000000000110000000000010000000100000000001000100000001
010000000010000000000000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
.logic_tile 7 10
000000000000000000000000001011000000101001010100000000
000000000000000000000010101101000000000000000000000000
001000000000100000000000000101101100000000000000000000
100000001111010000000000000111011111000001000000000000
010000000000000000000110001000001100000001010100000000
010000000000000000000000001101000000000010100000000101
000000000001010001100010000000011010000010100000000000
000000000110000000000000000011010000000001010000000000
000000000000000001000000010000000000000000100000000000
000000000000000000000010000000001011000000000000000000
000000000000001000000000000101100000000000000100000100
000000000000000001000000000011100000010110100000000001
000000000001001000000000010000000000000000000000000000
000000000000100001000010100000000000000000000000000000
110010100001010000000000000000000000000000000000000000
010000000000100000000000000000000000000000000000000000
.logic_tile 8 10
000000000000000011100111010000011111000100000010000001
000000000000000000000111011111011000001000000001000000
001000000000011000000000000101100000000000000111000001
100000000000100001000000000000000000000001000011000100
110000000000000000000110100000000000000000100100000001
010000000000000000000010000000001011000000000001000000
000000001000000011100000000000000000000000100100000000
000000000000000000100000000000001011000000000000000000
000000000000000000000000010000000000000000000100000000
000000000000000000000010011001000000000010000000000000
000000000000000000000000000000000000000000100110000110
000000000000000000000000000000001001000000000010000001
000000000000000000000110000001000000000000000100000000
000000000000000000000000000000000000000001000000000000
000000000001010000000000011001101110000010100010000100
000000001100000000000010001111010000000000000000000010
.logic_tile 9 10
000000000000000000000000010001101101000001000000000000
000000000000000000000011100111111001100001010000000000
001010000000000000000010101000000000000000000100000000
100001000000001101000010100011000000000010000000000000
010000000000000101000010000001111011010010100000000000
010000000000001101100110100101111001000010000000000000
000000100000001001000110000000011100000100000100000000
000001000110010111100010110000000000000000000000000000
000000000000000000000110010101001111101111010000000000
000000000000000000000010001011101011101110000010000000
000011100000001101000000011101011100101001010000000000
000100000000001011100010000101110000010100000010100000
000000000000001001100000000101011001000010000000000000
000000000000000001000000000000111001000010000000000000
010000000000000000000000000001111000101001010000000000
110000000000000000000000000101010000101010100000000000
.ramt_tile 10 10
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
.logic_tile 11 10
000000000000000000000000010011101111100010110100000100
000000000000000000000010010000001111100010110000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 10
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 10
000000000000000000
000100000001000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
001100000000000000
000000000000100000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 11
100000000000000000
000100000000011000
010000000000000000
000000000000011000
100000000000000000
000000000000000000
001100000000000000
100000000000000000
001000000000100000
000100000000000100
000000000000001100
000000000000001100
000001110000000000
000000001000000000
000000000000000000
000000000000000000
.logic_tile 1 11
000000000000000111100010100000000000000000100100000000
000000000000000101000010100000001101000000000000000001
101000100000000101100000000000000000001001000000000000
000000000000000000100011101111001011000110000000000100
000000000000001000000011100101000000000000000100000000
000000001010101101000110110000000000000001000000000000
000000000000000001100000000000011010001100110000000000
000000000000000101100010100000001000001100110000000000
000000000000001000000000010000000000000000000100000000
000000000000000001000010001101000000000010000010000000
000000000000000000000000000000000001100000010000000000
000000000000000000000000001001001010010000100000000000
000000000000000000000000000111111010101011010000000000
000000000000000000000011111001111100000111010000000000
000000000000000000000000001001011000010100000000000000
000000000000000000000010100001010000000010100000000000
.logic_tile 2 11
000000000000000101000000011001111101001000010000000000
000000000000000000000011101101111010000000000000000000
101000000000010101000110000101011001010010000000000000
000000001110100101100010101101101101000000000000000000
110000000000000101000010100000000000000000100100100101
010000000000000101000010100000001010000000000000000000
000000000000101011100010100000000001000000100100000000
000000000000010111000110000000001000000000000000000001
000000000001011000000010001001001010010010100000000000
000000000000011001000010001001001001101000010000000000
000000000000000000000010001011101011001001100000000000
000000000000000000000010000101101011010001100000000000
000000100000000000000000000101000000000000000100000001
000000001010000000000000000000000000000001000000100110
010000000000000000000000001011011100001100110000000000
000000000000000000000000000101011101000100100000000000
.ramb_tile 3 11
010000000000000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001010000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000010100000000000000000000000000000000000
001001000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000001010000000000000000000000000000000
000000000000000000000000000000000000000000
001000001000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000010000000000000000000000000000000
.logic_tile 4 11
000000000000000000000000000000011100000100000100000000
000000000000000000000000000000000000000000000000000000
101000001000000000000000000000000000000000000101000001
000000000000000000000000000111000000000010000001000000
000010000000000000000010000000000001000000100110000000
000000000000000000000000000000001010000000000001100000
000000000000000001100000000000011110000100000100000000
000000000100000000000000000000010000000000000001000000
000000000000000001000010001011001100010100000000000000
000000000000000000100100000111010000000001010000000000
000000000110000001000110000101000000000000000100000000
000000000000000000000000000000100000000001000000000000
000000000000001000000000000011100000000000000110000000
000000000000000001000000000000100000000001000001000000
000000000000000111100110111000000000000000000100000000
000000000000000000100010101111000000000010000000000000
.logic_tile 5 11
000000000000000000000111000000001010000100000101000000
000000000000000000000111100000010000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110000000000000000000000010000000000000000000000000000
110000000000000000000011010000000000000000000000000000
000000000000100000000111000000000000000000000000000000
000000000001010001000000000000000000000000000000000000
000000000000000000000000000000001000000100000100000000
000000000000000000000000000000010000000000000000000000
000000000000000000000000000000011010000100000100000000
000000000000000000000000000000010000000000000000000000
000000000000000000000011100000011010000100000100000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000001000000000000000100000000
000000000000000000000000000000100000000001000000000000
.logic_tile 6 11
000000000000000001100000010001001100000110100000000000
000000000000001101100011100001011111001111110000000000
001000000000100001100110011001100000101001010100000000
100000000000010101000011111001000000000000000100000000
010000001010000101000000000000011000110000000100000000
010000000000000001000010100000011010110000000100000010
000000000000001111100111111000000000000000000000000000
000000000000001111100010000001000000000010000000000000
000000000000000000000110100001101010111110100100000000
000000000000000000000000000000110000111110100100000000
000000001010000111000000001000011010100000000000000000
000000000000000000000000001101001010010000000010000000
000000000000000000000010001101111101010001110000000000
000000000000000000000100001001001011100000110000000000
010000000000000000000000001000011001001000000000000000
000000000000000000000000000101011100000100000000000000
.logic_tile 7 11
000000000000000101100011100111001110010111100000000000
000001000000000101000110100101011011001011100000000000
101000000000001101000000001001001000000110000000000000
101000000000000101000000000001011011000011000000000000
110001000000001101000110011000000001010000100000000000
010000000000000101000010011011001100100000010000000000
000000000000000011100000000001001001000100000000000000
000000000000000000000000001101011000000000000000000000
000000000000001001100110111011001101111111110100000000
000000000000000001000010001111101000101001110000000000
000001000000000101000000010011001110111111100100000000
000010100100000011100010100001011100111110100000000000
000000000000001001000110101011001010000011110100000000
000000000000000011000010110101000000010111110000000000
000000000000000000000110001101001010010111100000000000
000000000000000000000000000011101001001011100000000000
.logic_tile 8 11
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000001000001101100000011000000000000000000100000000
100000000000000101000010100001000000000010000000000000
110001000000000000000000001000000000000000000100000000
110000100000001101000010101001000000000010000000000000
000000000110000101000000000011011110000000000000000000
000000000000000000100000000111101011000010000000000000
000000000000000000000000011000000000000000000100000000
000000000000000000000010010001000000000010000000000000
000010000000000000000000000000011010000100000100000000
000000000000000000000000000000000000000000000010000000
000000000000001000000110101111001010111001010000000000
000000001010001001000100000111011101111100110000000000
000000000000000001100000000000000000000000100100000000
000000000110000000100000000000001010000000000000000000
.logic_tile 9 11
000000000000000101100000000000011011110001010000000000
000000000000000000000010111101011110110010100000000000
001000000000100101000110100000000001000000100100000000
100000000000000000100000000000001001000000000000000000
110000000000000000000110010001000000000000000100000000
110000000000000000000010100000000000000001000000000000
000000000000001111100000000000000001000000100100000000
000000000000000101100011100000001010000000000000000000
000000000000000000000000000111011011110001010000000000
000010000000000000000000000000111111110001010000000000
000000000001100000000000000000000000000000100100000000
000000000110100000000000000000001011000000000000000000
000000000000000000000011110000000000000000000100000000
000000000000000000000010001001000000000010000000000000
010000000001010001100110001000000000000000000100000000
110010000000010000000000000001000000000010000000000000
.ramb_tile 10 11
010000000000000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000111000000000000000000000000000000
001000000000100000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000100000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 11 11
000000000000000011100000010000000000000000000000000000
000000000000000000100011110000000000000000000000000000
101001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000011000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000011011100000100000010100000000
000000000000000000000011101111001000111001110100100000
.logic_tile 12 11
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 11
000001110000000010
000100000000000000
000000000000000000
000000000000000001
000000000000100010
000000000000010000
001100000000000000
000000000000000000
000001110000000000
000000000000000000
000000000000000010
000000000000010000
000000000000100000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 12
000000000100000000
000100000100000001
000000000100000000
010000000100000001
000001010100000000
000000001100000000
001100000100000000
000000000100000000
001000000000000000
000100000000000000
000000000000001100
000000000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 12
010000000000001011100111100101100000000000000100000000
001000000000001001100011100000000000000001000101000101
101000000000001101000111100101000000111111110000000000
000000000000000001000000000101100000000000000000000000
010000000000001000000111011111011101010110000000000000
011000000000001101000111001011001100101001010000000000
000000000000000000000010100000000000000000000000000000
001000000000001101000000000000000000000000000000000000
000000000000000001100000000001101000101000000000000000
001000000000000000000000001101110000000001010000000000
000000000000001001100000011001011110100000000000000000
001000000000001001100010000001011011000000000000000000
000000000000001000000000001000011010111110100100000101
001000000000000001000000001011000000111101010100100011
010000000000000000000110000101111000000000100000000000
001000000000000000000000000011101000000010000000000000
.logic_tile 2 12
010001000000000101000111000001000001100000010000000000
001000000000000000000100000101001010000000000000000000
001000000000000011100111101011111110000000010000000000
100000000000000101000000000111111011000010100000000000
010000000000000001100111110000011011111001000000000000
111000000000001111000011011011011100110110000000000010
000000000000001101000111011111011001000000000000000000
001000000000000111000011100101101111010000000000000000
000000000000000001000010110000011000000100000110000000
001000000000000000000111000000010000000000000110100001
000000000000001000000000000000000000011001100000000000
001000000000000001000010010011001001100110010000000000
000000000000000000000110000000011001001100110000000000
001000000000000000000100000000001011001100110000000010
010000000000000000000110010011100000111001110001000000
001000000000000001000010010101001101010000100000100010
.ramt_tile 3 12
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000100000100000000000000000000000000000
000000000011010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000001000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 12
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
101000000000001011100000001000000000010110100100000000
000000000000011111100000000001000000101001010000000011
010000000000001101000011100101101011010110100000000000
111000000000001111000000000101001000000100100001000000
000000000000000000000111010000011011100010110110000000
001000000000000101000111101011011011010001110001000000
000010100000000000000011100000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 5 12
010000000000000000000000000011100000000000000101000000
001000000000000000000000000000100000000001000000100000
101000000000100000000000000000001010000100000100000000
000000000000000000000000000000010000000000000001000000
000000000000000000000110000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000101000000000000000001000000100100000000
001000000000000101000000000000001110000000000000000000
000000000000000000000000000000011010000100000100000000
001000000000000000000000000000000000000000000000000000
000000000000001000000110000011100000000000000110000000
001000000000000001000000000000000000000001000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000001000000000000000011010000100000100000000
001000000000010011000000000000000000000000000000000000
.logic_tile 6 12
010000000000001000000000000001100000000000000100000000
001000000000000111000000000000000000000001000000000000
001000000000000001000000000000000000000000000000000000
100000000000001101100000000000000000000000000000000000
010000000000000000000110100000000000000000100100000000
111000000000000000000100000000001000000000000000000000
000000000000000011100000000000000000000000000000000000
001000000000000000100000000000000000000000000000000000
000000000000000000000010100000001100000100000000000000
001000000001000000000000000000010000000000000000000000
000000000000000000000000000000011010000100000100000000
001000000000000000000000000000000000000000001000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
011000000001000000000000000000000000000000000000000000
.logic_tile 7 12
010000000000000000000000001000000000100000010100000000
001000000000000000000011101111001011010000100100000000
001000000000000011100111000000011111110000000100000000
100000000000000000000000000000011000110000000100000000
110000000000000000000111001000000001100000010100000000
111000000000000111000000001111001010010000100100000000
000000000000000111000111000001011010001000000010000000
001000100000000000000100000011111110000000000000000000
000000000000000101000110101001100000101001010100000000
001000000000000000000010001111100000000000000100000000
000000000000000000000000000111100000100000010100000000
001000000000000000000000000000101010100000010100000000
000000000000000000000110000011011110000000000001000000
001000000000000001000100001011111001100000000000000000
010000000000000000000110000000000000000000000000000000
001000000000000000000110000000000000000000000000000000
.logic_tile 8 12
010000000000000101100000000111101010101101010100000000
001000000000000001000000001111101110001100000000000000
001000100000000101100010000111001011000011100000000000
001001000000000000000100000000111001000011100000000000
110000000000001001100010110001001100110000000100000000
011000000000000101000010100111001111111001010000000000
000000000000001000000000001000000001100000010000000000
001000000000000101000000000011001110010000100000000000
001000000000000011100010011000011010011110100100000000
001000000000000000100110011111001110101101010000000000
000000000000000001000010000101001111010110110100000000
001000000000000000000100000000001000010110110000000000
000000000000000001100110000101011100110000000100000000
001000000000000000100100000111111111111001010000000000
000000000000000000000110010111001010000011100000000000
001000001010000001000011010000111101000011100000000000
.logic_tile 9 12
010000000000000000000000010000000000000000000000000000
001000000000000000000011010000000000000000000000000000
001000000000001000000000010000000000000000000000000000
100000000000000101000010100000000000000000000000000000
010000000000000000000000011000000000000000000100000000
011000000000000000000010101001000000000010000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000000001101000000000010000000000000
000000000000000000000000000000000001000000100100000000
001000000000000000000000000000001000000000000000100000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.ramt_tile 10 12
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 12
010001000000000000000000000000000000000000000000000000
001010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001100000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 12 12
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
001100000000001101000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000101000000010110100000000000
001000000000000000000000000000000000010110100000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 12
000000000100000010
000000000100000000
110000000100000000
000000000100000001
000000000100010010
000000000100110000
000010000100000000
000010010100011000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 13
000000000100011000
100100000100000000
000010000100000000
000010110100000000
000000000100000000
100000000100000000
001100000100000000
000000000100000000
001000000000100000
000100000000000100
000000000000000100
000000000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 13
010000000000000001000000010101101100000001010000000000
001000000000000101100010000000100000000001010000000000
101000000000001000000000000101000000000000000000000000
000000000000000111000010110101000000010110100000000000
110000000000001101100000000000000001001001000000000000
011000000000000101000000000011001000000110000000000000
000000000000000000000000011001000000000000000100000000
001000000000001101000010010111001000100000010100000000
000000000000001001000000000000001110001000000000000000
001000001000000011000010101001001000000100000000000000
000000000000000000000000000101011001000000000000000001
001000000000000000000000000101011010000001000000000000
000000000000000000000000000101101011001111000000000000
001000000000000001000000000101001001001101000000100000
010000000000001000000000000001000000111111110000000000
001000000000000101000000000111000000010110100000000000
.logic_tile 2 13
010000000000001000000110000011011001000000000000000000
001000000000000101000000000011011101000001000010000000
101000000000000101000010000000000000111001110010000000
000000000000000000000100001111001110110110110000000000
000000000000000000000010100000000000000000000000000000
001000000000000101000000000000000000000000000000000000
000000000000000000000111101001011011010010000000000000
001000000000000000000100001011011000000000000000000000
000000000000001111000000001101001000101001010100000000
001000000000001001100000000111011011110110100000000011
000000000000000011000110010000000000000000000000000000
001000000000000000000010010000000000000000000000000000
000100000000101000000000010000000000000000000000000000
001100000001000001000011010000000000000000000000000000
010000000000000001100111000111100001001001000000000000
001000000000000000100000000000101100001001000000000000
.ramb_tile 3 13
010001000000000000000000000000000000000000
001000110000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001100000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000001000000000000000000000000000000000000
001000100000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 4 13
010010000000010000000111100000001000000100000100000000
001001000000100000000100000000010000000000000000000000
101000000000000111100011101000000000000000000100000000
000000000000000000000000000001000000000010000000000000
110000000000000111100000000101100000000000000100000000
111000000000000000100000000000000000000001000000000000
000000000000001101100000000000000000011001100100000000
001000000000001011100000000011001101100110010000000000
000000000000000001000010000000000000000000100100000000
001000000000000000000000000000001010000000000000000000
000000000000000000000000000111100001011001100100000000
001000000000000000000000000000101001011001100000000000
000000000000000000000111100000000000000000000000000000
001000000000000000000000000000000000000000000000000000
010000000100000000000010000101100000010110100100000000
001000000000000000000000000000000000010110100000000000
.logic_tile 5 13
010000000000001000000000001000000000000000000100000000
001000000000000001000000000101000000000010000000000000
001000000000000000000000000000011010000100000100000000
100000000000000000000000000000010000000000000000000000
000000000000001000000110100000000000000000100100100000
001000000000000101000000000000001000000000000000000000
000000000000001101100110100000000000000000000100100000
001000000000000101000000000011000000000010000000000000
000000000000000001100000000000000000000000100100000000
001000000000000000000000000000001011000000000000100000
000000000000000000000000000000000000000000100100000000
001000000000000000000000000000001010000000000000100000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000010000000000000000000000001000000100100000000
001000000000000000000000000000001010000000000000000010
.logic_tile 6 13
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
101000000000001011100000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
010001000000001001000011100000000000000000000000000000
111010000000001111000100000000000000000000000000000000
000000000000000111000000011101011110001000000010000000
001000000000000000000011101101001010000000000010000000
000000000000000000000000001000011001101111110000000000
001000000000000001000000000011001010011111110000000000
000000000000000000000000001001101010000000000000000100
001000000000000001000000001101001010000100000000000000
000000000000000000000011000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
010000000001000001000000001011001110101000000100000000
001000000000100001000000000111010000111110100100100000
.logic_tile 7 13
010000000000000000000000010011100001011111100100100000
001000000000000000000011101011101000101001010000000000
001000000000001000000110000111011011000000010000000000
100000000000000101000011101101101011000000000000000100
010000100000000011100110010000011111000011100000000000
011001000000000000000111001111011111000011010000000000
000000000000001001000010000101100001000110000000000000
001000000000001011000010001011101001001111000000000000
000000000000000000000010011101101101011011110000000000
001000000000000000000010001001011011001001010000000000
000000000000001000000111010101111101101100000000000000
001000000000001001000110000000111010101100000010000000
000000000000000000000110100001101100100000010000000010
001000000000000000000000001101111010010000000000000100
110000000000000000000110101001100000000000000000000000
011000000000000000000010110101100000101001010000000000
.logic_tile 8 13
010001000000000000000111000101000000000000000100000000
001000100000000000000100000000100000000001000000000000
001000000000001000000000000000011011001000000000000000
100000000000000101000011101001011011000100000000000000
110000001100001000000010110111100000000000000100000000
011000000000010011000011010000100000000001000000000000
000000000000000000000111001101100000100000010000000000
001000000000000000000110001101101001000000000000000000
000000000000000001100000000011001011101000000000000000
001000000000000000000010001101001000000100000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000010111000000000000000100000000
001000000000000000000010110000100000000001000000000000
000000000000000000000000010000011000000100000100000000
001000000000000000000010110000010000000000000000000000
.logic_tile 9 13
010000000000000111100110110000000000000000000000000000
001000000000000000100011100000000000000000000000000000
001000000000000111100000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000001101100111000001101010000000010010000000
011000000000000011000000001101001010000000000000000000
000001000000000000000000000000000000000000000100000000
001000000010010000000000000001000000000010000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000010100000000000000000000111000000100000010000000000
001000000000000000000000000000101001100000010010100000
000010100000000000000111100000000000000000000000000000
001000000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.ramb_tile 10 13
010000000000000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001110000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 11 13
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
001000000000000000000000001000000000000000000110000001
100000000000000000000000001101000000000010000100000000
010000000000000000000010000000000000000000000000000000
111000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
001000000000000000000011000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000001100000100000100000010
001000000000000000000000000000000000000000000100000010
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 12 13
010000001010000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 13
000000111100000000
000100000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000000010
000000000000010000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 14
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 14
000000000000000101000000000000011011111100110000000000
000000000000000000000010010000001010111100110000000001
101000000000000000000000010000000000000000000000000000
000000000000000111000010000000000000000000000000000000
010000000000001000000000000000000000000000000000000000
010000000000001011000010100000000000000000000000000000
000000000000000101000000000001111110010011110000000000
000000000000001101000000000101001011100001010000000000
000000000000000000000000001001000001000000000100000000
000000000000000000000000000011001001100000010100000001
000010100000001000000000000011111001001110000000000000
000000000000000001000000000001011010011110100000100000
000000000000000000000000001001000001001111000100000011
000000000000000000000000000011001001101111010100100010
010000000000000101000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 14
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000101000000001101001010111000110100100000
000000000000000000100000000001101111100000110000000000
010000000000000011100011100000011100000100000000000000
100000000000000000100100000000010000000000000000000000
000000000000000000000000000111100000000000000100100000
000000000000000000000000000000100000000001000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000110000000000000000000000000000000
000000000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 3 14
000000000000100000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 14
000000000000000000000000000000000001000000100100000000
000000000000000000000010100000001011000000000000000000
001000000000000000000000010001100000000000000100100000
100000000000000000000010000000100000000001000000000000
000000000000001101000000010000000000000000100100000000
000000000000000001000010000000001010000000000000000000
000000000000000000000111100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000001010000100000100000000
000000000000000000000000000000010000000000000000100010
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001001000000000000000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001010000000000000100000
.logic_tile 5 14
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000011100000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000000000000111000000011000000011110100100000
110000000000000000000000000000000000000011110000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 6 14
000000000000001000000010100000011010000100000100000000
000000000000001011000011100000000000000000000000000000
001000000000000111100110010000000000000000000000000000
100000000000000000000111100000000000000000000000000000
110000000000000000000000000001000001000000000000000000
010000000000000000000000000001101011100000010000000000
000001000000000000000110000000000001000000100100000000
000000000000000001000100000000001111000000000000000010
000000000000000000000000010111000000000000000100000000
000000000000000000000010000000100000000001000000000000
000000000000000000000110001001001001100000000000000000
000000000000000000000000001011011001110000100000000000
000000000000000000000000001001111110101000010000000000
000000000000000000000010001101001000000100000000000000
000000000000001000000000000001100000000000000100000000
000000000000000001000011100000100000000001000000000000
.logic_tile 7 14
000000000000000001100010110001101010101000010000000000
000000000000001111100011110111101101001000000000000000
001000000000001101100010101101101100100001010000000000
100000000000000111000000001001111110010000000000000000
110000000000001001100110000000000000000000000000000000
110000000000000101000100000000000000000000000000000000
000000000000001000000111011001011101110111110100100000
000000000000001111000010011111001000110110110000000000
000000000011001101000000000001011100101011110100000000
000000000000100001100010000101001001110111110000000010
000000000000001001100000001101011101011110100000000000
000000000000001001000000000111101011011101000000000000
000000000000000101000011000001001000010100000000000000
000000000000000101000000000000010000010100000010000000
010000000000000000000000000011101101111111000100000000
010000000000001101000010110011001010111111101000100000
.logic_tile 8 14
000000000000000101000010110111000001100000010000000000
000000000000000101000011110000101111100000010000000000
001000000000000000000000000111011000010111100000000000
100000000000001101000010110101001001001011100000000000
110000000000001000000000001001000000000000000000000000
010000000000000001000010100011001001010000100000000000
000000000000001001000010101011100000101111010100000000
000000000000000001000111111101001100001111000000000010
000000000000000001100000010101001001010111100000000000
000010000000000000000010100001011001001011100000000000
000000000000001000000000010101111101101111000100000000
000000000000001001000010000000001010101111000000000010
000000000000000101100000011001001011010111100000000000
000000000000000000000010110111111100000111010000000000
000000000000000111000110000011111010110110100100000000
000000000000000000000100000000111010110110100000100000
.logic_tile 9 14
000000000000000000000000000000000000000000100100000000
000000000000000000000011100000001001000000000000000000
001001000000000111000000011000000000000000000100000000
100000100000000000000011110101000000000010000000000000
110000000001010000000010100000000001000000100000000000
110000000000000000000000000000001100000000000000000000
000001000000001111100110000111101100000110100000000000
000000000000000011000000000011001101001111110000000000
000000000000001001100110001011001101010111100010000000
000000000000000001100100001101011001001011100000000000
000000000000001000000000000000000000000000000000000000
000000000000001001000000000000000000000000000000000000
000000000000000000000011101011001100010111100000000000
000000000000000000000000000101101011001011100001000000
000000000000000011100000001000000000000000000100000000
000000000000000000100000000001000000000010000000000000
.ramt_tile 10 14
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001110000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 14
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 14
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
.io_tile 13 14
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000000110010
000000000000010000
001101010000000000
000000001000000000
000000000000000000
000100000000000000
000000000000010010
000000000000110000
000001010000000000
000000001000000001
000000000000000010
000000000000000000
.io_tile 0 15
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 15
000000000000000000000000000111100000000000001000000000
000000000000000000000000000000100000000000000000001000
101000000000000000000000011101011000001000011100000000
000000000000000000000010001101111011010010000100000000
110000000000000001000110000101101000100001000100000000
110000000000000000000010000101101101001000010100000000
000000000000000000000110000111000000010110100000000000
000000000000000101000010100000000000010110100000000000
000000000000000000000000010101101111100000000000000000
000000000000000000000010000111111011000000000000000000
000000000000000000000000001111011010111100000000000000
000000000000000000000000000101011111011100000000000000
000000000000000001100011110000000001001111000000000000
000000000000000000000010000000001011001111000000000000
010000000000000001100000010111100001010000100100000000
000000000000000000000010000000001011010000100100000000
.logic_tile 2 15
000000000000000000000000010000000000000000001000000000
000000000000000000000011000000001011000000000000001000
101000000000001000000000000111101010001000011100000000
000000000000000101000000000101111011010010000100000000
110000000000001001100110010101001000100001000100000000
110000000000001011000011001011001001001000010100000000
000000000000000001100000000000000001001111000000000000
000000000000000000000000000000001111001111000000000000
000000000000000000000000011000000001100000010010000000
000000000010000000000010000011001000010000100000000000
000000000000001000000000000101001101100000000000000000
000000000000001001000000000101011111000000000000100000
000000000000000000000110001111101011010100100100000000
000000000000000000000100000111101010110100010100000000
010000000000000001000110010000001010000011110000000000
000000000000000000000010000000000000000011110000000000
.ramb_tile 3 15
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000001000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000011000000100000100000000
000000001110000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000000000000000000000000000000001110000100000110000000
000000000000000000000000000000010000000000000000000010
000000000000000000000110000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 5 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 6 15
000000000000000000000000000000000000000000000000000000
000000000000000000000011100000000000000000000000000000
001000000000000000000000011000000000000000000100000000
100000000000000000000011110011000000000010000100000000
010000000000000000000000010000000000000000000000000000
010000000000000000000011110000000000000000000000000000
000000000000001000000010000000000000000000000100000000
000000000000000111000000001101000000000010000110000001
000000000000000000000000001000000000000000000100000000
000000000010000000000000001001000000000010000110000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000101100000000000000100000000
000000000000000000000000000000000000000001000100000000
010000000000000000000000000000011010000100000100000000
000000000000000000000000000000010000000000000100000010
.logic_tile 7 15
000010000000000001110110111001000000001001000000000000
000000000000000000000011010001101010000000000000000000
001000000000001000000000010001101010000010100000000000
100000000000000101000010100000100000000010100000000000
010000000000000101100000001001001001001001000000000000
010000000000000000000000001101011000001000000000000000
000000000000000000000110100000000000000000000110000100
000000000000000000000000001011000000000010000100000010
000000000000001000000110100111000001000000000001000000
000000000000000011000100000011001001000110000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001110001000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
010000000000000000000000000001111010000000000000000000
000000000000000000000000001001011000010000010000000000
.logic_tile 8 15
000000000000000101000010110101101111001000010100000000
000000000000000000100110100101101101101101110000000010
001000000000000000000110100011101010011001010100000000
100000000000001101000000001101101110011010100000000000
010000000000000101100110101111101110111001100100000000
110000000000001101000110111101101010110110100000000001
000000000000000101000010100101001000000001110100000000
000000000000000000100110110000011010000001110010000000
000000000000000000000000000001011000111100000100000000
000000000000000000000000000101010000111101010000000100
000010000000000000000000000001101010001101010110000000
000000000000000000000011110000001110001101010010000000
000000000000001000000000000000001000110100110110000000
000000000000000111000000000101011001111000110000000000
000000001000000000000000001101101010010100000100000000
000000000100000000000011111001000000101001010010000000
.logic_tile 9 15
000000000000000000000010100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000010000000000000000011001010111110110100100000
100000000000000000000000001001011111111001110000000000
110000000000000000000110101000000000100000010000000000
010000000000000000000000000011001100010000100000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000010000000000000000000000000000
000000000000001001000011100000000000000000000000000000
000000000100001000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000010010000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramb_tile 10 15
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001010000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000110000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 15
000000111000000010
000100001000000000
000000000000000000
000000000000010001
000000000000010010
000000000000110000
001100000000000000
000001110000000000
000000000000000000
000100000000000000
000000000000000010
000000000000010000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 16
000000000000100111000000001000011010000001010100100000
000000000001010000000011110001000000000010100100000000
101000000000000000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000011100000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000001000001110110110000000000
000000000000000000000000000000001010110110110000100000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 3 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 5 16
000000000000000000000000000111100000010110100000000000
000000000000000000000000000000100000010110100000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000011110000000000000000000000000000
.logic_tile 6 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 16
000000000000001000000000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000100000000000000000000000000000000001111000100000000
000100000000000000000000000000001101001111000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 8 16
000000000000001000000110110000000001000000100100000000
000000000000000011000110010000001110000000000000000000
001000000000000000000000000000011110000100000100000000
100000000000000000000000000000010000000000000000000000
010000000000000000000000010000001000000100000100000000
010000000000000000000011010000010000000000000000000000
000000000000000000000000000000000001000000100100000000
000000000000000000000000000000001101000000000000000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001000000000000000000000
000000000000000000000011100000001110000100000100000000
000000000000000000000000000000000000000000000000000000
000000000000000101100011100000001010000100000100000000
000000000000000000100000000000010000000000000000000000
000000000000000101100110100111000000000000000100000000
000000000000000000100100000000100000000001000000000000
.logic_tile 9 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 10 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 1 17
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 2 17
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000110010
000000000000110000
000000000000000000
000000000000000001
000000000000000010
000011010000000000
.io_tile 3 17
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 17
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000000000000010010
000011110000010000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 5 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000001000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 6 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000100
000000000000001000
000100000000000000
000000000000000000
000010000000000000
000100010000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 7 17
110000000000000000
100000000000000001
010000000000000000
000000000000000001
000000000000001100
000000000000001000
001100000000000000
000000000000000000
000000000000000000
000000000000000000
000010000000000000
000010010000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 8 17
000000000000000000
010000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 9 17
000000000000001000
100000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000001100000
000000000000000000
100000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 10 17
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000000000000100010
000000000000010000
000000000000000000
000000000000000000
000000111000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 11 17
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000010000000010010
000011010000010000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 12 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.ram_data 3 5
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 3
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 5
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 7
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 9
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 3
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 1
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 7
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.sym 1 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 2 r_counter_$glb_clk
.sym 3 lvds_clock_$glb_clk
.sym 4 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 5 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 6 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 7 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 8 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 47 rx_fifo.mem_q.0.3_WDATA
.sym 48 w_rx_09_fifo_data[15]
.sym 51 w_rx_09_fifo_data[13]
.sym 54 w_rx_09_fifo_data[17]
.sym 177 rx_fifo.mem_q.0.2_WDATA_1
.sym 178 rx_fifo.mem_i.0.0_WDATA_1
.sym 179 w_rx_09_fifo_data[8]
.sym 180 w_rx_09_fifo_data[11]
.sym 181 w_rx_09_fifo_data[19]
.sym 182 w_rx_09_fifo_data[9]
.sym 183 w_rx_09_fifo_data[7]
.sym 184 rx_fifo.mem_q.0.2_WDATA
.sym 194 rx_fifo.rd_addr[9]
.sym 291 w_rx_24_fifo_data[9]
.sym 292 w_rx_24_fifo_data[17]
.sym 293 w_rx_24_fifo_data[15]
.sym 295 w_rx_24_fifo_data[19]
.sym 296 w_rx_24_fifo_data[13]
.sym 297 rx_fifo.mem_i.0.0_WDATA
.sym 298 w_rx_24_fifo_data[11]
.sym 405 w_rx_24_fifo_data[23]
.sym 406 rx_fifo.mem_q.0.1_WDATA_1
.sym 407 rx_fifo.mem_q.0.1_WDATA
.sym 408 w_rx_24_fifo_data[5]
.sym 409 w_rx_24_fifo_data[25]
.sym 410 w_rx_24_fifo_data[21]
.sym 411 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 412 w_rx_24_fifo_data[7]
.sym 430 rx_fifo.mem_i.0.0_WDATA
.sym 485 lvds_clock
.sym 492 io_pmod[0]$SB_IO_IN
.sym 497 lvds_clock
.sym 500 $PACKER_VCC_NET
.sym 503 io_pmod[0]$SB_IO_IN
.sym 515 lvds_clock
.sym 516 $PACKER_VCC_NET
.sym 519 w_rx_09_fifo_data[6]
.sym 520 w_rx_09_fifo_data[25]
.sym 521 w_rx_09_fifo_data[23]
.sym 522 rx_fifo.mem_i.0.1_WDATA
.sym 523 rx_fifo.mem_i.0.1_WDATA_1
.sym 524 rx_fifo.mem_i.0.2_WDATA
.sym 525 w_rx_09_fifo_data[21]
.sym 526 w_rx_09_fifo_data[27]
.sym 530 i_rst_b$SB_IO_IN
.sym 551 io_pmod[0]$SB_IO_IN
.sym 552 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 578 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 591 $PACKER_VCC_NET
.sym 633 w_rx_09_fifo_data[31]
.sym 634 w_rx_09_fifo_data[29]
.sym 635 w_rx_09_fifo_data[2]
.sym 636 w_rx_09_fifo_data[3]
.sym 637 w_rx_09_fifo_data[30]
.sym 638 w_rx_09_fifo_data[4]
.sym 639 w_rx_09_fifo_data[5]
.sym 746 rx_fifo.wr_addr[0]
.sym 747 rx_fifo.wr_addr[4]
.sym 748 rx_fifo.wr_addr[6]
.sym 751 rx_fifo.wr_addr[7]
.sym 752 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 756 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 826 $PACKER_GND_NET
.sym 827 $PACKER_GND_NET
.sym 830 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 858 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 861 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
.sym 862 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 863 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 864 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 865 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 866 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 867 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 899 rx_fifo.wr_addr[7]
.sym 906 rx_fifo.wr_addr[0]
.sym 908 rx_fifo.wr_addr[4]
.sym 940 lvds_clock
.sym 944 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 959 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 974 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 975 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
.sym 976 rx_fifo.rd_addr_gray_wr_r[6]
.sym 977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
.sym 978 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
.sym 979 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
.sym 980 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 981 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
.sym 1007 $PACKER_VCC_NET
.sym 1042 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 1051 $PACKER_VCC_NET
.sym 1054 w_lvds_rx_09_d0
.sym 1055 $PACKER_VCC_NET
.sym 1061 $PACKER_GND_NET
.sym 1062 $PACKER_GND_NET
.sym 1066 $PACKER_VCC_NET
.sym 1067 $PACKER_VCC_NET
.sym 1069 $PACKER_VCC_NET
.sym 1071 io_pmod[0]$SB_IO_IN
.sym 1076 $PACKER_GND_NET
.sym 1077 $PACKER_GND_NET
.sym 1078 $PACKER_VCC_NET
.sym 1084 io_pmod[0]$SB_IO_IN
.sym 1085 $PACKER_VCC_NET
.sym 1086 $PACKER_VCC_NET
.sym 1088 rx_fifo.rd_addr_gray_wr_r[4]
.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 1090 rx_fifo.rd_addr_gray_wr[4]
.sym 1091 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 1092 rx_fifo.rd_addr_gray_wr_r[2]
.sym 1093 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
.sym 1094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 1095 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 1116 $PACKER_VCC_NET
.sym 1121 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 1141 io_pmod[0]$SB_IO_IN
.sym 1142 $PACKER_VCC_NET
.sym 1173 w_lvds_rx_09_d0
.sym 1174 w_lvds_rx_09_d1
.sym 1183 $PACKER_VCC_NET
.sym 1184 lvds_clock_$glb_clk
.sym 1199 $PACKER_VCC_NET
.sym 1202 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 1203 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 1204 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
.sym 1206 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 1208 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 1209 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
.sym 1222 rx_fifo.rd_addr_gray_wr_r[8]
.sym 1235 $PACKER_GND_NET
.sym 1241 i_rst_b$SB_IO_IN
.sym 1242 w_lvds_rx_09_d0
.sym 1244 w_lvds_rx_09_d1
.sym 1256 $PACKER_VCC_NET
.sym 1271 w_lvds_rx_09_d1
.sym 1279 $PACKER_GND_NET
.sym 1287 lvds_clock
.sym 1297 $PACKER_VCC_NET
.sym 1305 $PACKER_VCC_NET
.sym 1316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 1317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 1318 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 1319 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 1320 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 1321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 1322 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 1323 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 1324 lvds_clock
.sym 1336 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 1348 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 1360 rx_fifo.rd_addr_gray_wr_r[9]
.sym 1362 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 1401 w_lvds_rx_24_d0
.sym 1402 w_lvds_rx_24_d1
.sym 1411 $PACKER_VCC_NET
.sym 1412 lvds_clock_$glb_clk
.sym 1416 $PACKER_VCC_NET
.sym 1430 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 1433 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
.sym 1434 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 1435 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 1436 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 1462 w_lvds_rx_24_d0
.sym 1463 w_lvds_rx_09_d0
.sym 1464 $PACKER_VCC_NET
.sym 1474 w_lvds_rx_24_d1
.sym 1545 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 1546 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 1547 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 1549 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
.sym 1550 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 1551 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 1690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 1894 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 1945 w_rx_09_fifo_data[5]
.sym 1951 w_rx_24_fifo_data[15]
.sym 2063 rx_fifo.mem_q.0.3_WDATA_1
.sym 2064 rx_fifo.mem_q.0.3_WDATA_2
.sym 2065 w_rx_09_fifo_data[10]
.sym 2066 rx_fifo.mem_q.0.3_WDATA_3
.sym 2067 w_rx_09_fifo_data[12]
.sym 2068 w_rx_09_fifo_data[18]
.sym 2069 w_rx_09_fifo_data[14]
.sym 2070 w_rx_09_fifo_data[16]
.sym 2081 $PACKER_VCC_NET
.sym 2120 rx_fifo.mem_q.0.2_WDATA
.sym 2123 rx_fifo.mem_q.0.2_WDATA_1
.sym 2124 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2125 rx_fifo.mem_i.0.0_WDATA_1
.sym 2128 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2129 w_rx_24_fifo_data[14]
.sym 2143 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2155 w_rx_09_fifo_data[11]
.sym 2156 w_rx_09_fifo_data[13]
.sym 2159 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2169 w_rx_09_fifo_data[15]
.sym 2172 w_rx_24_fifo_data[15]
.sym 2180 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2186 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2187 w_rx_24_fifo_data[15]
.sym 2188 w_rx_09_fifo_data[15]
.sym 2193 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2194 w_rx_09_fifo_data[13]
.sym 2210 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2212 w_rx_09_fifo_data[11]
.sym 2227 w_rx_09_fifo_data[15]
.sym 2229 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2232 lvds_clock_$glb_clk
.sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2234 w_rx_09_fifo_data[20]
.sym 2235 rx_fifo.mem_i.0.0_WDATA_3
.sym 2236 w_rx_09_fifo_data[26]
.sym 2237 rx_fifo.mem_q.0.2_WDATA_3
.sym 2238 w_rx_09_fifo_data[28]
.sym 2239 w_rx_09_fifo_data[22]
.sym 2240 w_rx_09_fifo_data[24]
.sym 2241 rx_fifo.mem_i.0.0_WDATA_2
.sym 2246 rx_fifo.mem_q.0.3_WDATA
.sym 2258 w_rx_09_fifo_data[10]
.sym 2260 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2262 w_rx_09_fifo_data[7]
.sym 2264 rx_fifo.wr_addr[0]
.sym 2265 rx_fifo.wr_addr[4]
.sym 2267 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2268 rx_fifo.wr_addr[6]
.sym 2270 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2271 w_rx_09_fifo_data[6]
.sym 2275 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 2287 w_rx_24_fifo_data[9]
.sym 2291 w_rx_09_fifo_data[5]
.sym 2292 w_rx_09_fifo_data[9]
.sym 2294 w_rx_09_fifo_data[17]
.sym 2296 w_rx_24_fifo_data[17]
.sym 2301 w_rx_09_fifo_data[7]
.sym 2302 w_rx_24_fifo_data[11]
.sym 2304 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2306 w_rx_09_fifo_data[11]
.sym 2308 w_rx_09_fifo_data[6]
.sym 2313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2321 w_rx_09_fifo_data[9]
.sym 2322 w_rx_24_fifo_data[9]
.sym 2323 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2326 w_rx_09_fifo_data[17]
.sym 2327 w_rx_24_fifo_data[17]
.sym 2328 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2333 w_rx_09_fifo_data[6]
.sym 2335 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2338 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2340 w_rx_09_fifo_data[9]
.sym 2345 w_rx_09_fifo_data[17]
.sym 2347 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2350 w_rx_09_fifo_data[7]
.sym 2352 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2358 w_rx_09_fifo_data[5]
.sym 2359 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2362 w_rx_09_fifo_data[11]
.sym 2364 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2365 w_rx_24_fifo_data[11]
.sym 2366 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2367 lvds_clock_$glb_clk
.sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2370 w_rx_24_fifo_data[18]
.sym 2371 rx_fifo.mem_q.0.2_WDATA_2
.sym 2372 w_rx_24_fifo_data[10]
.sym 2373 w_rx_24_fifo_data[8]
.sym 2374 w_rx_24_fifo_data[14]
.sym 2375 w_rx_24_fifo_data[16]
.sym 2376 w_rx_24_fifo_data[12]
.sym 2386 rx_fifo.mem_i.0.0_WDATA_2
.sym 2393 w_rx_09_fifo_data[26]
.sym 2395 w_rx_24_fifo_data[13]
.sym 2396 w_rx_24_fifo_data[26]
.sym 2398 w_rx_09_fifo_data[19]
.sym 2400 rx_fifo.mem_q.0.1_WDATA_1
.sym 2402 rx_fifo.mem_q.0.1_WDATA
.sym 2424 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2426 w_rx_09_fifo_data[19]
.sym 2429 w_rx_24_fifo_data[7]
.sym 2431 w_rx_24_fifo_data[17]
.sym 2435 w_rx_24_fifo_data[13]
.sym 2437 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2438 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2440 w_rx_24_fifo_data[15]
.sym 2445 w_rx_24_fifo_data[11]
.sym 2446 w_rx_24_fifo_data[9]
.sym 2450 w_rx_24_fifo_data[19]
.sym 2455 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2456 w_rx_24_fifo_data[7]
.sym 2462 w_rx_24_fifo_data[15]
.sym 2464 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2467 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2469 w_rx_24_fifo_data[13]
.sym 2479 w_rx_24_fifo_data[17]
.sym 2481 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2485 w_rx_24_fifo_data[11]
.sym 2488 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2491 w_rx_09_fifo_data[19]
.sym 2493 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2494 w_rx_24_fifo_data[19]
.sym 2498 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2499 w_rx_24_fifo_data[9]
.sym 2501 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2502 lvds_clock_$glb_clk
.sym 2503 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2504 rx_fifo.mem_q.0.1_WDATA_3
.sym 2505 rx_fifo.mem_i.0.2_WDATA_2
.sym 2506 w_rx_24_fifo_data[6]
.sym 2507 rx_fifo.mem_i.0.2_WDATA_1
.sym 2508 rx_fifo.mem_q.0.1_WDATA_2
.sym 2509 w_rx_24_fifo_data[27]
.sym 2510 w_rx_24_fifo_data[4]
.sym 2511 w_rx_24_fifo_data[20]
.sym 2520 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2526 rx_fifo.rd_addr[0]
.sym 2530 rx_fifo.wr_addr[6]
.sym 2531 w_rx_09_fifo_data[28]
.sym 2533 rx_fifo.wr_addr[9]
.sym 2535 w_rx_09_fifo_data[20]
.sym 2537 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2538 w_rx_09_fifo_data[4]
.sym 2540 w_rx_09_fifo_data[5]
.sym 2541 rx_fifo.mem_i.0.1_WDATA_1
.sym 2548 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2558 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 2560 w_rx_24_fifo_data[5]
.sym 2561 i_rst_b$SB_IO_IN
.sym 2568 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2569 w_rx_24_fifo_data[19]
.sym 2570 w_rx_09_fifo_data[7]
.sym 2572 w_rx_24_fifo_data[7]
.sym 2577 w_rx_09_fifo_data[5]
.sym 2578 w_rx_24_fifo_data[21]
.sym 2581 w_rx_24_fifo_data[23]
.sym 2585 w_rx_24_fifo_data[3]
.sym 2587 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2588 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2590 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2591 w_rx_24_fifo_data[21]
.sym 2596 w_rx_24_fifo_data[5]
.sym 2598 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2599 w_rx_09_fifo_data[5]
.sym 2602 w_rx_09_fifo_data[7]
.sym 2603 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2604 w_rx_24_fifo_data[7]
.sym 2608 w_rx_24_fifo_data[3]
.sym 2609 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2615 w_rx_24_fifo_data[23]
.sym 2622 w_rx_24_fifo_data[19]
.sym 2623 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2627 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 2628 i_rst_b$SB_IO_IN
.sym 2632 w_rx_24_fifo_data[5]
.sym 2635 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2636 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2637 lvds_clock_$glb_clk
.sym 2638 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2639 w_rx_24_fifo_data[29]
.sym 2640 rx_fifo.mem_i.0.1_WDATA_2
.sym 2641 w_rx_24_fifo_data[22]
.sym 2642 rx_fifo.mem_i.0.1_WDATA_3
.sym 2643 w_rx_24_fifo_data[3]
.sym 2644 w_rx_24_fifo_data[31]
.sym 2645 w_rx_24_fifo_data[2]
.sym 2646 w_rx_24_fifo_data[30]
.sym 2658 $PACKER_VCC_NET
.sym 2665 rx_fifo.wr_addr[4]
.sym 2666 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 2667 rx_fifo.wr_addr[6]
.sym 2672 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2673 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2683 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2692 w_rx_24_fifo_data[23]
.sym 2697 w_rx_24_fifo_data[27]
.sym 2704 w_rx_09_fifo_data[19]
.sym 2705 w_rx_24_fifo_data[21]
.sym 2706 w_rx_09_fifo_data[21]
.sym 2707 w_rx_09_fifo_data[27]
.sym 2711 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2717 w_rx_09_fifo_data[25]
.sym 2718 w_rx_09_fifo_data[23]
.sym 2720 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2722 w_rx_09_fifo_data[4]
.sym 2726 w_rx_09_fifo_data[4]
.sym 2728 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2731 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2733 w_rx_09_fifo_data[23]
.sym 2738 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2740 w_rx_09_fifo_data[21]
.sym 2743 w_rx_09_fifo_data[23]
.sym 2744 w_rx_24_fifo_data[23]
.sym 2745 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2750 w_rx_09_fifo_data[21]
.sym 2751 w_rx_24_fifo_data[21]
.sym 2752 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2755 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 2757 w_rx_24_fifo_data[27]
.sym 2758 w_rx_09_fifo_data[27]
.sym 2762 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2764 w_rx_09_fifo_data[19]
.sym 2768 w_rx_09_fifo_data[25]
.sym 2769 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2771 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2772 lvds_clock_$glb_clk
.sym 2773 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2774 rx_fifo.mem_q.0.0_WDATA
.sym 2776 rx_fifo.mem_i.0.3_WDATA_2
.sym 2777 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 2778 rx_fifo.mem_i.0.1_WDATA
.sym 2779 rx_fifo.mem_i.0.3_WDATA
.sym 2780 rx_fifo.mem_i.0.3_WDATA_1
.sym 2781 rx_fifo.mem_q.0.0_WDATA_2
.sym 2788 rx_fifo.mem_i.0.2_WDATA
.sym 2789 w_rx_24_fifo_data[1]
.sym 2792 rx_fifo.rd_addr[8]
.sym 2795 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 2797 w_rx_24_fifo_data[28]
.sym 2799 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2800 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 2803 rx_fifo.wr_addr[0]
.sym 2805 rx_fifo.wr_addr[4]
.sym 2807 rx_fifo.wr_addr[6]
.sym 2808 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 2810 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 2829 w_rx_09_fifo_data[2]
.sym 2836 w_rx_09_fifo_data[29]
.sym 2837 w_rx_09_fifo_data[28]
.sym 2838 w_rx_09_fifo_data[3]
.sym 2842 w_rx_09_fifo_data[27]
.sym 2844 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2851 w_rx_09_fifo_data[0]
.sym 2854 w_rx_09_fifo_data[1]
.sym 2862 w_rx_09_fifo_data[29]
.sym 2863 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2866 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2869 w_rx_09_fifo_data[27]
.sym 2873 w_rx_09_fifo_data[0]
.sym 2875 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2879 w_rx_09_fifo_data[1]
.sym 2880 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2885 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2887 w_rx_09_fifo_data[28]
.sym 2891 w_rx_09_fifo_data[2]
.sym 2892 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2896 w_rx_09_fifo_data[3]
.sym 2899 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2906 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2907 lvds_clock_$glb_clk
.sym 2908 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2909 rx_fifo.wr_addr[5]
.sym 2910 rx_fifo.wr_addr[3]
.sym 2911 rx_fifo.mem_q.0.0_WDATA_1
.sym 2912 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 2913 rx_fifo.wr_addr[2]
.sym 2914 rx_fifo.wr_addr[1]
.sym 2915 rx_fifo.wr_addr_gray[3]
.sym 2916 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 2922 rx_fifo.wr_addr[6]
.sym 2932 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2935 rx_fifo.wr_addr[7]
.sym 2937 w_rx_09_fifo_data[0]
.sym 2940 w_rx_09_fifo_data[1]
.sym 2945 rx_fifo.wr_addr[6]
.sym 2949 rx_fifo.rd_addr_gray_wr_r[3]
.sym 2950 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 2970 rx_fifo.wr_addr[0]
.sym 2973 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 2974 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 2990 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 2992 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 2993 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 2998 rx_fifo.wr_addr[0]
.sym 3001 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3008 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3026 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3032 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3041 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 3042 lvds_clock_$glb_clk
.sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3045 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 3046 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 3047 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3048 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3049 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3050 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3051 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3055 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3061 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 3064 rx_fifo.mem_i.0.1_WDATA_1
.sym 3065 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 3067 w_rx_24_fifo_data[1]
.sym 3069 rx_fifo.wr_addr[6]
.sym 3072 rx_fifo.wr_addr[2]
.sym 3073 rx_fifo.wr_addr[9]
.sym 3075 rx_fifo.wr_addr[7]
.sym 3076 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3077 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3079 rx_fifo.rd_addr_gray_wr_r[3]
.sym 3083 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
.sym 3088 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 3090 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3098 rx_fifo.wr_addr[3]
.sym 3099 rx_fifo.wr_addr[6]
.sym 3101 rx_fifo.wr_addr[2]
.sym 3102 rx_fifo.wr_addr[7]
.sym 3105 rx_fifo.wr_addr[5]
.sym 3106 rx_fifo.wr_addr[4]
.sym 3110 rx_fifo.wr_addr[1]
.sym 3117 rx_fifo.wr_addr[8]
.sym 3129 $nextpnr_ICESTORM_LC_6$O
.sym 3132 rx_fifo.wr_addr[1]
.sym 3135 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 3137 rx_fifo.wr_addr[2]
.sym 3139 rx_fifo.wr_addr[1]
.sym 3141 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 3143 rx_fifo.wr_addr[3]
.sym 3145 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 3147 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
.sym 3149 rx_fifo.wr_addr[4]
.sym 3151 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 3153 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 3155 rx_fifo.wr_addr[5]
.sym 3157 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 3161 rx_fifo.wr_addr[6]
.sym 3163 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 3167 rx_fifo.wr_addr[7]
.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 3173 rx_fifo.wr_addr[8]
.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 3179 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 3184 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 3186 rx_fifo.wr_addr_gray_rd[9]
.sym 3194 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3202 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 3203 rx_fifo.wr_addr[8]
.sym 3207 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3209 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3212 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 3213 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3215 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3221 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3226 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 3232 rx_fifo.rd_addr_gray_wr_r[3]
.sym 3233 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
.sym 3234 rx_fifo.rd_addr_gray_wr_r[6]
.sym 3236 rx_fifo.rd_addr_gray_wr_r[2]
.sym 3237 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 3238 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3239 rx_fifo.rd_addr_gray_wr[6]
.sym 3240 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3241 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
.sym 3242 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 3243 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 3244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 3245 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 3246 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 3247 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3250 rx_fifo.wr_addr[9]
.sym 3260 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3263 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
.sym 3267 rx_fifo.wr_addr[9]
.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 3271 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 3272 rx_fifo.rd_addr_gray_wr_r[2]
.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
.sym 3278 rx_fifo.rd_addr_gray_wr[6]
.sym 3283 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 3285 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3286 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
.sym 3289 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 3290 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
.sym 3292 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 3297 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 3298 rx_fifo.rd_addr_gray_wr_r[6]
.sym 3301 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3307 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 3308 rx_fifo.rd_addr_gray_wr_r[3]
.sym 3310 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 3312 lvds_clock_$glb_clk
.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
.sym 3315 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 3316 rx_fifo.wr_addr[9]
.sym 3317 rx_fifo.wr_addr_gray[7]
.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 3320 rx_fifo.wr_addr[8]
.sym 3321 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
.sym 3331 rx_fifo.wr_addr_gray_rd[9]
.sym 3332 rx_fifo.rd_addr_gray_wr_r[6]
.sym 3333 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 3335 rx_fifo.rd_addr_gray_wr[6]
.sym 3339 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3340 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 3343 rx_fifo.wr_addr[8]
.sym 3346 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3348 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 3350 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 3359 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3361 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3367 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3368 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3369 rx_fifo.rd_addr_gray_wr_r[6]
.sym 3370 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
.sym 3372 rx_fifo.rd_addr_gray_wr_r[8]
.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3375 rx_fifo.rd_addr_gray[4]
.sym 3377 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
.sym 3378 rx_fifo.rd_addr_gray_wr[2]
.sym 3379 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
.sym 3380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 3381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 3383 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3385 rx_fifo.rd_addr_gray_wr[4]
.sym 3393 i_rst_b$SB_IO_IN
.sym 3397 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 3402 rx_fifo.rd_addr_gray_wr[4]
.sym 3406 i_rst_b$SB_IO_IN
.sym 3408 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
.sym 3413 rx_fifo.rd_addr_gray[4]
.sym 3420 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3421 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 3424 rx_fifo.rd_addr_gray_wr[2]
.sym 3430 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
.sym 3432 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
.sym 3436 rx_fifo.rd_addr_gray_wr_r[6]
.sym 3437 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 3438 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3439 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 3442 rx_fifo.rd_addr_gray_wr_r[8]
.sym 3443 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3445 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3447 lvds_clock_$glb_clk
.sym 3449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 3450 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 3451 rx_fifo.mem_q.0.0_WDATA_3
.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 3453 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 3454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 3455 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 3456 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 3457 rx_fifo.rd_addr_gray[4]
.sym 3462 rx_fifo.rd_addr_gray_wr_r[9]
.sym 3466 rx_fifo.rd_addr_gray_wr[2]
.sym 3468 rx_fifo.rd_addr_gray_wr_r[3]
.sym 3471 rx_fifo.rd_addr_gray_wr_r[2]
.sym 3472 rx_fifo.rd_addr_gray_wr_r[5]
.sym 3476 w_rx_09_fifo_data[0]
.sym 3477 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3480 w_rx_09_fifo_data[1]
.sym 3481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3485 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3486 w_lvds_rx_09_d1
.sym 3493 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3502 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
.sym 3503 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 3504 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3505 rx_fifo.rd_addr_gray_wr_r[8]
.sym 3506 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3507 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
.sym 3509 rx_fifo.rd_addr_gray_wr_r[9]
.sym 3510 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3512 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
.sym 3513 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3514 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3517 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 3519 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3522 w_lvds_rx_09_d0
.sym 3523 w_lvds_rx_09_d1
.sym 3524 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3526 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3533 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
.sym 3536 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3541 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3542 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3547 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3548 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3549 w_lvds_rx_09_d0
.sym 3550 w_lvds_rx_09_d1
.sym 3559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3560 rx_fifo.rd_addr_gray_wr_r[9]
.sym 3562 rx_fifo.rd_addr_gray_wr_r[8]
.sym 3565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
.sym 3566 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
.sym 3567 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
.sym 3568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
.sym 3571 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3574 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3577 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3578 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 3579 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 3580 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 3581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3582 lvds_clock_$glb_clk
.sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3584 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3585 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3587 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 3588 w_rx_fifo_full
.sym 3591 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 3592 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3597 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 3599 rx_fifo.rd_addr_gray_wr_r[8]
.sym 3600 w_rx_data[0]
.sym 3601 w_rx_24_fifo_data[0]
.sym 3608 $PACKER_VCC_NET
.sym 3609 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3611 $PACKER_VCC_NET
.sym 3614 rx_fifo.rd_addr_gray_wr_r[3]
.sym 3617 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3619 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3637 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3638 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3639 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3641 w_lvds_rx_09_d0
.sym 3643 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3645 w_lvds_rx_24_d0
.sym 3646 w_lvds_rx_24_d1
.sym 3649 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3651 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 3653 w_lvds_rx_09_d1
.sym 3654 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3655 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 3661 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3665 w_rx_fifo_full
.sym 3671 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 3673 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3676 w_lvds_rx_24_d0
.sym 3677 w_lvds_rx_24_d1
.sym 3682 w_lvds_rx_09_d1
.sym 3684 w_lvds_rx_09_d0
.sym 3688 w_rx_fifo_full
.sym 3689 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3690 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3694 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3696 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3697 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3700 w_lvds_rx_24_d0
.sym 3701 w_lvds_rx_24_d1
.sym 3702 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3706 w_lvds_rx_24_d1
.sym 3707 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3709 w_lvds_rx_24_d0
.sym 3712 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3713 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3716 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 3717 lvds_clock_$glb_clk
.sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3720 w_rx_09_fifo_data[0]
.sym 3721 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 3722 w_rx_09_fifo_data[1]
.sym 3733 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3740 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3744 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 3747 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3751 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3752 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
.sym 3773 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3774 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3776 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3778 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3780 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3784 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3785 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3792 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3801 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3808 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3823 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3824 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 3825 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3826 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3830 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3831 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3836 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3838 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3842 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3843 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3851 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3852 lvds_clock_$glb_clk
.sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3855 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 3856 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 3857 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 3858 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 3859 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3860 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 3861 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
.sym 3883 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3897 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3913 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 3916 $PACKER_VCC_NET
.sym 3917 $PACKER_VCC_NET
.sym 3918 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
.sym 3919 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3921 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3922 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 3925 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 3932 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 3933 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 3934 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3936 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
.sym 3937 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 3939 $nextpnr_ICESTORM_LC_0$O
.sym 3941 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 3945 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 3946 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3947 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
.sym 3948 $PACKER_VCC_NET
.sym 3949 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 3952 $PACKER_VCC_NET
.sym 3953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3954 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 3955 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 3959 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 3964 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 3965 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3966 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 3967 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 3970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 3971 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 3972 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 3973 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 3978 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 3983 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
.sym 3984 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 3986 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3987 lvds_clock_$glb_clk
.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3989 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 3993 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
.sym 4209 o_shdn_tx_lna$SB_IO_OUT
.sym 4238 w_rx_fifo_pulled_data[12]
.sym 4242 w_rx_fifo_pulled_data[14]
.sym 4366 w_rx_fifo_pulled_data[13]
.sym 4370 w_rx_fifo_pulled_data[15]
.sym 4373 rx_fifo.wr_addr[9]
.sym 4375 rx_fifo.wr_addr[1]
.sym 4376 rx_fifo.wr_addr[9]
.sym 4377 rx_fifo.wr_addr[0]
.sym 4380 rx_fifo.wr_addr[4]
.sym 4383 rx_fifo.wr_addr[6]
.sym 4413 rx_fifo.rd_addr[0]
.sym 4416 w_rx_09_fifo_data[28]
.sym 4420 rx_fifo.wr_addr[2]
.sym 4421 rx_fifo.wr_addr[8]
.sym 4422 rx_fifo.wr_addr[7]
.sym 4424 rx_fifo.mem_q.0.2_WDATA_2
.sym 4426 rx_fifo.wr_addr[1]
.sym 4428 rx_fifo.wr_addr[5]
.sym 4429 rx_fifo.wr_addr[0]
.sym 4431 rx_fifo.wr_addr[4]
.sym 4444 w_rx_09_fifo_data[10]
.sym 4446 w_rx_09_fifo_data[13]
.sym 4449 w_rx_09_fifo_data[16]
.sym 4450 w_rx_24_fifo_data[13]
.sym 4460 w_rx_09_fifo_data[8]
.sym 4462 w_rx_09_fifo_data[12]
.sym 4463 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4464 w_rx_09_fifo_data[14]
.sym 4465 w_rx_24_fifo_data[12]
.sym 4468 w_rx_24_fifo_data[14]
.sym 4473 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4475 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4476 w_rx_24_fifo_data[13]
.sym 4477 w_rx_09_fifo_data[13]
.sym 4481 w_rx_24_fifo_data[14]
.sym 4482 w_rx_09_fifo_data[14]
.sym 4484 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4487 w_rx_09_fifo_data[8]
.sym 4490 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4494 w_rx_09_fifo_data[12]
.sym 4495 w_rx_24_fifo_data[12]
.sym 4496 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4499 w_rx_09_fifo_data[10]
.sym 4502 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4505 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4507 w_rx_09_fifo_data[16]
.sym 4511 w_rx_09_fifo_data[12]
.sym 4514 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4517 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4518 w_rx_09_fifo_data[14]
.sym 4521 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 4522 lvds_clock_$glb_clk
.sym 4523 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4525 w_rx_fifo_pulled_data[8]
.sym 4529 w_rx_fifo_pulled_data[10]
.sym 4546 w_rx_24_fifo_data[13]
.sym 4547 $PACKER_VCC_NET
.sym 4548 rx_fifo.wr_addr[8]
.sym 4551 w_rx_24_fifo_data[12]
.sym 4552 w_rx_09_fifo_data[24]
.sym 4555 rx_fifo.wr_addr[3]
.sym 4559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 4565 w_rx_09_fifo_data[20]
.sym 4566 w_rx_24_fifo_data[18]
.sym 4567 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4569 w_rx_24_fifo_data[8]
.sym 4570 w_rx_09_fifo_data[22]
.sym 4571 w_rx_24_fifo_data[16]
.sym 4572 w_rx_09_fifo_data[16]
.sym 4575 w_rx_09_fifo_data[8]
.sym 4578 w_rx_09_fifo_data[18]
.sym 4579 w_rx_09_fifo_data[24]
.sym 4581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4583 w_rx_09_fifo_data[26]
.sym 4598 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4600 w_rx_09_fifo_data[18]
.sym 4605 w_rx_24_fifo_data[16]
.sym 4606 w_rx_09_fifo_data[16]
.sym 4607 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4611 w_rx_09_fifo_data[24]
.sym 4612 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4617 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4618 w_rx_09_fifo_data[8]
.sym 4619 w_rx_24_fifo_data[8]
.sym 4622 w_rx_09_fifo_data[26]
.sym 4624 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4629 w_rx_09_fifo_data[20]
.sym 4631 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4636 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 4637 w_rx_09_fifo_data[22]
.sym 4640 w_rx_24_fifo_data[18]
.sym 4641 w_rx_09_fifo_data[18]
.sym 4643 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4644 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 4645 lvds_clock_$glb_clk
.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4648 w_rx_fifo_pulled_data[9]
.sym 4652 w_rx_fifo_pulled_data[11]
.sym 4659 w_rx_09_fifo_data[20]
.sym 4660 $PACKER_VCC_NET
.sym 4663 rx_fifo.mem_i.0.0_WDATA_3
.sym 4664 rx_fifo.wr_addr[6]
.sym 4665 rx_fifo.wr_addr[9]
.sym 4669 w_rx_09_fifo_data[28]
.sym 4678 w_rx_09_fifo_data[22]
.sym 4691 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4692 w_rx_09_fifo_data[10]
.sym 4693 w_rx_24_fifo_data[14]
.sym 4698 w_rx_24_fifo_data[6]
.sym 4699 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 4703 w_rx_24_fifo_data[12]
.sym 4707 w_rx_24_fifo_data[10]
.sym 4709 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4710 w_rx_24_fifo_data[16]
.sym 4716 w_rx_24_fifo_data[8]
.sym 4727 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4730 w_rx_24_fifo_data[16]
.sym 4733 w_rx_09_fifo_data[10]
.sym 4734 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4736 w_rx_24_fifo_data[10]
.sym 4739 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4741 w_rx_24_fifo_data[8]
.sym 4746 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4748 w_rx_24_fifo_data[6]
.sym 4751 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4754 w_rx_24_fifo_data[12]
.sym 4758 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4760 w_rx_24_fifo_data[14]
.sym 4763 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4765 w_rx_24_fifo_data[10]
.sym 4767 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 4768 lvds_clock_$glb_clk
.sym 4769 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4771 w_rx_fifo_pulled_data[24]
.sym 4775 w_rx_fifo_pulled_data[26]
.sym 4782 rx_fifo.mem_i.0.0_WDATA_1
.sym 4783 rx_fifo.rd_addr[3]
.sym 4784 rx_fifo.wr_addr[6]
.sym 4785 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4786 rx_fifo.mem_q.0.2_WDATA
.sym 4787 rx_fifo.wr_addr[4]
.sym 4788 rx_fifo.mem_q.0.2_WDATA_1
.sym 4789 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 4791 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 4792 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 4794 rx_fifo.mem_q.0.0_WDATA
.sym 4796 rx_fifo.rd_addr[0]
.sym 4798 w_rx_09_fifo_data[28]
.sym 4812 w_rx_24_fifo_data[18]
.sym 4815 w_rx_09_fifo_data[26]
.sym 4817 w_rx_24_fifo_data[4]
.sym 4818 w_rx_24_fifo_data[26]
.sym 4822 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 4823 w_rx_24_fifo_data[25]
.sym 4825 w_rx_24_fifo_data[2]
.sym 4827 w_rx_09_fifo_data[6]
.sym 4829 w_rx_24_fifo_data[6]
.sym 4830 w_rx_09_fifo_data[4]
.sym 4835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4836 w_rx_09_fifo_data[25]
.sym 4841 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4844 w_rx_24_fifo_data[4]
.sym 4845 w_rx_09_fifo_data[4]
.sym 4847 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4850 w_rx_24_fifo_data[26]
.sym 4852 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4853 w_rx_09_fifo_data[26]
.sym 4857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4858 w_rx_24_fifo_data[4]
.sym 4862 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4863 w_rx_09_fifo_data[25]
.sym 4864 w_rx_24_fifo_data[25]
.sym 4868 w_rx_09_fifo_data[6]
.sym 4869 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4870 w_rx_24_fifo_data[6]
.sym 4874 w_rx_24_fifo_data[25]
.sym 4876 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4883 w_rx_24_fifo_data[2]
.sym 4886 w_rx_24_fifo_data[18]
.sym 4888 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4890 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 4891 lvds_clock_$glb_clk
.sym 4892 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4894 w_rx_fifo_pulled_data[25]
.sym 4898 w_rx_fifo_pulled_data[27]
.sym 4905 rx_fifo.mem_q.0.1_WDATA_3
.sym 4906 rx_fifo.wr_addr[6]
.sym 4909 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 4911 rx_fifo.wr_addr[0]
.sym 4913 rx_fifo.wr_addr[4]
.sym 4915 rx_fifo.mem_q.0.1_WDATA_2
.sym 4917 rx_fifo.wr_addr[5]
.sym 4918 rx_fifo.mem_i.0.3_WDATA_1
.sym 4919 rx_fifo.wr_addr[8]
.sym 4920 rx_fifo.wr_addr[7]
.sym 4922 rx_fifo.wr_addr[9]
.sym 4923 w_rx_24_fifo_data[0]
.sym 4925 rx_fifo.wr_addr[2]
.sym 4926 rx_fifo.wr_addr[0]
.sym 4927 rx_fifo.wr_addr[1]
.sym 4928 rx_fifo.wr_addr[4]
.sym 4936 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 4937 w_rx_09_fifo_data[20]
.sym 4939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4940 w_rx_24_fifo_data[1]
.sym 4941 w_rx_24_fifo_data[20]
.sym 4944 w_rx_24_fifo_data[22]
.sym 4946 w_rx_24_fifo_data[28]
.sym 4947 w_rx_24_fifo_data[27]
.sym 4948 w_rx_09_fifo_data[22]
.sym 4949 w_rx_24_fifo_data[0]
.sym 4950 w_rx_24_fifo_data[29]
.sym 4961 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4967 w_rx_24_fifo_data[27]
.sym 4970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4973 w_rx_09_fifo_data[22]
.sym 4975 w_rx_24_fifo_data[22]
.sym 4976 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4982 w_rx_24_fifo_data[20]
.sym 4985 w_rx_24_fifo_data[20]
.sym 4986 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 4987 w_rx_09_fifo_data[20]
.sym 4993 w_rx_24_fifo_data[1]
.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 4999 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 5000 w_rx_24_fifo_data[29]
.sym 5003 w_rx_24_fifo_data[0]
.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 5009 w_rx_24_fifo_data[28]
.sym 5011 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 5014 lvds_clock_$glb_clk
.sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 5017 w_rx_fifo_pulled_data[20]
.sym 5021 w_rx_fifo_pulled_data[22]
.sym 5028 rx_fifo.mem_q.0.1_WDATA_1
.sym 5031 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 5032 w_rx_24_fifo_data[26]
.sym 5033 rx_fifo.wr_addr[7]
.sym 5034 w_rx_24_fifo_data[22]
.sym 5036 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5038 rx_fifo.mem_q.0.1_WDATA
.sym 5040 rx_fifo.wr_addr[8]
.sym 5041 rx_fifo.wr_addr_gray[3]
.sym 5043 i_rst_b$SB_IO_IN
.sym 5047 rx_fifo.wr_addr[3]
.sym 5051 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5057 w_rx_24_fifo_data[29]
.sym 5058 w_rx_09_fifo_data[29]
.sym 5060 w_rx_09_fifo_data[3]
.sym 5061 w_rx_24_fifo_data[3]
.sym 5062 w_rx_24_fifo_data[31]
.sym 5063 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5064 w_rx_24_fifo_data[30]
.sym 5065 w_rx_09_fifo_data[31]
.sym 5067 w_rx_09_fifo_data[2]
.sym 5069 w_rx_09_fifo_data[30]
.sym 5071 w_rx_24_fifo_data[2]
.sym 5082 w_rx_fifo_pulled_data[20]
.sym 5084 rx_fifo.mem_i.0.1_WDATA
.sym 5090 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5092 w_rx_24_fifo_data[3]
.sym 5093 w_rx_09_fifo_data[3]
.sym 5102 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5103 w_rx_09_fifo_data[30]
.sym 5105 w_rx_24_fifo_data[30]
.sym 5109 w_rx_fifo_pulled_data[20]
.sym 5116 rx_fifo.mem_i.0.1_WDATA
.sym 5120 w_rx_09_fifo_data[31]
.sym 5122 w_rx_24_fifo_data[31]
.sym 5123 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5126 w_rx_24_fifo_data[29]
.sym 5127 w_rx_09_fifo_data[29]
.sym 5128 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5132 w_rx_24_fifo_data[2]
.sym 5134 w_rx_09_fifo_data[2]
.sym 5135 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5140 w_rx_fifo_pulled_data[21]
.sym 5144 w_rx_fifo_pulled_data[23]
.sym 5149 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 5151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 5152 $PACKER_VCC_NET
.sym 5153 rx_fifo.mem_i.0.3_WDATA
.sym 5157 rx_fifo.mem_i.0.3_WDATA_2
.sym 5158 rx_fifo.wr_addr[6]
.sym 5159 rx_fifo.wr_addr[7]
.sym 5161 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 5162 rx_fifo.wr_addr[9]
.sym 5163 rx_fifo.wr_addr[2]
.sym 5174 rx_fifo.mem_q.0.0_WDATA_2
.sym 5182 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5183 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5184 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5189 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5190 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 5191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5192 w_rx_24_fifo_data[1]
.sym 5194 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5199 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 5202 w_rx_09_fifo_data[1]
.sym 5203 i_rst_b$SB_IO_IN
.sym 5214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5222 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5226 w_rx_24_fifo_data[1]
.sym 5227 w_rx_09_fifo_data[1]
.sym 5228 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5232 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5234 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5240 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 5244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5250 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 5255 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5257 i_rst_b$SB_IO_IN
.sym 5259 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5260 lvds_clock_$glb_clk
.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5263 w_rx_fifo_pulled_data[0]
.sym 5267 w_rx_fifo_pulled_data[2]
.sym 5274 rx_fifo.wr_addr[5]
.sym 5275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 5276 rx_fifo.wr_addr[1]
.sym 5278 rx_fifo.wr_addr[3]
.sym 5279 rx_fifo.rd_addr[3]
.sym 5282 rx_fifo.wr_addr[8]
.sym 5284 rx_fifo.wr_addr[2]
.sym 5285 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 5286 rx_fifo.mem_q.0.0_WDATA
.sym 5287 rx_fifo.mem_q.0.0_WDATA_1
.sym 5288 rx_fifo.rd_addr[0]
.sym 5292 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5293 rx_fifo.wr_addr[1]
.sym 5296 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5303 rx_fifo.wr_addr[5]
.sym 5307 rx_fifo.wr_addr[2]
.sym 5312 rx_fifo.wr_addr[3]
.sym 5316 rx_fifo.wr_addr[1]
.sym 5319 rx_fifo.wr_addr[0]
.sym 5320 rx_fifo.wr_addr[4]
.sym 5321 rx_fifo.wr_addr[6]
.sym 5327 rx_fifo.wr_addr[0]
.sym 5332 rx_fifo.wr_addr[7]
.sym 5335 $nextpnr_ICESTORM_LC_4$O
.sym 5337 rx_fifo.wr_addr[0]
.sym 5341 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5343 rx_fifo.wr_addr[1]
.sym 5345 rx_fifo.wr_addr[0]
.sym 5347 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5350 rx_fifo.wr_addr[2]
.sym 5351 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5355 rx_fifo.wr_addr[3]
.sym 5357 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5359 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5361 rx_fifo.wr_addr[4]
.sym 5363 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5365 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5367 rx_fifo.wr_addr[5]
.sym 5369 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5371 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 5374 rx_fifo.wr_addr[6]
.sym 5375 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 5377 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 5379 rx_fifo.wr_addr[7]
.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 5386 w_rx_fifo_pulled_data[1]
.sym 5390 w_rx_fifo_pulled_data[3]
.sym 5399 rx_fifo.wr_addr[0]
.sym 5401 rx_fifo.rd_addr[9]
.sym 5402 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5403 rx_fifo.wr_addr[8]
.sym 5405 rx_fifo.wr_addr[4]
.sym 5407 rx_fifo.wr_addr[6]
.sym 5410 rx_fifo.wr_addr[8]
.sym 5411 rx_fifo.rd_addr_gray_wr_r[0]
.sym 5412 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5413 rx_fifo.mem_q.0.0_WDATA_3
.sym 5414 w_rx_24_fifo_data[0]
.sym 5415 rx_fifo.wr_addr[7]
.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5418 rx_fifo.wr_addr[9]
.sym 5419 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5421 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 5427 rx_fifo.rd_addr_gray_wr_r[6]
.sym 5428 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 5430 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5431 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5432 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5433 rx_fifo.rd_addr_gray_wr_r[3]
.sym 5435 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5436 rx_fifo.wr_addr[9]
.sym 5437 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5440 rx_fifo.wr_addr[8]
.sym 5441 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5454 rx_fifo.rd_addr_gray_wr_r[2]
.sym 5458 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 5460 rx_fifo.wr_addr[8]
.sym 5462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 5467 rx_fifo.wr_addr[9]
.sym 5468 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 5471 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5473 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5474 rx_fifo.rd_addr_gray_wr_r[3]
.sym 5478 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 5479 rx_fifo.rd_addr_gray_wr_r[2]
.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5483 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5485 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 5491 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5496 rx_fifo.rd_addr_gray_wr_r[6]
.sym 5497 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5501 rx_fifo.wr_addr[9]
.sym 5506 r_counter_$glb_clk
.sym 5522 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 5524 $PACKER_VCC_NET
.sym 5526 io_pmod[0]$SB_IO_IN
.sym 5533 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5536 rx_fifo.wr_addr[8]
.sym 5537 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 5539 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 5540 w_rx_fifo_full
.sym 5550 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5551 rx_fifo.rd_addr_gray_wr_r[8]
.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 5554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
.sym 5557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 5560 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 5561 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5562 rx_fifo.wr_addr[2]
.sym 5563 rx_fifo.wr_addr[1]
.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5567 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5571 rx_fifo.rd_addr_gray_wr_r[0]
.sym 5572 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5582 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5583 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
.sym 5584 rx_fifo.wr_addr[2]
.sym 5585 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5588 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 5590 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5602 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 5607 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5608 rx_fifo.rd_addr_gray_wr_r[8]
.sym 5609 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5612 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5613 rx_fifo.rd_addr_gray_wr_r[0]
.sym 5614 rx_fifo.wr_addr[1]
.sym 5615 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5624 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 5627 rx_fifo.rd_addr_gray_wr_r[0]
.sym 5628 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5629 lvds_clock_$glb_clk
.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5645 rx_fifo.rd_addr_gray_wr_r[8]
.sym 5647 $PACKER_VCC_NET
.sym 5649 rx_fifo.rd_addr_gray_wr_r[5]
.sym 5652 $PACKER_VCC_NET
.sym 5653 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5658 rx_fifo.wr_addr_gray[7]
.sym 5673 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 5675 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5676 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 5677 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5679 w_rx_data[0]
.sym 5680 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5681 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 5682 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5683 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 5685 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 5686 w_rx_24_fifo_data[0]
.sym 5687 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5689 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5690 w_rx_09_fifo_data[0]
.sym 5691 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 5692 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5694 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5699 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 5700 w_rx_fifo_full
.sym 5702 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 5703 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5705 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 5706 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 5707 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 5711 w_rx_fifo_full
.sym 5712 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5714 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 5717 w_rx_09_fifo_data[0]
.sym 5719 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5720 w_rx_24_fifo_data[0]
.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 5732 w_rx_data[0]
.sym 5735 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5737 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5743 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5744 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5747 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5748 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 5751 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 5752 r_counter_$glb_clk
.sym 5753 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5766 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5769 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 5776 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5780 rx_fifo.rd_addr_gray_wr_r[9]
.sym 5783 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5784 w_lvds_rx_09_d1
.sym 5789 w_lvds_rx_09_d0
.sym 5795 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 5798 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 5800 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 5802 w_lvds_rx_09_d1
.sym 5803 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 5806 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 5810 rx_fifo.rd_addr_gray_wr_r[7]
.sym 5811 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 5812 w_lvds_rx_09_d0
.sym 5816 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 5817 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 5818 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 5819 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5821 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5824 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 5826 rx_fifo.rd_addr_gray_wr_r[3]
.sym 5828 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 5829 w_lvds_rx_09_d0
.sym 5830 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 5831 w_lvds_rx_09_d1
.sym 5834 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5836 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5846 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 5847 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 5848 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 5849 rx_fifo.rd_addr_gray_wr_r[7]
.sym 5852 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 5853 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 5854 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 5855 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 5871 rx_fifo.rd_addr_gray_wr_r[3]
.sym 5872 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 5875 lvds_clock_$glb_clk
.sym 5876 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5886 rx_fifo.wr_addr[1]
.sym 5889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5892 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 5906 w_rx_fifo_full
.sym 5910 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 5923 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5927 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 5929 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 5941 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 5944 w_lvds_rx_09_d1
.sym 5949 w_lvds_rx_09_d0
.sym 5957 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5958 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 5959 w_lvds_rx_09_d1
.sym 5960 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 5966 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 5970 w_lvds_rx_09_d0
.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 5998 lvds_clock_$glb_clk
.sym 6017 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 6043 $PACKER_VCC_NET
.sym 6045 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 6050 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 6051 $PACKER_VCC_NET
.sym 6052 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 6059 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 6061 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6068 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
.sym 6070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6071 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 6072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
.sym 6073 $nextpnr_ICESTORM_LC_7$O
.sym 6076 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 6079 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3
.sym 6080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 6081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
.sym 6082 $PACKER_VCC_NET
.sym 6083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 6086 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 6087 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 6088 $PACKER_VCC_NET
.sym 6089 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3
.sym 6094 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 6098 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 6104 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 6105 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 6107 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 6110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 6112 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 6113 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 6120 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
.sym 6121 lvds_clock_$glb_clk
.sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 6139 rx_fifo.rd_addr_gray_wr_r[3]
.sym 6165 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6166 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
.sym 6168 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 6176 w_rx_fifo_full
.sym 6177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 6197 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 6200 w_rx_fifo_full
.sym 6222 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 6223 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 6243 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
.sym 6244 lvds_clock_$glb_clk
.sym 6245 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 6257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 6258 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
.sym 6294 o_shdn_tx_lna$SB_IO_OUT
.sym 6314 o_shdn_tx_lna$SB_IO_OUT
.sym 6381 w_smi_data_output[6]
.sym 6389 rx_fifo.wr_addr[9]
.sym 6391 rx_fifo.wr_addr[0]
.sym 6392 rx_fifo.wr_addr[4]
.sym 6395 rx_fifo.wr_addr[6]
.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6400 rx_fifo.wr_addr[3]
.sym 6404 rx_fifo.wr_addr[1]
.sym 6406 $PACKER_VCC_NET
.sym 6408 rx_fifo.wr_addr[8]
.sym 6409 rx_fifo.wr_addr[7]
.sym 6411 rx_fifo.mem_q.0.3_WDATA_2
.sym 6413 rx_fifo.mem_q.0.3_WDATA_3
.sym 6414 rx_fifo.wr_addr[5]
.sym 6415 rx_fifo.wr_addr[2]
.sym 6422 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 6424 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 6438 rx_fifo.wr_addr[2]
.sym 6439 rx_fifo.wr_addr[3]
.sym 6441 rx_fifo.wr_addr[4]
.sym 6442 rx_fifo.wr_addr[5]
.sym 6443 rx_fifo.wr_addr[6]
.sym 6444 rx_fifo.wr_addr[7]
.sym 6445 rx_fifo.wr_addr[8]
.sym 6446 rx_fifo.wr_addr[9]
.sym 6447 rx_fifo.wr_addr[1]
.sym 6448 rx_fifo.wr_addr[0]
.sym 6449 lvds_clock_$glb_clk
.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6452 rx_fifo.mem_q.0.3_WDATA_3
.sym 6456 rx_fifo.mem_q.0.3_WDATA_2
.sym 6459 $PACKER_VCC_NET
.sym 6469 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6472 rx_fifo.wr_addr[3]
.sym 6478 $PACKER_VCC_NET
.sym 6493 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6497 rx_fifo.rd_addr[6]
.sym 6500 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6505 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6506 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6508 w_rx_fifo_pulled_data[9]
.sym 6511 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6512 rx_fifo.rd_addr[3]
.sym 6514 w_smi_data_output[1]
.sym 6515 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6517 w_rx_fifo_pulled_data[11]
.sym 6528 rx_fifo.mem_q.0.3_WDATA_1
.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6531 rx_fifo.rd_addr[0]
.sym 6532 $PACKER_VCC_NET
.sym 6537 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6540 rx_fifo.rd_addr[3]
.sym 6541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6542 rx_fifo.rd_addr[9]
.sym 6544 rx_fifo.mem_q.0.3_WDATA
.sym 6549 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6553 rx_fifo.rd_addr[6]
.sym 6555 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6557 rx_fifo.rd_addr[8]
.sym 6558 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6560 tx_fifo.rd_addr_gray[1]
.sym 6561 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 6562 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
.sym 6564 tx_fifo.rd_addr_gray[4]
.sym 6565 tx_fifo.rd_addr_gray[2]
.sym 6566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 6576 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6577 rx_fifo.rd_addr[3]
.sym 6579 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6581 rx_fifo.rd_addr[6]
.sym 6582 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6583 rx_fifo.rd_addr[8]
.sym 6584 rx_fifo.rd_addr[9]
.sym 6585 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6586 rx_fifo.rd_addr[0]
.sym 6587 r_counter_$glb_clk
.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6589 $PACKER_VCC_NET
.sym 6593 rx_fifo.mem_q.0.3_WDATA
.sym 6597 rx_fifo.mem_q.0.3_WDATA_1
.sym 6605 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 6607 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 6614 $PACKER_VCC_NET
.sym 6616 w_rx_fifo_pulled_data[10]
.sym 6618 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 6623 rx_fifo.rd_addr[8]
.sym 6624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 6625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 6630 rx_fifo.mem_q.0.2_WDATA_2
.sym 6631 rx_fifo.wr_addr[9]
.sym 6632 rx_fifo.wr_addr[1]
.sym 6634 $PACKER_VCC_NET
.sym 6635 rx_fifo.wr_addr[0]
.sym 6636 rx_fifo.wr_addr[6]
.sym 6637 rx_fifo.wr_addr[7]
.sym 6641 rx_fifo.mem_q.0.2_WDATA_3
.sym 6642 rx_fifo.wr_addr[5]
.sym 6643 rx_fifo.wr_addr[2]
.sym 6645 rx_fifo.wr_addr[4]
.sym 6648 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6655 rx_fifo.wr_addr[8]
.sym 6660 rx_fifo.wr_addr[3]
.sym 6662 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 6663 tx_fifo.rd_addr_gray_wr_r[0]
.sym 6664 tx_fifo.rd_addr_gray_wr[9]
.sym 6665 tx_fifo.rd_addr_gray_wr[0]
.sym 6666 tx_fifo.rd_addr_gray_wr[8]
.sym 6667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 6668 tx_fifo.rd_addr_gray_wr[1]
.sym 6669 tx_fifo.rd_addr_gray_wr_r[1]
.sym 6678 rx_fifo.wr_addr[2]
.sym 6679 rx_fifo.wr_addr[3]
.sym 6681 rx_fifo.wr_addr[4]
.sym 6682 rx_fifo.wr_addr[5]
.sym 6683 rx_fifo.wr_addr[6]
.sym 6684 rx_fifo.wr_addr[7]
.sym 6685 rx_fifo.wr_addr[8]
.sym 6686 rx_fifo.wr_addr[9]
.sym 6687 rx_fifo.wr_addr[1]
.sym 6688 rx_fifo.wr_addr[0]
.sym 6689 lvds_clock_$glb_clk
.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6692 rx_fifo.mem_q.0.2_WDATA_3
.sym 6696 rx_fifo.mem_q.0.2_WDATA_2
.sym 6699 $PACKER_VCC_NET
.sym 6705 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 6709 w_tx_fifo_pull
.sym 6710 i_rst_b$SB_IO_IN
.sym 6719 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 6720 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6727 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6732 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6734 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6737 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6741 rx_fifo.mem_q.0.2_WDATA_1
.sym 6744 rx_fifo.rd_addr[3]
.sym 6747 rx_fifo.mem_q.0.2_WDATA
.sym 6750 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6752 $PACKER_VCC_NET
.sym 6753 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6755 rx_fifo.rd_addr[9]
.sym 6756 rx_fifo.rd_addr[0]
.sym 6757 rx_fifo.rd_addr[6]
.sym 6759 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6761 rx_fifo.rd_addr[8]
.sym 6764 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 6767 rx_fifo.mem_i.0.2_WDATA_3
.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 6770 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 6771 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 6780 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6781 rx_fifo.rd_addr[3]
.sym 6783 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6784 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6785 rx_fifo.rd_addr[6]
.sym 6786 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6787 rx_fifo.rd_addr[8]
.sym 6788 rx_fifo.rd_addr[9]
.sym 6789 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6790 rx_fifo.rd_addr[0]
.sym 6791 r_counter_$glb_clk
.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6793 $PACKER_VCC_NET
.sym 6797 rx_fifo.mem_q.0.2_WDATA
.sym 6801 rx_fifo.mem_q.0.2_WDATA_1
.sym 6814 rx_fifo.wr_addr[5]
.sym 6816 rx_fifo.wr_addr[8]
.sym 6817 rx_fifo.wr_addr[2]
.sym 6819 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6821 rx_fifo.rd_addr[9]
.sym 6823 rx_fifo.rd_addr[6]
.sym 6824 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 6825 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6827 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6835 rx_fifo.wr_addr[0]
.sym 6836 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6838 rx_fifo.wr_addr[6]
.sym 6840 rx_fifo.wr_addr[8]
.sym 6843 rx_fifo.mem_i.0.2_WDATA_2
.sym 6845 rx_fifo.wr_addr[4]
.sym 6848 rx_fifo.wr_addr[3]
.sym 6851 rx_fifo.wr_addr[9]
.sym 6854 rx_fifo.wr_addr[2]
.sym 6856 rx_fifo.wr_addr[1]
.sym 6857 rx_fifo.wr_addr[7]
.sym 6861 rx_fifo.mem_i.0.2_WDATA_3
.sym 6862 rx_fifo.wr_addr[5]
.sym 6863 $PACKER_VCC_NET
.sym 6867 w_rx_24_fifo_data[24]
.sym 6871 w_rx_24_fifo_data[26]
.sym 6872 w_rx_24_fifo_data[28]
.sym 6882 rx_fifo.wr_addr[2]
.sym 6883 rx_fifo.wr_addr[3]
.sym 6885 rx_fifo.wr_addr[4]
.sym 6886 rx_fifo.wr_addr[5]
.sym 6887 rx_fifo.wr_addr[6]
.sym 6888 rx_fifo.wr_addr[7]
.sym 6889 rx_fifo.wr_addr[8]
.sym 6890 rx_fifo.wr_addr[9]
.sym 6891 rx_fifo.wr_addr[1]
.sym 6892 rx_fifo.wr_addr[0]
.sym 6893 lvds_clock_$glb_clk
.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6896 rx_fifo.mem_i.0.2_WDATA_3
.sym 6900 rx_fifo.mem_i.0.2_WDATA_2
.sym 6903 $PACKER_VCC_NET
.sym 6910 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 6911 w_rx_09_fifo_data[24]
.sym 6913 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 6915 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 6916 rx_fifo.wr_addr[8]
.sym 6920 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6922 rx_fifo.rd_addr[9]
.sym 6923 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 6925 rx_fifo.rd_addr[3]
.sym 6927 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 6928 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6930 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6931 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 6936 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6938 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6939 rx_fifo.rd_addr[9]
.sym 6942 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6947 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6954 rx_fifo.mem_i.0.2_WDATA
.sym 6956 rx_fifo.rd_addr[8]
.sym 6959 rx_fifo.rd_addr[0]
.sym 6960 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6961 rx_fifo.rd_addr[6]
.sym 6963 rx_fifo.mem_i.0.2_WDATA_1
.sym 6964 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6965 $PACKER_VCC_NET
.sym 6966 rx_fifo.rd_addr[3]
.sym 6968 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6969 rx_fifo.mem_i.0.3_WDATA_3
.sym 6970 rx_fifo.rd_addr[6]
.sym 6971 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6972 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6973 rx_fifo.rd_addr_gray[3]
.sym 6974 rx_fifo.rd_addr[3]
.sym 6975 rx_fifo.rd_addr[0]
.sym 6984 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 6985 rx_fifo.rd_addr[3]
.sym 6987 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 6988 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 6989 rx_fifo.rd_addr[6]
.sym 6990 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 6991 rx_fifo.rd_addr[8]
.sym 6992 rx_fifo.rd_addr[9]
.sym 6993 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 6994 rx_fifo.rd_addr[0]
.sym 6995 r_counter_$glb_clk
.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 6997 $PACKER_VCC_NET
.sym 7001 rx_fifo.mem_i.0.2_WDATA
.sym 7005 rx_fifo.mem_i.0.2_WDATA_1
.sym 7023 rx_fifo.rd_addr[8]
.sym 7029 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 7031 $PACKER_VCC_NET
.sym 7038 rx_fifo.wr_addr[6]
.sym 7042 $PACKER_VCC_NET
.sym 7043 rx_fifo.wr_addr[0]
.sym 7044 rx_fifo.wr_addr[8]
.sym 7045 rx_fifo.wr_addr[7]
.sym 7050 rx_fifo.wr_addr[9]
.sym 7053 rx_fifo.wr_addr[4]
.sym 7055 rx_fifo.wr_addr[3]
.sym 7056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 7058 rx_fifo.wr_addr[2]
.sym 7062 rx_fifo.wr_addr[5]
.sym 7063 rx_fifo.mem_i.0.1_WDATA_2
.sym 7065 rx_fifo.mem_i.0.1_WDATA_3
.sym 7067 rx_fifo.wr_addr[1]
.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 7071 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 7072 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 7074 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 7077 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 7086 rx_fifo.wr_addr[2]
.sym 7087 rx_fifo.wr_addr[3]
.sym 7089 rx_fifo.wr_addr[4]
.sym 7090 rx_fifo.wr_addr[5]
.sym 7091 rx_fifo.wr_addr[6]
.sym 7092 rx_fifo.wr_addr[7]
.sym 7093 rx_fifo.wr_addr[8]
.sym 7094 rx_fifo.wr_addr[9]
.sym 7095 rx_fifo.wr_addr[1]
.sym 7096 rx_fifo.wr_addr[0]
.sym 7097 lvds_clock_$glb_clk
.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 7100 rx_fifo.mem_i.0.1_WDATA_3
.sym 7104 rx_fifo.mem_i.0.1_WDATA_2
.sym 7107 $PACKER_VCC_NET
.sym 7112 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 7114 w_rx_fifo_pulled_data[22]
.sym 7115 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7117 rx_fifo.rd_addr[0]
.sym 7119 w_rx_09_fifo_data[28]
.sym 7123 rx_fifo.rd_addr[6]
.sym 7124 rx_fifo.rd_addr[6]
.sym 7127 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 7128 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7130 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 7134 w_rx_fifo_pulled_data[3]
.sym 7135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7140 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 7142 rx_fifo.rd_addr[6]
.sym 7144 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 7147 rx_fifo.rd_addr[0]
.sym 7148 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 7151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7152 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7154 rx_fifo.rd_addr[3]
.sym 7156 rx_fifo.rd_addr[8]
.sym 7158 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7160 rx_fifo.mem_i.0.1_WDATA
.sym 7161 rx_fifo.rd_addr[9]
.sym 7162 rx_fifo.mem_i.0.1_WDATA_1
.sym 7169 $PACKER_VCC_NET
.sym 7172 rx_fifo.rd_addr[8]
.sym 7173 rx_fifo.rd_addr_gray[6]
.sym 7174 rx_fifo.rd_addr_gray[8]
.sym 7175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
.sym 7176 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 7177 rx_fifo.rd_addr[9]
.sym 7178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 7179 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
.sym 7188 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 7189 rx_fifo.rd_addr[3]
.sym 7191 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 7192 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7193 rx_fifo.rd_addr[6]
.sym 7194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 7195 rx_fifo.rd_addr[8]
.sym 7196 rx_fifo.rd_addr[9]
.sym 7197 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7198 rx_fifo.rd_addr[0]
.sym 7199 r_counter_$glb_clk
.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7201 $PACKER_VCC_NET
.sym 7205 rx_fifo.mem_i.0.1_WDATA
.sym 7209 rx_fifo.mem_i.0.1_WDATA_1
.sym 7210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 7215 rx_fifo.wr_addr[4]
.sym 7216 w_rx_fifo_pulled_data[23]
.sym 7220 rx_fifo.wr_addr[0]
.sym 7222 rx_fifo.mem_i.0.3_WDATA_1
.sym 7227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 7228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 7229 rx_fifo.rd_addr[9]
.sym 7231 rx_fifo.rd_addr_gray[3]
.sym 7233 w_rx_fifo_pulled_data[1]
.sym 7236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 7246 rx_fifo.wr_addr[2]
.sym 7249 rx_fifo.wr_addr[0]
.sym 7251 rx_fifo.wr_addr[8]
.sym 7253 rx_fifo.wr_addr[4]
.sym 7255 rx_fifo.wr_addr[6]
.sym 7257 rx_fifo.mem_q.0.0_WDATA_2
.sym 7258 rx_fifo.mem_q.0.0_WDATA_3
.sym 7259 rx_fifo.wr_addr[3]
.sym 7262 $PACKER_VCC_NET
.sym 7263 rx_fifo.wr_addr[9]
.sym 7266 rx_fifo.wr_addr[5]
.sym 7268 rx_fifo.wr_addr[7]
.sym 7271 rx_fifo.wr_addr[1]
.sym 7274 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 7275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
.sym 7276 rx_fifo.empty_o_SB_LUT4_I0_O[3]
.sym 7277 rx_fifo.empty_o_SB_LUT4_I0_O[2]
.sym 7278 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
.sym 7279 rx_fifo.rd_addr_gray_wr[6]
.sym 7280 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
.sym 7281 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
.sym 7290 rx_fifo.wr_addr[2]
.sym 7291 rx_fifo.wr_addr[3]
.sym 7293 rx_fifo.wr_addr[4]
.sym 7294 rx_fifo.wr_addr[5]
.sym 7295 rx_fifo.wr_addr[6]
.sym 7296 rx_fifo.wr_addr[7]
.sym 7297 rx_fifo.wr_addr[8]
.sym 7298 rx_fifo.wr_addr[9]
.sym 7299 rx_fifo.wr_addr[1]
.sym 7300 rx_fifo.wr_addr[0]
.sym 7301 lvds_clock_$glb_clk
.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 7304 rx_fifo.mem_q.0.0_WDATA_3
.sym 7308 rx_fifo.mem_q.0.0_WDATA_2
.sym 7311 $PACKER_VCC_NET
.sym 7316 rx_fifo.wr_addr_gray[3]
.sym 7320 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 7323 rx_fifo.rd_addr[8]
.sym 7327 i_rst_b$SB_IO_IN
.sym 7330 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 7331 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7334 rx_fifo.rd_addr[9]
.sym 7335 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 7336 rx_fifo.rd_addr_gray_wr_r[9]
.sym 7338 rx_fifo.rd_addr[3]
.sym 7344 rx_fifo.rd_addr[8]
.sym 7346 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7348 rx_fifo.mem_q.0.0_WDATA
.sym 7349 rx_fifo.rd_addr[9]
.sym 7353 rx_fifo.rd_addr[6]
.sym 7355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 7357 rx_fifo.mem_q.0.0_WDATA_1
.sym 7358 rx_fifo.rd_addr[0]
.sym 7359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 7362 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7363 rx_fifo.rd_addr[3]
.sym 7364 $PACKER_VCC_NET
.sym 7365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 7374 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7376 rx_fifo.rd_addr_gray_wr[8]
.sym 7377 rx_fifo.rd_addr_gray_wr_r[8]
.sym 7378 rx_fifo.rd_addr_gray_wr_r[9]
.sym 7379 rx_fifo.rd_addr_gray_wr[2]
.sym 7380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 7381 rx_fifo.rd_addr_gray_wr[9]
.sym 7382 rx_fifo.rd_addr_gray_wr_r[5]
.sym 7383 rx_fifo.rd_addr_gray_wr[5]
.sym 7392 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 7393 rx_fifo.rd_addr[3]
.sym 7395 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 7396 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 7397 rx_fifo.rd_addr[6]
.sym 7398 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 7399 rx_fifo.rd_addr[8]
.sym 7400 rx_fifo.rd_addr[9]
.sym 7401 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 7402 rx_fifo.rd_addr[0]
.sym 7403 r_counter_$glb_clk
.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7405 $PACKER_VCC_NET
.sym 7409 rx_fifo.mem_q.0.0_WDATA
.sym 7413 rx_fifo.mem_q.0.0_WDATA_1
.sym 7415 w_ioc[1]
.sym 7422 i_rst_b$SB_IO_IN
.sym 7430 $PACKER_VCC_NET
.sym 7431 w_lvds_rx_24_d0
.sym 7433 w_lvds_rx_24_d1
.sym 7437 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 7441 $PACKER_VCC_NET
.sym 7479 w_rx_24_fifo_data[1]
.sym 7480 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 7481 w_rx_24_fifo_data[0]
.sym 7528 i_rst_b$SB_IO_IN
.sym 7531 rx_fifo.rd_addr_gray_wr_r[9]
.sym 7532 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 7535 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 7541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 7542 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 7543 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7580 rx_fifo.wr_addr_gray[5]
.sym 7581 rx_fifo.wr_addr_gray[4]
.sym 7582 rx_fifo.wr_addr_gray[6]
.sym 7583 rx_fifo.wr_addr_gray[2]
.sym 7584 rx_fifo.wr_addr_gray[1]
.sym 7585 rx_fifo.wr_addr_gray[8]
.sym 7587 rx_fifo.wr_addr_gray[0]
.sym 7624 rx_fifo.rd_addr_gray_wr_r[0]
.sym 7625 w_rx_24_fifo_data[0]
.sym 7626 rx_fifo.rd_addr_gray_wr_r[1]
.sym 7627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 7629 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7633 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 7636 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 7639 rx_fifo.rd_addr_gray[3]
.sym 7641 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 7682 rx_fifo.wr_addr_gray_rd[7]
.sym 7683 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 7684 rx_fifo.wr_addr_gray_rd[4]
.sym 7686 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 7688 rx_fifo.wr_addr_gray_rd[6]
.sym 7689 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 7724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 7730 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 7732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 7787 rx_fifo.rd_addr_gray_wr[3]
.sym 7789 rx_fifo.rd_addr_gray_wr_r[3]
.sym 7830 rx_fifo.wr_addr_gray[7]
.sym 8043 o_shdn_rx_lna$SB_IO_OUT
.sym 8093 w_smi_data_output[6]
.sym 8095 w_smi_data_direction
.sym 8099 $PACKER_VCC_NET
.sym 8110 w_smi_data_direction
.sym 8112 $PACKER_VCC_NET
.sym 8117 w_smi_data_output[6]
.sym 8118 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 8119 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 8120 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 8121 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
.sym 8122 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 8123 tx_fifo.rd_addr[0]
.sym 8124 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 8125 tx_fifo.rd_addr[2]
.sym 8150 w_smi_data_direction
.sym 8153 w_smi_data_output[1]
.sym 8247 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 8248 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8249 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8250 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8251 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8252 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 8253 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 8260 $PACKER_VCC_NET
.sym 8263 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8265 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 8272 $PACKER_VCC_NET
.sym 8276 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 8290 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8296 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 8298 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 8302 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 8309 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 8312 tx_fifo.rd_addr[9]
.sym 8325 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 8326 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
.sym 8329 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 8332 w_rx_fifo_pulled_data[13]
.sym 8336 w_rx_fifo_pulled_data[15]
.sym 8340 w_rx_fifo_pulled_data[12]
.sym 8342 w_rx_fifo_pulled_data[11]
.sym 8344 w_rx_fifo_pulled_data[14]
.sym 8348 w_rx_fifo_pulled_data[8]
.sym 8350 w_rx_fifo_pulled_data[9]
.sym 8353 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 8359 w_rx_fifo_pulled_data[14]
.sym 8362 w_rx_fifo_pulled_data[12]
.sym 8368 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 8369 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
.sym 8370 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 8371 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 8375 w_rx_fifo_pulled_data[13]
.sym 8380 w_rx_fifo_pulled_data[9]
.sym 8387 w_rx_fifo_pulled_data[8]
.sym 8393 w_rx_fifo_pulled_data[11]
.sym 8401 w_rx_fifo_pulled_data[15]
.sym 8402 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 8403 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 8407 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 8408 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
.sym 8409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 8410 tx_fifo.rd_addr_gray_wr[2]
.sym 8411 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 8412 tx_fifo.rd_addr_gray_wr[4]
.sym 8415 rx_fifo.rd_addr[9]
.sym 8432 tx_fifo.rd_addr_gray_wr_r[1]
.sym 8438 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 8439 tx_fifo.rd_addr[1]
.sym 8448 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
.sym 8452 w_tx_fifo_pull
.sym 8453 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 8455 i_rst_b$SB_IO_IN
.sym 8457 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8462 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 8464 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 8468 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
.sym 8472 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 8479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 8486 i_rst_b$SB_IO_IN
.sym 8488 w_tx_fifo_pull
.sym 8491 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
.sym 8493 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
.sym 8506 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 8510 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 8518 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 8525 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8526 lvds_clock_$glb_clk
.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8528 tx_fifo.rd_addr_gray[8]
.sym 8529 tx_fifo.rd_addr_gray[0]
.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 8531 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 8533 tx_fifo.rd_addr[9]
.sym 8534 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
.sym 8535 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 8540 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 8544 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8545 tx_fifo.rd_addr_gray_wr[4]
.sym 8557 smi_ctrl_ins.int_cnt_rx[4]
.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 8563 smi_ctrl_ins.int_cnt_rx[3]
.sym 8569 tx_fifo.rd_addr_gray[1]
.sym 8573 tx_fifo.rd_addr_gray_wr[8]
.sym 8586 tx_fifo.rd_addr_gray[0]
.sym 8587 tx_fifo.rd_addr_gray_wr[9]
.sym 8591 tx_fifo.rd_addr_gray_wr[1]
.sym 8593 tx_fifo.rd_addr_gray[8]
.sym 8596 tx_fifo.rd_addr_gray_wr[0]
.sym 8598 tx_fifo.rd_addr[9]
.sym 8604 tx_fifo.rd_addr_gray_wr[8]
.sym 8609 tx_fifo.rd_addr_gray_wr[0]
.sym 8616 tx_fifo.rd_addr[9]
.sym 8620 tx_fifo.rd_addr_gray[0]
.sym 8627 tx_fifo.rd_addr_gray[8]
.sym 8635 tx_fifo.rd_addr_gray_wr[9]
.sym 8640 tx_fifo.rd_addr_gray[1]
.sym 8647 tx_fifo.rd_addr_gray_wr[1]
.sym 8649 r_counter_$glb_clk
.sym 8651 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 8652 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 8653 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 8654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 8655 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 8656 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 8657 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 8658 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 8663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 8665 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 8667 tx_fifo.rd_addr_gray_wr_r[0]
.sym 8668 rx_fifo.rd_addr[9]
.sym 8669 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 8671 w_smi_data_output[1]
.sym 8672 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 8677 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 8682 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8686 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 8693 w_rx_24_fifo_data[24]
.sym 8696 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 8697 w_rx_fifo_pulled_data[26]
.sym 8698 w_rx_09_fifo_data[24]
.sym 8701 w_rx_fifo_pulled_data[24]
.sym 8703 w_rx_fifo_pulled_data[10]
.sym 8705 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 8709 w_rx_fifo_pulled_data[25]
.sym 8710 smi_ctrl_ins.int_cnt_rx[4]
.sym 8713 smi_ctrl_ins.int_cnt_rx[3]
.sym 8715 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 8716 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 8721 w_rx_fifo_pulled_data[27]
.sym 8723 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 8725 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 8726 smi_ctrl_ins.int_cnt_rx[3]
.sym 8727 smi_ctrl_ins.int_cnt_rx[4]
.sym 8728 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 8732 w_rx_fifo_pulled_data[27]
.sym 8740 w_rx_fifo_pulled_data[25]
.sym 8743 w_rx_24_fifo_data[24]
.sym 8744 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 8746 w_rx_09_fifo_data[24]
.sym 8749 w_rx_fifo_pulled_data[10]
.sym 8758 w_rx_fifo_pulled_data[24]
.sym 8764 w_rx_fifo_pulled_data[26]
.sym 8767 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 8768 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 8769 smi_ctrl_ins.int_cnt_rx[3]
.sym 8770 smi_ctrl_ins.int_cnt_rx[4]
.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8776 smi_ctrl_ins.int_cnt_rx[4]
.sym 8779 smi_ctrl_ins.int_cnt_rx[3]
.sym 8786 io_pmod[0]$SB_IO_IN
.sym 8787 $PACKER_VCC_NET
.sym 8790 w_rx_fifo_pulled_data[6]
.sym 8792 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 8798 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 8801 rx_fifo.rd_addr[0]
.sym 8802 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 8803 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 8806 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 8807 rx_fifo.rd_addr[6]
.sym 8808 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 8809 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 8828 w_rx_24_fifo_data[26]
.sym 8832 w_rx_24_fifo_data[24]
.sym 8837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 8842 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 8843 w_rx_24_fifo_data[22]
.sym 8854 w_rx_24_fifo_data[22]
.sym 8855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 8878 w_rx_24_fifo_data[24]
.sym 8879 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 8884 w_rx_24_fifo_data[26]
.sym 8886 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 8894 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 8895 lvds_clock_$glb_clk
.sym 8896 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 8898 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 8899 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 8911 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 8913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 8920 smi_ctrl_ins.int_cnt_rx[4]
.sym 8943 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 8944 w_rx_24_fifo_data[28]
.sym 8946 w_rx_09_fifo_data[28]
.sym 8949 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 8955 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 8956 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 8959 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 8961 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 8965 rx_fifo.rd_addr[3]
.sym 8968 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 8969 rx_fifo.rd_addr[0]
.sym 8972 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 8977 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 8978 w_rx_24_fifo_data[28]
.sym 8979 w_rx_09_fifo_data[28]
.sym 8984 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 8989 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 8996 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 9002 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 9009 rx_fifo.rd_addr[3]
.sym 9014 rx_fifo.rd_addr[0]
.sym 9017 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9018 r_counter_$glb_clk
.sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 9022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9023 rx_fifo.rd_addr[3]
.sym 9024 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 9026 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 9032 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 9034 rx_fifo.rd_addr_gray[3]
.sym 9036 rx_fifo.mem_i.0.3_WDATA_3
.sym 9045 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9047 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9048 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 9049 rx_fifo.rd_addr[8]
.sym 9052 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 9054 w_rx_24_fifo_data[1]
.sym 9065 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 9068 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 9070 w_rx_fifo_pulled_data[21]
.sym 9074 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 9075 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 9080 w_rx_fifo_pulled_data[3]
.sym 9082 w_rx_fifo_pulled_data[2]
.sym 9086 w_rx_fifo_pulled_data[0]
.sym 9088 w_rx_fifo_pulled_data[1]
.sym 9095 w_rx_fifo_pulled_data[3]
.sym 9100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 9102 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 9108 w_rx_fifo_pulled_data[1]
.sym 9120 w_rx_fifo_pulled_data[0]
.sym 9126 w_rx_fifo_pulled_data[2]
.sym 9130 w_rx_fifo_pulled_data[21]
.sym 9137 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 9139 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9143 rx_fifo.wr_addr_gray_rd[3]
.sym 9144 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 9147 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 9149 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
.sym 9150 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 9156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9158 rx_fifo.rd_addr[3]
.sym 9163 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 9165 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 9166 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9167 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9169 rx_fifo.rd_addr[9]
.sym 9171 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 9175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9176 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 9178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9185 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 9186 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9187 rx_fifo.rd_addr[3]
.sym 9189 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 9190 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9192 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 9194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 9202 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 9206 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 9207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 9213 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 9215 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
.sym 9218 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9225 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 9229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 9235 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
.sym 9237 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9238 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 9242 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9243 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 9248 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 9253 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 9254 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 9255 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 9256 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 9259 rx_fifo.rd_addr[3]
.sym 9260 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 9262 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9264 r_counter_$glb_clk
.sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9266 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9268 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 9271 rx_fifo.empty_o_SB_LUT4_I0_O[1]
.sym 9272 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 9273 rx_fifo.empty_o_SB_LUT4_I0_O[0]
.sym 9280 $PACKER_VCC_NET
.sym 9283 $PACKER_VCC_NET
.sym 9287 $PACKER_VCC_NET
.sym 9291 rx_fifo.rd_addr_gray[8]
.sym 9292 w_rx_24_fifo_data[1]
.sym 9293 w_rx_data[0]
.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 9297 rx_fifo.rd_addr_gray_wr_r[8]
.sym 9299 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9307 rx_fifo.rd_addr[8]
.sym 9308 rx_fifo.rd_addr[6]
.sym 9311 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
.sym 9312 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 9313 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 9314 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
.sym 9315 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 9316 rx_fifo.rd_addr_gray[6]
.sym 9317 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9318 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
.sym 9319 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 9320 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 9322 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 9323 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 9325 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 9327 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9329 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 9332 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
.sym 9335 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9337 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 9342 rx_fifo.rd_addr[8]
.sym 9346 rx_fifo.rd_addr[6]
.sym 9347 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 9348 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 9349 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 9352 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
.sym 9354 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
.sym 9355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
.sym 9358 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 9359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
.sym 9360 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 9361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 9364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 9365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 9366 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 9367 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
.sym 9373 rx_fifo.rd_addr_gray[6]
.sym 9377 rx_fifo.rd_addr[6]
.sym 9378 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 9382 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 9383 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 9384 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9385 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 9387 lvds_clock_$glb_clk
.sym 9389 rx_fifo.rd_addr_gray[4]
.sym 9393 rx_fifo.rd_addr_gray[1]
.sym 9394 rx_fifo.rd_addr_gray[7]
.sym 9395 rx_fifo.rd_addr_gray[5]
.sym 9396 rx_fifo.rd_addr_gray[2]
.sym 9405 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 9407 w_load
.sym 9408 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9410 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 9411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 9417 rx_fifo.rd_addr_gray_wr_r[7]
.sym 9418 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 9420 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 9421 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 9422 rx_fifo.wr_addr_gray_rd[2]
.sym 9423 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9424 rx_fifo.wr_addr_gray_rd[5]
.sym 9441 rx_fifo.rd_addr[9]
.sym 9443 rx_fifo.rd_addr_gray_wr[9]
.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9451 rx_fifo.rd_addr_gray[8]
.sym 9453 rx_fifo.rd_addr_gray_wr[5]
.sym 9454 rx_fifo.rd_addr_gray_wr[8]
.sym 9459 rx_fifo.rd_addr_gray_wr_r[2]
.sym 9460 rx_fifo.rd_addr_gray[5]
.sym 9461 rx_fifo.rd_addr_gray[2]
.sym 9466 rx_fifo.rd_addr_gray[8]
.sym 9469 rx_fifo.rd_addr_gray_wr[8]
.sym 9477 rx_fifo.rd_addr_gray_wr[9]
.sym 9484 rx_fifo.rd_addr_gray[2]
.sym 9487 rx_fifo.rd_addr_gray_wr_r[2]
.sym 9488 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 9490 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9494 rx_fifo.rd_addr[9]
.sym 9500 rx_fifo.rd_addr_gray_wr[5]
.sym 9505 rx_fifo.rd_addr_gray[5]
.sym 9510 lvds_clock_$glb_clk
.sym 9512 rx_fifo.rd_addr_gray_wr_r[7]
.sym 9513 rx_fifo.rd_addr_gray_wr_r[0]
.sym 9515 rx_fifo.rd_addr_gray_wr[0]
.sym 9516 rx_fifo.rd_addr_gray_wr[1]
.sym 9517 rx_fifo.rd_addr_gray_wr_r[1]
.sym 9519 rx_fifo.rd_addr_gray_wr[7]
.sym 9525 $PACKER_GND_NET
.sym 9530 $PACKER_GND_NET
.sym 9538 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9540 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 9541 rx_fifo.rd_addr_gray[0]
.sym 9543 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 9544 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 9546 w_rx_24_fifo_data[1]
.sym 9547 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9558 w_lvds_rx_24_d0
.sym 9561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9562 rx_fifo.rd_addr_gray_wr_r[8]
.sym 9564 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 9565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 9567 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 9568 w_lvds_rx_24_d1
.sym 9572 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 9592 w_lvds_rx_24_d0
.sym 9598 rx_fifo.rd_addr_gray_wr_r[8]
.sym 9599 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 9606 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 9607 w_lvds_rx_24_d1
.sym 9632 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 9633 lvds_clock_$glb_clk
.sym 9635 rx_fifo.wr_addr_gray_rd[8]
.sym 9636 rx_fifo.wr_addr_gray_rd[0]
.sym 9637 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 9638 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 9639 rx_fifo.wr_addr_gray_rd[2]
.sym 9640 rx_fifo.wr_addr_gray_rd[5]
.sym 9642 rx_fifo.wr_addr_gray_rd[1]
.sym 9669 rx_fifo.rd_addr_gray_wr_r[3]
.sym 9679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9681 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9683 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9685 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 9688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9689 rx_fifo.wr_addr[1]
.sym 9693 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 9695 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9703 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 9707 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9712 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9715 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9722 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9727 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 9729 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 9740 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9741 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9752 rx_fifo.wr_addr[1]
.sym 9755 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 9756 lvds_clock_$glb_clk
.sym 9757 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9760 rx_fifo.rd_addr_gray[0]
.sym 9801 rx_fifo.wr_addr_gray[6]
.sym 9805 rx_fifo.wr_addr_gray_rd[6]
.sym 9807 rx_fifo.wr_addr_gray_rd[7]
.sym 9808 rx_fifo.wr_addr_gray[4]
.sym 9809 rx_fifo.wr_addr_gray_rd[4]
.sym 9814 rx_fifo.wr_addr_gray[7]
.sym 9834 rx_fifo.wr_addr_gray[7]
.sym 9839 rx_fifo.wr_addr_gray_rd[6]
.sym 9846 rx_fifo.wr_addr_gray[4]
.sym 9859 rx_fifo.wr_addr_gray_rd[4]
.sym 9870 rx_fifo.wr_addr_gray[6]
.sym 9876 rx_fifo.wr_addr_gray_rd[7]
.sym 9879 r_counter_$glb_clk
.sym 9926 rx_fifo.rd_addr_gray[3]
.sym 9949 rx_fifo.rd_addr_gray_wr[3]
.sym 9976 rx_fifo.rd_addr_gray[3]
.sym 9988 rx_fifo.rd_addr_gray_wr[3]
.sym 10002 lvds_clock_$glb_clk
.sym 10004 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 10018 o_shdn_rx_lna$SB_IO_OUT
.sym 10172 o_shdn_rx_lna$SB_IO_OUT
.sym 10185 o_shdn_rx_lna$SB_IO_OUT
.sym 10201 w_smi_data_output[2]
.sym 10203 w_smi_data_direction
.sym 10204 w_smi_data_output[1]
.sym 10206 w_smi_data_direction
.sym 10207 $PACKER_VCC_NET
.sym 10212 $PACKER_VCC_NET
.sym 10214 w_smi_data_direction
.sym 10217 w_smi_data_output[1]
.sym 10222 w_smi_data_direction
.sym 10225 w_smi_data_output[2]
.sym 10226 tx_fifo.rd_addr[1]
.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 10231 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 10233 w_smi_data_output[2]
.sym 10270 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10271 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10272 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10277 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 10278 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 10283 tx_fifo.rd_addr[2]
.sym 10295 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10297 tx_fifo.rd_addr[0]
.sym 10301 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10304 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10308 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 10310 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10313 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 10320 tx_fifo.rd_addr[2]
.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10334 tx_fifo.rd_addr[0]
.sym 10338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10346 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10348 lvds_clock_$glb_clk
.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10352 w_smi_data_input[7]
.sym 10354 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
.sym 10355 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
.sym 10356 tx_fifo.empty_o_SB_LUT4_I1_O[3]
.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 10358 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 10359 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 10360 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
.sym 10361 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 10368 $PACKER_VCC_NET
.sym 10370 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 10372 $PACKER_VCC_NET
.sym 10373 tx_fifo.rd_addr[1]
.sym 10379 w_smi_data_output[0]
.sym 10392 $PACKER_VCC_NET
.sym 10396 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 10405 tx_fifo.empty_o_SB_LUT4_I1_O[3]
.sym 10409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 10411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 10412 w_smi_data_input[7]
.sym 10414 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 10423 w_smi_data_output[7]
.sym 10436 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 10439 tx_fifo.rd_addr[1]
.sym 10440 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 10441 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 10444 tx_fifo.rd_addr[0]
.sym 10445 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 10446 tx_fifo.rd_addr[2]
.sym 10453 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 10463 $nextpnr_ICESTORM_LC_5$O
.sym 10466 tx_fifo.rd_addr[0]
.sym 10469 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10472 tx_fifo.rd_addr[1]
.sym 10473 tx_fifo.rd_addr[0]
.sym 10475 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10478 tx_fifo.rd_addr[2]
.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10481 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10484 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 10485 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10487 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 10489 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 10491 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 10493 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
.sym 10496 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 10497 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 10499 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 10502 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 10503 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
.sym 10505 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 10507 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 10513 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 10514 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
.sym 10515 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 10516 tx_fifo.empty_o_SB_LUT4_I1_O[2]
.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 10518 w_tx_fifo_empty
.sym 10519 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 10537 w_smi_data_output[0]
.sym 10538 tx_fifo.rd_addr[1]
.sym 10540 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 10543 w_smi_data_output[7]
.sym 10546 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 10548 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 10549 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 10554 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
.sym 10557 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 10558 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10560 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
.sym 10561 tx_fifo.rd_addr[9]
.sym 10564 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
.sym 10565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 10566 tx_fifo.rd_addr_gray[4]
.sym 10567 tx_fifo.rd_addr_gray[2]
.sym 10568 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 10569 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 10571 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
.sym 10577 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 10581 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
.sym 10584 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10586 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 10589 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 10590 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 10593 tx_fifo.rd_addr[9]
.sym 10596 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 10600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 10601 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10605 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 10606 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 10607 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 10608 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
.sym 10611 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 10612 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10614 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 10618 tx_fifo.rd_addr_gray[2]
.sym 10623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
.sym 10624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
.sym 10625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
.sym 10626 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
.sym 10629 tx_fifo.rd_addr_gray[4]
.sym 10634 r_counter_$glb_clk
.sym 10636 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 10637 w_smi_data_output[7]
.sym 10638 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 10639 w_smi_data_output[3]
.sym 10640 w_smi_data_output[2]
.sym 10641 w_smi_data_output[6]
.sym 10642 w_smi_data_output[0]
.sym 10643 w_smi_data_output[1]
.sym 10650 tx_fifo.rd_addr_gray_wr[2]
.sym 10656 rx_fifo.mem_i.0.0_WDATA_2
.sym 10661 w_rx_fifo_pulled_data[18]
.sym 10664 smi_ctrl_ins.int_cnt_rx[4]
.sym 10666 w_rx_fifo_pulled_data[19]
.sym 10667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 10669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 10670 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10677 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 10678 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 10679 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 10680 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 10685 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10686 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 10687 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 10690 tx_fifo.rd_addr[9]
.sym 10691 tx_fifo.rd_addr[1]
.sym 10695 smi_ctrl_ins.int_cnt_rx[3]
.sym 10696 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10703 smi_ctrl_ins.int_cnt_rx[3]
.sym 10704 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10705 smi_ctrl_ins.int_cnt_rx[4]
.sym 10708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 10713 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 10716 tx_fifo.rd_addr[1]
.sym 10722 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 10723 smi_ctrl_ins.int_cnt_rx[3]
.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 10725 smi_ctrl_ins.int_cnt_rx[4]
.sym 10729 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 10730 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 10735 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 10736 smi_ctrl_ins.int_cnt_rx[3]
.sym 10737 smi_ctrl_ins.int_cnt_rx[4]
.sym 10743 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 10746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 10747 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10748 tx_fifo.rd_addr[9]
.sym 10749 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10754 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10756 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10757 lvds_clock_$glb_clk
.sym 10758 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10759 tx_fifo.wr_addr_gray_rd[7]
.sym 10760 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 10761 tx_fifo.wr_addr_gray_rd[8]
.sym 10762 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 10764 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 10765 tx_fifo.wr_addr_gray_rd[1]
.sym 10766 tx_fifo.wr_addr_gray_rd[5]
.sym 10772 rx_fifo.rd_addr[6]
.sym 10775 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 10776 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10780 rx_fifo.rd_addr[0]
.sym 10782 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 10783 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 10793 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 10801 w_rx_fifo_pulled_data[4]
.sym 10802 smi_ctrl_ins.int_cnt_rx[4]
.sym 10805 smi_ctrl_ins.int_cnt_rx[3]
.sym 10806 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 10807 w_rx_fifo_pulled_data[6]
.sym 10808 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 10809 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 10810 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 10813 smi_ctrl_ins.int_cnt_rx[3]
.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 10821 w_rx_fifo_pulled_data[18]
.sym 10826 w_rx_fifo_pulled_data[19]
.sym 10828 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 10830 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 10836 w_rx_fifo_pulled_data[6]
.sym 10839 smi_ctrl_ins.int_cnt_rx[3]
.sym 10840 smi_ctrl_ins.int_cnt_rx[4]
.sym 10841 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 10842 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 10848 w_rx_fifo_pulled_data[19]
.sym 10851 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 10852 smi_ctrl_ins.int_cnt_rx[4]
.sym 10853 smi_ctrl_ins.int_cnt_rx[3]
.sym 10854 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 10857 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 10858 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 10859 smi_ctrl_ins.int_cnt_rx[4]
.sym 10860 smi_ctrl_ins.int_cnt_rx[3]
.sym 10865 w_rx_fifo_pulled_data[18]
.sym 10870 w_rx_fifo_pulled_data[4]
.sym 10875 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 10876 smi_ctrl_ins.int_cnt_rx[4]
.sym 10877 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 10878 smi_ctrl_ins.int_cnt_rx[3]
.sym 10879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 10880 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10883 tx_fifo.wr_addr_gray_rd[0]
.sym 10885 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 10886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 10888 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 10889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 10891 w_rx_fifo_pulled_data[4]
.sym 10898 $PACKER_VCC_NET
.sym 10899 o_smi_read_req$SB_IO_OUT
.sym 10904 tx_fifo.rd_addr_gray_wr_r[1]
.sym 10908 smi_ctrl_ins.int_cnt_rx[3]
.sym 10910 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 10912 rx_fifo.rd_addr[3]
.sym 10916 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 10941 smi_ctrl_ins.int_cnt_rx[4]
.sym 10952 smi_ctrl_ins.int_cnt_rx[3]
.sym 10968 smi_ctrl_ins.int_cnt_rx[3]
.sym 10970 smi_ctrl_ins.int_cnt_rx[4]
.sym 10989 smi_ctrl_ins.int_cnt_rx[3]
.sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 11004 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11010 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 11011 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 11019 smi_ctrl_ins.int_cnt_rx[3]
.sym 11023 smi_ctrl_ins.int_cnt_rx[4]
.sym 11024 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 11028 rx_fifo.rd_addr[8]
.sym 11030 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 11038 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 11048 rx_fifo.rd_addr[6]
.sym 11049 rx_fifo.rd_addr[3]
.sym 11054 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 11056 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 11057 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11058 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 11060 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 11061 rx_fifo.rd_addr[0]
.sym 11078 $nextpnr_ICESTORM_LC_8$O
.sym 11081 rx_fifo.rd_addr[0]
.sym 11084 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 11086 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11088 rx_fifo.rd_addr[0]
.sym 11090 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 11092 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 11094 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 11096 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 11099 rx_fifo.rd_addr[3]
.sym 11100 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 11104 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 11106 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 11111 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 11117 rx_fifo.rd_addr[6]
.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11123 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 11128 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11132 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 11144 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 11146 rx_fifo.wr_addr[6]
.sym 11147 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11154 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 11157 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 11163 rx_fifo.wr_addr_gray_rd[1]
.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11170 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 11172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11179 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11181 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 11190 rx_fifo.rd_addr[9]
.sym 11193 rx_fifo.rd_addr[8]
.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11203 rx_fifo.rd_addr[8]
.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11208 rx_fifo.rd_addr[9]
.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 11222 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 11227 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 11228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 11239 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 11244 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 11246 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11249 r_counter_$glb_clk
.sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11251 w_rx_fifo_empty
.sym 11256 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 11258 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
.sym 11265 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 11266 rx_fifo.wr_addr_SB_DFFESR_Q_E
.sym 11267 rx_fifo.rd_addr[6]
.sym 11269 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11270 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 11271 rx_fifo.rd_addr[3]
.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11273 w_rx_data[0]
.sym 11278 rx_fifo.rd_addr[3]
.sym 11280 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 11292 rx_fifo.wr_addr_gray_rd[2]
.sym 11293 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 11295 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11296 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 11298 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11304 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 11306 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 11308 rx_fifo.wr_addr_gray[3]
.sym 11312 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11315 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11316 rx_fifo.wr_addr_gray_rd[3]
.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 11318 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 11319 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11322 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
.sym 11325 rx_fifo.wr_addr_gray[3]
.sym 11331 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 11332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 11333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 11340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11343 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 11344 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 11349 rx_fifo.wr_addr_gray_rd[2]
.sym 11357 rx_fifo.wr_addr_gray_rd[3]
.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11372 r_counter_$glb_clk
.sym 11374 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 11375 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 11376 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 11377 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 11378 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
.sym 11379 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 11380 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 11392 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 11396 rx_fifo.wr_addr_gray_rd[2]
.sym 11407 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 11415 w_rx_fifo_empty
.sym 11417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11418 rx_fifo.wr_addr_gray_rd[9]
.sym 11420 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 11422 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
.sym 11425 rx_fifo.empty_o_SB_LUT4_I0_O[3]
.sym 11426 rx_fifo.empty_o_SB_LUT4_I0_O[2]
.sym 11427 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 11428 rx_fifo.empty_o_SB_LUT4_I0_O[1]
.sym 11431 rx_fifo.rd_addr[8]
.sym 11432 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 11433 rx_fifo.wr_addr_gray_rd[1]
.sym 11434 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11438 rx_fifo.empty_o_SB_LUT4_I0_O[0]
.sym 11441 i_rst_b$SB_IO_IN
.sym 11442 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 11444 rx_fifo.rd_addr[9]
.sym 11446 rx_fifo.wr_addr_gray_rd[5]
.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 11451 i_rst_b$SB_IO_IN
.sym 11455 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11457 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 11460 rx_fifo.wr_addr_gray_rd[5]
.sym 11468 rx_fifo.wr_addr_gray_rd[9]
.sym 11472 rx_fifo.empty_o_SB_LUT4_I0_O[2]
.sym 11473 rx_fifo.empty_o_SB_LUT4_I0_O[3]
.sym 11474 rx_fifo.empty_o_SB_LUT4_I0_O[1]
.sym 11475 rx_fifo.empty_o_SB_LUT4_I0_O[0]
.sym 11478 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
.sym 11479 w_rx_fifo_empty
.sym 11480 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 11481 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 11484 rx_fifo.wr_addr_gray_rd[1]
.sym 11490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 11491 rx_fifo.rd_addr[9]
.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11493 rx_fifo.rd_addr[8]
.sym 11495 r_counter_$glb_clk
.sym 11497 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 11498 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
.sym 11499 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 11500 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11501 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
.sym 11502 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11503 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
.sym 11504 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 11509 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11510 w_cs[0]
.sym 11514 rx_fifo.wr_addr_gray_rd[9]
.sym 11516 w_rx_data[1]
.sym 11517 w_rx_data[4]
.sym 11522 w_rx_fifo_empty
.sym 11530 w_rx_data[3]
.sym 11540 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11541 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11550 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11574 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11598 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11604 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 11610 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 11614 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11618 r_counter_$glb_clk
.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11620 w_tx_data_smi[1]
.sym 11622 w_tx_data_smi[2]
.sym 11624 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 11625 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
.sym 11635 w_ioc[1]
.sym 11636 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 11642 w_cs[0]
.sym 11643 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 11645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 11646 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 11647 rx_fifo.wr_addr_gray_rd[1]
.sym 11653 w_ioc[0]
.sym 11672 rx_fifo.rd_addr_gray_wr[0]
.sym 11673 rx_fifo.rd_addr_gray[1]
.sym 11674 rx_fifo.rd_addr_gray[7]
.sym 11681 rx_fifo.rd_addr_gray_wr[1]
.sym 11684 rx_fifo.rd_addr_gray_wr[7]
.sym 11689 rx_fifo.rd_addr_gray[0]
.sym 11695 rx_fifo.rd_addr_gray_wr[7]
.sym 11703 rx_fifo.rd_addr_gray_wr[0]
.sym 11714 rx_fifo.rd_addr_gray[0]
.sym 11721 rx_fifo.rd_addr_gray[1]
.sym 11725 rx_fifo.rd_addr_gray_wr[1]
.sym 11739 rx_fifo.rd_addr_gray[7]
.sym 11741 lvds_clock_$glb_clk
.sym 11746 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 11747 o_led0_SB_LUT4_I1_O[1]
.sym 11748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
.sym 11750 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 11751 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 11773 o_shdn_rx_lna$SB_IO_OUT
.sym 11784 rx_fifo.wr_addr_gray_rd[8]
.sym 11792 rx_fifo.wr_addr_gray[5]
.sym 11795 rx_fifo.wr_addr_gray[2]
.sym 11796 rx_fifo.wr_addr_gray[1]
.sym 11797 rx_fifo.wr_addr_gray[8]
.sym 11799 rx_fifo.wr_addr_gray[0]
.sym 11801 rx_fifo.wr_addr_gray_rd[0]
.sym 11817 rx_fifo.wr_addr_gray[8]
.sym 11826 rx_fifo.wr_addr_gray[0]
.sym 11831 rx_fifo.wr_addr_gray_rd[8]
.sym 11835 rx_fifo.wr_addr_gray_rd[0]
.sym 11843 rx_fifo.wr_addr_gray[2]
.sym 11849 rx_fifo.wr_addr_gray[5]
.sym 11861 rx_fifo.wr_addr_gray[1]
.sym 11864 r_counter_$glb_clk
.sym 11866 io_ctrl_ins.o_pmod[0]
.sym 11868 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 11869 io_ctrl_ins.o_pmod[3]
.sym 11870 io_ctrl_ins.o_pmod[2]
.sym 11871 o_led1_SB_LUT4_I1_O[2]
.sym 11872 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
.sym 11873 io_ctrl_ins.o_pmod[1]
.sym 11881 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 11883 w_load
.sym 11885 w_fetch
.sym 11896 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
.sym 11912 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11918 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11955 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 11986 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 11987 r_counter_$glb_clk
.sym 11988 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11990 o_led0_SB_LUT4_I1_O[0]
.sym 11992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 11993 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 11995 o_led1_SB_LUT4_I1_O[0]
.sym 11996 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 12001 o_shdn_tx_lna$SB_IO_OUT
.sym 12006 w_rx_data[1]
.sym 12023 w_rx_data[3]
.sym 12125 w_rx_data[1]
.sym 12127 w_rx_data[3]
.sym 12133 w_rx_data[4]
.sym 12183 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 12187 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 12305 i_rst_b$SB_IO_IN
.sym 12307 o_shdn_tx_lna$SB_IO_OUT
.sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 12310 w_smi_data_output[0]
.sym 12312 w_smi_data_direction
.sym 12313 w_smi_data_output[7]
.sym 12315 w_smi_data_direction
.sym 12316 $PACKER_VCC_NET
.sym 12320 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 12321 w_smi_data_direction
.sym 12326 w_smi_data_output[7]
.sym 12328 w_smi_data_output[0]
.sym 12329 w_smi_data_direction
.sym 12332 $PACKER_VCC_NET
.sym 12335 tx_fifo.wr_addr_gray_rd[2]
.sym 12336 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 12337 w_smi_data_direction
.sym 12338 tx_fifo.wr_addr_gray_rd[3]
.sym 12339 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12340 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 12341 tx_fifo.wr_addr_gray_rd[6]
.sym 12342 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 12368 $PACKER_VCC_NET
.sym 12369 w_smi_data_input[7]
.sym 12385 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 12389 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 12394 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 12397 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12398 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 12404 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 12405 w_smi_data_output[2]
.sym 12406 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 12407 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 12411 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 12418 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 12434 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12435 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 12436 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 12437 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 12440 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 12447 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 12454 w_smi_data_output[2]
.sym 12456 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 12457 lvds_clock_$glb_clk
.sym 12458 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 12464 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 12465 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 12466 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12467 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 12468 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 12469 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12470 w_tx_fifo_pull
.sym 12475 tx_fifo.rd_addr[1]
.sym 12481 w_smi_data_input[7]
.sym 12492 w_smi_data_output[4]
.sym 12498 w_smi_data_output[6]
.sym 12507 w_tx_fifo_pull
.sym 12509 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 12512 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 12513 i_rst_b_SB_LUT4_I3_O
.sym 12516 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 12524 w_smi_data_output[3]
.sym 12525 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12526 w_smi_data_output[2]
.sym 12527 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 12540 tx_fifo.rd_addr[1]
.sym 12541 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
.sym 12544 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12545 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12546 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 12547 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 12549 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 12553 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 12554 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 12555 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 12557 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 12558 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 12563 tx_fifo.rd_addr[2]
.sym 12564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 12565 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 12566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 12567 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 12568 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 12570 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 12571 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 12573 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 12574 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
.sym 12575 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 12576 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 12579 tx_fifo.rd_addr[2]
.sym 12580 tx_fifo.rd_addr[1]
.sym 12581 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 12585 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12586 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 12587 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 12594 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 12598 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 12603 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 12604 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 12605 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 12609 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 12611 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 12612 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12615 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 12616 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 12617 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 12618 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 12623 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 12624 tx_fifo.wr_addr_gray_rd[9]
.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 12626 i_rst_b_SB_LUT4_I3_O
.sym 12627 tx_fifo.wr_addr_gray_rd[4]
.sym 12628 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12639 $PACKER_VCC_NET
.sym 12645 $PACKER_VCC_NET
.sym 12648 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 12649 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 12650 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 12652 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 12654 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 12666 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12667 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 12669 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 12670 w_tx_fifo_pull
.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12672 tx_fifo.empty_o_SB_LUT4_I1_O[3]
.sym 12673 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12675 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 12676 w_tx_fifo_empty
.sym 12677 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12678 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 12682 tx_fifo.empty_o_SB_LUT4_I1_O[2]
.sym 12685 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12686 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 12687 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12688 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 12689 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 12690 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 12692 tx_fifo.rd_addr[9]
.sym 12694 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 12696 tx_fifo.empty_o_SB_LUT4_I1_O[3]
.sym 12697 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 12698 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 12699 tx_fifo.empty_o_SB_LUT4_I1_O[2]
.sym 12702 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 12703 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12704 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12705 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 12709 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 12710 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12711 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 12714 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12715 tx_fifo.rd_addr[9]
.sym 12716 w_tx_fifo_pull
.sym 12717 w_tx_fifo_empty
.sym 12722 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12726 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12727 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12728 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 12729 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12732 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12733 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 12735 w_tx_fifo_pull
.sym 12738 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 12739 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 12741 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 12743 lvds_clock_$glb_clk
.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 12745 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 12747 tx_fifo.rd_addr_gray[3]
.sym 12748 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 12749 tx_fifo.rd_addr_gray[6]
.sym 12750 tx_fifo.rd_addr_gray[5]
.sym 12751 tx_fifo.rd_addr_gray[7]
.sym 12752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
.sym 12758 $PACKER_VCC_NET
.sym 12762 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12763 w_smi_data_output[5]
.sym 12764 rx_fifo.mem_i.0.0_WDATA_3
.sym 12769 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 12770 tx_fifo.wr_addr_gray_rd[1]
.sym 12771 w_smi_data_output[6]
.sym 12772 i_rst_b$SB_IO_IN
.sym 12773 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12774 w_smi_data_output[4]
.sym 12775 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 12777 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 12778 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 12779 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 12788 i_rst_b$SB_IO_IN
.sym 12793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12794 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 12795 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 12796 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 12797 smi_ctrl_ins.int_cnt_rx[3]
.sym 12798 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 12799 tx_fifo.rd_addr[1]
.sym 12801 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 12802 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 12805 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 12806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 12807 smi_ctrl_ins.int_cnt_rx[4]
.sym 12808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 12809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 12810 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 12811 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 12812 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 12813 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 12816 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 12817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 12819 smi_ctrl_ins.int_cnt_rx[3]
.sym 12820 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 12821 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 12822 smi_ctrl_ins.int_cnt_rx[4]
.sym 12826 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 12828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 12831 tx_fifo.rd_addr[1]
.sym 12832 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12833 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 12834 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 12837 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 12838 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 12843 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 12845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 12849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 12851 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 12856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 12858 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 12861 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 12862 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 12865 i_rst_b$SB_IO_IN
.sym 12866 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 12868 tx_fifo.wr_addr_gray[8]
.sym 12869 tx_fifo.wr_addr_gray[5]
.sym 12870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
.sym 12871 tx_fifo.wr_addr_gray[1]
.sym 12872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
.sym 12873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
.sym 12874 tx_fifo.wr_addr_gray[7]
.sym 12875 tx_fifo.wr_addr_gray[0]
.sym 12880 rx_fifo.mem_i.0.0_WDATA_1
.sym 12881 rx_fifo.wr_addr[6]
.sym 12883 rx_fifo.wr_addr[4]
.sym 12885 smi_ctrl_ins.int_cnt_rx[3]
.sym 12886 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 12889 rx_fifo.rd_addr[3]
.sym 12890 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 12895 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 12903 i_rst_b$SB_IO_IN
.sym 12909 tx_fifo.wr_addr_gray_rd[7]
.sym 12916 tx_fifo.wr_addr_gray_rd[5]
.sym 12925 tx_fifo.wr_addr_gray[8]
.sym 12927 smi_ctrl_ins.int_cnt_rx[4]
.sym 12929 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 12930 smi_ctrl_ins.int_cnt_rx[3]
.sym 12934 tx_fifo.wr_addr_gray[5]
.sym 12935 tx_fifo.wr_addr_gray_rd[8]
.sym 12936 tx_fifo.wr_addr_gray[1]
.sym 12937 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 12939 tx_fifo.wr_addr_gray[7]
.sym 12945 tx_fifo.wr_addr_gray[7]
.sym 12948 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 12949 smi_ctrl_ins.int_cnt_rx[4]
.sym 12950 smi_ctrl_ins.int_cnt_rx[3]
.sym 12951 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 12954 tx_fifo.wr_addr_gray[8]
.sym 12960 tx_fifo.wr_addr_gray_rd[8]
.sym 12966 tx_fifo.wr_addr_gray_rd[7]
.sym 12972 tx_fifo.wr_addr_gray_rd[5]
.sym 12978 tx_fifo.wr_addr_gray[1]
.sym 12987 tx_fifo.wr_addr_gray[5]
.sym 12989 lvds_clock_$glb_clk
.sym 12991 smi_ctrl_ins.w_fifo_pull_trigger
.sym 12993 w_smi_data_output[4]
.sym 12996 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 12998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 13003 rx_fifo.wr_addr[0]
.sym 13004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 13008 rx_fifo.mem_q.0.1_WDATA_3
.sym 13009 rx_fifo.mem_q.0.1_WDATA_2
.sym 13010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 13011 rx_fifo.wr_addr[4]
.sym 13014 rx_fifo.wr_addr[6]
.sym 13021 w_rx_fifo_pulled_data[31]
.sym 13026 w_rx_fifo_pulled_data[23]
.sym 13034 smi_ctrl_ins.int_cnt_rx[4]
.sym 13037 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 13039 tx_fifo.wr_addr_gray[0]
.sym 13042 smi_ctrl_ins.int_cnt_rx[4]
.sym 13045 smi_ctrl_ins.int_cnt_rx[3]
.sym 13046 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 13049 tx_fifo.wr_addr_gray_rd[0]
.sym 13056 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 13057 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 13063 i_rst_b$SB_IO_IN
.sym 13071 tx_fifo.wr_addr_gray[0]
.sym 13083 tx_fifo.wr_addr_gray_rd[0]
.sym 13089 smi_ctrl_ins.int_cnt_rx[3]
.sym 13090 smi_ctrl_ins.int_cnt_rx[4]
.sym 13091 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 13092 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 13101 i_rst_b$SB_IO_IN
.sym 13102 smi_ctrl_ins.int_cnt_rx[4]
.sym 13103 smi_ctrl_ins.int_cnt_rx[3]
.sym 13107 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 13108 smi_ctrl_ins.int_cnt_rx[4]
.sym 13109 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 13110 smi_ctrl_ins.int_cnt_rx[3]
.sym 13112 lvds_clock_$glb_clk
.sym 13114 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 13115 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 13117 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 13118 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 13122 io_pmod[7]$SB_IO_IN
.sym 13125 io_pmod[7]$SB_IO_IN
.sym 13128 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 13129 rx_fifo.mem_q.0.1_WDATA
.sym 13130 w_rx_fifo_pulled_data[19]
.sym 13131 rx_fifo.wr_addr[7]
.sym 13133 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 13134 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 13135 w_rx_fifo_pulled_data[18]
.sym 13136 rx_fifo.mem_q.0.1_WDATA_1
.sym 13138 w_rx_fifo_empty
.sym 13141 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 13142 rx_fifo.rd_addr[8]
.sym 13145 i_rst_b$SB_IO_IN
.sym 13147 i_rst_b$SB_IO_IN
.sym 13178 w_rx_fifo_pulled_data[22]
.sym 13186 w_rx_fifo_pulled_data[23]
.sym 13218 w_rx_fifo_pulled_data[22]
.sym 13226 w_rx_fifo_pulled_data[23]
.sym 13234 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 13235 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13237 w_rx_data[0]
.sym 13240 w_rx_data[5]
.sym 13242 w_rx_data[2]
.sym 13243 i_rst_b$SB_IO_IN
.sym 13249 rx_fifo.wr_addr[9]
.sym 13251 rx_fifo.mem_i.0.3_WDATA
.sym 13253 rx_fifo.rd_addr[3]
.sym 13255 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 13256 $PACKER_VCC_NET
.sym 13257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 13258 rx_fifo.mem_i.0.3_WDATA_2
.sym 13259 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 13260 rx_fifo.wr_addr[7]
.sym 13261 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 13266 w_rx_fifo_empty
.sym 13269 w_tx_fifo_full
.sym 13270 w_rx_data[0]
.sym 13271 i_rst_b$SB_IO_IN
.sym 13289 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13294 w_rx_data[0]
.sym 13299 w_rx_data[2]
.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13312 w_rx_data[2]
.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13337 w_rx_data[0]
.sym 13353 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 13357 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13358 r_counter_$glb_clk
.sym 13359 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13361 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 13362 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 13363 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 13364 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 13365 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 13368 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 13372 rx_fifo.wr_addr[5]
.sym 13373 rx_fifo.wr_addr[1]
.sym 13374 rx_fifo.wr_addr[3]
.sym 13376 rx_fifo.wr_addr[8]
.sym 13382 rx_fifo.wr_addr[2]
.sym 13383 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 13385 w_fetch
.sym 13388 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 13390 w_rx_data[2]
.sym 13408 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 13410 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 13413 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 13414 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 13416 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 13419 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 13420 rx_fifo.rd_addr[3]
.sym 13421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 13422 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 13427 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 13429 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 13434 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 13435 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 13436 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 13437 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 13464 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 13465 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 13466 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 13467 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 13476 rx_fifo.rd_addr[3]
.sym 13477 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 13478 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 13481 r_counter_$glb_clk
.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13483 w_cs[3]
.sym 13484 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 13485 w_cs[1]
.sym 13486 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 13487 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 13488 w_cs[2]
.sym 13495 w_rx_fifo_empty
.sym 13499 w_rx_data[3]
.sym 13500 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 13502 rx_fifo.rd_addr[9]
.sym 13509 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 13511 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 13513 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 13524 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13526 w_ioc[0]
.sym 13527 w_rx_data[4]
.sym 13528 w_cs[0]
.sym 13530 w_ioc[1]
.sym 13532 w_rx_data[1]
.sym 13534 w_ioc[1]
.sym 13540 w_rx_data[0]
.sym 13542 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 13543 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 13545 w_fetch
.sym 13550 w_rx_data[2]
.sym 13552 w_load
.sym 13557 w_ioc[1]
.sym 13559 w_ioc[0]
.sym 13560 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 13565 w_rx_data[1]
.sym 13571 w_rx_data[0]
.sym 13575 w_fetch
.sym 13576 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13577 w_load
.sym 13578 w_cs[0]
.sym 13582 w_rx_data[2]
.sym 13587 w_ioc[1]
.sym 13589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 13590 w_ioc[0]
.sym 13594 w_rx_data[4]
.sym 13603 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 13604 r_counter_$glb_clk
.sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13606 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
.sym 13607 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 13608 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 13609 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 13610 r_tx_data[0]
.sym 13611 r_tx_data[2]
.sym 13612 r_tx_data[1]
.sym 13613 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
.sym 13619 io_pmod[0]$SB_IO_IN
.sym 13620 w_ioc[1]
.sym 13621 $PACKER_VCC_NET
.sym 13622 w_ioc[0]
.sym 13626 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 13628 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13630 w_cs[1]
.sym 13631 w_tx_data_io[2]
.sym 13632 i_rst_b$SB_IO_IN
.sym 13633 w_load
.sym 13634 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 13636 w_cs[2]
.sym 13637 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 13639 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 13647 w_tx_data_smi[1]
.sym 13648 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 13649 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 13651 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
.sym 13652 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 13653 w_ioc[1]
.sym 13654 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 13655 w_fetch
.sym 13656 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 13657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 13659 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13660 w_cs[0]
.sym 13661 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
.sym 13662 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 13666 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 13668 w_ioc[0]
.sym 13674 w_tx_data_io[1]
.sym 13680 w_tx_data_smi[1]
.sym 13681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 13682 w_tx_data_io[1]
.sym 13683 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 13686 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 13687 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
.sym 13694 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 13695 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 13698 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 13705 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 13707 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 13710 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
.sym 13712 w_fetch
.sym 13713 w_cs[0]
.sym 13716 w_ioc[1]
.sym 13717 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13718 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 13719 w_ioc[0]
.sym 13722 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13724 w_ioc[0]
.sym 13725 w_ioc[1]
.sym 13726 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 13727 r_counter_$glb_clk
.sym 13728 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 13730 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 13731 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 13732 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 13733 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 13735 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 13743 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 13744 $PACKER_VCC_NET
.sym 13747 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 13753 w_ioc[1]
.sym 13757 w_tx_fifo_full
.sym 13758 w_rx_data[0]
.sym 13759 io_ctrl_ins.o_pmod[3]
.sym 13760 w_tx_data_io[1]
.sym 13761 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 13762 i_rst_b$SB_IO_IN
.sym 13763 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 13770 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 13774 o_led0_SB_LUT4_I1_O[1]
.sym 13775 w_tx_fifo_full
.sym 13781 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 13783 w_rx_fifo_empty
.sym 13789 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 13804 w_tx_fifo_full
.sym 13817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 13830 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 13836 w_rx_fifo_empty
.sym 13849 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 13850 r_counter_$glb_clk
.sym 13851 o_led0_SB_LUT4_I1_O[1]
.sym 13852 w_tx_data_io[2]
.sym 13853 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 13854 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
.sym 13855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 13856 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 13857 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 13858 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 13859 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 13867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 13874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 13877 i_rst_b$SB_IO_IN
.sym 13878 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 13881 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 13882 w_rx_data[2]
.sym 13887 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 13897 o_led0_SB_LUT4_I1_O[1]
.sym 13898 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 13901 w_fetch
.sym 13902 w_cs[1]
.sym 13904 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 13906 w_ioc[0]
.sym 13907 w_load
.sym 13909 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 13913 w_ioc[1]
.sym 13920 io_pmod[7]$SB_IO_IN
.sym 13921 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 13922 i_rst_b$SB_IO_IN
.sym 13944 w_load
.sym 13945 w_cs[1]
.sym 13946 w_fetch
.sym 13947 i_rst_b$SB_IO_IN
.sym 13950 w_ioc[1]
.sym 13952 w_ioc[0]
.sym 13953 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 13956 w_load
.sym 13957 o_led0_SB_LUT4_I1_O[1]
.sym 13958 w_fetch
.sym 13959 w_cs[1]
.sym 13968 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 13969 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 13971 io_pmod[7]$SB_IO_IN
.sym 13972 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 13973 lvds_clock_$glb_clk
.sym 13974 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13975 o_led0_SB_LUT4_I1_O[2]
.sym 13976 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
.sym 13978 w_tx_data_io[1]
.sym 13979 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 13980 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
.sym 13981 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 13982 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 13992 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 13995 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 14000 w_rx_data[0]
.sym 14002 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 14016 w_ioc[0]
.sym 14018 o_shdn_rx_lna$SB_IO_OUT
.sym 14019 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 14021 o_shdn_tx_lna$SB_IO_OUT
.sym 14022 w_rx_data[1]
.sym 14023 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 14028 w_rx_data[0]
.sym 14031 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 14034 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 14039 io_ctrl_ins.o_pmod[1]
.sym 14042 w_rx_data[2]
.sym 14044 io_ctrl_ins.o_pmod[2]
.sym 14046 w_rx_data[3]
.sym 14052 w_rx_data[0]
.sym 14061 w_ioc[0]
.sym 14062 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 14063 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 14069 w_rx_data[3]
.sym 14074 w_rx_data[2]
.sym 14079 io_ctrl_ins.o_pmod[1]
.sym 14080 w_ioc[0]
.sym 14081 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 14082 o_shdn_rx_lna$SB_IO_OUT
.sym 14085 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 14086 o_shdn_tx_lna$SB_IO_OUT
.sym 14087 w_ioc[0]
.sym 14088 io_ctrl_ins.o_pmod[2]
.sym 14092 w_rx_data[1]
.sym 14095 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 14096 r_counter_$glb_clk
.sym 14098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
.sym 14099 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 14100 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 14101 w_smi_data_direction
.sym 14102 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 14105 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 14111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 14119 i_config[0]$SB_IO_IN
.sym 14121 o_led0_SB_LUT4_I1_O[3]
.sym 14123 i_rst_b$SB_IO_IN
.sym 14141 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
.sym 14145 w_rx_data[3]
.sym 14149 w_rx_data[4]
.sym 14151 w_rx_data[1]
.sym 14154 w_rx_data[2]
.sym 14160 w_rx_data[0]
.sym 14178 w_rx_data[0]
.sym 14190 w_rx_data[4]
.sym 14196 w_rx_data[3]
.sym 14209 w_rx_data[1]
.sym 14217 w_rx_data[2]
.sym 14218 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
.sym 14219 r_counter_$glb_clk
.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14223 r_counter
.sym 14236 w_smi_data_direction
.sym 14237 o_shdn_rx_lna$SB_IO_OUT
.sym 14239 o_tr_vc1$SB_IO_OUT
.sym 14241 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 14243 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 14248 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 14249 i_rst_b$SB_IO_IN
.sym 14344 i_rst_b$SB_IO_IN
.sym 14359 i_glob_clock$SB_IO_IN
.sym 14365 i_rst_b$SB_IO_IN
.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 14406 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 14418 i_rst_b_SB_LUT4_I3_O
.sym 14419 w_smi_data_output[3]
.sym 14421 w_smi_data_direction
.sym 14425 $PACKER_VCC_NET
.sym 14430 w_smi_data_output[3]
.sym 14436 i_rst_b_SB_LUT4_I3_O
.sym 14438 w_smi_data_direction
.sym 14441 $PACKER_VCC_NET
.sym 14445 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14454 w_smi_data_direction
.sym 14456 i_rst_b_SB_LUT4_I3_O
.sym 14457 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 14474 i_rst_b$SB_IO_IN
.sym 14478 w_smi_data_output[4]
.sym 14489 tx_fifo.wr_addr_gray_rd[3]
.sym 14504 tx_fifo.wr_addr_gray[6]
.sym 14505 tx_fifo.wr_addr_gray[2]
.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 14510 tx_fifo.wr_addr_gray_rd[2]
.sym 14512 w_smi_data_direction
.sym 14513 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14514 tx_fifo.wr_addr_gray[3]
.sym 14516 tx_fifo.wr_addr_gray_rd[6]
.sym 14522 tx_fifo.wr_addr_gray[2]
.sym 14526 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14528 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 14534 w_smi_data_direction
.sym 14537 tx_fifo.wr_addr_gray[3]
.sym 14546 tx_fifo.wr_addr_gray_rd[3]
.sym 14551 tx_fifo.wr_addr_gray_rd[2]
.sym 14557 tx_fifo.wr_addr_gray[6]
.sym 14561 tx_fifo.wr_addr_gray_rd[6]
.sym 14566 lvds_clock_$glb_clk
.sym 14568 $io_pmod[3]$iobuf_i
.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14573 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 14574 tx_fifo.wr_addr_gray[6]
.sym 14575 tx_fifo.wr_addr_gray[2]
.sym 14576 tx_fifo.wr_addr_gray[3]
.sym 14577 tx_fifo.wr_addr_gray[4]
.sym 14578 tx_fifo.wr_addr[9]
.sym 14579 tx_fifo.wr_addr[1]
.sym 14602 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14613 $io_pmod[3]$iobuf_i
.sym 14614 w_smi_data_direction
.sym 14624 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 14627 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 14629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14634 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 14636 tx_fifo.rd_addr_gray_wr_r[0]
.sym 14637 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 14638 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 14649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 14651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14652 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14653 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 14655 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 14656 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14657 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 14658 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14661 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 14662 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 14663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 14666 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 14671 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 14673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 14676 i_rst_b_SB_LUT4_I3_O
.sym 14678 w_tx_fifo_empty
.sym 14682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 14688 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14690 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14694 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 14695 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 14696 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 14697 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 14701 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 14703 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 14707 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14712 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 14713 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 14715 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 14718 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 14719 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 14720 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 14721 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 14727 w_tx_fifo_empty
.sym 14728 i_rst_b_SB_LUT4_I3_O
.sym 14729 lvds_clock_$glb_clk
.sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14732 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 14734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 14737 w_smi_data_output[5]
.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14748 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 14750 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14752 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 14757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 14758 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14763 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 14764 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 14765 tx_fifo.wr_addr[1]
.sym 14766 $PACKER_VCC_NET
.sym 14777 tx_fifo.wr_addr_gray[4]
.sym 14786 tx_fifo.wr_addr[9]
.sym 14792 i_rst_b$SB_IO_IN
.sym 14793 tx_fifo.wr_addr_gray_rd[4]
.sym 14798 tx_fifo.wr_addr_gray_rd[9]
.sym 14801 tx_fifo.wr_addr_gray_rd[1]
.sym 14803 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14814 tx_fifo.wr_addr_gray_rd[1]
.sym 14820 tx_fifo.wr_addr[9]
.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14829 i_rst_b$SB_IO_IN
.sym 14837 tx_fifo.wr_addr_gray[4]
.sym 14842 tx_fifo.wr_addr_gray_rd[4]
.sym 14849 tx_fifo.wr_addr_gray_rd[9]
.sym 14852 lvds_clock_$glb_clk
.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 14855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14857 tx_fifo.rd_addr_gray_wr[5]
.sym 14858 tx_fifo.rd_addr_gray_wr[7]
.sym 14859 tx_fifo.rd_addr_gray_wr[3]
.sym 14860 tx_fifo.rd_addr_gray_wr[6]
.sym 14861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 14866 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 14874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 14875 i_rst_b$SB_IO_IN
.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 14881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14886 smi_ctrl_ins.int_cnt_rx[4]
.sym 14895 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 14897 smi_ctrl_ins.int_cnt_rx[4]
.sym 14899 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 14902 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 14904 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 14906 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14909 smi_ctrl_ins.int_cnt_rx[3]
.sym 14911 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 14912 smi_ctrl_ins.int_cnt_rx[4]
.sym 14913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 14915 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 14918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 14922 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 14923 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 14925 tx_fifo.wr_addr[1]
.sym 14926 tx_fifo.rd_addr_gray_wr_r[0]
.sym 14928 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 14929 smi_ctrl_ins.int_cnt_rx[3]
.sym 14930 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 14931 smi_ctrl_ins.int_cnt_rx[4]
.sym 14940 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 14946 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 14947 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 14948 smi_ctrl_ins.int_cnt_rx[3]
.sym 14949 smi_ctrl_ins.int_cnt_rx[4]
.sym 14955 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 14959 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 14966 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 14970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 14971 tx_fifo.rd_addr_gray_wr_r[0]
.sym 14972 tx_fifo.wr_addr[1]
.sym 14973 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 14974 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14975 lvds_clock_$glb_clk
.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 14980 o_smi_read_req$SB_IO_OUT
.sym 14981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 14988 w_rx_data[0]
.sym 14989 rx_fifo.wr_addr[2]
.sym 14997 rx_fifo.wr_addr[5]
.sym 14999 rx_fifo.wr_addr[8]
.sym 15001 w_smi_data_direction
.sym 15003 w_rx_fifo_pulled_data[28]
.sym 15004 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 15008 w_smi_data_direction
.sym 15010 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 15011 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 15020 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 15025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
.sym 15026 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 15028 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 15029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 15030 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 15036 w_tx_fifo_full
.sym 15037 tx_fifo.wr_addr[1]
.sym 15038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
.sym 15041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 15042 tx_fifo.rd_addr_gray_wr_r[1]
.sym 15044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 15047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 15052 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 15054 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 15057 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 15064 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 15065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 15066 tx_fifo.rd_addr_gray_wr_r[1]
.sym 15072 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 15075 w_tx_fifo_full
.sym 15076 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 15078 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 15081 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
.sym 15082 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
.sym 15083 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
.sym 15087 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 15090 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 15093 tx_fifo.wr_addr[1]
.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 15098 r_counter_$glb_clk
.sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15100 smi_ctrl_ins.r_fifo_pull_1
.sym 15101 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 15102 w_tx_fifo_full
.sym 15103 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 15104 smi_ctrl_ins.r_fifo_pull
.sym 15106 smi_ctrl_ins.r_fifo_push_1
.sym 15107 smi_ctrl_ins.r_fifo_push
.sym 15108 i_rst_b$SB_IO_IN
.sym 15111 i_rst_b$SB_IO_IN
.sym 15113 w_rx_fifo_empty
.sym 15114 rx_fifo.rd_addr[8]
.sym 15116 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 15118 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 15120 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 15121 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 15122 i_rst_b$SB_IO_IN
.sym 15123 rx_fifo.wr_addr[8]
.sym 15126 w_rx_fifo_pulled_data[29]
.sym 15135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 15144 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 15145 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 15146 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 15152 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 15159 smi_ctrl_ins.int_cnt_rx[3]
.sym 15162 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 15167 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 15168 i_rst_b$SB_IO_IN
.sym 15169 smi_ctrl_ins.int_cnt_rx[4]
.sym 15175 smi_ctrl_ins.int_cnt_rx[4]
.sym 15176 smi_ctrl_ins.int_cnt_rx[3]
.sym 15187 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 15189 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 15204 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 15205 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 15206 smi_ctrl_ins.int_cnt_rx[4]
.sym 15207 smi_ctrl_ins.int_cnt_rx[3]
.sym 15216 smi_ctrl_ins.int_cnt_rx[4]
.sym 15217 smi_ctrl_ins.int_cnt_rx[3]
.sym 15218 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 15219 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 15220 i_rst_b$SB_IO_IN
.sym 15221 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 15223 spi_if_ins.w_rx_data[1]
.sym 15225 spi_if_ins.w_rx_data[2]
.sym 15226 spi_if_ins.w_rx_data[4]
.sym 15228 spi_if_ins.w_rx_data[5]
.sym 15229 spi_if_ins.w_rx_data[6]
.sym 15230 spi_if_ins.w_rx_data[0]
.sym 15233 w_smi_data_direction
.sym 15241 w_rx_fifo_empty
.sym 15244 smi_ctrl_ins.w_fifo_push_trigger
.sym 15246 w_tx_fifo_full
.sym 15252 w_rx_data[0]
.sym 15253 $PACKER_VCC_NET
.sym 15256 spi_if_ins.w_rx_data[1]
.sym 15258 w_rx_data[5]
.sym 15266 w_rx_fifo_pulled_data[31]
.sym 15275 w_rx_fifo_pulled_data[28]
.sym 15279 w_rx_fifo_pulled_data[30]
.sym 15286 w_rx_fifo_pulled_data[29]
.sym 15297 w_rx_fifo_pulled_data[30]
.sym 15306 w_rx_fifo_pulled_data[31]
.sym 15318 w_rx_fifo_pulled_data[28]
.sym 15321 w_rx_fifo_pulled_data[29]
.sym 15343 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15346 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 15347 spi_if_ins.w_rx_data[3]
.sym 15348 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 15350 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 15351 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 15352 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15353 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 15357 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 15358 rx_fifo.rd_addr[6]
.sym 15361 rx_fifo.rd_addr[0]
.sym 15362 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 15367 w_rx_fifo_pulled_data[30]
.sym 15370 spi_if_ins.w_rx_data[2]
.sym 15372 w_rx_data[2]
.sym 15376 spi_if_ins.w_rx_data[5]
.sym 15378 spi_if_ins.w_rx_data[6]
.sym 15380 spi_if_ins.w_rx_data[0]
.sym 15381 spi_if_ins.w_rx_data[3]
.sym 15392 spi_if_ins.w_rx_data[5]
.sym 15394 spi_if_ins.w_rx_data[0]
.sym 15397 spi_if_ins.w_rx_data[2]
.sym 15398 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15414 i_rst_b$SB_IO_IN
.sym 15421 spi_if_ins.w_rx_data[0]
.sym 15440 spi_if_ins.w_rx_data[5]
.sym 15452 spi_if_ins.w_rx_data[2]
.sym 15456 i_rst_b$SB_IO_IN
.sym 15466 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15467 r_counter_$glb_clk
.sym 15469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 15470 w_rx_data[4]
.sym 15471 w_rx_data[7]
.sym 15472 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 15473 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15474 w_rx_data[3]
.sym 15475 w_rx_data[1]
.sym 15476 w_rx_data[6]
.sym 15481 rx_fifo.wr_addr[0]
.sym 15482 rx_fifo.wr_addr[4]
.sym 15485 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 15486 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 15489 rx_fifo.mem_i.0.3_WDATA_1
.sym 15490 w_rx_fifo_pulled_data[31]
.sym 15494 spi_if_ins.w_rx_data[1]
.sym 15495 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 15496 w_rx_data[5]
.sym 15500 w_rx_data[2]
.sym 15504 w_smi_data_direction
.sym 15513 w_rx_data[5]
.sym 15521 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 15528 w_rx_data[7]
.sym 15533 w_rx_data[6]
.sym 15538 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15539 w_rx_data[3]
.sym 15550 w_rx_data[7]
.sym 15558 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15563 w_rx_data[6]
.sym 15569 w_rx_data[3]
.sym 15575 w_rx_data[5]
.sym 15589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 15590 r_counter_$glb_clk
.sym 15591 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15592 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 15593 w_ioc[1]
.sym 15594 w_cs[0]
.sym 15595 w_ioc[4]
.sym 15596 w_ioc[3]
.sym 15597 w_ioc[0]
.sym 15598 w_ioc[2]
.sym 15599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 15605 w_rx_data[1]
.sym 15606 $PACKER_VCC_NET
.sym 15607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 15608 w_load
.sym 15609 i_rst_b$SB_IO_IN
.sym 15614 rx_fifo.rd_addr[8]
.sym 15621 i_glob_clock$SB_IO_IN
.sym 15622 w_rx_data[3]
.sym 15624 w_rx_data[1]
.sym 15627 w_ioc[1]
.sym 15635 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15644 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15646 w_cs[2]
.sym 15648 spi_if_ins.w_rx_data[5]
.sym 15650 spi_if_ins.w_rx_data[6]
.sym 15651 w_cs[1]
.sym 15653 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15657 w_cs[3]
.sym 15659 w_cs[0]
.sym 15666 spi_if_ins.w_rx_data[5]
.sym 15667 spi_if_ins.w_rx_data[6]
.sym 15672 w_cs[3]
.sym 15673 w_cs[2]
.sym 15674 w_cs[0]
.sym 15675 w_cs[1]
.sym 15678 spi_if_ins.w_rx_data[5]
.sym 15681 spi_if_ins.w_rx_data[6]
.sym 15684 spi_if_ins.w_rx_data[6]
.sym 15687 spi_if_ins.w_rx_data[5]
.sym 15692 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15696 spi_if_ins.w_rx_data[6]
.sym 15697 spi_if_ins.w_rx_data[5]
.sym 15712 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15713 r_counter_$glb_clk
.sym 15714 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15716 spi_if_ins.r_tx_byte[2]
.sym 15717 spi_if_ins.r_tx_byte[1]
.sym 15718 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 15719 spi_if_ins.r_tx_byte[0]
.sym 15720 spi_if_ins.r_tx_byte[7]
.sym 15721 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15722 spi_if_ins.r_tx_byte[6]
.sym 15734 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 15736 w_ioc[1]
.sym 15740 w_cs[1]
.sym 15743 w_fetch
.sym 15744 w_rx_data[0]
.sym 15745 w_ioc[0]
.sym 15746 w_cs[2]
.sym 15749 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 15750 w_rx_data[5]
.sym 15756 w_cs[3]
.sym 15757 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
.sym 15758 w_cs[1]
.sym 15759 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 15760 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
.sym 15761 w_cs[2]
.sym 15764 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 15765 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 15766 w_cs[0]
.sym 15767 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15769 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 15772 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
.sym 15773 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 15774 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 15775 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 15776 i_rst_b$SB_IO_IN
.sym 15777 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
.sym 15778 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15780 w_tx_data_io[2]
.sym 15781 i_glob_clock$SB_IO_IN
.sym 15782 w_tx_data_smi[2]
.sym 15783 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 15787 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
.sym 15789 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 15790 w_tx_data_io[2]
.sym 15791 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15792 w_tx_data_smi[2]
.sym 15795 w_cs[2]
.sym 15796 w_cs[3]
.sym 15797 w_cs[0]
.sym 15798 w_cs[1]
.sym 15801 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15803 i_rst_b$SB_IO_IN
.sym 15807 w_cs[0]
.sym 15808 w_cs[3]
.sym 15809 w_cs[2]
.sym 15810 w_cs[1]
.sym 15813 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
.sym 15814 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 15815 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
.sym 15816 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 15819 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
.sym 15820 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
.sym 15821 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 15822 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 15825 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 15826 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 15828 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 15831 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
.sym 15832 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15833 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 15834 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 15835 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 15836 i_glob_clock$SB_IO_IN
.sym 15838 r_tx_data[6]
.sym 15839 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 15840 r_tx_data[3]
.sym 15841 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 15842 r_tx_data[5]
.sym 15843 r_tx_data[7]
.sym 15844 r_tx_data[4]
.sym 15845 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
.sym 15850 w_fetch
.sym 15855 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 15865 w_ioc[1]
.sym 15870 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 15872 w_rx_data[2]
.sym 15873 w_ioc[0]
.sym 15881 w_cs[2]
.sym 15884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 15886 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 15887 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 15890 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 15892 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 15894 w_load
.sym 15896 o_led1_SB_LUT4_I1_I2[3]
.sym 15897 w_ioc[1]
.sym 15898 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 15903 w_fetch
.sym 15906 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 15909 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 15910 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15912 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15914 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 15920 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 15921 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15924 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15926 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 15930 o_led1_SB_LUT4_I1_I2[3]
.sym 15931 w_cs[2]
.sym 15932 w_fetch
.sym 15933 w_load
.sym 15936 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15937 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 15943 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15944 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 15948 w_ioc[1]
.sym 15949 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 15950 w_cs[2]
.sym 15951 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 15959 r_counter_$glb_clk
.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15961 io_ctrl_ins.pmod_dir_state[5]
.sym 15962 o_led1_SB_LUT4_I1_I2[3]
.sym 15963 io_ctrl_ins.pmod_dir_state[6]
.sym 15964 o_led1_SB_LUT4_I1_I2[2]
.sym 15965 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 15967 io_ctrl_ins.pmod_dir_state[3]
.sym 15968 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
.sym 15978 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 15984 lvds_clock
.sym 15987 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 15991 w_smi_data_direction
.sym 15992 w_rx_data[2]
.sym 15996 w_rx_data[5]
.sym 16004 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 16006 o_led0_SB_LUT4_I1_O[1]
.sym 16008 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 16009 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16011 w_cs[1]
.sym 16012 w_load
.sym 16013 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 16014 w_ioc[1]
.sym 16015 w_fetch
.sym 16016 w_cs[2]
.sym 16017 w_ioc[0]
.sym 16020 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
.sym 16021 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 16022 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 16024 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 16025 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 16029 o_led1_SB_LUT4_I1_I2[2]
.sym 16032 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
.sym 16033 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
.sym 16035 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
.sym 16036 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 16037 o_led0_SB_LUT4_I1_O[1]
.sym 16041 w_load
.sym 16042 o_led1_SB_LUT4_I1_I2[2]
.sym 16043 w_cs[2]
.sym 16044 w_fetch
.sym 16047 o_led1_SB_LUT4_I1_I2[2]
.sym 16049 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
.sym 16050 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
.sym 16053 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 16054 w_ioc[0]
.sym 16055 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16059 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 16060 w_ioc[1]
.sym 16061 w_ioc[0]
.sym 16062 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 16066 w_ioc[0]
.sym 16067 w_ioc[1]
.sym 16068 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 16071 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 16072 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16073 w_cs[1]
.sym 16074 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 16077 w_ioc[1]
.sym 16078 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 16081 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 16082 r_counter_$glb_clk
.sym 16083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 16084 i_config_SB_LUT4_I0_1_O[1]
.sym 16085 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
.sym 16086 i_config_SB_LUT4_I0_1_O[3]
.sym 16087 w_tx_data_io[7]
.sym 16088 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
.sym 16089 w_tx_data_io[5]
.sym 16090 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 16091 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 16098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 16109 w_rx_data[1]
.sym 16119 w_rx_data[3]
.sym 16125 o_led1_SB_LUT4_I1_O[3]
.sym 16126 o_led1_SB_LUT4_I1_I2[3]
.sym 16127 i_config[0]$SB_IO_IN
.sym 16128 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 16129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 16130 o_led1_SB_LUT4_I1_O[2]
.sym 16132 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16133 io_ctrl_ins.o_pmod[0]
.sym 16134 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
.sym 16136 o_led1_SB_LUT4_I1_I2[2]
.sym 16137 o_led0_SB_LUT4_I1_O[3]
.sym 16139 io_ctrl_ins.pmod_dir_state[3]
.sym 16140 io_ctrl_ins.o_pmod[3]
.sym 16141 o_led0_SB_LUT4_I1_O[2]
.sym 16142 o_led0_SB_LUT4_I1_O[0]
.sym 16143 w_ioc[0]
.sym 16145 o_led0_SB_LUT4_I1_O[1]
.sym 16146 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
.sym 16149 o_tr_vc2$SB_IO_OUT
.sym 16150 io_ctrl_ins.mixer_en_state
.sym 16152 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 16153 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16155 o_led1_SB_LUT4_I1_O[0]
.sym 16158 io_ctrl_ins.mixer_en_state
.sym 16159 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16160 w_ioc[0]
.sym 16161 io_ctrl_ins.o_pmod[0]
.sym 16164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 16165 io_ctrl_ins.o_pmod[3]
.sym 16166 o_tr_vc2$SB_IO_OUT
.sym 16167 w_ioc[0]
.sym 16176 o_led1_SB_LUT4_I1_O[0]
.sym 16177 o_led1_SB_LUT4_I1_O[3]
.sym 16178 o_led1_SB_LUT4_I1_O[2]
.sym 16179 o_led0_SB_LUT4_I1_O[1]
.sym 16182 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
.sym 16183 o_led1_SB_LUT4_I1_I2[3]
.sym 16184 i_config[0]$SB_IO_IN
.sym 16185 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
.sym 16188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16189 o_led1_SB_LUT4_I1_I2[2]
.sym 16190 io_ctrl_ins.pmod_dir_state[3]
.sym 16191 o_led0_SB_LUT4_I1_O[1]
.sym 16195 o_led1_SB_LUT4_I1_I2[3]
.sym 16197 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 16200 o_led0_SB_LUT4_I1_O[0]
.sym 16201 o_led0_SB_LUT4_I1_O[1]
.sym 16202 o_led0_SB_LUT4_I1_O[3]
.sym 16203 o_led0_SB_LUT4_I1_O[2]
.sym 16204 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 16205 r_counter_$glb_clk
.sym 16206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 16207 o_tr_vc2$SB_IO_OUT
.sym 16208 io_ctrl_ins.mixer_en_state
.sym 16209 o_shdn_tx_lna$SB_IO_OUT
.sym 16210 o_tr_vc1_b$SB_IO_OUT
.sym 16211 o_rx_h_tx_l$SB_IO_OUT
.sym 16212 o_shdn_rx_lna$SB_IO_OUT
.sym 16213 o_tr_vc1$SB_IO_OUT
.sym 16214 o_rx_h_tx_l_b$SB_IO_OUT
.sym 16219 o_led1_SB_LUT4_I1_O[3]
.sym 16228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 16232 o_rx_h_tx_l$SB_IO_OUT
.sym 16240 i_config[3]$SB_IO_IN
.sym 16249 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 16250 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 16251 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 16252 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16254 o_led1_SB_LUT4_I1_O[0]
.sym 16257 o_led0_SB_LUT4_I1_O[0]
.sym 16263 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 16264 i_rst_b$SB_IO_IN
.sym 16267 w_rx_data[0]
.sym 16272 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
.sym 16281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 16283 o_led0_SB_LUT4_I1_O[0]
.sym 16288 o_led1_SB_LUT4_I1_O[0]
.sym 16290 o_led0_SB_LUT4_I1_O[0]
.sym 16293 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 16294 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 16295 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16296 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 16299 w_rx_data[0]
.sym 16305 i_rst_b$SB_IO_IN
.sym 16306 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
.sym 16307 o_led1_SB_LUT4_I1_O[0]
.sym 16323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 16324 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 16325 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 16326 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 16327 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 16328 r_counter_$glb_clk
.sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 16330 io_ctrl_ins.rf_pin_state[4]
.sym 16331 io_ctrl_ins.rf_pin_state[7]
.sym 16332 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
.sym 16333 io_ctrl_ins.rf_pin_state[5]
.sym 16334 io_ctrl_ins.rf_pin_state[1]
.sym 16335 io_ctrl_ins.rf_pin_state[6]
.sym 16336 io_ctrl_ins.rf_pin_state[3]
.sym 16337 io_ctrl_ins.rf_pin_state[2]
.sym 16338 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 16344 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 16347 o_rx_h_tx_l_b$SB_IO_OUT
.sym 16354 i_button$SB_IO_IN
.sym 16371 i_glob_clock$SB_IO_IN
.sym 16389 r_counter
.sym 16418 r_counter
.sym 16451 i_glob_clock$SB_IO_IN
.sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 16453 i_config[3]$SB_IO_IN
.sym 16455 i_button$SB_IO_IN
.sym 16457 w_rx_data[0]
.sym 16480 w_rx_data[2]
.sym 16484 w_rx_data[5]
.sym 16497 r_counter
.sym 16517 r_counter
.sym 16554 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 16555 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 16556 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 16557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 16558 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 16559 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 16560 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 16577 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 16585 w_smi_data_direction
.sym 16596 tx_fifo.wr_addr[4]
.sym 16610 tx_fifo.wr_addr[1]
.sym 16612 tx_fifo.wr_addr[5]
.sym 16614 tx_fifo.wr_addr[6]
.sym 16623 tx_fifo.wr_addr[3]
.sym 16624 tx_fifo.wr_addr[7]
.sym 16625 tx_fifo.wr_addr[2]
.sym 16626 tx_fifo.wr_addr[0]
.sym 16627 $nextpnr_ICESTORM_LC_3$O
.sym 16630 tx_fifo.wr_addr[0]
.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 16635 tx_fifo.wr_addr[1]
.sym 16637 tx_fifo.wr_addr[0]
.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16641 tx_fifo.wr_addr[2]
.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 16645 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 16648 tx_fifo.wr_addr[3]
.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 16653 tx_fifo.wr_addr[4]
.sym 16655 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 16660 tx_fifo.wr_addr[5]
.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16665 tx_fifo.wr_addr[6]
.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 16669 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16671 tx_fifo.wr_addr[7]
.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16681 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 16682 tx_fifo.wr_addr[5]
.sym 16683 tx_fifo.wr_addr[8]
.sym 16684 tx_fifo.wr_addr[6]
.sym 16685 tx_fifo.wr_addr[3]
.sym 16686 tx_fifo.wr_addr[7]
.sym 16687 tx_fifo.wr_addr[2]
.sym 16688 tx_fifo.wr_addr[0]
.sym 16694 tx_fifo.wr_addr[4]
.sym 16697 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 16703 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 16733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 16735 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 16736 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 16742 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 16744 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16753 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 16765 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16767 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 16769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16770 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 16772 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 16775 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 16776 tx_fifo.wr_addr[8]
.sym 16780 tx_fifo.wr_addr[9]
.sym 16783 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 16790 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 16793 tx_fifo.wr_addr[8]
.sym 16794 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16798 tx_fifo.wr_addr[9]
.sym 16800 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 16812 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 16815 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 16823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 16828 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 16833 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16838 r_counter_$glb_clk
.sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 16845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 16850 w_rx_data[3]
.sym 16851 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 16857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16872 tx_fifo.wr_addr[2]
.sym 16875 $PACKER_VCC_NET
.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 16882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 16883 i_rst_b$SB_IO_IN
.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16890 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 16891 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 16892 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 16894 tx_fifo.rd_addr_gray_wr_r[0]
.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 16903 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 16904 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 16905 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 16907 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 16910 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 16933 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 16934 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 16945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 16946 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 16947 tx_fifo.rd_addr_gray_wr_r[0]
.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 16952 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 16956 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16958 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 16959 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 16960 i_rst_b$SB_IO_IN
.sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 16964 spi_if_ins.spi.r_rx_bit_count[1]
.sym 16965 spi_if_ins.spi.r_rx_bit_count[2]
.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 16969 spi_if_ins.spi.r_rx_bit_count[0]
.sym 16970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 16973 w_ioc[0]
.sym 16975 $io_pmod[3]$iobuf_i
.sym 16979 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 16983 tx_fifo.rd_addr_gray_wr[4]
.sym 16984 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 16985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 16988 i_ss$SB_IO_IN
.sym 16990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
.sym 16994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 17009 tx_fifo.rd_addr_gray[5]
.sym 17012 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 17014 tx_fifo.rd_addr_gray[3]
.sym 17016 tx_fifo.rd_addr_gray[6]
.sym 17017 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 17018 tx_fifo.rd_addr_gray[7]
.sym 17026 tx_fifo.rd_addr_gray_wr[6]
.sym 17032 tx_fifo.rd_addr_gray_wr[7]
.sym 17033 tx_fifo.rd_addr_gray_wr[3]
.sym 17037 tx_fifo.rd_addr_gray_wr[6]
.sym 17043 tx_fifo.rd_addr_gray_wr[7]
.sym 17049 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 17052 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 17055 tx_fifo.rd_addr_gray[5]
.sym 17062 tx_fifo.rd_addr_gray[7]
.sym 17069 tx_fifo.rd_addr_gray[3]
.sym 17074 tx_fifo.rd_addr_gray[6]
.sym 17080 tx_fifo.rd_addr_gray_wr[3]
.sym 17084 r_counter_$glb_clk
.sym 17088 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 17089 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 17091 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 17092 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 17096 w_rx_data[6]
.sym 17100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 17101 rx_fifo.rd_addr[9]
.sym 17105 i_sck$SB_IO_IN
.sym 17106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 17109 i_ss$SB_IO_IN
.sym 17129 w_tx_fifo_full
.sym 17130 tx_fifo.rd_addr_gray_wr[5]
.sym 17131 w_rx_fifo_empty
.sym 17132 i_rst_b$SB_IO_IN
.sym 17134 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 17138 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 17144 tx_fifo.wr_addr[2]
.sym 17151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 17154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 17156 tx_fifo.rd_addr_gray_wr_r[1]
.sym 17157 w_smi_data_direction
.sym 17160 tx_fifo.rd_addr_gray_wr_r[1]
.sym 17161 tx_fifo.wr_addr[2]
.sym 17162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 17179 w_rx_fifo_empty
.sym 17180 w_smi_data_direction
.sym 17181 w_tx_fifo_full
.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 17186 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 17187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 17190 tx_fifo.rd_addr_gray_wr[5]
.sym 17204 i_rst_b$SB_IO_IN
.sym 17205 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 17207 r_counter_$glb_clk
.sym 17210 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17212 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17225 w_rx_fifo_pulled_data[6]
.sym 17227 io_pmod[0]$SB_IO_IN
.sym 17232 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 17234 i_mosi$SB_IO_IN
.sym 17251 w_rx_fifo_empty
.sym 17252 smi_ctrl_ins.w_fifo_push_trigger
.sym 17255 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 17256 smi_ctrl_ins.r_fifo_push_1
.sym 17257 smi_ctrl_ins.r_fifo_push
.sym 17258 smi_ctrl_ins.w_fifo_pull_trigger
.sym 17260 w_tx_fifo_full
.sym 17262 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
.sym 17265 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
.sym 17270 smi_ctrl_ins.r_fifo_pull
.sym 17274 smi_ctrl_ins.r_fifo_pull_1
.sym 17279 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
.sym 17285 smi_ctrl_ins.r_fifo_pull
.sym 17289 w_rx_fifo_empty
.sym 17291 smi_ctrl_ins.r_fifo_pull_1
.sym 17292 smi_ctrl_ins.r_fifo_pull
.sym 17295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
.sym 17296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 17297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
.sym 17298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
.sym 17301 w_tx_fifo_full
.sym 17302 smi_ctrl_ins.r_fifo_push_1
.sym 17303 smi_ctrl_ins.r_fifo_push
.sym 17310 smi_ctrl_ins.w_fifo_pull_trigger
.sym 17320 smi_ctrl_ins.r_fifo_push
.sym 17328 smi_ctrl_ins.w_fifo_push_trigger
.sym 17330 r_counter_$glb_clk
.sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 17332 spi_if_ins.spi.r_rx_byte[5]
.sym 17333 spi_if_ins.spi.r_rx_byte[1]
.sym 17334 spi_if_ins.spi.r_rx_byte[7]
.sym 17335 spi_if_ins.spi.r_rx_byte[0]
.sym 17336 spi_if_ins.spi.r_rx_byte[2]
.sym 17337 spi_if_ins.spi.r_rx_byte[6]
.sym 17338 spi_if_ins.spi.r_rx_byte[4]
.sym 17339 spi_if_ins.spi.r_rx_byte[3]
.sym 17342 w_rx_data[4]
.sym 17347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17348 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 17351 i_ss$SB_IO_IN
.sym 17358 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17359 $PACKER_VCC_NET
.sym 17364 i_rst_b$SB_IO_IN
.sym 17384 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17390 spi_if_ins.spi.r_rx_byte[1]
.sym 17397 spi_if_ins.spi.r_rx_byte[5]
.sym 17400 spi_if_ins.spi.r_rx_byte[0]
.sym 17401 spi_if_ins.spi.r_rx_byte[2]
.sym 17402 spi_if_ins.spi.r_rx_byte[6]
.sym 17403 spi_if_ins.spi.r_rx_byte[4]
.sym 17407 spi_if_ins.spi.r_rx_byte[1]
.sym 17419 spi_if_ins.spi.r_rx_byte[2]
.sym 17426 spi_if_ins.spi.r_rx_byte[4]
.sym 17436 spi_if_ins.spi.r_rx_byte[5]
.sym 17444 spi_if_ins.spi.r_rx_byte[6]
.sym 17449 spi_if_ins.spi.r_rx_byte[0]
.sym 17452 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17453 r_counter_$glb_clk
.sym 17455 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 17456 spi_if_ins.state_if[0]
.sym 17457 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17458 spi_if_ins.state_if[1]
.sym 17459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 17460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 17461 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 17462 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17466 w_rx_data[7]
.sym 17467 spi_if_ins.w_rx_data[1]
.sym 17468 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 17469 w_rx_fifo_pulled_data[28]
.sym 17470 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 17472 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 17473 i_sck$SB_IO_IN
.sym 17474 rx_fifo.mem_i.0.3_WDATA_3
.sym 17475 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17478 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 17480 w_rx_data[1]
.sym 17481 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17482 spi_if_ins.w_rx_data[4]
.sym 17485 $PACKER_VCC_NET
.sym 17486 w_rx_data[4]
.sym 17488 w_rx_data[7]
.sym 17490 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17503 spi_if_ins.spi.r_rx_byte[3]
.sym 17504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 17506 spi_if_ins.spi.r_rx_byte[7]
.sym 17507 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17510 i_rst_b$SB_IO_IN
.sym 17512 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 17515 spi_if_ins.state_if[1]
.sym 17518 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17519 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17521 spi_if_ins.state_if[0]
.sym 17522 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17527 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 17530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17531 spi_if_ins.state_if[0]
.sym 17532 spi_if_ins.state_if[1]
.sym 17537 spi_if_ins.spi.r_rx_byte[3]
.sym 17542 spi_if_ins.spi.r_rx_byte[7]
.sym 17553 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 17554 i_rst_b$SB_IO_IN
.sym 17555 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 17559 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 17560 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17561 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17566 i_rst_b$SB_IO_IN
.sym 17567 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17568 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 17571 spi_if_ins.state_if[1]
.sym 17573 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17574 spi_if_ins.state_if[0]
.sym 17575 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17576 r_counter_$glb_clk
.sym 17579 $PACKER_VCC_NET
.sym 17580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 17581 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 17582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 17583 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 17584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17585 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17590 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 17592 w_rx_fifo_pulled_data[29]
.sym 17596 i_glob_clock$SB_IO_IN
.sym 17600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 17601 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 17604 w_rx_data[3]
.sym 17605 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 17606 w_rx_data[1]
.sym 17607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 17609 w_ioc[1]
.sym 17611 w_cs[0]
.sym 17612 w_rx_data[4]
.sym 17620 spi_if_ins.w_rx_data[3]
.sym 17621 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 17623 spi_if_ins.w_rx_data[6]
.sym 17627 spi_if_ins.w_rx_data[1]
.sym 17629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17630 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17633 i_rst_b$SB_IO_IN
.sym 17634 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17642 spi_if_ins.w_rx_data[4]
.sym 17646 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 17652 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17654 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 17655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17658 spi_if_ins.w_rx_data[4]
.sym 17666 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 17670 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17671 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17676 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 17677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 17678 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 17679 i_rst_b$SB_IO_IN
.sym 17682 spi_if_ins.w_rx_data[3]
.sym 17691 spi_if_ins.w_rx_data[1]
.sym 17697 spi_if_ins.w_rx_data[6]
.sym 17698 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 17699 r_counter_$glb_clk
.sym 17701 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 17702 spi_if_ins.spi.r_tx_byte[7]
.sym 17703 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 17704 spi_if_ins.spi.r_tx_byte[5]
.sym 17705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 17706 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17707 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 17708 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 17713 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 17714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 17719 w_rx_data[0]
.sym 17720 w_fetch
.sym 17721 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 17722 $PACKER_VCC_NET
.sym 17724 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 17732 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 17735 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17736 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17743 spi_if_ins.w_rx_data[2]
.sym 17744 spi_if_ins.w_rx_data[3]
.sym 17745 spi_if_ins.w_rx_data[0]
.sym 17746 w_ioc[3]
.sym 17752 spi_if_ins.w_rx_data[4]
.sym 17753 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 17755 spi_if_ins.w_rx_data[1]
.sym 17760 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 17769 w_ioc[4]
.sym 17772 w_ioc[2]
.sym 17775 w_ioc[4]
.sym 17777 w_ioc[3]
.sym 17778 w_ioc[2]
.sym 17782 spi_if_ins.w_rx_data[1]
.sym 17789 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 17795 spi_if_ins.w_rx_data[4]
.sym 17799 spi_if_ins.w_rx_data[3]
.sym 17807 spi_if_ins.w_rx_data[0]
.sym 17812 spi_if_ins.w_rx_data[2]
.sym 17817 w_ioc[2]
.sym 17818 w_ioc[3]
.sym 17820 w_ioc[4]
.sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 17822 r_counter_$glb_clk
.sym 17824 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 17825 spi_if_ins.spi.r_tx_byte[6]
.sym 17826 spi_if_ins.spi.r_tx_byte[2]
.sym 17827 spi_if_ins.spi.r_tx_byte[0]
.sym 17828 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 17829 spi_if_ins.spi.r_tx_byte[1]
.sym 17830 spi_if_ins.spi.r_tx_byte[4]
.sym 17831 spi_if_ins.spi.r_tx_byte[3]
.sym 17837 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 17838 w_ioc[0]
.sym 17840 w_ioc[1]
.sym 17842 w_load
.sym 17848 spi_if_ins.r_tx_byte[5]
.sym 17849 w_fetch
.sym 17850 w_load
.sym 17855 w_ioc[0]
.sym 17856 i_rst_b$SB_IO_IN
.sym 17859 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 17869 r_tx_data[0]
.sym 17870 r_tx_data[2]
.sym 17871 r_tx_data[1]
.sym 17873 r_tx_data[6]
.sym 17875 w_cs[0]
.sym 17878 r_tx_data[7]
.sym 17883 w_cs[1]
.sym 17889 w_cs[3]
.sym 17892 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17894 w_cs[2]
.sym 17904 r_tx_data[2]
.sym 17910 r_tx_data[1]
.sym 17916 w_cs[3]
.sym 17917 w_cs[1]
.sym 17918 w_cs[0]
.sym 17919 w_cs[2]
.sym 17922 r_tx_data[0]
.sym 17931 r_tx_data[7]
.sym 17934 w_cs[2]
.sym 17935 w_cs[3]
.sym 17936 w_cs[1]
.sym 17937 w_cs[0]
.sym 17942 r_tx_data[6]
.sym 17944 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17945 r_counter_$glb_clk
.sym 17949 spi_if_ins.r_tx_byte[4]
.sym 17952 spi_if_ins.r_tx_byte[3]
.sym 17953 spi_if_ins.r_tx_byte[5]
.sym 17960 $PACKER_GND_NET
.sym 17961 spi_if_ins.r_tx_byte[7]
.sym 17964 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 17969 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 17972 i_glob_clock$SB_IO_IN
.sym 17973 w_rx_data[1]
.sym 17975 i_config[2]$SB_IO_IN
.sym 17976 w_rx_data[7]
.sym 17977 w_tx_data_io[7]
.sym 17978 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17981 w_tx_data_io[5]
.sym 17988 i_glob_clock$SB_IO_IN
.sym 17989 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 17993 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 17995 w_tx_data_io[7]
.sym 17996 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 17997 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 17998 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 17999 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 18000 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
.sym 18005 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 18006 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 18007 w_tx_data_io[5]
.sym 18009 w_fetch
.sym 18011 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18013 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18015 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18016 i_rst_b$SB_IO_IN
.sym 18018 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 18019 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
.sym 18021 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18022 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 18023 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18024 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 18028 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18029 w_tx_data_io[7]
.sym 18030 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 18033 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18034 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 18035 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18036 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 18039 w_fetch
.sym 18041 i_rst_b$SB_IO_IN
.sym 18045 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
.sym 18047 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18048 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
.sym 18052 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 18053 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 18054 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18057 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18058 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 18059 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18060 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18064 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18065 w_tx_data_io[5]
.sym 18066 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 18067 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 18068 i_glob_clock$SB_IO_IN
.sym 18072 o_led1_SB_DFFER_Q_E
.sym 18073 io_ctrl_ins.pmod_dir_state[0]
.sym 18075 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18094 o_tr_vc2$SB_IO_OUT
.sym 18097 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18100 w_rx_data[4]
.sym 18103 w_rx_data[1]
.sym 18104 w_rx_data[3]
.sym 18114 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 18115 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18117 w_rx_data[2]
.sym 18119 w_cs[1]
.sym 18121 w_rx_data[5]
.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 18125 w_ioc[0]
.sym 18126 w_ioc[1]
.sym 18128 o_led1_SB_LUT4_I1_I2[3]
.sym 18129 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18137 w_rx_data[3]
.sym 18141 w_rx_data[6]
.sym 18145 w_rx_data[5]
.sym 18150 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 18152 w_ioc[0]
.sym 18153 w_ioc[1]
.sym 18157 w_rx_data[6]
.sym 18162 w_ioc[0]
.sym 18163 w_ioc[1]
.sym 18164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 18168 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 18169 o_led1_SB_LUT4_I1_I2[3]
.sym 18170 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18171 w_cs[1]
.sym 18181 w_rx_data[3]
.sym 18189 w_rx_data[2]
.sym 18190 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18191 r_counter_$glb_clk
.sym 18193 o_led1_SB_LUT4_I1_I2[1]
.sym 18194 io_ctrl_ins.pmod_dir_state[7]
.sym 18195 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 18196 i_config_SB_LUT4_I0_1_O[2]
.sym 18197 o_led1_SB_LUT4_I1_O[3]
.sym 18199 o_led0_SB_LUT4_I1_O[3]
.sym 18200 io_ctrl_ins.pmod_dir_state[1]
.sym 18205 w_cs[1]
.sym 18211 w_rx_data[0]
.sym 18212 o_rx_h_tx_l$SB_IO_OUT
.sym 18216 o_led1_SB_DFFER_Q_E
.sym 18234 io_ctrl_ins.pmod_dir_state[5]
.sym 18235 o_led1_SB_LUT4_I1_I2[3]
.sym 18236 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18237 o_led1_SB_LUT4_I1_I2[2]
.sym 18238 o_rx_h_tx_l$SB_IO_OUT
.sym 18240 o_tr_vc1$SB_IO_OUT
.sym 18242 i_config_SB_LUT4_I0_1_O[1]
.sym 18244 io_ctrl_ins.pmod_dir_state[6]
.sym 18246 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
.sym 18247 i_config[2]$SB_IO_IN
.sym 18248 i_button$SB_IO_IN
.sym 18249 o_rx_h_tx_l_b$SB_IO_OUT
.sym 18251 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
.sym 18252 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 18254 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18256 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 18259 io_ctrl_ins.pmod_dir_state[7]
.sym 18260 w_ioc[0]
.sym 18263 i_config[3]$SB_IO_IN
.sym 18265 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 18268 w_ioc[0]
.sym 18269 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 18273 i_config_SB_LUT4_I0_1_O[1]
.sym 18274 io_ctrl_ins.pmod_dir_state[7]
.sym 18275 o_led1_SB_LUT4_I1_I2[2]
.sym 18276 o_rx_h_tx_l$SB_IO_OUT
.sym 18279 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18280 o_led1_SB_LUT4_I1_I2[3]
.sym 18281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18285 i_button$SB_IO_IN
.sym 18286 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18287 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
.sym 18291 io_ctrl_ins.pmod_dir_state[5]
.sym 18292 i_config_SB_LUT4_I0_1_O[1]
.sym 18293 o_tr_vc1$SB_IO_OUT
.sym 18294 o_led1_SB_LUT4_I1_I2[2]
.sym 18298 i_config[2]$SB_IO_IN
.sym 18299 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
.sym 18300 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18303 i_config[3]$SB_IO_IN
.sym 18304 o_led1_SB_LUT4_I1_I2[2]
.sym 18305 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 18306 io_ctrl_ins.pmod_dir_state[6]
.sym 18310 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 18311 i_config_SB_LUT4_I0_1_O[1]
.sym 18312 o_rx_h_tx_l_b$SB_IO_OUT
.sym 18313 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 18314 r_counter_$glb_clk
.sym 18317 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18318 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18328 o_led0$SB_IO_OUT
.sym 18331 o_led1$SB_IO_OUT
.sym 18336 i_button$SB_IO_IN
.sym 18340 i_rst_b$SB_IO_IN
.sym 18341 i_config[1]$SB_IO_IN
.sym 18345 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 18347 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18358 io_ctrl_ins.rf_pin_state[7]
.sym 18359 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18360 io_ctrl_ins.rf_pin_state[5]
.sym 18361 io_ctrl_ins.rf_pin_state[1]
.sym 18364 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18365 io_ctrl_ins.rf_pin_state[4]
.sym 18366 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18367 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
.sym 18368 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 18370 io_ctrl_ins.rf_pin_state[6]
.sym 18371 io_ctrl_ins.rf_pin_state[3]
.sym 18372 io_ctrl_ins.rf_pin_state[2]
.sym 18379 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18381 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 18387 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18390 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18391 io_ctrl_ins.rf_pin_state[3]
.sym 18392 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18393 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 18396 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18398 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 18399 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18402 io_ctrl_ins.rf_pin_state[2]
.sym 18403 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 18404 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 18409 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18410 io_ctrl_ins.rf_pin_state[4]
.sym 18411 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18414 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18415 io_ctrl_ins.rf_pin_state[7]
.sym 18417 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18421 io_ctrl_ins.rf_pin_state[1]
.sym 18422 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 18423 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18426 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18428 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18429 io_ctrl_ins.rf_pin_state[5]
.sym 18432 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18433 io_ctrl_ins.rf_pin_state[6]
.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 18436 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 18437 r_counter_$glb_clk
.sym 18453 o_shdn_rx_lna$SB_IO_OUT
.sym 18459 o_tr_vc1_b$SB_IO_OUT
.sym 18464 o_shdn_tx_lna$SB_IO_OUT
.sym 18471 i_config[2]$SB_IO_IN
.sym 18480 w_rx_data[1]
.sym 18482 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18483 w_rx_data[0]
.sym 18490 w_rx_data[3]
.sym 18503 w_rx_data[5]
.sym 18505 w_rx_data[6]
.sym 18507 w_rx_data[2]
.sym 18509 w_rx_data[4]
.sym 18511 w_rx_data[7]
.sym 18515 w_rx_data[4]
.sym 18522 w_rx_data[7]
.sym 18528 w_rx_data[0]
.sym 18533 w_rx_data[5]
.sym 18539 w_rx_data[1]
.sym 18546 w_rx_data[6]
.sym 18552 w_rx_data[3]
.sym 18556 w_rx_data[2]
.sym 18559 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18560 r_counter_$glb_clk
.sym 18562 i_config[1]$SB_IO_IN
.sym 18564 i_config[2]$SB_IO_IN
.sym 18636 w_smi_data_output[4]
.sym 18638 w_smi_data_direction
.sym 18642 $PACKER_VCC_NET
.sym 18647 w_smi_data_output[4]
.sym 18655 $PACKER_VCC_NET
.sym 18657 w_smi_data_direction
.sym 18679 $PACKER_VCC_NET
.sym 18695 i_mosi$SB_IO_IN
.sym 18706 tx_fifo.wr_addr[6]
.sym 18707 tx_fifo.wr_addr[4]
.sym 18708 tx_fifo.wr_addr[7]
.sym 18712 tx_fifo.wr_addr[5]
.sym 18713 tx_fifo.wr_addr[8]
.sym 18715 tx_fifo.wr_addr[3]
.sym 18717 tx_fifo.wr_addr[2]
.sym 18726 tx_fifo.wr_addr[1]
.sym 18734 tx_fifo.wr_addr[1]
.sym 18735 $nextpnr_ICESTORM_LC_1$O
.sym 18737 tx_fifo.wr_addr[1]
.sym 18741 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18744 tx_fifo.wr_addr[2]
.sym 18745 tx_fifo.wr_addr[1]
.sym 18747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 18749 tx_fifo.wr_addr[3]
.sym 18751 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18753 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 18755 tx_fifo.wr_addr[4]
.sym 18757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 18759 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 18762 tx_fifo.wr_addr[5]
.sym 18763 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 18765 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 18768 tx_fifo.wr_addr[6]
.sym 18769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 18771 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 18773 tx_fifo.wr_addr[7]
.sym 18775 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 18777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
.sym 18780 tx_fifo.wr_addr[8]
.sym 18781 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 18785 i_smi_soe_se$SB_IO_IN
.sym 18818 $PACKER_VCC_NET
.sym 18831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 18835 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 18838 $PACKER_VCC_NET
.sym 18841 w_smi_data_output[5]
.sym 18842 w_smi_data_direction
.sym 18843 rx_fifo.wr_addr[6]
.sym 18844 w_smi_data_input[7]
.sym 18848 i_smi_soe_se$SB_IO_IN
.sym 18849 rx_fifo.wr_addr[1]
.sym 18850 rx_fifo.wr_addr[3]
.sym 18853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 18854 rx_fifo.wr_addr[4]
.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 18861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18872 tx_fifo.wr_addr[9]
.sym 18874 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 18881 tx_fifo.wr_addr[0]
.sym 18884 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 18885 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 18887 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 18888 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 18889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 18899 tx_fifo.wr_addr[9]
.sym 18902 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 18914 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 18931 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 18937 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 18942 tx_fifo.wr_addr[0]
.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18946 r_counter_$glb_clk
.sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 18949 w_rx_fifo_pulled_data[16]
.sym 18953 w_rx_fifo_pulled_data[18]
.sym 18960 i_ss$SB_IO_IN
.sym 18964 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18973 rx_fifo.wr_addr[0]
.sym 18976 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 18977 w_smi_data_input[7]
.sym 18978 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 18990 tx_fifo.rd_addr_gray_wr[2]
.sym 18992 tx_fifo.rd_addr_gray_wr[4]
.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 18997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 18998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 19002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 19004 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 19005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 19008 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
.sym 19012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
.sym 19015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 19017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 19018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 19020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 19023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 19024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 19031 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 19049 tx_fifo.rd_addr_gray_wr[4]
.sym 19052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
.sym 19055 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
.sym 19058 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 19060 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 19064 tx_fifo.rd_addr_gray_wr[2]
.sym 19069 r_counter_$glb_clk
.sym 19072 w_rx_fifo_pulled_data[17]
.sym 19076 w_rx_fifo_pulled_data[19]
.sym 19084 tx_fifo.rd_addr_gray_wr[2]
.sym 19091 rx_fifo.mem_i.0.0_WDATA_2
.sym 19097 rx_fifo.wr_addr[7]
.sym 19098 w_rx_fifo_pulled_data[19]
.sym 19101 w_rx_fifo_pulled_data[18]
.sym 19103 $PACKER_VCC_NET
.sym 19106 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 19112 i_sck$SB_IO_IN
.sym 19116 i_ss$SB_IO_IN
.sym 19117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 19118 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 19119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 19120 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 19121 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 19134 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19137 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19138 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
.sym 19144 $nextpnr_ICESTORM_LC_2$O
.sym 19147 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19150 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 19152 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19154 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19158 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19160 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 19165 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 19178 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 19183 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 19188 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 19189 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 19192 i_sck$SB_IO_IN
.sym 19193 i_ss$SB_IO_IN
.sym 19195 w_rx_fifo_pulled_data[4]
.sym 19199 w_rx_fifo_pulled_data[6]
.sym 19206 i_mosi$SB_IO_IN
.sym 19207 rx_fifo.rd_addr[6]
.sym 19211 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 19213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 19215 rx_fifo.rd_addr[0]
.sym 19219 rx_fifo.wr_addr[9]
.sym 19221 rx_fifo.rd_addr[3]
.sym 19223 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 19224 $PACKER_VCC_NET
.sym 19225 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 19226 $PACKER_VCC_NET
.sym 19227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 19228 w_smi_data_direction
.sym 19244 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19245 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19248 i_ss$SB_IO_IN
.sym 19249 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19260 w_rx_fifo_pulled_data[5]
.sym 19264 w_rx_fifo_pulled_data[7]
.sym 19280 w_rx_fifo_pulled_data[7]
.sym 19286 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19287 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19288 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19298 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19299 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19300 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19301 i_ss$SB_IO_IN
.sym 19304 w_rx_fifo_pulled_data[5]
.sym 19314 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 19315 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 19316 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 19318 w_rx_fifo_pulled_data[5]
.sym 19322 w_rx_fifo_pulled_data[7]
.sym 19337 o_smi_read_req$SB_IO_OUT
.sym 19341 rx_fifo.wr_addr[1]
.sym 19342 rx_fifo.wr_addr[5]
.sym 19343 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 19344 rx_fifo.wr_addr[8]
.sym 19345 i_smi_soe_se$SB_IO_IN
.sym 19346 rx_fifo.wr_addr[3]
.sym 19347 rx_fifo.wr_addr[1]
.sym 19350 rx_fifo.wr_addr[2]
.sym 19352 rx_fifo.wr_addr[3]
.sym 19359 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19366 i_ss$SB_IO_IN
.sym 19369 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 19397 i_ss$SB_IO_IN
.sym 19400 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 19411 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19438 r_counter_$glb_clk
.sym 19441 w_rx_fifo_pulled_data[28]
.sym 19445 w_rx_fifo_pulled_data[30]
.sym 19452 $PACKER_VCC_NET
.sym 19459 rx_fifo.rd_addr[8]
.sym 19463 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19464 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 19466 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 19467 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19468 rx_fifo.rd_addr[9]
.sym 19472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 19473 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 19481 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 19483 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 19485 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 19486 i_mosi$SB_IO_IN
.sym 19487 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 19489 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19490 i_sck$SB_IO_IN
.sym 19493 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 19495 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 19508 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 19517 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19522 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 19528 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 19532 i_mosi$SB_IO_IN
.sym 19541 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 19545 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 19550 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 19557 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 19560 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 19561 i_sck$SB_IO_IN
.sym 19564 w_rx_fifo_pulled_data[29]
.sym 19568 w_rx_fifo_pulled_data[31]
.sym 19575 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19579 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 19581 rx_fifo.wr_addr[6]
.sym 19585 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 19594 $PACKER_VCC_NET
.sym 19598 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 19604 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 19606 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 19608 i_rst_b$SB_IO_IN
.sym 19611 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 19612 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 19613 spi_if_ins.state_if[0]
.sym 19615 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 19617 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19618 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19623 spi_if_ins.state_if[1]
.sym 19625 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 19627 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 19631 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 19632 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 19638 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19640 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 19645 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 19649 spi_if_ins.state_if[0]
.sym 19650 spi_if_ins.state_if[1]
.sym 19655 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 19657 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 19658 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 19661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 19663 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 19664 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19667 spi_if_ins.state_if[1]
.sym 19668 spi_if_ins.state_if[0]
.sym 19669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 19673 i_rst_b$SB_IO_IN
.sym 19674 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 19675 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19676 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 19679 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 19683 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 19684 r_counter_$glb_clk
.sym 19685 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 19698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 19700 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 19702 rx_fifo.rd_addr[6]
.sym 19704 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 19706 rx_fifo.rd_addr[3]
.sym 19710 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 19719 w_smi_data_direction
.sym 19720 $PACKER_VCC_NET
.sym 19721 rx_fifo.mem_i.0.3_WDATA
.sym 19729 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 19730 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19731 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 19732 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 19734 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19740 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 19742 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 19746 i_rst_b$SB_IO_IN
.sym 19750 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 19752 $PACKER_VCC_NET
.sym 19753 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 19754 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 19756 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19757 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19759 $nextpnr_ICESTORM_LC_9$O
.sym 19761 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19765 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 19767 $PACKER_VCC_NET
.sym 19768 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19773 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 19774 $PACKER_VCC_NET
.sym 19775 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 19778 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 19779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 19780 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 19781 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 19784 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 19785 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 19787 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 19791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 19792 i_rst_b$SB_IO_IN
.sym 19796 $PACKER_VCC_NET
.sym 19797 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19799 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19804 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19806 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 19807 r_counter_$glb_clk
.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 19821 w_fetch
.sym 19826 w_load
.sym 19835 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 19836 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 19837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19838 i_glob_clock$SB_IO_IN
.sym 19852 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19854 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 19856 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19857 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19858 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 19859 spi_if_ins.spi.r_tx_byte[6]
.sym 19860 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 19861 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 19862 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 19863 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19864 spi_if_ins.spi.r_tx_byte[4]
.sym 19865 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 19868 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 19869 spi_if_ins.spi.r_tx_byte[5]
.sym 19870 spi_if_ins.r_tx_byte[5]
.sym 19871 spi_if_ins.r_tx_byte[7]
.sym 19872 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 19874 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 19875 spi_if_ins.spi.r_tx_byte[7]
.sym 19883 spi_if_ins.spi.r_tx_byte[7]
.sym 19884 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19885 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19886 spi_if_ins.spi.r_tx_byte[5]
.sym 19889 spi_if_ins.r_tx_byte[7]
.sym 19895 spi_if_ins.spi.r_tx_byte[6]
.sym 19896 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19897 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19898 spi_if_ins.spi.r_tx_byte[4]
.sym 19904 spi_if_ins.r_tx_byte[5]
.sym 19907 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 19908 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 19909 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 19910 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 19913 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 19914 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 19916 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 19920 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 19921 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19922 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19925 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 19926 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 19928 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19929 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19930 r_counter_$glb_clk
.sym 19931 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19944 i_glob_clock$SB_IO_IN
.sym 19946 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19954 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 19974 spi_if_ins.r_tx_byte[2]
.sym 19975 spi_if_ins.r_tx_byte[4]
.sym 19978 spi_if_ins.r_tx_byte[3]
.sym 19980 spi_if_ins.r_tx_byte[6]
.sym 19983 spi_if_ins.r_tx_byte[1]
.sym 19984 spi_if_ins.spi.r_tx_byte[0]
.sym 19985 spi_if_ins.r_tx_byte[0]
.sym 19986 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19987 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19999 spi_if_ins.spi.r_tx_byte[2]
.sym 20000 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 20002 spi_if_ins.spi.r_tx_byte[1]
.sym 20004 spi_if_ins.spi.r_tx_byte[3]
.sym 20006 spi_if_ins.spi.r_tx_byte[0]
.sym 20008 spi_if_ins.spi.r_tx_byte[1]
.sym 20009 spi_if_ins.spi.r_tx_bit_count[0]
.sym 20014 spi_if_ins.r_tx_byte[6]
.sym 20019 spi_if_ins.r_tx_byte[2]
.sym 20026 spi_if_ins.r_tx_byte[0]
.sym 20031 spi_if_ins.spi.r_tx_byte[2]
.sym 20032 spi_if_ins.spi.r_tx_byte[3]
.sym 20033 spi_if_ins.spi.r_tx_bit_count[0]
.sym 20038 spi_if_ins.r_tx_byte[1]
.sym 20042 spi_if_ins.r_tx_byte[4]
.sym 20048 spi_if_ins.r_tx_byte[3]
.sym 20052 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 20053 r_counter_$glb_clk
.sym 20054 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 20075 o_tr_vc2$SB_IO_OUT
.sym 20098 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 20100 r_tx_data[5]
.sym 20102 r_tx_data[4]
.sym 20106 r_tx_data[3]
.sym 20141 r_tx_data[4]
.sym 20159 r_tx_data[3]
.sym 20167 r_tx_data[5]
.sym 20175 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 20176 r_counter_$glb_clk
.sym 20206 w_smi_data_direction
.sym 20220 w_rx_data[0]
.sym 20221 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20222 o_led1_SB_LUT4_I1_I2[2]
.sym 20224 w_cs[1]
.sym 20227 w_fetch
.sym 20228 o_led1_SB_LUT4_I1_I2[3]
.sym 20230 w_load
.sym 20246 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20264 w_load
.sym 20265 w_cs[1]
.sym 20266 o_led1_SB_LUT4_I1_I2[3]
.sym 20267 w_fetch
.sym 20270 w_rx_data[0]
.sym 20283 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20284 o_led1_SB_LUT4_I1_I2[2]
.sym 20298 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20299 r_counter_$glb_clk
.sym 20315 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20326 i_glob_clock$SB_IO_IN
.sym 20344 w_rx_data[4]
.sym 20347 w_rx_data[1]
.sym 20348 o_led1$SB_IO_OUT
.sym 20353 io_ctrl_ins.pmod_dir_state[0]
.sym 20354 w_rx_data[7]
.sym 20355 o_led0$SB_IO_OUT
.sym 20357 io_ctrl_ins.pmod_dir_state[1]
.sym 20358 o_led1_SB_LUT4_I1_I2[1]
.sym 20359 o_led1_SB_LUT4_I1_I2[3]
.sym 20361 o_led1_SB_LUT4_I1_I2[2]
.sym 20362 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 20369 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20371 i_config[1]$SB_IO_IN
.sym 20377 w_rx_data[4]
.sym 20381 w_rx_data[7]
.sym 20389 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 20393 o_led1_SB_LUT4_I1_I2[3]
.sym 20394 i_config[1]$SB_IO_IN
.sym 20395 o_led1_SB_LUT4_I1_I2[2]
.sym 20396 o_led1_SB_LUT4_I1_I2[1]
.sym 20399 io_ctrl_ins.pmod_dir_state[1]
.sym 20400 o_led1_SB_LUT4_I1_I2[3]
.sym 20401 o_led1$SB_IO_OUT
.sym 20402 o_led1_SB_LUT4_I1_I2[2]
.sym 20411 o_led0$SB_IO_OUT
.sym 20412 o_led1_SB_LUT4_I1_I2[2]
.sym 20413 io_ctrl_ins.pmod_dir_state[0]
.sym 20414 o_led1_SB_LUT4_I1_I2[3]
.sym 20417 w_rx_data[1]
.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20422 r_counter_$glb_clk
.sym 20448 o_led1$SB_IO_OUT
.sym 20468 i_config_SB_LUT4_I0_1_O[2]
.sym 20476 o_tr_vc1_b$SB_IO_OUT
.sym 20481 i_config_SB_LUT4_I0_1_O[1]
.sym 20483 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 20485 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20491 i_config_SB_LUT4_I0_1_O[3]
.sym 20504 i_config_SB_LUT4_I0_1_O[2]
.sym 20505 i_config_SB_LUT4_I0_1_O[1]
.sym 20506 i_config_SB_LUT4_I0_1_O[3]
.sym 20507 o_tr_vc1_b$SB_IO_OUT
.sym 20510 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20512 i_config_SB_LUT4_I0_1_O[1]
.sym 20544 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 20545 r_counter_$glb_clk
.sym 20571 i_config[0]$SB_IO_IN
.sym 20672 i_config[0]$SB_IO_IN
.sym 20748 w_smi_data_output[5]
.sym 20750 w_smi_data_direction
.sym 20751 $PACKER_VCC_NET
.sym 20764 w_smi_data_output[5]
.sym 20765 w_smi_data_direction
.sym 20767 $PACKER_VCC_NET
.sym 20772 tx_fifo.wr_addr[4]
.sym 20844 i_mosi$SB_IO_IN
.sym 20931 rx_fifo.wr_addr[5]
.sym 20938 rx_fifo.wr_addr[2]
.sym 20940 rx_fifo.wr_addr[8]
.sym 20942 o_miso_$_TBUF__Y_E
.sym 20989 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 20990 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 21040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 21041 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 21043 rx_fifo.rd_addr[8]
.sym 21046 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21047 i_rst_b$SB_IO_IN
.sym 21056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21058 rx_fifo.wr_addr[6]
.sym 21060 rx_fifo.wr_addr[4]
.sym 21062 rx_fifo.wr_addr[9]
.sym 21063 rx_fifo.wr_addr[1]
.sym 21064 rx_fifo.wr_addr[3]
.sym 21065 rx_fifo.mem_i.0.0_WDATA_2
.sym 21067 rx_fifo.mem_i.0.0_WDATA_3
.sym 21074 $PACKER_VCC_NET
.sym 21075 rx_fifo.wr_addr[5]
.sym 21078 rx_fifo.wr_addr[0]
.sym 21081 rx_fifo.wr_addr[2]
.sym 21083 rx_fifo.wr_addr[8]
.sym 21084 rx_fifo.wr_addr[7]
.sym 21086 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 21087 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 21088 smi_ctrl_ins.tx_reg_state[1]
.sym 21089 smi_ctrl_ins.tx_reg_state[2]
.sym 21090 smi_ctrl_ins.tx_reg_state[3]
.sym 21091 o_miso_$_TBUF__Y_E
.sym 21092 smi_ctrl_ins.tx_reg_state[0]
.sym 21093 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 21102 rx_fifo.wr_addr[2]
.sym 21103 rx_fifo.wr_addr[3]
.sym 21105 rx_fifo.wr_addr[4]
.sym 21106 rx_fifo.wr_addr[5]
.sym 21107 rx_fifo.wr_addr[6]
.sym 21108 rx_fifo.wr_addr[7]
.sym 21109 rx_fifo.wr_addr[8]
.sym 21110 rx_fifo.wr_addr[9]
.sym 21111 rx_fifo.wr_addr[1]
.sym 21112 rx_fifo.wr_addr[0]
.sym 21113 lvds_clock_$glb_clk
.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21116 rx_fifo.mem_i.0.0_WDATA_3
.sym 21120 rx_fifo.mem_i.0.0_WDATA_2
.sym 21123 $PACKER_VCC_NET
.sym 21128 rx_fifo.wr_addr[9]
.sym 21135 rx_fifo.mem_i.0.0_WDATA_3
.sym 21140 smi_ctrl_ins.swe_and_reset
.sym 21146 smi_ctrl_ins.w_fifo_push_trigger
.sym 21148 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 21149 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 21156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21158 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21160 rx_fifo.rd_addr[6]
.sym 21162 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21163 rx_fifo.rd_addr[3]
.sym 21164 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21166 rx_fifo.rd_addr[0]
.sym 21167 rx_fifo.mem_i.0.0_WDATA_1
.sym 21171 rx_fifo.mem_i.0.0_WDATA
.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21175 rx_fifo.rd_addr[9]
.sym 21176 $PACKER_VCC_NET
.sym 21177 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21181 rx_fifo.rd_addr[8]
.sym 21189 smi_ctrl_ins.w_fifo_push_trigger
.sym 21194 smi_ctrl_ins.swe_and_reset
.sym 21204 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21205 rx_fifo.rd_addr[3]
.sym 21207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21208 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21209 rx_fifo.rd_addr[6]
.sym 21210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21211 rx_fifo.rd_addr[8]
.sym 21212 rx_fifo.rd_addr[9]
.sym 21213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21214 rx_fifo.rd_addr[0]
.sym 21215 r_counter_$glb_clk
.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21217 $PACKER_VCC_NET
.sym 21221 rx_fifo.mem_i.0.0_WDATA
.sym 21225 rx_fifo.mem_i.0.0_WDATA_1
.sym 21235 rx_fifo.mem_i.0.0_WDATA_1
.sym 21238 w_smi_data_input[7]
.sym 21239 rx_fifo.rd_addr[3]
.sym 21249 rx_fifo.rd_addr[6]
.sym 21251 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21252 rx_fifo.rd_addr[0]
.sym 21260 rx_fifo.wr_addr[4]
.sym 21261 rx_fifo.wr_addr[0]
.sym 21262 $PACKER_VCC_NET
.sym 21264 rx_fifo.mem_q.0.1_WDATA_3
.sym 21267 rx_fifo.wr_addr[6]
.sym 21272 rx_fifo.wr_addr[7]
.sym 21273 rx_fifo.mem_q.0.1_WDATA_2
.sym 21275 rx_fifo.wr_addr[3]
.sym 21276 rx_fifo.wr_addr[1]
.sym 21278 rx_fifo.wr_addr[8]
.sym 21279 rx_fifo.wr_addr[5]
.sym 21282 rx_fifo.wr_addr[9]
.sym 21285 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21287 rx_fifo.wr_addr[2]
.sym 21290 spi_if_ins.spi.r_rx_done
.sym 21306 rx_fifo.wr_addr[2]
.sym 21307 rx_fifo.wr_addr[3]
.sym 21309 rx_fifo.wr_addr[4]
.sym 21310 rx_fifo.wr_addr[5]
.sym 21311 rx_fifo.wr_addr[6]
.sym 21312 rx_fifo.wr_addr[7]
.sym 21313 rx_fifo.wr_addr[8]
.sym 21314 rx_fifo.wr_addr[9]
.sym 21315 rx_fifo.wr_addr[1]
.sym 21316 rx_fifo.wr_addr[0]
.sym 21317 lvds_clock_$glb_clk
.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21320 rx_fifo.mem_q.0.1_WDATA_3
.sym 21324 rx_fifo.mem_q.0.1_WDATA_2
.sym 21327 $PACKER_VCC_NET
.sym 21334 w_smi_data_input[7]
.sym 21336 rx_fifo.wr_addr[4]
.sym 21337 rx_fifo.wr_addr[0]
.sym 21340 rx_fifo.mem_q.0.1_WDATA_3
.sym 21341 rx_fifo.mem_q.0.1_WDATA_2
.sym 21343 rx_fifo.wr_addr[6]
.sym 21344 rx_fifo.wr_addr[4]
.sym 21345 rx_fifo.wr_addr[0]
.sym 21351 o_miso_$_TBUF__Y_E
.sym 21360 rx_fifo.rd_addr[8]
.sym 21361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21362 rx_fifo.mem_q.0.1_WDATA
.sym 21365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21367 rx_fifo.rd_addr[3]
.sym 21369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21371 rx_fifo.mem_q.0.1_WDATA_1
.sym 21373 $PACKER_VCC_NET
.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21380 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21384 rx_fifo.rd_addr[9]
.sym 21387 rx_fifo.rd_addr[6]
.sym 21389 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21390 rx_fifo.rd_addr[0]
.sym 21392 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 21394 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 21395 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 21396 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 21397 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 21398 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 21399 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 21408 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21409 rx_fifo.rd_addr[3]
.sym 21411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21412 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21413 rx_fifo.rd_addr[6]
.sym 21414 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21415 rx_fifo.rd_addr[8]
.sym 21416 rx_fifo.rd_addr[9]
.sym 21417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21418 rx_fifo.rd_addr[0]
.sym 21419 r_counter_$glb_clk
.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21421 $PACKER_VCC_NET
.sym 21425 rx_fifo.mem_q.0.1_WDATA
.sym 21429 rx_fifo.mem_q.0.1_WDATA_1
.sym 21435 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21436 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 21437 rx_fifo.mem_q.0.1_WDATA_1
.sym 21438 rx_fifo.mem_q.0.1_WDATA
.sym 21446 $PACKER_VCC_NET
.sym 21448 i_rst_b$SB_IO_IN
.sym 21452 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 21455 rx_fifo.rd_addr[8]
.sym 21463 rx_fifo.wr_addr[7]
.sym 21464 rx_fifo.wr_addr[1]
.sym 21466 $PACKER_VCC_NET
.sym 21467 rx_fifo.wr_addr[5]
.sym 21469 rx_fifo.wr_addr[3]
.sym 21470 rx_fifo.wr_addr[9]
.sym 21471 rx_fifo.wr_addr[6]
.sym 21473 rx_fifo.mem_i.0.3_WDATA_2
.sym 21475 rx_fifo.wr_addr[2]
.sym 21477 rx_fifo.wr_addr[8]
.sym 21482 rx_fifo.wr_addr[4]
.sym 21483 rx_fifo.wr_addr[0]
.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21491 rx_fifo.mem_i.0.3_WDATA_3
.sym 21494 smi_ctrl_ins.soe_and_reset
.sym 21495 spi_if_ins.r_tx_data_valid
.sym 21496 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 21497 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 21498 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 21510 rx_fifo.wr_addr[2]
.sym 21511 rx_fifo.wr_addr[3]
.sym 21513 rx_fifo.wr_addr[4]
.sym 21514 rx_fifo.wr_addr[5]
.sym 21515 rx_fifo.wr_addr[6]
.sym 21516 rx_fifo.wr_addr[7]
.sym 21517 rx_fifo.wr_addr[8]
.sym 21518 rx_fifo.wr_addr[9]
.sym 21519 rx_fifo.wr_addr[1]
.sym 21520 rx_fifo.wr_addr[0]
.sym 21521 lvds_clock_$glb_clk
.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 21524 rx_fifo.mem_i.0.3_WDATA_3
.sym 21528 rx_fifo.mem_i.0.3_WDATA_2
.sym 21531 $PACKER_VCC_NET
.sym 21536 rx_fifo.wr_addr[9]
.sym 21541 rx_fifo.mem_i.0.3_WDATA_2
.sym 21542 $PACKER_VCC_NET
.sym 21547 rx_fifo.wr_addr[7]
.sym 21567 rx_fifo.rd_addr[3]
.sym 21571 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21572 rx_fifo.rd_addr[9]
.sym 21573 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21579 rx_fifo.rd_addr[6]
.sym 21580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21582 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21584 $PACKER_VCC_NET
.sym 21589 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21591 rx_fifo.mem_i.0.3_WDATA_1
.sym 21592 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21593 rx_fifo.rd_addr[8]
.sym 21594 rx_fifo.rd_addr[0]
.sym 21595 rx_fifo.mem_i.0.3_WDATA
.sym 21600 w_fetch
.sym 21601 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 21602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 21612 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 21613 rx_fifo.rd_addr[3]
.sym 21615 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 21616 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 21617 rx_fifo.rd_addr[6]
.sym 21618 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 21619 rx_fifo.rd_addr[8]
.sym 21620 rx_fifo.rd_addr[9]
.sym 21621 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 21622 rx_fifo.rd_addr[0]
.sym 21623 r_counter_$glb_clk
.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 21625 $PACKER_VCC_NET
.sym 21629 rx_fifo.mem_i.0.3_WDATA
.sym 21633 rx_fifo.mem_i.0.3_WDATA_1
.sym 21641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 21644 i_glob_clock$SB_IO_IN
.sym 21645 i_smi_soe_se$SB_IO_IN
.sym 21647 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 21649 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 21651 w_fetch
.sym 21658 io_pmod[6]$SB_IO_IN
.sym 21660 rx_fifo.rd_addr[0]
.sym 21698 int_miso
.sym 21744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 21745 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 21750 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 21754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 21758 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 21802 $PACKER_GND_NET
.sym 21807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 21843 io_pmod[0]$SB_IO_IN
.sym 21861 w_rx_data[1]
.sym 21953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 22005 o_led1$SB_IO_OUT
.sym 22010 o_led0$SB_IO_OUT
.sym 22157 o_led1$SB_IO_OUT
.sym 22361 o_tr_vc1$SB_IO_OUT
.sym 22487 o_led1$SB_IO_OUT
.sym 22505 o_led1$SB_IO_OUT
.sym 22517 int_miso
.sym 22519 o_miso_$_TBUF__Y_E
.sym 22533 o_miso_$_TBUF__Y_E
.sym 22537 int_miso
.sym 22554 i_mosi$SB_IO_IN
.sym 22561 int_miso
.sym 22565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 22576 i_ss$SB_IO_IN
.sym 22595 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 22605 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 22632 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 22663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 22664 r_counter_$glb_clk
.sym 22665 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 22666 i_sck$SB_IO_IN
.sym 22668 i_ss$SB_IO_IN
.sym 22687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 22707 i_ss$SB_IO_IN
.sym 22720 i_sck$SB_IO_IN
.sym 22729 i_sck$SB_IO_IN
.sym 22733 i_ss$SB_IO_IN
.sym 22879 w_rx_fifo_pulled_data[16]
.sym 22887 w_rx_fifo_pulled_data[17]
.sym 22934 w_rx_fifo_pulled_data[16]
.sym 22940 w_rx_fifo_pulled_data[17]
.sym 22949 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 22950 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 22980 i_ss$SB_IO_IN
.sym 22996 w_smi_data_input[7]
.sym 22998 i_rst_b$SB_IO_IN
.sym 23000 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 23002 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 23004 w_smi_data_input[7]
.sym 23005 smi_ctrl_ins.tx_reg_state[3]
.sym 23006 i_rst_b$SB_IO_IN
.sym 23010 i_ss$SB_IO_IN
.sym 23015 smi_ctrl_ins.tx_reg_state[0]
.sym 23018 smi_ctrl_ins.swe_and_reset
.sym 23019 smi_ctrl_ins.tx_reg_state[1]
.sym 23020 smi_ctrl_ins.tx_reg_state[2]
.sym 23026 i_rst_b$SB_IO_IN
.sym 23028 smi_ctrl_ins.tx_reg_state[0]
.sym 23029 smi_ctrl_ins.tx_reg_state[3]
.sym 23032 i_rst_b$SB_IO_IN
.sym 23033 w_smi_data_input[7]
.sym 23034 smi_ctrl_ins.tx_reg_state[3]
.sym 23035 smi_ctrl_ins.tx_reg_state[0]
.sym 23038 smi_ctrl_ins.tx_reg_state[2]
.sym 23040 w_smi_data_input[7]
.sym 23041 i_rst_b$SB_IO_IN
.sym 23044 w_smi_data_input[7]
.sym 23045 smi_ctrl_ins.tx_reg_state[0]
.sym 23047 i_rst_b$SB_IO_IN
.sym 23050 w_smi_data_input[7]
.sym 23052 i_rst_b$SB_IO_IN
.sym 23053 smi_ctrl_ins.tx_reg_state[1]
.sym 23056 i_ss$SB_IO_IN
.sym 23062 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 23063 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 23068 smi_ctrl_ins.tx_reg_state[1]
.sym 23069 w_smi_data_input[7]
.sym 23071 smi_ctrl_ins.tx_reg_state[2]
.sym 23073 smi_ctrl_ins.swe_and_reset
.sym 23099 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 23103 $io_pmod[3]$iobuf_i
.sym 23104 i_sck$SB_IO_IN
.sym 23108 i_sck$SB_IO_IN
.sym 23116 i_rst_b$SB_IO_IN
.sym 23129 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 23131 w_smi_data_input[7]
.sym 23132 i_smi_swe_srw$rename$0
.sym 23141 smi_ctrl_ins.swe_and_reset
.sym 23158 w_smi_data_input[7]
.sym 23185 i_rst_b$SB_IO_IN
.sym 23187 i_smi_swe_srw$rename$0
.sym 23196 smi_ctrl_ins.swe_and_reset
.sym 23197 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 23198 i_smi_swe_srw$rename$0
.sym 23199 smi_ctrl_ins.swe_and_reset
.sym 23200 spi_if_ins.spi.r2_rx_done
.sym 23201 spi_if_ins.spi.r3_rx_done
.sym 23204 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 23226 i_ss$SB_IO_IN
.sym 23246 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 23252 i_ss$SB_IO_IN
.sym 23257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 23264 i_sck$SB_IO_IN
.sym 23273 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 23318 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 23319 i_sck$SB_IO_IN
.sym 23320 i_ss$SB_IO_IN
.sym 23328 spi_if_ins.spi.SCKr[0]
.sym 23347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 23354 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23365 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 23369 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 23373 o_miso_$_TBUF__Y_E
.sym 23375 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 23376 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 23378 i_sck$SB_IO_IN
.sym 23382 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 23386 i_mosi$SB_IO_IN
.sym 23388 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 23396 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 23410 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 23415 i_mosi$SB_IO_IN
.sym 23421 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 23425 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 23432 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 23440 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 23441 o_miso_$_TBUF__Y_E
.sym 23442 i_sck$SB_IO_IN
.sym 23445 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 23451 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 23455 o_led0$SB_IO_OUT
.sym 23467 io_pmod[6]$SB_IO_IN
.sym 23468 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23478 w_load
.sym 23487 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 23489 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23491 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 23493 i_smi_soe_se$SB_IO_IN
.sym 23498 i_ss$SB_IO_IN
.sym 23499 i_rst_b$SB_IO_IN
.sym 23502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 23510 spi_if_ins.r_tx_data_valid
.sym 23511 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 23519 i_smi_soe_se$SB_IO_IN
.sym 23521 i_rst_b$SB_IO_IN
.sym 23525 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 23530 i_ss$SB_IO_IN
.sym 23532 spi_if_ins.r_tx_data_valid
.sym 23537 spi_if_ins.r_tx_data_valid
.sym 23539 i_ss$SB_IO_IN
.sym 23543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 23544 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 23545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23564 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 23565 r_counter_$glb_clk
.sym 23566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23569 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23570 w_load
.sym 23579 smi_ctrl_ins.soe_and_reset
.sym 23587 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 23592 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23594 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 23602 spi_if_ins.r_tx_byte[7]
.sym 23613 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23614 i_rst_b$SB_IO_IN
.sym 23619 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 23621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 23634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 23635 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 23637 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 23665 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 23671 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23677 i_rst_b$SB_IO_IN
.sym 23678 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 23679 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 23680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 23687 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 23688 r_counter_$glb_clk
.sym 23689 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 23703 $PACKER_VCC_NET
.sym 23705 w_load
.sym 23710 i_rst_b$SB_IO_IN
.sym 23714 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 23733 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23752 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23755 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 23762 spi_if_ins.r_tx_byte[7]
.sym 23765 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23766 spi_if_ins.r_tx_byte[7]
.sym 23767 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 23810 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23811 r_counter_$glb_clk
.sym 23839 o_led1_SB_DFFER_Q_E
.sym 23845 w_rx_data[0]
.sym 23855 io_pmod[6]$SB_IO_IN
.sym 23856 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 23874 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 23884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 23929 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 23930 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 23931 io_pmod[6]$SB_IO_IN
.sym 23933 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 23934 lvds_clock_$glb_clk
.sym 23935 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 23942 $io_pmod[0]$iobuf_i
.sym 23954 $PACKER_GND_NET
.sym 23961 o_led0$SB_IO_OUT
.sym 23967 o_led1$SB_IO_OUT
.sym 24071 lvds_clock
.sym 24111 o_led1_SB_DFFER_Q_E
.sym 24114 w_rx_data[1]
.sym 24117 w_rx_data[0]
.sym 24139 w_rx_data[1]
.sym 24172 w_rx_data[0]
.sym 24179 o_led1_SB_DFFER_Q_E
.sym 24180 r_counter_$glb_clk
.sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 24443 o_rx_h_tx_l_b$SB_IO_OUT
.sym 24596 o_led0$SB_IO_OUT
.sym 24609 o_led0$SB_IO_OUT
.sym 24659 i_sck$SB_IO_IN
.sym 25401 io_pmod[7]$SB_IO_IN
.sym 25408 io_pmod[0]$SB_IO_IN
.sym 25480 spi_if_ins.spi.r_rx_done
.sym 25496 i_smi_swe_srw$rename$0
.sym 25498 spi_if_ins.spi.r2_rx_done
.sym 25499 spi_if_ins.spi.r3_rx_done
.sym 25502 smi_ctrl_ins.swe_and_reset
.sym 25508 i_smi_swe_srw$rename$0
.sym 25511 smi_ctrl_ins.swe_and_reset
.sym 25518 spi_if_ins.spi.r_rx_done
.sym 25523 spi_if_ins.spi.r2_rx_done
.sym 25543 spi_if_ins.spi.r3_rx_done
.sym 25544 spi_if_ins.spi.r2_rx_done
.sym 25552 r_counter_$glb_clk
.sym 25554 i_smi_swe_srw$rename$0
.sym 25556 io_pmod[6]$SB_IO_IN
.sym 25655 i_sck$SB_IO_IN
.sym 25702 i_sck$SB_IO_IN
.sym 25707 r_counter_$glb_clk
.sym 25711 i_glob_clock$SB_IO_IN
.sym 25724 $io_pmod[3]$iobuf_i
.sym 25797 spi_if_ins.spi.SCKr[0]
.sym 25813 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 25822 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 25858 spi_if_ins.spi.SCKr[0]
.sym 25862 r_counter_$glb_clk
.sym 25878 i_glob_clock$SB_IO_IN
.sym 25950 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 25957 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 25963 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 25964 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 25984 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 25990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 26016 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 26017 r_counter_$glb_clk
.sym 26018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 26329 io_pmod[0]$SB_IO_IN
.sym 26347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 26410 lvds_clock
.sym 26472 lvds_clock
.sym 26488 lvds_clock
.sym 26648 o_rx_h_tx_l$SB_IO_OUT
.sym 26968 o_tr_vc1_b$SB_IO_OUT
.sym 27248 o_smi_read_req$SB_IO_OUT
.sym 27283 o_smi_read_req$SB_IO_OUT
.sym 27292 o_smi_read_req$SB_IO_OUT
.sym 27365 io_pmod[0]$SB_IO_IN
.sym 27397 i_glob_clock$SB_IO_IN
.sym 27400 $io_pmod[3]$iobuf_i
.sym 27422 $io_pmod[3]$iobuf_i
.sym 27429 smi_ctrl_ins.soe_and_reset
.sym 27444 smi_ctrl_ins.soe_and_reset
.sym 27457 lvds_clock
.sym 27459 lvds_clock
.sym 27483 lvds_clock
.sym 27485 io_pmod[0]$SB_IO_IN
.sym 27514 io_pmod[0]$SB_IO_IN
.sym 27519 $PACKER_GND_NET
.sym 27522 $PACKER_GND_NET
.sym 27529 $PACKER_GND_NET
.sym 27537 $PACKER_GND_NET
.sym 27545 o_tr_vc1$SB_IO_OUT
.sym 27547 o_tr_vc2$SB_IO_OUT
.sym 27549 $io_pmod[0]$iobuf_i
.sym 27564 $io_pmod[0]$iobuf_i
.sym 27582 o_rx_h_tx_l$SB_IO_OUT
.sym 27589 o_rx_h_tx_l$SB_IO_OUT
.sym 27605 o_tr_vc1$SB_IO_OUT
.sym 27608 o_tr_vc2$SB_IO_OUT
.sym 27621 o_tr_vc2$SB_IO_OUT
.sym 27627 o_tr_vc1$SB_IO_OUT
.sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
.sym 27634 o_tr_vc1_b$SB_IO_OUT
.sym 27641 o_tr_vc1_b$SB_IO_OUT
.sym 27646 o_rx_h_tx_l_b$SB_IO_OUT
.sym 27715 w_rx_24_fifo_data[15]
.sym 27716 w_rx_09_fifo_data[15]
.sym 27717 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27720 w_rx_09_fifo_data[13]
.sym 27721 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27732 w_rx_09_fifo_data[11]
.sym 27733 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27744 w_rx_09_fifo_data[15]
.sym 27745 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27747 w_rx_09_fifo_data[9]
.sym 27748 w_rx_24_fifo_data[9]
.sym 27749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27751 w_rx_09_fifo_data[17]
.sym 27752 w_rx_24_fifo_data[17]
.sym 27753 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27756 w_rx_09_fifo_data[6]
.sym 27757 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27760 w_rx_09_fifo_data[9]
.sym 27761 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27764 w_rx_09_fifo_data[17]
.sym 27765 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27768 w_rx_09_fifo_data[7]
.sym 27769 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27772 w_rx_09_fifo_data[5]
.sym 27773 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27775 w_rx_09_fifo_data[11]
.sym 27776 w_rx_24_fifo_data[11]
.sym 27777 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27780 w_rx_24_fifo_data[7]
.sym 27781 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27784 w_rx_24_fifo_data[15]
.sym 27785 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27788 w_rx_24_fifo_data[13]
.sym 27789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27796 w_rx_24_fifo_data[17]
.sym 27797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27800 w_rx_24_fifo_data[11]
.sym 27801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27803 w_rx_24_fifo_data[19]
.sym 27804 w_rx_09_fifo_data[19]
.sym 27805 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27808 w_rx_24_fifo_data[9]
.sym 27809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27812 w_rx_24_fifo_data[21]
.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27815 w_rx_24_fifo_data[5]
.sym 27816 w_rx_09_fifo_data[5]
.sym 27817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27819 w_rx_24_fifo_data[7]
.sym 27820 w_rx_09_fifo_data[7]
.sym 27821 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27824 w_rx_24_fifo_data[3]
.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27828 w_rx_24_fifo_data[23]
.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27832 w_rx_24_fifo_data[19]
.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27836 i_rst_b$SB_IO_IN
.sym 27837 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
.sym 27840 w_rx_24_fifo_data[5]
.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 27844 w_rx_09_fifo_data[4]
.sym 27845 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27848 w_rx_09_fifo_data[23]
.sym 27849 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27852 w_rx_09_fifo_data[21]
.sym 27853 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27855 w_rx_24_fifo_data[23]
.sym 27856 w_rx_09_fifo_data[23]
.sym 27857 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27859 w_rx_09_fifo_data[21]
.sym 27860 w_rx_24_fifo_data[21]
.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27863 w_rx_09_fifo_data[27]
.sym 27864 w_rx_24_fifo_data[27]
.sym 27865 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 27868 w_rx_09_fifo_data[19]
.sym 27869 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27872 w_rx_09_fifo_data[25]
.sym 27873 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27876 w_rx_09_fifo_data[29]
.sym 27877 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27880 w_rx_09_fifo_data[27]
.sym 27881 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27884 w_rx_09_fifo_data[0]
.sym 27885 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27888 w_rx_09_fifo_data[1]
.sym 27889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27892 w_rx_09_fifo_data[28]
.sym 27893 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27896 w_rx_09_fifo_data[2]
.sym 27897 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27900 w_rx_09_fifo_data[3]
.sym 27901 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27909 rx_fifo.wr_addr[0]
.sym 27910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 27914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 27933 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 27939 rx_fifo.wr_addr[1]
.sym 27944 rx_fifo.wr_addr[2]
.sym 27945 rx_fifo.wr_addr[1]
.sym 27948 rx_fifo.wr_addr[3]
.sym 27949 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 27952 rx_fifo.wr_addr[4]
.sym 27953 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 27956 rx_fifo.wr_addr[5]
.sym 27957 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
.sym 27960 rx_fifo.wr_addr[6]
.sym 27961 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 27964 rx_fifo.wr_addr[7]
.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 27968 rx_fifo.wr_addr[8]
.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 27972 rx_fifo.wr_addr[9]
.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 27975 rx_fifo.rd_addr_gray_wr_r[2]
.sym 27976 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
.sym 27977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 27978 rx_fifo.rd_addr_gray_wr[6]
.sym 27982 rx_fifo.rd_addr_gray_wr_r[4]
.sym 27983 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 27984 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 27985 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
.sym 27986 rx_fifo.rd_addr_gray_wr_r[5]
.sym 27987 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
.sym 27988 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 27989 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
.sym 27991 rx_fifo.rd_addr_gray_wr_r[6]
.sym 27992 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
.sym 27993 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 27996 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 27997 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 27999 rx_fifo.rd_addr_gray_wr_r[3]
.sym 28000 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
.sym 28001 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
.sym 28002 rx_fifo.rd_addr_gray_wr[4]
.sym 28008 i_rst_b$SB_IO_IN
.sym 28009 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
.sym 28010 rx_fifo.rd_addr_gray[4]
.sym 28016 rx_fifo.rd_addr_gray_wr_r[5]
.sym 28017 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 28018 rx_fifo.rd_addr_gray_wr[2]
.sym 28024 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
.sym 28025 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
.sym 28026 rx_fifo.rd_addr_gray_wr_r[6]
.sym 28027 rx_fifo.rd_addr_gray_wr_r[4]
.sym 28028 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 28029 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 28031 rx_fifo.rd_addr_gray_wr_r[8]
.sym 28032 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 28033 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28034 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28040 rx_fifo.rd_addr_gray_wr_r[7]
.sym 28041 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 28042 w_lvds_rx_09_d0
.sym 28043 w_lvds_rx_09_d1
.sym 28044 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28045 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28051 rx_fifo.rd_addr_gray_wr_r[9]
.sym 28052 rx_fifo.rd_addr_gray_wr_r[8]
.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 28054 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
.sym 28055 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
.sym 28056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
.sym 28057 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
.sym 28060 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28061 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28062 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 28063 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 28064 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28065 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 28068 rx_fifo.rd_addr_gray_wr_r[4]
.sym 28069 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 28072 w_lvds_rx_24_d1
.sym 28073 w_lvds_rx_24_d0
.sym 28076 w_lvds_rx_09_d0
.sym 28077 w_lvds_rx_09_d1
.sym 28079 w_rx_fifo_full
.sym 28080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28084 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28085 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28086 w_lvds_rx_24_d1
.sym 28087 w_lvds_rx_24_d0
.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28089 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28090 w_lvds_rx_24_d1
.sym 28091 w_lvds_rx_24_d0
.sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28096 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28097 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 28101 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28112 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28113 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28115 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28116 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28117 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28118 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28119 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28120 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28121 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28123 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28124 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28125 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28131 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 28134 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28135 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
.sym 28136 $PACKER_VCC_NET
.sym 28137 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
.sym 28138 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28139 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 28140 $PACKER_VCC_NET
.sym 28141 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 28145 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 28146 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 28147 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 28148 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 28149 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28150 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 28151 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
.sym 28152 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
.sym 28153 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28157 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
.sym 28160 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28161 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
.sym 28227 w_rx_24_fifo_data[13]
.sym 28228 w_rx_09_fifo_data[13]
.sym 28229 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28231 w_rx_09_fifo_data[14]
.sym 28232 w_rx_24_fifo_data[14]
.sym 28233 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28236 w_rx_09_fifo_data[8]
.sym 28237 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28239 w_rx_09_fifo_data[12]
.sym 28240 w_rx_24_fifo_data[12]
.sym 28241 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28244 w_rx_09_fifo_data[10]
.sym 28245 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28248 w_rx_09_fifo_data[16]
.sym 28249 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28252 w_rx_09_fifo_data[12]
.sym 28253 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28256 w_rx_09_fifo_data[14]
.sym 28257 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28260 w_rx_09_fifo_data[18]
.sym 28261 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28263 w_rx_09_fifo_data[16]
.sym 28264 w_rx_24_fifo_data[16]
.sym 28265 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28268 w_rx_09_fifo_data[24]
.sym 28269 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28271 w_rx_09_fifo_data[8]
.sym 28272 w_rx_24_fifo_data[8]
.sym 28273 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28276 w_rx_09_fifo_data[26]
.sym 28277 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28280 w_rx_09_fifo_data[20]
.sym 28281 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28284 w_rx_09_fifo_data[22]
.sym 28285 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28287 w_rx_09_fifo_data[18]
.sym 28288 w_rx_24_fifo_data[18]
.sym 28289 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28296 w_rx_24_fifo_data[16]
.sym 28297 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28299 w_rx_09_fifo_data[10]
.sym 28300 w_rx_24_fifo_data[10]
.sym 28301 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28304 w_rx_24_fifo_data[8]
.sym 28305 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28308 w_rx_24_fifo_data[6]
.sym 28309 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28312 w_rx_24_fifo_data[12]
.sym 28313 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28316 w_rx_24_fifo_data[14]
.sym 28317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28320 w_rx_24_fifo_data[10]
.sym 28321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28323 w_rx_24_fifo_data[4]
.sym 28324 w_rx_09_fifo_data[4]
.sym 28325 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28327 w_rx_09_fifo_data[26]
.sym 28328 w_rx_24_fifo_data[26]
.sym 28329 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28332 w_rx_24_fifo_data[4]
.sym 28333 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28335 w_rx_24_fifo_data[25]
.sym 28336 w_rx_09_fifo_data[25]
.sym 28337 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28339 w_rx_09_fifo_data[6]
.sym 28340 w_rx_24_fifo_data[6]
.sym 28341 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28344 w_rx_24_fifo_data[25]
.sym 28345 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28348 w_rx_24_fifo_data[2]
.sym 28349 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28352 w_rx_24_fifo_data[18]
.sym 28353 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28356 w_rx_24_fifo_data[27]
.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28359 w_rx_09_fifo_data[22]
.sym 28360 w_rx_24_fifo_data[22]
.sym 28361 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28364 w_rx_24_fifo_data[20]
.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28367 w_rx_24_fifo_data[20]
.sym 28368 w_rx_09_fifo_data[20]
.sym 28369 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28372 w_rx_24_fifo_data[1]
.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28376 w_rx_24_fifo_data[29]
.sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28380 w_rx_24_fifo_data[0]
.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28384 w_rx_24_fifo_data[28]
.sym 28385 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28387 w_rx_24_fifo_data[3]
.sym 28388 w_rx_09_fifo_data[3]
.sym 28389 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28395 w_rx_24_fifo_data[30]
.sym 28396 w_rx_09_fifo_data[30]
.sym 28397 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28398 w_rx_fifo_pulled_data[20]
.sym 28405 rx_fifo.mem_i.0.1_WDATA
.sym 28407 w_rx_24_fifo_data[31]
.sym 28408 w_rx_09_fifo_data[31]
.sym 28409 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28411 w_rx_24_fifo_data[29]
.sym 28412 w_rx_09_fifo_data[29]
.sym 28413 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28415 w_rx_09_fifo_data[2]
.sym 28416 w_rx_24_fifo_data[2]
.sym 28417 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28418 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28422 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28427 w_rx_09_fifo_data[1]
.sym 28428 w_rx_24_fifo_data[1]
.sym 28429 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28432 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28433 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28434 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 28438 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 28442 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 28448 i_rst_b$SB_IO_IN
.sym 28449 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 28451 rx_fifo.wr_addr[0]
.sym 28456 rx_fifo.wr_addr[1]
.sym 28457 rx_fifo.wr_addr[0]
.sym 28460 rx_fifo.wr_addr[2]
.sym 28461 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28464 rx_fifo.wr_addr[3]
.sym 28465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28468 rx_fifo.wr_addr[4]
.sym 28469 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28472 rx_fifo.wr_addr[5]
.sym 28473 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28476 rx_fifo.wr_addr[6]
.sym 28477 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28480 rx_fifo.wr_addr[7]
.sym 28481 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 28484 rx_fifo.wr_addr[8]
.sym 28485 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 28488 rx_fifo.wr_addr[9]
.sym 28489 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 28491 rx_fifo.rd_addr_gray_wr_r[3]
.sym 28492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28495 rx_fifo.rd_addr_gray_wr_r[2]
.sym 28496 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28500 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 28501 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 28504 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28505 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28507 rx_fifo.rd_addr_gray_wr_r[6]
.sym 28508 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28509 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 28510 rx_fifo.wr_addr[9]
.sym 28514 rx_fifo.wr_addr[2]
.sym 28515 rx_fifo.rd_addr_gray_wr_r[1]
.sym 28516 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
.sym 28518 rx_fifo.rd_addr_gray_wr_r[1]
.sym 28519 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 28520 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 28522 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28526 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 28530 rx_fifo.rd_addr_gray_wr_r[8]
.sym 28531 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 28532 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28533 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 28534 rx_fifo.rd_addr_gray_wr_r[9]
.sym 28535 rx_fifo.wr_addr[1]
.sym 28536 rx_fifo.rd_addr_gray_wr_r[0]
.sym 28537 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28538 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 28542 rx_fifo.rd_addr_gray_wr_r[9]
.sym 28543 rx_fifo.rd_addr_gray_wr_r[0]
.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28547 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 28548 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 28549 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 28550 w_rx_fifo_full
.sym 28551 rx_fifo.rd_addr_gray_wr_r[9]
.sym 28552 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
.sym 28553 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28555 w_rx_24_fifo_data[0]
.sym 28556 w_rx_09_fifo_data[0]
.sym 28557 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 28559 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 28560 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 28562 w_rx_data[0]
.sym 28568 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 28569 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 28572 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28573 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28575 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28576 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28577 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 28578 w_lvds_rx_09_d0
.sym 28579 w_lvds_rx_09_d1
.sym 28580 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28584 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 28585 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28590 rx_fifo.rd_addr_gray_wr_r[7]
.sym 28591 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 28592 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 28593 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 28594 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 28595 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 28596 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 28597 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 28608 rx_fifo.rd_addr_gray_wr_r[3]
.sym 28609 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 28614 w_lvds_rx_09_d1
.sym 28615 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 28616 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28617 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28621 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 28622 w_lvds_rx_09_d0
.sym 28643 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 28646 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28647 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
.sym 28648 $PACKER_VCC_NET
.sym 28649 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
.sym 28650 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28651 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 28652 $PACKER_VCC_NET
.sym 28653 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3
.sym 28657 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 28660 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28661 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28662 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 28663 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 28664 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
.sym 28665 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28666 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 28667 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28668 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
.sym 28669 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28673 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 28676 w_rx_fifo_full
.sym 28677 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 28692 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
.sym 28693 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28738 w_rx_fifo_pulled_data[14]
.sym 28742 w_rx_fifo_pulled_data[12]
.sym 28746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 28747 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 28748 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 28749 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
.sym 28750 w_rx_fifo_pulled_data[13]
.sym 28754 w_rx_fifo_pulled_data[9]
.sym 28758 w_rx_fifo_pulled_data[8]
.sym 28762 w_rx_fifo_pulled_data[11]
.sym 28766 w_rx_fifo_pulled_data[15]
.sym 28770 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 28776 i_rst_b$SB_IO_IN
.sym 28777 w_tx_fifo_pull
.sym 28780 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
.sym 28781 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
.sym 28786 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 28790 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 28794 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 28802 tx_fifo.rd_addr_gray_wr[8]
.sym 28806 tx_fifo.rd_addr_gray_wr[0]
.sym 28810 tx_fifo.rd_addr[9]
.sym 28814 tx_fifo.rd_addr_gray[0]
.sym 28818 tx_fifo.rd_addr_gray[8]
.sym 28822 tx_fifo.rd_addr_gray_wr[9]
.sym 28826 tx_fifo.rd_addr_gray[1]
.sym 28830 tx_fifo.rd_addr_gray_wr[1]
.sym 28834 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 28835 smi_ctrl_ins.int_cnt_rx[4]
.sym 28836 smi_ctrl_ins.int_cnt_rx[3]
.sym 28837 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 28838 w_rx_fifo_pulled_data[27]
.sym 28842 w_rx_fifo_pulled_data[25]
.sym 28847 w_rx_24_fifo_data[24]
.sym 28848 w_rx_09_fifo_data[24]
.sym 28849 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28850 w_rx_fifo_pulled_data[10]
.sym 28854 w_rx_fifo_pulled_data[24]
.sym 28858 w_rx_fifo_pulled_data[26]
.sym 28862 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 28863 smi_ctrl_ins.int_cnt_rx[4]
.sym 28864 smi_ctrl_ins.int_cnt_rx[3]
.sym 28865 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 28872 w_rx_24_fifo_data[22]
.sym 28873 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28888 w_rx_24_fifo_data[24]
.sym 28889 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28892 w_rx_24_fifo_data[26]
.sym 28893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 28898 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 28903 w_rx_24_fifo_data[28]
.sym 28904 w_rx_09_fifo_data[28]
.sym 28905 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28906 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 28910 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 28914 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 28918 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 28925 rx_fifo.rd_addr[3]
.sym 28929 rx_fifo.rd_addr[0]
.sym 28930 w_rx_fifo_pulled_data[3]
.sym 28936 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 28937 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 28938 w_rx_fifo_pulled_data[1]
.sym 28946 w_rx_fifo_pulled_data[0]
.sym 28950 w_rx_fifo_pulled_data[2]
.sym 28954 w_rx_fifo_pulled_data[21]
.sym 28960 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 28961 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 28962 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 28966 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 28970 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 28974 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 28975 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 28976 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 28977 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
.sym 28978 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 28979 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 28980 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 28982 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 28986 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 28987 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 28988 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 28989 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 28991 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 28993 rx_fifo.rd_addr[3]
.sym 28996 rx_fifo.rd_addr[8]
.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
.sym 28998 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 28999 rx_fifo.rd_addr[6]
.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 29001 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 29003 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
.sym 29004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
.sym 29005 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
.sym 29006 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 29007 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 29008 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 29009 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
.sym 29010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 29011 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 29012 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
.sym 29013 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
.sym 29014 rx_fifo.rd_addr_gray[6]
.sym 29020 rx_fifo.rd_addr[6]
.sym 29021 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 29022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 29023 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 29024 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29025 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 29026 rx_fifo.rd_addr_gray[8]
.sym 29030 rx_fifo.rd_addr_gray_wr[8]
.sym 29034 rx_fifo.rd_addr_gray_wr[9]
.sym 29038 rx_fifo.rd_addr_gray[2]
.sym 29043 rx_fifo.rd_addr_gray_wr_r[2]
.sym 29044 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 29045 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29046 rx_fifo.rd_addr[9]
.sym 29050 rx_fifo.rd_addr_gray_wr[5]
.sym 29054 rx_fifo.rd_addr_gray[5]
.sym 29065 w_lvds_rx_24_d0
.sym 29066 rx_fifo.rd_addr_gray_wr_r[8]
.sym 29067 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29071 w_lvds_rx_24_d1
.sym 29072 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 29073 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 29090 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 29094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 29098 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 29104 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
.sym 29105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29106 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 29112 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 29113 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29121 rx_fifo.wr_addr[1]
.sym 29122 rx_fifo.wr_addr_gray[7]
.sym 29126 rx_fifo.wr_addr_gray_rd[6]
.sym 29130 rx_fifo.wr_addr_gray[4]
.sym 29138 rx_fifo.wr_addr_gray_rd[4]
.sym 29146 rx_fifo.wr_addr_gray[6]
.sym 29150 rx_fifo.wr_addr_gray_rd[7]
.sym 29166 rx_fifo.rd_addr_gray[3]
.sym 29174 rx_fifo.rd_addr_gray_wr[3]
.sym 29220 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29221 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29224 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 29225 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29226 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29232 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 29233 tx_fifo.rd_addr[2]
.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29241 tx_fifo.rd_addr[0]
.sym 29242 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29251 tx_fifo.rd_addr[0]
.sym 29256 tx_fifo.rd_addr[1]
.sym 29257 tx_fifo.rd_addr[0]
.sym 29260 tx_fifo.rd_addr[2]
.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 29264 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 29265 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 29268 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 29272 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 29273 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 29276 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 29277 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
.sym 29280 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 29284 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 29285 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29288 tx_fifo.rd_addr[9]
.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29292 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29293 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29294 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 29295 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 29296 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 29297 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
.sym 29299 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 29300 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 29301 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 29302 tx_fifo.rd_addr_gray[2]
.sym 29306 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
.sym 29307 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
.sym 29308 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
.sym 29309 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
.sym 29310 tx_fifo.rd_addr_gray[4]
.sym 29314 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 29321 tx_fifo.rd_addr[1]
.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 29323 smi_ctrl_ins.int_cnt_rx[4]
.sym 29324 smi_ctrl_ins.int_cnt_rx[3]
.sym 29325 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 29328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29329 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 29332 smi_ctrl_ins.int_cnt_rx[4]
.sym 29333 smi_ctrl_ins.int_cnt_rx[3]
.sym 29334 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29339 tx_fifo.rd_addr[9]
.sym 29340 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
.sym 29341 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 29342 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29346 w_rx_fifo_pulled_data[6]
.sym 29350 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 29351 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 29352 smi_ctrl_ins.int_cnt_rx[4]
.sym 29353 smi_ctrl_ins.int_cnt_rx[3]
.sym 29354 w_rx_fifo_pulled_data[19]
.sym 29358 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 29359 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 29360 smi_ctrl_ins.int_cnt_rx[4]
.sym 29361 smi_ctrl_ins.int_cnt_rx[3]
.sym 29362 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 29363 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 29364 smi_ctrl_ins.int_cnt_rx[4]
.sym 29365 smi_ctrl_ins.int_cnt_rx[3]
.sym 29366 w_rx_fifo_pulled_data[18]
.sym 29370 w_rx_fifo_pulled_data[4]
.sym 29374 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 29375 smi_ctrl_ins.int_cnt_rx[4]
.sym 29376 smi_ctrl_ins.int_cnt_rx[3]
.sym 29377 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 29388 smi_ctrl_ins.int_cnt_rx[4]
.sym 29389 smi_ctrl_ins.int_cnt_rx[3]
.sym 29401 smi_ctrl_ins.int_cnt_rx[3]
.sym 29411 rx_fifo.rd_addr[0]
.sym 29416 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29417 rx_fifo.rd_addr[0]
.sym 29420 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 29421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 29424 rx_fifo.rd_addr[3]
.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 29428 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
.sym 29429 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 29432 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 29436 rx_fifo.rd_addr[6]
.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 29440 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 29444 rx_fifo.rd_addr[8]
.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29448 rx_fifo.rd_addr[9]
.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29450 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 29460 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 29461 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 29472 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29474 rx_fifo.wr_addr_gray[3]
.sym 29479 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 29480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
.sym 29481 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
.sym 29484 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29485 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 29486 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29488 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 29490 rx_fifo.wr_addr_gray_rd[2]
.sym 29494 rx_fifo.wr_addr_gray_rd[3]
.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 29499 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 29502 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 29508 i_rst_b$SB_IO_IN
.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29512 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29513 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 29514 rx_fifo.wr_addr_gray_rd[5]
.sym 29518 rx_fifo.wr_addr_gray_rd[9]
.sym 29522 rx_fifo.empty_o_SB_LUT4_I0_O[0]
.sym 29523 rx_fifo.empty_o_SB_LUT4_I0_O[1]
.sym 29524 rx_fifo.empty_o_SB_LUT4_I0_O[2]
.sym 29525 rx_fifo.empty_o_SB_LUT4_I0_O[3]
.sym 29526 w_rx_fifo_empty
.sym 29527 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
.sym 29528 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
.sym 29529 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
.sym 29530 rx_fifo.wr_addr_gray_rd[1]
.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29535 rx_fifo.rd_addr[9]
.sym 29536 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
.sym 29537 rx_fifo.rd_addr[8]
.sym 29538 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 29558 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 29562 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 29566 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 29570 rx_fifo.rd_addr_gray_wr[7]
.sym 29574 rx_fifo.rd_addr_gray_wr[0]
.sym 29582 rx_fifo.rd_addr_gray[0]
.sym 29586 rx_fifo.rd_addr_gray[1]
.sym 29590 rx_fifo.rd_addr_gray_wr[1]
.sym 29598 rx_fifo.rd_addr_gray[7]
.sym 29602 rx_fifo.wr_addr_gray[8]
.sym 29606 rx_fifo.wr_addr_gray[0]
.sym 29610 rx_fifo.wr_addr_gray_rd[8]
.sym 29614 rx_fifo.wr_addr_gray_rd[0]
.sym 29618 rx_fifo.wr_addr_gray[2]
.sym 29622 rx_fifo.wr_addr_gray[5]
.sym 29630 rx_fifo.wr_addr_gray[1]
.sym 29645 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
.sym 29730 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 29734 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 29746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 29747 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 29748 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 29749 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 29750 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29756 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 29761 w_smi_data_output[2]
.sym 29762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
.sym 29763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 29764 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 29765 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
.sym 29767 tx_fifo.rd_addr[2]
.sym 29768 tx_fifo.rd_addr[1]
.sym 29769 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 29771 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 29772 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 29773 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 29779 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 29782 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
.sym 29784 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
.sym 29785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 29787 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
.sym 29788 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 29789 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
.sym 29790 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
.sym 29791 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 29792 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 29793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 29794 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 29795 tx_fifo.empty_o_SB_LUT4_I1_O[1]
.sym 29796 tx_fifo.empty_o_SB_LUT4_I1_O[2]
.sym 29797 tx_fifo.empty_o_SB_LUT4_I1_O[3]
.sym 29798 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 29799 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 29800 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
.sym 29801 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 29802 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
.sym 29803 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 29804 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
.sym 29805 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 29806 w_tx_fifo_pull
.sym 29807 w_tx_fifo_empty
.sym 29808 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29809 tx_fifo.rd_addr[9]
.sym 29812 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
.sym 29813 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29814 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 29815 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 29816 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 29817 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 29819 w_tx_fifo_pull
.sym 29820 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29821 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29823 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 29824 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 29825 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 29826 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 29827 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 29828 smi_ctrl_ins.int_cnt_rx[4]
.sym 29829 smi_ctrl_ins.int_cnt_rx[3]
.sym 29832 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 29833 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 29834 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29835 tx_fifo.rd_addr[1]
.sym 29836 tx_fifo.empty_o_SB_LUT4_I1_O[0]
.sym 29837 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29840 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 29841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 29844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 29845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 29848 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 29849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 29852 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 29853 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 29856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 29857 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 29858 tx_fifo.wr_addr_gray[7]
.sym 29862 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 29863 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 29864 smi_ctrl_ins.int_cnt_rx[4]
.sym 29865 smi_ctrl_ins.int_cnt_rx[3]
.sym 29866 tx_fifo.wr_addr_gray[8]
.sym 29870 tx_fifo.wr_addr_gray_rd[8]
.sym 29874 tx_fifo.wr_addr_gray_rd[7]
.sym 29878 tx_fifo.wr_addr_gray_rd[5]
.sym 29882 tx_fifo.wr_addr_gray[1]
.sym 29886 tx_fifo.wr_addr_gray[5]
.sym 29894 tx_fifo.wr_addr_gray[0]
.sym 29902 tx_fifo.wr_addr_gray_rd[0]
.sym 29906 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 29907 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 29908 smi_ctrl_ins.int_cnt_rx[4]
.sym 29909 smi_ctrl_ins.int_cnt_rx[3]
.sym 29915 i_rst_b$SB_IO_IN
.sym 29916 smi_ctrl_ins.int_cnt_rx[4]
.sym 29917 smi_ctrl_ins.int_cnt_rx[3]
.sym 29918 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 29919 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 29920 smi_ctrl_ins.int_cnt_rx[4]
.sym 29921 smi_ctrl_ins.int_cnt_rx[3]
.sym 29942 w_rx_fifo_pulled_data[22]
.sym 29946 w_rx_fifo_pulled_data[23]
.sym 29954 w_rx_data[2]
.sym 29960 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 29970 w_rx_data[0]
.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 29986 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 29987 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 29988 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 29989 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 30006 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 30007 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
.sym 30008 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
.sym 30009 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
.sym 30015 rx_fifo.rd_addr[3]
.sym 30016 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
.sym 30017 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 30019 w_ioc[1]
.sym 30020 w_ioc[0]
.sym 30021 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 30022 w_rx_data[1]
.sym 30026 w_rx_data[0]
.sym 30030 w_cs[0]
.sym 30031 w_load
.sym 30032 w_fetch
.sym 30033 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 30034 w_rx_data[2]
.sym 30039 w_ioc[1]
.sym 30040 w_ioc[0]
.sym 30041 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 30042 w_rx_data[4]
.sym 30050 w_tx_data_smi[1]
.sym 30051 w_tx_data_io[1]
.sym 30052 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 30053 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30056 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
.sym 30057 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30060 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 30061 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30065 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
.sym 30068 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 30069 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30071 w_cs[0]
.sym 30072 w_fetch
.sym 30073 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
.sym 30074 w_ioc[1]
.sym 30075 w_ioc[0]
.sym 30076 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 30077 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30079 w_ioc[1]
.sym 30080 w_ioc[0]
.sym 30081 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 30082 w_tx_fifo_full
.sym 30090 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 30101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 30102 w_rx_fifo_empty
.sym 30126 i_rst_b$SB_IO_IN
.sym 30127 w_cs[1]
.sym 30128 w_load
.sym 30129 w_fetch
.sym 30131 w_ioc[1]
.sym 30132 w_ioc[0]
.sym 30133 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30134 w_cs[1]
.sym 30135 w_load
.sym 30136 w_fetch
.sym 30137 o_led0_SB_LUT4_I1_O[1]
.sym 30143 io_pmod[7]$SB_IO_IN
.sym 30144 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 30145 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30146 w_rx_data[0]
.sym 30155 w_ioc[0]
.sym 30156 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 30157 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30158 w_rx_data[3]
.sym 30162 w_rx_data[2]
.sym 30166 o_shdn_rx_lna$SB_IO_OUT
.sym 30167 w_ioc[0]
.sym 30168 io_ctrl_ins.o_pmod[1]
.sym 30169 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30170 o_shdn_tx_lna$SB_IO_OUT
.sym 30171 w_ioc[0]
.sym 30172 io_ctrl_ins.o_pmod[2]
.sym 30173 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30174 w_rx_data[1]
.sym 30182 w_rx_data[0]
.sym 30190 w_rx_data[4]
.sym 30194 w_rx_data[3]
.sym 30202 w_rx_data[1]
.sym 30206 w_rx_data[2]
.sym 30242 tx_fifo.wr_addr_gray[2]
.sym 30248 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30249 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 30253 w_smi_data_direction
.sym 30254 tx_fifo.wr_addr_gray[3]
.sym 30258 tx_fifo.wr_addr_gray_rd[3]
.sym 30262 tx_fifo.wr_addr_gray_rd[2]
.sym 30266 tx_fifo.wr_addr_gray[6]
.sym 30270 tx_fifo.wr_addr_gray_rd[6]
.sym 30275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30280 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30281 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30282 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 30283 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 30284 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 30285 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 30288 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 30289 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 30291 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 30296 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 30297 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 30298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 30299 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 30300 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 30301 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
.sym 30305 w_tx_fifo_empty
.sym 30310 tx_fifo.wr_addr_gray_rd[1]
.sym 30314 tx_fifo.wr_addr[9]
.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 30325 i_rst_b$SB_IO_IN
.sym 30326 tx_fifo.wr_addr_gray[4]
.sym 30330 tx_fifo.wr_addr_gray_rd[4]
.sym 30334 tx_fifo.wr_addr_gray_rd[9]
.sym 30338 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 30339 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 30340 smi_ctrl_ins.int_cnt_rx[4]
.sym 30341 smi_ctrl_ins.int_cnt_rx[3]
.sym 30346 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
.sym 30350 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 30351 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 30352 smi_ctrl_ins.int_cnt_rx[4]
.sym 30353 smi_ctrl_ins.int_cnt_rx[3]
.sym 30354 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
.sym 30358 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
.sym 30362 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
.sym 30366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 30367 tx_fifo.wr_addr[1]
.sym 30368 tx_fifo.rd_addr_gray_wr_r[0]
.sym 30369 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 30372 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30373 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 30374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30378 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 30379 tx_fifo.rd_addr_gray_wr_r[1]
.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30382 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30387 w_tx_fifo_full
.sym 30388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 30389 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 30391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
.sym 30392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
.sym 30393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
.sym 30396 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30397 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30401 tx_fifo.wr_addr[1]
.sym 30404 smi_ctrl_ins.int_cnt_rx[4]
.sym 30405 smi_ctrl_ins.int_cnt_rx[3]
.sym 30412 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 30413 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 30422 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 30423 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 30424 smi_ctrl_ins.int_cnt_rx[4]
.sym 30425 smi_ctrl_ins.int_cnt_rx[3]
.sym 30430 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 30431 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 30432 smi_ctrl_ins.int_cnt_rx[4]
.sym 30433 smi_ctrl_ins.int_cnt_rx[3]
.sym 30434 w_rx_fifo_pulled_data[30]
.sym 30438 w_rx_fifo_pulled_data[31]
.sym 30446 w_rx_fifo_pulled_data[28]
.sym 30450 w_rx_fifo_pulled_data[29]
.sym 30466 spi_if_ins.w_rx_data[0]
.sym 30478 spi_if_ins.w_rx_data[5]
.sym 30486 spi_if_ins.w_rx_data[2]
.sym 30493 i_rst_b$SB_IO_IN
.sym 30502 w_rx_data[7]
.sym 30509 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 30510 w_rx_data[6]
.sym 30514 w_rx_data[3]
.sym 30518 w_rx_data[5]
.sym 30532 spi_if_ins.w_rx_data[6]
.sym 30533 spi_if_ins.w_rx_data[5]
.sym 30534 w_cs[3]
.sym 30535 w_cs[2]
.sym 30536 w_cs[1]
.sym 30537 w_cs[0]
.sym 30540 spi_if_ins.w_rx_data[6]
.sym 30541 spi_if_ins.w_rx_data[5]
.sym 30544 spi_if_ins.w_rx_data[6]
.sym 30545 spi_if_ins.w_rx_data[5]
.sym 30549 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 30552 spi_if_ins.w_rx_data[6]
.sym 30553 spi_if_ins.w_rx_data[5]
.sym 30562 w_tx_data_smi[2]
.sym 30563 w_tx_data_io[2]
.sym 30564 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 30565 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30566 w_cs[3]
.sym 30567 w_cs[2]
.sym 30568 w_cs[1]
.sym 30569 w_cs[0]
.sym 30572 i_rst_b$SB_IO_IN
.sym 30573 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 30574 w_cs[3]
.sym 30575 w_cs[2]
.sym 30576 w_cs[1]
.sym 30577 w_cs[0]
.sym 30578 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
.sym 30579 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30580 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 30581 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
.sym 30582 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
.sym 30583 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30584 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 30585 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
.sym 30587 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 30588 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30589 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 30590 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
.sym 30591 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
.sym 30592 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
.sym 30593 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30596 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 30597 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 30601 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30604 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30605 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30606 w_cs[2]
.sym 30607 w_load
.sym 30608 w_fetch
.sym 30609 o_led1_SB_LUT4_I1_I2[3]
.sym 30612 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 30613 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30616 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 30617 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30618 w_cs[2]
.sym 30619 w_ioc[1]
.sym 30620 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 30621 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30627 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 30628 o_led0_SB_LUT4_I1_O[1]
.sym 30629 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
.sym 30630 w_cs[2]
.sym 30631 w_load
.sym 30632 w_fetch
.sym 30633 o_led1_SB_LUT4_I1_I2[2]
.sym 30635 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
.sym 30636 o_led1_SB_LUT4_I1_I2[2]
.sym 30637 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
.sym 30639 w_ioc[0]
.sym 30640 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30641 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30642 w_ioc[1]
.sym 30643 w_ioc[0]
.sym 30644 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 30645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30647 w_ioc[1]
.sym 30648 w_ioc[0]
.sym 30649 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
.sym 30650 w_cs[1]
.sym 30651 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 30652 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 30653 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30656 w_ioc[1]
.sym 30657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 30658 w_ioc[0]
.sym 30659 io_ctrl_ins.o_pmod[0]
.sym 30660 io_ctrl_ins.mixer_en_state
.sym 30661 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30662 o_tr_vc2$SB_IO_OUT
.sym 30663 w_ioc[0]
.sym 30664 io_ctrl_ins.o_pmod[3]
.sym 30665 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 30670 o_led1_SB_LUT4_I1_O[0]
.sym 30671 o_led0_SB_LUT4_I1_O[1]
.sym 30672 o_led1_SB_LUT4_I1_O[2]
.sym 30673 o_led1_SB_LUT4_I1_O[3]
.sym 30674 i_config[0]$SB_IO_IN
.sym 30675 o_led1_SB_LUT4_I1_I2[3]
.sym 30676 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
.sym 30677 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
.sym 30678 io_ctrl_ins.pmod_dir_state[3]
.sym 30679 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 30680 o_led1_SB_LUT4_I1_I2[2]
.sym 30681 o_led0_SB_LUT4_I1_O[1]
.sym 30684 o_led1_SB_LUT4_I1_I2[3]
.sym 30685 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
.sym 30686 o_led0_SB_LUT4_I1_O[0]
.sym 30687 o_led0_SB_LUT4_I1_O[1]
.sym 30688 o_led0_SB_LUT4_I1_O[2]
.sym 30689 o_led0_SB_LUT4_I1_O[3]
.sym 30691 o_led0_SB_LUT4_I1_O[0]
.sym 30692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 30693 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 30696 o_led0_SB_LUT4_I1_O[0]
.sym 30697 o_led1_SB_LUT4_I1_O[0]
.sym 30698 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 30699 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 30700 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 30701 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 30702 w_rx_data[0]
.sym 30707 i_rst_b$SB_IO_IN
.sym 30708 o_led1_SB_LUT4_I1_O[0]
.sym 30709 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
.sym 30718 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 30719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
.sym 30720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 30721 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 30733 r_counter
.sym 30755 tx_fifo.wr_addr[0]
.sym 30760 tx_fifo.wr_addr[1]
.sym 30761 tx_fifo.wr_addr[0]
.sym 30764 tx_fifo.wr_addr[2]
.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 30768 tx_fifo.wr_addr[3]
.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 30772 tx_fifo.wr_addr[4]
.sym 30773 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 30776 tx_fifo.wr_addr[5]
.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
.sym 30780 tx_fifo.wr_addr[6]
.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
.sym 30784 tx_fifo.wr_addr[7]
.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 30788 tx_fifo.wr_addr[8]
.sym 30789 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 30792 tx_fifo.wr_addr[9]
.sym 30793 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 30796 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30798 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
.sym 30808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 30810 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 30823 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 30824 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 30832 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30833 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
.sym 30838 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 30839 tx_fifo.rd_addr_gray_wr_r[0]
.sym 30840 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 30841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 30846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 30847 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30849 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 30850 tx_fifo.rd_addr_gray_wr[6]
.sym 30854 tx_fifo.rd_addr_gray_wr[7]
.sym 30860 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30862 tx_fifo.rd_addr_gray[5]
.sym 30866 tx_fifo.rd_addr_gray[7]
.sym 30870 tx_fifo.rd_addr_gray[3]
.sym 30874 tx_fifo.rd_addr_gray[6]
.sym 30878 tx_fifo.rd_addr_gray_wr[3]
.sym 30883 tx_fifo.wr_addr[2]
.sym 30884 tx_fifo.rd_addr_gray_wr_r[1]
.sym 30885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 30895 w_tx_fifo_full
.sym 30896 w_rx_fifo_empty
.sym 30897 w_smi_data_direction
.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 30899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 30901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 30902 tx_fifo.rd_addr_gray_wr[5]
.sym 30912 i_rst_b$SB_IO_IN
.sym 30913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 30914 smi_ctrl_ins.r_fifo_pull
.sym 30919 w_rx_fifo_empty
.sym 30920 smi_ctrl_ins.r_fifo_pull_1
.sym 30921 smi_ctrl_ins.r_fifo_pull
.sym 30922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
.sym 30923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
.sym 30924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
.sym 30925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
.sym 30927 w_tx_fifo_full
.sym 30928 smi_ctrl_ins.r_fifo_push
.sym 30929 smi_ctrl_ins.r_fifo_push_1
.sym 30930 smi_ctrl_ins.w_fifo_pull_trigger
.sym 30938 smi_ctrl_ins.r_fifo_push
.sym 30942 smi_ctrl_ins.w_fifo_push_trigger
.sym 30946 spi_if_ins.spi.r_rx_byte[1]
.sym 30954 spi_if_ins.spi.r_rx_byte[2]
.sym 30958 spi_if_ins.spi.r_rx_byte[4]
.sym 30966 spi_if_ins.spi.r_rx_byte[5]
.sym 30970 spi_if_ins.spi.r_rx_byte[6]
.sym 30974 spi_if_ins.spi.r_rx_byte[0]
.sym 30979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 30980 spi_if_ins.state_if[1]
.sym 30981 spi_if_ins.state_if[0]
.sym 30982 spi_if_ins.spi.r_rx_byte[3]
.sym 30986 spi_if_ins.spi.r_rx_byte[7]
.sym 30995 i_rst_b$SB_IO_IN
.sym 30996 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 30997 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 30999 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 31001 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 31003 i_rst_b$SB_IO_IN
.sym 31004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 31007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31008 spi_if_ins.state_if[1]
.sym 31009 spi_if_ins.state_if[0]
.sym 31011 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 31012 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31013 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 31014 spi_if_ins.w_rx_data[4]
.sym 31018 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 31024 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31025 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 31026 i_rst_b$SB_IO_IN
.sym 31027 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31028 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 31030 spi_if_ins.w_rx_data[3]
.sym 31034 spi_if_ins.w_rx_data[1]
.sym 31038 spi_if_ins.w_rx_data[6]
.sym 31043 w_ioc[4]
.sym 31044 w_ioc[3]
.sym 31045 w_ioc[2]
.sym 31046 spi_if_ins.w_rx_data[1]
.sym 31050 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 31054 spi_if_ins.w_rx_data[4]
.sym 31058 spi_if_ins.w_rx_data[3]
.sym 31062 spi_if_ins.w_rx_data[0]
.sym 31066 spi_if_ins.w_rx_data[2]
.sym 31071 w_ioc[4]
.sym 31072 w_ioc[3]
.sym 31073 w_ioc[2]
.sym 31078 r_tx_data[2]
.sym 31082 r_tx_data[1]
.sym 31086 w_cs[3]
.sym 31087 w_cs[2]
.sym 31088 w_cs[1]
.sym 31089 w_cs[0]
.sym 31090 r_tx_data[0]
.sym 31094 r_tx_data[7]
.sym 31098 w_cs[3]
.sym 31099 w_cs[2]
.sym 31100 w_cs[1]
.sym 31101 w_cs[0]
.sym 31102 r_tx_data[6]
.sym 31106 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 31107 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 31108 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31111 w_tx_data_io[7]
.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31113 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 31114 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 31115 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 31116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31117 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31120 i_rst_b$SB_IO_IN
.sym 31121 w_fetch
.sym 31123 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
.sym 31124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31125 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
.sym 31127 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 31128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31129 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 31130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 31131 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 31132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31135 w_tx_data_io[5]
.sym 31136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31137 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
.sym 31138 w_rx_data[5]
.sym 31143 w_ioc[1]
.sym 31144 w_ioc[0]
.sym 31145 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 31146 w_rx_data[6]
.sym 31151 w_ioc[1]
.sym 31152 w_ioc[0]
.sym 31153 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
.sym 31154 w_cs[1]
.sym 31155 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
.sym 31156 o_led1_SB_LUT4_I1_I2[3]
.sym 31157 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 31162 w_rx_data[3]
.sym 31166 w_rx_data[2]
.sym 31172 w_ioc[0]
.sym 31173 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
.sym 31174 o_rx_h_tx_l$SB_IO_OUT
.sym 31175 io_ctrl_ins.pmod_dir_state[7]
.sym 31176 o_led1_SB_LUT4_I1_I2[2]
.sym 31177 i_config_SB_LUT4_I0_1_O[1]
.sym 31179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 31180 o_led1_SB_LUT4_I1_I2[3]
.sym 31181 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 31183 i_button$SB_IO_IN
.sym 31184 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 31185 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
.sym 31186 o_tr_vc1$SB_IO_OUT
.sym 31187 io_ctrl_ins.pmod_dir_state[5]
.sym 31188 o_led1_SB_LUT4_I1_I2[2]
.sym 31189 i_config_SB_LUT4_I0_1_O[1]
.sym 31191 i_config[2]$SB_IO_IN
.sym 31192 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 31193 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
.sym 31194 i_config[3]$SB_IO_IN
.sym 31195 io_ctrl_ins.pmod_dir_state[6]
.sym 31196 o_led1_SB_LUT4_I1_I2[2]
.sym 31197 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
.sym 31199 o_rx_h_tx_l_b$SB_IO_OUT
.sym 31200 i_config_SB_LUT4_I0_1_O[1]
.sym 31201 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 31202 io_ctrl_ins.rf_pin_state[3]
.sym 31203 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 31204 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 31205 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
.sym 31207 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 31209 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31210 io_ctrl_ins.rf_pin_state[2]
.sym 31211 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 31213 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31215 io_ctrl_ins.rf_pin_state[4]
.sym 31216 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31217 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31219 io_ctrl_ins.rf_pin_state[7]
.sym 31220 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31221 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31223 io_ctrl_ins.rf_pin_state[1]
.sym 31224 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
.sym 31225 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31227 io_ctrl_ins.rf_pin_state[5]
.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31229 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31231 io_ctrl_ins.rf_pin_state[6]
.sym 31232 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31234 w_rx_data[4]
.sym 31238 w_rx_data[7]
.sym 31242 w_rx_data[0]
.sym 31246 w_rx_data[5]
.sym 31250 w_rx_data[1]
.sym 31254 w_rx_data[6]
.sym 31258 w_rx_data[3]
.sym 31262 w_rx_data[2]
.sym 31267 tx_fifo.wr_addr[1]
.sym 31272 tx_fifo.wr_addr[2]
.sym 31273 tx_fifo.wr_addr[1]
.sym 31276 tx_fifo.wr_addr[3]
.sym 31277 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31280 tx_fifo.wr_addr[4]
.sym 31281 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 31284 tx_fifo.wr_addr[5]
.sym 31285 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 31288 tx_fifo.wr_addr[6]
.sym 31289 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 31292 tx_fifo.wr_addr[7]
.sym 31293 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 31296 tx_fifo.wr_addr[8]
.sym 31297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 31300 tx_fifo.wr_addr[9]
.sym 31301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
.sym 31302 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 31329 tx_fifo.wr_addr[0]
.sym 31331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
.sym 31332 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 31334 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 31346 tx_fifo.rd_addr_gray_wr[4]
.sym 31352 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
.sym 31353 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
.sym 31354 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 31355 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 31356 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 31358 tx_fifo.rd_addr_gray_wr[2]
.sym 31363 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31368 spi_if_ins.spi.r_rx_bit_count[1]
.sym 31369 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31372 spi_if_ins.spi.r_rx_bit_count[2]
.sym 31373 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 31383 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
.sym 31389 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31390 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
.sym 31391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 31402 w_rx_fifo_pulled_data[7]
.sym 31407 spi_if_ins.spi.r_rx_bit_count[2]
.sym 31408 spi_if_ins.spi.r_rx_bit_count[1]
.sym 31409 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31414 i_ss$SB_IO_IN
.sym 31415 spi_if_ins.spi.r_rx_bit_count[2]
.sym 31416 spi_if_ins.spi.r_rx_bit_count[1]
.sym 31417 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31418 w_rx_fifo_pulled_data[5]
.sym 31432 i_ss$SB_IO_IN
.sym 31433 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 31438 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 31458 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 31462 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 31466 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 31470 i_mosi$SB_IO_IN
.sym 31474 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 31478 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 31482 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 31486 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 31492 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31493 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 31494 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 31500 spi_if_ins.state_if[1]
.sym 31501 spi_if_ins.state_if[0]
.sym 31503 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 31504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 31505 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 31507 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31508 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 31509 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 31511 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31512 spi_if_ins.state_if[1]
.sym 31513 spi_if_ins.state_if[0]
.sym 31514 i_rst_b$SB_IO_IN
.sym 31515 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 31516 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 31517 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 31518 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
.sym 31523 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31528 $PACKER_VCC_NET
.sym 31531 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 31532 $PACKER_VCC_NET
.sym 31533 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 31534 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 31535 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
.sym 31536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 31537 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 31539 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 31540 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 31541 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 31544 i_rst_b$SB_IO_IN
.sym 31545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 31547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31548 $PACKER_VCC_NET
.sym 31549 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31553 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31554 spi_if_ins.spi.r_tx_byte[7]
.sym 31555 spi_if_ins.spi.r_tx_byte[5]
.sym 31556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31557 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31558 spi_if_ins.r_tx_byte[7]
.sym 31562 spi_if_ins.spi.r_tx_byte[6]
.sym 31563 spi_if_ins.spi.r_tx_byte[4]
.sym 31564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31565 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31566 spi_if_ins.r_tx_byte[5]
.sym 31570 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 31571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 31572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 31573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 31575 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 31576 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 31577 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 31579 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 31580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31581 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 31585 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 31587 spi_if_ins.spi.r_tx_byte[1]
.sym 31588 spi_if_ins.spi.r_tx_byte[0]
.sym 31589 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31590 spi_if_ins.r_tx_byte[6]
.sym 31594 spi_if_ins.r_tx_byte[2]
.sym 31598 spi_if_ins.r_tx_byte[0]
.sym 31603 spi_if_ins.spi.r_tx_byte[3]
.sym 31604 spi_if_ins.spi.r_tx_byte[2]
.sym 31605 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31606 spi_if_ins.r_tx_byte[1]
.sym 31610 spi_if_ins.r_tx_byte[4]
.sym 31614 spi_if_ins.r_tx_byte[3]
.sym 31626 r_tx_data[4]
.sym 31638 r_tx_data[3]
.sym 31642 r_tx_data[5]
.sym 31658 w_cs[1]
.sym 31659 w_load
.sym 31660 w_fetch
.sym 31661 o_led1_SB_LUT4_I1_I2[3]
.sym 31662 w_rx_data[0]
.sym 31672 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 31673 o_led1_SB_LUT4_I1_I2[2]
.sym 31682 w_rx_data[4]
.sym 31686 w_rx_data[7]
.sym 31693 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 31694 i_config[1]$SB_IO_IN
.sym 31695 o_led1_SB_LUT4_I1_I2[1]
.sym 31696 o_led1_SB_LUT4_I1_I2[2]
.sym 31697 o_led1_SB_LUT4_I1_I2[3]
.sym 31698 io_ctrl_ins.pmod_dir_state[1]
.sym 31699 o_led1$SB_IO_OUT
.sym 31700 o_led1_SB_LUT4_I1_I2[2]
.sym 31701 o_led1_SB_LUT4_I1_I2[3]
.sym 31706 io_ctrl_ins.pmod_dir_state[0]
.sym 31707 o_led0$SB_IO_OUT
.sym 31708 o_led1_SB_LUT4_I1_I2[2]
.sym 31709 o_led1_SB_LUT4_I1_I2[3]
.sym 31710 w_rx_data[1]
.sym 31718 o_tr_vc1_b$SB_IO_OUT
.sym 31719 i_config_SB_LUT4_I0_1_O[1]
.sym 31720 i_config_SB_LUT4_I0_1_O[2]
.sym 31721 i_config_SB_LUT4_I0_1_O[3]
.sym 31724 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 31725 i_config_SB_LUT4_I0_1_O[1]
.sym 31786 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
.sym 31862 w_rx_fifo_pulled_data[16]
.sym 31866 w_rx_fifo_pulled_data[17]
.sym 31875 i_rst_b$SB_IO_IN
.sym 31876 smi_ctrl_ins.tx_reg_state[3]
.sym 31877 smi_ctrl_ins.tx_reg_state[0]
.sym 31878 i_rst_b$SB_IO_IN
.sym 31879 w_smi_data_input[7]
.sym 31880 smi_ctrl_ins.tx_reg_state[3]
.sym 31881 smi_ctrl_ins.tx_reg_state[0]
.sym 31883 i_rst_b$SB_IO_IN
.sym 31884 w_smi_data_input[7]
.sym 31885 smi_ctrl_ins.tx_reg_state[2]
.sym 31887 i_rst_b$SB_IO_IN
.sym 31888 w_smi_data_input[7]
.sym 31889 smi_ctrl_ins.tx_reg_state[0]
.sym 31891 i_rst_b$SB_IO_IN
.sym 31892 w_smi_data_input[7]
.sym 31893 smi_ctrl_ins.tx_reg_state[1]
.sym 31897 i_ss$SB_IO_IN
.sym 31900 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 31901 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 31903 w_smi_data_input[7]
.sym 31904 smi_ctrl_ins.tx_reg_state[2]
.sym 31905 smi_ctrl_ins.tx_reg_state[1]
.sym 31913 w_smi_data_input[7]
.sym 31932 i_smi_swe_srw$rename$0
.sym 31933 i_rst_b$SB_IO_IN
.sym 31938 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 31970 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 31978 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 31982 i_mosi$SB_IO_IN
.sym 31986 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 31990 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 31994 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 31998 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 32004 i_smi_soe_se$SB_IO_IN
.sym 32005 i_rst_b$SB_IO_IN
.sym 32006 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
.sym 32012 i_ss$SB_IO_IN
.sym 32013 spi_if_ins.r_tx_data_valid
.sym 32016 i_ss$SB_IO_IN
.sym 32017 spi_if_ins.r_tx_data_valid
.sym 32019 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 32020 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 32021 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 32050 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 32057 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 32058 i_rst_b$SB_IO_IN
.sym 32059 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 32060 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 32061 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 32067 spi_if_ins.r_tx_byte[7]
.sym 32068 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 32069 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 32127 io_pmod[6]$SB_IO_IN
.sym 32128 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
.sym 32129 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
.sym 32166 w_rx_data[1]
.sym 32186 w_rx_data[0]
.sym 32453 i_smi_swe_srw$rename$0
.sym 32457 smi_ctrl_ins.swe_and_reset
.sym 32458 spi_if_ins.spi.r_rx_done
.sym 32462 spi_if_ins.spi.r2_rx_done
.sym 32476 spi_if_ins.spi.r3_rx_done
.sym 32477 spi_if_ins.spi.r2_rx_done
.sym 32510 i_sck$SB_IO_IN
.sym 32518 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 32542 spi_if_ins.spi.SCKr[0]
.sym 32557 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 32558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 32669 lvds_clock