kopia lustrzana https://github.com/cariboulabs/cariboulite
282 wiersze
10 KiB
Verilog
282 wiersze
10 KiB
Verilog
module smi_ctrl
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(
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input i_rst_b,
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input i_sys_clk, // FPGA Clock
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input [4:0] i_ioc,
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input [7:0] i_data_in,
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output reg [7:0] o_data_out,
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input i_cs,
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input i_fetch_cmd,
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input i_load_cmd,
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// FIFO INTERFACE
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output o_rx_fifo_pull,
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input [31:0] i_rx_fifo_pulled_data,
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input i_rx_fifo_empty,
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output o_tx_fifo_push,
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output reg [31:0] o_tx_fifo_pushed_data,
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input i_tx_fifo_full,
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output o_tx_fifo_clock,
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// SMI INTERFACE
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input i_smi_soe_se,
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input i_smi_swe_srw,
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output reg [7:0] o_smi_data_out,
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input [7:0] i_smi_data_in,
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output o_smi_read_req,
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output o_smi_write_req,
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input i_smi_test,
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output o_channel,
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output o_dir,
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// TX CONDITIONAL
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output reg o_cond_tx,
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// Errors
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output reg o_address_error);
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// ---------------------------------
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// MODULE SPECIFIC IOC LIST
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// ---------------------------------
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localparam
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ioc_module_version = 5'b00000, // read only
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ioc_fifo_status = 5'b00001, // read-only
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ioc_channel_select = 5'b00010,
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ioc_dir_select = 5'b00011;
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// ---------------------------------
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// MODULE SPECIFIC PARAMS
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// ---------------------------------
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localparam
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module_version = 8'b00000001;
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// ---------------------------------------
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// MODULE CONTROL
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// ---------------------------------------
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assign o_channel = r_channel;
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assign o_dir = r_dir;
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always @(posedge i_sys_clk or negedge i_rst_b)
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begin
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if (i_rst_b == 1'b0) begin
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o_address_error <= 1'b0;
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r_dir <= 1'b0;
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r_channel <= 1'b0;
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end else begin
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if (i_cs == 1'b1) begin
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//=============================================
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// READ OPERATIONS
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//=============================================
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if (i_fetch_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_module_version: o_data_out <= module_version; // Module Version
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//----------------------------------------------
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ioc_fifo_status: begin
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o_data_out[0] <= i_rx_fifo_empty;
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o_data_out[1] <= i_tx_fifo_full;
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o_data_out[2] <= r_channel;
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o_data_out[3] <= i_smi_test;
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o_data_out[4] <= r_dir;
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o_data_out[7:4] <= 3'b000;
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end
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endcase
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end
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//=============================================
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// WRITE OPERATIONS
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//=============================================
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else if (i_load_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_channel_select: begin
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r_channel <= i_data_in[0];
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end
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//----------------------------------------------
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ioc_dir_select: begin
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r_dir <= i_data_in[0];
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end
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endcase
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end
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end
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end
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end
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// ---------------------------------------
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// RX SIDE
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// ---------------------------------------
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reg [4:0] int_cnt_rx;
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reg [7:0] r_smi_test_count;
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reg r_fifo_pull;
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reg r_fifo_pull_1;
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wire w_fifo_pull_trigger;
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reg r_channel;
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reg r_dir;
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reg [31:0] r_fifo_pulled_data;
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wire soe_and_reset;
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assign soe_and_reset = i_rst_b & i_smi_soe_se;
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assign o_smi_read_req = (!i_rx_fifo_empty) || i_smi_test;
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assign o_rx_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_rx_fifo_empty;
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always @(negedge soe_and_reset)
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begin
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if (i_rst_b == 1'b0) begin
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int_cnt_rx <= 5'd0;
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r_smi_test_count <= 8'h56;
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r_fifo_pulled_data <= 32'h00000000;
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end else begin
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// trigger the fifo pulling on the second byte
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w_fifo_pull_trigger <= (int_cnt_rx == 5'd8) && !i_smi_test;
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if ( i_smi_test ) begin
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if (r_smi_test_count == 0) begin
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r_smi_test_count <= 8'h56;
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end else begin
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o_smi_data_out <= r_smi_test_count;
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r_smi_test_count <= {((r_smi_test_count[2] ^ r_smi_test_count[3]) & 1'b1), r_smi_test_count[7:1]};
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end
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end else begin
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int_cnt_rx <= int_cnt_rx + 8;
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o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
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// update the internal register as soon as we reach the fourth byte
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if (int_cnt_rx == 5'd24) begin
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r_fifo_pulled_data <= i_rx_fifo_pulled_data;
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end
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end
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end
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end
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always @(posedge i_sys_clk)
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begin
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if (i_rst_b == 1'b0) begin
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r_fifo_pull <= 1'b0;
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r_fifo_pull_1 <= 1'b0;
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end else begin
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r_fifo_pull <= w_fifo_pull_trigger;
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r_fifo_pull_1 <= r_fifo_pull;
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end
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end
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// -----------------------------------------
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// TX SIDE
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// -----------------------------------------
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localparam
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tx_state_first = 2'b00,
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tx_state_second = 2'b01,
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tx_state_third = 2'b10,
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tx_state_fourth = 2'b11;
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reg [12:0] int_cnt_tx;
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reg [31:0] r_fifo_pushed_data;
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reg [1:0] tx_reg_state;
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reg modem_tx_ctrl;
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reg cond_tx_ctrl;
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reg r_fifo_push;
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reg r_fifo_push_1;
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wire w_fifo_push_trigger;
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wire swe_and_reset;
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assign o_smi_write_req = !i_tx_fifo_full;
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assign o_tx_fifo_push = !r_fifo_push_1 && r_fifo_push && !i_tx_fifo_full;
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assign swe_and_reset = i_rst_b & i_smi_swe_srw;
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assign o_tx_fifo_clock = i_sys_clk;
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always @(negedge swe_and_reset)
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begin
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if (i_rst_b == 1'b0) begin
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tx_reg_state <= tx_state_first;
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w_fifo_push_trigger <= 1'b0;
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r_fifo_pushed_data <= 32'h00000000;
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modem_tx_ctrl <= 1'b0;
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cond_tx_ctrl <= 1'b0;
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// DEBUG
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int_cnt_tx <= 0;
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// END_DEBUG
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end else begin
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case (tx_reg_state)
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//----------------------------------------------
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tx_state_first:
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begin
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if (i_smi_data_in[7] == 1'b1) begin
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r_fifo_pushed_data[31:30] <= 2'b10;
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modem_tx_ctrl <= i_smi_data_in[6];
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cond_tx_ctrl <= i_smi_data_in[5];
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r_fifo_pushed_data[29:25] <= i_smi_data_in[4:0];
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tx_reg_state <= tx_state_second;
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w_fifo_push_trigger <= 1'b0;
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end else begin
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// if from some reason we are in the first byte stage and we got
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// a byte without '1' on its MSB, that means that we are not synced
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// so push a "sync" word into the modem.
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cond_tx_ctrl <= 1'b0;
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modem_tx_ctrl <= 1'b0;
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o_tx_fifo_pushed_data <= 32'h00000000;
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w_fifo_push_trigger <= 1'b1;
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end
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end
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//----------------------------------------------
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tx_state_second:
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begin
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if (i_smi_data_in[7] == 1'b0) begin
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r_fifo_pushed_data[24:18] <= i_smi_data_in[6:0];
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tx_reg_state <= tx_state_third;
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end else begin
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tx_reg_state <= tx_state_first;
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end
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w_fifo_push_trigger <= 1'b0;
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end
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//----------------------------------------------
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tx_state_third:
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begin
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if (i_smi_data_in[7] == 1'b0) begin
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r_fifo_pushed_data[17] <= i_smi_data_in[6];
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r_fifo_pushed_data[16] <= modem_tx_ctrl;
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r_fifo_pushed_data[15:14] <= 2'b01;
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r_fifo_pushed_data[13:8] <= i_smi_data_in[5:0];
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tx_reg_state <= tx_state_fourth;
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end else begin
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tx_reg_state <= tx_state_first;
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end
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w_fifo_push_trigger <= 1'b0;
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end
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//----------------------------------------------
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tx_state_fourth:
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begin
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if (i_smi_data_in[7] == 1'b0) begin
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o_tx_fifo_pushed_data <= {r_fifo_pushed_data[31:8], i_smi_data_in[6:0], 1'b0};
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//o_tx_fifo_pushed_data <= {i_smi_data_in[6:0], 1'b0, r_fifo_pushed_data[15:8], r_fifo_pushed_data[23:16], r_fifo_pushed_data[31:24]};
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o_tx_fifo_pushed_data <= {2'b10, int_cnt_tx, 1'b1, 2'b01, 13'h3F, 1'b0};
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int_cnt_tx <= int_cnt_tx + 512;
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w_fifo_push_trigger <= 1'b1;
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o_cond_tx <= cond_tx_ctrl;
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end else begin
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o_tx_fifo_pushed_data <= 32'h00000000;
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w_fifo_push_trigger <= 1'b0;
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end
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tx_reg_state <= tx_state_first;
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end
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endcase
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end
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end
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always @(posedge i_sys_clk)
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begin
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if (i_rst_b == 1'b0) begin
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r_fifo_push <= 1'b0;
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r_fifo_push_1 <= 1'b0;
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end else begin
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r_fifo_push <= w_fifo_push_trigger;
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r_fifo_push_1 <= r_fifo_push;
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end
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end
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endmodule // smi_ctrl
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