kopia lustrzana https://github.com/cariboulabs/cariboulite
130 wiersze
4.7 KiB
Verilog
130 wiersze
4.7 KiB
Verilog
module lvds_tx (
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input i_rst_b,
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input i_ddr_clk,
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output reg[1:0] o_ddr_data,
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input i_fifo_empty,
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output o_fifo_read_clk,
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output o_fifo_pull,
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input [31:0] i_fifo_data,
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input [3:0] i_sample_gap,
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input i_tx_state,
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input i_sync_input,
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input i_debug_lb,
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output o_tx_state_bit,
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output o_sync_state_bit,
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);
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// STATES and PARAMS
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localparam
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tx_state_sync = 1'b0,
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tx_state_tx = 1'b1;
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localparam sync_duration_frames = 4'd10; // at least 2.5usec
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localparam zero_frame = 32'b00000000_00000000_00000000_00000000;
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localparam lb_frame = 32'b10000100_00000011_01110000_01001000;
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// Internal Registers
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reg [3:0] r_sync_count;
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wire frame_pull_clock;
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wire frame_assign_clock;
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reg r_state;
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reg [3:0] r_phase_count;
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reg [31:0] r_fifo_data;
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reg r_pulled;
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reg r_schedule_zero_frame;
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// Initial conditions
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initial begin
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r_phase_count = 4'd15;
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r_fifo_data <= zero_frame;
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end
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assign o_fifo_read_clk = i_ddr_clk;
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assign o_tx_state_bit = r_state;
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assign o_sync_state_bit = 1'b0;
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assign o_fifo_pull = r_pulled;
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// SHIFT REGISTER
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always @(posedge i_ddr_clk) begin
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if (i_rst_b == 1'b0) begin
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r_phase_count <= 4'd15;
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end else begin
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o_ddr_data[1:0] <= r_fifo_data[2*r_phase_count+1 : 2*r_phase_count];
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r_phase_count <= r_phase_count - 1;
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end
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end
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// SYNC AND MANAGEMENT
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always @(posedge i_ddr_clk)
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begin
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if (i_rst_b == 1'b0) begin
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r_state <= tx_state_sync;
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r_pulled <= 1'b0;
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r_fifo_data <= zero_frame;
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r_sync_count <= sync_duration_frames;
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r_schedule_zero_frame <= 1'b0;
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end else begin
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case (r_state)
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//----------------------------------------------
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tx_state_sync:
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begin
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if (r_phase_count == 4'd0) begin
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if (r_schedule_zero_frame) begin
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r_fifo_data <= zero_frame;
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r_schedule_zero_frame <= 1'b0;
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end
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end else if (r_phase_count == 4'd1) begin
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if (r_sync_count == 4'd0) begin
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if (i_debug_lb && !i_tx_state) begin
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r_fifo_data <= lb_frame;
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r_state <= tx_state_sync;
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end else if (!i_debug_lb && i_tx_state) begin
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r_pulled <= !i_fifo_empty;
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r_state <= tx_state_tx;
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end else begin
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r_sync_count <= sync_duration_frames;
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r_state <= tx_state_sync;
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r_fifo_data <= zero_frame;
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end
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end else begin
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r_sync_count <= r_sync_count - 1;
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r_schedule_zero_frame <= 1'b1;
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//r_fifo_data <= zero_frame;
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r_state <= tx_state_sync;
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end
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end
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end
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//----------------------------------------------
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tx_state_tx:
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begin
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if (i_debug_lb || !i_tx_state) begin
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r_state <= tx_state_sync;
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r_sync_count <= sync_duration_frames;
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r_pulled <= 1'b0;
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end else if (r_phase_count == 4'd1) begin
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r_pulled <= !i_fifo_empty;
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r_state <= tx_state_tx;
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end else if (r_phase_count == 4'd0) begin
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if (r_pulled == 1'b0) begin
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r_sync_count <= sync_duration_frames;
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r_fifo_data <= zero_frame;
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r_state <= tx_state_sync;
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end else begin
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r_fifo_data <= i_fifo_data;
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if (i_sample_gap > 0) begin
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r_sync_count <= i_sample_gap;
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r_state <= tx_state_sync;
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end else begin
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r_state <= tx_state_tx;
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end
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end
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r_pulled <= 1'b0;
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end
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end
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endcase
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end
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end
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endmodule
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