kopia lustrzana https://github.com/cariboulabs/cariboulite
98 wiersze
3.4 KiB
Verilog
98 wiersze
3.4 KiB
Verilog
module sys_ctrl
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(
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input i_rst_b,
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input i_sys_clk, // FPGA Clock
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input [4:0] i_ioc,
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input [7:0] i_data_in,
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output reg [7:0] o_data_out,
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input i_cs,
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input i_fetch_cmd,
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input i_load_cmd,
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// controls output
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output o_debug_fifo_push,
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output o_debug_fifo_pull,
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output o_debug_smi_test,
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output o_debug_loopback_tx,
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output [3:0] o_tx_sample_gap,
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);
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// MODULE SPECIFIC IOC LIST
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// ------------------------
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localparam
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ioc_module_version = 5'b00000, // read only
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ioc_system_version = 5'b00001, // read only
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ioc_manu_id = 5'b00010, // read only
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ioc_error_state = 5'b00011, // read only
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ioc_debug_modes = 5'b00101, // write only
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ioc_tx_sample_gap = 5'b00110; // read / write
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// MODULE SPECIFIC PARAMS
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// ----------------------
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localparam
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module_version = 8'b00000001,
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system_version = 8'b00000001,
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manu_id = 8'b00000001;
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// MODULE INTERNAL SIGNALS
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// -----------------------
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reg debug_fifo_push;
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reg debug_fifo_pull;
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reg debug_smi_test;
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reg debug_loopback_tx;
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reg [3:0] tx_sample_gap;
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assign o_debug_fifo_push = debug_fifo_push;
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assign o_debug_fifo_pull = debug_fifo_pull;
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assign o_debug_smi_test = debug_smi_test;
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// MODULE MAIN PROCESS
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// -------------------
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always @(posedge i_sys_clk or negedge i_rst_b)
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begin
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if (i_rst_b == 1'b0) begin
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o_data_out <= 8'b00000000;
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debug_fifo_push <= 1'b0;
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debug_fifo_pull <= 1'b0;
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debug_smi_test <= 1'b0;
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debug_loopback_tx <= 1'b0;
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tx_sample_gap <= 4'd0;
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end else if (i_cs == 1'b1) begin
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//=============================================
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// READ OPERATIONS
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//=============================================
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if (i_fetch_cmd == 1'b1) begin
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case (i_ioc)
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ioc_module_version: o_data_out <= module_version;
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ioc_system_version: o_data_out <= system_version;
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ioc_manu_id: o_data_out <= manu_id;
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//----------------------------------------------
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ioc_tx_sample_gap: begin
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o_data_out[3:0] <= tx_sample_gap;
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o_data_out[7:4] <= 4'd0;
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end
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endcase
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end
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//=============================================
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// WRITE OPERATIONS
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//=============================================
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else if (i_load_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_debug_modes: begin
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debug_fifo_push <= i_data_in[0];
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debug_fifo_pull <= i_data_in[1];
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debug_smi_test <= i_data_in[2];
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debug_loopback_tx <= i_data_in[3];
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end
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//----------------------------------------------
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ioc_tx_sample_gap: begin
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tx_sample_gap <= i_data_in[3:0];
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end
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endcase
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end
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end
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end
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endmodule // sys_ctrl
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