kopia lustrzana https://github.com/cariboulabs/cariboulite
392 wiersze
14 KiB
C
392 wiersze
14 KiB
C
/**
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* Declarations and definitions for Broadcom's Secondary Memory Interface
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*
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* Written by Luke Wren <luke@raspberrypi.org>
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* Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
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* Copyright (c) 2010-2012 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BCM2835_SMI_H
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#define BCM2835_SMI_H
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#include <linux/ioctl.h>
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#ifndef __KERNEL__
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#include <stdint.h>
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#include <stdbool.h>
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#endif
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#define BCM2835_SMI_IOC_MAGIC 0x1
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#define BCM2835_SMI_INVALID_HANDLE (~0)
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/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
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#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0)
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#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1)
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#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2)
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#define BCM2835_SMI_IOC_MAX 2
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#define SMI_WIDTH_8BIT 0
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#define SMI_WIDTH_16BIT 1
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#define SMI_WIDTH_9BIT 2
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#define SMI_WIDTH_18BIT 3
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/* max number of bytes where DMA will not be used */
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#define DMA_THRESHOLD_BYTES 128
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#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
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#define DMA_BOUNCE_BUFFER_COUNT 3
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struct smi_settings {
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int data_width;
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/* Whether or not to pack multiple SMI transfers into a
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single 32 bit FIFO word */
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bool pack_data;
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/* Timing for reads (writes the same but for WE)
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*
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* OE ----------+ +--------------------
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* | |
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* +----------+
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* SD -<==============================>-----------
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* SA -<=========================================>-
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* <-setup-> <-strobe -> <-hold -> <- pace ->
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*/
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int read_setup_time;
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int read_hold_time;
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int read_pace_time;
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int read_strobe_time;
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int write_setup_time;
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int write_hold_time;
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int write_pace_time;
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int write_strobe_time;
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bool dma_enable; /* DREQs */
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bool dma_passthrough_enable; /* External DREQs */
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int dma_read_thresh;
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int dma_write_thresh;
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int dma_panic_read_thresh;
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int dma_panic_write_thresh;
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};
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/****************************************************************************
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*
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* Declare exported SMI functions
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*
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***************************************************************************/
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#ifdef __KERNEL__
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#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
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#include <linux/of.h>
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#include <linux/semaphore.h>
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struct bcm2835_smi_instance;
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struct bcm2835_smi_bounce_info {
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struct semaphore callback_sem;
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void *buffer[DMA_BOUNCE_BUFFER_COUNT];
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dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
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struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
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};
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void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
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struct smi_settings *bcm2835_smi_get_settings_from_regs(
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struct bcm2835_smi_instance *inst);
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void bcm2835_smi_write_buf(
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struct bcm2835_smi_instance *inst,
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const void *buf,
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size_t n_bytes);
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void bcm2835_smi_read_buf(
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struct bcm2835_smi_instance *inst,
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void *buf,
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size_t n_bytes);
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void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
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unsigned int address);
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ssize_t bcm2835_smi_user_dma(
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struct bcm2835_smi_instance *inst,
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enum dma_transfer_direction dma_dir,
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char __user *user_ptr,
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size_t count,
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struct bcm2835_smi_bounce_info **bounce);
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struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
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#endif /* __KERNEL__ */
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/****************************************************************
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*
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* Implementation-only declarations
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*
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****************************************************************/
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#ifdef BCM2835_SMI_IMPLEMENTATION
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/* Clock manager registers for SMI clock: */
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#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
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/* Clock manager "password" to protect registers from spurious writes */
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#define CM_PWD (0x5a << 24)
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#define CM_SMI_CTL 0x00
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#define CM_SMI_DIV 0x04
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#define CM_SMI_CTL_FLIP (1 << 8)
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#define CM_SMI_CTL_BUSY (1 << 7)
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#define CM_SMI_CTL_KILL (1 << 5)
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#define CM_SMI_CTL_ENAB (1 << 4)
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#define CM_SMI_CTL_SRC_MASK (0xf)
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#define CM_SMI_CTL_SRC_OFFS (0)
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#define CM_SMI_DIV_DIVI_MASK (0xf << 12)
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#define CM_SMI_DIV_DIVI_OFFS (12)
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#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
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#define CM_SMI_DIV_DIVF_OFFS (4)
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/* SMI register mapping:*/
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#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
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#define SMICS 0x00 /* control + status register */
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#define SMIL 0x04 /* length/count (n external txfers) */
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#define SMIA 0x08 /* address register */
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#define SMID 0x0c /* data register */
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#define SMIDSR0 0x10 /* device 0 read settings */
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#define SMIDSW0 0x14 /* device 0 write settings */
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#define SMIDSR1 0x18 /* device 1 read settings */
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#define SMIDSW1 0x1c /* device 1 write settings */
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#define SMIDSR2 0x20 /* device 2 read settings */
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#define SMIDSW2 0x24 /* device 2 write settings */
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#define SMIDSR3 0x28 /* device 3 read settings */
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#define SMIDSW3 0x2c /* device 3 write settings */
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#define SMIDC 0x30 /* DMA control registers */
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#define SMIDCS 0x34 /* direct control/status register */
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#define SMIDA 0x38 /* direct address register */
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#define SMIDD 0x3c /* direct data registers */
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#define SMIFD 0x40 /* FIFO debug register */
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/* Control and Status register bits:
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* SMICS_RXF : RX fifo full: 1 when RX fifo is full
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* SMICS_TXE : TX fifo empty: 1 when empty.
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* SMICS_RXD : RX fifo contains data: 1 when there is data.
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* SMICS_TXD : TX fifo can accept data: 1 when true.
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* SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or
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* when "DONE" and fifo not emptied.
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* SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full.
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* SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
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* when full. Write 1 to clear.
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* SMICS_EDREQ : 1 when external DREQ received.
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* SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes.
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* SMICS_SETERR : 1 if there was an error writing to setup regs (e.g.
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* tx was in progress). Write 1 to clear.
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* SMICS_PVMODE : Set to 1 to enable pixel valve mode.
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* SMICS_INTR : Set to 1 to enable interrupt on RX.
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* SMICS_INTT : Set to 1 to enable interrupt on TX.
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* SMICS_INTD : Set to 1 to enable interrupt on DONE condition.
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* SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait
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* for a TE trigger before writing.
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* SMICS_PAD1 : Padding settings for external transfers. For writes: the
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* number of bytes initially written to the TX fifo that
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* SMICS_PAD0 : should be ignored. For reads: the number of bytes that will
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* be read before the data, and should be dropped.
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* SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
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* SMICS_CLEAR : Write 1 to clear the FIFOs.
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* SMICS_START : Write 1 to start the programmed transfer.
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* SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway.
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* SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until
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* FIFO emptied.
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* SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable.
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*/
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#define SMICS_RXF (1 << 31)
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#define SMICS_TXE (1 << 30)
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#define SMICS_RXD (1 << 29)
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#define SMICS_TXD (1 << 28)
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#define SMICS_RXR (1 << 27)
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#define SMICS_TXW (1 << 26)
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#define SMICS_AFERR (1 << 25)
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#define SMICS_EDREQ (1 << 15)
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#define SMICS_PXLDAT (1 << 14)
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#define SMICS_SETERR (1 << 13)
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#define SMICS_PVMODE (1 << 12)
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#define SMICS_INTR (1 << 11)
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#define SMICS_INTT (1 << 10)
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#define SMICS_INTD (1 << 9)
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#define SMICS_TEEN (1 << 8)
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#define SMICS_PAD1 (1 << 7)
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#define SMICS_PAD0 (1 << 6)
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#define SMICS_WRITE (1 << 5)
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#define SMICS_CLEAR (1 << 4)
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#define SMICS_START (1 << 3)
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#define SMICS_ACTIVE (1 << 2)
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#define SMICS_DONE (1 << 1)
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#define SMICS_ENABLE (1 << 0)
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/* Address register bits: */
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#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
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#define SMIA_DEVICE_OFFS (8)
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#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */
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#define SMIA_ADDR_OFFS (0)
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/* DMA control register bits:
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* SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
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* SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by
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* SMI as usual. When set to 1, the top two pins are used for
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* external DREQs: pin 16 read request, 17 write.
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* SMIDC_PANIC* : Threshold at which DMA will panic during read/write.
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* SMIDC_REQ* : Threshold at which DMA will generate a DREQ.
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*/
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#define SMIDC_DMAEN (1 << 28)
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#define SMIDC_DMAP (1 << 24)
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#define SMIDC_PANICR_MASK (0x3f << 18)
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#define SMIDC_PANICR_OFFS (18)
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#define SMIDC_PANICW_MASK (0x3f << 12)
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#define SMIDC_PANICW_OFFS (12)
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#define SMIDC_REQR_MASK (0x3f << 6)
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#define SMIDC_REQR_OFFS (6)
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#define SMIDC_REQW_MASK (0x3f)
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#define SMIDC_REQW_OFFS (0)
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/* Device settings register bits: same for all 4 (or 3?) device register sets.
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* Device read settings:
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* SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit,
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* 10 = 18bit, 11 = 9bit.
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* SMIDSR_RSETUP : Read setup time: number of core cycles between chip
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* select/address and read strobe. Min 1, max 64.
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* SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins,
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* rather than OE + WE pin)
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* SMIDSR_FSETUP : If set to 1, setup time only applies to first
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* transfer after address change.
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* SMIDSR_RHOLD : Number of core cycles between read strobe going
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* inactive and CS/address going inactive. Min 1, max 64
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* SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always
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* be used for the next transaction, even if it is not
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* to this device.
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* SMIDSR_RPACE : Number of core cycles spent waiting between CS
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* deassert and start of next transfer. Min 1, max 128
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* SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads
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* from device. Must also set DMAP in SMICS.
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* SMIDSR_RSTROBE : Number of cycles to assert the read strobe.
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* min 1, max 128.
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*/
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#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30))
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#define SMIDSR_RWIDTH_OFFS (30)
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#define SMIDSR_RSETUP_MASK (0x3f << 24)
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#define SMIDSR_RSETUP_OFFS (24)
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#define SMIDSR_MODE68 (1 << 23)
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#define SMIDSR_FSETUP (1 << 22)
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#define SMIDSR_RHOLD_MASK (0x3f << 16)
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#define SMIDSR_RHOLD_OFFS (16)
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#define SMIDSR_RPACEALL (1 << 15)
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#define SMIDSR_RPACE_MASK (0x7f << 8)
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#define SMIDSR_RPACE_OFFS (8)
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#define SMIDSR_RDREQ (1 << 7)
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#define SMIDSR_RSTROBE_MASK (0x7f)
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#define SMIDSR_RSTROBE_OFFS (0)
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/* Device write settings:
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* SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit,
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* 10= 18bit, 11 = 9bit.
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* SMIDSW_WSETUP : Number of cycles between CS assert and write strobe.
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* Min 1, max 64.
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* SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565,
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* 1 = 32bit RGBA 8888
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* SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
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* SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64
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* SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next
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* transfer, regardless of that transfer's device.
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* SMIDSW_WPACE : Cycles between CS deassert and next CS assert.
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* Min 1, max 128
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* SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must
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* be set in SMICS.
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* SMIDSW_WSTROBE : Number of cycles to assert the write strobe.
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* Min 1, max 128
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*/
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#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30))
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#define SMIDSW_WWIDTH_OFFS (30)
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#define SMIDSW_WSETUP_MASK (0x3f << 24)
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#define SMIDSW_WSETUP_OFFS (24)
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#define SMIDSW_WFORMAT (1 << 23)
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#define SMIDSW_WSWAP (1 << 22)
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#define SMIDSW_WHOLD_MASK (0x3f << 16)
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#define SMIDSW_WHOLD_OFFS (16)
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#define SMIDSW_WPACEALL (1 << 15)
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#define SMIDSW_WPACE_MASK (0x7f << 8)
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#define SMIDSW_WPACE_OFFS (8)
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#define SMIDSW_WDREQ (1 << 7)
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#define SMIDSW_WSTROBE_MASK (0x7f)
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#define SMIDSW_WSTROBE_OFFS (0)
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/* Direct transfer control + status register
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* SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read
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* SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
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* SMIDCS_START : Write 1 to start a transfer, if one is not already underway.
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* SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
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*/
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#define SMIDCS_WRITE (1 << 3)
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#define SMIDCS_DONE (1 << 2)
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#define SMIDCS_START (1 << 1)
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#define SMIDCS_ENABLE (1 << 0)
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/* Direct transfer address register
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* SMIDA_DEVICE : Indicates which of the device settings banks should be used.
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* SMIDA_ADDR : The value to be asserted on the address pins.
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*/
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#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8))
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#define SMIDA_DEVICE_OFFS (8)
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#define SMIDA_ADDR_MASK (0x3f)
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#define SMIDA_ADDR_OFFS (0)
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/* FIFO debug register
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* SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer
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* SMIFD_FCNT : The current FIFO count.
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*/
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#define SMIFD_FLVL_MASK (0x3f << 8)
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#define SMIFD_FLVL_OFFS (8)
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#define SMIFD_FCNT_MASK (0x3f)
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#define SMIFD_FCNT_OFFS (0)
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#endif /* BCM2835_SMI_IMPLEMENTATION */
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#endif /* BCM2835_SMI_H */
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