diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c index 70d9465..97a7788 100644 --- a/driver/smi_stream_dev.c +++ b/driver/smi_stream_dev.c @@ -82,49 +82,47 @@ MODULE_PARM_DESC(fifo_mtu_multiplier, "the number of MTUs (N*MTU_SIZE) to alloca MODULE_PARM_DESC(addr_dir_offset, "GPIO_SA[4:0] offset of the channel direction (default cariboulite 2), valid: [0..4] or (-1) if unused"); MODULE_PARM_DESC(addr_ch_offset, "GPIO_SA[4:0] offset of the channel select (default cariboulite 3), valid: [0..4] or (-1) if unused"); +/***************************************************************************/ struct bcm2835_smi_dev_instance { - struct device *dev; - struct bcm2835_smi_instance *smi_inst; + struct device *dev; + struct bcm2835_smi_instance *smi_inst; - // address related - unsigned int cur_address; + // address related + unsigned int cur_address; int address_changed; - + // flags int invalidate_rx_buffers; int invalidate_tx_buffers; - - unsigned int count_since_refresh; - struct task_struct *reader_thread; - struct task_struct *writer_thread; - struct kfifo rx_fifo; - struct kfifo tx_fifo; - uint8_t* rx_fifo_buffer; - uint8_t* tx_fifo_buffer; - smi_stream_state_en state; - struct mutex read_lock; - struct mutex write_lock; - spinlock_t state_lock; - wait_queue_head_t poll_event; - uint32_t current_read_chunk; - uint32_t counter_missed; - bool readable; - bool writeable; - bool reader_thread_running; - bool writer_thread_running; + + unsigned int count_since_refresh; + struct kfifo rx_fifo; + struct kfifo tx_fifo; + uint8_t* rx_fifo_buffer; + uint8_t* tx_fifo_buffer; + smi_stream_state_en state; + struct mutex read_lock; + struct mutex write_lock; + spinlock_t state_lock; + wait_queue_head_t poll_event; + uint32_t current_read_chunk; + uint32_t counter_missed; + bool readable; + bool writeable; + bool transfer_thread_running; bool reader_waiting_sema; bool writer_waiting_sema; }; // Prototypes -ssize_t stream_smi_user_dma( struct bcm2835_smi_instance *inst, - enum dma_transfer_direction dma_dir, - struct bcm2835_smi_bounce_info **bounce, - int buff_num); +/***************************************************************************/ +ssize_t stream_smi_user_dma(struct bcm2835_smi_instance *inst, + enum dma_transfer_direction dma_dir, + struct bcm2835_smi_bounce_info **bounce, + int buff_num); -int writer_thread_init(struct bcm2835_smi_dev_instance *inst); int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfer_direction dir,dma_async_tx_callback callback); static void stream_smi_read_dma_callback(void *param); static void stream_smi_write_dma_callback(void *param); @@ -146,10 +144,12 @@ static const char *const ioctl_names[] = }; -#define BUSY_WAIT_WHILE_TIMEOUT(C,T,R) {int t = (T); while ((C) && t>0){t--;} (R)=t>0;} +#define BUSY_WAIT_WHILE_TIMEOUT(C,T,R) {int t = (T); while ((C) && t>0){t--;} (R)=t>0;} /***************************************************************************/ -static void write_smi_reg(struct bcm2835_smi_instance *inst, u32 val, unsigned reg) +static void write_smi_reg(struct bcm2835_smi_instance *inst, + u32 val, + unsigned reg) { writel(val, inst->smi_regs_ptr + reg); mb(); @@ -158,34 +158,37 @@ static void write_smi_reg(struct bcm2835_smi_instance *inst, u32 val, unsigned r /***************************************************************************/ static u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) { - return readl(inst->smi_regs_ptr + reg); + return readl(inst->smi_regs_ptr + reg); } +/***************************************************************************/ void print_smil_registers() { - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - unsigned int smics = read_smi_reg(smi_inst, SMICS); - unsigned int smil = read_smi_reg(smi_inst, SMIL); - unsigned int smidc = read_smi_reg(smi_inst, SMIDC); - unsigned int smidsw0 = read_smi_reg(smi_inst,SMIDSW0); - - dev_info(inst->dev, "regs: smics %08X smil %08X smids %08X smisw0 %08X",smics,smil,smidc,smidsw0); + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + unsigned int smics = read_smi_reg(smi_inst, SMICS); + unsigned int smil = read_smi_reg(smi_inst, SMIL); + unsigned int smidc = read_smi_reg(smi_inst, SMIDC); + unsigned int smidsw0 = read_smi_reg(smi_inst,SMIDSW0); + + dev_info(inst->dev, "regs: smics %08X smil %08X smids %08X smisw0 %08X",smics,smil,smidc,smidsw0); } +/***************************************************************************/ void print_smil_registers_ext(const char* b) { - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - unsigned int smics = read_smi_reg(smi_inst, SMICS); - unsigned int smil = read_smi_reg(smi_inst, SMIL); - unsigned int smidc = read_smi_reg(smi_inst, SMIDC); - unsigned int smidsw0 = read_smi_reg(smi_inst,SMIDSW0); - dev_info(inst->dev, "%s: regs: smics %08X smil %08X smids %08X smisw0 %08X",b,smics,smil,smidc,smidsw0); + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + unsigned int smics = read_smi_reg(smi_inst, SMICS); + unsigned int smil = read_smi_reg(smi_inst, SMIL); + unsigned int smidc = read_smi_reg(smi_inst, SMIDC); + unsigned int smidsw0 = read_smi_reg(smi_inst,SMIDSW0); + dev_info(inst->dev, "%s: regs: smics %08X smil %08X smids %08X smisw0 %08X",b,smics,smil,smidc,smidsw0); } +/***************************************************************************/ static unsigned int calc_address_from_state(smi_stream_state_en state) { - unsigned int return_val = (smi_stream_dir_device_to_smi<dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); - - spin_lock(&inst->state_lock); + dev_info(inst->dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); + + spin_lock(&inst->state_lock); // in any case if we want to change the state // then stop the current transfer and update the new state. - if(new_state != inst->state) - { + if(new_state != inst->state) + { // stop the transter transfer_thread_stop(inst); - if(smi_is_active(inst->smi_inst)) - { - spin_unlock(&inst->state_lock); - return -EAGAIN; - } + if(smi_is_active(inst->smi_inst)) + { + spin_unlock(&inst->state_lock); + return -EAGAIN; + } // update the state from current state - inst->state = smi_stream_idle; + inst->state = smi_stream_idle; bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); ret = 0; //now state is idle - } + } // else if the state is the same, do nothing else - { - spin_unlock(&inst->state_lock); + { + spin_unlock(&inst->state_lock); dev_info(inst->dev, "State is the same as before"); - return 0; - } + return 0; + } - + // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer - if(new_state != smi_stream_idle) - { + if(new_state != smi_stream_idle) + { bcm2835_smi_set_address(inst->smi_inst, new_address); - if (new_state == smi_stream_tx_channel) - { - ret = transfer_thread_init(inst,DMA_MEM_TO_DEV,stream_smi_write_dma_callback); - } - else - { - ret = transfer_thread_init(inst,DMA_DEV_TO_MEM,stream_smi_read_dma_callback); - } - + if (new_state == smi_stream_tx_channel) + { + ret = transfer_thread_init(inst,DMA_MEM_TO_DEV,stream_smi_write_dma_callback); + } + else + { + ret = transfer_thread_init(inst,DMA_DEV_TO_MEM,stream_smi_read_dma_callback); + } + // if starting the transfer succeeded update the state - if (!ret) - { - inst->state = new_state; - } + if (!ret) + { + inst->state = new_state; + } // if failed, go back to idle - else - { - bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + else + { + bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); inst->state = smi_stream_idle; - } - } + } + } mb(); - spin_unlock(&inst->state_lock); + spin_unlock(&inst->state_lock); // return the success - return ret; + return ret; } /***************************************************************************/ static void smi_setup_clock(struct bcm2835_smi_instance *inst) { - + } - - /***************************************************************************/ static inline int smi_enabled(struct bcm2835_smi_instance *inst) { - return read_smi_reg(inst, SMICS) & SMICS_ENABLE; + return read_smi_reg(inst, SMICS) & SMICS_ENABLE; } /***************************************************************************/ - - - static int smi_disable_sync(struct bcm2835_smi_instance *smi_inst) { - int smics_temp = 0; - int success = 0; - int errors = 0; - //dev_info(inst->dev, "smi disable sync enter"); - - /* Disable the peripheral: */ - smics_temp = read_smi_reg(smi_inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); - write_smi_reg(smi_inst, smics_temp, SMICS); + int smics_temp = 0; + int success = 0; + int errors = 0; + //dev_info(inst->dev, "smi disable sync enter"); + + /* Disable the peripheral: */ + smics_temp = read_smi_reg(smi_inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); + write_smi_reg(smi_inst, smics_temp, SMICS); + + // wait for the ENABLE to go low + BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 100000U, success); + + if (!success) + { + //dev_info(inst->dev, "error disable sync. %u %08X", smi_enabled(smi_inst), read_smi_reg(smi_inst, SMICS)); + errors = -1; + } + + //print_smil_registers(); + //dev_info(inst->dev, "smi disable sync exit"); + + return errors; - // wait for the ENABLE to go low - BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 100000U, success); - - if (!success) - { - //dev_info(inst->dev, "error disable sync. %u %08X", smi_enabled(smi_inst), read_smi_reg(smi_inst, SMICS)); - errors = -1; - } - - //print_smil_registers(); - //dev_info(inst->dev, "smi disable sync exit"); - - return errors; - } static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers) { - int smics_temp = 0; - //print_smil_registers_ext("refresh 1"); - write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting - //print_smil_registers_ext("refresh 2"); - // Start the transaction - smics_temp = read_smi_reg(smi_inst, SMICS); - smics_temp |= SMICS_START; - //smics_temp &= ~(SMICS_PVMODE); - write_smi_reg(smi_inst, smics_temp & 0xffff, SMICS); - inst->count_since_refresh = 0; - //print_smil_registers_ext("refresh 3"); + int smics_temp = 0; + //print_smil_registers_ext("refresh 1"); + write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting + //print_smil_registers_ext("refresh 2"); + // Start the transaction + smics_temp = read_smi_reg(smi_inst, SMICS); + smics_temp |= SMICS_START; + //smics_temp &= ~(SMICS_PVMODE); + write_smi_reg(smi_inst, smics_temp & 0xffff, SMICS); + inst->count_since_refresh = 0; + //print_smil_registers_ext("refresh 3"); } /***************************************************************************/ static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, enum dma_transfer_direction dma_dir,int num_transfers) { - int smics_temp = 0; - int success = 0; - - dev_info(inst->dev, "smi_init_programmed_transfer"); - print_smil_registers_ext("init 1"); - - write_smi_reg(inst->smi_inst, 0x0, SMIL); + int smics_temp = 0; + int success = 0; - print_smil_registers_ext("init 2"); - smics_temp = read_smi_reg(smi_inst, SMICS); + dev_info(inst->dev, "smi_init_programmed_transfer"); + print_smil_registers_ext("init 1"); - /* Program the transfer count: */ - write_smi_reg(smi_inst, num_transfers, SMIL); + write_smi_reg(inst->smi_inst, 0x0, SMIL); + + print_smil_registers_ext("init 2"); + smics_temp = read_smi_reg(smi_inst, SMICS); + + /* Program the transfer count: */ + write_smi_reg(smi_inst, num_transfers, SMIL); print_smil_registers_ext("init 3"); - /* re-enable and start: */ - smics_temp |= SMICS_CLEAR; - smics_temp |= SMICS_ENABLE; - if(dma_dir == DMA_MEM_TO_DEV) - { - smics_temp |= SMICS_WRITE; - } - - write_smi_reg(smi_inst, smics_temp, SMICS); + /* re-enable and start: */ + smics_temp |= SMICS_CLEAR; + smics_temp |= SMICS_ENABLE; + if(dma_dir == DMA_MEM_TO_DEV) + { + smics_temp |= SMICS_WRITE; + } + + write_smi_reg(smi_inst, smics_temp, SMICS); print_smil_registers_ext("init 4"); - /* IO barrier - to be sure that the last request have - been dispatched in the correct order - */ - mb(); + /* IO barrier - to be sure that the last request have + been dispatched in the correct order + */ + mb(); - // busy wait as long as the transaction is active (taking place) - BUSY_WAIT_WHILE_TIMEOUT(smi_is_active(smi_inst), 1000000U, success); - if (!success) - { - dev_info(inst->dev, "bb errore disable. %u %08X",smi_enabled(smi_inst),read_smi_reg(smi_inst, SMICS)); - - return -2; - } + // busy wait as long as the transaction is active (taking place) + BUSY_WAIT_WHILE_TIMEOUT(smi_is_active(smi_inst), 1000000U, success); + if (!success) + { + dev_info(inst->dev, "smi_init_programmed_transfer error disable. %u %08X", smi_enabled(smi_inst), read_smi_reg(smi_inst, SMICS)); + return -2; + } - // Clear the FIFO (reset it to zero contents) - write_smi_reg(smi_inst, smics_temp, SMICS); - print_smil_registers_ext("init 5"); + // Clear the FIFO (reset it to zero contents) + write_smi_reg(smi_inst, smics_temp, SMICS); + print_smil_registers_ext("init 5"); - return 0; + return 0; } @@ -405,77 +403,77 @@ static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, e ***************************************************************************/ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - long ret = 0; - - //dev_info(inst->dev, "serving ioctl..."); - - switch (cmd) - { - //------------------------------- - case BCM2835_SMI_IOC_GET_SETTINGS: - { - struct smi_settings *settings; - - dev_info(inst->dev, "Reading SMI settings to user."); - settings = bcm2835_smi_get_settings_from_regs(inst->smi_inst); - if (copy_to_user((void *)arg, settings, sizeof(struct smi_settings))) - { - dev_err(inst->dev, "settings copy failed."); - } - break; - } - //------------------------------- - case BCM2835_SMI_IOC_WRITE_SETTINGS: - { - struct smi_settings *settings; - - dev_info(inst->dev, "Setting user's SMI settings."); - settings = bcm2835_smi_get_settings_from_regs(inst->smi_inst); - if (copy_from_user(settings, (void *)arg, sizeof(struct smi_settings))) - { - dev_err(inst->dev, "settings copy failed."); - } - else - { - bcm2835_smi_set_regs_from_settings(inst->smi_inst); - } - break; - } - //------------------------------- - case BCM2835_SMI_IOC_ADDRESS: - { - dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); - //bcm2835_smi_set_address(inst->smi_inst, arg); - break; - } - //------------------------------- - case SMI_STREAM_IOC_SET_STREAM_IN_CHANNEL: - { - //dev_info(inst->dev, "SMI channel: 0x%02x", (int)arg); - //set_address_channel((smi_stream_channel_en)arg); - break; - } - //------------------------------- - case SMI_STREAM_IOC_GET_NATIVE_BUF_SIZE: - { - size_t size = (size_t)(DMA_BOUNCE_BUFFER_SIZE); - dev_info(inst->dev, "Reading native buffer size information"); - if (copy_to_user((void *)arg, &size, sizeof(size_t))) - { - dev_err(inst->dev, "buffer sizes copy failed."); - } - break; - } - //------------------------------- - case SMI_STREAM_IOC_SET_STREAM_STATUS: - { + long ret = 0; + + //dev_info(inst->dev, "serving ioctl..."); + + switch (cmd) + { + //------------------------------- + case BCM2835_SMI_IOC_GET_SETTINGS: + { + struct smi_settings *settings; + + dev_info(inst->dev, "Reading SMI settings to user."); + settings = bcm2835_smi_get_settings_from_regs(inst->smi_inst); + if (copy_to_user((void *)arg, settings, sizeof(struct smi_settings))) + { + dev_err(inst->dev, "settings copy failed."); + } + break; + } + //------------------------------- + case BCM2835_SMI_IOC_WRITE_SETTINGS: + { + struct smi_settings *settings; + + dev_info(inst->dev, "Setting user's SMI settings."); + settings = bcm2835_smi_get_settings_from_regs(inst->smi_inst); + if (copy_from_user(settings, (void *)arg, sizeof(struct smi_settings))) + { + dev_err(inst->dev, "settings copy failed."); + } + else + { + bcm2835_smi_set_regs_from_settings(inst->smi_inst); + } + break; + } + //------------------------------- + case BCM2835_SMI_IOC_ADDRESS: + { + dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); + //bcm2835_smi_set_address(inst->smi_inst, arg); + break; + } + //------------------------------- + case SMI_STREAM_IOC_SET_STREAM_IN_CHANNEL: + { + //dev_info(inst->dev, "SMI channel: 0x%02x", (int)arg); + //set_address_channel((smi_stream_channel_en)arg); + break; + } + //------------------------------- + case SMI_STREAM_IOC_GET_NATIVE_BUF_SIZE: + { + size_t size = (size_t)(DMA_BOUNCE_BUFFER_SIZE); + dev_info(inst->dev, "Reading native buffer size information"); + if (copy_to_user((void *)arg, &size, sizeof(size_t))) + { + dev_err(inst->dev, "buffer sizes copy failed."); + } + break; + } + //------------------------------- + case SMI_STREAM_IOC_SET_STREAM_STATUS: + { ret = set_state((smi_stream_state_en)arg); - - break; - } + + break; + } //------------------------------- - case SMI_STREAM_IOC_SET_FIFO_MULT: - { + case SMI_STREAM_IOC_SET_FIFO_MULT: + { int temp = (int)arg; if (temp > 20 || temp < 2) { @@ -484,11 +482,11 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long } dev_info(inst->dev, "Setting FIFO size multiplier to %d", temp); fifo_mtu_multiplier = temp; - break; - } + break; + } //------------------------------- - case SMI_STREAM_IOC_SET_ADDR_DIR_OFFSET: - { + case SMI_STREAM_IOC_SET_ADDR_DIR_OFFSET: + { int temp = (int)arg; if (temp > 4 || temp < -1) { @@ -497,11 +495,11 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long } dev_info(inst->dev, "Setting address direction indication offset to %d", temp); addr_dir_offset = temp; - break; - } + break; + } //------------------------------- - case SMI_STREAM_IOC_SET_ADDR_CH_OFFSET: - { + case SMI_STREAM_IOC_SET_ADDR_CH_OFFSET: + { int temp = (int)arg; if (temp > 4 || temp < -1) { @@ -510,39 +508,39 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long } dev_info(inst->dev, "Setting address channel indication offset to %d", temp); addr_ch_offset = temp; - break; - } + break; + } //------------------------------- - case SMI_STREAM_IOC_GET_FIFO_MULT: - { - dev_dbg(inst->dev, "Reading FIFO size multiplier of %d", fifo_mtu_multiplier); - if (copy_to_user((void *)arg, &fifo_mtu_multiplier, sizeof(fifo_mtu_multiplier))) - { - dev_err(inst->dev, "fifo_mtu_multiplier copy failed."); - } - break; - } + case SMI_STREAM_IOC_GET_FIFO_MULT: + { + dev_dbg(inst->dev, "Reading FIFO size multiplier of %d", fifo_mtu_multiplier); + if (copy_to_user((void *)arg, &fifo_mtu_multiplier, sizeof(fifo_mtu_multiplier))) + { + dev_err(inst->dev, "fifo_mtu_multiplier copy failed."); + } + break; + } //------------------------------- - case SMI_STREAM_IOC_GET_ADDR_DIR_OFFSET: - { + case SMI_STREAM_IOC_GET_ADDR_DIR_OFFSET: + { dev_dbg(inst->dev, "Reading address direction indication offset of %d", addr_dir_offset); - if (copy_to_user((void *)arg, &addr_dir_offset, sizeof(addr_dir_offset))) - { - dev_err(inst->dev, "addr_dir_offset copy failed."); - } - break; - } + if (copy_to_user((void *)arg, &addr_dir_offset, sizeof(addr_dir_offset))) + { + dev_err(inst->dev, "addr_dir_offset copy failed."); + } + break; + } //------------------------------- - case SMI_STREAM_IOC_GET_ADDR_CH_OFFSET: - { + case SMI_STREAM_IOC_GET_ADDR_CH_OFFSET: + { dev_dbg(inst->dev, "Reading address channel indication offset of %d", addr_ch_offset); - if (copy_to_user((void *)arg, &addr_ch_offset, sizeof(addr_ch_offset))) - { - dev_err(inst->dev, "addr_ch_offset copy failed."); - } - break; - } + if (copy_to_user((void *)arg, &addr_ch_offset, sizeof(addr_ch_offset))) + { + dev_err(inst->dev, "addr_ch_offset copy failed."); + } + break; + } //------------------------------- case SMI_STREAM_IOC_FLUSH_FIFO: { @@ -550,11 +548,11 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long break; } //------------------------------- - default: - dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); - ret = -ENOTTY; - break; - } + default: + dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); + ret = -ENOTTY; + break; + } return ret; } @@ -568,123 +566,123 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long static void stream_smi_read_dma_callback(void *param) { - /* Notify the bottom half that a chunk is ready for user copy */ - struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - uint8_t* buffer_pos; - - - smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - - buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; - buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; - if(kfifo_avail(&inst->rx_fifo) >=DMA_BOUNCE_BUFFER_SIZE/4) - { - kfifo_in(&inst->rx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); - } - else - { - inst->counter_missed++; - } - - if(!(inst->current_read_chunk % 100 )) - { - dev_info(inst->dev,"init programmed read. missed: %u, sema %u",inst->counter_missed,smi_inst->bounce.callback_sem.count); - } - - up(&smi_inst->bounce.callback_sem); - - inst->readable = true; - wake_up_interruptible(&inst->poll_event); - inst->current_read_chunk++; + /* Notify the bottom half that a chunk is ready for user copy */ + struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + uint8_t* buffer_pos; + + + smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + + buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; + buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; + if(kfifo_avail(&inst->rx_fifo) >=DMA_BOUNCE_BUFFER_SIZE/4) + { + kfifo_in(&inst->rx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); + } + else + { + inst->counter_missed++; + } + + if(!(inst->current_read_chunk % 100 )) + { + dev_info(inst->dev,"init programmed read. missed: %u, sema %u",inst->counter_missed,smi_inst->bounce.callback_sem.count); + } + + up(&smi_inst->bounce.callback_sem); + + inst->readable = true; + wake_up_interruptible(&inst->poll_event); + inst->current_read_chunk++; } static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) { - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - inst->count_since_refresh++; - if( (inst->count_since_refresh )>= SMI_TRANSFER_MULTIPLIER) - { - int i; - for(i = 0; i < 1000; i++) - { + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + inst->count_since_refresh++; + if( (inst->count_since_refresh )>= SMI_TRANSFER_MULTIPLIER) + { + int i; + for(i = 0; i < 1000; i++) + { if(!smi_is_active(smi_inst)) { break; } udelay(1); - } - if(i == 1000) - { - print_smil_registers_ext("write dma callback error 1000"); - } - - smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - } + } + if(i == 1000) + { + print_smil_registers_ext("write dma callback error 1000"); + } + + smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + } } static void stream_smi_write_dma_callback(void *param) { - /* Notify the bottom half that a chunk is ready for user copy */ - struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - uint8_t* buffer_pos; - stream_smi_check_and_restart(inst); - - inst->current_read_chunk++; - - buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; - buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; - - if(kfifo_len (&inst->tx_fifo) >= DMA_BOUNCE_BUFFER_SIZE/4) - { - int num_copied = kfifo_out(&inst->tx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); - (void)num_copied; - } - else - { - inst->counter_missed++; - } - - if(!(inst->current_read_chunk % 111 )) - { - dev_info(inst->dev,"init programmed write. missed: %u, sema %u, val %08X",inst->counter_missed,smi_inst->bounce.callback_sem.count,*(uint32_t*) &buffer_pos[0]); - } - - up(&smi_inst->bounce.callback_sem); - - inst->writeable = true; - wake_up_interruptible(&inst->poll_event); - + /* Notify the bottom half that a chunk is ready for user copy */ + struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + uint8_t* buffer_pos; + stream_smi_check_and_restart(inst); + + inst->current_read_chunk++; + + buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; + buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; + + if(kfifo_len (&inst->tx_fifo) >= DMA_BOUNCE_BUFFER_SIZE/4) + { + int num_copied = kfifo_out(&inst->tx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); + (void)num_copied; + } + else + { + inst->counter_missed++; + } + + if(!(inst->current_read_chunk % 111 )) + { + dev_info(inst->dev,"init programmed write. missed: %u, sema %u, val %08X",inst->counter_missed,smi_inst->bounce.callback_sem.count,*(uint32_t*) &buffer_pos[0]); + } + + up(&smi_inst->bounce.callback_sem); + + inst->writeable = true; + wake_up_interruptible(&inst->poll_event); + } -static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic(struct bcm2835_smi_instance *inst, - enum dma_transfer_direction dir, - dma_async_tx_callback callback, void*param) +static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm2835_smi_instance *inst, + enum dma_transfer_direction dir, + dma_async_tx_callback callback, void*param) { - struct dma_async_tx_descriptor *desc = NULL; + struct dma_async_tx_descriptor *desc = NULL; - //printk(KERN_ERR DRIVER_NAME": SUBMIT_PREP %lu\n", (long unsigned int)(inst->dma_chan)); - desc = dmaengine_prep_dma_cyclic(inst->dma_chan, - inst->bounce.phys[0], - DMA_BOUNCE_BUFFER_SIZE, - DMA_BOUNCE_BUFFER_SIZE/4, - dir,DMA_PREP_INTERRUPT | DMA_CTRL_ACK | DMA_PREP_FENCE); - if (!desc) - { - dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); - return NULL; - } + //printk(KERN_ERR DRIVER_NAME": SUBMIT_PREP %lu\n", (long unsigned int)(inst->dma_chan)); + desc = dmaengine_prep_dma_cyclic(inst->dma_chan, + inst->bounce.phys[0], + DMA_BOUNCE_BUFFER_SIZE, + DMA_BOUNCE_BUFFER_SIZE/4, + dir,DMA_PREP_INTERRUPT | DMA_CTRL_ACK | DMA_PREP_FENCE); + if (!desc) + { + dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); + return NULL; + } + + desc->callback = callback; + desc->callback_param = param; - desc->callback = callback; - desc->callback_param = param; - - if (dmaengine_submit(desc) < 0) - { - return NULL; - } - return desc; + if (dmaengine_submit(desc) < 0) + { + return NULL; + } + return desc; } /**************************************************************************** @@ -697,77 +695,77 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe { unsigned int errors = 0; - int ret; - int success; - - dev_info(inst->dev, "Starting cyclic transfer"); - inst->reader_thread_running = true; + int ret; + int success; + + dev_info(inst->dev, "Starting cyclic transfer"); + inst->transfer_thread_running = true; - /* Disable the peripheral: */ - if(smi_disable_sync(inst->smi_inst)) - { + /* Disable the peripheral: */ + if(smi_disable_sync(inst->smi_inst)) + { dev_err(inst->smi_inst->dev, "smi_disable_sync failed"); return -1; - } - write_smi_reg(inst->smi_inst, 0, SMIL); - - sema_init(&inst->smi_inst->bounce.callback_sem, 0); - - spin_lock(&inst->smi_inst->transaction_lock); - ret = smi_init_programmed_transfer(inst->smi_inst, dir, DMA_BOUNCE_BUFFER_SIZE/4); - if (ret != 0) - { - spin_unlock(&inst->smi_inst->transaction_lock); - dev_err(inst->smi_inst->dev, "smi_init_programmed_transfer returned %d", ret); - smi_disable_sync(inst->smi_inst); - return -2; - } - else - { + } + write_smi_reg(inst->smi_inst, 0, SMIL); + sema_init(&inst->smi_inst->bounce.callback_sem, 0); + + spin_lock(&inst->smi_inst->transaction_lock); + ret = smi_init_programmed_transfer(inst->smi_inst, dir, DMA_BOUNCE_BUFFER_SIZE/4); + if (ret != 0) + { spin_unlock(&inst->smi_inst->transaction_lock); - } - inst->current_read_chunk = 0; - inst->counter_missed = 0; - if(!errors) - { - struct dma_async_tx_descriptor *desc = NULL; - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - spin_lock(&smi_inst->transaction_lock); - desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst); - - if(desc) - { - dma_async_issue_pending(smi_inst->dma_chan); - } - else - { - errors = 1; - } - spin_unlock(&smi_inst->transaction_lock); - } - smi_refresh_dma_command(inst->smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - BUSY_WAIT_WHILE_TIMEOUT(!smi_is_active(inst->smi_inst), 1000000U, success); - print_smil_registers_ext("post init 0"); - return errors; + dev_err(inst->smi_inst->dev, "smi_init_programmed_transfer returned %d", ret); + smi_disable_sync(inst->smi_inst); + return -2; + } + else + { + spin_unlock(&inst->smi_inst->transaction_lock); + } + inst->current_read_chunk = 0; + inst->counter_missed = 0; + if(!errors) + { + struct dma_async_tx_descriptor *desc = NULL; + struct bcm2835_smi_instance *smi_inst = inst->smi_inst; + spin_lock(&smi_inst->transaction_lock); + desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst); + + if(desc) + { + dma_async_issue_pending(smi_inst->dma_chan); + } + else + { + errors = 1; + } + spin_unlock(&smi_inst->transaction_lock); + } + smi_refresh_dma_command(inst->smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + BUSY_WAIT_WHILE_TIMEOUT(!smi_is_active(inst->smi_inst), 1000000U, success); + print_smil_registers_ext("post init 0"); + return errors; } +/***************************************************************************/ void transfer_thread_stop(struct bcm2835_smi_dev_instance *inst) { - //int errors = 0; - //dev_info(inst->dev, "Reader state became idle, terminating dma %u %u", (inst->address_changed) ,errors); - print_smil_registers_ext("thread stop 0"); - spin_lock(&inst->smi_inst->transaction_lock); + //int errors = 0; + //dev_info(inst->dev, "Reader state became idle, terminating dma %u %u", (inst->address_changed) ,errors); + print_smil_registers_ext("thread stop 0"); + spin_lock(&inst->smi_inst->transaction_lock); dmaengine_terminate_sync(inst->smi_inst->dma_chan); spin_unlock(&inst->smi_inst->transaction_lock); - - //dev_info(inst->dev, "Reader state became idle, terminating smi transaction"); - smi_disable_sync(inst->smi_inst); - bcm2835_smi_set_regs_from_settings(inst->smi_inst); - - //dev_info(inst->dev, "Left reader thread"); - inst->reader_thread_running = false; + + //dev_info(inst->dev, "Reader state became idle, terminating smi transaction"); + smi_disable_sync(inst->smi_inst); + bcm2835_smi_set_regs_from_settings(inst->smi_inst); + + //dev_info(inst->dev, "Left reader thread"); + inst->transfer_thread_running = false; inst->reader_waiting_sema = false; - return ; + return ; } @@ -779,74 +777,64 @@ void transfer_thread_stop(struct bcm2835_smi_dev_instance *inst) static int smi_stream_open(struct inode *inode, struct file *file) { - int dev = iminor(inode); + int dev = iminor(inode); - dev_dbg(inst->dev, "SMI device opened."); + dev_dbg(inst->dev, "SMI device opened."); - if (dev != DEVICE_MINOR) - { - dev_err(inst->dev, "smi_stream_open: Unknown minor device: %d", dev); // error here - return -ENXIO; - } - - // preinit the thread handlers to NULL - inst->reader_thread = NULL; - inst->writer_thread = NULL; - - // create the data fifo ( N x dma_bounce size ) - // we want this fifo to be deep enough to allow the application react without - // loosing stream elements - - inst->rx_fifo_buffer = vmalloc(fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); - if (!inst->rx_fifo_buffer) - { - printk(KERN_ERR DRIVER_NAME": error rx_fifo_buffer vmallok failed\n"); - return -ENOMEM; - } - - inst->tx_fifo_buffer = vmalloc(fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); + if (dev != DEVICE_MINOR) + { + dev_err(inst->dev, "smi_stream_open: Unknown minor device: %d", dev); // error here + return -ENXIO; + } + + // create the data fifo ( N x dma_bounce size ) + // we want this fifo to be deep enough to allow the application react without + // loosing stream elements + inst->rx_fifo_buffer = vmalloc(fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); + if (!inst->rx_fifo_buffer) + { + printk(KERN_ERR DRIVER_NAME": error rx_fifo_buffer vmallok failed\n"); + return -ENOMEM; + } + + inst->tx_fifo_buffer = vmalloc(fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); if (!inst->tx_fifo_buffer) - { - printk(KERN_ERR DRIVER_NAME": error tx_fifo_buffer vmallok failed\n"); + { + printk(KERN_ERR DRIVER_NAME": error tx_fifo_buffer vmallok failed\n"); vfree(inst->rx_fifo_buffer); - return -ENOMEM; - } + return -ENOMEM; + } - kfifo_init(&inst->rx_fifo, inst->rx_fifo_buffer, fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); - kfifo_init(&inst->tx_fifo, inst->tx_fifo_buffer, fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); - // when file is being openned, stream state is still idle + kfifo_init(&inst->rx_fifo, inst->rx_fifo_buffer, fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); + kfifo_init(&inst->tx_fifo, inst->tx_fifo_buffer, fifo_mtu_multiplier * DMA_BOUNCE_BUFFER_SIZE); + // when file is being openned, stream state is still idle set_state(smi_stream_idle); - + inst->address_changed = 0; - return 0; + return 0; } /***************************************************************************/ static int smi_stream_release(struct inode *inode, struct file *file) { - int dev = iminor(inode); + int dev = iminor(inode); - dev_info(inst->dev, "smi_stream_release: closing device: %d", dev); + dev_info(inst->dev, "smi_stream_release: closing device: %d", dev); - if (dev != DEVICE_MINOR) - { - dev_err(inst->dev, "smi_stream_release: Unknown minor device %d", dev); - return -ENXIO; - } + if (dev != DEVICE_MINOR) + { + dev_err(inst->dev, "smi_stream_release: Unknown minor device %d", dev); + return -ENXIO; + } - // make sure stream is idle - set_state(smi_stream_idle); + // make sure stream is idle + set_state(smi_stream_idle); - if (inst->reader_thread != NULL) kthread_stop(inst->reader_thread); - if (inst->writer_thread != NULL) kthread_stop(inst->writer_thread); - - if (inst->rx_fifo_buffer) vfree(inst->rx_fifo_buffer); - if (inst->tx_fifo_buffer) vfree(inst->tx_fifo_buffer); + if (inst->rx_fifo_buffer) vfree(inst->rx_fifo_buffer); + if (inst->tx_fifo_buffer) vfree(inst->tx_fifo_buffer); - inst->rx_fifo_buffer = NULL; + inst->rx_fifo_buffer = NULL; inst->tx_fifo_buffer = NULL; - inst->reader_thread = NULL; - inst->writer_thread = NULL; inst->address_changed = 0; return 0; @@ -855,11 +843,11 @@ static int smi_stream_release(struct inode *inode, struct file *file) /***************************************************************************/ static ssize_t smi_stream_read_file_fifo(struct file *file, char __user *buf, size_t count, loff_t *ppos) { - int ret = 0; - unsigned int copied = 0; - - if (buf == NULL) - { + int ret = 0; + unsigned int copied = 0; + + if (buf == NULL) + { //dev_info(inst->dev, "Flushing internal rx_kfifo"); if (mutex_lock_interruptible(&inst->read_lock)) { @@ -868,9 +856,9 @@ static ssize_t smi_stream_read_file_fifo(struct file *file, char __user *buf, si kfifo_reset_out(&inst->rx_fifo); mutex_unlock(&inst->read_lock); inst->invalidate_rx_buffers = 1; - return 0; + return 0; } - + if (mutex_lock_interruptible(&inst->read_lock)) { return -EINTR; @@ -878,76 +866,75 @@ static ssize_t smi_stream_read_file_fifo(struct file *file, char __user *buf, si ret = kfifo_to_user(&inst->rx_fifo, buf, count, &copied); mutex_unlock(&inst->read_lock); - return ret < 0 ? ret : (ssize_t)copied; + return ret < 0 ? ret : (ssize_t)copied; } /***************************************************************************/ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr, size_t count, loff_t *offs) { - int ret = 0; - unsigned int num_bytes_available = 0; - unsigned int num_to_push = 0; - unsigned int actual_copied = 0; - - if (mutex_lock_interruptible(&inst->write_lock)) - { - return -EAGAIN; - } - - if (kfifo_is_full(&inst->tx_fifo)) - { - if(wait_event_interruptible(inst->poll_event, !kfifo_is_full(&inst->tx_fifo))) - { - mutex_unlock(&inst->write_lock); - return -EAGAIN; - } - } - - // check how many bytes are available in the tx fifo - num_bytes_available = kfifo_avail(&inst->tx_fifo); - num_to_push = num_bytes_available > count ? count : num_bytes_available; - ret = kfifo_from_user(&inst->tx_fifo, user_ptr, num_to_push, &actual_copied); + int ret = 0; + unsigned int num_bytes_available = 0; + unsigned int num_to_push = 0; + unsigned int actual_copied = 0; + + if (mutex_lock_interruptible(&inst->write_lock)) + { + return -EAGAIN; + } + + if (kfifo_is_full(&inst->tx_fifo)) + { + if(wait_event_interruptible(inst->poll_event, !kfifo_is_full(&inst->tx_fifo))) + { + mutex_unlock(&inst->write_lock); + return -EAGAIN; + } + } + + // check how many bytes are available in the tx fifo + num_bytes_available = kfifo_avail(&inst->tx_fifo); + num_to_push = num_bytes_available > count ? count : num_bytes_available; + ret = kfifo_from_user(&inst->tx_fifo, user_ptr, num_to_push, &actual_copied); - mutex_unlock(&inst->write_lock); + mutex_unlock(&inst->write_lock); - return ret ? ret : (ssize_t)actual_copied; + return ret ? ret : (ssize_t)actual_copied; } /***************************************************************************/ static unsigned int smi_stream_poll(struct file *filp, struct poll_table_struct *wait) { - __poll_t mask = 0; - - - poll_wait(filp, &inst->poll_event, wait); + __poll_t mask = 0; + poll_wait(filp, &inst->poll_event, wait); + if (!kfifo_is_empty(&inst->rx_fifo)) { //dev_info(inst->dev, "poll_wait result => readable=%d", inst->readable); - inst->readable = false; - mask |= ( POLLIN | POLLRDNORM ); - } - - if (!kfifo_is_full(&inst->rx_fifo)) - { + inst->readable = false; + mask |= ( POLLIN | POLLRDNORM ); + } + + if (!kfifo_is_full(&inst->rx_fifo)) + { //dev_info(inst->dev, "poll_wait result => writeable=%d", inst->writeable); - inst->writeable = false; - mask |= ( POLLOUT | POLLWRNORM ); - } + inst->writeable = false; + mask |= ( POLLOUT | POLLWRNORM ); + } - return mask; + return mask; } /***************************************************************************/ static const struct file_operations smi_stream_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = smi_stream_ioctl, - .open = smi_stream_open, - .release = smi_stream_release, - .read = smi_stream_read_file_fifo, - .write = smi_stream_write_file, - .poll = smi_stream_poll, + .owner = THIS_MODULE, + .unlocked_ioctl = smi_stream_ioctl, + .open = smi_stream_open, + .release = smi_stream_release, + .read = smi_stream_read_file_fifo, + .write = smi_stream_write_file, + .poll = smi_stream_poll, }; /**************************************************************************** @@ -964,12 +951,12 @@ static struct device *smi_stream_dev; static int smi_stream_dev_probe(struct platform_device *pdev) { - int err; - void *ptr_err; - struct device *dev = &pdev->dev; - struct device_node *smi_node; + int err; + void *ptr_err; + struct device *dev = &pdev->dev; + struct device_node *smi_node; - printk(KERN_INFO DRIVER_NAME": smi_stream_dev_probe (fifo_mtu_multiplier=%d, addr_dir_offset=%d, addr_ch_offset=%d)\n", + printk(KERN_INFO DRIVER_NAME": smi_stream_dev_probe (fifo_mtu_multiplier=%d, addr_dir_offset=%d, addr_ch_offset=%d)\n", fifo_mtu_multiplier, addr_dir_offset, addr_ch_offset); @@ -978,129 +965,123 @@ static int smi_stream_dev_probe(struct platform_device *pdev) if (fifo_mtu_multiplier > 32 || fifo_mtu_multiplier < 2) { dev_err(dev, "Parameter error: 2 4 || addr_dir_offset < -1) { dev_err(dev, "Parameter error: 0<=addr_dir_offset<=4 or (-1 - unused)"); - return -EINVAL; + return -EINVAL; } if (addr_ch_offset > 4 || addr_ch_offset < -1) { dev_err(dev, "Parameter error: 0<=addr_ch_offset<=4 or (-1 - unused)"); - return -EINVAL; + return -EINVAL; } if (addr_dir_offset == addr_ch_offset && addr_dir_offset != -1) { dev_err(dev, "Parameter error: addr_ch_offset should be different than addr_dir_offset"); - return -EINVAL; + return -EINVAL; } - if (!dev->of_node) - { - dev_err(dev, "No device tree node supplied!"); - return -EINVAL; - } + if (!dev->of_node) + { + dev_err(dev, "No device tree node supplied!"); + return -EINVAL; + } - smi_node = of_parse_phandle(dev->of_node, "smi_handle", 0); - if (!smi_node) - { - dev_err(dev, "No such property: smi_handle"); - return -ENXIO; - } + smi_node = of_parse_phandle(dev->of_node, "smi_handle", 0); + if (!smi_node) + { + dev_err(dev, "No such property: smi_handle"); + return -ENXIO; + } - // Allocate buffers and instance data (of type struct bcm2835_smi_dev_instance) - inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); - if (!inst) - { - return -ENOMEM; - } + // Allocate buffers and instance data (of type struct bcm2835_smi_dev_instance) + inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); + if (!inst) + { + return -ENOMEM; + } - inst->smi_inst = bcm2835_smi_get(smi_node); - if (!inst->smi_inst) - { - return -EPROBE_DEFER; - } + inst->smi_inst = bcm2835_smi_get(smi_node); + if (!inst->smi_inst) + { + return -EPROBE_DEFER; + } - //smi_stream_print_smi_inst(inst->smi_inst); + //smi_stream_print_smi_inst(inst->smi_inst); - inst->dev = dev; + inst->dev = dev; - /* Create character device entries */ - err = alloc_chrdev_region(&smi_stream_devid, DEVICE_MINOR, 1, DEVICE_NAME); - if (err != 0) - { - dev_err(inst->dev, "unable to allocate device number"); - return -ENOMEM; - } + /* Create character device entries */ + err = alloc_chrdev_region(&smi_stream_devid, DEVICE_MINOR, 1, DEVICE_NAME); + if (err != 0) + { + dev_err(inst->dev, "unable to allocate device number"); + return -ENOMEM; + } - // init the char device with file operations - cdev_init(&smi_stream_cdev, &smi_stream_fops); - smi_stream_cdev.owner = THIS_MODULE; - err = cdev_add(&smi_stream_cdev, smi_stream_devid, 1); - if (err != 0) - { - dev_err(inst->dev, "unable to register device"); - err = -ENOMEM; - unregister_chrdev_region(smi_stream_devid, 1); - dev_err(dev, "could not load smi_stream_dev"); - return err; - } + // init the char device with file operations + cdev_init(&smi_stream_cdev, &smi_stream_fops); + smi_stream_cdev.owner = THIS_MODULE; + err = cdev_add(&smi_stream_cdev, smi_stream_devid, 1); + if (err != 0) + { + dev_err(inst->dev, "unable to register device"); + err = -ENOMEM; + unregister_chrdev_region(smi_stream_devid, 1); + dev_err(dev, "could not load smi_stream_dev"); + return err; + } - // Create sysfs entries with "smi-stream-dev" - smi_stream_class = class_create(THIS_MODULE, DEVICE_NAME); - ptr_err = smi_stream_class; - if (IS_ERR(ptr_err)) - { - cdev_del(&smi_stream_cdev); - unregister_chrdev_region(smi_stream_devid, 1); - dev_err(dev, "could not load smi_stream_dev"); - return PTR_ERR(ptr_err); - } + // Create sysfs entries with "smi-stream-dev" + smi_stream_class = class_create(THIS_MODULE, DEVICE_NAME); + ptr_err = smi_stream_class; + if (IS_ERR(ptr_err)) + { + cdev_del(&smi_stream_cdev); + unregister_chrdev_region(smi_stream_devid, 1); + dev_err(dev, "could not load smi_stream_dev"); + return PTR_ERR(ptr_err); + } - printk(KERN_INFO DRIVER_NAME": creating a device and registering it with sysfs\n"); - smi_stream_dev = device_create(smi_stream_class, // pointer to the struct class that this device should be registered to - NULL, // pointer to the parent struct device of this new device, if any - smi_stream_devid, // the dev_t for the char device to be added - NULL, // the data to be added to the device for callbacks - "smi"); // string for the device's name + printk(KERN_INFO DRIVER_NAME": creating a device and registering it with sysfs\n"); + smi_stream_dev = device_create(smi_stream_class, // pointer to the struct class that this device should be registered to + NULL, // pointer to the parent struct device of this new device, if any + smi_stream_devid, // the dev_t for the char device to be added + NULL, // the data to be added to the device for callbacks + "smi"); // string for the device's name - ptr_err = smi_stream_dev; - if (IS_ERR(ptr_err)) - { - class_destroy(smi_stream_class); - cdev_del(&smi_stream_cdev); - unregister_chrdev_region(smi_stream_devid, 1); - dev_err(dev, "could not load smi_stream_dev"); - return PTR_ERR(ptr_err); - } + ptr_err = smi_stream_dev; + if (IS_ERR(ptr_err)) + { + class_destroy(smi_stream_class); + cdev_del(&smi_stream_cdev); + unregister_chrdev_region(smi_stream_devid, 1); + dev_err(dev, "could not load smi_stream_dev"); + return PTR_ERR(ptr_err); + } - smi_setup_clock(inst->smi_inst); + smi_setup_clock(inst->smi_inst); - // Streaming instance initializations - inst->reader_thread = NULL; - inst->writer_thread = NULL; + // Streaming instance initializations inst->invalidate_rx_buffers = 0; inst->invalidate_tx_buffers = 0; - init_waitqueue_head(&inst->poll_event); - inst->readable = false; - inst->writeable = false; - inst->reader_thread_running = false; - inst->writer_thread_running = false; + init_waitqueue_head(&inst->poll_event); + inst->readable = false; + inst->writeable = false; + inst->transfer_thread_running = false; inst->reader_waiting_sema = false; inst->writer_waiting_sema = false; - mutex_init(&inst->read_lock); - mutex_init(&inst->write_lock); - spin_lock_init(&inst->state_lock); - - //inst->reader_thread = kthread_create(test_thread_stream_function, NULL, "smi-test-thread"); - - dev_info(inst->dev, "initialised"); - //wake_up_process(inst->reader_thread); - return 0; + mutex_init(&inst->read_lock); + mutex_init(&inst->write_lock); + spin_lock_init(&inst->state_lock); + + dev_info(inst->dev, "initialised"); + return 0; } /**************************************************************************** @@ -1111,16 +1092,16 @@ static int smi_stream_dev_probe(struct platform_device *pdev) static int smi_stream_dev_remove(struct platform_device *pdev) { - if (inst->reader_thread != NULL) kthread_stop(inst->reader_thread); - inst->reader_thread = NULL; - - device_destroy(smi_stream_class, smi_stream_devid); - class_destroy(smi_stream_class); - cdev_del(&smi_stream_cdev); - unregister_chrdev_region(smi_stream_devid, 1); + //if (inst->reader_thread != NULL) kthread_stop(inst->reader_thread); + //inst->reader_thread = NULL; + + device_destroy(smi_stream_class, smi_stream_devid); + class_destroy(smi_stream_class); + cdev_del(&smi_stream_cdev); + unregister_chrdev_region(smi_stream_devid, 1); - dev_info(inst->dev, DRIVER_NAME": smi-stream dev removed"); - return 0; + dev_info(inst->dev, DRIVER_NAME": smi-stream dev removed"); + return 0; } /**************************************************************************** @@ -1130,20 +1111,20 @@ static int smi_stream_dev_remove(struct platform_device *pdev) ***************************************************************************/ static const struct of_device_id smi_stream_dev_of_match[] = { - {.compatible = "brcm,bcm2835-smi-dev",}, - { /* sentinel */ }, + {.compatible = "brcm,bcm2835-smi-dev",}, + { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, smi_stream_dev_of_match); static struct platform_driver smi_stream_dev_driver = { - .probe = smi_stream_dev_probe, - .remove = smi_stream_dev_remove, - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = smi_stream_dev_of_match, - }, + .probe = smi_stream_dev_probe, + .remove = smi_stream_dev_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = smi_stream_dev_of_match, + }, }; module_platform_driver(smi_stream_dev_driver); diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index 5dcc3c6..789e2d4 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -18,12 +18,12 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure * Date: 2024-03-14 - * Time: 22:58:51 + * Time: 23:08:06 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 51, - .tm_min = 58, - .tm_hour = 22, + .tm_sec = 6, + .tm_min = 8, + .tm_hour = 23, .tm_mday = 14, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ @@ -38,394 +38,394 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 984 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 1009 rx_fifo.wr_addr[8] -.sym 1031 $PACKER_VCC_NET -.sym 1046 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 972 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 974 $PACKER_GND_NET +.sym 976 w_rx_09_fifo_data[3] +.sym 980 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1000 rx_fifo.wr_addr[6] .sym 1054 o_iq_tx_clk_p$SB_IO_OUT -.sym 1055 $PACKER_VCC_NET .sym 1061 $PACKER_GND_NET .sym 1062 $PACKER_GND_NET .sym 1066 $PACKER_VCC_NET .sym 1067 $PACKER_VCC_NET .sym 1069 $PACKER_VCC_NET .sym 1071 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1074 $PACKER_VCC_NET -.sym 1077 $PACKER_GND_NET -.sym 1085 $PACKER_GND_NET -.sym 1086 $PACKER_VCC_NET -.sym 1088 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 1089 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 1090 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 1091 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 1092 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] -.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 1094 w_rx_fifo_full -.sym 1095 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 1120 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 1121 rx_fifo.wr_addr[3] -.sym 1123 rx_fifo.wr_addr[5] -.sym 1125 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 1126 $PACKER_VCC_NET -.sym 1127 rx_fifo.wr_addr[7] -.sym 1129 rx_fifo.wr_addr[3] -.sym 1130 $PACKER_VCC_NET -.sym 1132 rx_fifo.wr_addr[9] -.sym 1136 rx_fifo.wr_addr[1] -.sym 1160 $PACKER_GND_NET -.sym 1165 rx_fifo.wr_addr[1] +.sym 1072 $PACKER_GND_NET +.sym 1076 $PACKER_VCC_NET +.sym 1080 $PACKER_GND_NET +.sym 1084 $PACKER_VCC_NET +.sym 1085 $PACKER_VCC_NET +.sym 1088 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 1090 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 1091 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 1094 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 1095 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 1128 i_rst_b$SB_IO_IN .sym 1173 w_lvds_rx_09_d0 .sym 1174 w_lvds_rx_09_d1 .sym 1183 $PACKER_VCC_NET .sym 1184 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1196 $PACKER_VCC_NET -.sym 1202 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 1203 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 1204 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 1206 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 1208 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 1209 rx_fifo.rd_addr_gray_wr_r[0] -.sym 1230 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 1234 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 1235 w_rx_fifo_full -.sym 1242 i_rst_b$SB_IO_IN -.sym 1246 $PACKER_VCC_NET -.sym 1261 w_rx_fifo_full -.sym 1269 w_lvds_rx_09_d0 -.sym 1271 w_lvds_rx_09_d1 -.sym 1282 w_lvds_rx_24_d0 +.sym 1191 $PACKER_VCC_NET +.sym 1203 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 1204 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 1205 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 1206 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 1207 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 1209 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 1234 w_lvds_rx_09_d0 +.sym 1246 w_lvds_rx_09_d1 +.sym 1248 $PACKER_VCC_NET +.sym 1259 $PACKER_VCC_NET .sym 1287 o_iq_tx_clk_p$SB_IO_OUT .sym 1297 $PACKER_VCC_NET -.sym 1313 $PACKER_VCC_NET -.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 1317 w_rx_09_fifo_data[0] -.sym 1318 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 1319 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 1320 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 1321 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 1322 w_rx_09_fifo_data[1] -.sym 1323 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 1343 rx_fifo.rd_addr_gray_wr[0] +.sym 1310 $PACKER_VCC_NET +.sym 1317 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 1318 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 1319 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 1320 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 1321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 1322 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 1323 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 1349 w_lvds_rx_09_d0 +.sym 1350 $PACKER_VCC_NET +.sym 1393 w_lvds_rx_09_d1 .sym 1401 w_lvds_rx_24_d0 .sym 1402 w_lvds_rx_24_d1 .sym 1411 $PACKER_VCC_NET .sym 1412 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1416 $PACKER_VCC_NET -.sym 1430 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 1431 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 1432 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 1433 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 1434 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 1459 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 1463 i_rst_b$SB_IO_IN -.sym 1474 w_lvds_rx_24_d1 -.sym 1481 $PACKER_VCC_NET -.sym 1510 i_rst_b$SB_IO_IN -.sym 1545 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 1547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 1550 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 1699 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 1714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 1880 w_rx_09_fifo_data[13] -.sym 1882 w_rx_09_fifo_data[15] -.sym 1883 rx_fifo.mem_q.0.3_WDATA_1 -.sym 1884 w_rx_09_fifo_data[17] -.sym 1886 rx_fifo.mem_q.0.3_WDATA -.sym 1914 o_led0$SB_IO_OUT -.sym 1939 w_rx_09_fifo_data[10] -.sym 2063 w_rx_24_fifo_data[14] -.sym 2064 w_rx_24_fifo_data[16] -.sym 2065 w_rx_24_fifo_data[17] -.sym 2066 w_rx_24_fifo_data[22] -.sym 2067 w_rx_24_fifo_data[18] -.sym 2068 rx_fifo.mem_q.0.3_WDATA_2 -.sym 2069 rx_fifo.mem_q.0.3_WDATA_3 -.sym 2070 w_rx_24_fifo_data[15] -.sym 2072 rx_fifo.wr_addr[5] -.sym 2073 rx_fifo.wr_addr[5] -.sym 2079 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 2091 o_led1$SB_IO_OUT -.sym 2093 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2107 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2122 w_rx_09_fifo_data[11] -.sym 2124 w_rx_09_fifo_data[17] -.sym 2137 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2152 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2155 w_rx_09_fifo_data[10] -.sym 2180 w_rx_09_fifo_data[12] -.sym 2183 w_rx_09_fifo_data[14] -.sym 2209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2212 w_rx_09_fifo_data[10] +.sym 1424 $PACKER_VCC_NET +.sym 1431 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 1432 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 1435 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 1436 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 1437 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 1464 w_lvds_rx_24_d1 +.sym 1470 w_lvds_rx_24_d0 +.sym 1499 $PACKER_VCC_NET +.sym 1560 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 1883 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 1885 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 1911 w_smi_data_direction +.sym 1941 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 1946 w_rx_09_fifo_data[19] +.sym 1954 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2063 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 2064 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 2066 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 2067 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 2068 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 2070 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 2104 smi_ctrl_ins.int_cnt_rx[4] +.sym 2115 w_rx_09_fifo_data[29] +.sym 2140 w_rx_24_fifo_data[26] +.sym 2144 w_rx_24_fifo_data[24] +.sym 2163 w_rx_24_fifo_data[22] +.sym 2165 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2166 w_rx_09_fifo_data[23] +.sym 2167 w_rx_09_fifo_data[22] +.sym 2168 w_rx_09_fifo_data[25] +.sym 2172 w_rx_09_fifo_data[21] +.sym 2176 w_rx_09_fifo_data[19] +.sym 2182 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2183 w_rx_09_fifo_data[27] +.sym 2187 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2188 w_rx_09_fifo_data[23] +.sym 2192 w_rx_24_fifo_data[22] +.sym 2193 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2194 w_rx_09_fifo_data[22] +.sym 2204 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2206 w_rx_09_fifo_data[27] +.sym 2210 w_rx_09_fifo_data[19] +.sym 2211 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 2221 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2223 w_rx_09_fifo_data[14] -.sym 2228 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2229 w_rx_09_fifo_data[12] +.sym 2223 w_rx_09_fifo_data[21] +.sym 2228 w_rx_09_fifo_data[25] +.sym 2230 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2232 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2234 w_rx_09_fifo_data[25] -.sym 2235 w_rx_09_fifo_data[19] -.sym 2236 w_rx_09_fifo_data[21] -.sym 2237 rx_fifo.mem_i.0.1_WDATA_2 -.sym 2238 rx_fifo.mem_i.0.0_WDATA_2 -.sym 2239 w_rx_09_fifo_data[23] -.sym 2240 rx_fifo.mem_i.0.0_WDATA_3 -.sym 2241 rx_fifo.mem_i.0.0_WDATA_1 -.sym 2242 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2244 w_rx_09_fifo_data[0] -.sym 2245 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2251 rx_fifo.rd_addr[1] -.sym 2254 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2256 o_led1$SB_IO_OUT -.sym 2258 w_rx_24_fifo_data[17] -.sym 2260 w_rx_24_fifo_data[22] -.sym 2262 w_rx_24_fifo_data[12] -.sym 2266 w_rx_24_fifo_data[13] -.sym 2270 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2293 w_rx_09_fifo_data[18] -.sym 2301 w_rx_09_fifo_data[16] -.sym 2310 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2316 w_rx_09_fifo_data[20] -.sym 2350 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2353 w_rx_09_fifo_data[18] +.sym 2234 w_smi_data_output[2] +.sym 2235 w_smi_data_output[3] +.sym 2236 w_smi_data_output[1] +.sym 2237 rx_fifo.mem_i.0.0_WDATA +.sym 2238 w_smi_data_output[0] +.sym 2239 w_smi_data_output[6] +.sym 2240 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 2241 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 2246 w_rx_09_fifo_data[25] +.sym 2251 w_rx_24_fifo_data[22] +.sym 2256 w_rx_09_fifo_data[21] +.sym 2259 rx_fifo.mem_i.0.1_WDATA_3 +.sym 2268 rx_fifo.mem_i.0.2_WDATA_2 +.sym 2272 w_rx_24_fifo_data[22] +.sym 2277 w_rx_09_fifo_data[14] +.sym 2290 w_rx_09_fifo_data[26] +.sym 2291 w_rx_09_fifo_data[28] +.sym 2292 w_rx_09_fifo_data[24] +.sym 2294 w_rx_09_fifo_data[20] +.sym 2295 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2298 w_rx_09_fifo_data[29] +.sym 2299 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2303 w_rx_24_fifo_data[24] +.sym 2307 w_rx_24_fifo_data[26] +.sym 2310 w_rx_09_fifo_data[22] +.sym 2320 w_rx_09_fifo_data[29] +.sym 2323 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2326 w_rx_09_fifo_data[26] +.sym 2328 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2329 w_rx_24_fifo_data[26] +.sym 2333 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2334 w_rx_24_fifo_data[24] +.sym 2335 w_rx_09_fifo_data[24] +.sym 2338 w_rx_09_fifo_data[24] +.sym 2340 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2345 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2347 w_rx_09_fifo_data[26] +.sym 2350 w_rx_09_fifo_data[22] +.sym 2352 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 2357 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2359 w_rx_09_fifo_data[16] -.sym 2364 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2365 w_rx_09_fifo_data[20] +.sym 2358 w_rx_09_fifo_data[28] +.sym 2362 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2364 w_rx_09_fifo_data[20] .sym 2366 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2367 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2369 w_rx_24_fifo_data[24] -.sym 2370 w_rx_24_fifo_data[26] -.sym 2371 rx_fifo.mem_i.0.0_WDATA -.sym 2372 w_rx_24_fifo_data[19] -.sym 2373 rx_fifo.mem_i.0.2_WDATA_3 -.sym 2374 w_rx_24_fifo_data[21] -.sym 2375 w_rx_24_fifo_data[30] -.sym 2376 w_rx_24_fifo_data[28] -.sym 2378 w_rx_fifo_pulled_data[22] -.sym 2383 w_rx_09_fifo_data[20] -.sym 2384 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2388 w_rx_09_fifo_data[25] -.sym 2392 o_led1$SB_IO_OUT -.sym 2394 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2396 w_rx_24_fifo_data[21] -.sym 2402 o_led1$SB_IO_OUT -.sym 2403 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2405 rx_fifo.mem_q.0.2_WDATA_2 -.sym 2407 w_rx_09_fifo_data[10] -.sym 2415 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2424 o_led1$SB_IO_OUT -.sym 2427 w_rx_09_fifo_data[9] -.sym 2429 w_rx_09_fifo_data[22] -.sym 2430 w_rx_24_fifo_data[9] -.sym 2442 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2445 w_rx_09_fifo_data[7] -.sym 2467 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2470 w_rx_09_fifo_data[9] -.sym 2485 w_rx_09_fifo_data[7] +.sym 2369 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 2370 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 2371 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 2372 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 2373 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 2374 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 2375 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 2376 rx_fifo.mem_i.0.0_WDATA_1 +.sym 2378 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2379 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2381 w_rx_09_fifo_data[31] +.sym 2386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 2388 w_smi_data_output[2] +.sym 2391 w_rx_09_fifo_data[28] +.sym 2392 w_smi_data_output[1] +.sym 2393 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 2394 w_rx_24_fifo_data[17] +.sym 2399 rx_fifo.rd_addr[8] +.sym 2403 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2404 w_rx_24_fifo_data[19] +.sym 2405 w_rx_09_fifo_data[15] +.sym 2406 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2412 w_rx_24_fifo_data[14] +.sym 2423 w_rx_24_fifo_data[16] +.sym 2425 w_rx_09_fifo_data[17] +.sym 2427 w_rx_24_fifo_data[20] +.sym 2433 w_rx_24_fifo_data[18] +.sym 2435 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2442 w_rx_09_fifo_data[16] +.sym 2443 w_rx_09_fifo_data[18] +.sym 2445 w_rx_09_fifo_data[20] +.sym 2450 w_rx_09_fifo_data[15] +.sym 2451 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2452 w_rx_09_fifo_data[14] +.sym 2455 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2456 w_rx_09_fifo_data[17] +.sym 2462 w_rx_09_fifo_data[16] +.sym 2463 w_rx_24_fifo_data[16] +.sym 2464 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2467 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2468 w_rx_09_fifo_data[18] +.sym 2469 w_rx_24_fifo_data[18] +.sym 2473 w_rx_09_fifo_data[15] +.sym 2474 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2480 w_rx_09_fifo_data[14] +.sym 2481 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2486 w_rx_09_fifo_data[16] .sym 2488 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2491 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2492 w_rx_09_fifo_data[22] -.sym 2497 w_rx_09_fifo_data[9] -.sym 2498 o_led1$SB_IO_OUT -.sym 2499 w_rx_24_fifo_data[9] +.sym 2492 w_rx_24_fifo_data[20] +.sym 2493 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2494 w_rx_09_fifo_data[20] +.sym 2499 w_rx_09_fifo_data[18] +.sym 2500 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 2501 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2502 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2504 rx_fifo.mem_q.0.2_WDATA -.sym 2505 w_rx_09_fifo_data[5] -.sym 2506 rx_fifo.mem_q.0.1_WDATA_1 -.sym 2507 rx_fifo.mem_q.0.1_WDATA -.sym 2508 rx_fifo.mem_i.0.2_WDATA_2 -.sym 2509 w_rx_09_fifo_data[26] -.sym 2510 w_rx_09_fifo_data[28] -.sym 2511 w_rx_09_fifo_data[7] -.sym 2513 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2514 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2516 rx_fifo.rd_addr[4] -.sym 2517 w_rx_24_fifo_data[30] -.sym 2518 o_led1$SB_IO_OUT -.sym 2520 rx_fifo.rd_addr[8] -.sym 2528 rx_fifo.wr_addr[5] -.sym 2530 rx_fifo.wr_addr[3] -.sym 2531 rx_fifo.wr_addr[1] -.sym 2534 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2542 w_rx_24_fifo_data[8] -.sym 2557 w_rx_24_fifo_data[9] -.sym 2561 o_iq_tx_clk_p$SB_IO_OUT -.sym 2568 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2570 w_rx_24_fifo_data[10] -.sym 2574 w_rx_24_fifo_data[11] -.sym 2575 w_rx_24_fifo_data[5] -.sym 2576 w_rx_24_fifo_data[8] -.sym 2580 w_rx_24_fifo_data[7] -.sym 2585 w_rx_24_fifo_data[6] -.sym 2587 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2591 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2593 w_rx_24_fifo_data[7] -.sym 2596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2597 w_rx_24_fifo_data[9] -.sym 2603 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2604 w_rx_24_fifo_data[10] -.sym 2608 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2610 w_rx_24_fifo_data[6] -.sym 2615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2617 w_rx_24_fifo_data[11] -.sym 2620 w_rx_24_fifo_data[8] -.sym 2622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2626 o_iq_tx_clk_p$SB_IO_OUT -.sym 2634 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2635 w_rx_24_fifo_data[5] +.sym 2504 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 2505 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 2506 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 2507 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 2508 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 2509 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 2525 rx_fifo.rd_addr[2] +.sym 2526 rx_fifo.rd_addr[8] +.sym 2527 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2530 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 2531 rx_fifo.mem_q.0.3_WDATA_2 +.sym 2536 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 2538 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2541 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2551 w_rx_09_fifo_data[10] +.sym 2561 w_rx_24_fifo_data[24] +.sym 2564 w_rx_24_fifo_data[22] +.sym 2568 w_rx_24_fifo_data[18] +.sym 2574 w_rx_24_fifo_data[16] +.sym 2578 w_rx_24_fifo_data[20] +.sym 2579 w_rx_24_fifo_data[14] +.sym 2584 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2585 o_iq_tx_clk_p$SB_IO_OUT +.sym 2586 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2597 w_rx_24_fifo_data[14] +.sym 2599 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2602 w_rx_24_fifo_data[24] +.sym 2604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2610 w_rx_24_fifo_data[16] +.sym 2611 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2617 w_rx_24_fifo_data[22] +.sym 2621 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2623 w_rx_24_fifo_data[18] +.sym 2627 o_iq_tx_clk_p$SB_IO_OUT +.sym 2632 w_rx_24_fifo_data[20] +.sym 2635 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 2636 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 2637 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2638 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2639 w_rx_24_fifo_data[2] -.sym 2640 rx_fifo.mem_q.0.0_WDATA_2 -.sym 2641 w_rx_24_fifo_data[5] -.sym 2642 rx_fifo.mem_q.0.0_WDATA -.sym 2643 w_rx_24_fifo_data[6] -.sym 2644 w_rx_24_fifo_data[3] -.sym 2645 w_rx_24_fifo_data[4] -.sym 2646 rx_fifo.mem_q.0.1_WDATA_3 -.sym 2652 w_rx_09_fifo_data[28] -.sym 2664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 2667 rx_fifo.rd_addr_gray_wr[9] -.sym 2671 rx_fifo.wr_addr[6] -.sym 2673 rx_fifo.wr_addr[4] -.sym 2676 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2678 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2693 w_rx_09_fifo_data[6] -.sym 2697 w_rx_24_fifo_data[10] -.sym 2701 w_rx_09_fifo_data[6] -.sym 2702 w_rx_09_fifo_data[1] -.sym 2704 o_led1$SB_IO_OUT -.sym 2705 w_rx_09_fifo_data[4] -.sym 2707 w_rx_09_fifo_data[10] -.sym 2708 w_rx_09_fifo_data[8] -.sym 2709 w_rx_09_fifo_data[0] -.sym 2710 w_rx_09_fifo_data[2] -.sym 2712 w_rx_24_fifo_data[6] -.sym 2716 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2725 w_rx_09_fifo_data[6] -.sym 2726 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2731 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2732 w_rx_09_fifo_data[4] -.sym 2738 w_rx_09_fifo_data[0] -.sym 2740 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2743 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2745 w_rx_09_fifo_data[1] -.sym 2749 w_rx_24_fifo_data[6] -.sym 2750 w_rx_09_fifo_data[6] -.sym 2752 o_led1$SB_IO_OUT -.sym 2757 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2758 w_rx_09_fifo_data[2] -.sym 2762 o_led1$SB_IO_OUT -.sym 2763 w_rx_09_fifo_data[10] -.sym 2764 w_rx_24_fifo_data[10] -.sym 2767 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2770 w_rx_09_fifo_data[8] +.sym 2639 w_rx_24_fifo_data[17] +.sym 2640 w_rx_24_fifo_data[11] +.sym 2641 rx_fifo.mem_q.0.2_WDATA +.sym 2642 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2643 w_rx_24_fifo_data[15] +.sym 2644 w_rx_24_fifo_data[19] +.sym 2645 w_rx_24_fifo_data[13] +.sym 2646 rx_fifo.mem_q.0.2_WDATA_1 +.sym 2650 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 2652 rx_fifo.wr_addr[8] +.sym 2654 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 2661 rx_fifo.mem_q.0.1_WDATA_2 +.sym 2668 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2684 rx_fifo.mem_q.0.1_WDATA_2 +.sym 2695 w_rx_24_fifo_data[14] +.sym 2700 w_rx_09_fifo_data[11] +.sym 2703 w_rx_09_fifo_data[14] +.sym 2705 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2709 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2710 w_rx_09_fifo_data[10] +.sym 2713 w_rx_09_fifo_data[12] +.sym 2718 w_rx_09_fifo_data[13] +.sym 2721 w_rx_09_fifo_data[9] +.sym 2725 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2727 w_rx_09_fifo_data[9] +.sym 2739 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2740 w_rx_09_fifo_data[11] +.sym 2744 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2745 w_rx_09_fifo_data[12] +.sym 2756 w_rx_09_fifo_data[10] +.sym 2758 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2761 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2764 w_rx_09_fifo_data[13] +.sym 2767 w_rx_24_fifo_data[14] +.sym 2768 w_rx_09_fifo_data[14] +.sym 2769 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] .sym 2771 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2773 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2774 rx_fifo.rd_addr_gray_wr[9] -.sym 2790 w_rx_09_fifo_data[1] -.sym 2792 o_led1$SB_IO_OUT -.sym 2794 rx_fifo.rd_addr[0] -.sym 2796 rx_fifo.rd_addr[1] -.sym 2799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 2802 rx_fifo.rd_addr[9] -.sym 2803 rx_fifo.mem_q.0.1_WDATA_2 -.sym 2807 w_rx_24_fifo_data[0] -.sym 2808 rx_fifo.mem_q.0.1_WDATA_3 -.sym 2814 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2818 w_rx_09_fifo_data[1] -.sym 2819 $PACKER_GND_NET -.sym 2833 w_rx_24_fifo_data[8] -.sym 2835 w_rx_09_fifo_data[8] -.sym 2842 o_led1$SB_IO_OUT -.sym 2845 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2847 w_lvds_rx_24_d0 -.sym 2893 w_lvds_rx_24_d0 -.sym 2903 o_led1$SB_IO_OUT -.sym 2904 w_rx_09_fifo_data[8] -.sym 2905 w_rx_24_fifo_data[8] +.sym 2774 rx_fifo.mem_q.0.1_WDATA_1 +.sym 2775 w_rx_09_fifo_data[7] +.sym 2776 rx_fifo.mem_q.0.3_WDATA_3 +.sym 2777 rx_fifo.mem_q.0.3_WDATA +.sym 2778 w_rx_09_fifo_data[5] +.sym 2779 w_rx_09_fifo_data[9] +.sym 2780 rx_fifo.mem_q.0.3_WDATA_1 +.sym 2781 rx_fifo.mem_q.0.1_WDATA +.sym 2790 rx_fifo.rd_addr[7] +.sym 2800 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2803 rx_fifo.mem_q.0.2_WDATA_3 +.sym 2805 w_rx_24_fifo_data[4] +.sym 2807 rx_fifo.mem_q.0.2_WDATA_2 +.sym 2809 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 2811 rx_fifo.rd_addr_gray_wr[0] +.sym 2814 rx_fifo.rd_addr[9] +.sym 2832 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2833 w_rx_24_fifo_data[4] +.sym 2836 w_rx_24_fifo_data[6] +.sym 2837 w_rx_24_fifo_data[10] +.sym 2838 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2839 w_rx_24_fifo_data[7] +.sym 2840 w_rx_24_fifo_data[12] +.sym 2841 w_rx_09_fifo_data[6] +.sym 2842 w_rx_24_fifo_data[8] +.sym 2847 w_rx_24_fifo_data[5] +.sym 2852 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2860 w_rx_24_fifo_data[6] +.sym 2861 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2863 w_rx_09_fifo_data[6] +.sym 2867 w_rx_24_fifo_data[4] +.sym 2869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2872 w_rx_24_fifo_data[8] +.sym 2874 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2879 w_rx_24_fifo_data[12] +.sym 2881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2884 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2886 w_rx_24_fifo_data[5] +.sym 2891 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2892 w_rx_24_fifo_data[10] +.sym 2896 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2899 w_rx_24_fifo_data[7] +.sym 2903 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2905 w_rx_24_fifo_data[6] .sym 2906 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 2907 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2910 rx_fifo.wr_addr_gray_rd[9] -.sym 2912 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 2913 rx_fifo.mem_q.0.0_WDATA_1 -.sym 2921 rx_fifo.wr_addr[4] -.sym 2922 rx_fifo.mem_q.0.2_WDATA_2 -.sym 2930 o_led1$SB_IO_OUT -.sym 2933 rx_fifo.wr_addr[6] -.sym 2935 rx_fifo.wr_addr[4] -.sym 2936 w_rx_09_fifo_data[0] -.sym 2937 rx_fifo.rd_addr_gray_wr_r[5] -.sym 2938 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2939 rx_fifo.wr_addr[5] -.sym 2940 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 2941 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 2942 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2943 rx_fifo.wr_addr[7] -.sym 2945 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 2951 rx_fifo.wr_addr[4] -.sym 2964 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 2970 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 2977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 2982 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 2985 rx_fifo.rd_addr_gray_wr_r[8] -.sym 3008 rx_fifo.rd_addr_gray_wr_r[8] -.sym 3009 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 3019 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3027 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 2908 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2909 rx_fifo.mem_q.0.1_WDATA_3 +.sym 2910 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 2911 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 2914 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 2916 w_rx_fifo_full +.sym 2926 rx_fifo.wr_addr[5] +.sym 2927 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2930 rx_fifo.wr_addr[9] +.sym 2933 w_rx_24_fifo_data[5] +.sym 2935 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2937 w_rx_09_fifo_data[3] +.sym 2938 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 2942 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 2943 rx_fifo.rd_addr[8] +.sym 2944 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 2950 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2964 w_rx_24_fifo_data[10] +.sym 2965 w_rx_09_fifo_data[2] +.sym 2967 w_rx_09_fifo_data[10] +.sym 2969 w_rx_24_fifo_data[8] +.sym 2970 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2971 w_rx_09_fifo_data[8] +.sym 2974 w_rx_09_fifo_data[4] +.sym 2987 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2992 w_rx_09_fifo_data[6] +.sym 2995 w_rx_09_fifo_data[8] +.sym 2996 w_rx_24_fifo_data[8] +.sym 2998 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 3002 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3003 w_rx_09_fifo_data[6] +.sym 3008 w_rx_09_fifo_data[10] +.sym 3009 w_rx_24_fifo_data[10] +.sym 3010 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 3019 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3022 w_rx_09_fifo_data[2] +.sym 3026 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3028 w_rx_09_fifo_data[8] +.sym 3031 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3034 w_rx_09_fifo_data[4] +.sym 3041 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 3042 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3044 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] -.sym 3045 rx_fifo.mem_q.0.0_WDATA_3 -.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 3047 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 3048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] -.sym 3049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 3050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 3051 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 3052 rx_fifo.wr_addr[6] -.sym 3057 rx_fifo.wr_addr[9] -.sym 3058 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 3064 o_led1$SB_IO_OUT -.sym 3068 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3069 rx_fifo.wr_addr[3] -.sym 3070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 3072 w_rx_09_fifo_data[1] -.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 3075 rx_fifo.wr_addr[1] -.sym 3078 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3079 rx_fifo.wr_addr[5] -.sym 3101 rx_fifo.wr_addr[6] -.sym 3102 rx_fifo.wr_addr[7] -.sym 3103 rx_fifo.wr_addr[8] -.sym 3106 rx_fifo.wr_addr[1] -.sym 3108 rx_fifo.wr_addr[5] -.sym 3109 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 3110 rx_fifo.wr_addr[4] -.sym 3111 rx_fifo.wr_addr[3] -.sym 3129 $nextpnr_ICESTORM_LC_6$O -.sym 3132 rx_fifo.wr_addr[1] -.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3138 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 3139 rx_fifo.wr_addr[1] -.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 3143 rx_fifo.wr_addr[3] -.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3149 rx_fifo.wr_addr[4] -.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 3156 rx_fifo.wr_addr[5] -.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3161 rx_fifo.wr_addr[6] -.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3167 rx_fifo.wr_addr[7] -.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 3173 rx_fifo.wr_addr[8] -.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3184 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3198 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3201 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 3202 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3203 rx_fifo.wr_addr[9] -.sym 3204 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3205 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3208 rx_fifo.rd_addr_gray_wr_r[8] -.sym 3209 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 3210 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 3212 rx_fifo.rd_addr_gray_wr[9] -.sym 3213 rx_fifo.wr_addr[1] -.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3218 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3220 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 3232 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] -.sym 3234 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 3247 rx_fifo.wr_addr[9] -.sym 3249 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3250 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3255 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3259 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3261 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 3265 rx_fifo.wr_addr[9] -.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] -.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 3311 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3043 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 3044 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 3045 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 3047 w_rx_24_fifo_data[4] +.sym 3048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 3049 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] +.sym 3050 w_rx_24_fifo_data[5] +.sym 3051 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 3052 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 3056 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 3059 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 3061 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 3062 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3066 w_rx_09_fifo_data[4] +.sym 3067 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 3068 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 3069 w_rx_24_fifo_data[2] +.sym 3070 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 3072 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 3074 $PACKER_VCC_NET +.sym 3075 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 3077 rx_fifo.wr_addr[1] +.sym 3078 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3097 rx_fifo.rd_addr[9] +.sym 3110 rx_fifo.rd_addr_gray_wr[0] +.sym 3121 rx_fifo.rd_addr_gray_wr[9] +.sym 3130 rx_fifo.rd_addr[9] +.sym 3149 rx_fifo.rd_addr_gray_wr[0] +.sym 3167 rx_fifo.rd_addr_gray_wr[9] +.sym 3177 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3179 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 3180 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 3181 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 3183 rx_fifo.mem_q.0.0_WDATA +.sym 3184 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 3185 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 3186 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 3193 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 3195 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 3196 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 3197 $PACKER_VCC_NET +.sym 3200 $PACKER_VCC_NET +.sym 3201 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 3202 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 3203 w_rx_09_fifo_data[2] +.sym 3205 w_rx_24_fifo_data[3] +.sym 3208 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 3212 w_rx_09_fifo_data[1] +.sym 3215 $PACKER_VCC_NET +.sym 3221 $PACKER_VCC_NET +.sym 3226 $PACKER_VCC_NET +.sym 3234 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3235 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3248 w_rx_09_fifo_data[1] +.sym 3261 i_rst_b$SB_IO_IN +.sym 3277 w_rx_09_fifo_data[1] +.sym 3279 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3301 i_rst_b$SB_IO_IN +.sym 3302 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3311 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 3312 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3313 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 3315 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 3317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 3319 rx_fifo.wr_addr[0] -.sym 3320 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 3321 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 3322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 3329 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 3330 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 3334 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3336 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 3337 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3338 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3341 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 3343 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 3346 $PACKER_VCC_NET -.sym 3347 w_rx_24_fifo_data[0] -.sym 3349 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 3350 w_rx_09_fifo_data[1] -.sym 3351 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3357 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3358 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3367 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3368 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 3369 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 3372 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3374 rx_fifo.rd_addr_gray_wr_r[0] -.sym 3375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] -.sym 3376 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 3377 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3378 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 3379 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 3380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 3381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3382 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3388 i_rst_b$SB_IO_IN -.sym 3389 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3390 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 3391 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3393 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 3394 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 3398 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3400 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3402 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3403 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 3408 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3409 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3413 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 3414 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 3419 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 3420 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 3421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 3424 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3425 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] -.sym 3426 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 3427 rx_fifo.rd_addr_gray_wr_r[0] -.sym 3431 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3432 i_rst_b$SB_IO_IN -.sym 3436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 3437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 3438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 3439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 3442 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 3443 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 3444 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] -.sym 3445 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3313 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 3314 w_rx_24_fifo_data[2] +.sym 3316 rx_fifo.mem_q.0.0_WDATA_3 +.sym 3318 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 3319 rx_fifo.mem_q.0.0_WDATA_2 +.sym 3320 rx_fifo.mem_q.0.0_WDATA_1 +.sym 3321 w_rx_24_fifo_data[3] +.sym 3333 rx_fifo.rd_addr[9] +.sym 3335 rx_fifo.rd_addr_gray_wr[0] +.sym 3346 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 3348 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3349 w_rx_24_fifo_data[0] +.sym 3369 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 3370 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3371 w_lvds_rx_09_d0 +.sym 3372 w_lvds_rx_09_d1 +.sym 3376 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3378 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3382 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3385 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3388 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3400 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3401 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3402 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3406 w_lvds_rx_09_d1 +.sym 3409 w_lvds_rx_09_d0 +.sym 3412 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3414 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3418 w_lvds_rx_09_d1 +.sym 3419 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3420 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3421 w_lvds_rx_09_d0 +.sym 3431 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3436 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3437 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3438 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3439 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3443 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3444 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3445 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3446 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E .sym 3447 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 3448 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3449 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 3450 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 3451 rx_fifo.rd_addr_gray_wr_r[8] -.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 3453 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 3454 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3455 rx_fifo.rd_addr_gray_wr[8] -.sym 3456 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 3462 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 3468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 3469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 3471 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] -.sym 3472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 3473 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 3476 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3480 w_rx_09_fifo_data[0] -.sym 3482 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3486 w_lvds_rx_09_d1 -.sym 3488 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3489 w_lvds_rx_09_d0 -.sym 3503 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 3508 w_rx_fifo_full -.sym 3511 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3516 rx_fifo.rd_addr_gray_wr[0] -.sym 3518 rx_fifo.rd_addr_gray_wr[9] -.sym 3519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3521 rx_fifo.wr_addr[1] -.sym 3522 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 3524 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3526 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3528 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 3530 w_lvds_rx_09_d0 -.sym 3531 w_lvds_rx_09_d1 -.sym 3532 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 3533 rx_fifo.rd_addr_gray_wr_r[0] -.sym 3535 w_lvds_rx_09_d1 -.sym 3536 w_lvds_rx_09_d0 -.sym 3537 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3538 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3542 rx_fifo.rd_addr_gray_wr[9] -.sym 3547 w_lvds_rx_09_d1 +.sym 3449 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3450 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 3453 w_rx_09_fifo_data[1] +.sym 3454 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3455 w_rx_09_fifo_data[0] +.sym 3467 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3469 rx_fifo.wr_addr[5] +.sym 3474 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 3475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3487 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 3504 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 3506 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 3507 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3509 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 3512 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3514 $PACKER_VCC_NET +.sym 3517 $PACKER_VCC_NET +.sym 3518 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3527 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 3529 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 3531 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 3534 $nextpnr_ICESTORM_LC_1$O +.sym 3537 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3540 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 3541 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3542 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 3543 $PACKER_VCC_NET +.sym 3544 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3547 $PACKER_VCC_NET .sym 3548 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3549 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3550 w_lvds_rx_09_d0 -.sym 3559 rx_fifo.rd_addr_gray_wr_r[0] -.sym 3560 rx_fifo.wr_addr[1] -.sym 3561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3565 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 3566 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 3567 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 3571 w_rx_fifo_full -.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 3573 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3574 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 3577 rx_fifo.rd_addr_gray_wr[0] +.sym 3549 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 3550 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 3554 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 3555 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 3556 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 3559 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 3565 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3566 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 3567 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 3568 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 3579 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3580 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 3581 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E .sym 3582 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3584 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 3586 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 3587 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 3588 w_rx_24_fifo_data[0] -.sym 3590 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3607 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 3609 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3612 w_rx_09_fifo_data[1] -.sym 3613 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3637 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3641 w_lvds_rx_24_d0 -.sym 3644 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3645 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3649 i_rst_b$SB_IO_IN -.sym 3650 w_lvds_rx_24_d1 -.sym 3652 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 3655 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 3659 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3661 w_lvds_rx_09_d1 -.sym 3663 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3666 w_lvds_rx_09_d0 -.sym 3667 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3670 w_lvds_rx_24_d1 -.sym 3671 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3672 w_lvds_rx_24_d0 -.sym 3673 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3676 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3677 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 3678 w_lvds_rx_09_d1 -.sym 3684 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 3685 i_rst_b$SB_IO_IN -.sym 3689 w_lvds_rx_24_d1 -.sym 3691 w_lvds_rx_24_d0 -.sym 3694 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3696 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3697 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3702 w_lvds_rx_09_d1 -.sym 3703 w_lvds_rx_09_d0 -.sym 3708 w_lvds_rx_09_d0 -.sym 3712 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3713 w_lvds_rx_24_d0 -.sym 3714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3715 w_lvds_rx_24_d1 -.sym 3716 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3587 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3589 w_rx_24_fifo_data[0] +.sym 3591 w_rx_24_fifo_data[1] +.sym 3597 w_rx_09_fifo_data[0] +.sym 3614 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3638 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3642 w_lvds_rx_24_d1 +.sym 3643 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3644 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 3645 w_lvds_rx_24_d0 +.sym 3646 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3647 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 3648 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 3652 $PACKER_VCC_NET +.sym 3656 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 3657 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 3658 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3662 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 3664 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 3669 $nextpnr_ICESTORM_LC_0$O +.sym 3671 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 3675 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 3676 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3677 $PACKER_VCC_NET +.sym 3678 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 3679 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 3682 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3683 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 3684 $PACKER_VCC_NET +.sym 3685 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 3689 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 3694 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 3695 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3696 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3697 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3700 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3701 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 3702 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 3703 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 3706 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3707 w_lvds_rx_24_d1 +.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3709 w_lvds_rx_24_d0 +.sym 3715 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 3716 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O .sym 3717 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3720 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 3721 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 3722 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 3723 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 3724 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 3725 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3726 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 3732 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3740 o_shdn_tx_lna$SB_IO_OUT -.sym 3743 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3761 o_shdn_tx_lna$SB_IO_OUT -.sym 3772 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3775 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3780 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 3783 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 3785 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3794 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3796 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3798 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3802 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3807 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3808 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3811 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 3812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3818 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3819 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3820 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3825 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3829 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3830 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3831 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3832 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3851 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3719 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 3720 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 3725 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3774 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3777 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3778 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3783 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3788 w_lvds_rx_24_d0 +.sym 3789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3793 w_lvds_rx_24_d1 +.sym 3801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3817 w_lvds_rx_24_d0 +.sym 3820 w_lvds_rx_24_d1 +.sym 3835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3836 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3838 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3847 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3848 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3849 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3850 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3851 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O .sym 3852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3855 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 3856 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 3857 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 3859 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 3860 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3861 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 3862 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3874 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3911 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3916 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3918 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3921 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3929 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3934 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3947 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3948 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3959 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3965 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3976 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3977 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3978 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3986 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3987 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4002 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 4005 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 4208 o_shdn_tx_lna$SB_IO_OUT -.sym 4238 w_rx_fifo_pulled_data[12] -.sym 4242 w_rx_fifo_pulled_data[14] -.sym 4285 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4286 w_rx_24_fifo_data[15] -.sym 4288 w_rx_24_fifo_data[13] -.sym 4290 w_rx_09_fifo_data[15] -.sym 4291 o_led1$SB_IO_OUT -.sym 4296 w_rx_09_fifo_data[13] -.sym 4303 w_rx_09_fifo_data[11] -.sym 4319 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4320 w_rx_09_fifo_data[11] -.sym 4332 w_rx_09_fifo_data[13] -.sym 4333 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4337 o_led1$SB_IO_OUT -.sym 4338 w_rx_24_fifo_data[13] -.sym 4339 w_rx_09_fifo_data[13] -.sym 4343 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4345 w_rx_09_fifo_data[15] -.sym 4354 o_led1$SB_IO_OUT -.sym 4355 w_rx_09_fifo_data[15] -.sym 4356 w_rx_24_fifo_data[15] -.sym 4358 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 4359 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4360 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4366 w_rx_fifo_pulled_data[13] -.sym 4370 w_rx_fifo_pulled_data[15] -.sym 4388 w_rx_24_fifo_data[13] -.sym 4393 $PACKER_VCC_NET -.sym 4394 rx_fifo.wr_addr[1] -.sym 4396 rx_fifo.wr_addr[7] -.sym 4398 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 4402 rx_fifo.wr_addr[3] -.sym 4408 rx_fifo.wr_addr[0] -.sym 4414 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 4424 rx_fifo.wr_addr[4] -.sym 4427 rx_fifo.wr_addr[6] -.sym 4428 rx_fifo.rd_addr[4] -.sym 4444 w_rx_24_fifo_data[20] -.sym 4446 w_rx_09_fifo_data[12] -.sym 4447 o_led1$SB_IO_OUT -.sym 4448 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4451 w_rx_24_fifo_data[16] -.sym 4453 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4457 w_rx_09_fifo_data[14] -.sym 4458 w_rx_24_fifo_data[14] -.sym 4462 w_rx_24_fifo_data[13] -.sym 4466 w_rx_24_fifo_data[12] -.sym 4473 w_rx_24_fifo_data[15] -.sym 4477 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4478 w_rx_24_fifo_data[12] -.sym 4482 w_rx_24_fifo_data[14] -.sym 4484 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4487 w_rx_24_fifo_data[15] -.sym 4489 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4494 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4496 w_rx_24_fifo_data[20] -.sym 4499 w_rx_24_fifo_data[16] -.sym 4501 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4505 o_led1$SB_IO_OUT -.sym 4506 w_rx_09_fifo_data[14] -.sym 4508 w_rx_24_fifo_data[14] -.sym 4512 o_led1$SB_IO_OUT -.sym 4513 w_rx_09_fifo_data[12] -.sym 4514 w_rx_24_fifo_data[12] -.sym 4518 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4520 w_rx_24_fifo_data[13] -.sym 4521 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4522 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4523 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 3860 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 4238 w_rx_fifo_pulled_data[24] +.sym 4242 w_rx_fifo_pulled_data[26] +.sym 4256 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 4259 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 4261 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 4300 w_rx_fifo_pulled_data[26] +.sym 4304 w_rx_fifo_pulled_data[25] +.sym 4336 w_rx_fifo_pulled_data[25] +.sym 4349 w_rx_fifo_pulled_data[26] +.sym 4358 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 4359 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4360 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4366 w_rx_fifo_pulled_data[25] +.sym 4370 w_rx_fifo_pulled_data[27] +.sym 4383 rx_fifo.mem_i.0.2_WDATA_2 +.sym 4384 rx_fifo.mem_i.0.1_WDATA_3 +.sym 4398 rx_fifo.wr_addr[0] +.sym 4402 rx_fifo.wr_addr[5] +.sym 4406 $PACKER_VCC_NET +.sym 4408 rx_fifo.rd_addr[4] +.sym 4410 smi_ctrl_ins.int_cnt_rx[3] +.sym 4414 rx_fifo.rd_addr[5] +.sym 4415 rx_fifo.rd_addr[3] +.sym 4418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 4422 w_rx_fifo_pulled_data[17] +.sym 4425 rx_fifo.mem_i.0.0_WDATA_3 +.sym 4427 w_smi_data_output[3] +.sym 4430 smi_ctrl_ins.int_cnt_rx[4] +.sym 4431 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 4443 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 4451 w_rx_fifo_pulled_data[24] +.sym 4452 w_rx_fifo_pulled_data[17] +.sym 4454 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 4455 smi_ctrl_ins.int_cnt_rx[4] +.sym 4456 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 4463 w_rx_fifo_pulled_data[18] +.sym 4465 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 4467 smi_ctrl_ins.int_cnt_rx[3] +.sym 4471 w_rx_fifo_pulled_data[27] +.sym 4475 smi_ctrl_ins.int_cnt_rx[3] +.sym 4476 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 4477 smi_ctrl_ins.int_cnt_rx[4] +.sym 4478 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 4481 w_rx_fifo_pulled_data[18] +.sym 4494 w_rx_fifo_pulled_data[27] +.sym 4499 w_rx_fifo_pulled_data[24] +.sym 4505 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 4506 smi_ctrl_ins.int_cnt_rx[4] +.sym 4507 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 4508 smi_ctrl_ins.int_cnt_rx[3] +.sym 4517 w_rx_fifo_pulled_data[17] +.sym 4521 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 4522 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4523 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 4525 w_rx_fifo_pulled_data[16] .sym 4529 w_rx_fifo_pulled_data[18] -.sym 4536 rx_fifo.rd_addr[0] -.sym 4537 o_led1$SB_IO_OUT -.sym 4538 w_rx_24_fifo_data[20] -.sym 4539 rx_fifo.rd_addr[8] .sym 4540 rx_fifo.rd_addr[7] -.sym 4542 rx_fifo.rd_addr[2] -.sym 4543 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4544 rx_fifo.rd_addr[3] -.sym 4545 w_rx_24_fifo_data[21] -.sym 4546 w_rx_24_fifo_data[18] -.sym 4548 rx_fifo.mem_q.0.2_WDATA -.sym 4549 rx_fifo.rd_addr[5] -.sym 4550 rx_fifo.rd_addr[3] -.sym 4551 w_rx_24_fifo_data[28] -.sym 4554 rx_fifo.rd_addr[6] -.sym 4556 rx_fifo.rd_addr[0] +.sym 4541 rx_fifo.rd_addr[9] +.sym 4542 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4543 rx_fifo.rd_addr[6] +.sym 4545 rx_fifo.rd_addr[8] +.sym 4549 rx_fifo.rd_addr[0] +.sym 4551 rx_fifo.rd_addr[2] +.sym 4552 w_rx_fifo_pulled_data[8] +.sym 4554 rx_fifo.rd_addr[4] +.sym 4555 w_rx_fifo_pulled_data[10] .sym 4558 rx_fifo.rd_addr[1] -.sym 4567 w_rx_24_fifo_data[17] -.sym 4568 o_led1$SB_IO_OUT -.sym 4569 w_rx_24_fifo_data[18] -.sym 4570 w_rx_09_fifo_data[23] -.sym 4571 w_rx_09_fifo_data[18] -.sym 4572 w_rx_09_fifo_data[22] -.sym 4574 w_rx_24_fifo_data[16] -.sym 4575 w_rx_09_fifo_data[17] -.sym 4576 w_rx_24_fifo_data[22] -.sym 4577 o_led1$SB_IO_OUT -.sym 4583 w_rx_09_fifo_data[21] -.sym 4586 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4587 w_rx_09_fifo_data[16] -.sym 4590 w_rx_09_fifo_data[19] -.sym 4599 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4601 w_rx_09_fifo_data[23] -.sym 4604 w_rx_09_fifo_data[17] -.sym 4606 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4610 w_rx_09_fifo_data[19] -.sym 4611 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4616 o_led1$SB_IO_OUT -.sym 4618 w_rx_09_fifo_data[22] -.sym 4619 w_rx_24_fifo_data[22] -.sym 4622 w_rx_24_fifo_data[18] -.sym 4623 o_led1$SB_IO_OUT -.sym 4624 w_rx_09_fifo_data[18] -.sym 4630 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4631 w_rx_09_fifo_data[21] -.sym 4634 w_rx_24_fifo_data[16] -.sym 4635 o_led1$SB_IO_OUT -.sym 4636 w_rx_09_fifo_data[16] -.sym 4640 o_led1$SB_IO_OUT -.sym 4642 w_rx_09_fifo_data[17] -.sym 4643 w_rx_24_fifo_data[17] -.sym 4644 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 4645 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4559 smi_ctrl_ins.int_cnt_rx[3] +.sym 4565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 4566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 4567 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 4568 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 4569 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 4570 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 4571 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 4572 smi_ctrl_ins.int_cnt_rx[3] +.sym 4573 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 4576 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 4577 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 4578 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 4579 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 4580 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 4583 i_rst_b$SB_IO_IN +.sym 4587 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 4588 w_rx_24_fifo_data[19] +.sym 4589 w_rx_09_fifo_data[19] +.sym 4592 smi_ctrl_ins.int_cnt_rx[4] +.sym 4596 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4598 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 4601 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 4605 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 4607 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 4610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 4611 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 4616 w_rx_09_fifo_data[19] +.sym 4618 w_rx_24_fifo_data[19] +.sym 4619 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 4624 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 4628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 4630 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 4634 smi_ctrl_ins.int_cnt_rx[4] +.sym 4635 smi_ctrl_ins.int_cnt_rx[3] +.sym 4636 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 4637 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 4640 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 4641 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 4642 smi_ctrl_ins.int_cnt_rx[3] +.sym 4643 smi_ctrl_ins.int_cnt_rx[4] +.sym 4644 i_rst_b$SB_IO_IN +.sym 4645 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 4648 w_rx_fifo_pulled_data[17] .sym 4652 w_rx_fifo_pulled_data[19] -.sym 4659 rx_fifo.mem_i.0.1_WDATA -.sym 4660 rx_fifo.wr_addr[5] -.sym 4661 w_rx_09_fifo_data[23] -.sym 4662 o_led1$SB_IO_OUT -.sym 4663 rx_fifo.wr_addr[1] -.sym 4664 rx_fifo.wr_addr[3] -.sym 4665 w_rx_09_fifo_data[21] -.sym 4667 rx_fifo.mem_i.0.1_WDATA_2 -.sym 4668 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 4671 $PACKER_VCC_NET -.sym 4672 rx_fifo.wr_addr[1] -.sym 4673 rx_fifo.mem_q.0.0_WDATA_2 -.sym 4674 rx_fifo.mem_i.0.2_WDATA -.sym 4676 rx_fifo.wr_addr[1] -.sym 4678 rx_fifo.wr_addr[3] -.sym 4679 rx_fifo.mem_i.0.2_WDATA_1 -.sym 4680 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 4681 rx_fifo.wr_addr[7] -.sym 4689 w_rx_24_fifo_data[26] -.sym 4690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4692 w_rx_24_fifo_data[17] -.sym 4694 w_rx_09_fifo_data[24] -.sym 4695 o_led1$SB_IO_OUT -.sym 4697 w_rx_09_fifo_data[19] -.sym 4702 w_rx_24_fifo_data[22] -.sym 4704 w_rx_24_fifo_data[24] -.sym 4707 w_rx_24_fifo_data[19] -.sym 4711 w_rx_24_fifo_data[28] -.sym 4715 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4723 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4724 w_rx_24_fifo_data[22] -.sym 4728 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4730 w_rx_24_fifo_data[24] -.sym 4733 w_rx_09_fifo_data[19] -.sym 4734 o_led1$SB_IO_OUT -.sym 4736 w_rx_24_fifo_data[19] -.sym 4740 w_rx_24_fifo_data[17] -.sym 4742 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4745 w_rx_09_fifo_data[24] -.sym 4746 o_led1$SB_IO_OUT -.sym 4747 w_rx_24_fifo_data[24] -.sym 4751 w_rx_24_fifo_data[19] -.sym 4754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4758 w_rx_24_fifo_data[28] -.sym 4759 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4764 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4765 w_rx_24_fifo_data[26] -.sym 4767 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4768 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4769 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4771 w_rx_fifo_pulled_data[24] -.sym 4775 w_rx_fifo_pulled_data[26] -.sym 4784 w_smi_data_output[0] -.sym 4785 rx_fifo.wr_addr[4] -.sym 4786 rx_fifo.rd_addr[2] -.sym 4790 rx_fifo.rd_addr[6] -.sym 4793 rx_fifo.wr_addr[6] -.sym 4797 rx_fifo.wr_addr[0] -.sym 4801 w_rx_24_fifo_data[21] -.sym 4802 $PACKER_VCC_NET -.sym 4804 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 4805 rx_fifo.mem_q.0.0_WDATA -.sym 4812 w_rx_24_fifo_data[26] -.sym 4816 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4820 w_rx_24_fifo_data[11] -.sym 4821 w_rx_24_fifo_data[5] -.sym 4824 o_led1$SB_IO_OUT -.sym 4826 w_rx_24_fifo_data[7] -.sym 4828 w_rx_09_fifo_data[5] -.sym 4830 w_rx_09_fifo_data[3] -.sym 4832 w_rx_09_fifo_data[26] -.sym 4833 w_rx_09_fifo_data[24] -.sym 4834 w_rx_09_fifo_data[7] -.sym 4837 w_rx_09_fifo_data[11] -.sym 4844 o_led1$SB_IO_OUT -.sym 4845 w_rx_09_fifo_data[11] -.sym 4846 w_rx_24_fifo_data[11] -.sym 4850 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4852 w_rx_09_fifo_data[3] -.sym 4856 o_led1$SB_IO_OUT -.sym 4857 w_rx_09_fifo_data[5] -.sym 4859 w_rx_24_fifo_data[5] -.sym 4863 o_led1$SB_IO_OUT -.sym 4864 w_rx_09_fifo_data[7] -.sym 4865 w_rx_24_fifo_data[7] -.sym 4869 w_rx_24_fifo_data[26] -.sym 4870 o_led1$SB_IO_OUT -.sym 4871 w_rx_09_fifo_data[26] -.sym 4875 w_rx_09_fifo_data[24] -.sym 4876 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4881 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4883 w_rx_09_fifo_data[26] -.sym 4886 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 4888 w_rx_09_fifo_data[5] -.sym 4890 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 4891 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4892 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4894 w_rx_fifo_pulled_data[25] -.sym 4898 w_rx_fifo_pulled_data[27] -.sym 4905 $PACKER_VCC_NET -.sym 4908 rx_fifo.mem_q.0.1_WDATA_3 -.sym 4910 rx_fifo.rd_addr[2] -.sym 4911 rx_fifo.mem_q.0.1_WDATA_1 -.sym 4912 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 4913 rx_fifo.mem_q.0.1_WDATA -.sym 4914 rx_fifo.rd_addr[6] -.sym 4916 rx_fifo.mem_q.0.1_WDATA_2 -.sym 4917 rx_fifo.rd_addr[4] -.sym 4918 rx_fifo.wr_addr[6] -.sym 4920 rx_fifo.wr_addr[4] -.sym 4924 rx_fifo.wr_addr[6] -.sym 4936 w_rx_09_fifo_data[2] -.sym 4937 w_rx_09_fifo_data[3] -.sym 4939 w_rx_09_fifo_data[4] -.sym 4942 w_rx_24_fifo_data[2] -.sym 4943 o_led1$SB_IO_OUT -.sym 4944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4945 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4947 w_rx_24_fifo_data[3] -.sym 4955 w_rx_24_fifo_data[0] -.sym 4956 w_rx_24_fifo_data[4] -.sym 4963 w_rx_24_fifo_data[1] +.sym 4657 w_rx_fifo_full +.sym 4661 w_rx_09_fifo_data[29] +.sym 4662 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4663 rx_fifo.mem_i.0.3_WDATA_1 +.sym 4664 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 4665 rx_fifo.wr_addr[3] +.sym 4668 smi_ctrl_ins.int_cnt_rx[4] +.sym 4669 w_smi_data_output[0] +.sym 4671 rx_fifo.wr_addr[0] +.sym 4673 rx_fifo.rd_addr[9] +.sym 4675 rx_fifo.mem_q.0.2_WDATA +.sym 4677 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4678 rx_fifo.wr_addr[5] +.sym 4680 rx_fifo.wr_addr[0] +.sym 4681 rx_fifo.wr_addr[5] +.sym 4682 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4689 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 4692 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 4693 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 4697 w_rx_fifo_pulled_data[16] +.sym 4698 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 4699 w_rx_09_fifo_data[17] +.sym 4700 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4704 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 4707 smi_ctrl_ins.int_cnt_rx[4] +.sym 4708 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 4709 w_rx_fifo_pulled_data[19] +.sym 4710 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 4712 w_rx_24_fifo_data[17] +.sym 4713 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 4716 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 4718 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 4719 smi_ctrl_ins.int_cnt_rx[3] +.sym 4721 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 4722 smi_ctrl_ins.int_cnt_rx[4] +.sym 4723 smi_ctrl_ins.int_cnt_rx[3] +.sym 4724 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 4727 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 4728 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 4729 smi_ctrl_ins.int_cnt_rx[4] +.sym 4730 smi_ctrl_ins.int_cnt_rx[3] +.sym 4733 smi_ctrl_ins.int_cnt_rx[3] +.sym 4734 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 4735 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 4736 smi_ctrl_ins.int_cnt_rx[4] +.sym 4741 w_rx_fifo_pulled_data[19] +.sym 4747 w_rx_fifo_pulled_data[16] +.sym 4751 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 4752 smi_ctrl_ins.int_cnt_rx[3] +.sym 4753 smi_ctrl_ins.int_cnt_rx[4] +.sym 4754 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 4757 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 4758 smi_ctrl_ins.int_cnt_rx[4] +.sym 4759 smi_ctrl_ins.int_cnt_rx[3] +.sym 4760 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 4763 w_rx_24_fifo_data[17] +.sym 4764 w_rx_09_fifo_data[17] +.sym 4765 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4767 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 4768 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4769 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4771 w_rx_fifo_pulled_data[4] +.sym 4775 w_rx_fifo_pulled_data[6] +.sym 4783 rx_fifo.rd_addr[6] +.sym 4788 rx_fifo.rd_addr[3] +.sym 4790 rx_fifo.rd_addr[7] +.sym 4795 $PACKER_VCC_NET +.sym 4796 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 4799 i_rst_b$SB_IO_IN +.sym 4803 rx_fifo.rd_addr[3] +.sym 4804 rx_fifo.rd_addr[5] +.sym 4805 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 4824 w_rx_fifo_pulled_data[8] +.sym 4825 w_rx_fifo_pulled_data[10] +.sym 4832 w_rx_fifo_pulled_data[6] +.sym 4834 w_rx_fifo_pulled_data[13] +.sym 4838 w_rx_fifo_pulled_data[3] +.sym 4842 w_rx_fifo_pulled_data[15] +.sym 4845 w_rx_fifo_pulled_data[13] +.sym 4853 w_rx_fifo_pulled_data[8] +.sym 4859 w_rx_fifo_pulled_data[10] +.sym 4865 w_rx_fifo_pulled_data[15] +.sym 4868 w_rx_fifo_pulled_data[3] +.sym 4874 w_rx_fifo_pulled_data[6] +.sym 4890 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 4891 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4892 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4894 w_rx_fifo_pulled_data[5] +.sym 4898 w_rx_fifo_pulled_data[7] +.sym 4907 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 4908 rx_fifo.rd_addr[1] +.sym 4912 rx_fifo.rd_addr[0] +.sym 4914 rx_fifo.rd_addr[2] +.sym 4915 rx_fifo.wr_addr[3] +.sym 4917 rx_fifo.mem_q.0.1_WDATA_3 +.sym 4920 w_rx_fifo_pulled_data[13] +.sym 4924 w_rx_fifo_pulled_data[3] +.sym 4927 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 4928 w_rx_fifo_pulled_data[15] +.sym 4934 w_rx_09_fifo_data[11] +.sym 4935 w_rx_24_fifo_data[11] +.sym 4937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4938 w_rx_24_fifo_data[15] +.sym 4939 w_rx_09_fifo_data[9] +.sym 4940 w_rx_24_fifo_data[13] +.sym 4942 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 4943 w_rx_24_fifo_data[11] +.sym 4952 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4956 w_rx_24_fifo_data[9] +.sym 4958 w_rx_24_fifo_data[17] +.sym 4959 i_rst_b$SB_IO_IN +.sym 4961 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4967 w_rx_24_fifo_data[15] .sym 4968 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4970 w_rx_24_fifo_data[0] -.sym 4973 w_rx_24_fifo_data[2] -.sym 4974 o_led1$SB_IO_OUT -.sym 4976 w_rx_09_fifo_data[2] -.sym 4979 w_rx_24_fifo_data[3] -.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4986 o_led1$SB_IO_OUT -.sym 4987 w_rx_09_fifo_data[3] -.sym 4988 w_rx_24_fifo_data[3] -.sym 4991 w_rx_24_fifo_data[4] +.sym 4973 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4976 w_rx_24_fifo_data[9] +.sym 4979 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 4980 w_rx_24_fifo_data[11] +.sym 4981 w_rx_09_fifo_data[11] +.sym 4986 i_rst_b$SB_IO_IN +.sym 4987 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 4993 w_rx_24_fifo_data[13] .sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 4997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4998 w_rx_24_fifo_data[1] -.sym 5004 w_rx_24_fifo_data[2] -.sym 5006 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5010 o_led1$SB_IO_OUT -.sym 5011 w_rx_09_fifo_data[4] -.sym 5012 w_rx_24_fifo_data[4] +.sym 4999 w_rx_24_fifo_data[17] +.sym 5003 w_rx_24_fifo_data[11] +.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5010 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5011 w_rx_09_fifo_data[9] +.sym 5012 w_rx_24_fifo_data[9] .sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5014 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5017 w_rx_fifo_pulled_data[8] -.sym 5021 w_rx_fifo_pulled_data[10] -.sym 5029 rx_fifo.rd_addr[7] -.sym 5030 rx_fifo.rd_addr[2] -.sym 5031 rx_fifo.rd_addr[3] -.sym 5032 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 5033 o_led1$SB_IO_OUT -.sym 5034 rx_fifo.wr_addr[7] -.sym 5035 rx_fifo.rd_addr[8] -.sym 5036 rx_fifo.wr_addr[6] -.sym 5037 rx_fifo.wr_addr[5] -.sym 5038 rx_fifo.wr_addr[4] -.sym 5041 rx_fifo.rd_addr[5] -.sym 5043 rx_fifo.rd_addr[6] -.sym 5045 rx_fifo.mem_q.0.2_WDATA -.sym 5047 rx_fifo.rd_addr[1] -.sym 5049 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 5051 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5086 rx_fifo.rd_addr[9] -.sym 5090 rx_fifo.rd_addr[9] +.sym 5017 w_rx_fifo_pulled_data[12] +.sym 5021 w_rx_fifo_pulled_data[14] +.sym 5030 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5031 rx_fifo.rd_addr[8] +.sym 5032 rx_fifo.rd_addr[1] +.sym 5033 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5035 rx_fifo.rd_addr[4] +.sym 5038 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 5039 rx_fifo.rd_addr[9] +.sym 5041 rx_fifo.rd_addr[0] +.sym 5043 w_rx_fifo_pulled_data[8] +.sym 5049 rx_fifo.rd_addr[2] +.sym 5050 rx_fifo.rd_addr[4] +.sym 5051 w_rx_fifo_pulled_data[10] +.sym 5058 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5061 w_rx_24_fifo_data[15] +.sym 5062 w_rx_24_fifo_data[12] +.sym 5066 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5069 w_rx_24_fifo_data[7] +.sym 5071 w_rx_24_fifo_data[13] +.sym 5073 w_rx_09_fifo_data[3] +.sym 5074 w_rx_09_fifo_data[7] +.sym 5077 w_rx_24_fifo_data[5] +.sym 5083 w_rx_09_fifo_data[13] +.sym 5085 w_rx_09_fifo_data[5] +.sym 5086 w_rx_09_fifo_data[12] +.sym 5087 w_rx_09_fifo_data[15] +.sym 5090 w_rx_24_fifo_data[5] +.sym 5091 w_rx_09_fifo_data[5] +.sym 5092 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5096 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5098 w_rx_09_fifo_data[5] +.sym 5102 w_rx_09_fifo_data[12] +.sym 5104 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5105 w_rx_24_fifo_data[12] +.sym 5109 w_rx_24_fifo_data[15] +.sym 5110 w_rx_09_fifo_data[15] +.sym 5111 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5115 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5116 w_rx_09_fifo_data[3] +.sym 5120 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5122 w_rx_09_fifo_data[7] +.sym 5126 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5127 w_rx_24_fifo_data[13] +.sym 5129 w_rx_09_fifo_data[13] +.sym 5132 w_rx_09_fifo_data[7] +.sym 5134 w_rx_24_fifo_data[7] +.sym 5135 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5136 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 5137 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5140 w_rx_fifo_pulled_data[9] -.sym 5144 w_rx_fifo_pulled_data[11] -.sym 5153 rx_fifo.wr_addr[5] -.sym 5154 rx_fifo.wr_addr[1] -.sym 5158 rx_fifo.wr_addr[3] -.sym 5159 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 5163 rx_fifo.mem_q.0.0_WDATA_1 -.sym 5164 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 5165 o_led1$SB_IO_OUT -.sym 5166 rx_fifo.wr_addr[7] -.sym 5167 io_pmod[7]$SB_IO_IN -.sym 5168 rx_fifo.wr_addr[1] -.sym 5170 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 5172 rx_fifo.wr_addr[7] -.sym 5173 rx_fifo.mem_q.0.0_WDATA_2 -.sym 5174 rx_fifo.wr_addr[3] -.sym 5183 o_led1$SB_IO_OUT -.sym 5184 rx_fifo.wr_addr[9] -.sym 5204 w_rx_09_fifo_data[1] -.sym 5205 rx_fifo.wr_addr_gray_rd[9] -.sym 5209 w_rx_24_fifo_data[1] -.sym 5220 rx_fifo.wr_addr[9] -.sym 5234 rx_fifo.wr_addr_gray_rd[9] -.sym 5238 w_rx_09_fifo_data[1] -.sym 5239 w_rx_24_fifo_data[1] -.sym 5240 o_led1$SB_IO_OUT -.sym 5260 r_counter_$glb_clk -.sym 5263 w_rx_fifo_pulled_data[0] -.sym 5267 w_rx_fifo_pulled_data[2] -.sym 5275 rx_fifo.rd_addr[0] -.sym 5277 rx_fifo.rd_addr[6] -.sym 5278 rx_fifo.rd_addr[2] +.sym 5138 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 5140 w_rx_fifo_pulled_data[13] +.sym 5144 w_rx_fifo_pulled_data[15] +.sym 5152 $PACKER_VCC_NET +.sym 5154 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 5155 rx_fifo.wr_addr[1] +.sym 5156 rx_fifo.wr_addr[3] +.sym 5159 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5161 rx_fifo.mem_q.0.3_WDATA_2 +.sym 5162 rx_fifo.wr_addr[0] +.sym 5164 rx_fifo.wr_addr[5] +.sym 5165 rx_fifo.rd_addr[9] +.sym 5166 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5168 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5169 w_rx_fifo_pulled_data[14] +.sym 5170 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 5171 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5172 rx_fifo.mem_q.0.2_WDATA +.sym 5173 rx_fifo.mem_q.0.2_WDATA_1 +.sym 5180 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 5181 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5182 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 5184 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 5185 w_rx_09_fifo_data[4] +.sym 5186 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 5187 w_rx_fifo_full +.sym 5190 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 5191 w_rx_24_fifo_data[4] +.sym 5192 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 5193 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5194 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 5195 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5196 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 5197 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 5202 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5210 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5213 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5215 w_rx_24_fifo_data[4] +.sym 5216 w_rx_09_fifo_data[4] +.sym 5219 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 5220 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 5221 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 5225 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5226 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5227 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5228 w_rx_fifo_full +.sym 5243 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5244 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5245 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 5246 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 5255 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 5256 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 5257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 5258 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 5260 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5263 w_rx_fifo_pulled_data[8] +.sym 5267 w_rx_fifo_pulled_data[10] +.sym 5275 rx_fifo.rd_addr[6] +.sym 5276 rx_fifo.rd_addr[1] +.sym 5279 rx_fifo.rd_addr[5] +.sym 5280 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] .sym 5281 rx_fifo.rd_addr[7] -.sym 5282 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5293 rx_fifo.mem_q.0.0_WDATA -.sym 5296 rx_fifo.wr_addr[0] -.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5303 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5304 w_rx_24_fifo_data[0] -.sym 5305 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 5306 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] -.sym 5307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] -.sym 5309 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 5310 w_rx_09_fifo_data[0] -.sym 5311 rx_fifo.rd_addr_gray_wr_r[7] -.sym 5312 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 5313 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 5314 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5316 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 5318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 5319 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 5322 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 5323 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] -.sym 5325 o_led1$SB_IO_OUT -.sym 5326 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 5327 io_pmod[7]$SB_IO_IN -.sym 5330 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 5336 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] -.sym 5342 w_rx_09_fifo_data[0] -.sym 5344 w_rx_24_fifo_data[0] -.sym 5345 o_led1$SB_IO_OUT -.sym 5348 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5350 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] -.sym 5351 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] -.sym 5354 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] -.sym 5355 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] -.sym 5356 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 5357 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 5361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 5362 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5367 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 5368 io_pmod[7]$SB_IO_IN -.sym 5369 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 5373 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 5374 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 5375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 5378 rx_fifo.rd_addr_gray_wr_r[7] -.sym 5380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 5382 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 5285 rx_fifo.rd_addr[3] +.sym 5288 $PACKER_VCC_NET +.sym 5290 rx_fifo.rd_addr[5] +.sym 5291 $PACKER_VCC_NET +.sym 5292 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5294 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 5295 rx_fifo.rd_addr[3] +.sym 5296 rx_fifo.wr_addr[7] +.sym 5303 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 5305 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 5306 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 5309 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5310 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 5312 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5314 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 5315 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 5316 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 5317 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 5319 rx_fifo.wr_addr[1] +.sym 5320 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 5327 w_rx_24_fifo_data[2] +.sym 5328 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 5330 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 5331 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5332 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] +.sym 5333 w_rx_24_fifo_data[3] +.sym 5334 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5336 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5337 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5338 rx_fifo.wr_addr[1] +.sym 5339 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5342 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 5343 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5344 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 5345 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] +.sym 5356 w_rx_24_fifo_data[2] +.sym 5357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 5361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 5362 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 5363 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 5366 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5367 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 5368 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5369 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 5373 w_rx_24_fifo_data[3] +.sym 5374 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5378 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5379 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 5381 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 5382 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5383 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5386 w_rx_fifo_pulled_data[1] -.sym 5390 w_rx_fifo_pulled_data[3] -.sym 5397 rx_fifo.rd_addr[9] -.sym 5398 w_rx_24_fifo_data[0] -.sym 5399 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5401 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 5402 $PACKER_VCC_NET -.sym 5406 $PACKER_VCC_NET -.sym 5407 rx_fifo.rd_addr_gray[0] -.sym 5410 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 5412 rx_fifo.rd_addr[4] -.sym 5413 rx_fifo.wr_addr[6] -.sym 5414 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5415 rx_fifo.wr_addr[4] -.sym 5416 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5419 rx_fifo.wr_addr[8] -.sym 5420 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 5427 rx_fifo.wr_addr[1] -.sym 5429 rx_fifo.wr_addr[4] -.sym 5431 rx_fifo.wr_addr[7] -.sym 5435 rx_fifo.wr_addr[6] -.sym 5437 rx_fifo.wr_addr[5] -.sym 5438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 5439 rx_fifo.wr_addr[0] -.sym 5440 rx_fifo.wr_addr[3] -.sym 5458 $nextpnr_ICESTORM_LC_8$O -.sym 5461 rx_fifo.wr_addr[0] -.sym 5464 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 5467 rx_fifo.wr_addr[1] -.sym 5468 rx_fifo.wr_addr[0] -.sym 5470 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 5472 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 5476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 5479 rx_fifo.wr_addr[3] -.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 5482 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 5484 rx_fifo.wr_addr[4] -.sym 5486 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 5488 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 5490 rx_fifo.wr_addr[5] -.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 5494 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 5497 rx_fifo.wr_addr[6] -.sym 5498 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 5500 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 5503 rx_fifo.wr_addr[7] -.sym 5504 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 5523 rx_fifo.rd_addr[2] +.sym 5384 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 5386 w_rx_fifo_pulled_data[9] +.sym 5390 w_rx_fifo_pulled_data[11] +.sym 5393 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 5396 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 5401 rx_fifo.mem_q.0.2_WDATA_2 +.sym 5403 rx_fifo.mem_q.0.2_WDATA_3 +.sym 5405 rx_fifo.wr_addr[4] +.sym 5411 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 5412 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 5420 w_rx_fifo_pulled_data[3] +.sym 5428 w_rx_09_fifo_data[3] +.sym 5433 w_rx_24_fifo_data[3] +.sym 5438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5441 w_rx_fifo_pulled_data[14] +.sym 5443 w_rx_fifo_pulled_data[0] +.sym 5447 w_rx_fifo_pulled_data[11] +.sym 5451 w_rx_fifo_pulled_data[9] +.sym 5452 w_rx_fifo_pulled_data[1] +.sym 5455 w_rx_fifo_pulled_data[2] +.sym 5462 w_rx_fifo_pulled_data[0] +.sym 5465 w_rx_fifo_pulled_data[11] +.sym 5473 w_rx_fifo_pulled_data[14] +.sym 5483 w_rx_09_fifo_data[3] +.sym 5484 w_rx_24_fifo_data[3] +.sym 5486 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5489 w_rx_fifo_pulled_data[1] +.sym 5497 w_rx_fifo_pulled_data[9] +.sym 5504 w_rx_fifo_pulled_data[2] +.sym 5505 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 5506 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 5507 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5509 w_rx_fifo_pulled_data[0] +.sym 5513 w_rx_fifo_pulled_data[2] +.sym 5522 rx_fifo.rd_addr[1] +.sym 5523 rx_fifo.rd_addr[8] .sym 5526 rx_fifo.rd_addr[7] -.sym 5527 rx_fifo.rd_addr[1] -.sym 5528 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5529 rx_fifo.rd_addr[3] -.sym 5530 rx_fifo.rd_addr[0] -.sym 5532 rx_fifo.rd_addr_gray[8] -.sym 5534 rx_fifo.rd_addr[5] -.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5536 rx_fifo.rd_addr[6] -.sym 5544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 5551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 5552 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5554 rx_fifo.wr_addr[0] -.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 5560 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5561 rx_fifo.wr_addr[9] -.sym 5562 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5579 rx_fifo.wr_addr[8] -.sym 5581 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 5583 rx_fifo.wr_addr[8] -.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 5590 rx_fifo.wr_addr[9] -.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 5594 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5600 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 5603 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5608 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 5614 rx_fifo.wr_addr[0] -.sym 5620 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5621 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5624 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5627 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5628 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 5531 rx_fifo.rd_addr[6] +.sym 5533 rx_fifo.rd_addr[4] +.sym 5537 rx_fifo.mem_q.0.0_WDATA +.sym 5538 w_rx_fifo_pulled_data[1] +.sym 5539 rx_fifo.rd_addr[5] +.sym 5541 rx_fifo.rd_addr[0] +.sym 5542 rx_fifo.rd_addr[2] +.sym 5550 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5553 w_rx_09_fifo_data[1] +.sym 5554 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5555 w_rx_09_fifo_data[0] +.sym 5557 w_rx_24_fifo_data[2] +.sym 5558 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5559 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5560 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 5561 w_rx_09_fifo_data[2] +.sym 5565 w_lvds_rx_09_d0 +.sym 5567 w_lvds_rx_09_d1 +.sym 5571 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5572 w_rx_24_fifo_data[1] +.sym 5575 w_rx_24_fifo_data[0] +.sym 5584 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5585 w_rx_24_fifo_data[0] +.sym 5594 w_rx_09_fifo_data[0] +.sym 5595 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5597 w_rx_24_fifo_data[0] +.sym 5606 w_lvds_rx_09_d0 +.sym 5607 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5608 w_lvds_rx_09_d1 +.sym 5609 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5612 w_rx_24_fifo_data[2] +.sym 5613 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5614 w_rx_09_fifo_data[2] +.sym 5618 w_rx_09_fifo_data[1] +.sym 5619 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 5621 w_rx_24_fifo_data[1] +.sym 5625 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5626 w_rx_24_fifo_data[1] +.sym 5628 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5629 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5645 rx_fifo.wr_addr[0] -.sym 5649 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5651 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 5653 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 5654 w_rx_fifo_full -.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 5661 $PACKER_VCC_NET -.sym 5662 $PACKER_VCC_NET -.sym 5672 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5673 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5674 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 5677 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 5678 rx_fifo.rd_addr_gray_wr[8] -.sym 5679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 5681 rx_fifo.rd_addr_gray_wr[5] -.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 5687 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 5689 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 5690 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5692 rx_fifo.rd_addr_gray[8] -.sym 5693 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5696 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 5697 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 5700 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 5703 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 5705 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 5706 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5711 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 5712 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5714 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5717 rx_fifo.rd_addr_gray_wr[8] -.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 5729 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5730 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 5731 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 5732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 5738 rx_fifo.rd_addr_gray_wr[5] -.sym 5743 rx_fifo.rd_addr_gray[8] -.sym 5747 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5748 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5749 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 5750 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5630 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 5632 w_rx_fifo_pulled_data[1] +.sym 5636 w_rx_fifo_pulled_data[3] +.sym 5644 rx_fifo.wr_addr[3] +.sym 5649 rx_fifo.wr_addr[0] +.sym 5651 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 5653 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 5656 rx_fifo.rd_addr[8] +.sym 5657 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 5658 w_rx_24_fifo_data[1] +.sym 5659 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5674 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5675 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 5685 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 5687 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5689 w_lvds_rx_09_d0 +.sym 5695 w_lvds_rx_09_d1 +.sym 5698 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5701 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5707 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5712 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5713 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5730 w_lvds_rx_09_d0 +.sym 5735 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 5737 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5738 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5741 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5743 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 5744 w_lvds_rx_09_d1 +.sym 5751 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 5752 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5766 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 5773 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 5776 rx_fifo.wr_addr[9] -.sym 5777 rx_fifo.rd_addr_gray_wr[5] -.sym 5780 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 5786 $PACKER_VCC_NET -.sym 5789 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 5797 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5798 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 5799 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 5800 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5801 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 5803 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 5804 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 5805 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5806 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 5807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5808 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 5814 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5815 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5819 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5821 w_lvds_rx_24_d1 -.sym 5826 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5828 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 5829 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 5831 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5840 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 5841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 5842 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 5843 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 5847 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 5852 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5853 w_lvds_rx_24_d1 -.sym 5854 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5866 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 5867 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5763 o_shdn_tx_lna$SB_IO_OUT +.sym 5764 o_shdn_tx_lna$SB_IO_OUT +.sym 5767 rx_fifo.rd_addr[7] +.sym 5770 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5771 rx_fifo.rd_addr[1] +.sym 5772 rx_fifo.rd_addr[9] +.sym 5774 rx_fifo.rd_addr[2] +.sym 5775 rx_fifo.rd_addr[3] +.sym 5776 w_rx_09_fifo_data[2] +.sym 5777 rx_fifo.rd_addr[6] +.sym 5779 $PACKER_VCC_NET +.sym 5806 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 5808 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5811 w_lvds_rx_24_d0 +.sym 5812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5813 w_lvds_rx_24_d1 +.sym 5819 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5846 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5847 w_lvds_rx_24_d1 +.sym 5848 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5849 w_lvds_rx_24_d0 +.sym 5858 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5859 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5860 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5861 w_lvds_rx_24_d1 +.sym 5873 w_lvds_rx_24_d0 .sym 5874 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5875 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5892 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 5895 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5896 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5898 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5900 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 5919 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 5921 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5922 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 5926 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5927 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 5929 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 5930 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 5932 $PACKER_VCC_NET -.sym 5933 $PACKER_VCC_NET -.sym 5936 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 5941 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5945 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 5947 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 5950 $nextpnr_ICESTORM_LC_2$O -.sym 5952 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 5956 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 5957 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5958 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 5959 $PACKER_VCC_NET -.sym 5960 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 5963 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 5964 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5965 $PACKER_VCC_NET -.sym 5966 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 5969 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5970 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 5971 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5972 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 5978 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5981 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 5988 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 5989 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 5990 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5994 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 5995 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 5897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5908 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 5909 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 5920 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 5924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5927 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5929 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5936 w_rx_fifo_full +.sym 5939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5951 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5957 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5958 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5960 w_rx_fifo_full +.sym 5989 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5990 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5997 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E .sym 5998 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6043 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 6044 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 6050 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6051 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 6058 $PACKER_VCC_NET -.sym 6059 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 6060 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 6062 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 6063 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 6066 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 6070 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 6072 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 6073 $nextpnr_ICESTORM_LC_0$O -.sym 6075 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 6079 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 6080 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6081 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 6082 $PACKER_VCC_NET -.sym 6083 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 6086 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6087 $PACKER_VCC_NET -.sym 6088 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 6089 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 6092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 6093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 6094 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 6095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6106 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 6110 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 6111 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 6112 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 6113 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 6117 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 6120 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 6056 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 6058 w_rx_fifo_full +.sym 6068 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 6110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 6113 w_rx_fifo_full +.sym 6120 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E .sym 6121 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 6294 o_shdn_tx_lna$SB_IO_OUT -.sym 6305 o_shdn_tx_lna$SB_IO_OUT -.sym 6346 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 6347 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 6348 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 6349 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 6351 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 6352 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 6353 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 6390 $PACKER_VCC_NET -.sym 6391 rx_fifo.wr_addr[5] -.sym 6393 rx_fifo.wr_addr[7] -.sym 6395 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 6398 rx_fifo.wr_addr[3] -.sym 6399 rx_fifo.wr_addr[1] -.sym 6402 rx_fifo.wr_addr[4] -.sym 6404 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6405 rx_fifo.wr_addr[9] -.sym 6408 rx_fifo.mem_q.0.3_WDATA_3 -.sym 6412 rx_fifo.wr_addr[0] -.sym 6413 rx_fifo.wr_addr[6] -.sym 6415 rx_fifo.mem_q.0.3_WDATA_2 -.sym 6417 rx_fifo.wr_addr[8] -.sym 6422 w_rx_24_fifo_data[23] -.sym 6423 w_rx_24_fifo_data[20] -.sym 6424 w_rx_24_fifo_data[25] -.sym 6425 rx_fifo.wr_addr[9] -.sym 6426 w_rx_24_fifo_data[31] -.sym 6427 w_rx_24_fifo_data[27] -.sym 6428 w_rx_24_fifo_data[29] -.sym 6429 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 6314 o_shdn_tx_lna$SB_IO_OUT +.sym 6359 $PACKER_VCC_NET +.sym 6381 w_smi_data_output[3] +.sym 6387 rx_fifo.wr_addr[0] +.sym 6388 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6389 rx_fifo.wr_addr[9] +.sym 6390 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6394 rx_fifo.wr_addr[7] +.sym 6395 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6398 rx_fifo.wr_addr[5] +.sym 6399 rx_fifo.wr_addr[8] +.sym 6401 rx_fifo.wr_addr[6] +.sym 6404 rx_fifo.wr_addr[1] +.sym 6406 $PACKER_VCC_NET +.sym 6407 rx_fifo.wr_addr[3] +.sym 6408 rx_fifo.wr_addr[4] +.sym 6413 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6422 rx_fifo.mem_i.0.1_WDATA_1 +.sym 6423 w_rx_24_fifo_data[23] +.sym 6424 rx_fifo.mem_i.0.1_WDATA +.sym 6425 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6426 w_rx_24_fifo_data[27] +.sym 6427 rx_fifo.mem_i.0.2_WDATA +.sym 6428 w_rx_24_fifo_data[25] +.sym 6429 w_rx_24_fifo_data[29] +.sym 6438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 6439 rx_fifo.wr_addr[3] .sym 6441 rx_fifo.wr_addr[4] .sym 6442 rx_fifo.wr_addr[5] @@ -6055,39 +5919,49 @@ .sym 6447 rx_fifo.wr_addr[1] .sym 6448 rx_fifo.wr_addr[0] .sym 6449 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6450 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6452 rx_fifo.mem_q.0.3_WDATA_3 -.sym 6456 rx_fifo.mem_q.0.3_WDATA_2 +.sym 6450 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6452 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6456 rx_fifo.mem_i.0.2_WDATA_2 .sym 6459 $PACKER_VCC_NET -.sym 6470 smi_ctrl_ins.int_cnt_rx[4] -.sym 6486 w_rx_fifo_pulled_data[7] -.sym 6502 smi_ctrl_ins.int_cnt_rx[3] -.sym 6514 w_smi_data_output[6] -.sym 6517 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 6518 rx_fifo.wr_addr[8] -.sym 6519 $PACKER_VCC_NET -.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6531 rx_fifo.rd_addr[3] -.sym 6533 rx_fifo.rd_addr[0] -.sym 6534 rx_fifo.rd_addr[8] +.sym 6481 rx_fifo.wr_addr[3] +.sym 6482 rx_fifo.wr_addr[4] +.sym 6493 rx_fifo.wr_addr[7] +.sym 6495 w_smi_data_output[6] +.sym 6496 rx_fifo.wr_addr[9] +.sym 6497 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6500 rx_fifo.wr_addr[9] +.sym 6501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6503 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6504 rx_fifo.wr_addr[1] +.sym 6506 $PACKER_VCC_NET +.sym 6507 $PACKER_VCC_NET +.sym 6508 rx_fifo.mem_i.0.0_WDATA_2 +.sym 6511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 6512 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 6519 rx_fifo.wr_addr[8] +.sym 6521 rx_fifo.wr_addr[6] +.sym 6528 rx_fifo.rd_addr[6] +.sym 6530 rx_fifo.rd_addr[8] +.sym 6533 rx_fifo.rd_addr[3] .sym 6535 rx_fifo.rd_addr[7] -.sym 6537 rx_fifo.rd_addr[2] -.sym 6546 rx_fifo.rd_addr[6] -.sym 6548 rx_fifo.mem_q.0.3_WDATA_1 -.sym 6549 rx_fifo.rd_addr[5] -.sym 6553 rx_fifo.rd_addr[4] -.sym 6555 rx_fifo.rd_addr[1] -.sym 6557 $PACKER_VCC_NET -.sym 6558 rx_fifo.rd_addr[9] -.sym 6559 rx_fifo.mem_q.0.3_WDATA -.sym 6560 rx_fifo.mem_i.0.1_WDATA_3 -.sym 6561 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 6562 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 6563 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 6564 rx_fifo.mem_i.0.1_WDATA -.sym 6565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 6566 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 6567 rx_fifo.mem_i.0.1_WDATA_1 +.sym 6538 rx_fifo.rd_addr[5] +.sym 6541 $PACKER_VCC_NET +.sym 6542 rx_fifo.rd_addr[9] +.sym 6543 rx_fifo.rd_addr[4] +.sym 6546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6549 rx_fifo.rd_addr[0] +.sym 6550 rx_fifo.rd_addr[1] +.sym 6555 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6557 rx_fifo.mem_i.0.2_WDATA +.sym 6559 rx_fifo.rd_addr[2] +.sym 6560 rx_fifo.mem_i.0.3_WDATA +.sym 6561 w_rx_24_fifo_data[28] +.sym 6562 w_rx_24_fifo_data[30] +.sym 6563 rx_fifo.mem_i.0.3_WDATA_3 +.sym 6564 w_rx_24_fifo_data[21] +.sym 6565 rx_fifo.mem_i.0.3_WDATA_1 +.sym 6566 w_rx_24_fifo_data[31] +.sym 6567 rx_fifo.mem_i.0.3_WDATA_2 .sym 6576 rx_fifo.rd_addr[2] .sym 6577 rx_fifo.rd_addr[3] .sym 6579 rx_fifo.rd_addr[4] @@ -6099,43 +5973,41 @@ .sym 6585 rx_fifo.rd_addr[1] .sym 6586 rx_fifo.rd_addr[0] .sym 6587 r_counter_$glb_clk -.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 6589 $PACKER_VCC_NET -.sym 6593 rx_fifo.mem_q.0.3_WDATA -.sym 6597 rx_fifo.mem_q.0.3_WDATA_1 -.sym 6607 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6612 rx_fifo.mem_i.0.2_WDATA -.sym 6614 rx_fifo.wr_addr[9] -.sym 6617 rx_fifo.rd_addr[7] -.sym 6619 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 6620 i_rst_b$SB_IO_IN -.sym 6622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 6623 $PACKER_VCC_NET -.sym 6624 rx_fifo.rd_addr[9] -.sym 6625 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 6630 rx_fifo.wr_addr[4] -.sym 6631 rx_fifo.wr_addr[9] -.sym 6632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6634 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6636 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6637 rx_fifo.wr_addr[0] -.sym 6641 rx_fifo.wr_addr[6] -.sym 6642 rx_fifo.wr_addr[5] -.sym 6644 rx_fifo.wr_addr[3] -.sym 6645 rx_fifo.wr_addr[1] +.sym 6593 rx_fifo.mem_i.0.2_WDATA +.sym 6597 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6602 w_rx_09_fifo_data[23] +.sym 6604 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 6610 rx_fifo.mem_i.0.1_WDATA_2 +.sym 6611 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 6613 rx_fifo.mem_i.0.1_WDATA +.sym 6616 w_rx_24_fifo_data[26] +.sym 6617 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 6619 rx_fifo.wr_addr[6] +.sym 6620 rx_fifo.wr_addr[6] +.sym 6622 rx_fifo.wr_addr[8] +.sym 6631 rx_fifo.wr_addr[3] +.sym 6632 rx_fifo.wr_addr[8] +.sym 6634 rx_fifo.wr_addr[6] +.sym 6638 rx_fifo.wr_addr[7] +.sym 6639 rx_fifo.mem_i.0.0_WDATA_3 +.sym 6641 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6644 rx_fifo.wr_addr[9] +.sym 6645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6648 rx_fifo.wr_addr[1] .sym 6650 $PACKER_VCC_NET -.sym 6659 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 6660 rx_fifo.wr_addr[7] -.sym 6661 rx_fifo.wr_addr[8] -.sym 6662 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 6663 w_smi_data_output[0] -.sym 6664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 6665 w_smi_data_output[6] -.sym 6666 w_smi_data_output[1] -.sym 6667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 6668 w_smi_data_output[3] -.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 6678 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 6651 rx_fifo.wr_addr[0] +.sym 6652 rx_fifo.mem_i.0.0_WDATA_2 +.sym 6657 rx_fifo.wr_addr[4] +.sym 6660 rx_fifo.wr_addr[5] +.sym 6663 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 6665 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 6666 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 6667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 6668 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 6669 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 6678 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 6679 rx_fifo.wr_addr[3] .sym 6681 rx_fifo.wr_addr[4] .sym 6682 rx_fifo.wr_addr[5] @@ -6146,37 +6018,44 @@ .sym 6687 rx_fifo.wr_addr[1] .sym 6688 rx_fifo.wr_addr[0] .sym 6689 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6690 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6690 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] .sym 6692 rx_fifo.mem_i.0.0_WDATA_3 .sym 6696 rx_fifo.mem_i.0.0_WDATA_2 .sym 6699 $PACKER_VCC_NET -.sym 6704 smi_ctrl_ins.int_cnt_rx[3] -.sym 6712 w_rx_24_fifo_data[21] -.sym 6713 rx_fifo.wr_addr[0] -.sym 6720 rx_fifo.wr_addr[5] -.sym 6721 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 6723 w_rx_fifo_pulled_data[5] -.sym 6734 rx_fifo.mem_i.0.0_WDATA -.sym 6737 rx_fifo.rd_addr[5] +.sym 6706 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6707 smi_ctrl_ins.int_cnt_rx[3] +.sym 6709 rx_fifo.mem_i.0.3_WDATA_2 +.sym 6710 i_rst_b$SB_IO_IN +.sym 6713 w_rx_09_fifo_data[30] +.sym 6714 rx_fifo.rd_addr[3] +.sym 6715 rx_fifo.rd_addr[4] +.sym 6718 rx_fifo.wr_addr[4] +.sym 6719 w_rx_24_fifo_data[19] +.sym 6721 rx_fifo.wr_addr[3] +.sym 6723 rx_fifo.wr_addr[4] +.sym 6724 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 6726 w_rx_fifo_pulled_data[7] +.sym 6733 rx_fifo.rd_addr[3] +.sym 6734 rx_fifo.rd_addr[4] +.sym 6735 rx_fifo.rd_addr[7] +.sym 6736 rx_fifo.rd_addr[6] +.sym 6737 rx_fifo.rd_addr[0] .sym 6738 rx_fifo.rd_addr[1] -.sym 6743 rx_fifo.rd_addr[6] -.sym 6744 rx_fifo.rd_addr[0] -.sym 6746 rx_fifo.rd_addr[3] -.sym 6747 rx_fifo.rd_addr[2] -.sym 6748 rx_fifo.rd_addr[4] -.sym 6750 rx_fifo.rd_addr[8] -.sym 6755 rx_fifo.rd_addr[7] -.sym 6759 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6743 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6747 rx_fifo.mem_i.0.0_WDATA_1 +.sym 6748 rx_fifo.rd_addr[8] +.sym 6751 rx_fifo.rd_addr[9] +.sym 6759 rx_fifo.mem_i.0.0_WDATA .sym 6761 $PACKER_VCC_NET -.sym 6762 rx_fifo.rd_addr[9] -.sym 6763 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 6762 rx_fifo.rd_addr[5] +.sym 6763 rx_fifo.rd_addr[2] +.sym 6765 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 6766 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 6767 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 6768 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 6769 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 6770 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 6771 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] .sym 6780 rx_fifo.rd_addr[2] .sym 6781 rx_fifo.rd_addr[3] .sym 6783 rx_fifo.rd_addr[4] @@ -6188,34 +6067,42 @@ .sym 6789 rx_fifo.rd_addr[1] .sym 6790 rx_fifo.rd_addr[0] .sym 6791 r_counter_$glb_clk -.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 6793 $PACKER_VCC_NET .sym 6797 rx_fifo.mem_i.0.0_WDATA .sym 6801 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6807 w_smi_data_output[3] -.sym 6809 smi_ctrl_ins.int_cnt_rx[3] -.sym 6813 smi_ctrl_ins.int_cnt_rx[3] -.sym 6819 smi_ctrl_ins.int_cnt_rx[4] -.sym 6821 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6825 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6827 smi_ctrl_ins.int_cnt_rx[3] -.sym 6829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 6834 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 6836 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6837 rx_fifo.wr_addr[3] -.sym 6838 rx_fifo.mem_i.0.2_WDATA_2 -.sym 6843 rx_fifo.wr_addr[1] -.sym 6847 $PACKER_VCC_NET -.sym 6848 rx_fifo.wr_addr[7] -.sym 6854 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6855 rx_fifo.wr_addr[9] -.sym 6858 rx_fifo.wr_addr[5] -.sym 6860 rx_fifo.wr_addr[0] -.sym 6861 rx_fifo.wr_addr[8] -.sym 6863 rx_fifo.wr_addr[6] -.sym 6865 rx_fifo.wr_addr[4] -.sym 6868 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 6882 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 6809 smi_ctrl_ins.int_cnt_rx[4] +.sym 6813 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6819 rx_fifo.wr_addr[7] +.sym 6820 rx_fifo.wr_addr[9] +.sym 6822 smi_ctrl_ins.int_cnt_rx[3] +.sym 6823 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6824 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6825 w_rx_fifo_pulled_data[5] +.sym 6829 rx_fifo.wr_addr[1] +.sym 6837 rx_fifo.wr_addr[9] +.sym 6838 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6839 rx_fifo.wr_addr[3] +.sym 6842 rx_fifo.wr_addr[7] +.sym 6846 rx_fifo.wr_addr[0] +.sym 6848 rx_fifo.wr_addr[5] +.sym 6849 rx_fifo.wr_addr[6] +.sym 6850 rx_fifo.mem_q.0.1_WDATA_2 +.sym 6852 rx_fifo.wr_addr[1] +.sym 6854 rx_fifo.mem_q.0.1_WDATA_3 +.sym 6856 rx_fifo.wr_addr[4] +.sym 6859 rx_fifo.wr_addr[8] +.sym 6861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6863 $PACKER_VCC_NET +.sym 6866 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 6867 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6868 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 6869 rx_fifo.wr_addr_gray_rd[0] +.sym 6870 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 6871 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 6872 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 6873 rx_fifo.wr_addr_gray_rd[5] +.sym 6882 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 6883 rx_fifo.wr_addr[3] .sym 6885 rx_fifo.wr_addr[4] .sym 6886 rx_fifo.wr_addr[5] @@ -6226,43 +6113,46 @@ .sym 6891 rx_fifo.wr_addr[1] .sym 6892 rx_fifo.wr_addr[0] .sym 6893 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6894 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 6896 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6900 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6894 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6896 rx_fifo.mem_q.0.1_WDATA_3 +.sym 6900 rx_fifo.mem_q.0.1_WDATA_2 .sym 6903 $PACKER_VCC_NET -.sym 6908 rx_fifo.rd_addr[5] -.sym 6910 rx_fifo.rd_addr[3] -.sym 6912 rx_fifo.rd_addr[6] -.sym 6914 rx_fifo.rd_addr[0] +.sym 6908 rx_fifo.rd_addr[0] +.sym 6912 rx_fifo.rd_addr[2] +.sym 6915 smi_ctrl_ins.int_cnt_rx[3] .sym 6916 rx_fifo.rd_addr[1] -.sym 6917 w_rx_fifo_pulled_data[6] -.sym 6918 w_rx_24_fifo_data[28] -.sym 6920 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 6921 rx_fifo.wr_addr[9] -.sym 6923 rx_fifo.wr_addr[8] -.sym 6924 rx_fifo.rd_addr[9] -.sym 6927 rx_fifo.wr_addr[8] -.sym 6929 rx_fifo.mem_q.0.2_WDATA_1 -.sym 6936 rx_fifo.rd_addr[8] -.sym 6938 rx_fifo.mem_i.0.2_WDATA -.sym 6940 $PACKER_VCC_NET -.sym 6941 rx_fifo.rd_addr[9] -.sym 6945 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6948 rx_fifo.rd_addr[7] -.sym 6950 rx_fifo.rd_addr[3] -.sym 6951 rx_fifo.rd_addr[2] -.sym 6952 rx_fifo.rd_addr[1] -.sym 6957 rx_fifo.rd_addr[5] -.sym 6961 rx_fifo.rd_addr[4] -.sym 6963 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6966 rx_fifo.rd_addr[0] -.sym 6967 rx_fifo.rd_addr[6] -.sym 6969 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 6970 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 6972 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 6973 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 6974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 6975 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 6917 rx_fifo.rd_addr[4] +.sym 6920 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 6922 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 6923 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 6924 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 6925 rx_fifo.wr_addr[6] +.sym 6928 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 6929 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 6930 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 6931 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6936 rx_fifo.rd_addr[4] +.sym 6938 rx_fifo.rd_addr[6] +.sym 6941 rx_fifo.rd_addr[3] +.sym 6942 rx_fifo.rd_addr[8] +.sym 6948 rx_fifo.rd_addr[9] +.sym 6949 $PACKER_VCC_NET +.sym 6950 rx_fifo.rd_addr[5] +.sym 6951 rx_fifo.rd_addr[1] +.sym 6952 rx_fifo.mem_q.0.1_WDATA_1 +.sym 6957 rx_fifo.rd_addr[0] +.sym 6962 rx_fifo.rd_addr[7] +.sym 6963 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6965 rx_fifo.rd_addr[2] +.sym 6967 rx_fifo.mem_q.0.1_WDATA +.sym 6968 rx_fifo.wr_addr[7] +.sym 6969 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 6970 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6971 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 6972 rx_fifo.wr_addr_gray[5] +.sym 6973 rx_fifo.wr_addr[1] +.sym 6974 rx_fifo.wr_addr_gray[0] +.sym 6975 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] .sym 6984 rx_fifo.rd_addr[2] .sym 6985 rx_fifo.rd_addr[3] .sym 6987 rx_fifo.rd_addr[4] @@ -6274,41 +6164,47 @@ .sym 6993 rx_fifo.rd_addr[1] .sym 6994 rx_fifo.rd_addr[0] .sym 6995 r_counter_$glb_clk -.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 6997 $PACKER_VCC_NET -.sym 7001 rx_fifo.mem_i.0.2_WDATA -.sym 7005 rx_fifo.mem_i.0.2_WDATA_1 -.sym 7011 $PACKER_VCC_NET -.sym 7015 rx_fifo.wr_addr[3] -.sym 7017 io_pmod[7]$SB_IO_IN -.sym 7021 i_rst_b_SB_LUT4_I3_O -.sym 7022 $PACKER_VCC_NET -.sym 7024 rx_fifo.rd_addr[7] -.sym 7026 rx_fifo.wr_addr[9] -.sym 7027 i_rst_b$SB_IO_IN -.sym 7028 rx_fifo.rd_addr[3] -.sym 7029 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 7031 rx_fifo.rd_addr[9] +.sym 7001 rx_fifo.mem_q.0.1_WDATA +.sym 7005 rx_fifo.mem_q.0.1_WDATA_1 +.sym 7010 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 7012 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 7013 rx_fifo.wr_addr_gray_rd[0] +.sym 7014 rx_fifo.rd_addr[6] +.sym 7018 rx_fifo.wr_addr[5] +.sym 7020 rx_fifo.wr_addr[0] +.sym 7023 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 7027 rx_fifo.wr_addr[6] +.sym 7028 i_rst_b$SB_IO_IN +.sym 7029 rx_fifo.wr_addr[8] +.sym 7030 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 7031 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 7033 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 7040 rx_fifo.mem_q.0.3_WDATA_3 .sym 7042 $PACKER_VCC_NET -.sym 7044 rx_fifo.wr_addr[1] -.sym 7045 rx_fifo.wr_addr[5] -.sym 7046 rx_fifo.wr_addr[3] -.sym 7048 rx_fifo.wr_addr[0] -.sym 7049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 7051 rx_fifo.wr_addr[6] -.sym 7053 rx_fifo.wr_addr[4] -.sym 7059 rx_fifo.wr_addr[9] -.sym 7060 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7061 rx_fifo.wr_addr[7] -.sym 7063 rx_fifo.mem_q.0.2_WDATA_2 -.sym 7065 rx_fifo.wr_addr[8] -.sym 7067 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 7073 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 7077 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 7086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 7044 rx_fifo.wr_addr[8] +.sym 7049 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7050 rx_fifo.wr_addr[0] +.sym 7051 rx_fifo.mem_q.0.3_WDATA_2 +.sym 7052 rx_fifo.wr_addr[3] +.sym 7056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7057 rx_fifo.wr_addr[5] +.sym 7060 rx_fifo.wr_addr[4] +.sym 7061 rx_fifo.wr_addr[9] +.sym 7062 rx_fifo.wr_addr[7] +.sym 7063 rx_fifo.wr_addr[6] +.sym 7067 rx_fifo.wr_addr[1] +.sym 7070 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 7071 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 7072 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 7073 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 7074 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 7075 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 7076 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 7077 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 7086 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 7087 rx_fifo.wr_addr[3] .sym 7089 rx_fifo.wr_addr[4] .sym 7090 rx_fifo.wr_addr[5] @@ -6319,38 +6215,47 @@ .sym 7095 rx_fifo.wr_addr[1] .sym 7096 rx_fifo.wr_addr[0] .sym 7097 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7098 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 7100 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7104 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7098 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7100 rx_fifo.mem_q.0.3_WDATA_3 +.sym 7104 rx_fifo.mem_q.0.3_WDATA_2 .sym 7107 $PACKER_VCC_NET -.sym 7115 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7118 $PACKER_VCC_NET -.sym 7124 rx_fifo.wr_addr[1] -.sym 7126 w_rx_fifo_pulled_data[1] -.sym 7128 rx_fifo.wr_addr[5] -.sym 7130 rx_fifo.wr_addr[3] -.sym 7134 w_rx_fifo_pulled_data[3] -.sym 7140 rx_fifo.rd_addr[4] -.sym 7142 rx_fifo.rd_addr[8] -.sym 7145 rx_fifo.rd_addr[5] -.sym 7146 rx_fifo.rd_addr[6] +.sym 7109 $PACKER_VCC_NET +.sym 7114 $PACKER_VCC_NET +.sym 7115 rx_fifo.rd_addr[5] +.sym 7117 $PACKER_VCC_NET +.sym 7119 rx_fifo.wr_addr[7] +.sym 7121 $PACKER_VCC_NET +.sym 7123 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7124 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7125 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 7126 rx_fifo.wr_addr[4] +.sym 7128 rx_fifo.wr_addr[3] +.sym 7129 rx_fifo.rd_addr_gray_wr_r[8] +.sym 7131 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 7132 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 7134 rx_fifo.wr_addr[0] +.sym 7144 rx_fifo.rd_addr[6] +.sym 7145 rx_fifo.rd_addr[0] +.sym 7146 rx_fifo.rd_addr[4] .sym 7148 rx_fifo.rd_addr[7] -.sym 7149 rx_fifo.mem_q.0.2_WDATA -.sym 7151 rx_fifo.rd_addr[1] -.sym 7152 rx_fifo.rd_addr[0] -.sym 7155 rx_fifo.rd_addr[2] -.sym 7156 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7160 $PACKER_VCC_NET -.sym 7166 rx_fifo.rd_addr[3] -.sym 7167 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7168 rx_fifo.rd_addr[9] -.sym 7172 rx_fifo.rd_addr_gray[0] -.sym 7173 rx_fifo.rd_addr_gray[8] -.sym 7174 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 7175 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] -.sym 7176 rx_fifo.rd_addr[9] -.sym 7177 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 7179 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 7151 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7152 rx_fifo.rd_addr[3] +.sym 7153 rx_fifo.rd_addr[2] +.sym 7154 rx_fifo.rd_addr[5] +.sym 7155 rx_fifo.rd_addr[1] +.sym 7159 rx_fifo.rd_addr[9] +.sym 7162 rx_fifo.mem_q.0.3_WDATA_1 +.sym 7165 rx_fifo.rd_addr[8] +.sym 7167 rx_fifo.mem_q.0.3_WDATA +.sym 7169 $PACKER_VCC_NET +.sym 7172 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 7173 rx_fifo.rd_addr[8] +.sym 7174 rx_fifo.wr_addr[6] +.sym 7175 rx_fifo.wr_addr[8] +.sym 7176 rx_fifo.wr_addr_gray[2] +.sym 7177 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 7178 rx_fifo.wr_addr_gray[4] +.sym 7179 rx_fifo.wr_addr[4] .sym 7188 rx_fifo.rd_addr[2] .sym 7189 rx_fifo.rd_addr[3] .sym 7191 rx_fifo.rd_addr[4] @@ -6362,40 +6267,45 @@ .sym 7197 rx_fifo.rd_addr[1] .sym 7198 rx_fifo.rd_addr[0] .sym 7199 r_counter_$glb_clk -.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7200 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 7201 $PACKER_VCC_NET -.sym 7205 rx_fifo.mem_q.0.2_WDATA -.sym 7209 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7216 rx_fifo.rd_addr[8] -.sym 7224 rx_fifo.rd_addr[4] -.sym 7227 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7229 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 7233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7234 rx_fifo.wr_addr_gray_rd[5] -.sym 7236 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 7244 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 7248 rx_fifo.mem_q.0.0_WDATA_2 -.sym 7249 rx_fifo.wr_addr[7] -.sym 7251 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7253 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 7205 rx_fifo.mem_q.0.3_WDATA +.sym 7209 rx_fifo.mem_q.0.3_WDATA_1 +.sym 7216 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 7218 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 7226 rx_fifo.rd_addr_gray_wr_r[6] +.sym 7227 rx_fifo.wr_addr[9] +.sym 7228 rx_fifo.rd_addr_gray_wr_r[7] +.sym 7230 $PACKER_VCC_NET +.sym 7231 rx_fifo.wr_addr[1] +.sym 7232 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7233 rx_fifo.rd_addr[4] +.sym 7235 $PACKER_VCC_NET +.sym 7236 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 7237 rx_fifo.wr_addr[1] +.sym 7246 rx_fifo.wr_addr[1] +.sym 7247 rx_fifo.wr_addr[5] +.sym 7250 rx_fifo.wr_addr[9] +.sym 7251 rx_fifo.mem_q.0.2_WDATA_3 +.sym 7253 rx_fifo.wr_addr[8] .sym 7255 $PACKER_VCC_NET -.sym 7258 rx_fifo.wr_addr[6] -.sym 7260 rx_fifo.wr_addr[4] -.sym 7261 rx_fifo.wr_addr[0] -.sym 7262 rx_fifo.wr_addr[1] -.sym 7263 rx_fifo.wr_addr[9] -.sym 7266 rx_fifo.wr_addr[5] -.sym 7268 rx_fifo.wr_addr[3] -.sym 7269 rx_fifo.wr_addr[8] -.sym 7274 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 7275 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 7276 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 7277 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 7278 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 7279 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 7280 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 7281 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 7290 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 7257 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7260 rx_fifo.wr_addr[6] +.sym 7261 rx_fifo.wr_addr[7] +.sym 7262 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7266 rx_fifo.wr_addr[3] +.sym 7269 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7272 rx_fifo.wr_addr[0] +.sym 7273 rx_fifo.wr_addr[4] +.sym 7274 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 7275 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 7276 rx_fifo.rd_addr_gray_wr_r[8] +.sym 7277 rx_fifo.rd_addr_gray_wr[7] +.sym 7278 rx_fifo.rd_addr_gray_wr[6] +.sym 7279 rx_fifo.rd_addr_gray_wr[0] +.sym 7280 rx_fifo.rd_addr_gray_wr_r[6] +.sym 7281 rx_fifo.rd_addr_gray_wr_r[7] +.sym 7290 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 7291 rx_fifo.wr_addr[3] .sym 7293 rx_fifo.wr_addr[4] .sym 7294 rx_fifo.wr_addr[5] @@ -6406,41 +6316,44 @@ .sym 7299 rx_fifo.wr_addr[1] .sym 7300 rx_fifo.wr_addr[0] .sym 7301 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7302 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 7304 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7308 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7302 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7304 rx_fifo.mem_q.0.2_WDATA_3 +.sym 7308 rx_fifo.mem_q.0.2_WDATA_2 .sym 7311 $PACKER_VCC_NET -.sym 7321 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 7322 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7323 $PACKER_VCC_NET -.sym 7325 rx_fifo.rd_addr_gray[8] -.sym 7329 rx_fifo.wr_addr[9] -.sym 7332 rx_fifo.rd_addr[9] -.sym 7333 rx_fifo.rd_addr_gray_wr_r[7] -.sym 7334 rx_fifo.rd_addr[8] -.sym 7335 rx_fifo.wr_addr[8] -.sym 7344 rx_fifo.rd_addr[1] +.sym 7316 rx_fifo.rd_addr[5] +.sym 7319 rx_fifo.wr_addr[8] +.sym 7321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 7324 rx_fifo.rd_addr[4] +.sym 7327 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 7328 rx_fifo.wr_addr[6] +.sym 7329 w_rx_09_fifo_data[2] +.sym 7330 rx_fifo.wr_addr[8] +.sym 7335 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 7337 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7338 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7339 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7344 rx_fifo.mem_q.0.2_WDATA .sym 7345 rx_fifo.rd_addr[7] -.sym 7348 $PACKER_VCC_NET -.sym 7349 rx_fifo.rd_addr[0] -.sym 7350 rx_fifo.rd_addr[2] -.sym 7353 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7354 rx_fifo.rd_addr[3] -.sym 7355 rx_fifo.mem_q.0.0_WDATA -.sym 7356 rx_fifo.rd_addr[9] -.sym 7359 rx_fifo.rd_addr[8] -.sym 7360 rx_fifo.rd_addr[6] -.sym 7362 rx_fifo.rd_addr[4] -.sym 7371 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7374 rx_fifo.rd_addr[5] -.sym 7376 rx_fifo.wr_addr_gray_rd[7] -.sym 7377 rx_fifo.wr_addr_gray_rd[2] -.sym 7378 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 7379 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 7380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 7381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 7382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 7383 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 7346 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7348 rx_fifo.rd_addr[6] +.sym 7349 rx_fifo.rd_addr[3] +.sym 7350 rx_fifo.rd_addr[8] +.sym 7352 rx_fifo.rd_addr[5] +.sym 7354 rx_fifo.rd_addr[9] +.sym 7355 rx_fifo.mem_q.0.2_WDATA_1 +.sym 7359 rx_fifo.rd_addr[1] +.sym 7365 rx_fifo.rd_addr[0] +.sym 7366 rx_fifo.rd_addr[2] +.sym 7371 rx_fifo.rd_addr[4] +.sym 7373 $PACKER_VCC_NET +.sym 7376 rx_fifo.wr_addr[9] +.sym 7377 rx_fifo.wr_addr_gray[3] +.sym 7378 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 7379 rx_fifo.wr_addr_gray[8] +.sym 7380 rx_fifo.wr_addr_gray[1] +.sym 7381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 7382 rx_fifo.wr_addr_gray[6] +.sym 7383 rx_fifo.wr_addr_gray[7] .sym 7392 rx_fifo.rd_addr[2] .sym 7393 rx_fifo.rd_addr[3] .sym 7395 rx_fifo.rd_addr[4] @@ -6452,3651 +6365,4043 @@ .sym 7401 rx_fifo.rd_addr[1] .sym 7402 rx_fifo.rd_addr[0] .sym 7403 r_counter_$glb_clk -.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7404 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 7405 $PACKER_VCC_NET -.sym 7409 rx_fifo.mem_q.0.0_WDATA -.sym 7413 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7418 $PACKER_VCC_NET -.sym 7420 o_led1$SB_IO_OUT -.sym 7424 $PACKER_VCC_NET +.sym 7409 rx_fifo.mem_q.0.2_WDATA +.sym 7413 rx_fifo.mem_q.0.2_WDATA_1 +.sym 7420 rx_fifo.rd_addr[9] +.sym 7421 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 7422 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7424 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] .sym 7425 i_rst_b$SB_IO_IN -.sym 7427 $PACKER_VCC_NET -.sym 7429 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 7433 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 7434 rx_fifo.wr_addr[9] +.sym 7426 rx_fifo.rd_addr[8] +.sym 7429 rx_fifo.rd_addr_gray_wr_r[8] +.sym 7433 rx_fifo.rd_addr_gray_wr[8] .sym 7435 i_rst_b$SB_IO_IN -.sym 7439 rx_fifo.wr_addr_gray_rd[4] -.sym 7440 rx_fifo.wr_addr[8] -.sym 7441 rx_fifo.wr_addr_gray_rd[6] -.sym 7478 rx_fifo.wr_addr[9] -.sym 7479 rx_fifo.wr_addr_gray[4] -.sym 7480 rx_fifo.wr_addr_gray[8] -.sym 7481 rx_fifo.wr_addr[8] -.sym 7482 rx_fifo.wr_addr_gray[3] -.sym 7483 rx_fifo.wr_addr_gray[7] -.sym 7484 rx_fifo.wr_addr_gray[6] -.sym 7485 rx_fifo.wr_addr_gray[2] -.sym 7516 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 7522 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7525 $PACKER_VCC_NET -.sym 7527 i_rst_b$SB_IO_IN -.sym 7531 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 7532 rx_fifo.wr_addr_gray_rd[3] -.sym 7534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 7536 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7541 rx_fifo.wr_addr[9] -.sym 7581 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 7582 rx_fifo.wr_addr_gray_rd[8] -.sym 7584 rx_fifo.wr_addr_gray_rd[4] -.sym 7585 rx_fifo.wr_addr_gray_rd[6] -.sym 7586 rx_fifo.wr_addr_gray_rd[3] -.sym 7587 rx_fifo.wr_addr_gray_rd[5] -.sym 7622 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 7624 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 7625 rx_fifo.wr_addr[8] -.sym 7628 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 7629 rx_fifo.wr_addr[9] -.sym 7630 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7634 w_rx_fifo_full -.sym 7638 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 7641 rx_fifo.wr_addr_gray_rd[5] -.sym 7643 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 7683 rx_fifo.wr_addr_gray[1] -.sym 7686 rx_fifo.wr_addr_gray[5] -.sym 7741 rx_fifo.rd_addr_gray_wr_r[7] -.sym 7788 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 7789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 7826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 7830 spi_if_ins.r_tx_byte[2] +.sym 7447 rx_fifo.wr_addr[0] +.sym 7448 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7449 rx_fifo.wr_addr[7] +.sym 7450 $PACKER_VCC_NET +.sym 7455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7458 rx_fifo.wr_addr[3] +.sym 7459 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7464 rx_fifo.wr_addr[1] +.sym 7466 rx_fifo.wr_addr[6] +.sym 7468 rx_fifo.wr_addr[8] +.sym 7470 rx_fifo.wr_addr[9] +.sym 7473 rx_fifo.wr_addr[4] +.sym 7476 rx_fifo.wr_addr[5] +.sym 7478 w_rx_09_fifo_data[2] +.sym 7494 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7495 rx_fifo.wr_addr[3] +.sym 7497 rx_fifo.wr_addr[4] +.sym 7498 rx_fifo.wr_addr[5] +.sym 7499 rx_fifo.wr_addr[6] +.sym 7500 rx_fifo.wr_addr[7] +.sym 7501 rx_fifo.wr_addr[8] +.sym 7502 rx_fifo.wr_addr[9] +.sym 7503 rx_fifo.wr_addr[1] +.sym 7504 rx_fifo.wr_addr[0] +.sym 7505 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 7508 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7512 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7515 $PACKER_VCC_NET +.sym 7539 rx_fifo.wr_addr[4] +.sym 7549 rx_fifo.rd_addr[9] +.sym 7550 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7551 rx_fifo.rd_addr[5] +.sym 7552 rx_fifo.rd_addr[6] +.sym 7553 rx_fifo.rd_addr[0] +.sym 7554 rx_fifo.rd_addr[1] +.sym 7557 rx_fifo.mem_q.0.0_WDATA +.sym 7558 rx_fifo.rd_addr[3] +.sym 7559 rx_fifo.rd_addr[2] +.sym 7560 rx_fifo.rd_addr[7] +.sym 7561 rx_fifo.rd_addr[4] +.sym 7564 rx_fifo.rd_addr[8] +.sym 7570 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7577 $PACKER_VCC_NET +.sym 7596 rx_fifo.rd_addr[2] +.sym 7597 rx_fifo.rd_addr[3] +.sym 7599 rx_fifo.rd_addr[4] +.sym 7600 rx_fifo.rd_addr[5] +.sym 7601 rx_fifo.rd_addr[6] +.sym 7602 rx_fifo.rd_addr[7] +.sym 7603 rx_fifo.rd_addr[8] +.sym 7604 rx_fifo.rd_addr[9] +.sym 7605 rx_fifo.rd_addr[1] +.sym 7606 rx_fifo.rd_addr[0] +.sym 7607 r_counter_$glb_clk +.sym 7608 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7609 $PACKER_VCC_NET +.sym 7613 rx_fifo.mem_q.0.0_WDATA +.sym 7617 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7746 o_shdn_rx_lna$SB_IO_OUT .sym 7838 i_rst_b$SB_IO_IN -.sym 7888 rx_fifo.rd_addr_gray_wr_r[7] .sym 8093 w_smi_data_output[6] -.sym 8095 o_led0$SB_IO_OUT +.sym 8095 w_smi_data_direction .sym 8099 $PACKER_VCC_NET -.sym 8107 $PACKER_VCC_NET -.sym 8109 o_led0$SB_IO_OUT -.sym 8113 w_smi_data_output[6] -.sym 8119 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 8122 w_smi_data_output[4] -.sym 8124 w_smi_data_output[7] -.sym 8133 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 8137 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 8142 rx_fifo.wr_addr[9] -.sym 8151 $PACKER_VCC_NET -.sym 8152 w_smi_data_input[7] -.sym 8161 smi_ctrl_ins.int_cnt_rx[4] -.sym 8165 w_rx_fifo_pulled_data[14] -.sym 8169 w_rx_fifo_pulled_data[12] -.sym 8170 w_rx_fifo_pulled_data[7] -.sym 8172 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 8176 smi_ctrl_ins.int_cnt_rx[3] -.sym 8177 w_rx_fifo_pulled_data[13] -.sym 8178 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8181 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8185 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 8189 w_rx_fifo_pulled_data[15] -.sym 8194 w_rx_fifo_pulled_data[13] -.sym 8200 w_rx_fifo_pulled_data[12] -.sym 8206 w_rx_fifo_pulled_data[7] -.sym 8211 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8212 smi_ctrl_ins.int_cnt_rx[3] -.sym 8213 smi_ctrl_ins.int_cnt_rx[4] -.sym 8214 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8226 w_rx_fifo_pulled_data[15] -.sym 8229 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 8230 smi_ctrl_ins.int_cnt_rx[4] -.sym 8231 smi_ctrl_ins.int_cnt_rx[3] -.sym 8232 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 8235 w_rx_fifo_pulled_data[14] -.sym 8239 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8240 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8241 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8246 rx_fifo.mem_i.0.2_WDATA -.sym 8247 w_rx_09_fifo_data[29] -.sym 8249 w_rx_09_fifo_data[30] -.sym 8250 rx_fifo.mem_i.0.3_WDATA_1 -.sym 8251 rx_fifo.mem_i.0.3_WDATA -.sym 8252 lvds_rx_09_inst.o_fifo_data[31] -.sym 8253 w_rx_09_fifo_data[27] -.sym 8264 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 8265 $PACKER_VCC_NET -.sym 8267 i_rst_b$SB_IO_IN -.sym 8274 o_led1$SB_IO_OUT -.sym 8278 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8287 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 8292 w_rx_09_fifo_data[25] -.sym 8294 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 8299 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8303 rx_fifo.mem_i.0.1_WDATA_1 -.sym 8308 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 8309 w_smi_data_output[1] -.sym 8315 w_smi_data_output[2] -.sym 8323 w_rx_24_fifo_data[23] -.sym 8332 o_led1$SB_IO_OUT -.sym 8337 w_rx_24_fifo_data[29] -.sym 8339 w_rx_24_fifo_data[18] -.sym 8347 w_rx_09_fifo_data[25] -.sym 8349 w_rx_24_fifo_data[25] -.sym 8350 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 8351 rx_fifo.wr_addr[9] -.sym 8352 w_rx_24_fifo_data[27] -.sym 8353 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8354 w_rx_24_fifo_data[21] -.sym 8356 w_rx_24_fifo_data[21] -.sym 8359 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8362 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8363 w_rx_24_fifo_data[18] -.sym 8370 w_rx_24_fifo_data[23] -.sym 8371 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8374 rx_fifo.wr_addr[9] -.sym 8381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8383 w_rx_24_fifo_data[29] -.sym 8386 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8388 w_rx_24_fifo_data[25] -.sym 8394 w_rx_24_fifo_data[27] -.sym 8395 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8398 w_rx_09_fifo_data[25] -.sym 8399 o_led1$SB_IO_OUT -.sym 8400 w_rx_24_fifo_data[25] +.sym 8104 w_smi_data_output[6] +.sym 8114 w_smi_data_direction +.sym 8115 $PACKER_VCC_NET +.sym 8119 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 8121 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 8122 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 8123 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 8125 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 8133 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 8134 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8139 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8141 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 8246 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 8247 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 8248 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 8250 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 8251 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 8252 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 8253 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 8255 tx_fifo.wr_addr[5] +.sym 8261 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 8265 w_rx_fifo_pulled_data[22] +.sym 8277 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 8289 $PACKER_VCC_NET +.sym 8290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 8292 smi_ctrl_ins.int_cnt_rx[3] +.sym 8297 w_smi_data_output[1] +.sym 8298 w_rx_fifo_pulled_data[28] +.sym 8299 w_smi_data_output[2] +.sym 8306 rx_fifo.mem_i.0.3_WDATA +.sym 8310 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 8324 w_rx_24_fifo_data[23] +.sym 8325 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8335 w_rx_24_fifo_data[21] +.sym 8336 w_rx_09_fifo_data[23] +.sym 8337 w_rx_09_fifo_data[27] +.sym 8338 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8343 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8344 w_rx_09_fifo_data[21] +.sym 8351 w_rx_24_fifo_data[27] +.sym 8352 w_rx_09_fifo_data[25] +.sym 8353 w_rx_24_fifo_data[25] +.sym 8356 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8357 w_rx_09_fifo_data[21] +.sym 8359 w_rx_24_fifo_data[21] +.sym 8363 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8364 w_rx_24_fifo_data[21] +.sym 8368 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8369 w_rx_24_fifo_data[23] +.sym 8370 w_rx_09_fifo_data[23] +.sym 8374 w_rx_24_fifo_data[25] +.sym 8375 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8377 w_rx_09_fifo_data[25] +.sym 8380 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8383 w_rx_24_fifo_data[25] +.sym 8386 w_rx_09_fifo_data[27] +.sym 8387 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8388 w_rx_24_fifo_data[27] +.sym 8393 w_rx_24_fifo_data[23] +.sym 8394 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8398 w_rx_24_fifo_data[27] +.sym 8399 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 8402 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 8403 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 8404 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 8405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 8406 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 8408 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 8410 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 8412 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 8421 w_rx_fifo_pulled_data[7] -.sym 8429 w_rx_09_fifo_data[28] +.sym 8405 rx_fifo.rd_addr[3] +.sym 8406 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 8407 rx_fifo.rd_addr_gray[1] +.sym 8408 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 8409 rx_fifo.rd_addr_gray[4] +.sym 8410 rx_fifo.rd_addr_gray[2] +.sym 8411 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 8416 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 8417 rx_fifo.mem_i.0.1_WDATA_1 +.sym 8425 w_rx_09_fifo_data[27] +.sym 8431 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] .sym 8435 i_rst_b$SB_IO_IN -.sym 8438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 8439 w_smi_data_output[2] -.sym 8447 w_rx_fifo_pulled_data[16] -.sym 8448 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 8449 smi_ctrl_ins.int_cnt_rx[4] -.sym 8451 smi_ctrl_ins.int_cnt_rx[3] -.sym 8454 w_rx_24_fifo_data[23] -.sym 8455 w_rx_24_fifo_data[20] -.sym 8457 w_rx_24_fifo_data[21] -.sym 8459 w_rx_fifo_pulled_data[18] -.sym 8464 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 8467 w_rx_fifo_pulled_data[19] -.sym 8469 w_rx_09_fifo_data[20] -.sym 8471 w_rx_fifo_pulled_data[17] -.sym 8472 w_rx_09_fifo_data[23] -.sym 8474 w_rx_09_fifo_data[21] -.sym 8475 o_led1$SB_IO_OUT -.sym 8479 o_led1$SB_IO_OUT -.sym 8480 w_rx_09_fifo_data[20] -.sym 8481 w_rx_24_fifo_data[20] -.sym 8488 w_rx_fifo_pulled_data[18] -.sym 8492 w_rx_fifo_pulled_data[16] -.sym 8498 w_rx_fifo_pulled_data[17] -.sym 8503 o_led1$SB_IO_OUT -.sym 8504 w_rx_24_fifo_data[23] -.sym 8506 w_rx_09_fifo_data[23] -.sym 8509 smi_ctrl_ins.int_cnt_rx[4] -.sym 8510 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 8511 smi_ctrl_ins.int_cnt_rx[3] -.sym 8512 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 8518 w_rx_fifo_pulled_data[19] -.sym 8521 w_rx_09_fifo_data[21] -.sym 8522 o_led1$SB_IO_OUT -.sym 8524 w_rx_24_fifo_data[21] -.sym 8525 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8526 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8529 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8531 w_smi_data_output[2] -.sym 8532 smi_ctrl_ins.w_fifo_pull_trigger -.sym 8535 rx_fifo.mem_i.0.3_WDATA_2 -.sym 8537 rx_fifo.wr_addr[8] -.sym 8538 rx_fifo.wr_addr[8] -.sym 8540 rx_fifo.mem_i.0.1_WDATA_3 -.sym 8543 smi_ctrl_ins.int_cnt_rx[4] -.sym 8549 smi_ctrl_ins.int_cnt_rx[3] -.sym 8552 rx_fifo.rd_addr[0] -.sym 8554 rx_fifo.rd_addr[1] -.sym 8555 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8559 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 8436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 8439 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 8440 rx_fifo.wr_addr[8] +.sym 8454 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8455 w_rx_24_fifo_data[28] +.sym 8456 w_rx_09_fifo_data[30] +.sym 8460 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8461 w_rx_24_fifo_data[29] +.sym 8464 w_rx_24_fifo_data[30] +.sym 8465 w_rx_24_fifo_data[26] +.sym 8467 w_rx_09_fifo_data[28] +.sym 8469 w_rx_24_fifo_data[19] +.sym 8472 w_rx_09_fifo_data[29] +.sym 8473 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8475 w_rx_09_fifo_data[31] +.sym 8476 w_rx_24_fifo_data[31] +.sym 8480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8481 w_rx_09_fifo_data[31] +.sym 8482 w_rx_24_fifo_data[31] +.sym 8485 w_rx_24_fifo_data[26] +.sym 8487 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8492 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8493 w_rx_24_fifo_data[28] +.sym 8497 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8498 w_rx_24_fifo_data[28] +.sym 8499 w_rx_09_fifo_data[28] +.sym 8504 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8506 w_rx_24_fifo_data[19] +.sym 8509 w_rx_09_fifo_data[29] +.sym 8511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8512 w_rx_24_fifo_data[29] +.sym 8516 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8517 w_rx_24_fifo_data[29] +.sym 8521 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8522 w_rx_24_fifo_data[30] +.sym 8523 w_rx_09_fifo_data[30] +.sym 8525 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8526 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 8527 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 8528 w_smi_data_output[4] +.sym 8529 w_smi_data_output[7] +.sym 8530 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 8531 w_smi_data_output[5] +.sym 8532 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 8533 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 8534 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 8535 smi_ctrl_ins.w_fifo_pull_trigger +.sym 8540 rx_fifo.wr_addr[7] +.sym 8542 rx_fifo.wr_addr[1] +.sym 8543 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 8545 smi_ctrl_ins.int_cnt_rx[4] +.sym 8547 smi_ctrl_ins.int_cnt_rx[3] +.sym 8548 rx_fifo.mem_i.0.3_WDATA_3 +.sym 8554 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 8556 rx_fifo.rd_addr_gray[6] .sym 8560 rx_fifo.rd_addr[7] -.sym 8561 o_led1$SB_IO_OUT -.sym 8562 rx_fifo.rd_addr[2] -.sym 8569 smi_ctrl_ins.int_cnt_rx[3] -.sym 8570 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 8571 i_rst_b$SB_IO_IN -.sym 8572 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 8573 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 8575 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 8577 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 8578 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 8580 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 8581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 8582 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 8583 smi_ctrl_ins.int_cnt_rx[3] -.sym 8585 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 8587 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 8590 smi_ctrl_ins.int_cnt_rx[4] -.sym 8592 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 8595 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8597 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 8598 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 8600 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 8602 smi_ctrl_ins.int_cnt_rx[3] -.sym 8603 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 8604 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 8605 smi_ctrl_ins.int_cnt_rx[4] -.sym 8609 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 8610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 8614 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 8615 smi_ctrl_ins.int_cnt_rx[4] -.sym 8616 smi_ctrl_ins.int_cnt_rx[3] -.sym 8617 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 8622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8623 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 8628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 8629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 8632 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 8633 smi_ctrl_ins.int_cnt_rx[3] -.sym 8634 smi_ctrl_ins.int_cnt_rx[4] -.sym 8635 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 8638 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 8639 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 8644 smi_ctrl_ins.int_cnt_rx[3] -.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 8646 smi_ctrl_ins.int_cnt_rx[4] -.sym 8647 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 8648 i_rst_b$SB_IO_IN +.sym 8562 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 8573 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8575 smi_ctrl_ins.int_cnt_rx[4] +.sym 8580 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 8583 smi_ctrl_ins.int_cnt_rx[4] +.sym 8584 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 8588 w_rx_fifo_pulled_data[7] +.sym 8591 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 8593 smi_ctrl_ins.int_cnt_rx[3] +.sym 8594 w_rx_fifo_pulled_data[4] +.sym 8596 w_rx_fifo_pulled_data[5] +.sym 8599 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 8600 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8608 smi_ctrl_ins.int_cnt_rx[3] +.sym 8609 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 8610 smi_ctrl_ins.int_cnt_rx[4] +.sym 8611 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 8623 w_rx_fifo_pulled_data[5] +.sym 8626 smi_ctrl_ins.int_cnt_rx[4] +.sym 8627 smi_ctrl_ins.int_cnt_rx[3] +.sym 8628 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 8629 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 8632 smi_ctrl_ins.int_cnt_rx[4] +.sym 8633 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8634 smi_ctrl_ins.int_cnt_rx[3] +.sym 8635 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8639 w_rx_fifo_pulled_data[7] +.sym 8645 w_rx_fifo_pulled_data[4] +.sym 8648 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8651 rx_fifo.mem_i.0.3_WDATA_3 -.sym 8652 rx_fifo.rd_addr[3] +.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8651 rx_fifo.rd_addr_gray[6] +.sym 8652 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] .sym 8653 rx_fifo.rd_addr[7] -.sym 8654 rx_fifo.rd_addr[2] -.sym 8655 rx_fifo.rd_addr[5] -.sym 8656 rx_fifo.rd_addr[6] -.sym 8657 rx_fifo.rd_addr[0] +.sym 8654 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 8655 rx_fifo.rd_addr[0] +.sym 8656 rx_fifo.rd_addr[2] +.sym 8657 rx_fifo.rd_addr_gray[3] .sym 8658 rx_fifo.rd_addr[1] -.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 8667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8671 tx_fifo.rd_addr_gray_wr[2] -.sym 8678 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 8680 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 8681 smi_ctrl_ins.int_cnt_rx[4] -.sym 8684 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 8685 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8686 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 8693 w_rx_fifo_pulled_data[24] -.sym 8697 w_rx_fifo_pulled_data[26] -.sym 8701 w_rx_fifo_pulled_data[4] -.sym 8702 w_rx_fifo_pulled_data[6] -.sym 8703 w_rx_fifo_pulled_data[5] -.sym 8713 w_rx_fifo_pulled_data[27] -.sym 8717 w_rx_fifo_pulled_data[25] -.sym 8726 w_rx_fifo_pulled_data[27] -.sym 8732 w_rx_fifo_pulled_data[25] -.sym 8739 w_rx_fifo_pulled_data[4] -.sym 8743 w_rx_fifo_pulled_data[26] -.sym 8750 w_rx_fifo_pulled_data[6] -.sym 8757 w_rx_fifo_pulled_data[24] -.sym 8770 w_rx_fifo_pulled_data[5] -.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8775 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 8776 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 8777 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8778 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 8779 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 8780 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8781 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8787 w_rx_fifo_pulled_data[4] -.sym 8790 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8791 $PACKER_VCC_NET -.sym 8795 rx_fifo.rd_addr[3] -.sym 8797 rx_fifo.rd_addr[7] -.sym 8799 rx_fifo.rd_addr[4] -.sym 8800 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 8662 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 8664 $PACKER_VCC_NET +.sym 8665 smi_ctrl_ins.int_cnt_rx[4] +.sym 8667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 8672 $PACKER_VCC_NET +.sym 8673 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 8675 rx_fifo.wr_addr[9] +.sym 8676 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 8677 rx_fifo.wr_addr[5] +.sym 8679 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 8682 smi_ctrl_ins.int_cnt_rx[3] +.sym 8683 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 8684 rx_fifo.rd_addr_gray_wr_r[6] +.sym 8685 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 8701 rx_fifo.wr_addr[6] +.sym 8703 rx_fifo.wr_addr[4] +.sym 8708 rx_fifo.wr_addr[0] +.sym 8710 rx_fifo.wr_addr[1] +.sym 8711 rx_fifo.wr_addr[3] +.sym 8712 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 8716 rx_fifo.wr_addr[7] +.sym 8723 rx_fifo.wr_addr[5] +.sym 8724 $nextpnr_ICESTORM_LC_7$O +.sym 8727 rx_fifo.wr_addr[0] +.sym 8730 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 8732 rx_fifo.wr_addr[1] +.sym 8734 rx_fifo.wr_addr[0] +.sym 8736 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 8739 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 8740 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 8742 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 8745 rx_fifo.wr_addr[3] +.sym 8746 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 8748 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 8751 rx_fifo.wr_addr[4] +.sym 8752 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 8754 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 8756 rx_fifo.wr_addr[5] +.sym 8758 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 8760 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 8763 rx_fifo.wr_addr[6] +.sym 8764 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 8766 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 8769 rx_fifo.wr_addr[7] +.sym 8770 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 8774 rx_fifo.wr_addr[0] +.sym 8775 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] +.sym 8776 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 8777 rx_fifo.wr_addr[3] +.sym 8778 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 8779 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 8780 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 8781 rx_fifo.wr_addr[5] +.sym 8790 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 8794 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8797 rx_fifo.wr_addr[6] +.sym 8799 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 8800 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] .sym 8801 rx_fifo.rd_addr[8] -.sym 8804 rx_fifo.rd_addr[6] -.sym 8806 w_rx_fifo_pulled_data[21] -.sym 8836 w_rx_fifo_pulled_data[10] -.sym 8863 w_rx_fifo_pulled_data[10] -.sym 8894 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8895 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8897 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 8898 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 8899 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 8900 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 8901 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 8902 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 8903 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 8904 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 8917 w_rx_fifo_pulled_data[5] -.sym 8921 rx_fifo.wr_addr[8] -.sym 8923 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 8924 rx_fifo.rd_addr[5] -.sym 8925 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 8926 rx_fifo.rd_addr[6] -.sym 8927 i_rst_b$SB_IO_IN -.sym 8929 rx_fifo.rd_addr[9] -.sym 8930 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 8931 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8932 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 8939 w_rx_fifo_pulled_data[8] -.sym 8943 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 8945 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 8948 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 8949 smi_ctrl_ins.int_cnt_rx[3] -.sym 8952 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 8953 smi_ctrl_ins.int_cnt_rx[4] -.sym 8955 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 8959 w_rx_fifo_pulled_data[11] -.sym 8963 w_rx_fifo_pulled_data[9] -.sym 8966 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 8978 w_rx_fifo_pulled_data[9] -.sym 8984 w_rx_fifo_pulled_data[11] -.sym 8996 w_rx_fifo_pulled_data[8] -.sym 9001 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 9002 smi_ctrl_ins.int_cnt_rx[3] -.sym 9003 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 9004 smi_ctrl_ins.int_cnt_rx[4] -.sym 9007 smi_ctrl_ins.int_cnt_rx[4] -.sym 9008 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 9009 smi_ctrl_ins.int_cnt_rx[3] -.sym 9010 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 9013 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 9014 smi_ctrl_ins.int_cnt_rx[4] -.sym 9015 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 9016 smi_ctrl_ins.int_cnt_rx[3] -.sym 9017 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 9018 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8804 rx_fifo.rd_addr[2] +.sym 8805 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 8806 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 8808 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8809 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 8810 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 8817 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 8818 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8819 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8820 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 8821 rx_fifo.wr_addr_gray[0] +.sym 8827 rx_fifo.wr_addr_gray[5] +.sym 8828 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8829 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8830 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 8834 rx_fifo.wr_addr[8] +.sym 8835 rx_fifo.wr_addr[9] +.sym 8844 rx_fifo.rd_addr_gray_wr_r[6] +.sym 8846 rx_fifo.wr_addr_gray_rd[5] +.sym 8847 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 8849 rx_fifo.wr_addr[8] +.sym 8851 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 8855 rx_fifo.wr_addr[9] +.sym 8857 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 8861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 8862 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 8863 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8869 rx_fifo.wr_addr_gray[0] +.sym 8872 rx_fifo.rd_addr_gray_wr_r[6] +.sym 8873 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8874 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 8881 rx_fifo.wr_addr_gray_rd[5] +.sym 8884 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8886 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8890 rx_fifo.wr_addr_gray[5] +.sym 8895 r_counter_$glb_clk +.sym 8898 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 8899 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 8900 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 8901 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 8902 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 8903 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 8904 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 8909 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 8912 rx_fifo.wr_addr[3] +.sym 8913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8916 rx_fifo.wr_addr[0] +.sym 8922 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 8923 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 8925 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 8926 i_rst_b$SB_IO_IN +.sym 8927 rx_fifo.wr_addr[8] +.sym 8929 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 8930 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 8931 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 8939 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8940 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 8942 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 8944 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 8945 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 8946 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 8948 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 8950 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 8951 rx_fifo.wr_addr[1] +.sym 8952 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 8955 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 8957 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 8963 rx_fifo.rd_addr_gray_wr_r[8] +.sym 8964 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 8965 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 8974 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 8977 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8978 rx_fifo.rd_addr_gray_wr_r[8] +.sym 8979 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 8980 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 8986 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 8989 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 8990 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 8991 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 8992 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 8998 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9003 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 9009 rx_fifo.wr_addr[1] +.sym 9013 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9015 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 9017 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9018 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9020 rx_fifo.rd_addr[4] -.sym 9021 rx_fifo.rd_addr[8] -.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 9023 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 9024 rx_fifo.rd_addr_gray[4] -.sym 9025 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 9026 rx_fifo.rd_addr_gray[5] -.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 9036 w_rx_fifo_pulled_data[30] -.sym 9037 smi_ctrl_ins.int_cnt_rx[3] -.sym 9039 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9040 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9041 smi_ctrl_ins.int_cnt_rx[4] -.sym 9044 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9046 rx_fifo.rd_addr[1] -.sym 9048 rx_fifo.rd_addr[7] -.sym 9051 rx_fifo.rd_addr[1] -.sym 9052 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 9054 rx_fifo.rd_addr[2] -.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 9062 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9078 w_rx_fifo_pulled_data[0] -.sym 9080 w_rx_fifo_pulled_data[1] -.sym 9082 w_rx_fifo_pulled_data[2] -.sym 9088 w_rx_fifo_pulled_data[3] -.sym 9095 w_rx_fifo_pulled_data[2] -.sym 9114 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9125 w_rx_fifo_pulled_data[3] -.sym 9133 w_rx_fifo_pulled_data[1] -.sym 9138 w_rx_fifo_pulled_data[0] +.sym 9020 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 9021 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] +.sym 9022 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 9023 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 9024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] +.sym 9025 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 9026 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 9027 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] +.sym 9032 rx_fifo.rd_addr[4] +.sym 9034 rx_fifo.wr_addr[1] +.sym 9036 $PACKER_VCC_NET +.sym 9039 $PACKER_VCC_NET +.sym 9045 rx_fifo.rd_addr[7] +.sym 9046 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 9047 rx_fifo.wr_addr[4] +.sym 9048 rx_fifo.rd_addr_gray[6] +.sym 9052 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9053 rx_fifo.wr_addr[6] +.sym 9054 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9062 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 9063 i_rst_b$SB_IO_IN +.sym 9064 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9065 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9066 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 9067 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 9068 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 9069 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9070 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 9072 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 9073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 9074 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 9075 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 9076 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 9077 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 9078 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 9081 rx_fifo.rd_addr_gray_wr_r[6] +.sym 9082 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 9083 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9086 w_rx_fifo_pulled_data[12] +.sym 9089 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 9091 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 9095 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 9096 i_rst_b$SB_IO_IN +.sym 9100 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 9101 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 9103 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 9106 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 9107 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 9108 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9109 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 9114 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 9115 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 9120 w_rx_fifo_pulled_data[12] +.sym 9124 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 9125 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9126 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9127 rx_fifo.rd_addr_gray_wr_r[6] +.sym 9130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 9131 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 9132 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 9133 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 9136 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 9138 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] .sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9143 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] -.sym 9144 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] -.sym 9147 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] -.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 9150 w_rx_fifo_empty -.sym 9162 rx_fifo.rd_addr[4] -.sym 9164 rx_fifo.rd_addr[8] -.sym 9168 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9170 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 9171 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9172 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9173 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9174 w_rx_fifo_empty -.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9184 rx_fifo.rd_addr[4] -.sym 9185 rx_fifo.rd_addr[8] -.sym 9186 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 9187 rx_fifo.rd_addr[7] -.sym 9188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9194 rx_fifo.rd_addr[5] -.sym 9195 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9196 rx_fifo.rd_addr[6] -.sym 9197 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 9200 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9202 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9203 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] -.sym 9206 rx_fifo.rd_addr[1] -.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9212 rx_fifo.rd_addr[9] -.sym 9219 rx_fifo.rd_addr[1] -.sym 9224 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9226 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9229 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 9230 rx_fifo.rd_addr[7] -.sym 9231 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 9232 rx_fifo.rd_addr[6] -.sym 9235 rx_fifo.rd_addr[8] -.sym 9236 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9237 rx_fifo.rd_addr[9] -.sym 9238 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9249 rx_fifo.rd_addr[5] -.sym 9250 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 9259 rx_fifo.rd_addr[5] -.sym 9260 rx_fifo.rd_addr[4] -.sym 9261 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] -.sym 9262 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9264 r_counter_$glb_clk +.sym 9143 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 9144 rx_fifo.wr_addr_gray_rd[4] +.sym 9147 rx_fifo.wr_addr_gray_rd[2] +.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.sym 9150 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 9155 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9157 w_rx_data[5] +.sym 9166 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 9167 rx_fifo.wr_addr[9] +.sym 9168 rx_fifo.rd_addr_gray_wr_r[6] +.sym 9170 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9171 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9173 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 9174 rx_fifo.wr_addr[5] +.sym 9188 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9190 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 9192 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9193 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9195 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9196 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 9200 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9207 rx_fifo.rd_addr[8] +.sym 9211 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9212 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 9217 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 9219 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9223 rx_fifo.rd_addr[8] +.sym 9230 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 9236 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9243 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9244 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9247 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9249 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 9250 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9255 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9260 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9263 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9264 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9266 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 9268 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 9269 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 9271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 9272 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9273 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 9280 rx_fifo.wr_addr[9] -.sym 9283 w_rx_fifo_empty -.sym 9288 $PACKER_VCC_NET -.sym 9290 rx_fifo.wr_addr[9] -.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 9294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 9295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 9298 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9301 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9307 i_rst_b$SB_IO_IN -.sym 9308 rx_fifo.wr_addr_gray_rd[2] -.sym 9311 rx_fifo.wr_addr_gray_rd[5] -.sym 9313 rx_fifo.wr_addr_gray_rd[3] -.sym 9315 rx_fifo.wr_addr_gray_rd[7] -.sym 9320 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9321 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9330 rx_fifo.wr_addr_gray_rd[6] -.sym 9331 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9334 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 9336 rx_fifo.wr_addr_gray_rd[4] -.sym 9338 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9342 i_rst_b$SB_IO_IN -.sym 9346 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9347 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9348 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9349 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 9353 rx_fifo.wr_addr_gray_rd[6] -.sym 9358 rx_fifo.wr_addr_gray_rd[7] -.sym 9364 rx_fifo.wr_addr_gray_rd[5] -.sym 9373 rx_fifo.wr_addr_gray_rd[3] -.sym 9377 rx_fifo.wr_addr_gray_rd[2] -.sym 9383 rx_fifo.wr_addr_gray_rd[4] -.sym 9387 r_counter_$glb_clk -.sym 9389 rx_fifo.rd_addr_gray[6] -.sym 9390 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 9391 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9392 rx_fifo.rd_addr_gray[2] -.sym 9393 rx_fifo.rd_addr_gray[3] -.sym 9394 rx_fifo.rd_addr_gray[1] -.sym 9395 rx_fifo.rd_addr_gray[7] -.sym 9409 rx_fifo.wr_addr_gray_rd[3] -.sym 9413 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 9415 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9418 i_rst_b$SB_IO_IN -.sym 9422 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 9423 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9424 rx_fifo.wr_addr[8] -.sym 9435 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 9437 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9438 i_rst_b$SB_IO_IN -.sym 9439 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9443 rx_fifo.wr_addr_gray[7] -.sym 9445 rx_fifo.wr_addr_gray[2] -.sym 9446 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 9450 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 9451 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] -.sym 9452 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 9454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9456 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9458 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9459 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 9460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9461 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9465 rx_fifo.wr_addr_gray[7] -.sym 9472 rx_fifo.wr_addr_gray[2] -.sym 9475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9477 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9481 i_rst_b$SB_IO_IN -.sym 9483 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9487 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 9488 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] -.sym 9489 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 9490 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9495 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 9499 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9501 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9502 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 9506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 9507 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9510 r_counter_$glb_clk -.sym 9513 rx_fifo.rd_addr_gray_wr[6] -.sym 9514 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 9515 rx_fifo.rd_addr_gray_wr[0] -.sym 9516 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 9517 rx_fifo.rd_addr_gray_wr[3] -.sym 9518 rx_fifo.rd_addr_gray_wr[5] -.sym 9525 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 9527 $PACKER_VCC_NET -.sym 9534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 9535 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 9536 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 9537 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 9538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 9539 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9542 rx_fifo.rd_addr_gray[1] -.sym 9543 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 9544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9545 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 9546 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9564 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9566 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9568 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9569 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9570 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9577 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9595 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9605 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9610 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9616 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9623 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9629 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9630 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9266 rx_fifo.rd_addr_gray[0] +.sym 9267 rx_fifo.rd_addr[9] +.sym 9268 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 9269 rx_fifo.rd_addr_gray[7] +.sym 9270 rx_fifo.rd_addr_gray[8] +.sym 9273 rx_fifo.rd_addr[8] +.sym 9280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 9282 rx_fifo.rd_addr_gray_wr[8] +.sym 9285 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 9291 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 9292 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 9297 rx_fifo.rd_addr[8] +.sym 9300 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 9307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 9309 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9312 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 9317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9318 rx_fifo.rd_addr_gray_wr[7] +.sym 9320 rx_fifo.rd_addr_gray[6] +.sym 9321 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9322 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9323 rx_fifo.rd_addr_gray[0] +.sym 9325 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9327 rx_fifo.rd_addr_gray_wr[6] +.sym 9333 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 9334 rx_fifo.rd_addr_gray[7] +.sym 9338 rx_fifo.rd_addr_gray_wr[8] +.sym 9340 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9341 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 9342 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9343 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9346 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9347 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 9348 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 9349 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9354 rx_fifo.rd_addr_gray_wr[8] +.sym 9361 rx_fifo.rd_addr_gray[7] +.sym 9364 rx_fifo.rd_addr_gray[6] +.sym 9371 rx_fifo.rd_addr_gray[0] +.sym 9376 rx_fifo.rd_addr_gray_wr[6] +.sym 9383 rx_fifo.rd_addr_gray_wr[7] +.sym 9387 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 9389 rx_fifo.wr_addr_gray_rd[6] +.sym 9390 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 9391 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9392 rx_fifo.wr_addr_gray_rd[9] +.sym 9393 rx_fifo.wr_addr_gray_rd[1] +.sym 9394 rx_fifo.wr_addr_gray_rd[3] +.sym 9395 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 9396 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 9413 i_rst_b$SB_IO_IN +.sym 9416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 9421 rx_fifo.wr_addr[9] +.sym 9435 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9436 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9440 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9441 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9445 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9448 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 9456 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9457 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9459 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9461 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9472 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9475 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9477 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 9482 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9484 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9487 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9494 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9495 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9505 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9509 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9510 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 9511 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 9512 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 9513 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 9517 rx_fifo.wr_addr_gray_rd[8] +.sym 9518 rx_fifo.wr_addr_gray_rd[7] +.sym 9573 w_rx_09_fifo_data[0] +.sym 9581 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 9588 w_rx_09_fifo_data[0] +.sym 9589 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 9632 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 9633 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9634 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9636 rx_fifo.rd_addr_gray_wr[4] -.sym 9637 rx_fifo.rd_addr_gray_wr[2] -.sym 9638 rx_fifo.rd_addr_gray_wr[1] -.sym 9639 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 9641 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 9642 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 9660 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 9664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9678 rx_fifo.wr_addr_gray[8] -.sym 9680 rx_fifo.wr_addr_gray[3] -.sym 9682 rx_fifo.wr_addr_gray[6] -.sym 9685 rx_fifo.wr_addr_gray[4] -.sym 9688 rx_fifo.wr_addr_gray[5] -.sym 9702 rx_fifo.wr_addr_gray_rd[8] -.sym 9717 rx_fifo.wr_addr_gray_rd[8] -.sym 9723 rx_fifo.wr_addr_gray[8] -.sym 9733 rx_fifo.wr_addr_gray[4] -.sym 9742 rx_fifo.wr_addr_gray[6] -.sym 9745 rx_fifo.wr_addr_gray[3] -.sym 9751 rx_fifo.wr_addr_gray[5] -.sym 9756 r_counter_$glb_clk -.sym 9763 spi_if_ins.r_tx_byte[2] -.sym 9782 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 9810 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9812 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9824 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9858 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9878 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9879 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9884 rx_fifo.wr_addr_gray_rd[1] -.sym 9887 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 9889 o_shdn_rx_lna$SB_IO_OUT -.sym 9892 o_shdn_rx_lna$SB_IO_OUT +.sym 9634 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 9635 rx_fifo.rd_addr_gray_wr[4] +.sym 9636 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 9642 rx_fifo.rd_addr_gray_wr[1] +.sym 9649 $PACKER_VCC_NET +.sym 9650 o_shdn_rx_lna$SB_IO_OUT +.sym 9667 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 9773 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E .sym 9905 i_rst_b$SB_IO_IN -.sym 9914 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9924 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 9931 w_rx_fifo_full -.sym 9941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 9942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 9945 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 9979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 9980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 9981 w_rx_fifo_full -.sym 9985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 9987 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 10001 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 10002 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10003 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10004 rx_fifo.rd_addr_gray_wr[7] -.sym 10006 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 10018 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 10069 rx_fifo.rd_addr_gray_wr[7] -.sym 10091 rx_fifo.rd_addr_gray_wr[7] -.sym 10125 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 10010 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10155 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10162 o_shdn_rx_lna$SB_IO_OUT .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10192 o_shdn_rx_lna$SB_IO_OUT +.sym 10196 o_shdn_rx_lna$SB_IO_OUT .sym 10197 i_rst_b$SB_IO_IN .sym 10201 w_smi_data_output[2] -.sym 10203 o_led0$SB_IO_OUT +.sym 10203 w_smi_data_direction .sym 10204 w_smi_data_output[1] -.sym 10206 o_led0$SB_IO_OUT +.sym 10206 w_smi_data_direction .sym 10207 $PACKER_VCC_NET -.sym 10213 o_led0$SB_IO_OUT -.sym 10221 o_led0$SB_IO_OUT -.sym 10222 w_smi_data_output[1] -.sym 10223 $PACKER_VCC_NET -.sym 10225 w_smi_data_output[2] -.sym 10228 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 10231 w_smi_data_output[5] -.sym 10261 o_led0$SB_IO_OUT -.sym 10268 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 10270 i_rst_b$SB_IO_IN -.sym 10271 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10274 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 10276 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 10283 smi_ctrl_ins.int_cnt_rx[3] -.sym 10284 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 10290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10296 smi_ctrl_ins.int_cnt_rx[4] -.sym 10307 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 10308 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 10309 smi_ctrl_ins.int_cnt_rx[4] -.sym 10310 smi_ctrl_ins.int_cnt_rx[3] -.sym 10325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 10327 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 10337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10340 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10347 i_rst_b$SB_IO_IN +.sym 10210 w_smi_data_direction +.sym 10211 w_smi_data_output[1] +.sym 10212 $PACKER_VCC_NET +.sym 10218 w_smi_data_direction +.sym 10221 w_smi_data_output[2] +.sym 10227 tx_fifo.wr_addr_gray_rd[6] +.sym 10228 tx_fifo.wr_addr_gray_rd[2] +.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 10232 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10233 tx_fifo.wr_addr_gray_rd[5] +.sym 10236 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10245 w_rx_data[0] +.sym 10248 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 10249 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 10250 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 10258 w_smi_data_direction +.sym 10259 $PACKER_VCC_NET +.sym 10260 w_smi_data_input[7] +.sym 10268 w_rx_fifo_pulled_data[22] +.sym 10269 w_rx_fifo_pulled_data[20] +.sym 10275 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 10284 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10289 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 10290 w_rx_fifo_pulled_data[23] +.sym 10292 w_rx_fifo_pulled_data[21] +.sym 10297 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 10309 w_rx_fifo_pulled_data[20] +.sym 10319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 10320 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10321 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 10322 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 10325 w_rx_fifo_pulled_data[22] +.sym 10334 w_rx_fifo_pulled_data[23] +.sym 10345 w_rx_fifo_pulled_data[21] +.sym 10347 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 10348 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 10352 w_smi_data_input[7] -.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 10355 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 10356 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10358 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 10359 tx_fifo.rd_addr[0] -.sym 10360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 10361 tx_fifo.rd_addr[1] -.sym 10364 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10365 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 10376 w_smi_data_output[4] -.sym 10380 $PACKER_VCC_NET -.sym 10381 smi_ctrl_ins.soe_and_reset -.sym 10386 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10403 smi_ctrl_ins.int_cnt_rx[3] -.sym 10405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10408 w_smi_data_input[7] -.sym 10412 w_smi_data_input[7] -.sym 10414 w_smi_data_output[0] -.sym 10416 w_rx_fifo_pulled_data[23] -.sym 10431 w_rx_09_fifo_data[25] -.sym 10435 w_rx_24_fifo_data[31] -.sym 10437 w_rx_24_fifo_data[29] -.sym 10439 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10440 w_rx_09_fifo_data[29] -.sym 10443 o_led1$SB_IO_OUT -.sym 10444 w_rx_24_fifo_data[27] -.sym 10451 w_rx_09_fifo_data[28] -.sym 10453 lvds_rx_09_inst.o_fifo_data[31] -.sym 10454 w_rx_09_fifo_data[27] -.sym 10465 w_rx_09_fifo_data[27] -.sym 10466 w_rx_24_fifo_data[27] -.sym 10467 o_led1$SB_IO_OUT -.sym 10470 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10472 w_rx_09_fifo_data[27] -.sym 10482 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10483 w_rx_09_fifo_data[28] -.sym 10488 w_rx_24_fifo_data[29] -.sym 10489 o_led1$SB_IO_OUT -.sym 10490 w_rx_09_fifo_data[29] -.sym 10494 o_led1$SB_IO_OUT -.sym 10495 lvds_rx_09_inst.o_fifo_data[31] -.sym 10497 w_rx_24_fifo_data[31] -.sym 10502 w_rx_09_fifo_data[29] -.sym 10503 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10506 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10507 w_rx_09_fifo_data[25] -.sym 10510 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 10511 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10512 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 10513 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 10514 tx_fifo.rd_addr_gray[3] -.sym 10515 tx_fifo.rd_addr_gray[2] -.sym 10516 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 10518 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 10519 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 10520 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10524 rx_fifo.rd_addr_gray[5] -.sym 10529 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 10530 tx_fifo.rd_addr[1] -.sym 10531 o_led1$SB_IO_OUT -.sym 10535 o_led1$SB_IO_OUT -.sym 10539 rx_fifo.rd_addr[3] -.sym 10540 w_rx_09_fifo_data[30] -.sym 10542 rx_fifo.mem_i.0.3_WDATA_1 -.sym 10543 $PACKER_VCC_NET -.sym 10544 rx_fifo.mem_i.0.3_WDATA -.sym 10545 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 10548 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10555 w_rx_fifo_pulled_data[22] -.sym 10558 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10560 smi_ctrl_ins.int_cnt_rx[4] -.sym 10561 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 10563 w_rx_fifo_pulled_data[20] -.sym 10564 smi_ctrl_ins.int_cnt_rx[3] -.sym 10565 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 10571 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10581 w_rx_fifo_pulled_data[23] -.sym 10587 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 10588 smi_ctrl_ins.int_cnt_rx[3] -.sym 10589 smi_ctrl_ins.int_cnt_rx[4] -.sym 10590 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 10594 w_rx_fifo_pulled_data[23] -.sym 10605 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10606 smi_ctrl_ins.int_cnt_rx[4] -.sym 10607 smi_ctrl_ins.int_cnt_rx[3] -.sym 10608 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10617 w_rx_fifo_pulled_data[22] -.sym 10630 w_rx_fifo_pulled_data[20] -.sym 10633 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 10634 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10354 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10355 tx_fifo.wr_addr_gray_rd[4] +.sym 10356 tx_fifo.wr_addr_gray_rd[3] +.sym 10357 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10358 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 10359 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 10361 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 10363 w_rx_fifo_pulled_data[20] +.sym 10365 rx_fifo.rd_addr_gray[1] +.sym 10369 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 10371 rx_fifo.wr_addr[8] +.sym 10383 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 10384 w_rx_fifo_pulled_data[23] +.sym 10386 w_rx_fifo_pulled_data[21] +.sym 10389 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10391 w_rx_fifo_pulled_data[29] +.sym 10392 w_rx_fifo_pulled_data[31] +.sym 10394 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 10396 rx_fifo.rd_addr[3] +.sym 10402 w_rx_fifo_pulled_data[30] +.sym 10403 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 10404 w_smi_data_output[0] +.sym 10407 smi_ctrl_ins.int_cnt_rx[4] +.sym 10408 tx_fifo.wr_addr_gray_rd[2] +.sym 10410 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10414 rx_fifo.rd_addr[3] +.sym 10419 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 10423 w_smi_data_direction +.sym 10425 w_smi_data_output[7] +.sym 10435 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 10437 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 10439 smi_ctrl_ins.int_cnt_rx[3] +.sym 10440 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10444 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 10446 w_rx_fifo_pulled_data[28] +.sym 10447 w_rx_fifo_pulled_data[31] +.sym 10448 w_rx_fifo_pulled_data[29] +.sym 10449 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 10456 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10458 w_rx_fifo_pulled_data[30] +.sym 10461 smi_ctrl_ins.int_cnt_rx[4] +.sym 10464 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10465 smi_ctrl_ins.int_cnt_rx[3] +.sym 10466 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10467 smi_ctrl_ins.int_cnt_rx[4] +.sym 10473 w_rx_fifo_pulled_data[28] +.sym 10476 w_rx_fifo_pulled_data[30] +.sym 10491 w_rx_fifo_pulled_data[29] +.sym 10494 smi_ctrl_ins.int_cnt_rx[3] +.sym 10495 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 10496 smi_ctrl_ins.int_cnt_rx[4] +.sym 10497 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 10502 w_rx_fifo_pulled_data[31] +.sym 10506 smi_ctrl_ins.int_cnt_rx[4] +.sym 10507 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 10508 smi_ctrl_ins.int_cnt_rx[3] +.sym 10509 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 10510 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 10511 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10515 tx_fifo.wr_addr_gray_rd[9] +.sym 10516 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 10518 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 10519 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 10520 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 10523 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 10529 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 10530 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10536 rx_fifo.rd_addr[7] +.sym 10537 rx_fifo.rd_addr_gray[4] +.sym 10539 rx_fifo.rd_addr_gray[2] +.sym 10544 w_smi_data_output[7] +.sym 10554 smi_ctrl_ins.int_cnt_rx[3] +.sym 10560 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 10565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10566 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 10568 smi_ctrl_ins.int_cnt_rx[4] +.sym 10569 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 10571 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 10574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 10576 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 10579 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10581 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 10582 i_rst_b$SB_IO_IN +.sym 10589 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 10594 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10596 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 10599 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 10605 i_rst_b$SB_IO_IN +.sym 10606 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 10611 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 10617 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 10623 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 10624 smi_ctrl_ins.int_cnt_rx[4] +.sym 10625 smi_ctrl_ins.int_cnt_rx[3] +.sym 10626 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 10633 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10634 r_counter_$glb_clk .sym 10635 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10636 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 10637 tx_fifo.rd_addr_gray_wr[3] -.sym 10638 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] -.sym 10639 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] -.sym 10641 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10643 tx_fifo.rd_addr_gray_wr[2] -.sym 10645 w_rx_fifo_pulled_data[20] -.sym 10653 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 10654 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10659 o_led1$SB_IO_OUT -.sym 10660 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 10661 rx_fifo.rd_addr[0] -.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 10636 smi_ctrl_ins.r_fifo_pull_1 +.sym 10637 smi_ctrl_ins.r_fifo_pull +.sym 10638 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] +.sym 10639 smi_ctrl_ins.r_fifo_push +.sym 10640 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 10641 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 10642 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 10643 smi_ctrl_ins.r_fifo_push_1 +.sym 10648 smi_ctrl_ins.int_cnt_rx[3] +.sym 10649 rx_fifo.wr_addr[9] +.sym 10650 w_rx_fifo_pulled_data[28] +.sym 10653 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 10655 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 10658 rx_fifo.wr_addr[5] +.sym 10659 $PACKER_VCC_NET +.sym 10660 rx_fifo.wr_addr[0] +.sym 10661 rx_fifo.rd_addr_gray[3] +.sym 10662 rx_fifo.rd_addr[9] .sym 10663 rx_fifo.rd_addr[1] -.sym 10665 w_tx_fifo_pull -.sym 10666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 10667 rx_fifo.rd_addr[3] +.sym 10664 rx_fifo.rd_addr[6] +.sym 10665 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10666 rx_fifo.wr_addr[3] +.sym 10667 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] .sym 10669 rx_fifo.rd_addr[7] -.sym 10670 rx_fifo.rd_addr[8] -.sym 10671 rx_fifo.rd_addr[2] -.sym 10677 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 10670 w_rx_fifo_empty +.sym 10671 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 10677 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 10678 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] .sym 10679 i_rst_b$SB_IO_IN -.sym 10689 w_rx_24_fifo_data[30] -.sym 10690 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10693 o_led1$SB_IO_OUT -.sym 10694 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 10696 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 10698 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10700 w_rx_09_fifo_data[30] -.sym 10702 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 10703 smi_ctrl_ins.int_cnt_rx[4] -.sym 10704 smi_ctrl_ins.int_cnt_rx[3] -.sym 10716 smi_ctrl_ins.int_cnt_rx[4] -.sym 10717 smi_ctrl_ins.int_cnt_rx[3] -.sym 10718 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 10719 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 10722 smi_ctrl_ins.int_cnt_rx[3] -.sym 10723 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10725 smi_ctrl_ins.int_cnt_rx[4] -.sym 10729 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 10735 smi_ctrl_ins.int_cnt_rx[4] -.sym 10736 smi_ctrl_ins.int_cnt_rx[3] -.sym 10752 w_rx_24_fifo_data[30] -.sym 10754 w_rx_09_fifo_data[30] -.sym 10755 o_led1$SB_IO_OUT +.sym 10680 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 10682 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 10686 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 10687 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 10688 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10689 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 10690 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 10691 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 10692 smi_ctrl_ins.int_cnt_rx[4] +.sym 10695 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] +.sym 10696 smi_ctrl_ins.int_cnt_rx[3] +.sym 10697 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 10699 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10700 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 10702 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 10704 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 10706 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 10707 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 10717 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10719 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 10722 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10723 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 10724 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 10725 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 10729 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 10734 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 10735 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 10736 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] +.sym 10737 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 10740 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10741 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 10742 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 10743 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 10746 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 10747 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 10748 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 10749 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 10754 smi_ctrl_ins.int_cnt_rx[3] +.sym 10755 smi_ctrl_ins.int_cnt_rx[4] .sym 10756 i_rst_b$SB_IO_IN .sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 10760 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 10761 w_tx_fifo_empty -.sym 10762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 10763 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] -.sym 10764 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10765 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 10766 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 10773 o_led1$SB_IO_OUT -.sym 10775 rx_fifo.mem_i.0.1_WDATA_1 -.sym 10776 w_rx_fifo_pulled_data[21] -.sym 10777 w_rx_24_fifo_data[30] -.sym 10778 rx_fifo.rd_addr[4] -.sym 10783 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 10788 smi_ctrl_ins.w_fifo_pull_trigger -.sym 10790 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10791 rx_fifo.mem_i.0.3_WDATA_3 -.sym 10793 smi_ctrl_ins.int_cnt_rx[3] -.sym 10794 rx_fifo.mem_i.0.3_WDATA_2 -.sym 10801 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 10802 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10803 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10805 o_led1$SB_IO_OUT -.sym 10811 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 10812 w_rx_09_fifo_data[28] -.sym 10813 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 10814 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10815 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10816 w_rx_24_fifo_data[28] -.sym 10830 rx_fifo.rd_addr[0] -.sym 10833 w_rx_24_fifo_data[28] -.sym 10834 o_led1$SB_IO_OUT -.sym 10836 w_rx_09_fifo_data[28] -.sym 10839 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10847 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10852 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10857 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 10863 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10870 rx_fifo.rd_addr[0] -.sym 10877 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 10879 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 10759 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 10760 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] +.sym 10761 w_tx_fifo_full +.sym 10762 w_rx_fifo_empty +.sym 10763 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] +.sym 10764 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.sym 10765 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10766 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 10771 w_smi_data_output[4] +.sym 10773 smi_ctrl_ins.w_fifo_push_trigger +.sym 10774 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 10777 rx_fifo.mem_i.0.3_WDATA +.sym 10779 w_smi_data_output[5] +.sym 10783 rx_fifo.rd_addr[3] +.sym 10785 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10786 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 10788 rx_fifo.wr_addr[0] +.sym 10789 rx_fifo.rd_addr[1] +.sym 10790 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10793 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 10794 rx_fifo.wr_addr[3] +.sym 10804 rx_fifo.rd_addr[0] +.sym 10805 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 10806 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 10812 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 10817 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 10818 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10822 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10823 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10825 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10826 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10829 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 10830 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10836 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 10839 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10841 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10848 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10851 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 10852 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 10853 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 10854 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 10859 rx_fifo.rd_addr[0] +.sym 10865 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10871 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 10878 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10879 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 10880 r_counter_$glb_clk .sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10884 w_tx_fifo_pull -.sym 10885 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 10888 i_rst_b_SB_LUT4_I3_O -.sym 10893 rx_fifo.rd_addr_gray[7] -.sym 10895 rx_fifo.wr_addr[8] -.sym 10896 rx_fifo.rd_addr[6] -.sym 10900 w_rx_09_fifo_data[28] -.sym 10904 rx_fifo.rd_addr[5] -.sym 10906 w_rx_fifo_pulled_data[31] +.sym 10883 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10884 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10885 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 10886 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 10887 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10888 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10889 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10895 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 10900 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 10901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 10906 rx_fifo.rd_addr[6] .sym 10907 rx_fifo.rd_addr[7] -.sym 10908 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 10909 rx_fifo.rd_addr[2] -.sym 10910 w_rx_fifo_pulled_data[29] -.sym 10911 rx_fifo.rd_addr[5] -.sym 10913 rx_fifo.rd_addr[6] -.sym 10915 rx_fifo.rd_addr[0] -.sym 10916 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10908 rx_fifo.rd_addr[5] +.sym 10909 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10911 rx_fifo.rd_addr[3] +.sym 10912 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.sym 10913 rx_fifo.rd_addr[2] +.sym 10915 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 10916 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] .sym 10917 rx_fifo.rd_addr[1] -.sym 10924 rx_fifo.rd_addr[3] -.sym 10925 rx_fifo.rd_addr[7] -.sym 10929 rx_fifo.rd_addr[0] -.sym 10934 rx_fifo.rd_addr[2] -.sym 10935 rx_fifo.rd_addr[5] -.sym 10936 rx_fifo.rd_addr[6] -.sym 10938 rx_fifo.rd_addr[1] -.sym 10947 rx_fifo.rd_addr[4] -.sym 10955 $nextpnr_ICESTORM_LC_5$O -.sym 10958 rx_fifo.rd_addr[0] -.sym 10961 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 10963 rx_fifo.rd_addr[1] -.sym 10965 rx_fifo.rd_addr[0] -.sym 10967 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 10970 rx_fifo.rd_addr[2] -.sym 10971 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 10973 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 10976 rx_fifo.rd_addr[3] -.sym 10977 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 10979 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 10981 rx_fifo.rd_addr[4] -.sym 10983 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 10985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 10988 rx_fifo.rd_addr[5] -.sym 10989 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 10991 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 10994 rx_fifo.rd_addr[6] -.sym 10995 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 10997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 10999 rx_fifo.rd_addr[7] -.sym 11001 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11005 smi_ctrl_ins.r_fifo_pull -.sym 11006 smi_ctrl_ins.r_fifo_pull_1 -.sym 11007 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11008 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 11012 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 11018 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11021 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 11022 rx_fifo.rd_addr[7] -.sym 11023 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 11026 rx_fifo.rd_addr[0] -.sym 11027 o_led1$SB_IO_OUT -.sym 11028 rx_fifo.rd_addr[1] -.sym 11030 $PACKER_VCC_NET -.sym 11032 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11035 $PACKER_VCC_NET -.sym 11036 rx_fifo.rd_addr[3] -.sym 11038 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11039 w_tx_data_smi[2] -.sym 11041 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 11047 rx_fifo.rd_addr[8] -.sym 11050 w_rx_fifo_pulled_data[21] -.sym 11053 w_rx_fifo_pulled_data[30] -.sym 11055 w_rx_fifo_pulled_data[28] -.sym 11058 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11059 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 11063 rx_fifo.rd_addr[9] -.sym 11066 w_rx_fifo_pulled_data[31] -.sym 11070 w_rx_fifo_pulled_data[29] -.sym 11078 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 11080 rx_fifo.rd_addr[8] -.sym 11082 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 11085 rx_fifo.rd_addr[9] -.sym 11088 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 11093 w_rx_fifo_pulled_data[31] -.sym 11097 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11098 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 11106 w_rx_fifo_pulled_data[30] -.sym 11112 w_rx_fifo_pulled_data[21] -.sym 11116 w_rx_fifo_pulled_data[29] -.sym 11124 w_rx_fifo_pulled_data[28] -.sym 11125 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 11126 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 11127 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11128 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] -.sym 11130 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] -.sym 11131 w_tx_data_smi[2] -.sym 11133 w_tx_data_smi[1] -.sym 11134 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] -.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] -.sym 11137 w_rx_fifo_pulled_data[28] -.sym 11140 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11144 smi_ctrl_ins.int_cnt_rx[4] -.sym 11145 rx_fifo.wr_addr[4] -.sym 11148 w_rx_fifo_empty -.sym 11149 o_led1$SB_IO_OUT -.sym 11152 rx_fifo.rd_addr_gray[4] -.sym 11155 rx_fifo.rd_addr[3] -.sym 11156 rx_fifo.rd_addr[1] +.sym 10923 rx_fifo.wr_addr[0] +.sym 10924 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] +.sym 10925 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 10928 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 10930 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10932 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] +.sym 10936 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 10939 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 10942 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10943 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10944 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 10945 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10946 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10951 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 10952 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10953 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10958 rx_fifo.wr_addr[0] +.sym 10962 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10963 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10964 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 10969 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10970 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10974 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10980 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] +.sym 10981 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] +.sym 10982 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 10983 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 10987 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 10988 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 10993 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10994 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10995 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11001 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11002 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11003 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11004 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 11005 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11006 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11007 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.sym 11008 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 11009 rx_fifo.rd_addr[4] +.sym 11010 rx_fifo.rd_addr_gray[5] +.sym 11011 rx_fifo.rd_addr[6] +.sym 11012 rx_fifo.rd_addr[5] +.sym 11021 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11029 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 11030 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11032 rx_fifo.wr_addr[3] +.sym 11036 rx_fifo.wr_addr[4] +.sym 11037 rx_fifo.rd_addr_gray[4] +.sym 11039 rx_fifo.rd_addr_gray[2] +.sym 11040 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 11046 rx_fifo.wr_addr[7] +.sym 11049 rx_fifo.wr_addr[3] +.sym 11056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 11059 rx_fifo.wr_addr[1] +.sym 11061 rx_fifo.wr_addr[5] +.sym 11069 rx_fifo.wr_addr[8] +.sym 11075 rx_fifo.wr_addr[6] +.sym 11077 rx_fifo.wr_addr[4] +.sym 11078 $nextpnr_ICESTORM_LC_5$O +.sym 11081 rx_fifo.wr_addr[1] +.sym 11084 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 11087 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 11088 rx_fifo.wr_addr[1] +.sym 11090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11092 rx_fifo.wr_addr[3] +.sym 11094 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 11096 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 11098 rx_fifo.wr_addr[4] +.sym 11100 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11102 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 11105 rx_fifo.wr_addr[5] +.sym 11106 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 11108 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 11110 rx_fifo.wr_addr[6] +.sym 11112 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 11114 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11117 rx_fifo.wr_addr[7] +.sym 11118 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 11120 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 11123 rx_fifo.wr_addr[8] +.sym 11124 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11128 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 11129 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 11130 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.sym 11131 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] +.sym 11132 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] +.sym 11133 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 11134 rx_fifo.rd_addr_gray_wr[5] +.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] +.sym 11147 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11149 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11153 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.sym 11154 rx_fifo.rd_addr[9] +.sym 11155 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 11156 rx_fifo.rd_addr[4] .sym 11157 rx_fifo.rd_addr[7] -.sym 11159 rx_fifo.rd_addr[2] -.sym 11160 rx_fifo.rd_addr[4] -.sym 11161 rx_fifo.rd_addr[0] -.sym 11162 rx_fifo.rd_addr[8] -.sym 11169 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11170 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 11171 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11172 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11179 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11182 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 11187 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 11188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 11193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11194 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 11196 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11200 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11209 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11216 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 11217 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 11221 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11223 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 11229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 11232 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 11240 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11244 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 11245 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 11246 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 11247 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11160 rx_fifo.rd_addr[6] +.sym 11161 rx_fifo.rd_addr_gray[3] +.sym 11163 rx_fifo.rd_addr[1] +.sym 11164 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 11170 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 11171 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 11173 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 11176 w_rx_data[5] +.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11178 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11180 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 11182 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 11183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 11187 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 11188 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 11189 w_rx_data[0] +.sym 11190 rx_fifo.rd_addr_gray_wr_r[6] +.sym 11191 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 11192 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] +.sym 11193 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11197 rx_fifo.wr_addr[9] +.sym 11199 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 11203 rx_fifo.wr_addr[9] +.sym 11205 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 11208 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] +.sym 11209 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 11210 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 11211 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 11215 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11220 w_rx_data[5] +.sym 11226 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 11227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 11228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 11229 rx_fifo.rd_addr_gray_wr_r[6] +.sym 11235 w_rx_data[0] +.sym 11238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 11239 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11240 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 11244 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 11246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 11247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 11248 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E .sym 11249 r_counter_$glb_clk .sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11251 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 11252 spi_if_ins.state_if[1] -.sym 11253 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 11254 spi_if_ins.state_if[0] -.sym 11255 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11256 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 11258 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 11264 rx_fifo.rd_addr[6] -.sym 11265 o_led1$SB_IO_OUT -.sym 11267 rx_fifo.rd_addr[8] -.sym 11268 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 11274 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 11275 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 11276 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 11279 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 11281 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 11282 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 11283 w_rx_fifo_full -.sym 11285 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11286 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 11292 rx_fifo.rd_addr[7] -.sym 11293 rx_fifo.rd_addr[8] -.sym 11294 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 11295 rx_fifo.rd_addr[1] -.sym 11298 rx_fifo.rd_addr[2] -.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] -.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 11302 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11303 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11304 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 11305 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11306 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] -.sym 11307 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 11308 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11309 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11310 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 11311 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] -.sym 11312 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11313 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 11315 rx_fifo.rd_addr[3] -.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 11319 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 11321 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] -.sym 11322 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 11325 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 11326 rx_fifo.rd_addr[8] -.sym 11327 rx_fifo.rd_addr[7] -.sym 11333 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11334 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 11337 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 11339 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11340 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11343 rx_fifo.rd_addr[1] -.sym 11344 rx_fifo.rd_addr[2] -.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] -.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 11349 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11351 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11355 rx_fifo.rd_addr[3] -.sym 11356 rx_fifo.rd_addr[2] -.sym 11357 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] -.sym 11358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] -.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] -.sym 11364 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 11369 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 11251 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11252 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 11253 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 11254 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 11255 rx_fifo.rd_addr_gray_wr[3] +.sym 11256 rx_fifo.rd_addr_gray_wr[8] +.sym 11257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 11258 rx_fifo.rd_addr_gray_wr[2] +.sym 11269 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 11271 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 11274 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 11275 rx_fifo.wr_addr[3] +.sym 11276 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 11277 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 11278 rx_fifo.rd_addr[8] +.sym 11279 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 11280 rx_fifo.wr_addr[0] +.sym 11282 rx_fifo.rd_addr[9] +.sym 11286 rx_fifo.rd_addr[1] +.sym 11297 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.sym 11298 rx_fifo.wr_addr_gray[4] +.sym 11301 rx_fifo.wr_addr_gray_rd[4] +.sym 11303 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 11304 rx_fifo.wr_addr_gray[2] +.sym 11305 rx_fifo.rd_addr[7] +.sym 11307 rx_fifo.rd_addr[8] +.sym 11312 rx_fifo.wr_addr_gray_rd[2] +.sym 11313 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 11320 rx_fifo.rd_addr[6] +.sym 11325 rx_fifo.wr_addr_gray_rd[4] +.sym 11332 rx_fifo.wr_addr_gray[4] +.sym 11352 rx_fifo.wr_addr_gray[2] +.sym 11357 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 11358 rx_fifo.rd_addr[8] +.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 11362 rx_fifo.rd_addr[6] +.sym 11363 rx_fifo.rd_addr[7] +.sym 11364 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.sym 11370 rx_fifo.wr_addr_gray_rd[2] .sym 11372 r_counter_$glb_clk -.sym 11373 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11374 spi_if_ins.r_tx_data_valid -.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11379 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 11380 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 11385 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 11388 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 11398 i_glob_clock$SB_IO_IN -.sym 11406 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 11409 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 11416 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 11419 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11420 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11424 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 11426 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 11428 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11429 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 11431 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11435 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 11438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11441 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11442 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 11443 w_rx_fifo_full -.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11446 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 11450 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 11455 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 11456 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 11457 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 11460 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 11461 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11462 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11463 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 11469 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11474 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 11475 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11480 w_rx_fifo_full -.sym 11481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11487 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11494 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 11495 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11377 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 11380 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.sym 11381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11389 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 11390 rx_fifo.wr_addr[9] +.sym 11392 $PACKER_VCC_NET +.sym 11397 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 11399 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 11400 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 11401 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 11402 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 11403 rx_fifo.rd_addr[6] +.sym 11404 rx_fifo.rd_addr[3] +.sym 11405 rx_fifo.rd_addr[2] +.sym 11406 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11407 rx_fifo.rd_addr[7] +.sym 11408 rx_fifo.rd_addr[9] +.sym 11409 rx_fifo.rd_addr[1] +.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11417 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11423 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11426 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11436 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 11441 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 11444 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11446 rx_fifo.rd_addr[1] +.sym 11448 rx_fifo.rd_addr[1] +.sym 11457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 11460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11461 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 11466 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 11473 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 11491 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11494 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11495 r_counter_$glb_clk .sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11497 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 11499 w_cs[1] -.sym 11500 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 11501 w_cs[2] -.sym 11504 w_cs[3] -.sym 11521 rx_fifo.rd_addr_gray[0] -.sym 11524 w_tx_data_smi[2] -.sym 11525 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 11527 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 11530 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 11531 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11540 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 11545 o_led1$SB_IO_OUT -.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 11553 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11555 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 11557 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11565 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 11577 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 11578 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 11584 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 11585 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 11586 o_led1$SB_IO_OUT -.sym 11591 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 11598 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11602 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11609 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11497 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 11499 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11500 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 11505 w_rx_data[0] +.sym 11513 rx_fifo.rd_addr[9] +.sym 11516 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 11521 rx_fifo.rd_addr_gray_wr[4] +.sym 11527 w_rx_data[4] +.sym 11528 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 11529 rx_fifo.rd_addr_gray[4] +.sym 11532 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 11542 rx_fifo.wr_addr_gray[1] +.sym 11543 rx_fifo.wr_addr_gray_rd[3] +.sym 11544 rx_fifo.wr_addr_gray[6] +.sym 11546 rx_fifo.wr_addr[9] +.sym 11547 rx_fifo.wr_addr_gray[3] +.sym 11557 rx_fifo.wr_addr_gray_rd[9] +.sym 11558 rx_fifo.wr_addr_gray_rd[1] +.sym 11562 rx_fifo.wr_addr_gray_rd[6] +.sym 11571 rx_fifo.wr_addr_gray[6] +.sym 11579 rx_fifo.wr_addr_gray_rd[6] +.sym 11584 rx_fifo.wr_addr_gray_rd[3] +.sym 11589 rx_fifo.wr_addr[9] +.sym 11597 rx_fifo.wr_addr_gray[1] +.sym 11604 rx_fifo.wr_addr_gray[3] +.sym 11607 rx_fifo.wr_addr_gray_rd[1] +.sym 11613 rx_fifo.wr_addr_gray_rd[9] .sym 11618 r_counter_$glb_clk -.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11620 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 11622 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 11623 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11624 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 11626 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 11634 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11637 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 11639 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 11641 o_led1$SB_IO_OUT -.sym 11642 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 11643 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 11645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 11647 rx_fifo.rd_addr_gray[2] -.sym 11652 rx_fifo.rd_addr_gray[4] -.sym 11661 rx_fifo.rd_addr_gray[6] -.sym 11665 rx_fifo.rd_addr_gray[3] -.sym 11670 rx_fifo.rd_addr_gray_wr[6] -.sym 11681 rx_fifo.rd_addr_gray[0] -.sym 11689 rx_fifo.rd_addr_gray[5] -.sym 11690 rx_fifo.rd_addr_gray_wr[3] -.sym 11701 rx_fifo.rd_addr_gray[6] -.sym 11708 rx_fifo.rd_addr_gray_wr[3] -.sym 11713 rx_fifo.rd_addr_gray[0] -.sym 11720 rx_fifo.rd_addr_gray_wr[6] -.sym 11727 rx_fifo.rd_addr_gray[3] -.sym 11731 rx_fifo.rd_addr_gray[5] -.sym 11741 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 11743 r_tx_data[1] -.sym 11744 r_tx_data[4] -.sym 11745 r_tx_data[7] -.sym 11746 r_tx_data[6] -.sym 11747 r_tx_data[5] -.sym 11748 r_tx_data[2] -.sym 11749 r_tx_data[3] -.sym 11750 r_tx_data[0] -.sym 11776 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 11787 rx_fifo.rd_addr_gray_wr[1] -.sym 11794 rx_fifo.rd_addr_gray[1] -.sym 11807 rx_fifo.rd_addr_gray[2] -.sym 11809 rx_fifo.rd_addr_gray_wr[4] -.sym 11810 rx_fifo.rd_addr_gray_wr[2] -.sym 11812 rx_fifo.rd_addr_gray[4] -.sym 11823 rx_fifo.rd_addr_gray[4] -.sym 11832 rx_fifo.rd_addr_gray[2] -.sym 11837 rx_fifo.rd_addr_gray[1] -.sym 11844 rx_fifo.rd_addr_gray_wr[2] -.sym 11853 rx_fifo.rd_addr_gray_wr[4] -.sym 11859 rx_fifo.rd_addr_gray_wr[1] +.sym 11620 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 11623 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 11624 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] +.sym 11626 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] +.sym 11627 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] +.sym 11632 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 11636 o_led0_SB_LUT4_I1_O[1] +.sym 11648 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 11667 rx_fifo.wr_addr_gray_rd[7] +.sym 11682 rx_fifo.wr_addr_gray_rd[8] +.sym 11688 rx_fifo.wr_addr_gray[8] +.sym 11692 rx_fifo.wr_addr_gray[7] +.sym 11696 rx_fifo.wr_addr_gray_rd[7] +.sym 11702 rx_fifo.wr_addr_gray_rd[8] +.sym 11727 rx_fifo.wr_addr_gray[8] +.sym 11730 rx_fifo.wr_addr_gray[7] +.sym 11741 r_counter_$glb_clk +.sym 11743 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 11744 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 11745 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 11747 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 11748 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 11749 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 11750 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 11778 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 11801 rx_fifo.rd_addr_gray[4] +.sym 11808 rx_fifo.rd_addr_gray[1] +.sym 11815 rx_fifo.rd_addr_gray_wr[1] +.sym 11820 rx_fifo.rd_addr_gray[4] +.sym 11826 rx_fifo.rd_addr_gray_wr[1] +.sym 11861 rx_fifo.rd_addr_gray[1] .sym 11864 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 11866 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 11867 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 11868 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 11869 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 11870 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 11871 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 11872 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 11873 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 11879 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 11881 o_shdn_tx_lna$SB_IO_OUT -.sym 11893 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 11895 i_glob_clock$SB_IO_IN -.sym 11897 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 11909 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 11912 r_tx_data[2] -.sym 11972 r_tx_data[2] -.sym 11986 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 11987 r_counter_$glb_clk -.sym 11997 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 12014 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 12041 rx_fifo.wr_addr_gray_rd[1] -.sym 12055 rx_fifo.wr_addr_gray[1] -.sym 12084 rx_fifo.wr_addr_gray[1] -.sym 12101 rx_fifo.wr_addr_gray_rd[1] -.sym 12110 r_counter_$glb_clk -.sym 12128 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 12172 rx_fifo.rd_addr_gray[7] -.sym 12176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 12189 rx_fifo.rd_addr_gray[7] -.sym 12199 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 12233 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11866 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 11867 w_tx_data_io[7] +.sym 11870 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 11873 w_tx_data_io[5] +.sym 11989 i_button_SB_LUT4_I0_O[2] +.sym 11990 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 11992 io_ctrl_ins.pmod_dir_state[6] +.sym 11994 io_ctrl_ins.pmod_dir_state[7] +.sym 11995 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 11996 io_ctrl_ins.pmod_dir_state[5] +.sym 12001 i_button_SB_LUT4_I0_O[1] +.sym 12126 i_config[2]$SB_IO_IN +.sym 12128 o_led1_SB_LUT4_I1_I3[3] +.sym 12130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 12181 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 12225 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 12305 i_rst_b$SB_IO_IN -.sym 12309 smi_ctrl_ins.soe_and_reset +.sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E .sym 12310 w_smi_data_output[0] -.sym 12312 o_led0$SB_IO_OUT +.sym 12312 w_smi_data_direction .sym 12313 w_smi_data_output[7] -.sym 12315 o_led0$SB_IO_OUT +.sym 12315 w_smi_data_direction .sym 12316 $PACKER_VCC_NET -.sym 12321 $PACKER_VCC_NET -.sym 12322 smi_ctrl_ins.soe_and_reset -.sym 12326 o_led0$SB_IO_OUT -.sym 12328 w_smi_data_output[0] -.sym 12333 w_smi_data_output[7] -.sym 12334 o_led0$SB_IO_OUT -.sym 12336 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 12337 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12338 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 12339 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 12340 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 12341 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 12342 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12377 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 12386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 12394 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 12395 i_rst_b$SB_IO_IN -.sym 12424 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 12441 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 12442 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 12456 i_rst_b$SB_IO_IN -.sym 12457 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 12463 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 12465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12466 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 12468 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 12469 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12470 tx_fifo.rd_addr[6] -.sym 12473 w_tx_data_smi[1] -.sym 12477 w_smi_data_output[5] -.sym 12481 w_smi_data_input[7] -.sym 12483 smi_ctrl_ins.soe_and_reset -.sym 12486 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12506 tx_fifo.rd_addr[1] -.sym 12509 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 12512 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 12515 i_rst_b$SB_IO_IN -.sym 12516 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12517 w_smi_data_output[3] -.sym 12518 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12520 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12524 tx_fifo.rd_addr[1] -.sym 12528 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 12542 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12543 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 12545 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 12549 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12569 tx_fifo.rd_addr[0] -.sym 12574 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 12579 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 12585 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12591 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 12606 tx_fifo.rd_addr[0] -.sym 12610 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 12618 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 12619 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12319 w_smi_data_output[0] +.sym 12320 w_smi_data_output[7] +.sym 12322 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 12323 w_smi_data_direction +.sym 12326 w_smi_data_direction +.sym 12332 $PACKER_VCC_NET +.sym 12335 tx_fifo.wr_addr[0] +.sym 12336 tx_fifo.wr_addr_gray[5] +.sym 12337 tx_fifo.wr_addr_gray[2] +.sym 12338 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 12339 tx_fifo.wr_addr_gray[3] +.sym 12341 tx_fifo.wr_addr_gray[6] +.sym 12342 tx_fifo.wr_addr[5] +.sym 12369 w_smi_data_input[7] +.sym 12384 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 12399 tx_fifo.wr_addr_gray[6] +.sym 12402 tx_fifo.wr_addr_gray[5] +.sym 12403 tx_fifo.wr_addr_gray[2] +.sym 12408 tx_fifo.wr_addr_gray_rd[5] +.sym 12417 tx_fifo.wr_addr_gray[6] +.sym 12423 tx_fifo.wr_addr_gray[2] +.sym 12436 tx_fifo.wr_addr_gray_rd[5] +.sym 12449 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 12453 tx_fifo.wr_addr_gray[5] +.sym 12457 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 12463 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12465 tx_fifo.wr_addr[9] +.sym 12466 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 12467 tx_fifo.wr_addr_gray[4] +.sym 12468 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12469 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 12470 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 12474 rx_fifo.rd_addr[6] +.sym 12476 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 12479 w_smi_data_direction +.sym 12480 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 12481 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 12482 tx_fifo.wr_addr[0] +.sym 12485 rx_fifo.mem_i.0.1_WDATA_3 +.sym 12486 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12507 i_rst_b$SB_IO_IN +.sym 12515 $PACKER_VCC_NET +.sym 12520 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 12523 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 12524 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 12528 smi_ctrl_ins.int_cnt_rx[4] +.sym 12541 tx_fifo.wr_addr_gray_rd[6] +.sym 12543 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12544 tx_fifo.wr_addr_gray[3] +.sym 12546 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12553 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12555 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 12557 tx_fifo.wr_addr_gray_rd[4] +.sym 12559 smi_ctrl_ins.int_cnt_rx[4] +.sym 12560 tx_fifo.wr_addr_gray[4] +.sym 12562 i_rst_b$SB_IO_IN +.sym 12564 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12567 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 12568 smi_ctrl_ins.int_cnt_rx[3] +.sym 12573 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12574 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12575 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12582 tx_fifo.wr_addr_gray[4] +.sym 12587 tx_fifo.wr_addr_gray[3] +.sym 12591 smi_ctrl_ins.int_cnt_rx[4] +.sym 12592 i_rst_b$SB_IO_IN +.sym 12593 smi_ctrl_ins.int_cnt_rx[3] +.sym 12598 tx_fifo.wr_addr_gray_rd[6] +.sym 12604 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 12606 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 12617 tx_fifo.wr_addr_gray_rd[4] .sym 12620 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12622 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 12623 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] -.sym 12624 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] -.sym 12625 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12627 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] -.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 12629 rx_fifo.wr_addr_gray[0] -.sym 12641 o_led1$SB_IO_OUT -.sym 12643 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 12647 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 12649 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 12650 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 12651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 12652 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 12653 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12656 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12657 smi_ctrl_ins.int_cnt_rx[4] -.sym 12663 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12665 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12669 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12670 tx_fifo.rd_addr[1] -.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12680 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12681 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12683 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12690 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12691 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12698 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12699 tx_fifo.rd_addr[1] -.sym 12703 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12710 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12714 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12715 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12716 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12717 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12726 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12727 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12728 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12729 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12735 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 12738 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12739 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12740 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12741 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12742 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12623 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 12624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 12625 smi_ctrl_ins.int_cnt_rx[4] +.sym 12626 smi_ctrl_ins.int_cnt_rx[3] +.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 12629 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 12634 rx_fifo.wr_addr[3] +.sym 12635 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 12636 w_rx_fifo_pulled_data[23] +.sym 12639 rx_fifo.rd_addr[9] +.sym 12640 w_rx_fifo_pulled_data[29] +.sym 12641 w_rx_fifo_pulled_data[21] +.sym 12642 rx_fifo.wr_addr[0] +.sym 12643 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12644 w_rx_fifo_pulled_data[31] +.sym 12645 tx_fifo.wr_addr[9] +.sym 12647 smi_ctrl_ins.int_cnt_rx[3] +.sym 12649 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 12651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 12653 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 12654 tx_fifo.wr_addr_gray_rd[1] +.sym 12655 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12657 smi_ctrl_ins.r_fifo_push +.sym 12665 tx_fifo.wr_addr[9] +.sym 12673 tx_fifo.wr_addr_gray_rd[3] +.sym 12675 tx_fifo.wr_addr_gray_rd[2] +.sym 12680 tx_fifo.wr_addr_gray_rd[1] +.sym 12681 tx_fifo.wr_addr_gray_rd[9] +.sym 12708 tx_fifo.wr_addr[9] +.sym 12716 tx_fifo.wr_addr_gray_rd[3] +.sym 12726 tx_fifo.wr_addr_gray_rd[2] +.sym 12735 tx_fifo.wr_addr_gray_rd[1] +.sym 12739 tx_fifo.wr_addr_gray_rd[9] .sym 12743 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12746 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 12747 smi_ctrl_ins.r_fifo_push -.sym 12748 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] -.sym 12750 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 12751 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 12752 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] -.sym 12757 rx_fifo.mem_i.0.1_WDATA -.sym 12761 rx_fifo.mem_i.0.1_WDATA_2 -.sym 12762 rx_fifo.wr_addr[3] -.sym 12764 rx_fifo.wr_addr[1] -.sym 12767 o_led1$SB_IO_OUT -.sym 12769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12770 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12771 i_rst_b_SB_LUT4_I3_O -.sym 12773 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 12777 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12787 tx_fifo.rd_addr_gray[3] -.sym 12788 tx_fifo.rd_addr_gray[2] -.sym 12792 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 12800 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12801 tx_fifo.rd_addr[1] -.sym 12803 tx_fifo.rd_addr_gray_wr[3] -.sym 12804 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12805 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 12811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 12812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12813 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12816 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 12821 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12822 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12825 tx_fifo.rd_addr_gray[3] -.sym 12832 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12833 tx_fifo.rd_addr[1] -.sym 12834 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 12839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 12851 tx_fifo.rd_addr_gray_wr[3] -.sym 12864 tx_fifo.rd_addr_gray[2] +.sym 12745 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 12746 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] +.sym 12747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 12748 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 12749 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] +.sym 12750 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12751 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12752 tx_fifo.rd_addr_gray_wr[1] +.sym 12757 rx_fifo.rd_addr[1] +.sym 12758 w_rx_fifo_pulled_data[30] +.sym 12759 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12760 smi_ctrl_ins.int_cnt_rx[4] +.sym 12763 rx_fifo.wr_addr[0] +.sym 12764 rx_fifo.mem_i.0.3_WDATA_1 +.sym 12765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12769 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 12771 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 12772 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12773 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 12774 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 12775 smi_ctrl_ins.r_fifo_push_1 +.sym 12776 rx_fifo.wr_addr[5] +.sym 12778 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 12779 rx_fifo.wr_addr_gray_rd[0] +.sym 12780 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 12786 smi_ctrl_ins.r_fifo_pull_1 +.sym 12789 w_rx_fifo_empty +.sym 12793 smi_ctrl_ins.w_fifo_push_trigger +.sym 12795 smi_ctrl_ins.r_fifo_pull +.sym 12797 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 12801 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12802 rx_fifo.rd_addr[3] +.sym 12807 rx_fifo.rd_addr[2] +.sym 12809 rx_fifo.rd_addr[1] +.sym 12812 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 12813 smi_ctrl_ins.r_fifo_push +.sym 12814 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 12815 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12821 smi_ctrl_ins.r_fifo_pull +.sym 12826 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12832 rx_fifo.rd_addr[1] +.sym 12833 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12839 smi_ctrl_ins.w_fifo_push_trigger +.sym 12843 smi_ctrl_ins.r_fifo_pull +.sym 12844 w_rx_fifo_empty +.sym 12845 smi_ctrl_ins.r_fifo_pull_1 +.sym 12849 rx_fifo.rd_addr[2] +.sym 12850 rx_fifo.rd_addr[3] +.sym 12851 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 12857 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 12858 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 12864 smi_ctrl_ins.r_fifo_push .sym 12866 r_counter_$glb_clk -.sym 12868 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 12869 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 12870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 12871 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12872 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 12873 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 12874 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 12875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 12868 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 12869 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 12871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 12872 tx_fifo.wr_addr_gray[1] +.sym 12873 tx_fifo.wr_addr_gray[0] +.sym 12874 tx_fifo.wr_addr_gray[7] +.sym 12875 tx_fifo.wr_addr_gray[8] .sym 12880 rx_fifo.rd_addr[7] -.sym 12881 rx_fifo.rd_addr[0] -.sym 12882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 12883 rx_fifo.rd_addr[6] -.sym 12884 rx_fifo.wr_addr[4] -.sym 12887 rx_fifo.wr_addr[6] -.sym 12888 w_rx_fifo_pulled_data[23] -.sym 12889 w_smi_data_input[7] -.sym 12894 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 12896 tx_fifo.rd_addr[1] -.sym 12899 smi_ctrl_ins.int_cnt_rx[3] -.sym 12901 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 12902 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12881 rx_fifo.rd_addr[6] +.sym 12882 rx_fifo.rd_addr[3] +.sym 12887 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12890 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 12891 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 12896 rx_fifo.wr_addr[7] +.sym 12898 $PACKER_VCC_NET +.sym 12900 rx_fifo.rd_addr[4] +.sym 12901 rx_fifo.rd_addr[3] .sym 12903 i_rst_b$SB_IO_IN -.sym 12910 w_tx_fifo_pull -.sym 12911 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] -.sym 12912 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] -.sym 12913 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12914 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 12916 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12917 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 12919 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 12920 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] -.sym 12923 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12927 i_rst_b$SB_IO_IN -.sym 12928 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12929 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] -.sym 12931 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12932 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 12934 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 12935 w_tx_fifo_empty -.sym 12936 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12940 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 12948 w_tx_fifo_empty -.sym 12949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 12950 w_tx_fifo_pull -.sym 12951 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12954 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12955 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12956 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12957 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] -.sym 12961 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] -.sym 12962 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 12963 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] -.sym 12966 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12967 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12968 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 12969 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 12974 w_tx_fifo_pull -.sym 12975 i_rst_b$SB_IO_IN -.sym 12978 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] -.sym 12979 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12980 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 12981 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 12984 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 12985 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 12987 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12989 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 12910 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12912 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 12913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 12914 rx_fifo.rd_addr[2] +.sym 12915 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12916 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 12918 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 12919 w_tx_fifo_full +.sym 12920 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 12921 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12922 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 12923 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 12924 rx_fifo.rd_addr[1] +.sym 12925 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12927 smi_ctrl_ins.r_fifo_push +.sym 12928 w_rx_fifo_empty +.sym 12929 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] +.sym 12930 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12931 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 12932 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12935 smi_ctrl_ins.r_fifo_push_1 +.sym 12936 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 12939 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 12940 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 12942 smi_ctrl_ins.r_fifo_push +.sym 12943 w_tx_fifo_full +.sym 12945 smi_ctrl_ins.r_fifo_push_1 +.sym 12948 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 12949 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 12950 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 12954 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12955 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12956 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12957 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12960 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 12961 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 12962 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 12963 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 12967 rx_fifo.rd_addr[2] +.sym 12968 rx_fifo.rd_addr[1] +.sym 12969 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12972 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12973 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 12974 rx_fifo.rd_addr[2] +.sym 12975 rx_fifo.rd_addr[1] +.sym 12978 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 12980 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 12984 w_rx_fifo_empty +.sym 12985 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 12986 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 12987 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] +.sym 12989 r_counter_$glb_clk .sym 12990 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12991 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12992 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 12993 tx_fifo.rd_addr_gray[4] -.sym 12994 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 12995 tx_fifo.rd_addr_gray[7] -.sym 12996 tx_fifo.rd_addr_gray[6] -.sym 12997 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 13003 rx_fifo.mem_i.0.3_WDATA -.sym 13004 tx_fifo.wr_addr_gray_rd[2] -.sym 13005 rx_fifo.mem_i.0.3_WDATA_1 -.sym 13006 rx_fifo.mem_q.0.1_WDATA_3 -.sym 13007 rx_fifo.mem_q.0.1_WDATA -.sym 13008 tx_fifo.wr_addr_gray_rd[8] -.sym 13009 rx_fifo.mem_q.0.1_WDATA_1 -.sym 13011 rx_fifo.rd_addr[2] -.sym 13012 rx_fifo.rd_addr[6] -.sym 13014 rx_fifo.mem_q.0.1_WDATA_2 -.sym 13018 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 13019 rx_fifo.wr_addr[9] -.sym 13022 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 13025 smi_ctrl_ins.int_cnt_rx[3] -.sym 13033 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 13034 w_tx_fifo_pull -.sym 13042 w_tx_fifo_empty -.sym 13043 i_rst_b_SB_LUT4_I3_O -.sym 13045 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 13047 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 13051 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 13057 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 13063 i_rst_b$SB_IO_IN -.sym 13078 w_tx_fifo_empty -.sym 13083 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 13084 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 13086 w_tx_fifo_pull -.sym 13089 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 13091 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 13092 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 13103 i_rst_b$SB_IO_IN -.sym 13111 i_rst_b_SB_LUT4_I3_O -.sym 13112 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 13113 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13116 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 13117 smi_ctrl_ins.int_cnt_rx[3] -.sym 13119 smi_ctrl_ins.int_cnt_rx[4] -.sym 13126 rx_fifo.rd_addr[3] -.sym 13128 rx_fifo.rd_addr[2] -.sym 13129 rx_fifo.rd_addr[8] -.sym 13130 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 13131 o_led1$SB_IO_OUT -.sym 13132 rx_fifo.wr_addr[7] -.sym 13134 rx_fifo.wr_addr[6] -.sym 13135 rx_fifo.wr_addr[5] -.sym 13136 rx_fifo.wr_addr[4] -.sym 13137 rx_fifo.rd_addr[4] -.sym 13141 smi_ctrl_ins.int_cnt_rx[4] -.sym 13144 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 13147 i_rst_b_SB_LUT4_I3_O -.sym 13148 w_tx_fifo_full -.sym 13158 w_rx_fifo_empty -.sym 13159 smi_ctrl_ins.w_fifo_pull_trigger -.sym 13160 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 13161 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 13164 smi_ctrl_ins.r_fifo_pull_1 -.sym 13171 smi_ctrl_ins.r_fifo_pull -.sym 13174 smi_ctrl_ins.int_cnt_rx[3] -.sym 13176 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 13184 smi_ctrl_ins.int_cnt_rx[4] -.sym 13185 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 13190 smi_ctrl_ins.w_fifo_pull_trigger -.sym 13197 smi_ctrl_ins.r_fifo_pull -.sym 13201 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 13203 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 13206 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 13207 smi_ctrl_ins.int_cnt_rx[4] -.sym 13208 smi_ctrl_ins.int_cnt_rx[3] -.sym 13209 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 13230 w_rx_fifo_empty -.sym 13231 smi_ctrl_ins.r_fifo_pull -.sym 13233 smi_ctrl_ins.r_fifo_pull_1 +.sym 12991 tx_fifo.wr_addr_gray_rd[8] +.sym 12992 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 12994 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 12995 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 12997 tx_fifo.wr_addr_gray_rd[7] +.sym 12998 tx_fifo.wr_addr_gray_rd[0] +.sym 13003 tx_fifo.wr_addr[1] +.sym 13006 rx_fifo.wr_addr[4] +.sym 13007 rx_fifo.rd_addr[1] +.sym 13008 rx_fifo.rd_addr[2] +.sym 13009 w_tx_fifo_full +.sym 13010 rx_fifo.rd_addr[0] +.sym 13012 rx_fifo.wr_addr[3] +.sym 13016 w_tx_fifo_full +.sym 13018 w_rx_fifo_empty +.sym 13036 rx_fifo.rd_addr[3] +.sym 13038 rx_fifo.rd_addr[6] +.sym 13039 rx_fifo.rd_addr[5] +.sym 13044 rx_fifo.rd_addr[4] +.sym 13052 rx_fifo.rd_addr[0] +.sym 13053 rx_fifo.rd_addr[2] +.sym 13058 rx_fifo.rd_addr[7] +.sym 13063 rx_fifo.rd_addr[1] +.sym 13064 $nextpnr_ICESTORM_LC_4$O +.sym 13067 rx_fifo.rd_addr[0] +.sym 13070 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 13072 rx_fifo.rd_addr[1] +.sym 13074 rx_fifo.rd_addr[0] +.sym 13076 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 13078 rx_fifo.rd_addr[2] +.sym 13080 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 13082 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 13084 rx_fifo.rd_addr[3] +.sym 13086 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 13088 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 13090 rx_fifo.rd_addr[4] +.sym 13092 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 13094 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 13097 rx_fifo.rd_addr[5] +.sym 13098 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 13100 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 13103 rx_fifo.rd_addr[6] +.sym 13104 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 13106 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 13109 rx_fifo.rd_addr[7] +.sym 13110 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 13114 w_tx_data_smi[2] +.sym 13116 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 13117 w_tx_data_smi[1] +.sym 13119 w_tx_data_smi[0] +.sym 13120 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 13122 io_pmod[7]$SB_IO_IN +.sym 13125 io_pmod[7]$SB_IO_IN +.sym 13129 w_rx_fifo_empty +.sym 13131 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 13138 rx_fifo.rd_addr[4] +.sym 13142 o_led0_SB_LUT4_I1_O[1] +.sym 13144 rx_fifo.rd_addr[5] +.sym 13150 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 13155 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 13157 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.sym 13159 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 13160 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 13161 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 13162 rx_fifo.rd_addr[8] +.sym 13166 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13167 rx_fifo.rd_addr[4] +.sym 13168 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 13169 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 13172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 13177 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 13184 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.sym 13185 rx_fifo.rd_addr[9] +.sym 13186 rx_fifo.rd_addr[5] +.sym 13187 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 13189 rx_fifo.rd_addr[8] +.sym 13191 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 13196 rx_fifo.rd_addr[9] +.sym 13197 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 13200 rx_fifo.rd_addr[5] +.sym 13201 rx_fifo.rd_addr[4] +.sym 13202 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 13203 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 13206 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 13207 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.sym 13208 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 13209 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.sym 13214 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 13219 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 13224 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 13231 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 13234 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 13235 r_counter_$glb_clk .sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13241 w_tx_data_smi[0] -.sym 13245 io_pmod[6]$SB_IO_IN -.sym 13248 io_pmod[6]$SB_IO_IN -.sym 13251 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 13252 smi_ctrl_ins.int_cnt_rx[3] +.sym 13237 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] +.sym 13238 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 13243 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 13244 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 13251 $PACKER_VCC_NET +.sym 13252 rx_fifo.rd_addr[9] .sym 13253 rx_fifo.wr_addr[1] -.sym 13255 rx_fifo.mem_i.0.3_WDATA_2 -.sym 13256 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 13257 rx_fifo.wr_addr[5] -.sym 13258 rx_fifo.wr_addr[1] -.sym 13259 rx_fifo.wr_addr[3] -.sym 13260 rx_fifo.mem_i.0.3_WDATA_3 -.sym 13263 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13267 $PACKER_VCC_NET -.sym 13272 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 13278 rx_fifo.rd_addr[4] -.sym 13280 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 13281 rx_fifo.rd_addr[3] -.sym 13282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 13284 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 13285 o_led1$SB_IO_OUT -.sym 13286 rx_fifo.rd_addr[4] -.sym 13288 rx_fifo.rd_addr[1] -.sym 13289 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 13290 rx_fifo.rd_addr[5] -.sym 13292 rx_fifo.wr_addr_gray_rd_r[0] -.sym 13295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] -.sym 13296 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13301 w_rx_fifo_empty -.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] -.sym 13308 w_tx_fifo_full -.sym 13309 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] -.sym 13312 rx_fifo.wr_addr_gray_rd_r[0] -.sym 13314 rx_fifo.rd_addr[1] -.sym 13317 rx_fifo.rd_addr[4] -.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 13319 rx_fifo.rd_addr[5] -.sym 13324 rx_fifo.rd_addr[3] -.sym 13325 rx_fifo.rd_addr[4] -.sym 13331 o_led1$SB_IO_OUT -.sym 13341 w_tx_fifo_full -.sym 13347 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 13348 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] -.sym 13349 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] -.sym 13350 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] -.sym 13353 rx_fifo.wr_addr_gray_rd_r[0] -.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 13355 w_rx_fifo_empty -.sym 13357 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13358 r_counter_$glb_clk -.sym 13359 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 13361 $PACKER_VCC_NET -.sym 13362 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 13363 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 13364 spi_if_ins.spi.r_tx_bit_count[0] -.sym 13365 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 13366 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 13367 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 13372 rx_fifo.rd_addr[7] -.sym 13373 w_rx_fifo_pulled_data[31] -.sym 13374 rx_fifo.rd_addr[1] -.sym 13377 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 13378 rx_fifo.rd_addr[5] -.sym 13379 w_rx_fifo_pulled_data[29] -.sym 13380 rx_fifo.wr_addr_gray_rd_r[0] -.sym 13381 i_glob_clock$SB_IO_IN -.sym 13382 rx_fifo.rd_addr[0] -.sym 13384 spi_if_ins.w_rx_data[5] -.sym 13385 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13393 spi_if_ins.w_rx_data[6] -.sym 13395 $PACKER_VCC_NET -.sym 13402 spi_if_ins.state_if[1] -.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13406 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13408 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13416 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13417 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13419 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13420 spi_if_ins.state_if[0] -.sym 13423 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 13425 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13434 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13436 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 13437 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13440 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13442 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13443 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13446 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13454 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13459 spi_if_ins.state_if[1] -.sym 13461 spi_if_ins.state_if[0] -.sym 13464 spi_if_ins.state_if[0] -.sym 13465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13466 spi_if_ins.state_if[1] -.sym 13471 spi_if_ins.state_if[1] -.sym 13472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13473 spi_if_ins.state_if[0] -.sym 13476 spi_if_ins.state_if[0] -.sym 13478 spi_if_ins.state_if[1] -.sym 13479 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13481 r_counter_$glb_clk -.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13483 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 13484 spi_if_ins.spi.r_tx_byte[4] -.sym 13485 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 13486 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 13487 spi_if_ins.spi.r_tx_byte[7] -.sym 13488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 13489 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 13490 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 13497 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13500 rx_fifo.rd_addr[9] -.sym 13502 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13504 $PACKER_VCC_NET -.sym 13507 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 13508 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13511 rx_fifo.wr_addr[9] -.sym 13512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13516 w_cs[1] -.sym 13517 rx_fifo.wr_addr[8] -.sym 13526 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13528 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13535 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13538 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13540 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13545 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13551 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 13554 i_rst_b$SB_IO_IN -.sym 13555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13563 i_rst_b$SB_IO_IN -.sym 13564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 13569 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13570 i_rst_b$SB_IO_IN -.sym 13571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13572 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13575 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13576 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13583 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13584 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13589 i_rst_b$SB_IO_IN -.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13594 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13596 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13599 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13600 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13603 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13604 r_counter_$glb_clk -.sym 13605 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13606 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13607 spi_if_ins.spi.r_tx_byte[0] -.sym 13608 spi_if_ins.spi.r_tx_byte[2] -.sym 13609 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 13610 spi_if_ins.spi.r_tx_byte[5] -.sym 13611 spi_if_ins.spi.r_tx_byte[6] -.sym 13612 spi_if_ins.spi.r_tx_byte[3] -.sym 13613 spi_if_ins.spi.r_tx_byte[1] -.sym 13618 spi_if_ins.r_tx_data_valid -.sym 13622 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13627 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 13631 spi_if_ins.r_tx_byte[3] -.sym 13632 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13633 spi_if_ins.r_tx_byte[4] -.sym 13634 w_tx_data_io[0] -.sym 13635 spi_if_ins.r_tx_byte[7] -.sym 13637 spi_if_ins.r_tx_byte[1] -.sym 13639 w_tx_data_io[1] -.sym 13640 i_rst_b$SB_IO_IN -.sym 13641 spi_if_ins.r_tx_byte[0] -.sym 13648 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 13649 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13651 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 13655 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13656 spi_if_ins.w_rx_data[5] -.sym 13661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13663 spi_if_ins.w_rx_data[6] -.sym 13681 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13683 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13692 spi_if_ins.w_rx_data[5] -.sym 13694 spi_if_ins.w_rx_data[6] -.sym 13698 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 13704 spi_if_ins.w_rx_data[5] -.sym 13706 spi_if_ins.w_rx_data[6] -.sym 13723 spi_if_ins.w_rx_data[6] -.sym 13725 spi_if_ins.w_rx_data[5] -.sym 13726 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13727 r_counter_$glb_clk -.sym 13728 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 13729 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 13730 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 13731 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13733 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 13735 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13742 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13743 rx_fifo.wr_addr[0] -.sym 13745 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13747 w_cs[1] -.sym 13748 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13751 w_cs[2] -.sym 13753 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 13754 w_cs[1] -.sym 13755 spi_if_ins.r_tx_byte[5] -.sym 13756 spi_if_ins.r_tx_byte[2] +.sym 13258 rx_fifo.rd_addr[8] +.sym 13259 rx_fifo.rd_addr[4] +.sym 13262 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 13266 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 13269 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 13270 rx_fifo.rd_addr[6] +.sym 13279 rx_fifo.rd_addr[6] +.sym 13280 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 13281 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 13282 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 13283 rx_fifo.rd_addr_gray[5] +.sym 13284 rx_fifo.rd_addr[2] +.sym 13285 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.sym 13286 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 13288 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 13289 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 13290 rx_fifo.rd_addr[4] +.sym 13292 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 13293 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] +.sym 13294 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] +.sym 13296 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.sym 13297 rx_fifo.rd_addr[9] +.sym 13298 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] +.sym 13299 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.sym 13301 rx_fifo.rd_addr[8] +.sym 13302 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13304 rx_fifo.rd_addr[5] +.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] +.sym 13309 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 13312 rx_fifo.rd_addr[6] +.sym 13313 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 13317 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] +.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 13320 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] +.sym 13323 rx_fifo.rd_addr[2] +.sym 13324 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13325 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 13326 rx_fifo.rd_addr[4] +.sym 13329 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 13330 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.sym 13331 rx_fifo.rd_addr[5] +.sym 13336 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 13337 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 13341 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.sym 13342 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] +.sym 13343 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.sym 13344 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] +.sym 13348 rx_fifo.rd_addr_gray[5] +.sym 13353 rx_fifo.rd_addr[9] +.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 13355 rx_fifo.rd_addr[8] +.sym 13356 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 13358 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13361 w_rx_data[4] +.sym 13362 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13363 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13364 w_rx_data[5] +.sym 13365 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 13366 w_rx_data[7] +.sym 13367 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13373 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 13376 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 13377 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 13382 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13385 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.sym 13386 io_pmod[6]$SB_IO_IN +.sym 13389 rx_fifo.rd_addr[3] +.sym 13390 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 13391 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13395 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13402 rx_fifo.rd_addr_gray_wr[4] +.sym 13405 rx_fifo.rd_addr_gray_wr[3] +.sym 13408 rx_fifo.rd_addr_gray_wr[2] +.sym 13412 rx_fifo.rd_addr_gray[2] +.sym 13414 rx_fifo.rd_addr_gray[3] +.sym 13415 rx_fifo.rd_addr_gray_wr[5] +.sym 13418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] +.sym 13421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] +.sym 13429 rx_fifo.rd_addr_gray[8] +.sym 13436 rx_fifo.rd_addr_gray_wr[3] +.sym 13442 rx_fifo.rd_addr_gray_wr[5] +.sym 13446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] +.sym 13449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] +.sym 13454 rx_fifo.rd_addr_gray_wr[4] +.sym 13460 rx_fifo.rd_addr_gray[3] +.sym 13464 rx_fifo.rd_addr_gray[8] +.sym 13471 rx_fifo.rd_addr_gray_wr[2] +.sym 13477 rx_fifo.rd_addr_gray[2] +.sym 13481 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13483 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 13484 spi_if_ins.state_if[0] +.sym 13485 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13486 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13487 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 13488 spi_if_ins.state_if[1] +.sym 13489 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 13490 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13496 rx_fifo.rd_addr_gray_wr[4] +.sym 13500 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13504 w_rx_data[4] +.sym 13507 w_rx_data[2] +.sym 13508 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 13510 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13511 w_rx_data[5] +.sym 13512 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 13514 i_glob_clock$SB_IO_IN +.sym 13515 w_rx_data[7] +.sym 13516 w_rx_data[1] +.sym 13517 w_rx_data[6] +.sym 13518 w_rx_data[3] +.sym 13527 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 13529 rx_fifo.rd_addr[4] +.sym 13532 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13542 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13546 io_pmod[6]$SB_IO_IN +.sym 13547 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13549 rx_fifo.rd_addr[3] +.sym 13551 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13554 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 13577 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 13593 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13594 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 13595 rx_fifo.rd_addr[3] +.sym 13596 rx_fifo.rd_addr[4] +.sym 13599 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13600 io_pmod[6]$SB_IO_IN +.sym 13601 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13603 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13604 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13607 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 13609 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13610 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 13611 o_led0_SB_LUT4_I1_O[1] +.sym 13612 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 13618 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13625 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13631 i_rst_b$SB_IO_IN +.sym 13632 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 13633 o_led0_SB_LUT4_I1_O[1] +.sym 13636 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 13639 w_rx_data[4] +.sym 13641 w_fetch +.sym 13648 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 13655 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13658 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 13663 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13667 rx_fifo.rd_addr[6] +.sym 13670 io_pmod[7]$SB_IO_IN +.sym 13671 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 13674 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 13676 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13678 rx_fifo.rd_addr[8] +.sym 13680 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 13682 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13693 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13694 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13695 io_pmod[7]$SB_IO_IN +.sym 13698 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 13699 rx_fifo.rd_addr[8] +.sym 13700 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 13701 rx_fifo.rd_addr[6] +.sym 13726 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 13727 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13728 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13729 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 13730 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 13731 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 13732 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 13734 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13735 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.sym 13736 o_led1_SB_LUT4_I1_I2[2] +.sym 13744 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 13748 w_fetch +.sym 13755 o_rx_h_tx_l$SB_IO_OUT +.sym 13756 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] .sym 13757 i_rst_b$SB_IO_IN -.sym 13760 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13761 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 13770 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13771 w_tx_data_io[2] -.sym 13772 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 13779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13781 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 13784 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13785 w_tx_data_smi[2] -.sym 13787 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 13788 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13789 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13796 w_tx_data_smi[1] -.sym 13798 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13799 w_tx_data_io[1] -.sym 13800 i_rst_b$SB_IO_IN -.sym 13801 io_pmod[6]$SB_IO_IN -.sym 13803 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 13804 w_tx_data_smi[1] -.sym 13805 w_tx_data_io[1] -.sym 13806 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13816 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13821 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13822 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13824 io_pmod[6]$SB_IO_IN -.sym 13827 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13828 i_rst_b$SB_IO_IN -.sym 13829 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13833 i_rst_b$SB_IO_IN -.sym 13835 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 13839 w_tx_data_smi[2] -.sym 13840 w_tx_data_io[2] -.sym 13841 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 13842 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13849 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 13850 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13758 o_rx_h_tx_l_b$SB_IO_OUT +.sym 13762 w_rx_data[1] +.sym 13779 w_rx_data[2] +.sym 13780 w_rx_data[4] +.sym 13781 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 13786 w_rx_data[1] +.sym 13787 w_rx_data[7] +.sym 13788 w_rx_data[3] +.sym 13789 w_rx_data[6] +.sym 13806 w_rx_data[4] +.sym 13823 w_rx_data[6] +.sym 13828 w_rx_data[7] +.sym 13836 w_rx_data[3] +.sym 13841 w_rx_data[1] +.sym 13846 w_rx_data[2] +.sym 13849 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 13850 r_counter_$glb_clk .sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13852 spi_if_ins.r_tx_byte[3] -.sym 13853 spi_if_ins.r_tx_byte[4] -.sym 13854 spi_if_ins.r_tx_byte[7] -.sym 13855 spi_if_ins.r_tx_byte[1] -.sym 13856 spi_if_ins.r_tx_byte[6] -.sym 13857 spi_if_ins.r_tx_byte[0] -.sym 13858 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 13859 spi_if_ins.r_tx_byte[5] -.sym 13874 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13875 w_tx_data_io[2] -.sym 13880 w_cs[0] -.sym 13881 w_rx_data[1] -.sym 13883 w_rx_data[2] -.sym 13886 i_rst_b$SB_IO_IN -.sym 13893 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 13894 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 13895 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 13896 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13897 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 13898 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 13899 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13900 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 13901 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 13904 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 13905 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 13906 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 13907 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 13908 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 13909 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 13913 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 13917 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 13918 i_glob_clock$SB_IO_IN -.sym 13920 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 13921 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 13923 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 13926 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 13927 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 13928 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13932 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 13933 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 13934 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13935 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13938 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 13939 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 13940 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13944 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13945 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13946 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 13947 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 13950 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13951 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 13952 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 13956 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 13957 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13958 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 13959 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 13962 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13963 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 13964 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 13965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 13968 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 13969 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 13970 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 13971 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 13972 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 13973 i_glob_clock$SB_IO_IN -.sym 13975 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13976 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] -.sym 13977 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] -.sym 13978 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13979 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13980 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] -.sym 13981 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 13982 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13987 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E -.sym 13996 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 14000 i_glob_clock$SB_IO_IN -.sym 14001 w_rx_data[0] -.sym 14003 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 14027 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14033 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] -.sym 14035 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14036 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 14037 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] -.sym 14040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 14042 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] -.sym 14045 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14046 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] -.sym 14047 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14049 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14052 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14056 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 14058 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14063 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14064 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] -.sym 14068 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14070 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14076 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 14079 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] -.sym 14082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14088 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] -.sym 14093 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] -.sym 14094 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 14095 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13852 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 13853 io_ctrl_ins.pmod_dir_state[1] +.sym 13854 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 13856 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 13858 o_led1_SB_LUT4_I1_I3[1] +.sym 13867 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 13878 spi_if_ins.w_rx_data[6] +.sym 13880 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 13881 i_rst_b$SB_IO_IN +.sym 13882 w_cs[2] +.sym 13884 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 13885 spi_if_ins.w_rx_data[5] +.sym 13886 o_led1_SB_LUT4_I1_I2[2] +.sym 13887 o_tr_vc1$SB_IO_OUT +.sym 13895 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13897 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13898 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13899 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] +.sym 13901 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13904 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13906 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] +.sym 13908 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] +.sym 13920 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 13926 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13927 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13932 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13933 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] +.sym 13940 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13941 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13950 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13951 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13956 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13959 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] +.sym 13963 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13968 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13971 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] +.sym 13972 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 13973 r_counter_$glb_clk +.sym 13974 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13975 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 13976 w_cs[2] +.sym 13977 w_cs[3] +.sym 13979 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 13980 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 13982 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 14003 w_rx_data[7] +.sym 14004 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 14006 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 14007 i_glob_clock$SB_IO_IN +.sym 14008 w_rx_data[5] +.sym 14017 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 14022 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 14024 i_button_SB_LUT4_I0_O[2] +.sym 14026 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 14027 o_rx_h_tx_l$SB_IO_OUT +.sym 14028 o_rx_h_tx_l_b$SB_IO_OUT +.sym 14029 i_button_SB_LUT4_I0_O[1] +.sym 14043 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 14047 o_tr_vc1$SB_IO_OUT +.sym 14049 i_button_SB_LUT4_I0_O[1] +.sym 14050 o_rx_h_tx_l_b$SB_IO_OUT +.sym 14051 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 14055 i_button_SB_LUT4_I0_O[2] +.sym 14056 o_rx_h_tx_l$SB_IO_OUT +.sym 14058 i_button_SB_LUT4_I0_O[1] +.sym 14076 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 14092 o_tr_vc1$SB_IO_OUT +.sym 14093 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 14094 i_button_SB_LUT4_I0_O[1] +.sym 14095 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E .sym 14096 r_counter_$glb_clk -.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14104 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] -.sym 14131 i_rst_b$SB_IO_IN -.sym 14226 r_counter -.sym 14243 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 14099 r_tx_data[2] +.sym 14100 r_tx_data[5] +.sym 14101 r_tx_data[7] +.sym 14102 r_tx_data[6] +.sym 14104 r_tx_data[4] +.sym 14105 r_tx_data[1] +.sym 14113 w_tx_data_io[1] +.sym 14123 i_rst_b$SB_IO_IN +.sym 14124 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 14129 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 14141 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 14146 i_config[2]$SB_IO_IN +.sym 14147 w_rx_data[6] +.sym 14150 io_ctrl_ins.pmod_dir_state[6] +.sym 14152 io_ctrl_ins.pmod_dir_state[7] +.sym 14154 o_led1_SB_LUT4_I1_I3[3] +.sym 14158 o_led1_SB_LUT4_I1_I2[2] +.sym 14160 i_button$SB_IO_IN +.sym 14163 w_rx_data[7] +.sym 14167 i_config[3]$SB_IO_IN +.sym 14168 w_rx_data[5] +.sym 14170 io_ctrl_ins.pmod_dir_state[5] +.sym 14172 io_ctrl_ins.pmod_dir_state[7] +.sym 14173 i_button$SB_IO_IN +.sym 14174 o_led1_SB_LUT4_I1_I3[3] +.sym 14175 o_led1_SB_LUT4_I1_I2[2] +.sym 14178 i_config[2]$SB_IO_IN +.sym 14179 io_ctrl_ins.pmod_dir_state[5] +.sym 14180 o_led1_SB_LUT4_I1_I2[2] +.sym 14181 o_led1_SB_LUT4_I1_I3[3] +.sym 14192 w_rx_data[6] +.sym 14202 w_rx_data[7] +.sym 14208 o_led1_SB_LUT4_I1_I3[3] +.sym 14209 i_config[3]$SB_IO_IN +.sym 14210 io_ctrl_ins.pmod_dir_state[6] +.sym 14211 o_led1_SB_LUT4_I1_I2[2] +.sym 14217 w_rx_data[5] +.sym 14218 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 14219 r_counter_$glb_clk +.sym 14221 r_counter +.sym 14225 i_config[3]$SB_IO_IN +.sym 14226 i_button$SB_IO_IN +.sym 14235 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 14237 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 14243 w_rx_data[6] .sym 14249 i_rst_b$SB_IO_IN +.sym 14251 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 14344 i_rst_b$SB_IO_IN .sym 14373 i_rst_b$SB_IO_IN -.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14408 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14418 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14412 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14418 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .sym 14419 w_smi_data_output[3] -.sym 14421 o_led0$SB_IO_OUT +.sym 14421 w_smi_data_direction .sym 14425 $PACKER_VCC_NET .sym 14430 $PACKER_VCC_NET -.sym 14431 o_led0$SB_IO_OUT -.sym 14432 w_smi_data_output[3] -.sym 14438 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14445 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14447 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14448 smi_ctrl_ins.swe_and_reset -.sym 14449 tx_fifo.wr_addr_gray_rd[4] -.sym 14450 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14451 smi_ctrl_ins.soe_and_reset -.sym 14456 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14458 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 14462 $PACKER_VCC_NET -.sym 14468 w_tx_data_smi[0] -.sym 14501 tx_fifo.rd_addr[6] -.sym 14503 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14504 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14507 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 14508 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 14509 tx_fifo.rd_addr[1] -.sym 14514 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 14515 tx_fifo.rd_addr[0] -.sym 14518 $nextpnr_ICESTORM_LC_7$O -.sym 14521 tx_fifo.rd_addr[0] -.sym 14524 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 14527 tx_fifo.rd_addr[1] -.sym 14528 tx_fifo.rd_addr[0] -.sym 14530 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 14532 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 14534 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 14536 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 14539 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 14540 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 14542 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 14544 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14546 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 14548 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 14550 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 14552 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 14554 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 14557 tx_fifo.rd_addr[6] -.sym 14558 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 14560 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 14562 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14564 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 14436 w_smi_data_direction +.sym 14439 w_smi_data_output[3] +.sym 14442 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14445 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14446 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 14447 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 14448 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14449 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14450 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14451 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14455 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14474 i_rst_b$SB_IO_IN +.sym 14479 w_smi_data_output[3] +.sym 14486 tx_fifo.wr_addr[0] +.sym 14489 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14490 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14492 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 14495 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14496 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14498 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 14500 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14507 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 14513 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14521 tx_fifo.wr_addr[0] +.sym 14528 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14534 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14537 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14539 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 14546 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 14555 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 14557 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14561 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14565 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14566 r_counter_$glb_clk +.sym 14567 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 14568 i_smi_swe_srw$SB_IO_IN -.sym 14573 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14574 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 14575 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14576 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 14577 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14578 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14579 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 14580 i_rst_b$SB_IO_IN -.sym 14583 i_rst_b$SB_IO_IN -.sym 14588 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 14597 i_smi_soe_se$SB_IO_IN -.sym 14609 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 14611 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14617 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14624 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14627 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14628 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14634 tx_fifo.rd_addr_gray_wr[6] -.sym 14637 rx_fifo.wr_addr_gray_rd[0] -.sym 14638 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14641 $PACKER_VCC_NET -.sym 14644 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 14650 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14572 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14573 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 14574 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.sym 14575 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 14576 tx_fifo.rd_addr[1] +.sym 14577 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 14578 tx_fifo.rd_addr[0] +.sym 14579 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 14584 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 14588 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14592 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 14600 tx_fifo.rd_addr[7] +.sym 14601 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 14603 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 14606 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14617 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 14620 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 14621 tx_fifo.wr_addr[5] +.sym 14624 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14626 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 14627 tx_fifo.rd_addr[1] +.sym 14629 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14631 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14632 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 14636 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 14638 smi_ctrl_ins.int_cnt_rx[4] +.sym 14651 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] .sym 14653 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] .sym 14654 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] .sym 14655 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14656 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14657 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14658 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14657 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 14658 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] .sym 14659 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14663 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14667 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14673 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14681 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 14683 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14685 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 14690 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 14695 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14702 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14703 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 14707 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14708 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 14713 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14714 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14718 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14725 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14729 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14660 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 14661 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 14664 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14665 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14668 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 14680 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14682 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14684 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 14689 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14690 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 14691 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14696 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 14701 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14702 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 14713 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14714 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 14715 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14720 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14721 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14726 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 14727 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14728 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14729 r_counter_$glb_clk .sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14731 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 14733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 14734 rx_fifo.wr_addr_gray_rd[0] -.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 14737 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 14738 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 14743 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14745 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 14752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14758 tx_fifo.rd_addr_gray_wr[4] -.sym 14761 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 14762 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14763 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 14765 $PACKER_VCC_NET -.sym 14766 tx_fifo.rd_addr[6] -.sym 14774 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 14776 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14778 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 14779 tx_fifo.rd_addr[6] -.sym 14780 rx_fifo.wr_addr[1] -.sym 14781 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 14783 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14784 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14788 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 14789 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14790 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14794 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 14796 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 14798 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 14807 tx_fifo.wr_addr_gray_rd_r[6] -.sym 14808 tx_fifo.rd_addr[6] -.sym 14811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 14812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 14813 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14814 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14817 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 14818 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 14820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 14825 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14836 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 14837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 14838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14843 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 14847 rx_fifo.wr_addr[1] -.sym 14851 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 14852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14731 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] +.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14733 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 14734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14735 w_tx_fifo_empty +.sym 14736 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 14737 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 14738 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 14742 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 14745 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 14746 rx_fifo.wr_addr[5] +.sym 14749 tx_fifo.wr_addr[9] +.sym 14750 rx_fifo.mem_i.0.1_WDATA +.sym 14751 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 14753 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 14754 rx_fifo.mem_i.0.1_WDATA_2 +.sym 14758 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14759 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 14760 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 14761 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 14765 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 14766 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 14773 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 14774 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14776 smi_ctrl_ins.int_cnt_rx[3] +.sym 14777 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 14778 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 14780 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 14784 tx_fifo.rd_addr[1] +.sym 14785 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 14786 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 14787 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 14788 tx_fifo.rd_addr[2] +.sym 14791 smi_ctrl_ins.int_cnt_rx[4] +.sym 14795 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14813 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 14814 tx_fifo.rd_addr[2] +.sym 14817 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 14818 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 14819 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 14820 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 14823 smi_ctrl_ins.int_cnt_rx[4] +.sym 14824 smi_ctrl_ins.int_cnt_rx[3] +.sym 14831 smi_ctrl_ins.int_cnt_rx[3] +.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 14842 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14844 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 14847 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 14848 tx_fifo.rd_addr[2] +.sym 14849 tx_fifo.rd_addr[1] +.sym 14852 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14854 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14855 smi_ctrl_ins.w_fifo_push_trigger -.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14858 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14859 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14861 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 14866 tx_fifo.wr_addr[8] -.sym 14868 rx_fifo.wr_addr[0] -.sym 14870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 14871 i_rst_b$SB_IO_IN -.sym 14872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 14876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14878 tx_fifo.wr_addr_gray_rd[9] -.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14881 w_rx_fifo_pulled_data[7] -.sym 14882 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 14884 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14895 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 14896 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] -.sym 14897 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] -.sym 14898 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14854 tx_fifo.rd_addr[2] +.sym 14855 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 14856 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 14857 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 14858 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 14859 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 14860 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] +.sym 14861 tx_fifo.rd_addr_gray[1] +.sym 14862 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 14865 w_tx_data_smi[2] +.sym 14868 i_rst_b$SB_IO_IN +.sym 14869 rx_fifo.rd_addr[3] +.sym 14870 rx_fifo.rd_addr[4] +.sym 14871 rx_fifo.mem_i.0.3_WDATA_2 +.sym 14873 rx_fifo.wr_addr[7] +.sym 14874 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 14876 smi_ctrl_ins.int_cnt_rx[3] +.sym 14878 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 14879 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14880 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14881 tx_fifo.rd_addr[8] +.sym 14882 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 14885 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 14886 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 14888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 14896 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14897 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 14898 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] .sym 14899 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14900 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14902 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 14904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 14906 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14908 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] -.sym 14911 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 14912 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 14918 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] -.sym 14920 smi_ctrl_ins.w_fifo_push_trigger -.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 14925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 14926 tx_fifo.rd_addr[6] -.sym 14935 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14937 tx_fifo.rd_addr[6] -.sym 14942 smi_ctrl_ins.w_fifo_push_trigger -.sym 14946 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] -.sym 14947 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] -.sym 14948 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] -.sym 14949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] -.sym 14958 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 14959 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 14960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 14964 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 14965 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 14967 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 14970 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 14971 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 14972 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 14973 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 14901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 14902 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 14903 tx_fifo.rd_addr[1] +.sym 14904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 14906 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14909 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 14911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 14914 rx_fifo.wr_addr_gray_rd[0] +.sym 14917 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 14918 tx_fifo.rd_addr_gray[1] +.sym 14919 tx_fifo.rd_addr[2] +.sym 14922 i_rst_b$SB_IO_IN +.sym 14925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 14926 tx_fifo.rd_addr_gray_wr[1] +.sym 14928 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 14929 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 14934 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 14935 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 14936 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 14937 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 14940 i_rst_b$SB_IO_IN +.sym 14942 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 14949 tx_fifo.rd_addr_gray_wr[1] +.sym 14952 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 14953 tx_fifo.rd_addr[2] +.sym 14955 tx_fifo.rd_addr[1] +.sym 14958 rx_fifo.wr_addr_gray_rd[0] +.sym 14964 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14965 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14966 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 14967 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 14970 tx_fifo.rd_addr_gray[1] .sym 14975 r_counter_$glb_clk -.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14977 tx_fifo.rd_addr_gray_wr_r[8] -.sym 14978 tx_fifo.rd_addr_gray_wr[4] -.sym 14979 tx_fifo.rd_addr_gray_wr[8] -.sym 14980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14981 tx_fifo.rd_addr_gray_wr[7] -.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 14983 tx_fifo.rd_addr_gray_wr[1] -.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14995 smi_ctrl_ins.r_fifo_push -.sym 14996 rx_fifo.wr_addr[9] -.sym 14998 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 15007 smi_ctrl_ins.int_cnt_rx[3] -.sym 15011 smi_ctrl_ins.int_cnt_rx[4] -.sym 15018 tx_fifo.wr_addr_gray_rd[1] -.sym 15020 tx_fifo.wr_addr_gray_rd[3] -.sym 15022 tx_fifo.wr_addr_gray_rd[5] -.sym 15024 tx_fifo.wr_addr_gray_rd[8] -.sym 15025 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 15030 tx_fifo.wr_addr_gray_rd[2] -.sym 15031 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 15032 tx_fifo.wr_addr_gray_rd[7] -.sym 15038 tx_fifo.wr_addr_gray_rd[9] -.sym 15040 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 15046 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 15054 tx_fifo.wr_addr_gray_rd[7] -.sym 15060 tx_fifo.wr_addr_gray_rd[8] -.sym 15066 tx_fifo.wr_addr_gray_rd[2] -.sym 15072 tx_fifo.wr_addr_gray_rd[3] -.sym 15075 tx_fifo.wr_addr_gray_rd[5] -.sym 15081 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 15082 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 15083 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 15084 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 15089 tx_fifo.wr_addr_gray_rd[1] -.sym 15094 tx_fifo.wr_addr_gray_rd[9] -.sym 15098 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 15101 tx_fifo.rd_addr_gray[1] -.sym 15104 tx_fifo.rd_addr_gray[8] -.sym 15105 tx_fifo.rd_addr_gray[5] -.sym 15107 tx_fifo.rd_addr_gray[0] +.sym 14977 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] +.sym 14978 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 14979 tx_fifo.wr_addr_gray_rd[1] +.sym 14980 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 14983 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] +.sym 14984 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] +.sym 14989 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 14993 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 14995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 14998 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 15001 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 15004 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15005 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 15007 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 15008 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 15012 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 15018 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15019 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 15020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 15022 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 15023 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 15025 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 15027 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 15030 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 15031 tx_fifo.wr_addr[1] +.sym 15035 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 15037 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 15038 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 15040 tx_fifo.rd_addr[9] +.sym 15043 tx_fifo.rd_addr[8] +.sym 15051 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 15053 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 15054 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 15057 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 15060 tx_fifo.rd_addr[8] +.sym 15069 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 15070 tx_fifo.rd_addr[8] +.sym 15071 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 15072 tx_fifo.rd_addr[9] +.sym 15075 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15084 tx_fifo.wr_addr[1] +.sym 15088 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 15090 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 15094 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 15095 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 15098 r_counter_$glb_clk +.sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15100 tx_fifo.rd_addr_gray[3] +.sym 15101 tx_fifo.rd_addr[8] +.sym 15102 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 15103 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 15104 tx_fifo.rd_addr_gray[0] +.sym 15105 tx_fifo.rd_addr_gray[8] +.sym 15106 tx_fifo.rd_addr[9] +.sym 15107 tx_fifo.rd_addr_gray[7] +.sym 15108 i_rst_b$SB_IO_IN .sym 15111 i_rst_b$SB_IO_IN -.sym 15112 rx_fifo.rd_addr[5] -.sym 15113 rx_fifo.rd_addr[3] -.sym 15114 tx_fifo.wr_addr_gray_rd[3] -.sym 15115 w_tx_fifo_full -.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 15118 tx_fifo.wr_addr_gray_rd[5] -.sym 15120 tx_fifo.wr_addr_gray_rd[7] -.sym 15121 w_rx_fifo_pulled_data[6] -.sym 15122 tx_fifo.wr_addr_gray_rd[1] -.sym 15123 rx_fifo.rd_addr[1] -.sym 15126 tx_fifo.rd_addr_gray_wr[6] -.sym 15127 rx_fifo.wr_addr_gray_rd[0] -.sym 15128 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 15131 tx_fifo.rd_addr_gray_wr[2] -.sym 15133 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 15147 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 15148 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 15149 tx_fifo.rd_addr[1] -.sym 15154 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 15155 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 15156 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 15159 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 15160 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 15161 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 15162 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15177 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 15180 tx_fifo.rd_addr[1] -.sym 15181 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 15182 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 15183 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 15186 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 15195 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 15200 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 15201 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15204 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 15206 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15212 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 15213 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 15220 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 15112 rx_fifo.rd_addr[0] +.sym 15113 tx_fifo.rd_addr[7] +.sym 15114 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 15118 tx_fifo.rd_addr_gray_wr[0] +.sym 15121 rx_fifo.rd_addr[5] +.sym 15122 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 15123 tx_fifo.wr_addr_gray_rd[1] +.sym 15124 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15130 $PACKER_VCC_NET +.sym 15133 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 15146 tx_fifo.wr_addr_gray[0] +.sym 15147 tx_fifo.wr_addr_gray[7] +.sym 15148 tx_fifo.wr_addr_gray[8] +.sym 15163 tx_fifo.wr_addr_gray_rd[7] +.sym 15164 tx_fifo.wr_addr_gray_rd[0] +.sym 15165 tx_fifo.wr_addr_gray_rd[8] +.sym 15177 tx_fifo.wr_addr_gray[8] +.sym 15182 tx_fifo.wr_addr_gray_rd[8] +.sym 15194 tx_fifo.wr_addr_gray_rd[0] +.sym 15200 tx_fifo.wr_addr_gray_rd[7] +.sym 15212 tx_fifo.wr_addr_gray[7] +.sym 15218 tx_fifo.wr_addr_gray[0] .sym 15221 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 15222 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15229 tx_fifo.rd_addr_gray_wr[9] -.sym 15230 tx_fifo.rd_addr_gray_wr[6] -.sym 15237 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 15238 rx_fifo.wr_addr[3] -.sym 15242 io_pmod[7]$SB_IO_IN -.sym 15244 $PACKER_VCC_NET -.sym 15249 $PACKER_VCC_NET -.sym 15252 rx_fifo.wr_addr[9] +.sym 15224 $PACKER_VCC_NET +.sym 15225 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 15226 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15227 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 15228 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 15230 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15233 w_tx_data_smi[1] +.sym 15241 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 15242 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15251 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] .sym 15253 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 15255 w_rx_fifo_empty -.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15267 smi_ctrl_ins.int_cnt_rx[3] -.sym 15292 i_rst_b$SB_IO_IN -.sym 15293 smi_ctrl_ins.int_cnt_rx[4] -.sym 15309 smi_ctrl_ins.int_cnt_rx[4] -.sym 15310 smi_ctrl_ins.int_cnt_rx[3] -.sym 15312 i_rst_b$SB_IO_IN -.sym 15315 smi_ctrl_ins.int_cnt_rx[3] -.sym 15327 smi_ctrl_ins.int_cnt_rx[3] -.sym 15330 smi_ctrl_ins.int_cnt_rx[4] -.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15353 rx_fifo.wr_addr_gray_rd_r[0] -.sym 15359 tx_fifo.rd_addr_gray_wr[9] -.sym 15369 spi_if_ins.spi.r2_rx_done -.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15400 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 15405 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15415 w_rx_fifo_empty -.sym 15445 w_rx_fifo_empty -.sym 15466 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15254 spi_if_ins.w_rx_data[4] +.sym 15257 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15258 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15270 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 15275 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15277 w_tx_fifo_full +.sym 15279 w_rx_fifo_empty +.sym 15284 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 15285 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15286 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 15293 o_led0_SB_LUT4_I1_O[1] +.sym 15299 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 15309 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 15312 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15316 w_tx_fifo_full +.sym 15330 w_rx_fifo_empty +.sym 15334 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15335 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 15343 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15344 r_counter_$glb_clk +.sym 15345 o_led0_SB_LUT4_I1_O[1] +.sym 15346 w_load +.sym 15347 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 15348 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 15349 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15350 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 15351 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 15352 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 15353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 15361 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15362 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 15367 $PACKER_VCC_NET +.sym 15369 io_pmod[6]$SB_IO_IN +.sym 15370 w_rx_data[0] +.sym 15372 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15375 spi_if_ins.spi.r_tx_byte[0] +.sym 15377 w_tx_data_smi[0] +.sym 15379 w_load +.sym 15388 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 15389 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15396 w_rx_data[0] +.sym 15397 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 15400 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15402 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15405 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 15406 i_rst_b$SB_IO_IN +.sym 15411 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 15421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 15423 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 15426 i_rst_b$SB_IO_IN +.sym 15427 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15456 w_rx_data[0] +.sym 15463 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15464 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 15465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15466 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E .sym 15467 r_counter_$glb_clk -.sym 15468 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 15471 int_miso -.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15487 rx_fifo.wr_addr[8] -.sym 15488 rx_fifo.wr_addr[9] -.sym 15493 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15495 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15499 i_ss$SB_IO_IN -.sym 15503 $PACKER_VCC_NET -.sym 15510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 15512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 15520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15522 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 15527 $PACKER_VCC_NET -.sym 15528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15535 $PACKER_VCC_NET -.sym 15539 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15542 $nextpnr_ICESTORM_LC_9$O -.sym 15544 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15548 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 15550 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15551 $PACKER_VCC_NET -.sym 15555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15557 $PACKER_VCC_NET -.sym 15558 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 15561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 15562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 15563 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 15564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15570 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15573 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15576 $PACKER_VCC_NET -.sym 15579 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15585 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15586 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15588 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15589 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15468 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15470 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +.sym 15471 w_ioc[2] +.sym 15472 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 15474 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] +.sym 15476 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 15481 i_glob_clock$SB_IO_IN +.sym 15482 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 15486 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 15493 spi_if_ins.spi.r_tx_byte[1] +.sym 15494 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 15495 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15496 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15497 spi_if_ins.r_tx_byte[2] +.sym 15499 spi_if_ins.r_tx_byte[3] +.sym 15502 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15503 w_rx_data[4] +.sym 15504 spi_if_ins.r_tx_byte[0] +.sym 15510 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15511 spi_if_ins.state_if[0] +.sym 15513 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15515 spi_if_ins.state_if[1] +.sym 15517 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15518 spi_if_ins.w_rx_data[5] +.sym 15521 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15524 spi_if_ins.w_rx_data[4] +.sym 15525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15528 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15534 i_rst_b$SB_IO_IN +.sym 15537 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15544 spi_if_ins.state_if[0] +.sym 15546 spi_if_ins.state_if[1] +.sym 15551 spi_if_ins.w_rx_data[4] +.sym 15555 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15556 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15557 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15561 spi_if_ins.state_if[1] +.sym 15562 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15563 spi_if_ins.state_if[0] +.sym 15570 spi_if_ins.w_rx_data[5] +.sym 15573 i_rst_b$SB_IO_IN +.sym 15574 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15576 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15581 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15585 spi_if_ins.state_if[1] +.sym 15587 spi_if_ins.state_if[0] +.sym 15588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15589 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 15590 r_counter_$glb_clk -.sym 15591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15592 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15596 w_fetch -.sym 15597 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15598 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15602 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 15608 $PACKER_VCC_NET -.sym 15614 i_rst_b_SB_LUT4_I3_O -.sym 15615 int_miso -.sym 15619 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 15623 w_tx_data_io[7] -.sym 15627 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 15634 spi_if_ins.spi.r_tx_byte[0] -.sym 15635 spi_if_ins.spi.r_tx_byte[2] -.sym 15637 spi_if_ins.spi.r_tx_byte[5] -.sym 15640 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 15644 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15645 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15646 spi_if_ins.spi.r_tx_byte[6] -.sym 15647 spi_if_ins.spi.r_tx_byte[3] -.sym 15648 spi_if_ins.spi.r_tx_byte[1] -.sym 15650 spi_if_ins.spi.r_tx_byte[4] -.sym 15651 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 15653 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15654 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 15655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15656 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15658 spi_if_ins.r_tx_byte[7] -.sym 15661 spi_if_ins.spi.r_tx_byte[7] -.sym 15662 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15664 spi_if_ins.r_tx_byte[4] -.sym 15666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15667 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15668 spi_if_ins.spi.r_tx_byte[6] -.sym 15669 spi_if_ins.spi.r_tx_byte[4] -.sym 15673 spi_if_ins.r_tx_byte[4] -.sym 15679 spi_if_ins.spi.r_tx_byte[0] -.sym 15680 spi_if_ins.spi.r_tx_byte[1] -.sym 15681 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15684 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 15686 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15687 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15692 spi_if_ins.r_tx_byte[7] -.sym 15696 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15697 spi_if_ins.spi.r_tx_byte[2] -.sym 15698 spi_if_ins.spi.r_tx_byte[3] -.sym 15702 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 15704 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 15708 spi_if_ins.spi.r_tx_byte[7] -.sym 15709 spi_if_ins.spi.r_tx_byte[5] -.sym 15710 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15711 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15712 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15592 spi_if_ins.spi.r_tx_byte[2] +.sym 15593 spi_if_ins.spi.r_tx_byte[5] +.sym 15594 spi_if_ins.spi.r_tx_byte[0] +.sym 15595 spi_if_ins.spi.r_tx_byte[4] +.sym 15596 spi_if_ins.spi.r_tx_byte[3] +.sym 15597 spi_if_ins.spi.r_tx_byte[6] +.sym 15598 spi_if_ins.spi.r_tx_byte[1] +.sym 15599 spi_if_ins.spi.r_tx_byte[7] +.sym 15600 spi_if_ins.w_rx_data[5] +.sym 15604 i_rst_b$SB_IO_IN +.sym 15608 w_rx_data[4] +.sym 15610 w_fetch +.sym 15613 rx_fifo.wr_addr[8] +.sym 15616 w_ioc[2] +.sym 15617 w_load +.sym 15618 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15621 w_rx_data[5] +.sym 15622 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15625 w_rx_data[7] +.sym 15627 $PACKER_VCC_NET +.sym 15633 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15635 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15636 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15640 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15641 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 15642 spi_if_ins.state_if[0] +.sym 15644 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 15646 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15648 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15654 spi_if_ins.state_if[1] +.sym 15656 i_rst_b$SB_IO_IN +.sym 15659 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15660 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 15662 i_rst_b$SB_IO_IN +.sym 15664 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15666 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15667 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15668 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15672 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 15678 spi_if_ins.state_if[0] +.sym 15679 spi_if_ins.state_if[1] +.sym 15680 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15686 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15690 i_rst_b$SB_IO_IN +.sym 15691 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15692 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15696 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 15698 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15699 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15702 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15703 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 15704 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 15705 i_rst_b$SB_IO_IN +.sym 15709 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 15712 spi_if_ins.state_if_SB_DFFESR_Q_E .sym 15713 r_counter_$glb_clk -.sym 15714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15715 w_cs[0] -.sym 15718 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15720 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15721 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 15722 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15728 $PACKER_VCC_NET -.sym 15729 o_led1$SB_IO_OUT -.sym 15734 i_rst_b$SB_IO_IN -.sym 15741 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 15743 spi_if_ins.r_tx_byte[7] -.sym 15747 spi_if_ins.r_tx_byte[6] -.sym 15757 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15758 w_cs[1] -.sym 15760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15763 w_cs[3] -.sym 15767 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15768 w_cs[2] -.sym 15769 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15772 w_cs[0] -.sym 15773 spi_if_ins.r_tx_byte[6] -.sym 15776 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15778 spi_if_ins.r_tx_byte[1] -.sym 15780 spi_if_ins.r_tx_byte[3] -.sym 15782 spi_if_ins.r_tx_byte[0] -.sym 15784 i_rst_b$SB_IO_IN -.sym 15786 spi_if_ins.r_tx_byte[5] -.sym 15787 spi_if_ins.r_tx_byte[2] -.sym 15789 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15790 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15792 i_rst_b$SB_IO_IN -.sym 15795 spi_if_ins.r_tx_byte[0] -.sym 15801 spi_if_ins.r_tx_byte[2] -.sym 15807 w_cs[2] -.sym 15808 w_cs[1] -.sym 15809 w_cs[3] -.sym 15810 w_cs[0] -.sym 15814 spi_if_ins.r_tx_byte[5] -.sym 15819 spi_if_ins.r_tx_byte[6] -.sym 15826 spi_if_ins.r_tx_byte[3] -.sym 15834 spi_if_ins.r_tx_byte[1] -.sym 15835 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15714 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15715 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 15716 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 15717 io_ctrl_ins.rf_pin_state[2] +.sym 15718 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] +.sym 15719 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 15720 io_ctrl_ins.rf_pin_state[7] +.sym 15722 io_ctrl_ins.rf_pin_state[5] +.sym 15731 w_rx_data[1] +.sym 15737 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15739 spi_if_ins.w_rx_data[4] +.sym 15741 spi_if_ins.w_rx_data[3] +.sym 15742 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15746 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 15747 spi_if_ins.w_rx_data[6] +.sym 15750 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 15758 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 15759 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 15763 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 15764 w_fetch +.sym 15769 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15771 w_cs[2] +.sym 15774 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15777 w_load +.sym 15778 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15782 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15783 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.sym 15786 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15787 o_led1_SB_LUT4_I1_I2[1] +.sym 15795 w_load +.sym 15796 o_led1_SB_LUT4_I1_I2[1] +.sym 15797 w_fetch +.sym 15798 w_cs[2] +.sym 15807 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15808 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 15809 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15810 w_cs[2] +.sym 15813 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15814 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15815 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15816 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 15819 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15820 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15821 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15825 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15828 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 15835 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E .sym 15836 r_counter_$glb_clk -.sym 15837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15838 w_load -.sym 15839 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 15842 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 15843 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 15844 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 15845 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 15850 w_rx_data[2] -.sym 15852 w_rx_data[1] -.sym 15853 i_rst_b$SB_IO_IN -.sym 15855 spi_if_ins.w_rx_data[6] -.sym 15856 spi_if_ins.w_rx_data[0] -.sym 15857 w_cs[0] -.sym 15859 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15837 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15838 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 15839 w_tx_data_io[2] +.sym 15840 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15841 o_led1_SB_LUT4_I1_I3[3] +.sym 15842 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] +.sym 15843 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 15844 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15845 o_led1_SB_LUT4_I1_I2[1] +.sym 15850 o_led1_SB_LUT4_I1_O[0] +.sym 15852 o_led0_SB_LUT4_I1_O[1] +.sym 15854 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 15856 i_rst_b$SB_IO_IN +.sym 15857 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15859 w_cs[2] .sym 15860 spi_if_ins.w_rx_data[5] -.sym 15865 w_fetch -.sym 15866 w_rx_data[7] -.sym 15868 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15871 w_load -.sym 15872 w_rx_data[7] -.sym 15879 w_tx_data_io[0] -.sym 15884 w_rx_data[2] -.sym 15887 w_cs[0] -.sym 15888 w_rx_data[0] -.sym 15890 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 15893 w_tx_data_io[7] -.sym 15895 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 15897 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 15898 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15899 w_cs[2] -.sym 15903 w_tx_data_smi[0] -.sym 15905 w_cs[1] -.sym 15910 w_cs[3] -.sym 15912 w_cs[2] -.sym 15913 w_cs[1] -.sym 15914 w_cs[3] -.sym 15915 w_cs[0] -.sym 15918 w_cs[0] -.sym 15919 w_cs[2] -.sym 15920 w_cs[1] -.sym 15921 w_cs[3] -.sym 15927 w_rx_data[2] -.sym 15930 w_cs[1] -.sym 15931 w_cs[3] -.sym 15932 w_cs[0] -.sym 15933 w_cs[2] -.sym 15936 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 15937 w_tx_data_smi[0] -.sym 15938 w_tx_data_io[0] -.sym 15939 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15942 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15944 w_tx_data_io[7] -.sym 15945 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 15948 w_cs[2] -.sym 15949 w_cs[1] -.sym 15950 w_cs[3] -.sym 15951 w_cs[0] -.sym 15957 w_rx_data[0] -.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 15861 spi_if_ins.w_rx_data[6] +.sym 15863 o_led1_SB_LUT4_I1_I3[1] +.sym 15865 w_tx_data_smi[0] +.sym 15868 o_led1_SB_LUT4_I1_I2[2] +.sym 15869 w_cs[1] +.sym 15871 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 15872 w_load +.sym 15873 w_tx_data_io[2] +.sym 15879 w_rx_data[2] +.sym 15881 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 15885 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.sym 15886 w_fetch +.sym 15887 w_load +.sym 15890 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15892 i_rst_b$SB_IO_IN +.sym 15894 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15897 w_cs[0] +.sym 15905 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15909 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15914 w_rx_data[2] +.sym 15918 w_fetch +.sym 15919 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.sym 15921 w_cs[0] +.sym 15924 i_rst_b$SB_IO_IN +.sym 15927 w_fetch +.sym 15930 w_fetch +.sym 15931 w_cs[0] +.sym 15932 w_load +.sym 15943 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15944 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15945 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15948 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15949 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15950 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15951 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15954 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 15955 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 15956 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 15957 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15958 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 15959 r_counter_$glb_clk -.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15961 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 15963 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 15964 i_button_SB_LUT4_I0_O[1] -.sym 15965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 15966 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] -.sym 15967 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 15968 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 15974 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 15979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15980 w_rx_data[2] -.sym 15981 i_glob_clock$SB_IO_IN -.sym 15982 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 15983 w_cs[1] -.sym 15984 w_rx_data[0] -.sym 15987 w_rx_data[3] -.sym 15989 w_ioc[1] -.sym 15991 w_rx_data[5] -.sym 15992 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 15993 w_rx_data[4] -.sym 15996 w_tx_data_io[5] -.sym 16002 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 16003 w_tx_data_io[5] -.sym 16005 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16006 r_tx_data[5] -.sym 16008 r_tx_data[3] -.sym 16010 r_tx_data[1] -.sym 16011 r_tx_data[4] -.sym 16012 r_tx_data[7] -.sym 16013 r_tx_data[6] -.sym 16017 r_tx_data[0] -.sym 16020 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 16035 r_tx_data[3] -.sym 16042 r_tx_data[4] -.sym 16048 r_tx_data[7] -.sym 16055 r_tx_data[1] -.sym 16059 r_tx_data[6] -.sym 16066 r_tx_data[0] -.sym 16071 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 16072 w_tx_data_io[5] -.sym 16074 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16080 r_tx_data[5] -.sym 16081 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 15961 w_ioc[3] +.sym 15962 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 15963 w_cs[0] +.sym 15964 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15965 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 15966 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15968 w_ioc[4] +.sym 15976 w_rx_data[6] +.sym 15978 w_rx_data[1] +.sym 15980 w_rx_data[3] +.sym 15981 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15983 w_rx_data[2] +.sym 15987 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 15988 spi_if_ins.r_tx_byte[2] +.sym 15989 spi_if_ins.w_rx_data[6] +.sym 15990 spi_if_ins.r_tx_byte[3] +.sym 15992 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15994 spi_if_ins.w_rx_data[5] +.sym 15996 spi_if_ins.r_tx_byte[0] +.sym 16002 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 16004 w_cs[3] +.sym 16009 o_led1_SB_LUT4_I1_I2[1] +.sym 16010 w_rx_data[4] +.sym 16011 w_cs[2] +.sym 16012 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 16015 w_rx_data[1] +.sym 16017 o_led1_SB_LUT4_I1_I2[2] +.sym 16020 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 16021 w_cs[1] +.sym 16028 w_cs[0] +.sym 16029 w_cs[1] +.sym 16035 o_led1_SB_LUT4_I1_I2[2] +.sym 16036 o_led1_SB_LUT4_I1_I2[1] +.sym 16037 w_cs[1] +.sym 16038 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 16042 w_rx_data[1] +.sym 16047 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 16059 w_cs[3] +.sym 16060 w_cs[1] +.sym 16061 w_cs[2] +.sym 16062 w_cs[0] +.sym 16074 w_rx_data[4] +.sym 16081 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 16082 r_counter_$glb_clk -.sym 16084 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 16085 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 16086 io_ctrl_ins.pmod_dir_state[7] -.sym 16087 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] -.sym 16089 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 16090 io_ctrl_ins.pmod_dir_state[6] -.sym 16091 io_ctrl_ins.pmod_dir_state[4] -.sym 16095 i_rst_b$SB_IO_IN -.sym 16096 w_tx_data_io[0] -.sym 16097 i_rst_b$SB_IO_IN -.sym 16098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 16099 i_button_SB_LUT4_I0_O[1] -.sym 16106 w_tx_data_io[1] -.sym 16110 w_tx_data_io[7] -.sym 16125 w_cs[0] -.sym 16126 w_rx_data[1] -.sym 16128 w_rx_data[2] -.sym 16130 w_rx_data[6] -.sym 16135 w_fetch -.sym 16138 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] -.sym 16144 w_rx_data[7] -.sym 16147 w_rx_data[3] -.sym 16151 w_rx_data[5] -.sym 16152 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 16153 w_rx_data[4] -.sym 16159 w_rx_data[6] -.sym 16165 w_rx_data[3] -.sym 16171 w_rx_data[2] -.sym 16178 w_rx_data[5] -.sym 16185 w_rx_data[7] -.sym 16188 w_rx_data[1] -.sym 16194 w_cs[0] -.sym 16196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] -.sym 16197 w_fetch -.sym 16200 w_rx_data[4] -.sym 16204 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 16084 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16085 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 16086 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 16087 w_cs[1] +.sym 16088 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16089 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16096 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 16097 o_led1$SB_IO_OUT +.sym 16100 io_ctrl_ins.pmod_dir_state[1] +.sym 16103 i_rst_b$SB_IO_IN +.sym 16106 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 16111 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16113 i_glob_clock$SB_IO_IN +.sym 16129 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 16130 spi_if_ins.w_rx_data[5] +.sym 16131 w_tx_data_io[1] +.sym 16134 w_tx_data_io[7] +.sym 16137 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 16138 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 16139 spi_if_ins.w_rx_data[6] +.sym 16140 w_tx_data_io[5] +.sym 16142 w_tx_data_smi[1] +.sym 16143 w_tx_data_io[2] +.sym 16144 w_tx_data_smi[2] +.sym 16145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16149 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16152 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 16153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16158 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16159 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16160 w_tx_data_io[5] +.sym 16164 spi_if_ins.w_rx_data[5] +.sym 16166 spi_if_ins.w_rx_data[6] +.sym 16171 spi_if_ins.w_rx_data[5] +.sym 16173 spi_if_ins.w_rx_data[6] +.sym 16182 w_tx_data_io[7] +.sym 16183 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16185 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16188 w_tx_data_smi[1] +.sym 16189 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 16190 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16191 w_tx_data_io[1] +.sym 16200 w_tx_data_smi[2] +.sym 16201 w_tx_data_io[2] +.sym 16202 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 16203 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16204 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 16205 r_counter_$glb_clk -.sym 16206 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16207 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 16208 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 16209 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 16212 w_tx_data_io[5] -.sym 16213 i_button_SB_LUT4_I0_O[2] -.sym 16214 w_tx_data_io[7] -.sym 16219 w_cs[1] +.sym 16206 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 16207 spi_if_ins.r_tx_byte[5] +.sym 16208 spi_if_ins.r_tx_byte[2] +.sym 16209 spi_if_ins.r_tx_byte[3] +.sym 16210 spi_if_ins.r_tx_byte[6] +.sym 16211 spi_if_ins.r_tx_byte[4] +.sym 16212 spi_if_ins.r_tx_byte[0] +.sym 16213 spi_if_ins.r_tx_byte[7] +.sym 16214 spi_if_ins.r_tx_byte[1] .sym 16221 i_rst_b$SB_IO_IN -.sym 16226 w_rx_data[6] -.sym 16232 i_config[3]$SB_IO_IN -.sym 16238 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 16262 w_rx_data[0] -.sym 16266 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 16318 w_rx_data[0] -.sym 16327 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 16328 r_counter_$glb_clk -.sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16334 io_ctrl_ins.pmod_dir_state[5] -.sym 16354 i_button$SB_IO_IN -.sym 16361 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 16371 i_glob_clock$SB_IO_IN -.sym 16400 r_counter -.sym 16437 r_counter +.sym 16222 o_rx_h_tx_l_b$SB_IO_OUT +.sym 16223 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 16224 o_rx_h_tx_l$SB_IO_OUT +.sym 16228 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 16248 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16249 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 16251 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 16252 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 16253 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 16255 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 16256 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 16257 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 16259 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 16260 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16261 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16263 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 16266 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 16268 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 16271 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16272 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 16273 i_glob_clock$SB_IO_IN +.sym 16276 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 16287 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16288 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 16289 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 16290 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 16293 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16294 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 16296 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 16300 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 16301 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 16302 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16305 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 16306 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16307 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16308 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 16317 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 16318 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 16319 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16320 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16323 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 16325 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 16326 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 16327 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 16328 i_glob_clock$SB_IO_IN +.sym 16343 spi_if_ins.r_tx_byte[7] +.sym 16344 o_tr_vc1$SB_IO_OUT +.sym 16345 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 16371 r_counter +.sym 16380 i_glob_clock$SB_IO_IN +.sym 16393 i_button$SB_IO_IN +.sym 16395 i_config[3]$SB_IO_IN +.sym 16406 r_counter +.sym 16429 i_config[3]$SB_IO_IN +.sym 16437 i_button$SB_IO_IN .sym 16451 i_glob_clock$SB_IO_IN .sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN -.sym 16479 w_rx_data[5] .sym 16497 r_counter -.sym 16512 r_counter -.sym 16554 tx_fifo.wr_addr_gray_rd[6] -.sym 16560 tx_fifo.wr_addr_gray_rd[0] -.sym 16585 i_smi_soe_se$SB_IO_IN -.sym 16586 $PACKER_VCC_NET -.sym 16587 w_smi_data_input[7] -.sym 16596 i_smi_soe_se$SB_IO_IN -.sym 16599 i_smi_swe_srw$SB_IO_IN -.sym 16600 tx_fifo.wr_addr_gray_rd[4] -.sym 16606 i_rst_b$SB_IO_IN -.sym 16612 tx_fifo.wr_addr_gray[4] -.sym 16618 tx_fifo.wr_addr_gray_rd[0] -.sym 16620 tx_fifo.wr_addr_gray_rd[6] -.sym 16635 tx_fifo.wr_addr_gray_rd[6] -.sym 16648 tx_fifo.wr_addr_gray_rd[0] -.sym 16652 i_smi_swe_srw$SB_IO_IN -.sym 16654 i_rst_b$SB_IO_IN -.sym 16658 tx_fifo.wr_addr_gray[4] -.sym 16667 tx_fifo.wr_addr_gray_rd[4] -.sym 16670 i_smi_soe_se$SB_IO_IN -.sym 16671 i_rst_b$SB_IO_IN -.sym 16675 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 16681 tx_fifo.wr_addr_gray[0] -.sym 16682 tx_fifo.wr_addr_gray[4] -.sym 16683 tx_fifo.wr_addr[6] -.sym 16684 tx_fifo.wr_addr[7] -.sym 16685 tx_fifo.wr_addr[4] -.sym 16686 tx_fifo.wr_addr[3] -.sym 16687 tx_fifo.wr_addr[5] -.sym 16688 tx_fifo.wr_addr_gray[6] -.sym 16703 smi_ctrl_ins.swe_and_reset -.sym 16704 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 16723 smi_ctrl_ins.swe_and_reset -.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 16743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16751 w_smi_data_output[4] -.sym 16776 tx_fifo.wr_addr[1] -.sym 16777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16778 tx_fifo.wr_addr[4] -.sym 16779 tx_fifo.wr_addr[3] -.sym 16780 tx_fifo.wr_addr[0] -.sym 16784 tx_fifo.wr_addr[6] -.sym 16785 tx_fifo.wr_addr[7] -.sym 16788 tx_fifo.wr_addr[5] -.sym 16790 $nextpnr_ICESTORM_LC_3$O -.sym 16793 tx_fifo.wr_addr[0] -.sym 16796 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 16798 tx_fifo.wr_addr[1] -.sym 16800 tx_fifo.wr_addr[0] -.sym 16802 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 16808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16811 tx_fifo.wr_addr[3] -.sym 16812 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16814 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 16817 tx_fifo.wr_addr[4] -.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16820 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16823 tx_fifo.wr_addr[5] -.sym 16824 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 16826 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 16828 tx_fifo.wr_addr[6] -.sym 16830 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16832 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16834 tx_fifo.wr_addr[7] -.sym 16836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 16841 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 16842 tx_fifo.wr_addr[1] -.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16844 tx_fifo.wr_addr[8] -.sym 16845 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 16846 tx_fifo.wr_addr[0] -.sym 16847 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 16853 tx_fifo.wr_addr[5] -.sym 16865 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 16867 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 16875 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 16876 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 16882 tx_fifo.wr_addr[9] -.sym 16883 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 16884 tx_fifo.rd_addr_gray_wr[6] -.sym 16885 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16886 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 16888 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16895 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 16896 rx_fifo.wr_addr_gray[0] -.sym 16903 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16907 tx_fifo.rd_addr_gray_wr[4] -.sym 16909 tx_fifo.wr_addr[8] -.sym 16910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 16913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 16915 tx_fifo.wr_addr[8] -.sym 16917 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16920 tx_fifo.wr_addr[9] -.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 16929 tx_fifo.rd_addr_gray_wr[6] -.sym 16933 rx_fifo.wr_addr_gray[0] -.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 16940 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 16944 tx_fifo.rd_addr_gray_wr[4] -.sym 16950 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16952 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16953 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 16961 r_counter_$glb_clk -.sym 16963 tx_fifo.wr_addr_gray[8] -.sym 16964 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 16965 tx_fifo.wr_addr_gray[2] -.sym 16966 tx_fifo.wr_addr_gray[1] -.sym 16967 tx_fifo.wr_addr_gray[7] -.sym 16968 tx_fifo.wr_addr_gray[3] -.sym 16970 tx_fifo.wr_addr_gray[5] -.sym 16977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16979 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16980 rx_fifo.mem_i.0.1_WDATA_3 -.sym 16981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 16986 tx_fifo.wr_addr[9] -.sym 16988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16989 tx_fifo.rd_addr[1] -.sym 16990 o_led1$SB_IO_OUT -.sym 16993 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 16998 o_led1$SB_IO_OUT -.sym 17004 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 17005 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 17008 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 17009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 17011 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 17012 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17013 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 17014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 17015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 17016 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 17019 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 17020 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 17022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17024 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 17025 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 17026 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 17027 w_smi_data_input[7] -.sym 17029 smi_ctrl_ins.swe_and_reset -.sym 17030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17037 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 17038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 17040 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 17045 w_smi_data_input[7] -.sym 17050 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 17052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 17061 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 17063 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 17064 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17067 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 17068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17069 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 17070 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 17079 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 17080 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 17081 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 17082 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 17084 smi_ctrl_ins.swe_and_reset -.sym 17085 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 17086 tx_fifo.wr_addr_gray_rd[1] -.sym 17087 tx_fifo.wr_addr_gray_rd[3] -.sym 17088 tx_fifo.wr_addr_gray_rd[2] -.sym 17089 tx_fifo.wr_addr_gray_rd[8] -.sym 17092 tx_fifo.wr_addr_gray_rd[5] -.sym 17093 tx_fifo.wr_addr_gray_rd[7] -.sym 17098 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 17102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17112 o_led1$SB_IO_OUT -.sym 17115 smi_ctrl_ins.swe_and_reset -.sym 17129 tx_fifo.rd_addr_gray_wr[8] -.sym 17131 tx_fifo.rd_addr_gray[8] -.sym 17136 tx_fifo.rd_addr_gray[1] -.sym 17141 tx_fifo.rd_addr_gray_wr[1] -.sym 17145 tx_fifo.rd_addr_gray[4] -.sym 17147 tx_fifo.rd_addr_gray[7] -.sym 17154 tx_fifo.rd_addr_gray_wr[2] -.sym 17155 tx_fifo.rd_addr_gray_wr[7] -.sym 17160 tx_fifo.rd_addr_gray_wr[8] -.sym 17169 tx_fifo.rd_addr_gray[4] -.sym 17172 tx_fifo.rd_addr_gray[8] -.sym 17181 tx_fifo.rd_addr_gray_wr[2] -.sym 17184 tx_fifo.rd_addr_gray[7] -.sym 17192 tx_fifo.rd_addr_gray_wr[1] -.sym 17198 tx_fifo.rd_addr_gray[1] -.sym 17204 tx_fifo.rd_addr_gray_wr[7] -.sym 17207 r_counter_$glb_clk -.sym 17209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17214 tx_fifo.rd_addr_gray_wr[0] -.sym 17221 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17223 w_rx_fifo_pulled_data[4] -.sym 17229 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 17232 rx_fifo.wr_addr[9] -.sym 17240 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 17242 rx_fifo.rd_addr[8] -.sym 17244 o_led1$SB_IO_OUT -.sym 17261 tx_fifo.rd_addr[1] -.sym 17263 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 17264 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 17265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 16515 r_counter +.sym 16523 i_rst_b$SB_IO_IN +.sym 16554 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 16555 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 16556 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16557 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16558 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 16559 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16560 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 16564 tx_fifo.rd_addr[1] +.sym 16567 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16585 i_smi_swe_srw$SB_IO_IN +.sym 16599 tx_fifo.rd_addr[1] +.sym 16601 tx_fifo.rd_addr[0] +.sym 16602 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 16607 tx_fifo.rd_addr[7] +.sym 16609 tx_fifo.rd_addr[0] +.sym 16615 tx_fifo.rd_addr[2] +.sym 16616 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 16620 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 16621 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 16627 $nextpnr_ICESTORM_LC_6$O +.sym 16629 tx_fifo.rd_addr[0] +.sym 16633 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16635 tx_fifo.rd_addr[1] +.sym 16637 tx_fifo.rd_addr[0] +.sym 16639 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 16642 tx_fifo.rd_addr[2] +.sym 16643 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16645 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 16648 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 16649 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 16651 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 16654 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 16655 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 16657 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16660 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 16661 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 16663 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16665 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 16667 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16672 tx_fifo.rd_addr[7] +.sym 16673 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16681 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 16682 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16683 tx_fifo.wr_addr[1] +.sym 16684 tx_fifo.wr_addr[3] +.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16686 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 16687 tx_fifo.wr_addr[4] +.sym 16688 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 16697 w_rx_fifo_pulled_data[22] +.sym 16698 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 16700 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 16702 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 16707 $PACKER_VCC_NET +.sym 16710 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 16712 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16715 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 16721 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 16723 w_smi_data_direction +.sym 16728 $PACKER_VCC_NET +.sym 16729 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 16730 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16731 tx_fifo.rd_addr[9] +.sym 16735 tx_fifo.rd_addr[2] +.sym 16736 w_smi_data_output[4] +.sym 16740 tx_fifo.rd_addr_gray_wr_r[8] +.sym 16741 tx_fifo.wr_addr[7] +.sym 16743 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 16744 tx_fifo.wr_addr[8] +.sym 16747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16750 $PACKER_VCC_NET +.sym 16753 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16760 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 16761 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16762 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 16764 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 16767 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16768 tx_fifo.rd_addr[8] +.sym 16769 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 16770 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16774 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 16776 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 16787 tx_fifo.rd_addr[9] +.sym 16788 tx_fifo.rd_addr[0] +.sym 16790 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 16792 tx_fifo.rd_addr[8] +.sym 16794 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16798 tx_fifo.rd_addr[9] +.sym 16800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 16803 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 16805 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 16810 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 16812 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 16817 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16830 tx_fifo.rd_addr[0] +.sym 16836 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 16837 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 16838 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16841 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 16845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 16852 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 16853 tx_fifo.rd_addr[7] +.sym 16856 tx_fifo.rd_addr[8] +.sym 16857 rx_fifo.mem_i.0.1_WDATA_1 +.sym 16860 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 16861 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16864 tx_fifo.wr_addr[6] +.sym 16865 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 16867 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 16868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16870 $PACKER_VCC_NET +.sym 16871 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16874 rx_fifo.wr_addr[9] +.sym 16875 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 16881 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 16882 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 16883 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.sym 16884 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 16886 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 16887 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 16890 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 16891 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 16892 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 16893 tx_fifo.rd_addr[1] +.sym 16894 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 16895 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 16896 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16897 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 16899 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 16900 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 16901 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 16902 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 16903 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 16905 tx_fifo.rd_addr_gray_wr_r[8] +.sym 16907 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 16908 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 16909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16911 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 16912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16914 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 16915 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 16916 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 16917 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 16920 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 16921 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16922 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 16923 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.sym 16926 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 16927 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 16928 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 16929 tx_fifo.rd_addr[1] +.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16933 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 16934 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 16935 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 16938 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 16939 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 16940 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 16941 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 16944 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 16946 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 16947 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 16951 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 16952 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16953 tx_fifo.rd_addr_gray_wr_r[8] +.sym 16956 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 16957 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 16961 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16962 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16963 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 16964 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] +.sym 16965 tx_fifo.wr_addr[7] +.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 16967 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] +.sym 16968 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 16969 tx_fifo.wr_addr[6] +.sym 16970 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 16974 spi_if_ins.r_tx_byte[5] +.sym 16975 rx_fifo.wr_addr[7] +.sym 16976 tx_fifo.wr_addr[5] +.sym 16977 rx_fifo.wr_addr[1] +.sym 16985 w_tx_fifo_empty +.sym 16986 rx_fifo.mem_i.0.3_WDATA_3 +.sym 16987 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 16992 w_tx_fifo_empty +.sym 16994 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 16995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 17004 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] +.sym 17005 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] +.sym 17006 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 17008 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 17009 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 17010 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] +.sym 17011 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 17012 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] +.sym 17013 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 17014 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 17015 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 17017 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 17018 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 17019 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 17021 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 17022 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 17023 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 17026 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] +.sym 17030 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 17033 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 17037 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 17043 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] +.sym 17044 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] +.sym 17045 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] +.sym 17046 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] +.sym 17051 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 17055 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 17056 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] +.sym 17057 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 17064 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 17067 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 17068 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 17069 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 17070 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 17073 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 17074 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 17075 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 17076 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 17082 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 17083 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 17084 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17085 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 17086 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 17087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 17088 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17089 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 17090 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 17091 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 17092 tx_fifo.rd_addr_gray_wr[0] +.sym 17093 tx_fifo.rd_addr_gray_wr[7] +.sym 17096 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 17099 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 17102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17103 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 17104 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 17110 o_smi_read_req$SB_IO_OUT +.sym 17111 tx_fifo.rd_addr[9] +.sym 17112 $PACKER_VCC_NET +.sym 17113 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 17121 w_smi_data_direction +.sym 17127 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 17128 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 17129 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 17130 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 17131 tx_fifo.rd_addr[7] +.sym 17132 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 17133 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17135 w_tx_fifo_pull +.sym 17137 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 17138 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 17139 tx_fifo.wr_addr_gray[1] +.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 17141 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17142 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 17143 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 17145 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 17146 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 17147 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 17150 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] +.sym 17151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 17152 w_tx_fifo_empty +.sym 17154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 17155 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] +.sym 17160 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 17161 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 17162 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 17163 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 17166 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17167 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 17169 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 17173 tx_fifo.wr_addr_gray[1] +.sym 17178 w_tx_fifo_pull +.sym 17179 w_tx_fifo_empty +.sym 17180 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 17181 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 17186 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 17187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 17196 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 17197 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] +.sym 17198 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 17199 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] +.sym 17202 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 17203 tx_fifo.rd_addr[7] +.sym 17204 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 17205 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 17207 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17210 spi_if_ins.spi.r_rx_bit_count[1] +.sym 17211 spi_if_ins.spi.r_rx_bit_count[2] +.sym 17212 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 17214 spi_if_ins.spi.r_rx_bit_count[0] +.sym 17215 o_smi_read_req$SB_IO_OUT +.sym 17217 w_tx_fifo_pull +.sym 17222 o_miso_$_TBUF__Y_E +.sym 17225 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 17228 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 17230 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 17232 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17233 w_load +.sym 17237 tx_fifo.rd_addr_gray_wr_r[8] +.sym 17239 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17250 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 17252 w_tx_fifo_pull +.sym 17253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 17254 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17255 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 17259 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 17260 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 17261 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] .sym 17268 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17292 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 17308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 17316 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 17326 tx_fifo.rd_addr[1] +.sym 17271 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 17274 tx_fifo.rd_addr[1] +.sym 17280 tx_fifo.rd_addr[9] +.sym 17286 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 17290 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 17295 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17296 tx_fifo.rd_addr[9] +.sym 17297 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 17298 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 17301 tx_fifo.rd_addr[1] +.sym 17302 w_tx_fifo_pull +.sym 17303 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 17308 tx_fifo.rd_addr[1] +.sym 17316 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 17320 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 17325 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 17326 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] .sym 17329 lvds_tx_inst.r_pulled_SB_LUT4_I3_O .sym 17330 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17333 spi_if_ins.spi.r3_rx_done -.sym 17335 tx_fifo.rd_addr_gray_wr[5] -.sym 17336 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17343 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17345 tx_fifo.wr_addr_gray_rd[9] -.sym 17346 w_rx_fifo_pulled_data[5] -.sym 17348 w_rx_fifo_pulled_data[7] -.sym 17394 tx_fifo.rd_addr_gray[6] -.sym 17397 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 17445 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 17448 tx_fifo.rd_addr_gray[6] +.sym 17332 tx_fifo.rd_addr_gray_wr_r[8] +.sym 17333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17334 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17335 tx_fifo.rd_addr_gray_wr[8] +.sym 17336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 17337 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 17338 tx_fifo.rd_addr_gray_wr[3] +.sym 17339 tx_fifo.rd_addr_gray_wr[9] +.sym 17342 spi_if_ins.r_tx_byte[6] +.sym 17346 w_tx_fifo_pull +.sym 17355 i_ss$SB_IO_IN +.sym 17365 rx_fifo.wr_addr[9] +.sym 17366 $PACKER_VCC_NET +.sym 17367 spi_if_ins.w_rx_data[0] +.sym 17375 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17377 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17378 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 17382 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17385 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17388 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17391 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17395 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17398 $PACKER_VCC_NET +.sym 17405 $nextpnr_ICESTORM_LC_9$O +.sym 17408 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17411 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 17413 $PACKER_VCC_NET +.sym 17414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17418 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17420 $PACKER_VCC_NET +.sym 17421 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 17424 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 17425 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17430 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17432 $PACKER_VCC_NET +.sym 17433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17436 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17439 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17451 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 17453 r_counter_$glb_clk -.sym 17461 spi_if_ins.spi.SCKr[0] -.sym 17471 w_rx_fifo_pulled_data[30] -.sym 17473 $PACKER_VCC_NET -.sym 17476 i_ss$SB_IO_IN -.sym 17482 o_led1$SB_IO_OUT -.sym 17487 w_fetch -.sym 17506 rx_fifo.wr_addr_gray_rd[0] -.sym 17573 rx_fifo.wr_addr_gray_rd[0] +.sym 17454 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17458 spi_if_ins.r_tx_data_valid +.sym 17460 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17461 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17462 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 17471 $PACKER_VCC_NET +.sym 17478 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17479 w_fetch +.sym 17487 w_load +.sym 17490 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17497 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 17498 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17500 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 17505 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +.sym 17506 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17508 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] +.sym 17511 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17516 spi_if_ins.spi.r_tx_byte[1] +.sym 17519 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17521 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 17523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 17524 spi_if_ins.spi.r_tx_byte[0] +.sym 17527 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17536 spi_if_ins.spi.r_tx_byte[1] +.sym 17537 spi_if_ins.spi.r_tx_byte[0] +.sym 17538 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17542 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17549 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17553 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 17555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17556 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] +.sym 17562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +.sym 17566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 17572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 17573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 17574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 17575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .sym 17576 r_counter_$glb_clk -.sym 17578 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 17582 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17584 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 17591 rx_fifo.rd_addr[4] -.sym 17594 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 17598 i_sck$SB_IO_IN -.sym 17603 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17608 o_led1$SB_IO_OUT -.sym 17610 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17621 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17624 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17630 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 17632 spi_if_ins.r_tx_byte[7] -.sym 17635 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 17641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 17664 spi_if_ins.r_tx_byte[7] -.sym 17666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 17667 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17682 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17683 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 17685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 17698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17583 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 17584 w_fetch +.sym 17585 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17586 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17590 w_load +.sym 17591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17592 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 17599 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17601 i_ss$SB_IO_IN +.sym 17604 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 17607 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 17609 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 17610 spi_if_ins.r_tx_byte[4] +.sym 17619 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17620 spi_if_ins.spi.r_tx_byte[5] +.sym 17622 spi_if_ins.spi.r_tx_byte[4] +.sym 17624 spi_if_ins.spi.r_tx_byte[6] +.sym 17626 spi_if_ins.w_rx_data[2] +.sym 17627 spi_if_ins.spi.r_tx_byte[2] +.sym 17628 spi_if_ins.w_rx_data[1] +.sym 17630 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17631 spi_if_ins.spi.r_tx_byte[3] +.sym 17632 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17634 spi_if_ins.spi.r_tx_byte[7] +.sym 17637 spi_if_ins.w_rx_data[0] +.sym 17642 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17650 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17653 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17654 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17659 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17660 spi_if_ins.spi.r_tx_byte[6] +.sym 17661 spi_if_ins.spi.r_tx_byte[7] +.sym 17665 spi_if_ins.w_rx_data[2] +.sym 17673 spi_if_ins.w_rx_data[0] +.sym 17676 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17678 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17683 spi_if_ins.w_rx_data[1] +.sym 17688 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17689 spi_if_ins.spi.r_tx_byte[5] +.sym 17691 spi_if_ins.spi.r_tx_byte[4] +.sym 17694 spi_if_ins.spi.r_tx_byte[3] +.sym 17695 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17696 spi_if_ins.spi.r_tx_byte[2] +.sym 17698 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 17699 r_counter_$glb_clk -.sym 17702 o_led1$SB_IO_OUT -.sym 17703 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17720 spi_if_ins.r_tx_byte[7] -.sym 17721 w_rx_fifo_empty -.sym 17727 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 17702 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 17705 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 17710 spi_if_ins.w_rx_data[1] +.sym 17712 spi_if_ins.r_tx_byte[7] +.sym 17714 spi_if_ins.w_rx_data[4] +.sym 17718 spi_if_ins.w_rx_data[3] +.sym 17720 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17721 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17722 spi_if_ins.w_rx_data[2] +.sym 17724 spi_if_ins.w_rx_data[6] .sym 17728 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17736 o_led1$SB_IO_OUT -.sym 17746 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17752 i_ss$SB_IO_IN -.sym 17755 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 17764 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17766 spi_if_ins.r_tx_data_valid -.sym 17777 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17799 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17805 i_ss$SB_IO_IN -.sym 17807 spi_if_ins.r_tx_data_valid -.sym 17812 spi_if_ins.r_tx_data_valid -.sym 17814 i_ss$SB_IO_IN -.sym 17821 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17729 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 17730 w_load +.sym 17732 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 17733 w_fetch +.sym 17734 io_ctrl_ins.rf_pin_state[2] +.sym 17743 spi_if_ins.r_tx_byte[1] +.sym 17749 spi_if_ins.r_tx_byte[0] +.sym 17750 spi_if_ins.r_tx_byte[2] +.sym 17752 spi_if_ins.r_tx_byte[3] +.sym 17753 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 17755 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 17761 spi_if_ins.r_tx_byte[5] +.sym 17765 spi_if_ins.r_tx_byte[7] +.sym 17767 spi_if_ins.r_tx_byte[6] +.sym 17770 spi_if_ins.r_tx_byte[4] +.sym 17778 spi_if_ins.r_tx_byte[2] +.sym 17781 spi_if_ins.r_tx_byte[5] +.sym 17788 spi_if_ins.r_tx_byte[0] +.sym 17795 spi_if_ins.r_tx_byte[4] +.sym 17802 spi_if_ins.r_tx_byte[3] +.sym 17806 spi_if_ins.r_tx_byte[6] +.sym 17812 spi_if_ins.r_tx_byte[1] +.sym 17819 spi_if_ins.r_tx_byte[7] +.sym 17821 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 17822 r_counter_$glb_clk -.sym 17823 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17824 w_ioc[1] -.sym 17827 w_ioc[4] -.sym 17828 w_ioc[3] -.sym 17829 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 17830 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 17831 w_ioc[2] -.sym 17836 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17839 w_rx_data[7] -.sym 17846 w_fetch -.sym 17847 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17849 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 17853 w_fetch -.sym 17855 spi_if_ins.w_rx_data[4] -.sym 17857 w_ioc[1] -.sym 17858 i_config[1]$SB_IO_IN -.sym 17868 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 17870 spi_if_ins.w_rx_data[5] -.sym 17871 i_rst_b$SB_IO_IN -.sym 17874 spi_if_ins.w_rx_data[0] -.sym 17876 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 17877 w_fetch -.sym 17879 spi_if_ins.w_rx_data[6] -.sym 17881 w_ioc[1] -.sym 17889 w_cs[2] -.sym 17894 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 17895 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 17901 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 17916 spi_if_ins.w_rx_data[5] -.sym 17918 spi_if_ins.w_rx_data[6] -.sym 17928 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 17929 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 17930 w_cs[2] -.sym 17931 w_ioc[1] -.sym 17936 i_rst_b$SB_IO_IN -.sym 17937 w_fetch -.sym 17941 spi_if_ins.w_rx_data[0] -.sym 17944 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17823 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 17824 o_led0_SB_LUT4_I1_O[0] +.sym 17825 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 17826 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 17827 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E +.sym 17828 o_led1_SB_LUT4_I1_O[0] +.sym 17830 o_led1_SB_LUT4_I1_I2[0] +.sym 17831 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 17833 spi_if_ins.r_tx_byte[1] +.sym 17834 spi_if_ins.r_tx_byte[1] +.sym 17837 w_rx_data[0] +.sym 17850 io_ctrl_ins.rf_pin_state[7] +.sym 17854 io_ctrl_ins.rf_pin_state[5] +.sym 17855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 17857 spi_if_ins.w_rx_data[5] +.sym 17865 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 17866 w_rx_data[5] +.sym 17867 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 17869 w_rx_data[2] +.sym 17870 w_rx_data[7] +.sym 17871 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 17874 i_rst_b$SB_IO_IN +.sym 17875 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 17876 io_pmod[2]$SB_IO_IN +.sym 17877 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 17883 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 17884 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 17888 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17891 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 17892 w_cs[1] +.sym 17898 i_rst_b$SB_IO_IN +.sym 17900 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 17901 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 17904 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 17905 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 17906 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 17907 w_cs[1] +.sym 17910 w_rx_data[2] +.sym 17916 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17918 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 17919 io_pmod[2]$SB_IO_IN +.sym 17924 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 17925 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 17930 w_rx_data[7] +.sym 17940 w_rx_data[5] +.sym 17944 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O .sym 17945 r_counter_$glb_clk -.sym 17947 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 17948 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 17949 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] -.sym 17950 o_led1_SB_DFFER_Q_E -.sym 17951 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 17952 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 17953 w_tx_data_io[2] -.sym 17954 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] -.sym 17959 spi_if_ins.w_rx_data[3] -.sym 17960 w_rx_data[5] -.sym 17964 w_rx_data[4] -.sym 17966 w_ioc[1] -.sym 17970 w_rx_data[3] -.sym 17971 o_tr_vc1_b$SB_IO_OUT -.sym 17972 w_fetch -.sym 17973 o_tr_vc2$SB_IO_OUT -.sym 17976 w_rx_data[0] -.sym 17977 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 17979 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 17980 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 17981 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 17982 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17988 w_cs[0] -.sym 17990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 17993 w_cs[1] -.sym 17994 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 17995 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17996 w_ioc[1] -.sym 17997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 18001 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18002 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 18003 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18008 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 18010 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18012 w_load -.sym 18013 w_fetch -.sym 18016 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 18021 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 18027 w_ioc[1] -.sym 18029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18030 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18045 w_cs[0] -.sym 18047 w_fetch -.sym 18048 w_load -.sym 18051 w_ioc[1] -.sym 18052 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18053 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 17947 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 17948 w_tx_data_io[1] +.sym 17949 w_tx_data_io[0] +.sym 17950 o_led1_SB_LUT4_I1_O[2] +.sym 17951 i_button_SB_LUT4_I0_O[1] +.sym 17952 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 17953 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 17954 o_led0_SB_LUT4_I1_O[3] +.sym 17960 o_led1_SB_LUT4_I1_I2[0] +.sym 17962 w_rx_data[4] +.sym 17963 spi_if_ins.w_rx_data[5] +.sym 17964 io_pmod[2]$SB_IO_IN +.sym 17965 w_rx_data[2] +.sym 17966 spi_if_ins.w_rx_data[6] +.sym 17967 w_rx_data[1] +.sym 17969 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 17970 io_pmod_SB_DFFE_Q_E +.sym 17971 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 17972 i_button_SB_LUT4_I0_O[1] +.sym 17973 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 17975 w_load +.sym 17976 w_fetch +.sym 17977 w_cs[1] +.sym 17978 w_rx_data[3] +.sym 17979 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 17988 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 17989 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 17990 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 17991 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] +.sym 17995 w_ioc[4] +.sym 17996 w_ioc[3] +.sym 17997 w_ioc[2] +.sym 17999 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18000 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 18001 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 18002 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 18003 o_shdn_tx_lna$SB_IO_OUT +.sym 18007 o_led1_SB_LUT4_I1_I3[3] +.sym 18008 i_button_SB_LUT4_I0_O[1] +.sym 18009 o_led0_SB_LUT4_I1_O[1] +.sym 18015 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18016 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] +.sym 18018 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 18022 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18023 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18024 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 18027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] +.sym 18028 i_button_SB_LUT4_I0_O[1] +.sym 18029 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] +.sym 18030 o_shdn_tx_lna$SB_IO_OUT +.sym 18034 w_ioc[4] +.sym 18035 w_ioc[2] +.sym 18036 w_ioc[3] +.sym 18039 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 18041 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 18042 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18045 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 18046 o_led0_SB_LUT4_I1_O[1] +.sym 18047 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18048 o_led1_SB_LUT4_I1_I3[3] +.sym 18051 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 18053 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] .sym 18054 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18058 w_ioc[1] -.sym 18059 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18063 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 18064 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18065 w_cs[1] -.sym 18066 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18067 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 18058 w_ioc[3] +.sym 18059 w_ioc[2] +.sym 18060 w_ioc[4] +.sym 18063 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 18065 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 18066 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18067 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E .sym 18068 r_counter_$glb_clk -.sym 18069 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 18070 w_tx_data_io[1] -.sym 18071 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] -.sym 18072 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] -.sym 18073 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E -.sym 18074 w_tx_data_io[0] -.sym 18075 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 18076 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 18077 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] -.sym 18078 io_pmod[0]$SB_IO_IN -.sym 18090 o_shdn_rx_lna$SB_IO_OUT -.sym 18094 io_pmod[1]$SB_IO_IN -.sym 18097 w_rx_data[2] -.sym 18099 w_rx_data[1] -.sym 18102 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 18104 io_pmod[2]$SB_IO_IN -.sym 18105 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 18112 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 18114 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18115 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 18117 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18120 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 18123 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 18126 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18127 w_ioc[1] -.sym 18130 i_config[1]$SB_IO_IN -.sym 18133 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18137 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18139 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18141 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 18146 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 18156 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18157 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18159 i_config[1]$SB_IO_IN -.sym 18163 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18165 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18168 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18170 w_ioc[1] -.sym 18174 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18175 w_ioc[1] -.sym 18176 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18177 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18180 w_ioc[1] -.sym 18181 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18182 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18186 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 18187 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 18188 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18189 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18069 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 18070 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18071 o_led1_SB_DFFER_Q_E +.sym 18073 o_led1_SB_LUT4_I1_O[3] +.sym 18074 w_smi_data_direction +.sym 18076 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18077 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 18085 o_shdn_rx_lna$SB_IO_OUT +.sym 18087 o_led0_SB_LUT4_I1_O[2] +.sym 18088 i_glob_clock$SB_IO_IN +.sym 18091 o_shdn_tx_lna$SB_IO_OUT +.sym 18096 io_pmod[1]$SB_IO_IN +.sym 18097 o_led1_SB_LUT4_I1_I3[3] +.sym 18098 i_button_SB_LUT4_I0_O[1] +.sym 18100 o_led0_SB_LUT4_I1_O[1] +.sym 18101 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18102 spi_if_ins.r_tx_byte[4] +.sym 18104 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18105 o_led1_SB_LUT4_I1_I2[1] +.sym 18112 spi_if_ins.w_rx_data[4] +.sym 18113 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 18114 o_led1_SB_LUT4_I1_I3[3] +.sym 18115 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 18117 w_load +.sym 18120 spi_if_ins.w_rx_data[6] +.sym 18121 w_tx_data_io[0] +.sym 18122 spi_if_ins.w_rx_data[3] +.sym 18123 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18126 w_tx_data_smi[0] +.sym 18127 spi_if_ins.w_rx_data[5] +.sym 18128 w_cs[2] +.sym 18136 w_fetch +.sym 18138 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 18144 spi_if_ins.w_rx_data[3] +.sym 18150 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18151 w_tx_data_smi[0] +.sym 18152 w_tx_data_io[0] +.sym 18153 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 18156 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 18163 spi_if_ins.w_rx_data[6] +.sym 18165 spi_if_ins.w_rx_data[5] +.sym 18168 w_load +.sym 18169 w_cs[2] +.sym 18170 w_fetch +.sym 18171 o_led1_SB_LUT4_I1_I3[3] +.sym 18177 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 18188 spi_if_ins.w_rx_data[4] +.sym 18190 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 18191 r_counter_$glb_clk -.sym 18193 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] -.sym 18194 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] -.sym 18195 io_ctrl_ins.pmod_dir_state[3] -.sym 18196 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 18197 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] -.sym 18198 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 18199 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 18200 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] -.sym 18205 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 18206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 18214 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 18220 i_button_SB_LUT4_I0_O[1] -.sym 18226 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 18234 w_rx_data[6] -.sym 18237 i_button_SB_LUT4_I0_O[1] -.sym 18239 w_rx_data[7] -.sym 18242 w_ioc[1] -.sym 18243 o_tr_vc1_b$SB_IO_OUT -.sym 18245 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18246 w_rx_data[4] -.sym 18247 w_cs[1] -.sym 18248 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18249 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18250 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 18251 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18253 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18259 w_rx_data[1] -.sym 18265 io_ctrl_ins.pmod_dir_state[4] -.sym 18267 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 18268 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18269 w_cs[1] -.sym 18270 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 18273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18274 io_ctrl_ins.pmod_dir_state[4] -.sym 18275 i_button_SB_LUT4_I0_O[1] -.sym 18276 o_tr_vc1_b$SB_IO_OUT -.sym 18282 w_rx_data[7] -.sym 18285 w_ioc[1] -.sym 18286 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18287 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 18288 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18291 w_rx_data[1] -.sym 18297 w_ioc[1] -.sym 18298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 18300 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18303 w_rx_data[6] -.sym 18311 w_rx_data[4] -.sym 18313 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18194 r_tx_data[3] +.sym 18197 i_config_SB_LUT4_I0_2_O[3] +.sym 18199 i_config_SB_LUT4_I0_2_O[2] +.sym 18200 r_tx_data[0] +.sym 18201 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 18205 w_rx_data[0] +.sym 18209 io_ctrl_ins.pmod_dir_state[3] +.sym 18212 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18214 o_led1_SB_DFFER_Q_E +.sym 18235 w_cs[2] +.sym 18236 w_cs[3] +.sym 18237 w_cs[1] +.sym 18239 spi_if_ins.w_rx_data[5] +.sym 18241 i_rst_b$SB_IO_IN +.sym 18242 spi_if_ins.w_rx_data[6] +.sym 18243 w_cs[2] +.sym 18244 w_cs[0] +.sym 18245 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 18252 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 18261 w_cs[1] +.sym 18263 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 18267 w_cs[3] +.sym 18268 w_cs[0] +.sym 18269 w_cs[2] +.sym 18270 w_cs[1] +.sym 18274 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 18275 i_rst_b$SB_IO_IN +.sym 18279 w_cs[3] +.sym 18280 w_cs[1] +.sym 18281 w_cs[2] +.sym 18282 w_cs[0] +.sym 18285 spi_if_ins.w_rx_data[6] +.sym 18287 spi_if_ins.w_rx_data[5] +.sym 18291 w_cs[1] +.sym 18292 w_cs[2] +.sym 18293 w_cs[3] +.sym 18294 w_cs[0] +.sym 18297 w_cs[0] +.sym 18298 w_cs[2] +.sym 18299 w_cs[1] +.sym 18300 w_cs[3] +.sym 18313 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 18314 r_counter_$glb_clk -.sym 18317 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] -.sym 18321 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 18322 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18328 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 18332 w_load -.sym 18345 i_config[2]$SB_IO_IN -.sym 18349 i_config[1]$SB_IO_IN -.sym 18359 io_ctrl_ins.pmod_dir_state[7] -.sym 18360 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18361 i_config[2]$SB_IO_IN -.sym 18362 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18363 io_ctrl_ins.pmod_dir_state[6] -.sym 18368 o_rx_h_tx_l$SB_IO_OUT -.sym 18369 io_ctrl_ins.pmod_dir_state[5] -.sym 18370 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18372 o_tr_vc1$SB_IO_OUT -.sym 18373 i_config[3]$SB_IO_IN -.sym 18374 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 18375 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 18377 i_button$SB_IO_IN -.sym 18380 i_button_SB_LUT4_I0_O[1] -.sym 18383 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18384 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 18387 i_button_SB_LUT4_I0_O[2] -.sym 18390 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 18391 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18393 i_button_SB_LUT4_I0_O[1] -.sym 18396 io_ctrl_ins.pmod_dir_state[5] -.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18398 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18399 i_config[2]$SB_IO_IN -.sym 18402 io_ctrl_ins.pmod_dir_state[6] -.sym 18403 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18404 i_config[3]$SB_IO_IN -.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18420 i_button_SB_LUT4_I0_O[1] -.sym 18421 o_tr_vc1$SB_IO_OUT -.sym 18422 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 18426 i_button$SB_IO_IN -.sym 18427 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18428 io_ctrl_ins.pmod_dir_state[7] -.sym 18429 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 18432 i_button_SB_LUT4_I0_O[1] -.sym 18434 i_button_SB_LUT4_I0_O[2] -.sym 18435 o_rx_h_tx_l$SB_IO_OUT -.sym 18436 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 18315 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 18320 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 18336 o_led1_SB_LUT4_I1_I3[1] +.sym 18337 o_led1_SB_LUT4_I1_I2[2] +.sym 18338 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 18358 r_tx_data[2] +.sym 18359 r_tx_data[5] +.sym 18360 r_tx_data[7] +.sym 18361 r_tx_data[6] +.sym 18363 r_tx_data[4] +.sym 18364 r_tx_data[0] +.sym 18366 r_tx_data[3] +.sym 18368 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 18372 r_tx_data[1] +.sym 18392 r_tx_data[5] +.sym 18396 r_tx_data[2] +.sym 18402 r_tx_data[3] +.sym 18411 r_tx_data[6] +.sym 18414 r_tx_data[4] +.sym 18420 r_tx_data[0] +.sym 18429 r_tx_data[7] +.sym 18433 r_tx_data[1] +.sym 18436 spi_if_ins.r_tx_byte_SB_DFFE_Q_E .sym 18437 r_counter_$glb_clk -.sym 18451 w_rx_data[0] -.sym 18452 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18456 o_rx_h_tx_l$SB_IO_OUT -.sym 18460 o_tr_vc1$SB_IO_OUT -.sym 18469 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18482 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18506 w_rx_data[5] -.sym 18538 w_rx_data[5] -.sym 18559 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18560 r_counter_$glb_clk +.sym 18453 o_tr_vc1_b$SB_IO_OUT +.sym 18467 i_config[1]$SB_IO_IN .sym 18562 i_config[1]$SB_IO_IN .sym 18564 i_config[2]$SB_IO_IN +.sym 18587 i_config[2]$SB_IO_IN .sym 18636 w_smi_data_output[4] -.sym 18638 o_led0$SB_IO_OUT +.sym 18638 w_smi_data_direction .sym 18642 $PACKER_VCC_NET -.sym 18645 w_smi_data_output[4] -.sym 18648 o_led0$SB_IO_OUT -.sym 18658 $PACKER_VCC_NET -.sym 18687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18691 tx_fifo.wr_addr[1] -.sym 18694 o_miso_$_TBUF__Y_E -.sym 18696 o_led0$SB_IO_OUT -.sym 18703 tx_fifo.wr_addr_gray[0] -.sym 18710 tx_fifo.wr_addr_gray[6] -.sym 18744 tx_fifo.wr_addr_gray[6] -.sym 18779 tx_fifo.wr_addr_gray[0] -.sym 18783 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 18647 $PACKER_VCC_NET +.sym 18653 w_smi_data_direction +.sym 18658 w_smi_data_output[4] +.sym 18662 w_rx_fifo_pulled_data[20] +.sym 18666 w_rx_fifo_pulled_data[22] +.sym 18691 w_smi_data_direction +.sym 18694 $PACKER_VCC_NET +.sym 18695 w_smi_data_input[7] +.sym 18696 w_smi_data_output[5] +.sym 18704 tx_fifo.wr_addr[6] +.sym 18705 tx_fifo.wr_addr[1] +.sym 18709 tx_fifo.wr_addr[4] +.sym 18713 tx_fifo.wr_addr[5] +.sym 18714 tx_fifo.wr_addr[3] +.sym 18715 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 18719 tx_fifo.wr_addr[0] +.sym 18727 tx_fifo.wr_addr[0] +.sym 18728 tx_fifo.wr_addr[7] +.sym 18735 $nextpnr_ICESTORM_LC_3$O +.sym 18737 tx_fifo.wr_addr[0] +.sym 18741 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 18743 tx_fifo.wr_addr[1] +.sym 18745 tx_fifo.wr_addr[0] +.sym 18747 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18749 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 18751 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 18753 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18755 tx_fifo.wr_addr[3] +.sym 18757 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18759 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 18762 tx_fifo.wr_addr[4] +.sym 18763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18765 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18768 tx_fifo.wr_addr[5] +.sym 18769 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 18771 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 18773 tx_fifo.wr_addr[6] +.sym 18775 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18777 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18779 tx_fifo.wr_addr[7] +.sym 18781 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18815 $PACKER_VCC_NET -.sym 18846 rx_fifo.wr_addr[4] -.sym 18847 w_smi_data_output[5] -.sym 18853 tx_fifo.wr_addr[1] -.sym 18854 rx_fifo.wr_addr[6] -.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 18868 tx_fifo.wr_addr[1] -.sym 18871 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 18790 w_rx_fifo_pulled_data[21] +.sym 18794 w_rx_fifo_pulled_data[23] +.sym 18801 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 18802 tx_fifo.wr_addr[6] +.sym 18804 rx_fifo.wr_addr[9] +.sym 18805 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 18806 rx_fifo.wr_addr[8] +.sym 18807 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 18809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18810 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 18812 $PACKER_VCC_NET +.sym 18814 rx_fifo.wr_addr[4] +.sym 18818 rx_fifo.wr_addr[0] +.sym 18824 rx_fifo.wr_addr[3] +.sym 18831 i_sck$SB_IO_IN +.sym 18832 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 18833 rx_fifo.rd_addr[8] +.sym 18837 rx_fifo.rd_addr[1] +.sym 18841 rx_fifo.wr_addr[1] +.sym 18843 rx_fifo.rd_addr[6] +.sym 18844 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 18845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18846 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 18850 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 18851 tx_fifo.wr_addr[8] +.sym 18852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18853 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18855 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 18859 w_smi_data_direction +.sym 18861 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18867 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 18872 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18873 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 18876 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] .sym 18877 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] .sym 18878 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 18881 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 18893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18899 tx_fifo.wr_addr[1] -.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 18907 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 18911 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 18930 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 18938 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 18942 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 18944 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18879 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 18880 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18889 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 18891 tx_fifo.wr_addr[8] +.sym 18894 tx_fifo.wr_addr[9] +.sym 18898 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 18901 tx_fifo.wr_addr[8] +.sym 18902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18905 tx_fifo.wr_addr[9] +.sym 18908 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 18912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 18918 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18924 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 18929 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 18930 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18931 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 18938 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 18941 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18944 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] .sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 18946 r_counter_$glb_clk .sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 18949 w_rx_fifo_pulled_data[20] -.sym 18953 w_rx_fifo_pulled_data[22] -.sym 18962 tx_fifo.wr_addr[3] -.sym 18966 tx_fifo.wr_addr[6] -.sym 18968 tx_fifo.wr_addr[7] -.sym 18970 tx_fifo.wr_addr[4] -.sym 18978 rx_fifo.rd_addr[6] -.sym 18979 rx_fifo.rd_addr[2] -.sym 18980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18982 rx_fifo.rd_addr[9] -.sym 18983 $PACKER_VCC_NET -.sym 18989 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18995 tx_fifo.wr_addr[0] -.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 19008 i_rst_b$SB_IO_IN -.sym 19011 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19012 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 19015 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 19016 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19017 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 19018 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 19019 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 19025 i_rst_b$SB_IO_IN -.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 19029 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19030 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19042 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 19048 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19055 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 19058 tx_fifo.wr_addr[0] -.sym 19064 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 19067 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 19069 r_counter_$glb_clk -.sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19072 w_rx_fifo_pulled_data[21] -.sym 19076 w_rx_fifo_pulled_data[23] -.sym 19081 o_led1_SB_DFFER_Q_E -.sym 19095 rx_fifo.wr_addr[5] -.sym 19096 tx_fifo.wr_addr[1] -.sym 19098 rx_fifo.wr_addr[4] -.sym 19100 rx_fifo.wr_addr[7] -.sym 19102 rx_fifo.wr_addr[6] -.sym 19104 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 19105 o_led1$SB_IO_OUT -.sym 19117 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 19119 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 19122 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 18949 w_rx_fifo_pulled_data[28] +.sym 18953 w_rx_fifo_pulled_data[30] +.sym 18960 rx_fifo.rd_addr[7] +.sym 18962 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 18964 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 18968 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 18970 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18973 tx_fifo.wr_addr[1] +.sym 18974 rx_fifo.rd_addr[2] +.sym 18975 rx_fifo.rd_addr[1] +.sym 18976 rx_fifo.wr_addr[4] +.sym 18978 rx_fifo.wr_addr[3] +.sym 18981 w_smi_data_direction +.sym 18982 rx_fifo.rd_addr[0] +.sym 18983 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 18991 tx_fifo.wr_addr[1] +.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 18995 tx_fifo.wr_addr[6] +.sym 18999 tx_fifo.wr_addr[7] +.sym 19000 tx_fifo.wr_addr[3] +.sym 19001 tx_fifo.wr_addr[5] +.sym 19003 tx_fifo.wr_addr[4] +.sym 19016 tx_fifo.wr_addr[8] +.sym 19021 $nextpnr_ICESTORM_LC_8$O +.sym 19024 tx_fifo.wr_addr[1] +.sym 19027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 19031 tx_fifo.wr_addr[1] +.sym 19033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19036 tx_fifo.wr_addr[3] +.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19042 tx_fifo.wr_addr[4] +.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19045 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19047 tx_fifo.wr_addr[5] +.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19051 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19053 tx_fifo.wr_addr[6] +.sym 19055 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19057 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 19059 tx_fifo.wr_addr[7] +.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 19063 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 19065 tx_fifo.wr_addr[8] +.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 19072 w_rx_fifo_pulled_data[29] +.sym 19076 w_rx_fifo_pulled_data[31] +.sym 19082 w_fetch +.sym 19084 o_smi_read_req$SB_IO_OUT +.sym 19089 rx_fifo.wr_addr[5] +.sym 19090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 19092 w_rx_fifo_pulled_data[28] +.sym 19093 $PACKER_VCC_NET +.sym 19094 rx_fifo.wr_addr[9] +.sym 19098 w_rx_fifo_pulled_data[31] +.sym 19103 tx_fifo.wr_addr[9] +.sym 19104 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19106 w_rx_fifo_pulled_data[29] +.sym 19107 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 19113 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 19114 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19115 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19116 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19117 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 19119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19121 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 19122 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 19125 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 19127 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19136 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 19137 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 19141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 19147 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 19148 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 19151 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 19152 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19153 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 19154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 19157 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 19165 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 19169 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 19170 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 19175 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 19189 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 19124 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 19125 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19126 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19128 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19129 tx_fifo.wr_addr[9] +.sym 19130 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 19132 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] +.sym 19137 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] +.sym 19146 tx_fifo.wr_addr[9] +.sym 19148 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 19151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19153 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19157 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19166 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19169 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 19170 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 19172 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19175 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 19176 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] +.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19178 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19183 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19187 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 19188 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19189 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19190 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] .sym 19191 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 19192 r_counter_$glb_clk .sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19195 w_rx_fifo_pulled_data[4] -.sym 19199 w_rx_fifo_pulled_data[6] -.sym 19206 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 19207 rx_fifo.rd_addr[4] -.sym 19208 rx_fifo.mem_i.0.1_WDATA_1 -.sym 19209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 19210 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 19214 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 19215 w_rx_fifo_pulled_data[21] -.sym 19216 rx_fifo.rd_addr[8] -.sym 19219 rx_fifo.wr_addr[0] -.sym 19221 o_led1$SB_IO_OUT -.sym 19222 rx_fifo.mem_i.0.1_WDATA -.sym 19223 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19227 rx_fifo.wr_addr[1] -.sym 19228 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 19235 tx_fifo.wr_addr_gray[8] -.sym 19238 tx_fifo.wr_addr_gray[1] -.sym 19239 tx_fifo.wr_addr_gray[7] -.sym 19245 tx_fifo.wr_addr_gray[2] -.sym 19248 tx_fifo.wr_addr_gray[3] -.sym 19250 tx_fifo.wr_addr_gray[5] -.sym 19271 tx_fifo.wr_addr_gray[1] -.sym 19275 tx_fifo.wr_addr_gray[3] -.sym 19281 tx_fifo.wr_addr_gray[2] -.sym 19287 tx_fifo.wr_addr_gray[8] -.sym 19306 tx_fifo.wr_addr_gray[5] -.sym 19313 tx_fifo.wr_addr_gray[7] -.sym 19315 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 19318 w_rx_fifo_pulled_data[5] -.sym 19322 w_rx_fifo_pulled_data[7] -.sym 19325 tx_fifo.wr_addr[1] -.sym 19330 rx_fifo.wr_addr[8] -.sym 19333 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 19344 rx_fifo.rd_addr[0] -.sym 19346 rx_fifo.wr_addr[6] -.sym 19351 rx_fifo.rd_addr[6] -.sym 19361 tx_fifo.rd_addr_gray_wr[5] -.sym 19365 tx_fifo.rd_addr_gray[0] -.sym 19394 tx_fifo.rd_addr_gray_wr[5] -.sym 19421 tx_fifo.rd_addr_gray[0] -.sym 19438 r_counter_$glb_clk -.sym 19441 w_rx_fifo_pulled_data[28] -.sym 19445 w_rx_fifo_pulled_data[30] -.sym 19454 tx_fifo.rd_addr_gray_wr[0] -.sym 19459 rx_fifo.rd_addr[1] -.sym 19460 rx_fifo.rd_addr[7] -.sym 19461 rx_fifo.rd_addr[0] -.sym 19464 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19465 rx_fifo.mem_i.0.3_WDATA -.sym 19466 rx_fifo.rd_addr[9] -.sym 19467 rx_fifo.mem_q.0.1_WDATA -.sym 19470 $PACKER_VCC_NET -.sym 19472 rx_fifo.mem_q.0.1_WDATA_1 -.sym 19474 rx_fifo.rd_addr[2] -.sym 19475 rx_fifo.mem_i.0.3_WDATA_1 -.sym 19498 spi_if_ins.spi.r3_rx_done -.sym 19506 spi_if_ins.spi.r2_rx_done -.sym 19510 tx_fifo.rd_addr_gray[5] -.sym 19521 spi_if_ins.spi.r2_rx_done -.sym 19533 tx_fifo.rd_addr_gray[5] -.sym 19538 spi_if_ins.spi.r2_rx_done -.sym 19539 spi_if_ins.spi.r3_rx_done +.sym 19206 rx_fifo.mem_i.0.3_WDATA +.sym 19212 tx_fifo.wr_addr[8] +.sym 19214 w_smi_data_output[5] +.sym 19215 smi_ctrl_ins.w_fifo_push_trigger +.sym 19221 rx_fifo.wr_addr[1] +.sym 19222 rx_fifo.rd_addr[9] +.sym 19223 i_sck$SB_IO_IN +.sym 19224 rx_fifo.rd_addr[8] +.sym 19227 rx_fifo.rd_addr[4] +.sym 19229 rx_fifo.mem_i.0.3_WDATA_1 +.sym 19235 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 19238 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 19239 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 19240 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 19243 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 19245 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 19246 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 19247 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 19249 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19250 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 19251 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 19252 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 19253 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19255 tx_fifo.rd_addr_gray[0] +.sym 19256 tx_fifo.rd_addr_gray_wr[3] +.sym 19258 tx_fifo.rd_addr_gray[7] +.sym 19259 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19264 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19268 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 19269 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 19274 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 19275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 19276 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 19277 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 19283 tx_fifo.rd_addr_gray_wr[3] +.sym 19286 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19287 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 19288 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19289 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 19292 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 19293 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 19294 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 19298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 19299 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 19300 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 19301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 19304 tx_fifo.rd_addr_gray[0] +.sym 19310 tx_fifo.rd_addr_gray[7] +.sym 19315 r_counter_$glb_clk +.sym 19328 w_smi_data_direction +.sym 19331 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 19339 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 19342 tx_fifo.rd_addr_gray_wr[3] +.sym 19350 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19352 tx_fifo.rd_addr_gray_wr[7] +.sym 19362 i_ss$SB_IO_IN +.sym 19363 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19367 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19368 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19380 w_rx_fifo_empty +.sym 19382 w_smi_data_direction +.sym 19383 i_sck$SB_IO_IN +.sym 19386 w_tx_fifo_full +.sym 19387 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19390 $nextpnr_ICESTORM_LC_2$O +.sym 19392 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19396 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 19398 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19400 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19404 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19406 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 19409 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19410 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19411 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19412 i_ss$SB_IO_IN +.sym 19423 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19427 w_rx_fifo_empty +.sym 19428 w_tx_fifo_full +.sym 19430 w_smi_data_direction +.sym 19438 i_sck$SB_IO_IN +.sym 19439 i_ss$SB_IO_IN +.sym 19464 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 19468 w_smi_data_direction +.sym 19472 w_tx_fifo_full +.sym 19482 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19483 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19486 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19488 tx_fifo.rd_addr_gray_wr[9] +.sym 19492 tx_fifo.rd_addr_gray_wr[8] +.sym 19494 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19502 tx_fifo.rd_addr_gray[8] +.sym 19503 tx_fifo.rd_addr[9] +.sym 19505 tx_fifo.rd_addr_gray[3] +.sym 19512 tx_fifo.rd_addr_gray_wr[7] +.sym 19514 tx_fifo.rd_addr_gray_wr[8] +.sym 19523 tx_fifo.rd_addr_gray_wr[7] +.sym 19529 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19532 tx_fifo.rd_addr_gray[8] +.sym 19539 tx_fifo.rd_addr_gray_wr[9] +.sym 19545 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19546 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19547 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19551 tx_fifo.rd_addr_gray[3] +.sym 19559 tx_fifo.rd_addr[9] .sym 19561 r_counter_$glb_clk -.sym 19564 w_rx_fifo_pulled_data[29] -.sym 19568 w_rx_fifo_pulled_data[31] -.sym 19583 rx_fifo.wr_addr[4] -.sym 19588 rx_fifo.rd_addr[3] -.sym 19589 o_led1$SB_IO_OUT -.sym 19592 rx_fifo.wr_addr[7] -.sym 19593 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 19615 i_sck$SB_IO_IN -.sym 19673 i_sck$SB_IO_IN +.sym 19582 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19595 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 19615 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 19616 i_ss$SB_IO_IN +.sym 19618 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 19621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 19631 spi_if_ins.r_tx_data_valid +.sym 19633 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 19669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 19675 spi_if_ins.r_tx_data_valid +.sym 19676 i_ss$SB_IO_IN +.sym 19681 i_ss$SB_IO_IN +.sym 19682 spi_if_ins.r_tx_data_valid +.sym 19683 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .sym 19684 r_counter_$glb_clk -.sym 19699 rx_fifo.rd_addr[6] -.sym 19705 rx_fifo.rd_addr[8] -.sym 19710 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19715 rx_fifo.wr_addr[0] -.sym 19717 o_led1$SB_IO_OUT -.sym 19736 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19741 spi_if_ins.spi.SCKr[0] -.sym 19757 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19761 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19784 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19799 spi_if_ins.spi.SCKr[0] +.sym 19685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19714 w_fetch +.sym 19731 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 19735 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 19740 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 19742 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19745 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 19748 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19749 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19751 i_rst_b$SB_IO_IN +.sym 19791 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19797 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 19802 i_rst_b$SB_IO_IN +.sym 19803 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 19804 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19805 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19806 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .sym 19807 r_counter_$glb_clk -.sym 19821 spi_if_ins.w_rx_data[4] -.sym 19825 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 19833 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 19854 w_rx_data[0] -.sym 19862 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19868 o_led1_SB_DFFER_Q_E -.sym 19871 i_rst_b$SB_IO_IN -.sym 19881 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 19892 w_rx_data[0] -.sym 19896 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19897 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 19898 i_rst_b$SB_IO_IN -.sym 19929 o_led1_SB_DFFER_Q_E +.sym 19808 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 19823 spi_if_ins.w_rx_data[0] +.sym 19831 spi_if_ins.w_rx_data[5] +.sym 19834 o_led1_SB_LUT4_I1_I2[0] +.sym 19838 o_led0_SB_LUT4_I1_O[0] +.sym 19840 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 19850 w_rx_data[2] +.sym 19861 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 19862 w_rx_data[0] +.sym 19890 w_rx_data[2] +.sym 19910 w_rx_data[0] +.sym 19929 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E .sym 19930 r_counter_$glb_clk .sym 19931 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19950 w_rx_data[0] -.sym 19960 spi_if_ins.w_rx_data[1] -.sym 19964 spi_if_ins.w_rx_data[2] -.sym 19967 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 19975 spi_if_ins.w_rx_data[2] -.sym 19976 w_ioc[4] -.sym 19977 w_ioc[3] -.sym 19978 spi_if_ins.w_rx_data[3] -.sym 19984 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 19986 spi_if_ins.w_rx_data[1] -.sym 19995 spi_if_ins.w_rx_data[4] -.sym 20004 w_ioc[2] -.sym 20006 spi_if_ins.w_rx_data[1] -.sym 20025 spi_if_ins.w_rx_data[4] -.sym 20031 spi_if_ins.w_rx_data[3] -.sym 20036 w_ioc[4] -.sym 20037 w_ioc[2] -.sym 20039 w_ioc[3] -.sym 20042 w_ioc[2] -.sym 20044 w_ioc[3] -.sym 20045 w_ioc[4] -.sym 20051 spi_if_ins.w_rx_data[2] -.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 19944 w_rx_data[3] +.sym 19948 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 19954 w_rx_data[2] +.sym 19956 io_pmod[3]$SB_IO_IN +.sym 19958 o_led0$SB_IO_OUT +.sym 19960 o_led1_SB_LUT4_I1_I2[0] +.sym 19962 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 19964 w_smi_data_direction +.sym 19966 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 19974 w_rx_data[2] +.sym 19976 w_rx_data[1] +.sym 19977 i_button_SB_LUT4_I0_O[1] +.sym 19979 w_rx_data[4] +.sym 19982 w_load +.sym 19985 w_fetch +.sym 19991 w_cs[1] +.sym 19992 w_rx_data[3] +.sym 19995 w_rx_data[0] +.sym 19999 o_led0_SB_LUT4_I1_O[1] +.sym 20000 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E +.sym 20001 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20006 w_rx_data[0] +.sym 20014 w_rx_data[3] +.sym 20018 i_button_SB_LUT4_I0_O[1] +.sym 20019 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20024 w_fetch +.sym 20025 w_load +.sym 20026 o_led0_SB_LUT4_I1_O[1] +.sym 20027 w_cs[1] +.sym 20031 w_rx_data[1] +.sym 20044 w_rx_data[4] +.sym 20050 w_rx_data[2] +.sym 20052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E .sym 20053 r_counter_$glb_clk -.sym 20068 io_pmod[1]$SB_IO_IN -.sym 20069 w_rx_data[1] -.sym 20070 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 20072 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 20074 io_pmod[2]$SB_IO_IN -.sym 20075 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 20077 w_rx_data[2] -.sym 20079 io_pmod[3]$SB_IO_IN -.sym 20096 w_ioc[1] -.sym 20097 w_fetch -.sym 20098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 20099 o_shdn_rx_lna$SB_IO_OUT -.sym 20100 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 20101 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 20103 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 20104 w_load -.sym 20105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20106 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] -.sym 20107 io_pmod[0]$SB_IO_IN -.sym 20109 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 20110 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20116 io_pmod[1]$SB_IO_IN -.sym 20118 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20119 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20123 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20125 w_cs[2] -.sym 20127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20129 w_cs[2] -.sym 20130 w_fetch -.sym 20131 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20132 w_load -.sym 20136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 20138 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20141 io_pmod[0]$SB_IO_IN -.sym 20142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20147 w_fetch -.sym 20148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20149 w_load -.sym 20150 w_cs[2] -.sym 20153 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 20154 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20159 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 20160 w_ioc[1] -.sym 20161 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 20167 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20168 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] -.sym 20171 o_shdn_rx_lna$SB_IO_OUT -.sym 20172 io_pmod[1]$SB_IO_IN -.sym 20173 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20174 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 20054 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 20067 o_led0_SB_LUT4_I1_O[0] +.sym 20069 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 20071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 20078 io_pmod[1]$SB_IO_IN +.sym 20080 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 20081 w_rx_data[0] +.sym 20084 i_config[0]$SB_IO_IN +.sym 20088 o_led1_SB_LUT4_I1_I2[0] +.sym 20089 w_tx_data_io[1] +.sym 20096 o_led0_SB_LUT4_I1_O[0] +.sym 20097 io_ctrl_ins.pmod_dir_state[0] +.sym 20098 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20099 o_led1_SB_LUT4_I1_O[3] +.sym 20100 o_led1_SB_LUT4_I1_O[0] +.sym 20101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 20102 o_shdn_rx_lna$SB_IO_OUT +.sym 20103 o_led1_SB_LUT4_I1_I2[1] +.sym 20105 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 20106 o_tr_vc2$SB_IO_OUT +.sym 20107 o_led1_SB_LUT4_I1_I3[3] +.sym 20109 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20110 o_led0_SB_LUT4_I1_O[2] +.sym 20111 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 20114 o_led0_SB_LUT4_I1_O[1] +.sym 20115 o_led1_SB_LUT4_I1_O[2] +.sym 20116 io_pmod[3]$SB_IO_IN +.sym 20117 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 20118 o_led0$SB_IO_OUT +.sym 20122 o_led0_SB_LUT4_I1_O[1] +.sym 20123 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20124 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20126 io_pmod[1]$SB_IO_IN +.sym 20127 o_led0_SB_LUT4_I1_O[3] +.sym 20130 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 20132 o_led1_SB_LUT4_I1_I2[1] +.sym 20135 o_led1_SB_LUT4_I1_O[2] +.sym 20136 o_led0_SB_LUT4_I1_O[1] +.sym 20137 o_led1_SB_LUT4_I1_O[3] +.sym 20138 o_led1_SB_LUT4_I1_O[0] +.sym 20141 o_led0_SB_LUT4_I1_O[3] +.sym 20142 o_led0_SB_LUT4_I1_O[2] +.sym 20143 o_led0_SB_LUT4_I1_O[0] +.sym 20144 o_led0_SB_LUT4_I1_O[1] +.sym 20147 io_pmod[1]$SB_IO_IN +.sym 20148 o_shdn_rx_lna$SB_IO_OUT +.sym 20149 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20150 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20153 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20154 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20159 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20160 io_pmod[3]$SB_IO_IN +.sym 20161 o_tr_vc2$SB_IO_OUT +.sym 20162 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20165 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 20166 o_led0_SB_LUT4_I1_O[1] +.sym 20167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 20168 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 20171 o_led1_SB_LUT4_I1_I2[1] +.sym 20172 o_led0$SB_IO_OUT +.sym 20173 io_ctrl_ins.pmod_dir_state[0] +.sym 20174 o_led1_SB_LUT4_I1_I3[3] +.sym 20175 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 20176 r_counter_$glb_clk -.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 20192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 20194 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20198 o_led0$SB_IO_OUT -.sym 20200 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20202 w_rx_data[3] -.sym 20203 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20208 w_rx_data[1] -.sym 20209 o_led1$SB_IO_OUT -.sym 20210 w_cs[1] -.sym 20211 w_cs[2] -.sym 20219 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 20220 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] -.sym 20221 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 20222 i_button_SB_LUT4_I0_O[1] -.sym 20223 w_fetch -.sym 20224 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20226 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20227 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] -.sym 20228 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] -.sym 20229 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] -.sym 20230 o_shdn_tx_lna$SB_IO_OUT -.sym 20231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] -.sym 20232 io_ctrl_ins.mixer_en_state -.sym 20233 o_tr_vc2$SB_IO_OUT -.sym 20234 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] -.sym 20236 w_cs[1] -.sym 20237 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 20238 io_pmod[2]$SB_IO_IN -.sym 20239 io_pmod[3]$SB_IO_IN -.sym 20240 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20241 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20243 w_load -.sym 20244 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20245 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 20248 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20249 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20250 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] -.sym 20252 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] -.sym 20253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] -.sym 20254 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 20259 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 20260 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] -.sym 20261 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20264 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] -.sym 20265 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] -.sym 20267 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20270 w_load -.sym 20271 w_fetch -.sym 20272 w_cs[1] -.sym 20273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20276 io_ctrl_ins.mixer_en_state -.sym 20277 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] -.sym 20278 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] -.sym 20279 i_button_SB_LUT4_I0_O[1] -.sym 20282 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20283 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 20284 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20285 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 20288 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20289 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20290 io_pmod[3]$SB_IO_IN -.sym 20291 o_tr_vc2$SB_IO_OUT -.sym 20294 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20295 o_shdn_tx_lna$SB_IO_OUT -.sym 20296 io_pmod[2]$SB_IO_IN -.sym 20297 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20187 io_ctrl_ins.pmod_dir_state[0] +.sym 20190 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20192 o_tr_vc2$SB_IO_OUT +.sym 20198 o_shdn_rx_lna$SB_IO_OUT +.sym 20200 io_ctrl_ins.rf_pin_state[2] +.sym 20206 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20210 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20211 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 20219 w_load +.sym 20224 w_rx_data[0] +.sym 20226 io_ctrl_ins.pmod_dir_state[3] +.sym 20230 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 20233 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20236 o_led1$SB_IO_OUT +.sym 20237 io_ctrl_ins.pmod_dir_state[1] +.sym 20238 w_cs[1] +.sym 20239 w_fetch +.sym 20240 i_rst_b$SB_IO_IN +.sym 20242 o_led1_SB_LUT4_I1_I2[1] +.sym 20244 i_config[0]$SB_IO_IN +.sym 20246 o_led1_SB_LUT4_I1_I3[3] +.sym 20252 o_led1_SB_LUT4_I1_I3[3] +.sym 20255 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20258 w_cs[1] +.sym 20259 w_load +.sym 20260 o_led1_SB_LUT4_I1_I2[1] +.sym 20261 w_fetch +.sym 20270 o_led1$SB_IO_OUT +.sym 20271 io_ctrl_ins.pmod_dir_state[1] +.sym 20272 o_led1_SB_LUT4_I1_I2[1] +.sym 20273 o_led1_SB_LUT4_I1_I3[3] +.sym 20277 w_rx_data[0] +.sym 20288 w_fetch +.sym 20289 i_rst_b$SB_IO_IN +.sym 20290 w_load +.sym 20291 w_cs[1] +.sym 20294 io_ctrl_ins.pmod_dir_state[3] +.sym 20295 i_config[0]$SB_IO_IN +.sym 20296 o_led1_SB_LUT4_I1_I2[1] +.sym 20297 o_led1_SB_LUT4_I1_I3[3] +.sym 20298 smi_ctrl_ins.r_dir_SB_DFFER_Q_E .sym 20299 r_counter_$glb_clk -.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20313 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 20318 o_shdn_tx_lna$SB_IO_OUT -.sym 20320 io_ctrl_ins.mixer_en_state -.sym 20323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 20329 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20342 w_fetch -.sym 20343 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] -.sym 20344 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20346 w_rx_data[0] -.sym 20347 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20349 w_rx_data[2] -.sym 20354 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] -.sym 20355 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 20357 w_load -.sym 20360 io_ctrl_ins.pmod_dir_state[3] -.sym 20362 w_rx_data[3] -.sym 20364 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20367 i_config[0]$SB_IO_IN -.sym 20368 i_rst_b$SB_IO_IN -.sym 20370 w_cs[1] -.sym 20372 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20373 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] -.sym 20375 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20376 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] -.sym 20377 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 20378 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20381 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] -.sym 20382 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20383 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20384 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] -.sym 20389 w_rx_data[3] -.sym 20393 w_cs[1] -.sym 20394 w_fetch -.sym 20395 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20396 w_load -.sym 20402 w_rx_data[2] -.sym 20405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20406 i_config[0]$SB_IO_IN -.sym 20407 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 20408 io_ctrl_ins.pmod_dir_state[3] -.sym 20411 w_load -.sym 20412 i_rst_b$SB_IO_IN -.sym 20413 w_fetch -.sym 20414 w_cs[1] -.sym 20418 w_rx_data[0] -.sym 20421 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20422 r_counter_$glb_clk -.sym 20437 o_tr_vc1_b$SB_IO_OUT -.sym 20440 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20441 o_tr_vc2$SB_IO_OUT -.sym 20445 o_rx_h_tx_l_b$SB_IO_OUT -.sym 20453 i_config[0]$SB_IO_IN -.sym 20471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20476 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 20478 w_rx_data[0] -.sym 20480 w_rx_data[1] -.sym 20486 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20507 w_rx_data[0] -.sym 20531 w_rx_data[1] -.sym 20536 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20537 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 20544 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 20300 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 20314 io_ctrl_ins.rf_pin_state[5] +.sym 20318 io_ctrl_ins.rf_pin_state[7] +.sym 20342 i_glob_clock$SB_IO_IN +.sym 20344 i_config[1]$SB_IO_IN +.sym 20345 o_led1_SB_LUT4_I1_I3[1] +.sym 20346 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 20347 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 20349 o_led1_SB_LUT4_I1_I3[3] +.sym 20350 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 20352 o_led1_SB_LUT4_I1_I2[2] +.sym 20353 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 20355 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 20357 o_led1_SB_LUT4_I1_I2[1] +.sym 20358 o_led1_SB_LUT4_I1_I2[0] +.sym 20367 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 20368 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 20371 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 20381 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 20382 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 20383 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 20384 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 20399 o_led1_SB_LUT4_I1_I2[1] +.sym 20400 o_led1_SB_LUT4_I1_I2[2] +.sym 20401 o_led1_SB_LUT4_I1_I2[0] +.sym 20411 o_led1_SB_LUT4_I1_I2[1] +.sym 20412 o_led1_SB_LUT4_I1_I3[3] +.sym 20413 i_config[1]$SB_IO_IN +.sym 20414 o_led1_SB_LUT4_I1_I3[1] +.sym 20417 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 20418 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 20419 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 20420 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 20421 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 20422 i_glob_clock$SB_IO_IN +.sym 20436 i_glob_clock$SB_IO_IN +.sym 20438 i_config[1]$SB_IO_IN +.sym 20451 o_led1$SB_IO_OUT +.sym 20476 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20477 i_config_SB_LUT4_I0_2_O[3] +.sym 20478 i_button_SB_LUT4_I0_O[1] +.sym 20479 i_config_SB_LUT4_I0_2_O[2] +.sym 20480 o_tr_vc1_b$SB_IO_OUT +.sym 20522 i_button_SB_LUT4_I0_O[1] +.sym 20523 i_config_SB_LUT4_I0_2_O[3] +.sym 20524 o_tr_vc1_b$SB_IO_OUT +.sym 20525 i_config_SB_LUT4_I0_2_O[2] +.sym 20544 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 20545 r_counter_$glb_clk -.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 20569 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 20571 i_config[0]$SB_IO_IN .sym 20672 i_config[0]$SB_IO_IN -.sym 20698 o_led1$SB_IO_OUT .sym 20748 w_smi_data_output[5] -.sym 20750 o_led0$SB_IO_OUT +.sym 20750 w_smi_data_direction .sym 20751 $PACKER_VCC_NET -.sym 20756 $PACKER_VCC_NET -.sym 20766 w_smi_data_output[5] -.sym 20769 o_led0$SB_IO_OUT -.sym 20771 smi_ctrl_ins.tx_reg_state[2] -.sym 20772 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 20773 smi_ctrl_ins.tx_reg_state[1] -.sym 20774 smi_ctrl_ins.tx_reg_state[0] -.sym 20775 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 20776 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 20777 smi_ctrl_ins.tx_reg_state[3] +.sym 20754 w_smi_data_direction +.sym 20759 $PACKER_VCC_NET +.sym 20761 w_smi_data_output[5] +.sym 20771 tx_fifo.rd_addr_gray_wr[4] +.sym 20773 i_smi_soe_se$SB_IO_IN +.sym 20774 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 20782 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 20786 rx_fifo.wr_addr[6] +.sym 20802 i_sck$SB_IO_IN +.sym 20804 w_smi_data_input[7] +.sym 20810 rx_fifo.mem_i.0.1_WDATA_3 +.sym 20812 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 20813 rx_fifo.wr_addr[3] +.sym 20814 $PACKER_VCC_NET +.sym 20815 rx_fifo.wr_addr[0] +.sym 20816 rx_fifo.wr_addr[8] +.sym 20819 rx_fifo.wr_addr[4] +.sym 20824 rx_fifo.wr_addr[9] +.sym 20826 rx_fifo.wr_addr[6] +.sym 20828 rx_fifo.wr_addr[1] +.sym 20829 rx_fifo.wr_addr[7] +.sym 20830 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 20832 rx_fifo.mem_i.0.1_WDATA_2 +.sym 20840 rx_fifo.wr_addr[5] .sym 20844 i_mosi$SB_IO_IN -.sym 20847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 20848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 20849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 20850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 20851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 20852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 20853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 20888 w_smi_data_input[7] -.sym 20912 int_miso -.sym 20924 tx_fifo.wr_addr[8] -.sym 20927 i_rst_b$SB_IO_IN -.sym 20941 rx_fifo.wr_addr[9] -.sym 20984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 20985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 20986 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 20987 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 20988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 20989 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 20990 tx_fifo.wr_addr[9] -.sym 20991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 21026 tx_fifo.wr_addr[1] -.sym 21033 tx_fifo.wr_addr[1] -.sym 21039 rx_fifo.rd_addr[5] -.sym 21040 rx_fifo.rd_addr[1] -.sym 21043 $PACKER_VCC_NET -.sym 21044 rx_fifo.rd_addr[3] -.sym 21045 int_miso -.sym 21046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 21047 $PACKER_VCC_NET -.sym 21048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 21056 rx_fifo.mem_i.0.1_WDATA_2 -.sym 21058 $PACKER_VCC_NET -.sym 21060 rx_fifo.wr_addr[6] -.sym 21063 rx_fifo.wr_addr[1] -.sym 21065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21067 rx_fifo.wr_addr[8] -.sym 21068 rx_fifo.wr_addr[3] -.sym 21069 rx_fifo.wr_addr[4] -.sym 21071 rx_fifo.wr_addr[7] -.sym 21077 rx_fifo.wr_addr[0] -.sym 21081 rx_fifo.mem_i.0.1_WDATA_3 -.sym 21082 rx_fifo.wr_addr[5] -.sym 21083 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 21084 rx_fifo.wr_addr[9] -.sym 21086 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 21087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 21088 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 21089 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 21090 tx_fifo.wr_addr_gray_rd[9] -.sym 21091 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 21092 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 21093 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 21102 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 20847 tx_fifo.rd_addr_gray[2] +.sym 20848 tx_fifo.rd_addr[7] +.sym 20849 tx_fifo.rd_addr_gray[6] +.sym 20850 tx_fifo.rd_addr_gray[4] +.sym 20851 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 20852 tx_fifo.rd_addr_gray[5] +.sym 20862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 20863 rx_fifo.wr_addr[3] +.sym 20865 rx_fifo.wr_addr[4] +.sym 20866 rx_fifo.wr_addr[5] +.sym 20867 rx_fifo.wr_addr[6] +.sym 20868 rx_fifo.wr_addr[7] +.sym 20869 rx_fifo.wr_addr[8] +.sym 20870 rx_fifo.wr_addr[9] +.sym 20871 rx_fifo.wr_addr[1] +.sym 20872 rx_fifo.wr_addr[0] +.sym 20873 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 20874 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 20876 rx_fifo.mem_i.0.1_WDATA_3 +.sym 20880 rx_fifo.mem_i.0.1_WDATA_2 +.sym 20883 $PACKER_VCC_NET +.sym 20898 rx_fifo.mem_i.0.1_WDATA_3 +.sym 20906 rx_fifo.mem_i.0.1_WDATA_2 +.sym 20915 rx_fifo.wr_addr[5] +.sym 20918 $PACKER_VCC_NET +.sym 20922 rx_fifo.rd_addr[3] +.sym 20926 rx_fifo.rd_addr[4] +.sym 20928 o_miso_$_TBUF__Y_E +.sym 20929 rx_fifo.wr_addr[7] +.sym 20932 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 20933 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 20938 int_miso +.sym 20939 i_mosi$SB_IO_IN +.sym 20942 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 20957 rx_fifo.rd_addr[7] +.sym 20958 rx_fifo.rd_addr[8] +.sym 20963 rx_fifo.rd_addr[1] +.sym 20966 rx_fifo.rd_addr[9] +.sym 20968 rx_fifo.mem_i.0.1_WDATA +.sym 20970 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 20972 $PACKER_VCC_NET +.sym 20974 rx_fifo.rd_addr[2] +.sym 20976 rx_fifo.rd_addr[3] +.sym 20977 rx_fifo.rd_addr[6] +.sym 20978 rx_fifo.rd_addr[5] +.sym 20979 rx_fifo.mem_i.0.1_WDATA_1 +.sym 20981 rx_fifo.rd_addr[4] +.sym 20982 rx_fifo.rd_addr[0] +.sym 20984 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 20985 tx_fifo.rd_addr_gray_wr[6] +.sym 20986 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 20987 tx_fifo.rd_addr_gray_wr[2] +.sym 20989 tx_fifo.rd_addr_gray_wr[5] +.sym 20991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 21000 rx_fifo.rd_addr[2] +.sym 21001 rx_fifo.rd_addr[3] +.sym 21003 rx_fifo.rd_addr[4] +.sym 21004 rx_fifo.rd_addr[5] +.sym 21005 rx_fifo.rd_addr[6] +.sym 21006 rx_fifo.rd_addr[7] +.sym 21007 rx_fifo.rd_addr[8] +.sym 21008 rx_fifo.rd_addr[9] +.sym 21009 rx_fifo.rd_addr[1] +.sym 21010 rx_fifo.rd_addr[0] +.sym 21011 r_counter_$glb_clk +.sym 21012 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 21013 $PACKER_VCC_NET +.sym 21017 rx_fifo.mem_i.0.1_WDATA +.sym 21021 rx_fifo.mem_i.0.1_WDATA_1 +.sym 21028 w_rx_fifo_pulled_data[23] +.sym 21030 w_rx_fifo_pulled_data[21] +.sym 21032 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 21034 rx_fifo.rd_addr[9] +.sym 21038 tx_fifo.rd_addr[7] +.sym 21039 rx_fifo.rd_addr[0] +.sym 21044 rx_fifo.rd_addr[5] +.sym 21046 rx_fifo.wr_addr[8] +.sym 21054 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 21055 rx_fifo.wr_addr[5] +.sym 21056 rx_fifo.wr_addr[8] +.sym 21062 rx_fifo.wr_addr[0] +.sym 21066 rx_fifo.wr_addr[9] +.sym 21067 $PACKER_VCC_NET +.sym 21072 rx_fifo.wr_addr[1] +.sym 21074 rx_fifo.wr_addr[6] +.sym 21076 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21077 rx_fifo.wr_addr[3] +.sym 21078 rx_fifo.wr_addr[7] +.sym 21079 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21081 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 21083 rx_fifo.wr_addr[4] +.sym 21090 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 21091 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 21092 tx_fifo.wr_addr[8] +.sym 21102 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] .sym 21103 rx_fifo.wr_addr[3] .sym 21105 rx_fifo.wr_addr[4] .sym 21106 rx_fifo.wr_addr[5] @@ -10107,38 +10412,34 @@ .sym 21111 rx_fifo.wr_addr[1] .sym 21112 rx_fifo.wr_addr[0] .sym 21113 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21114 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21116 rx_fifo.mem_i.0.1_WDATA_3 -.sym 21120 rx_fifo.mem_i.0.1_WDATA_2 +.sym 21114 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 21116 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21120 rx_fifo.mem_i.0.3_WDATA_2 .sym 21123 $PACKER_VCC_NET -.sym 21129 rx_fifo.wr_addr[1] -.sym 21131 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21132 rx_fifo.mem_i.0.1_WDATA_2 -.sym 21136 rx_fifo.wr_addr[3] -.sym 21139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 21140 $PACKER_VCC_NET -.sym 21141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 21146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 21150 rx_fifo.wr_addr[3] -.sym 21151 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21157 rx_fifo.rd_addr[0] -.sym 21158 rx_fifo.rd_addr[6] -.sym 21160 rx_fifo.rd_addr[4] +.sym 21128 rx_fifo.wr_addr[0] +.sym 21130 w_rx_fifo_pulled_data[30] +.sym 21139 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 21140 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 21141 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 21160 rx_fifo.rd_addr[6] +.sym 21162 rx_fifo.rd_addr[2] .sym 21164 rx_fifo.rd_addr[7] -.sym 21167 rx_fifo.rd_addr[2] -.sym 21169 rx_fifo.rd_addr[8] -.sym 21170 rx_fifo.rd_addr[9] -.sym 21171 rx_fifo.mem_i.0.1_WDATA_1 -.sym 21172 rx_fifo.mem_i.0.1_WDATA -.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21177 rx_fifo.rd_addr[5] -.sym 21178 rx_fifo.rd_addr[1] -.sym 21182 rx_fifo.rd_addr[3] -.sym 21185 $PACKER_VCC_NET -.sym 21190 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 21192 w_tx_fifo_full -.sym 21193 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 21195 smi_ctrl_ins.r_fifo_push_1 +.sym 21166 rx_fifo.rd_addr[3] +.sym 21167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 21169 rx_fifo.mem_i.0.3_WDATA +.sym 21171 rx_fifo.rd_addr[1] +.sym 21174 rx_fifo.rd_addr[8] +.sym 21176 $PACKER_VCC_NET +.sym 21177 rx_fifo.rd_addr[0] +.sym 21180 rx_fifo.rd_addr[9] +.sym 21182 rx_fifo.rd_addr[5] +.sym 21185 rx_fifo.rd_addr[4] +.sym 21187 rx_fifo.mem_i.0.3_WDATA_1 +.sym 21188 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 21189 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 21191 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 21192 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 21193 lvds_tx_inst.r_pulled_SB_LUT4_I3_O .sym 21204 rx_fifo.rd_addr[2] .sym 21205 rx_fifo.rd_addr[3] .sym 21207 rx_fifo.rd_addr[4] @@ -10150,2553 +10451,2419 @@ .sym 21213 rx_fifo.rd_addr[1] .sym 21214 rx_fifo.rd_addr[0] .sym 21215 r_counter_$glb_clk -.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] .sym 21217 $PACKER_VCC_NET -.sym 21221 rx_fifo.mem_i.0.1_WDATA -.sym 21225 rx_fifo.mem_i.0.1_WDATA_1 -.sym 21232 w_rx_fifo_pulled_data[23] -.sym 21234 tx_fifo.wr_addr[1] -.sym 21236 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 21221 rx_fifo.mem_i.0.3_WDATA +.sym 21225 rx_fifo.mem_i.0.3_WDATA_1 +.sym 21231 tx_fifo.wr_addr[8] +.sym 21232 rx_fifo.rd_addr[3] +.sym 21233 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 21236 rx_fifo.rd_addr[6] +.sym 21238 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 21239 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] .sym 21240 rx_fifo.rd_addr[7] -.sym 21241 rx_fifo.rd_addr[0] -.sym 21242 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 21245 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 21248 tx_fifo.rd_addr_gray_wr[9] -.sym 21250 spi_if_ins.spi.r2_rx_done -.sym 21259 rx_fifo.wr_addr[7] -.sym 21260 rx_fifo.mem_q.0.1_WDATA_3 -.sym 21262 rx_fifo.wr_addr[8] -.sym 21267 rx_fifo.mem_q.0.1_WDATA_2 -.sym 21269 rx_fifo.wr_addr[6] -.sym 21270 rx_fifo.wr_addr[5] -.sym 21271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 21273 rx_fifo.wr_addr[4] -.sym 21274 rx_fifo.wr_addr[1] -.sym 21275 rx_fifo.wr_addr[9] -.sym 21278 $PACKER_VCC_NET -.sym 21282 rx_fifo.wr_addr[0] -.sym 21285 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21288 rx_fifo.wr_addr[3] -.sym 21290 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 21291 o_smi_read_req$SB_IO_OUT -.sym 21292 spi_if_ins.spi.r2_rx_done -.sym 21296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 21306 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 21307 rx_fifo.wr_addr[3] -.sym 21309 rx_fifo.wr_addr[4] -.sym 21310 rx_fifo.wr_addr[5] -.sym 21311 rx_fifo.wr_addr[6] -.sym 21312 rx_fifo.wr_addr[7] -.sym 21313 rx_fifo.wr_addr[8] -.sym 21314 rx_fifo.wr_addr[9] -.sym 21315 rx_fifo.wr_addr[1] -.sym 21316 rx_fifo.wr_addr[0] -.sym 21317 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21318 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21320 rx_fifo.mem_q.0.1_WDATA_3 -.sym 21324 rx_fifo.mem_q.0.1_WDATA_2 -.sym 21327 $PACKER_VCC_NET -.sym 21336 rx_fifo.mem_q.0.1_WDATA_3 -.sym 21343 rx_fifo.mem_q.0.1_WDATA_2 -.sym 21348 rx_fifo.wr_addr[9] -.sym 21349 smi_ctrl_ins.r_fifo_push -.sym 21355 rx_fifo.wr_addr[8] -.sym 21360 rx_fifo.rd_addr[1] -.sym 21362 rx_fifo.rd_addr[8] -.sym 21363 rx_fifo.rd_addr[7] -.sym 21368 rx_fifo.rd_addr[3] -.sym 21369 rx_fifo.rd_addr[2] -.sym 21370 rx_fifo.rd_addr[0] -.sym 21373 rx_fifo.rd_addr[4] -.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21380 rx_fifo.mem_q.0.1_WDATA_1 -.sym 21381 rx_fifo.rd_addr[5] -.sym 21387 rx_fifo.rd_addr[6] -.sym 21389 $PACKER_VCC_NET -.sym 21390 rx_fifo.rd_addr[9] -.sym 21391 rx_fifo.mem_q.0.1_WDATA -.sym 21393 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 21395 o_miso_$_TBUF__Y_E -.sym 21396 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 21408 rx_fifo.rd_addr[2] -.sym 21409 rx_fifo.rd_addr[3] -.sym 21411 rx_fifo.rd_addr[4] -.sym 21412 rx_fifo.rd_addr[5] -.sym 21413 rx_fifo.rd_addr[6] -.sym 21414 rx_fifo.rd_addr[7] -.sym 21415 rx_fifo.rd_addr[8] -.sym 21416 rx_fifo.rd_addr[9] -.sym 21417 rx_fifo.rd_addr[1] -.sym 21418 rx_fifo.rd_addr[0] -.sym 21419 r_counter_$glb_clk -.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21421 $PACKER_VCC_NET -.sym 21425 rx_fifo.mem_q.0.1_WDATA -.sym 21429 rx_fifo.mem_q.0.1_WDATA_1 -.sym 21434 rx_fifo.rd_addr[3] -.sym 21435 rx_fifo.rd_addr[2] -.sym 21438 rx_fifo.rd_addr[8] -.sym 21441 rx_fifo.rd_addr[4] -.sym 21447 rx_fifo.rd_addr[5] -.sym 21448 int_miso -.sym 21455 $PACKER_VCC_NET -.sym 21456 o_led0$SB_IO_OUT -.sym 21462 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21463 rx_fifo.wr_addr[5] -.sym 21464 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21470 rx_fifo.wr_addr[3] -.sym 21471 rx_fifo.wr_addr[6] -.sym 21473 rx_fifo.wr_addr[4] -.sym 21474 rx_fifo.wr_addr[0] -.sym 21475 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21477 rx_fifo.wr_addr[1] -.sym 21479 rx_fifo.wr_addr[7] -.sym 21480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 21482 $PACKER_VCC_NET -.sym 21486 rx_fifo.wr_addr[9] -.sym 21493 rx_fifo.wr_addr[8] -.sym 21494 spi_if_ins.spi.r_rx_byte[4] -.sym 21495 spi_if_ins.spi.r_rx_byte[5] -.sym 21496 spi_if_ins.spi.r_rx_byte[2] -.sym 21497 spi_if_ins.spi.r_rx_byte[6] -.sym 21498 spi_if_ins.spi.r_rx_byte[7] -.sym 21499 spi_if_ins.spi.r_rx_byte[0] -.sym 21500 spi_if_ins.spi.r_rx_byte[3] -.sym 21501 spi_if_ins.spi.r_rx_byte[1] -.sym 21510 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 21511 rx_fifo.wr_addr[3] -.sym 21513 rx_fifo.wr_addr[4] -.sym 21514 rx_fifo.wr_addr[5] -.sym 21515 rx_fifo.wr_addr[6] -.sym 21516 rx_fifo.wr_addr[7] -.sym 21517 rx_fifo.wr_addr[8] -.sym 21518 rx_fifo.wr_addr[9] -.sym 21519 rx_fifo.wr_addr[1] -.sym 21520 rx_fifo.wr_addr[0] -.sym 21521 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21522 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21524 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21528 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21531 $PACKER_VCC_NET -.sym 21536 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 21542 rx_fifo.wr_addr[0] -.sym 21543 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21545 rx_fifo.wr_addr[1] -.sym 21546 rx_fifo.wr_addr[3] -.sym 21547 rx_fifo.wr_addr[5] -.sym 21564 rx_fifo.rd_addr[8] -.sym 21568 rx_fifo.rd_addr[6] -.sym 21570 rx_fifo.rd_addr[2] -.sym 21571 rx_fifo.rd_addr[5] -.sym 21572 rx_fifo.rd_addr[7] -.sym 21573 rx_fifo.rd_addr[1] -.sym 21574 rx_fifo.rd_addr[0] -.sym 21575 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21577 rx_fifo.mem_i.0.3_WDATA -.sym 21578 rx_fifo.rd_addr[9] -.sym 21579 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21588 rx_fifo.rd_addr[3] -.sym 21589 rx_fifo.rd_addr[4] -.sym 21593 $PACKER_VCC_NET +.sym 21242 $PACKER_VCC_NET +.sym 21251 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 21296 spi_if_ins.spi.r_rx_done +.sym 21332 tx_fifo.wr_addr[1] +.sym 21333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 21341 w_tx_fifo_full +.sym 21345 i_mosi$SB_IO_IN +.sym 21346 int_miso +.sym 21350 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 21352 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 21398 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 21399 int_miso +.sym 21442 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 21446 rx_fifo.wr_addr[8] +.sym 21494 spi_if_ins.spi.r_rx_byte[0] +.sym 21495 spi_if_ins.spi.r_rx_byte[1] +.sym 21496 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 21497 spi_if_ins.spi.r_rx_byte[2] +.sym 21499 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 21501 spi_if_ins.spi.r_rx_byte[5] .sym 21596 spi_if_ins.w_rx_data[5] -.sym 21597 spi_if_ins.w_rx_data[6] -.sym 21598 spi_if_ins.w_rx_data[2] -.sym 21599 spi_if_ins.w_rx_data[1] -.sym 21600 spi_if_ins.w_rx_data[4] -.sym 21601 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 21602 spi_if_ins.w_rx_data[0] -.sym 21603 spi_if_ins.w_rx_data[3] -.sym 21612 rx_fifo.rd_addr[2] -.sym 21613 rx_fifo.rd_addr[3] -.sym 21615 rx_fifo.rd_addr[4] -.sym 21616 rx_fifo.rd_addr[5] -.sym 21617 rx_fifo.rd_addr[6] -.sym 21618 rx_fifo.rd_addr[7] -.sym 21619 rx_fifo.rd_addr[8] -.sym 21620 rx_fifo.rd_addr[9] -.sym 21621 rx_fifo.rd_addr[1] -.sym 21622 rx_fifo.rd_addr[0] -.sym 21623 r_counter_$glb_clk -.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21625 $PACKER_VCC_NET -.sym 21629 rx_fifo.mem_i.0.3_WDATA -.sym 21633 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21634 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 21639 rx_fifo.rd_addr[1] -.sym 21640 w_rx_fifo_pulled_data[31] -.sym 21641 rx_fifo.wr_addr[6] -.sym 21642 w_rx_fifo_pulled_data[29] -.sym 21643 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 21644 i_glob_clock$SB_IO_IN -.sym 21647 rx_fifo.rd_addr[5] -.sym 21648 rx_fifo.rd_addr[7] -.sym 21652 w_rx_data[7] -.sym 21653 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 21655 spi_if_ins.w_rx_data[0] +.sym 21597 spi_if_ins.w_rx_data[0] +.sym 21598 spi_if_ins.w_rx_data[4] +.sym 21599 spi_if_ins.w_rx_data[3] +.sym 21600 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 21601 spi_if_ins.w_rx_data[2] +.sym 21602 spi_if_ins.w_rx_data[6] +.sym 21603 spi_if_ins.w_rx_data[1] +.sym 21651 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 21653 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 21655 spi_if_ins.w_rx_data[6] +.sym 21656 spi_if_ins.r_tx_byte[7] +.sym 21658 w_rx_data[0] .sym 21659 spi_if_ins.w_rx_data[5] -.sym 21661 spi_if_ins.w_rx_data[6] -.sym 21704 w_rx_data[0] -.sym 21705 w_rx_data[7] -.sym 21743 spi_if_ins.w_rx_data[1] -.sym 21749 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 21751 spi_if_ins.w_rx_data[2] -.sym 21752 i_glob_clock$SB_IO_IN -.sym 21756 w_rx_data[2] -.sym 21757 w_rx_data[0] -.sym 21800 w_rx_data[2] -.sym 21801 w_rx_data[1] -.sym 21802 w_rx_data[5] -.sym 21803 w_rx_data[4] -.sym 21804 w_rx_data[6] -.sym 21806 w_rx_data[3] -.sym 21843 io_pmod[3]$SB_IO_IN -.sym 21856 o_led0$SB_IO_OUT -.sym 21863 w_rx_data[2] -.sym 21865 w_rx_data[1] -.sym 21905 io_pmod_SB_DFFE_Q_E -.sym 21909 o_led0$SB_IO_OUT -.sym 21945 w_rx_data[3] -.sym 21953 w_rx_data[1] -.sym 21958 w_rx_data[4] -.sym 21960 w_rx_data[6] -.sym 22004 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 22005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 22006 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 22007 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 22008 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 22009 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 22010 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 22011 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 22053 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 22055 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 22059 w_rx_data[2] -.sym 22060 w_rx_data[7] -.sym 22061 w_rx_data[1] -.sym 22106 io_ctrl_ins.rf_pin_state[0] -.sym 22107 io_ctrl_ins.rf_pin_state[4] -.sym 22108 io_ctrl_ins.rf_pin_state[7] -.sym 22109 io_ctrl_ins.rf_pin_state[6] -.sym 22110 io_ctrl_ins.rf_pin_state[2] -.sym 22111 io_ctrl_ins.rf_pin_state[3] -.sym 22112 io_ctrl_ins.rf_pin_state[1] -.sym 22113 io_ctrl_ins.rf_pin_state[5] -.sym 22156 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E -.sym 22214 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 22272 i_button_SB_LUT4_I0_O[1] -.sym 22352 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 22372 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 21698 w_rx_data[2] +.sym 21699 w_rx_data[1] +.sym 21700 w_rx_data[0] +.sym 21702 w_rx_data[3] +.sym 21741 io_pmod[3]$SB_IO_IN +.sym 21753 w_rx_data[3] +.sym 21761 w_rx_data[2] +.sym 21763 w_rx_data[1] +.sym 21800 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] +.sym 21801 io_ctrl_ins.rf_pin_state[1] +.sym 21804 io_ctrl_ins.rf_pin_state[4] +.sym 21806 io_pmod_SB_DFFE_Q_E +.sym 21807 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +.sym 21853 w_rx_data[0] +.sym 21854 i_rst_b$SB_IO_IN +.sym 21855 io_ctrl_ins.rf_pin_state[4] +.sym 21858 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 21860 w_rx_data[4] +.sym 21902 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 21903 o_tr_vc2$SB_IO_OUT +.sym 21905 o_led0_SB_LUT4_I1_O[2] +.sym 21906 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 21907 o_shdn_tx_lna$SB_IO_OUT +.sym 21909 o_shdn_rx_lna$SB_IO_OUT +.sym 21951 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 21958 o_rx_h_tx_l$SB_IO_OUT +.sym 21966 o_rx_h_tx_l_b$SB_IO_OUT +.sym 21967 o_tr_vc2$SB_IO_OUT +.sym 22004 io_ctrl_ins.mixer_en_state +.sym 22005 o_tr_vc1$SB_IO_OUT +.sym 22007 o_rx_h_tx_l_b$SB_IO_OUT +.sym 22008 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 22009 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 22010 o_tr_vc1_b$SB_IO_OUT +.sym 22011 o_rx_h_tx_l$SB_IO_OUT +.sym 22046 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 22048 o_led0_SB_LUT4_I1_O[0] +.sym 22054 o_led1_SB_LUT4_I1_I2[0] +.sym 22059 w_rx_data[0] +.sym 22062 o_led1_SB_LUT4_I1_O[0] +.sym 22064 spi_if_ins.r_tx_byte[7] +.sym 22069 o_tr_vc1$SB_IO_OUT +.sym 22107 io_ctrl_ins.rf_pin_state[0] +.sym 22111 io_ctrl_ins.rf_pin_state[6] +.sym 22150 o_led0$SB_IO_OUT +.sym 22151 o_led1_SB_LUT4_I1_I2[0] +.sym 22153 o_rx_h_tx_l$SB_IO_OUT +.sym 22155 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 22157 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 22158 o_led1$SB_IO_OUT +.sym 22164 w_rx_data[6] +.sym 22167 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 22208 w_rx_data[6] +.sym 22258 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 22262 i_rst_b$SB_IO_IN +.sym 22268 o_led0$SB_IO_OUT +.sym 22359 w_rx_data[6] .sym 22487 o_led1$SB_IO_OUT -.sym 22505 o_led1$SB_IO_OUT +.sym 22498 o_led1$SB_IO_OUT .sym 22517 int_miso .sym 22519 o_miso_$_TBUF__Y_E -.sym 22527 o_miso_$_TBUF__Y_E -.sym 22528 int_miso -.sym 22554 i_mosi$SB_IO_IN -.sym 22563 i_mosi$SB_IO_IN -.sym 22587 smi_ctrl_ins.tx_reg_state[1] -.sym 22588 smi_ctrl_ins.tx_reg_state[0] -.sym 22589 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 22592 i_rst_b$SB_IO_IN -.sym 22593 smi_ctrl_ins.tx_reg_state[2] -.sym 22597 w_smi_data_input[7] -.sym 22599 smi_ctrl_ins.tx_reg_state[3] -.sym 22600 smi_ctrl_ins.swe_and_reset -.sym 22601 i_rst_b$SB_IO_IN -.sym 22602 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 22605 w_smi_data_input[7] -.sym 22623 i_rst_b$SB_IO_IN -.sym 22625 w_smi_data_input[7] -.sym 22626 smi_ctrl_ins.tx_reg_state[0] -.sym 22630 smi_ctrl_ins.tx_reg_state[1] -.sym 22631 smi_ctrl_ins.tx_reg_state[2] -.sym 22632 w_smi_data_input[7] -.sym 22635 w_smi_data_input[7] -.sym 22636 smi_ctrl_ins.tx_reg_state[2] -.sym 22637 i_rst_b$SB_IO_IN -.sym 22641 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 22644 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 22647 w_smi_data_input[7] -.sym 22648 smi_ctrl_ins.tx_reg_state[0] -.sym 22649 i_rst_b$SB_IO_IN -.sym 22650 smi_ctrl_ins.tx_reg_state[3] -.sym 22653 smi_ctrl_ins.tx_reg_state[3] -.sym 22655 smi_ctrl_ins.tx_reg_state[0] -.sym 22656 i_rst_b$SB_IO_IN -.sym 22659 smi_ctrl_ins.tx_reg_state[1] -.sym 22661 i_rst_b$SB_IO_IN -.sym 22662 w_smi_data_input[7] -.sym 22664 smi_ctrl_ins.swe_and_reset +.sym 22536 o_miso_$_TBUF__Y_E +.sym 22537 int_miso +.sym 22588 tx_fifo.rd_addr_gray[4] +.sym 22609 tx_fifo.rd_addr_gray_wr[4] +.sym 22612 i_smi_soe_se$SB_IO_IN +.sym 22624 tx_fifo.rd_addr_gray[4] +.sym 22635 i_smi_soe_se$SB_IO_IN +.sym 22643 tx_fifo.rd_addr_gray_wr[4] +.sym 22664 r_counter_$glb_clk .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN -.sym 22699 w_smi_data_input[7] -.sym 22715 i_ss$SB_IO_IN +.sym 22671 smi_ctrl_ins.soe_and_reset +.sym 22675 smi_ctrl_ins.swe_and_reset +.sym 22707 i_ss$SB_IO_IN +.sym 22710 smi_ctrl_ins.swe_and_reset +.sym 22712 i_smi_swe_srw$SB_IO_IN .sym 22720 i_sck$SB_IO_IN -.sym 22723 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 22724 i_ss$SB_IO_IN +.sym 22726 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 22727 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] .sym 22729 i_sck$SB_IO_IN -.sym 22733 i_ss$SB_IO_IN -.sym 22734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22740 smi_ctrl_ins.swe_and_reset -.sym 22747 tx_fifo.wr_addr[1] -.sym 22750 tx_fifo.wr_addr[8] -.sym 22760 tx_fifo.wr_addr[1] -.sym 22763 tx_fifo.wr_addr[4] -.sym 22765 tx_fifo.wr_addr[3] -.sym 22767 tx_fifo.wr_addr[5] -.sym 22769 tx_fifo.wr_addr[7] -.sym 22775 tx_fifo.wr_addr[6] -.sym 22777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 22779 $nextpnr_ICESTORM_LC_1$O -.sym 22782 tx_fifo.wr_addr[1] -.sym 22785 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22788 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 22789 tx_fifo.wr_addr[1] -.sym 22791 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22794 tx_fifo.wr_addr[3] -.sym 22795 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22797 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22799 tx_fifo.wr_addr[4] -.sym 22801 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22803 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22806 tx_fifo.wr_addr[5] -.sym 22807 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22809 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22812 tx_fifo.wr_addr[6] -.sym 22813 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22815 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 22818 tx_fifo.wr_addr[7] -.sym 22819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 22821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 22824 tx_fifo.wr_addr[8] -.sym 22825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 22854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 22860 tx_fifo.rd_addr_gray_wr_r[8] -.sym 22865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 22870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 22871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 22872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 22877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 22881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 22882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22887 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22891 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 22893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 22895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 22897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 22899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22900 tx_fifo.wr_addr[9] -.sym 22901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 22904 tx_fifo.wr_addr[9] -.sym 22906 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 22909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 22916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 22917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 22918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 22923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 22924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22927 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 22928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 22930 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22936 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 22939 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 22945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 22946 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 22947 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 22948 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 22949 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 22730 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 22734 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 22736 smi_ctrl_ins.soe_and_reset +.sym 22753 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 22756 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 22766 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 22769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 22771 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 22773 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 22774 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 22788 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 22795 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 22798 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 22799 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 22806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 22812 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 22816 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 22826 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 22827 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 22828 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 22829 o_miso_$_TBUF__Y_E +.sym 22830 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 22831 smi_ctrl_ins.tx_reg_state[3] +.sym 22832 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 22833 smi_ctrl_ins.tx_reg_state[2] +.sym 22834 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 22835 smi_ctrl_ins.tx_reg_state[0] +.sym 22836 smi_ctrl_ins.tx_reg_state[1] +.sym 22849 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 22855 i_rst_b_SB_LUT4_I3_O +.sym 22859 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 22861 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 22862 o_miso_$_TBUF__Y_E +.sym 22871 tx_fifo.rd_addr_gray[2] +.sym 22873 tx_fifo.rd_addr_gray_wr[2] +.sym 22881 tx_fifo.rd_addr_gray[6] +.sym 22884 tx_fifo.rd_addr_gray[5] +.sym 22895 tx_fifo.rd_addr_gray_wr[6] +.sym 22899 tx_fifo.rd_addr_gray_wr[5] +.sym 22906 tx_fifo.rd_addr_gray_wr[2] +.sym 22912 tx_fifo.rd_addr_gray[6] +.sym 22917 tx_fifo.rd_addr_gray_wr[6] +.sym 22923 tx_fifo.rd_addr_gray[2] +.sym 22935 tx_fifo.rd_addr_gray[5] +.sym 22946 tx_fifo.rd_addr_gray_wr[5] .sym 22950 r_counter_$glb_clk -.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 22967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 22976 tx_fifo.wr_addr_gray_rd[9] -.sym 22995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 22996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 22998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 22999 tx_fifo.wr_addr[9] -.sym 23000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 23001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 23002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 23003 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 23005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 23007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 23008 tx_fifo.wr_addr[1] -.sym 23009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 23011 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 23013 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 23017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 23019 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 23020 tx_fifo.rd_addr_gray_wr_r[8] -.sym 23021 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 23024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 23026 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 23027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 23028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 23029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 23032 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 23034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 23035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23038 tx_fifo.wr_addr[1] -.sym 23039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23040 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 23041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 23045 tx_fifo.rd_addr_gray_wr_r[8] -.sym 23046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 23047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23050 tx_fifo.wr_addr[9] -.sym 23056 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 23059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 23063 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 23064 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 23065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 23068 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 23069 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 23070 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 23073 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 23086 w_rx_data[0] -.sym 23100 i_ss$SB_IO_IN +.sym 22957 smi_ctrl_ins.w_fifo_push_trigger +.sym 22963 spi_if_ins.w_rx_data[6] +.sym 22964 w_smi_data_input[7] +.sym 22966 i_rst_b$SB_IO_IN +.sym 22971 o_miso_$_TBUF__Y_E +.sym 22976 smi_ctrl_ins.swe_and_reset +.sym 22977 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 22980 w_tx_fifo_pull +.sym 22984 i_ss$SB_IO_IN +.sym 22994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 22995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 23003 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 23004 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 23008 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 23013 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 23018 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 23019 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 23050 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 23053 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 23056 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 23057 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 23058 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 23059 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 23064 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 23072 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 23073 r_counter_$glb_clk +.sym 23074 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 23075 w_tx_fifo_pull +.sym 23087 w_smi_data_input[7] +.sym 23098 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 23099 w_tx_fifo_empty +.sym 23101 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 23104 i_sck$SB_IO_IN -.sym 23105 i_ss$SB_IO_IN -.sym 23106 o_smi_read_req$SB_IO_OUT -.sym 23108 i_sck$SB_IO_IN -.sym 23116 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 23120 tx_fifo.wr_addr[1] -.sym 23121 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 23124 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23131 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 23136 w_tx_fifo_full -.sym 23139 smi_ctrl_ins.r_fifo_push_1 -.sym 23141 smi_ctrl_ins.r_fifo_push -.sym 23142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 23161 w_tx_fifo_full -.sym 23162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23163 tx_fifo.wr_addr[1] -.sym 23173 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 23174 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 23175 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 23176 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 23179 smi_ctrl_ins.r_fifo_push_1 -.sym 23180 smi_ctrl_ins.r_fifo_push -.sym 23182 w_tx_fifo_full -.sym 23194 smi_ctrl_ins.r_fifo_push +.sym 23116 i_rst_b$SB_IO_IN +.sym 23118 w_tx_fifo_full +.sym 23120 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23121 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 23124 tx_fifo.rd_addr_gray_wr[0] +.sym 23128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23129 tx_fifo.wr_addr[1] +.sym 23132 w_tx_fifo_pull +.sym 23133 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 23137 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 23143 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 23144 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23149 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 23150 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 23152 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 23156 tx_fifo.wr_addr[1] +.sym 23157 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23158 w_tx_fifo_full +.sym 23167 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 23168 tx_fifo.wr_addr[1] +.sym 23169 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23170 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23176 tx_fifo.rd_addr_gray_wr[0] +.sym 23180 i_rst_b$SB_IO_IN +.sym 23182 w_tx_fifo_pull .sym 23196 r_counter_$glb_clk -.sym 23197 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23203 o_miso_$_TBUF__Y_E -.sym 23204 spi_if_ins.spi.r_rx_done -.sym 23220 w_tx_fifo_full -.sym 23222 i_sck$SB_IO_IN -.sym 23223 i_ss$SB_IO_IN -.sym 23225 o_miso_$_TBUF__Y_E -.sym 23226 i_sck$SB_IO_IN +.sym 23210 tx_fifo.rd_addr_gray_wr[0] +.sym 23222 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23227 i_ss$SB_IO_IN +.sym 23228 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23229 smi_ctrl_ins.soe_and_reset .sym 23230 i_ss$SB_IO_IN -.sym 23241 tx_fifo.rd_addr_gray_wr[9] -.sym 23251 w_tx_fifo_full -.sym 23261 o_led0$SB_IO_OUT -.sym 23265 tx_fifo.rd_addr_gray_wr[0] -.sym 23266 w_rx_fifo_empty -.sym 23269 spi_if_ins.spi.r_rx_done -.sym 23273 tx_fifo.rd_addr_gray_wr[0] -.sym 23278 w_tx_fifo_full -.sym 23279 w_rx_fifo_empty -.sym 23281 o_led0$SB_IO_OUT -.sym 23285 spi_if_ins.spi.r_rx_done -.sym 23310 tx_fifo.rd_addr_gray_wr[9] -.sym 23319 r_counter_$glb_clk -.sym 23322 spi_if_ins.spi.r_rx_bit_count[1] -.sym 23323 spi_if_ins.spi.r_rx_bit_count[2] -.sym 23325 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 23326 spi_if_ins.spi.r_rx_bit_count[0] -.sym 23327 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23344 io_pmod[7]$SB_IO_IN -.sym 23352 w_rx_fifo_empty -.sym 23367 o_miso_$_TBUF__Y_E -.sym 23373 o_miso_$_TBUF__Y_E -.sym 23378 i_sck$SB_IO_IN -.sym 23379 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23386 i_mosi$SB_IO_IN -.sym 23403 i_mosi$SB_IO_IN -.sym 23413 o_miso_$_TBUF__Y_E -.sym 23422 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23441 o_miso_$_TBUF__Y_E -.sym 23442 i_sck$SB_IO_IN -.sym 23444 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23447 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23231 i_sck$SB_IO_IN +.sym 23233 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 23243 i_ss$SB_IO_IN +.sym 23244 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23250 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23264 i_sck$SB_IO_IN +.sym 23311 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23318 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23319 i_sck$SB_IO_IN +.sym 23320 i_ss$SB_IO_IN +.sym 23321 spi_if_ins.spi.r3_rx_done +.sym 23323 spi_if_ins.spi.SCKr[0] +.sym 23324 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23325 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23326 spi_if_ins.spi.r2_rx_done +.sym 23327 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23346 i_rst_b_SB_LUT4_I3_O +.sym 23352 o_miso_$_TBUF__Y_E +.sym 23369 spi_if_ins.r_tx_byte[7] +.sym 23373 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 23374 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 23382 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23388 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23389 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23392 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23393 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 23431 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23432 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23434 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 23438 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 23439 spi_if_ins.r_tx_byte[7] +.sym 23440 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23441 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 23442 r_counter_$glb_clk +.sym 23444 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23445 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23446 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23447 spi_if_ins.spi.r_temp_rx_byte[4] .sym 23448 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 23449 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23450 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23451 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23454 o_led0$SB_IO_OUT -.sym 23470 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 23486 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23494 i_sck$SB_IO_IN -.sym 23496 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23497 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23501 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23504 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23505 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 23506 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23508 i_mosi$SB_IO_IN -.sym 23516 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23518 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23525 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23533 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23538 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23542 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 23548 i_mosi$SB_IO_IN -.sym 23555 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23560 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23449 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23450 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23465 spi_if_ins.r_tx_byte[7] +.sym 23467 io_pmod[6]$SB_IO_IN +.sym 23470 w_rx_data[1] +.sym 23478 io_pmod_SB_DFFE_Q_E +.sym 23487 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23493 i_mosi$SB_IO_IN +.sym 23497 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23501 i_sck$SB_IO_IN +.sym 23502 i_ss$SB_IO_IN +.sym 23508 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23509 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23511 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23512 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23521 i_mosi$SB_IO_IN +.sym 23524 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23533 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23538 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23548 i_ss$SB_IO_IN +.sym 23550 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23561 spi_if_ins.spi.r_temp_rx_byte[4] .sym 23564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O .sym 23565 i_sck$SB_IO_IN -.sym 23580 i_glob_clock$SB_IO_IN -.sym 23591 spi_if_ins.w_rx_data[4] -.sym 23592 w_rx_data[0] -.sym 23597 spi_if_ins.w_rx_data[3] -.sym 23602 $io_pmod[3]$iobuf_i -.sym 23608 spi_if_ins.spi.r_rx_byte[4] -.sym 23609 spi_if_ins.spi.r_rx_byte[5] +.sym 23567 i_rst_b_SB_LUT4_I3_O +.sym 23568 spi_if_ins.spi.r_rx_byte[7] +.sym 23569 spi_if_ins.spi.r_rx_byte[4] +.sym 23571 spi_if_ins.spi.r_rx_byte[3] +.sym 23573 spi_if_ins.spi.r_rx_byte[6] +.sym 23579 i_mosi$SB_IO_IN +.sym 23581 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23590 i_glob_clock$SB_IO_IN +.sym 23591 $io_pmod[3]$iobuf_i +.sym 23593 io_pmod_SB_DFFE_Q_E +.sym 23595 spi_if_ins.w_rx_data[6] +.sym 23596 w_rx_data[2] +.sym 23598 w_rx_data[1] +.sym 23599 spi_if_ins.w_rx_data[5] +.sym 23609 spi_if_ins.spi.r_rx_byte[1] .sym 23610 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23612 spi_if_ins.spi.r_rx_byte[7] -.sym 23614 spi_if_ins.spi.r_rx_byte[3] -.sym 23615 spi_if_ins.spi.r_rx_byte[1] -.sym 23618 spi_if_ins.spi.r_rx_byte[2] -.sym 23619 spi_if_ins.spi.r_rx_byte[6] -.sym 23621 spi_if_ins.spi.r_rx_byte[0] +.sym 23615 spi_if_ins.spi.r_rx_byte[5] +.sym 23616 spi_if_ins.spi.r_rx_byte[0] +.sym 23619 spi_if_ins.spi.r_rx_byte[2] +.sym 23633 spi_if_ins.spi.r_rx_byte[7] +.sym 23634 spi_if_ins.spi.r_rx_byte[4] +.sym 23636 spi_if_ins.spi.r_rx_byte[3] +.sym 23638 spi_if_ins.spi.r_rx_byte[6] .sym 23642 spi_if_ins.spi.r_rx_byte[5] -.sym 23648 spi_if_ins.spi.r_rx_byte[6] -.sym 23656 spi_if_ins.spi.r_rx_byte[2] -.sym 23661 spi_if_ins.spi.r_rx_byte[1] -.sym 23667 spi_if_ins.spi.r_rx_byte[4] -.sym 23674 spi_if_ins.spi.r_rx_byte[7] -.sym 23677 spi_if_ins.spi.r_rx_byte[0] -.sym 23686 spi_if_ins.spi.r_rx_byte[3] +.sym 23649 spi_if_ins.spi.r_rx_byte[0] +.sym 23656 spi_if_ins.spi.r_rx_byte[4] +.sym 23659 spi_if_ins.spi.r_rx_byte[3] +.sym 23665 spi_if_ins.spi.r_rx_byte[7] +.sym 23672 spi_if_ins.spi.r_rx_byte[2] +.sym 23678 spi_if_ins.spi.r_rx_byte[6] +.sym 23683 spi_if_ins.spi.r_rx_byte[1] .sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 23688 r_counter_$glb_clk -.sym 23708 i_rst_b_SB_LUT4_I3_O -.sym 23715 spi_if_ins.w_rx_data[2] -.sym 23717 spi_if_ins.w_rx_data[1] +.sym 23696 $io_pmod[3]$iobuf_i +.sym 23710 i_rst_b$SB_IO_IN +.sym 23719 i_glob_clock$SB_IO_IN +.sym 23720 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23732 spi_if_ins.w_rx_data[0] +.sym 23734 spi_if_ins.w_rx_data[3] +.sym 23736 spi_if_ins.w_rx_data[2] +.sym 23738 spi_if_ins.w_rx_data[1] .sym 23742 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 23744 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 23745 spi_if_ins.w_rx_data[0] -.sym 23803 spi_if_ins.w_rx_data[0] -.sym 23807 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 23767 spi_if_ins.w_rx_data[2] +.sym 23770 spi_if_ins.w_rx_data[1] +.sym 23777 spi_if_ins.w_rx_data[0] +.sym 23789 spi_if_ins.w_rx_data[3] .sym 23810 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 23811 r_counter_$glb_clk -.sym 23814 $io_pmod[2]$iobuf_i -.sym 23816 $io_pmod[1]$iobuf_i -.sym 23818 $io_pmod[3]$iobuf_i -.sym 23846 w_rx_data[0] -.sym 23854 spi_if_ins.w_rx_data[5] -.sym 23863 spi_if_ins.w_rx_data[4] -.sym 23864 spi_if_ins.w_rx_data[6] -.sym 23869 spi_if_ins.w_rx_data[3] -.sym 23875 spi_if_ins.w_rx_data[2] -.sym 23877 spi_if_ins.w_rx_data[1] -.sym 23881 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 23888 spi_if_ins.w_rx_data[2] -.sym 23893 spi_if_ins.w_rx_data[1] -.sym 23899 spi_if_ins.w_rx_data[5] -.sym 23906 spi_if_ins.w_rx_data[4] -.sym 23914 spi_if_ins.w_rx_data[6] -.sym 23925 spi_if_ins.w_rx_data[3] -.sym 23933 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23816 $io_pmod[2]$iobuf_i +.sym 23818 $io_pmod[1]$iobuf_i +.sym 23819 $io_pmod[0]$iobuf_i +.sym 23828 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23829 w_rx_data[1] +.sym 23838 w_rx_data[0] +.sym 23842 w_rx_data[3] +.sym 23844 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 23845 io_ctrl_ins.pmod_dir_state[3] +.sym 23847 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 23854 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 23855 w_rx_data[1] +.sym 23862 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 23866 w_rx_data[3] +.sym 23870 o_led0_SB_LUT4_I1_O[0] +.sym 23871 i_rst_b$SB_IO_IN +.sym 23872 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 23874 o_led1_SB_LUT4_I1_I2[0] +.sym 23880 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 23883 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 23885 w_rx_data[4] +.sym 23887 o_led1_SB_LUT4_I1_I2[0] +.sym 23888 i_rst_b$SB_IO_IN +.sym 23889 o_led0_SB_LUT4_I1_O[0] +.sym 23890 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 23893 w_rx_data[1] +.sym 23911 w_rx_data[4] +.sym 23923 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 23924 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 23925 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 23931 w_rx_data[3] +.sym 23933 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O .sym 23934 r_counter_$glb_clk -.sym 23943 $io_pmod[0]$iobuf_i -.sym 23948 w_rx_data[2] -.sym 23952 w_rx_data[1] -.sym 23961 w_rx_data[5] -.sym 23969 w_rx_data[3] -.sym 23977 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 23978 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 23979 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 23989 w_rx_data[0] -.sym 23993 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 24028 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 24029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 24031 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 24052 w_rx_data[0] -.sym 24056 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 23938 io_ctrl_ins.pmod_dir_state[3] +.sym 23943 io_ctrl_ins.pmod_dir_state[0] +.sym 23967 o_tr_vc1$SB_IO_OUT +.sym 23968 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 23969 io_pmod_SB_DFFE_Q_E +.sym 23970 w_rx_data[1] +.sym 23977 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] +.sym 23979 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 23982 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 23984 o_led0_SB_LUT4_I1_O[0] +.sym 23985 io_ctrl_ins.mixer_en_state +.sym 23986 io_ctrl_ins.rf_pin_state[1] +.sym 23988 o_led1_SB_LUT4_I1_I2[0] +.sym 23989 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 23990 io_pmod[0]$SB_IO_IN +.sym 23992 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +.sym 23993 io_ctrl_ins.rf_pin_state[2] +.sym 23997 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 24001 o_led1_SB_LUT4_I1_O[0] +.sym 24007 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24010 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] +.sym 24013 o_led1_SB_LUT4_I1_O[0] +.sym 24016 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24017 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +.sym 24018 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24019 o_led1_SB_LUT4_I1_I2[0] +.sym 24028 io_ctrl_ins.mixer_en_state +.sym 24029 io_pmod[0]$SB_IO_IN +.sym 24030 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24031 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 24035 o_led0_SB_LUT4_I1_O[0] +.sym 24037 o_led1_SB_LUT4_I1_O[0] +.sym 24040 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24041 o_led1_SB_LUT4_I1_I2[0] +.sym 24042 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24043 io_ctrl_ins.rf_pin_state[2] +.sym 24052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24054 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24055 io_ctrl_ins.rf_pin_state[1] +.sym 24056 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O .sym 24057 r_counter_$glb_clk -.sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24062 o_shdn_tx_lna$SB_IO_OUT -.sym 24063 io_ctrl_ins.mixer_en_state -.sym 24072 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 24084 w_rx_data[0] -.sym 24085 o_rx_h_tx_l$SB_IO_OUT -.sym 24089 o_tr_vc1$SB_IO_OUT -.sym 24100 w_rx_data[2] -.sym 24102 w_rx_data[1] -.sym 24104 i_rst_b$SB_IO_IN -.sym 24106 w_rx_data[4] -.sym 24108 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24109 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E -.sym 24113 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 24116 w_rx_data[0] -.sym 24126 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 24129 w_rx_data[3] -.sym 24130 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 24135 w_rx_data[0] -.sym 24142 w_rx_data[1] -.sym 24147 w_rx_data[4] -.sym 24151 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 24154 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 24159 w_rx_data[2] -.sym 24164 w_rx_data[3] -.sym 24169 i_rst_b$SB_IO_IN -.sym 24170 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 24171 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 24172 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 24179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 24059 o_led1$SB_IO_OUT +.sym 24060 o_led0$SB_IO_OUT +.sym 24078 io_pmod[0]$SB_IO_IN +.sym 24083 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 24087 o_tr_vc1_b$SB_IO_OUT +.sym 24100 io_ctrl_ins.rf_pin_state[4] +.sym 24102 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24105 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 24106 o_led1_SB_LUT4_I1_I2[0] +.sym 24108 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24109 io_ctrl_ins.rf_pin_state[0] +.sym 24111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 24112 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24113 io_ctrl_ins.rf_pin_state[6] +.sym 24119 io_ctrl_ins.rf_pin_state[7] +.sym 24125 io_ctrl_ins.rf_pin_state[5] +.sym 24128 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 24133 o_led1_SB_LUT4_I1_I2[0] +.sym 24134 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24135 io_ctrl_ins.rf_pin_state[0] +.sym 24136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24139 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24140 io_ctrl_ins.rf_pin_state[5] +.sym 24141 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 24142 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24151 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 24152 io_ctrl_ins.rf_pin_state[6] +.sym 24153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24157 o_led1_SB_LUT4_I1_I2[0] +.sym 24159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24163 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24164 o_led1_SB_LUT4_I1_I2[0] +.sym 24165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24166 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24169 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24170 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 24171 io_ctrl_ins.rf_pin_state[4] +.sym 24172 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 24175 io_ctrl_ins.rf_pin_state[7] +.sym 24177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 24178 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O .sym 24180 r_counter_$glb_clk -.sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24182 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 24183 o_tr_vc1$SB_IO_OUT -.sym 24184 o_tr_vc1_b$SB_IO_OUT -.sym 24185 o_tr_vc2$SB_IO_OUT -.sym 24186 o_shdn_rx_lna$SB_IO_OUT -.sym 24187 o_rx_h_tx_l_b$SB_IO_OUT -.sym 24188 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 24189 o_rx_h_tx_l$SB_IO_OUT -.sym 24198 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 24200 i_rst_b$SB_IO_IN -.sym 24207 o_shdn_rx_lna$SB_IO_OUT -.sym 24225 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 24226 w_rx_data[4] -.sym 24228 w_rx_data[6] -.sym 24229 w_rx_data[7] -.sym 24230 w_rx_data[1] -.sym 24231 w_rx_data[5] -.sym 24236 w_rx_data[2] -.sym 24239 w_rx_data[3] -.sym 24251 w_rx_data[0] -.sym 24257 w_rx_data[0] -.sym 24264 w_rx_data[4] -.sym 24270 w_rx_data[7] -.sym 24274 w_rx_data[6] -.sym 24282 w_rx_data[2] -.sym 24287 w_rx_data[3] -.sym 24293 w_rx_data[1] -.sym 24298 w_rx_data[5] +.sym 24184 o_rx_h_tx_l_b$SB_IO_OUT +.sym 24197 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 24201 o_led1$SB_IO_OUT +.sym 24203 o_led0$SB_IO_OUT +.sym 24228 w_rx_data[0] +.sym 24231 w_rx_data[6] +.sym 24234 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 24264 w_rx_data[0] +.sym 24288 w_rx_data[6] .sym 24302 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O .sym 24303 r_counter_$glb_clk -.sym 24321 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 24351 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 24373 i_button_SB_LUT4_I0_O[1] -.sym 24415 i_button_SB_LUT4_I0_O[1] -.sym 24416 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 24323 o_tr_vc2$SB_IO_OUT +.sym 24357 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 24362 spi_if_ins.w_rx_data[6] +.sym 24379 spi_if_ins.w_rx_data[6] +.sym 24425 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 24426 r_counter_$glb_clk .sym 24596 o_led0$SB_IO_OUT -.sym 24618 o_led0$SB_IO_OUT -.sym 24655 i_ss$SB_IO_IN -.sym 24664 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 25100 o_smi_read_req$SB_IO_OUT -.sym 25261 o_miso_$_TBUF__Y_E +.sym 24620 o_led0$SB_IO_OUT +.sym 24621 i_rst_b$SB_IO_IN +.sym 24656 smi_ctrl_ins.swe_and_reset +.sym 24659 i_sck$SB_IO_IN +.sym 24856 i_smi_swe_srw$SB_IO_IN +.sym 24861 i_rst_b$SB_IO_IN +.sym 24871 i_smi_soe_se$SB_IO_IN +.sym 24893 i_smi_soe_se$SB_IO_IN +.sym 24894 i_rst_b$SB_IO_IN +.sym 24916 i_smi_swe_srw$SB_IO_IN +.sym 24918 i_rst_b$SB_IO_IN +.sym 24943 i_rst_b$SB_IO_IN +.sym 25011 smi_ctrl_ins.tx_reg_state[2] +.sym 25012 w_smi_data_input[7] +.sym 25013 smi_ctrl_ins.tx_reg_state[0] +.sym 25014 i_rst_b$SB_IO_IN +.sym 25017 smi_ctrl_ins.tx_reg_state[3] +.sym 25019 i_ss$SB_IO_IN +.sym 25020 w_smi_data_input[7] +.sym 25022 i_rst_b$SB_IO_IN +.sym 25024 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 25026 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 25032 smi_ctrl_ins.swe_and_reset +.sym 25038 smi_ctrl_ins.tx_reg_state[1] +.sym 25041 i_ss$SB_IO_IN +.sym 25047 smi_ctrl_ins.tx_reg_state[1] +.sym 25048 w_smi_data_input[7] +.sym 25049 smi_ctrl_ins.tx_reg_state[2] +.sym 25052 smi_ctrl_ins.tx_reg_state[1] +.sym 25054 w_smi_data_input[7] +.sym 25055 i_rst_b$SB_IO_IN +.sym 25058 smi_ctrl_ins.tx_reg_state[3] +.sym 25059 i_rst_b$SB_IO_IN +.sym 25060 w_smi_data_input[7] +.sym 25061 smi_ctrl_ins.tx_reg_state[0] +.sym 25065 w_smi_data_input[7] +.sym 25066 smi_ctrl_ins.tx_reg_state[0] +.sym 25067 i_rst_b$SB_IO_IN +.sym 25071 i_rst_b$SB_IO_IN +.sym 25072 smi_ctrl_ins.tx_reg_state[3] +.sym 25073 smi_ctrl_ins.tx_reg_state[0] +.sym 25077 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 25079 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 25083 smi_ctrl_ins.tx_reg_state[2] +.sym 25084 i_rst_b$SB_IO_IN +.sym 25085 w_smi_data_input[7] +.sym 25087 smi_ctrl_ins.swe_and_reset +.sym 25167 w_smi_data_input[7] +.sym 25175 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 25187 smi_ctrl_ins.swe_and_reset +.sym 25225 w_smi_data_input[7] +.sym 25242 smi_ctrl_ins.swe_and_reset +.sym 25243 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 25328 i_rst_b_SB_LUT4_I3_O +.sym 25334 w_tx_fifo_empty +.sym 25353 w_tx_fifo_empty +.sym 25396 i_rst_b_SB_LUT4_I3_O +.sym 25397 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 25398 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 25401 io_pmod[7]$SB_IO_IN -.sym 25478 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25481 i_sck$SB_IO_IN -.sym 25485 i_ss$SB_IO_IN -.sym 25491 i_ss$SB_IO_IN -.sym 25499 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 25537 i_ss$SB_IO_IN -.sym 25541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25551 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 25552 i_sck$SB_IO_IN -.sym 25553 i_ss$SB_IO_IN .sym 25554 io_pmod[3]$SB_IO_IN .sym 25556 io_pmod[6]$SB_IO_IN -.sym 25627 i_sck$SB_IO_IN -.sym 25631 i_ss$SB_IO_IN -.sym 25636 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25640 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25651 i_ss$SB_IO_IN -.sym 25653 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25659 $nextpnr_ICESTORM_LC_4$O -.sym 25662 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25665 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 25667 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25669 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25673 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25675 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 25684 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25685 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25686 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25687 i_ss$SB_IO_IN -.sym 25693 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25696 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25697 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25698 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25707 i_sck$SB_IO_IN -.sym 25708 i_ss$SB_IO_IN +.sym 25641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 25643 spi_if_ins.spi.r3_rx_done +.sym 25648 spi_if_ins.spi.r2_rx_done +.sym 25649 spi_if_ins.spi.r_rx_done +.sym 25653 spi_if_ins.spi.SCKr[0] +.sym 25655 i_sck$SB_IO_IN +.sym 25661 spi_if_ins.spi.r2_rx_done +.sym 25675 i_sck$SB_IO_IN +.sym 25680 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 25684 spi_if_ins.spi.r3_rx_done +.sym 25687 spi_if_ins.spi.r2_rx_done +.sym 25693 spi_if_ins.spi.r_rx_done +.sym 25699 spi_if_ins.spi.SCKr[0] +.sym 25707 r_counter_$glb_clk .sym 25711 i_glob_clock$SB_IO_IN -.sym 25719 $io_pmod[3]$iobuf_i -.sym 25782 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 25784 o_miso_$_TBUF__Y_E -.sym 25788 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25790 i_ss$SB_IO_IN -.sym 25791 i_sck$SB_IO_IN -.sym 25795 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 25801 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25802 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 25805 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 25817 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 25833 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 25725 $io_pmod[3]$iobuf_i +.sym 25782 i_sck$SB_IO_IN +.sym 25784 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 25785 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 25787 i_mosi$SB_IO_IN +.sym 25791 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 25793 o_miso_$_TBUF__Y_E +.sym 25796 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 25806 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 25811 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25817 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 25821 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 25828 i_mosi$SB_IO_IN +.sym 25836 spi_if_ins.spi.r_temp_rx_byte[3] .sym 25840 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25846 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 25851 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25852 i_ss$SB_IO_IN -.sym 25858 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25846 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 25854 spi_if_ins.spi.r_temp_rx_byte[4] .sym 25861 o_miso_$_TBUF__Y_E .sym 25862 i_sck$SB_IO_IN -.sym 25879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 25878 i_glob_clock$SB_IO_IN +.sym 25880 smi_ctrl_ins.soe_and_reset +.sym 25938 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 25941 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 25943 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 25948 i_rst_b$SB_IO_IN +.sym 25950 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25953 i_sck$SB_IO_IN +.sym 25955 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 25970 i_rst_b$SB_IO_IN +.sym 25979 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 25982 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25995 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 26006 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 26016 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 26017 i_sck$SB_IO_IN +.sym 26103 io_pmod_SB_DFFE_Q_E +.sym 26104 w_rx_data[3] +.sym 26164 w_rx_data[3] +.sym 26171 io_pmod_SB_DFFE_Q_E +.sym 26172 r_counter_$glb_clk .sym 26174 io_pmod[2]$SB_IO_IN .sym 26176 io_pmod[1]$SB_IO_IN -.sym 26247 w_rx_data[2] -.sym 26248 w_rx_data[1] -.sym 26261 w_rx_data[3] -.sym 26274 io_pmod_SB_DFFE_Q_E -.sym 26287 w_rx_data[2] -.sym 26300 w_rx_data[1] -.sym 26310 w_rx_data[3] +.sym 26258 io_pmod_SB_DFFE_Q_E +.sym 26263 w_rx_data[2] +.sym 26264 w_rx_data[1] +.sym 26265 w_rx_data[0] +.sym 26299 w_rx_data[2] +.sym 26312 w_rx_data[1] +.sym 26316 w_rx_data[0] .sym 26326 io_pmod_SB_DFFE_Q_E .sym 26327 r_counter_$glb_clk .sym 26329 io_pmod[0]$SB_IO_IN -.sym 26413 io_pmod_SB_DFFE_Q_E -.sym 26415 w_rx_data[0] -.sym 26480 w_rx_data[0] -.sym 26481 io_pmod_SB_DFFE_Q_E +.sym 26337 io_pmod[2]$SB_IO_IN +.sym 26407 w_rx_data[0] +.sym 26411 w_rx_data[3] +.sym 26413 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 26447 w_rx_data[3] +.sym 26479 w_rx_data[0] +.sym 26481 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 26482 r_counter_$glb_clk -.sym 26559 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26562 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26564 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26568 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 26570 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26573 io_ctrl_ins.rf_pin_state[0] -.sym 26585 io_ctrl_ins.rf_pin_state[2] -.sym 26608 io_ctrl_ins.rf_pin_state[2] -.sym 26609 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26610 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26611 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26614 io_ctrl_ins.rf_pin_state[0] -.sym 26615 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26616 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26617 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26636 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26557 w_rx_data[0] +.sym 26563 w_rx_data[1] +.sym 26568 o_led1_SB_DFFER_Q_E +.sym 26592 w_rx_data[1] +.sym 26597 w_rx_data[0] +.sym 26636 o_led1_SB_DFFER_Q_E .sym 26637 r_counter_$glb_clk -.sym 26715 io_ctrl_ins.rf_pin_state[6] -.sym 26719 io_ctrl_ins.rf_pin_state[5] -.sym 26720 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 26721 io_ctrl_ins.rf_pin_state[4] -.sym 26722 io_ctrl_ins.rf_pin_state[7] -.sym 26725 io_ctrl_ins.rf_pin_state[3] -.sym 26726 io_ctrl_ins.rf_pin_state[1] -.sym 26732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 26733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26738 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26739 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 26741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26742 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 26743 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26745 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 26746 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26747 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26751 io_ctrl_ins.rf_pin_state[5] -.sym 26752 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26753 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 26754 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26757 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26758 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 26759 io_ctrl_ins.rf_pin_state[4] -.sym 26760 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26763 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26764 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26765 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26766 io_ctrl_ins.rf_pin_state[3] -.sym 26770 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 26771 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26772 io_ctrl_ins.rf_pin_state[1] -.sym 26775 io_ctrl_ins.rf_pin_state[6] -.sym 26777 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 26778 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26782 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 26783 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 26787 io_ctrl_ins.rf_pin_state[7] -.sym 26789 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 26790 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 26791 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 26792 r_counter_$glb_clk +.sym 26638 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 26648 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 26652 o_led1_SB_DFFER_Q_E +.sym 26731 o_rx_h_tx_l_b$SB_IO_OUT +.sym 26760 o_rx_h_tx_l_b$SB_IO_OUT +.sym 26810 o_tr_vc1$SB_IO_OUT +.sym 26960 o_tr_vc1_b$SB_IO_OUT +.sym 27275 i_rst_b$SB_IO_IN .sym 27283 o_smi_read_req$SB_IO_OUT -.sym 27292 o_smi_read_req$SB_IO_OUT -.sym 27338 o_led0$SB_IO_OUT -.sym 27395 io_pmod[3]$SB_IO_IN +.sym 27301 o_smi_read_req$SB_IO_OUT +.sym 27365 io_pmod[3]$SB_IO_IN +.sym 27395 i_rst_b$SB_IO_IN +.sym 27397 i_glob_clock$SB_IO_IN .sym 27400 $io_pmod[3]$iobuf_i -.sym 27411 $io_pmod[3]$iobuf_i -.sym 27429 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 27444 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 27458 o_led0$SB_IO_OUT +.sym 27415 $io_pmod[3]$iobuf_i +.sym 27429 smi_ctrl_ins.soe_and_reset +.sym 27453 smi_ctrl_ins.soe_and_reset .sym 27459 i_rst_b_SB_LUT4_I3_O -.sym 27470 i_rst_b_SB_LUT4_I3_O +.sym 27477 i_rst_b_SB_LUT4_I3_O +.sym 27514 i_rst_b$SB_IO_IN +.sym 27516 i_glob_clock$SB_IO_IN .sym 27519 $io_pmod[2]$iobuf_i .sym 27522 $io_pmod[1]$iobuf_i -.sym 27531 $io_pmod[1]$iobuf_i -.sym 27537 $io_pmod[2]$iobuf_i +.sym 27533 $io_pmod[1]$iobuf_i +.sym 27539 $io_pmod[2]$iobuf_i .sym 27549 $io_pmod[0]$iobuf_i -.sym 27573 $io_pmod[0]$iobuf_i +.sym 27564 $io_pmod[0]$iobuf_i .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27595 o_rx_h_tx_l$SB_IO_OUT +.sym 27591 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27617 o_tr_vc2$SB_IO_OUT -.sym 27623 o_tr_vc1$SB_IO_OUT +.sym 27615 o_tr_vc2$SB_IO_OUT +.sym 27620 o_tr_vc1$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27650 o_tr_vc1_b$SB_IO_OUT -.sym 27653 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27732 w_rx_09_fifo_data[10] +.sym 27642 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27643 o_tr_vc1_b$SB_IO_OUT +.sym 27716 w_rx_09_fifo_data[23] +.sym 27717 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27719 w_rx_09_fifo_data[22] +.sym 27720 w_rx_24_fifo_data[22] +.sym 27721 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27728 w_rx_09_fifo_data[27] +.sym 27729 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27732 w_rx_09_fifo_data[19] .sym 27733 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27740 w_rx_09_fifo_data[14] +.sym 27740 w_rx_09_fifo_data[21] .sym 27741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27744 w_rx_09_fifo_data[12] +.sym 27744 w_rx_09_fifo_data[25] .sym 27745 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27768 w_rx_09_fifo_data[18] +.sym 27748 w_rx_09_fifo_data[29] +.sym 27749 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27751 w_rx_09_fifo_data[26] +.sym 27752 w_rx_24_fifo_data[26] +.sym 27753 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27755 w_rx_09_fifo_data[24] +.sym 27756 w_rx_24_fifo_data[24] +.sym 27757 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27760 w_rx_09_fifo_data[24] +.sym 27761 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27764 w_rx_09_fifo_data[26] +.sym 27765 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27768 w_rx_09_fifo_data[22] .sym 27769 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27772 w_rx_09_fifo_data[16] +.sym 27772 w_rx_09_fifo_data[28] .sym 27773 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] .sym 27776 w_rx_09_fifo_data[20] .sym 27777 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27788 w_rx_09_fifo_data[9] -.sym 27789 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27800 w_rx_09_fifo_data[7] +.sym 27780 w_rx_09_fifo_data[17] +.sym 27781 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27783 w_rx_24_fifo_data[16] +.sym 27784 w_rx_09_fifo_data[16] +.sym 27785 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27787 w_rx_09_fifo_data[18] +.sym 27788 w_rx_24_fifo_data[18] +.sym 27789 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27792 w_rx_09_fifo_data[15] +.sym 27793 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27796 w_rx_09_fifo_data[14] +.sym 27797 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27800 w_rx_09_fifo_data[16] .sym 27801 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27804 w_rx_09_fifo_data[22] -.sym 27805 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27807 w_rx_09_fifo_data[9] -.sym 27808 w_rx_24_fifo_data[9] -.sym 27809 o_led1$SB_IO_OUT -.sym 27812 w_rx_24_fifo_data[7] -.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27816 w_rx_24_fifo_data[9] +.sym 27803 w_rx_09_fifo_data[20] +.sym 27804 w_rx_24_fifo_data[20] +.sym 27805 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27808 w_rx_09_fifo_data[18] +.sym 27809 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27816 w_rx_24_fifo_data[14] .sym 27817 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27820 w_rx_24_fifo_data[10] +.sym 27820 w_rx_24_fifo_data[24] .sym 27821 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27824 w_rx_24_fifo_data[6] +.sym 27824 w_rx_24_fifo_data[16] .sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27828 w_rx_24_fifo_data[11] +.sym 27828 w_rx_24_fifo_data[22] .sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27832 w_rx_24_fifo_data[8] +.sym 27832 w_rx_24_fifo_data[18] .sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 27837 o_iq_tx_clk_p$SB_IO_OUT -.sym 27840 w_rx_24_fifo_data[5] +.sym 27840 w_rx_24_fifo_data[20] .sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27844 w_rx_09_fifo_data[6] +.sym 27844 w_rx_09_fifo_data[9] .sym 27845 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27848 w_rx_09_fifo_data[4] -.sym 27849 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27852 w_rx_09_fifo_data[0] +.sym 27852 w_rx_09_fifo_data[11] .sym 27853 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27856 w_rx_09_fifo_data[1] +.sym 27856 w_rx_09_fifo_data[12] .sym 27857 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27859 w_rx_24_fifo_data[6] -.sym 27860 w_rx_09_fifo_data[6] -.sym 27861 o_led1$SB_IO_OUT -.sym 27864 w_rx_09_fifo_data[2] +.sym 27864 w_rx_09_fifo_data[10] .sym 27865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27867 w_rx_24_fifo_data[10] -.sym 27868 w_rx_09_fifo_data[10] -.sym 27869 o_led1$SB_IO_OUT -.sym 27872 w_rx_09_fifo_data[8] -.sym 27873 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27897 w_lvds_rx_24_d0 -.sym 27903 w_rx_24_fifo_data[8] -.sym 27904 w_rx_09_fifo_data[8] -.sym 27905 o_led1$SB_IO_OUT -.sym 27916 rx_fifo.rd_addr_gray_wr_r[8] -.sym 27917 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 27922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 27939 rx_fifo.wr_addr[1] -.sym 27944 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 27945 rx_fifo.wr_addr[1] -.sym 27948 rx_fifo.wr_addr[3] -.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 27952 rx_fifo.wr_addr[4] -.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 27956 rx_fifo.wr_addr[5] -.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 27960 rx_fifo.wr_addr[6] -.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 27964 rx_fifo.wr_addr[7] -.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 27968 rx_fifo.wr_addr[8] -.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 27972 rx_fifo.wr_addr[9] -.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 27974 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] -.sym 27982 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 27986 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 27990 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 27994 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 28003 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 28004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28005 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28008 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28009 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28012 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 28013 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28014 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 28015 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 28016 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 28017 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 28018 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 28019 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28020 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 28021 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] -.sym 28024 i_rst_b$SB_IO_IN -.sym 28025 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 28026 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 28027 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 28028 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 28029 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 28030 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 28031 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] -.sym 28032 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 28033 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 28034 w_lvds_rx_09_d0 -.sym 28035 w_lvds_rx_09_d1 -.sym 28036 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28037 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28038 rx_fifo.rd_addr_gray_wr[9] -.sym 28042 w_lvds_rx_09_d0 -.sym 28043 w_lvds_rx_09_d1 -.sym 28044 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28045 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 28051 rx_fifo.wr_addr[1] -.sym 28052 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28055 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 28056 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 28057 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 28058 w_rx_fifo_full -.sym 28059 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] -.sym 28060 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 28061 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28062 rx_fifo.rd_addr_gray_wr[0] -.sym 28066 w_lvds_rx_24_d1 -.sym 28067 w_lvds_rx_24_d0 -.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28071 w_lvds_rx_09_d1 -.sym 28072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28073 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 28076 i_rst_b$SB_IO_IN -.sym 28077 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 28080 w_lvds_rx_24_d1 -.sym 28081 w_lvds_rx_24_d0 -.sym 28083 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28084 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 28085 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28088 w_lvds_rx_09_d0 -.sym 28089 w_lvds_rx_09_d1 -.sym 28090 w_lvds_rx_09_d0 -.sym 28094 w_lvds_rx_24_d1 -.sym 28095 w_lvds_rx_24_d0 -.sym 28096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28097 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28100 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28101 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 28104 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 28105 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28107 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28108 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28109 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28110 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 28114 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28115 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28116 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28117 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28136 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28137 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28142 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28147 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28148 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28149 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28154 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28156 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28157 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28200 w_rx_09_fifo_data[11] -.sym 28201 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28208 w_rx_09_fifo_data[13] -.sym 28209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28211 w_rx_09_fifo_data[13] -.sym 28212 w_rx_24_fifo_data[13] -.sym 28213 o_led1$SB_IO_OUT -.sym 28216 w_rx_09_fifo_data[15] -.sym 28217 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28223 w_rx_09_fifo_data[15] -.sym 28224 w_rx_24_fifo_data[15] -.sym 28225 o_led1$SB_IO_OUT -.sym 28228 w_rx_24_fifo_data[12] -.sym 28229 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28232 w_rx_24_fifo_data[14] -.sym 28233 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28236 w_rx_24_fifo_data[15] -.sym 28237 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28240 w_rx_24_fifo_data[20] -.sym 28241 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28244 w_rx_24_fifo_data[16] -.sym 28245 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28247 w_rx_09_fifo_data[14] -.sym 28248 w_rx_24_fifo_data[14] -.sym 28249 o_led1$SB_IO_OUT -.sym 28251 w_rx_09_fifo_data[12] -.sym 28252 w_rx_24_fifo_data[12] -.sym 28253 o_led1$SB_IO_OUT -.sym 28256 w_rx_24_fifo_data[13] -.sym 28257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28260 w_rx_09_fifo_data[23] -.sym 28261 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28264 w_rx_09_fifo_data[17] -.sym 28265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28268 w_rx_09_fifo_data[19] -.sym 28269 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28271 w_rx_24_fifo_data[22] -.sym 28272 w_rx_09_fifo_data[22] -.sym 28273 o_led1$SB_IO_OUT -.sym 28275 w_rx_09_fifo_data[18] -.sym 28276 w_rx_24_fifo_data[18] -.sym 28277 o_led1$SB_IO_OUT -.sym 28280 w_rx_09_fifo_data[21] -.sym 28281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28283 w_rx_09_fifo_data[16] -.sym 28284 w_rx_24_fifo_data[16] -.sym 28285 o_led1$SB_IO_OUT -.sym 28287 w_rx_09_fifo_data[17] -.sym 28288 w_rx_24_fifo_data[17] -.sym 28289 o_led1$SB_IO_OUT -.sym 28292 w_rx_24_fifo_data[22] -.sym 28293 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28296 w_rx_24_fifo_data[24] -.sym 28297 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28299 w_rx_24_fifo_data[19] -.sym 28300 w_rx_09_fifo_data[19] -.sym 28301 o_led1$SB_IO_OUT -.sym 28304 w_rx_24_fifo_data[17] -.sym 28305 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28307 w_rx_09_fifo_data[24] -.sym 28308 w_rx_24_fifo_data[24] -.sym 28309 o_led1$SB_IO_OUT -.sym 28312 w_rx_24_fifo_data[19] -.sym 28313 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28316 w_rx_24_fifo_data[28] -.sym 28317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28320 w_rx_24_fifo_data[26] -.sym 28321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28323 w_rx_09_fifo_data[11] -.sym 28324 w_rx_24_fifo_data[11] -.sym 28325 o_led1$SB_IO_OUT -.sym 28328 w_rx_09_fifo_data[3] -.sym 28329 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28331 w_rx_09_fifo_data[5] -.sym 28332 w_rx_24_fifo_data[5] -.sym 28333 o_led1$SB_IO_OUT -.sym 28335 w_rx_09_fifo_data[7] -.sym 28336 w_rx_24_fifo_data[7] -.sym 28337 o_led1$SB_IO_OUT -.sym 28339 w_rx_24_fifo_data[26] -.sym 28340 w_rx_09_fifo_data[26] -.sym 28341 o_led1$SB_IO_OUT -.sym 28344 w_rx_09_fifo_data[24] -.sym 28345 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28348 w_rx_09_fifo_data[26] -.sym 28349 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28352 w_rx_09_fifo_data[5] -.sym 28353 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28356 w_rx_24_fifo_data[0] +.sym 27868 w_rx_09_fifo_data[13] +.sym 27869 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27871 w_rx_09_fifo_data[14] +.sym 27872 w_rx_24_fifo_data[14] +.sym 27873 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27875 w_rx_09_fifo_data[6] +.sym 27876 w_rx_24_fifo_data[6] +.sym 27877 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27880 w_rx_24_fifo_data[4] +.sym 27881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27884 w_rx_24_fifo_data[8] +.sym 27885 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27888 w_rx_24_fifo_data[12] +.sym 27889 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27892 w_rx_24_fifo_data[5] +.sym 27893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27896 w_rx_24_fifo_data[10] +.sym 27897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27900 w_rx_24_fifo_data[7] +.sym 27901 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27904 w_rx_24_fifo_data[6] +.sym 27905 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27907 w_rx_24_fifo_data[8] +.sym 27908 w_rx_09_fifo_data[8] +.sym 27909 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27912 w_rx_09_fifo_data[6] +.sym 27913 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27915 w_rx_09_fifo_data[10] +.sym 27916 w_rx_24_fifo_data[10] +.sym 27917 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 27924 w_rx_09_fifo_data[2] +.sym 27925 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27928 w_rx_09_fifo_data[8] +.sym 27929 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27932 w_rx_09_fifo_data[4] +.sym 27933 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27938 rx_fifo.rd_addr[9] +.sym 27950 rx_fifo.rd_addr_gray_wr[0] +.sym 27962 rx_fifo.rd_addr_gray_wr[9] +.sym 27980 w_rx_09_fifo_data[1] +.sym 27981 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27996 i_rst_b$SB_IO_IN +.sym 27997 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 28003 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28004 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 28005 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28008 w_lvds_rx_09_d0 +.sym 28009 w_lvds_rx_09_d1 +.sym 28012 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28013 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 28014 w_lvds_rx_09_d0 +.sym 28015 w_lvds_rx_09_d1 +.sym 28016 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28017 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28022 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 28026 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28027 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28028 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28029 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28031 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28032 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28033 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28035 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28038 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28039 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 28040 $PACKER_VCC_NET +.sym 28041 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28042 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28043 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28044 $PACKER_VCC_NET +.sym 28045 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 28047 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28048 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28049 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28053 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28054 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28055 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28056 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28057 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28064 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28065 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 28067 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 28070 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28071 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 28072 $PACKER_VCC_NET +.sym 28073 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 28074 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28075 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 28076 $PACKER_VCC_NET +.sym 28077 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 28081 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28082 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28083 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28084 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28085 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28086 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 28087 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28088 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 28089 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28090 w_lvds_rx_24_d1 +.sym 28091 w_lvds_rx_24_d0 +.sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28097 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 28104 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28105 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28108 w_lvds_rx_24_d1 +.sym 28109 w_lvds_rx_24_d0 +.sym 28119 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28120 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28121 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28122 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28126 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28127 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28128 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28129 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28210 w_rx_fifo_pulled_data[25] +.sym 28218 w_rx_fifo_pulled_data[26] +.sym 28226 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 28227 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 28228 smi_ctrl_ins.int_cnt_rx[4] +.sym 28229 smi_ctrl_ins.int_cnt_rx[3] +.sym 28230 w_rx_fifo_pulled_data[18] +.sym 28238 w_rx_fifo_pulled_data[27] +.sym 28242 w_rx_fifo_pulled_data[24] +.sym 28246 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 28247 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 28248 smi_ctrl_ins.int_cnt_rx[4] +.sym 28249 smi_ctrl_ins.int_cnt_rx[3] +.sym 28254 w_rx_fifo_pulled_data[17] +.sym 28260 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 28261 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 28264 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 28265 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 28268 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 28269 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 28271 w_rx_24_fifo_data[19] +.sym 28272 w_rx_09_fifo_data[19] +.sym 28273 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28276 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 28277 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 28280 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 28281 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 28282 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 28283 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 28284 smi_ctrl_ins.int_cnt_rx[4] +.sym 28285 smi_ctrl_ins.int_cnt_rx[3] +.sym 28286 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 28287 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 28288 smi_ctrl_ins.int_cnt_rx[4] +.sym 28289 smi_ctrl_ins.int_cnt_rx[3] +.sym 28290 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 28291 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 28292 smi_ctrl_ins.int_cnt_rx[4] +.sym 28293 smi_ctrl_ins.int_cnt_rx[3] +.sym 28294 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 28295 smi_ctrl_ins.int_cnt_rx[4] +.sym 28296 smi_ctrl_ins.int_cnt_rx[3] +.sym 28297 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 28298 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 28299 smi_ctrl_ins.int_cnt_rx[4] +.sym 28300 smi_ctrl_ins.int_cnt_rx[3] +.sym 28301 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 28302 w_rx_fifo_pulled_data[19] +.sym 28306 w_rx_fifo_pulled_data[16] +.sym 28310 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 28311 smi_ctrl_ins.int_cnt_rx[4] +.sym 28312 smi_ctrl_ins.int_cnt_rx[3] +.sym 28313 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 28314 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 28315 smi_ctrl_ins.int_cnt_rx[4] +.sym 28316 smi_ctrl_ins.int_cnt_rx[3] +.sym 28317 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 28319 w_rx_09_fifo_data[17] +.sym 28320 w_rx_24_fifo_data[17] +.sym 28321 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28322 w_rx_fifo_pulled_data[13] +.sym 28326 w_rx_fifo_pulled_data[8] +.sym 28330 w_rx_fifo_pulled_data[10] +.sym 28334 w_rx_fifo_pulled_data[15] +.sym 28338 w_rx_fifo_pulled_data[3] +.sym 28342 w_rx_fifo_pulled_data[6] +.sym 28356 w_rx_24_fifo_data[15] .sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28359 w_rx_24_fifo_data[2] -.sym 28360 w_rx_09_fifo_data[2] -.sym 28361 o_led1$SB_IO_OUT -.sym 28364 w_rx_24_fifo_data[3] -.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28367 w_rx_09_fifo_data[3] -.sym 28368 w_rx_24_fifo_data[3] -.sym 28369 o_led1$SB_IO_OUT -.sym 28372 w_rx_24_fifo_data[4] +.sym 28360 w_rx_24_fifo_data[9] +.sym 28361 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28363 w_rx_09_fifo_data[11] +.sym 28364 w_rx_24_fifo_data[11] +.sym 28365 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28368 i_rst_b$SB_IO_IN +.sym 28369 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 28372 w_rx_24_fifo_data[13] .sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28376 w_rx_24_fifo_data[1] +.sym 28376 w_rx_24_fifo_data[17] .sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28380 w_rx_24_fifo_data[2] +.sym 28380 w_rx_24_fifo_data[11] .sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28383 w_rx_24_fifo_data[4] -.sym 28384 w_rx_09_fifo_data[4] -.sym 28385 o_led1$SB_IO_OUT -.sym 28386 rx_fifo.rd_addr[9] -.sym 28422 rx_fifo.wr_addr[9] -.sym 28430 rx_fifo.wr_addr_gray_rd[9] -.sym 28435 w_rx_24_fifo_data[1] -.sym 28436 w_rx_09_fifo_data[1] -.sym 28437 o_led1$SB_IO_OUT -.sym 28452 rx_fifo.rd_addr_gray_wr_r[5] -.sym 28453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] -.sym 28455 w_rx_24_fifo_data[0] -.sym 28456 w_rx_09_fifo_data[0] -.sym 28457 o_led1$SB_IO_OUT -.sym 28459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 28460 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] -.sym 28461 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] -.sym 28462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 28463 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 28464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] -.sym 28465 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] -.sym 28467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 28468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 28469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 28471 io_pmod[7]$SB_IO_IN -.sym 28472 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 28473 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 28475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 28476 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 28477 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 28479 rx_fifo.rd_addr_gray_wr_r[7] -.sym 28480 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] -.sym 28481 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 28483 rx_fifo.wr_addr[0] -.sym 28488 rx_fifo.wr_addr[1] -.sym 28489 rx_fifo.wr_addr[0] -.sym 28492 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 28496 rx_fifo.wr_addr[3] -.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 28500 rx_fifo.wr_addr[4] -.sym 28501 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 28504 rx_fifo.wr_addr[5] -.sym 28505 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28508 rx_fifo.wr_addr[6] -.sym 28509 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28512 rx_fifo.wr_addr[7] -.sym 28513 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 28516 rx_fifo.wr_addr[8] -.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 28520 rx_fifo.wr_addr[9] -.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28528 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28529 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28532 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28533 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 28537 rx_fifo.wr_addr[0] -.sym 28540 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28543 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28548 rx_fifo.rd_addr_gray_wr_r[5] -.sym 28549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 28550 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28551 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 28552 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28553 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28554 rx_fifo.rd_addr_gray_wr[8] -.sym 28558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 28559 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 28560 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 28562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] -.sym 28563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 28564 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 28566 rx_fifo.rd_addr_gray_wr[5] -.sym 28570 rx_fifo.rd_addr_gray[8] -.sym 28574 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28576 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 28579 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 28580 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28581 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28586 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 28587 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 28588 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 28589 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 28593 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 28594 w_lvds_rx_24_d1 -.sym 28595 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28597 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28603 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28604 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28605 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28611 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 28614 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28615 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 28616 $PACKER_VCC_NET -.sym 28617 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 28618 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28619 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28620 $PACKER_VCC_NET -.sym 28621 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 28622 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28623 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28624 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28625 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28629 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28633 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28635 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28636 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28637 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28640 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28641 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 28643 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 28646 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28647 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 28648 $PACKER_VCC_NET -.sym 28649 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 28650 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28651 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 28652 $PACKER_VCC_NET -.sym 28653 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 28654 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28656 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28657 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28665 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28666 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 28667 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28668 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 28669 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28673 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 28706 w_rx_fifo_pulled_data[13] -.sym 28710 w_rx_fifo_pulled_data[12] -.sym 28714 w_rx_fifo_pulled_data[7] -.sym 28718 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 28719 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 28720 smi_ctrl_ins.int_cnt_rx[4] -.sym 28721 smi_ctrl_ins.int_cnt_rx[3] -.sym 28726 w_rx_fifo_pulled_data[15] -.sym 28730 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 28731 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 28732 smi_ctrl_ins.int_cnt_rx[4] -.sym 28733 smi_ctrl_ins.int_cnt_rx[3] -.sym 28734 w_rx_fifo_pulled_data[14] +.sym 28383 w_rx_09_fifo_data[9] +.sym 28384 w_rx_24_fifo_data[9] +.sym 28385 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28387 w_rx_09_fifo_data[5] +.sym 28388 w_rx_24_fifo_data[5] +.sym 28389 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28392 w_rx_09_fifo_data[5] +.sym 28393 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28395 w_rx_24_fifo_data[12] +.sym 28396 w_rx_09_fifo_data[12] +.sym 28397 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28399 w_rx_24_fifo_data[15] +.sym 28400 w_rx_09_fifo_data[15] +.sym 28401 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28404 w_rx_09_fifo_data[3] +.sym 28405 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28408 w_rx_09_fifo_data[7] +.sym 28409 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28411 w_rx_24_fifo_data[13] +.sym 28412 w_rx_09_fifo_data[13] +.sym 28413 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28415 w_rx_09_fifo_data[7] +.sym 28416 w_rx_24_fifo_data[7] +.sym 28417 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28419 w_rx_24_fifo_data[4] +.sym 28420 w_rx_09_fifo_data[4] +.sym 28421 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28423 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 28424 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 28425 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 28426 w_rx_fifo_full +.sym 28427 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28428 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 28429 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28438 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28439 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28440 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 28441 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 28446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 28447 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 28448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 28449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 28450 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28451 rx_fifo.wr_addr[1] +.sym 28452 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28453 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 28455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 28456 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 28457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] +.sym 28464 w_rx_24_fifo_data[2] +.sym 28465 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 28467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 28468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 28469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 28470 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28471 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28472 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 28473 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.sym 28476 w_rx_24_fifo_data[3] +.sym 28477 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28479 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 28480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28481 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 28482 w_rx_fifo_pulled_data[0] +.sym 28486 w_rx_fifo_pulled_data[11] +.sym 28490 w_rx_fifo_pulled_data[14] +.sym 28499 w_rx_09_fifo_data[3] +.sym 28500 w_rx_24_fifo_data[3] +.sym 28501 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28502 w_rx_fifo_pulled_data[1] +.sym 28506 w_rx_fifo_pulled_data[9] +.sym 28510 w_rx_fifo_pulled_data[2] +.sym 28516 w_rx_24_fifo_data[0] +.sym 28517 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28523 w_rx_09_fifo_data[0] +.sym 28524 w_rx_24_fifo_data[0] +.sym 28525 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28530 w_lvds_rx_09_d0 +.sym 28531 w_lvds_rx_09_d1 +.sym 28532 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28533 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28535 w_rx_24_fifo_data[2] +.sym 28536 w_rx_09_fifo_data[2] +.sym 28537 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28539 w_rx_24_fifo_data[1] +.sym 28540 w_rx_09_fifo_data[1] +.sym 28541 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28544 w_rx_24_fifo_data[1] +.sym 28545 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28549 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28552 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28553 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28562 w_lvds_rx_09_d0 +.sym 28567 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28568 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28569 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28571 w_lvds_rx_09_d1 +.sym 28572 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 28573 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 28590 w_lvds_rx_24_d1 +.sym 28591 w_lvds_rx_24_d0 +.sym 28592 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28593 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28598 w_lvds_rx_24_d1 +.sym 28599 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 28600 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28601 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28609 w_lvds_rx_24_d0 +.sym 28612 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28613 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28615 w_rx_fifo_full +.sym 28616 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28617 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28636 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 28637 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28668 w_rx_fifo_full +.sym 28669 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 28739 w_rx_09_fifo_data[21] .sym 28740 w_rx_24_fifo_data[21] -.sym 28741 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28744 w_rx_24_fifo_data[18] +.sym 28741 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28744 w_rx_24_fifo_data[21] .sym 28745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28747 w_rx_09_fifo_data[23] .sym 28748 w_rx_24_fifo_data[23] -.sym 28749 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28753 rx_fifo.wr_addr[9] -.sym 28756 w_rx_24_fifo_data[29] +.sym 28749 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28751 w_rx_24_fifo_data[25] +.sym 28752 w_rx_09_fifo_data[25] +.sym 28753 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28756 w_rx_24_fifo_data[25] .sym 28757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28760 w_rx_24_fifo_data[25] -.sym 28761 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28764 w_rx_24_fifo_data[27] +.sym 28759 w_rx_09_fifo_data[27] +.sym 28760 w_rx_24_fifo_data[27] +.sym 28761 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28764 w_rx_24_fifo_data[23] .sym 28765 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28767 w_rx_24_fifo_data[25] -.sym 28768 w_rx_09_fifo_data[25] -.sym 28769 o_led1$SB_IO_OUT -.sym 28771 w_rx_09_fifo_data[20] -.sym 28772 w_rx_24_fifo_data[20] -.sym 28773 o_led1$SB_IO_OUT -.sym 28774 w_rx_fifo_pulled_data[18] -.sym 28778 w_rx_fifo_pulled_data[16] -.sym 28782 w_rx_fifo_pulled_data[17] -.sym 28787 w_rx_24_fifo_data[23] -.sym 28788 w_rx_09_fifo_data[23] -.sym 28789 o_led1$SB_IO_OUT -.sym 28790 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 28791 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 28792 smi_ctrl_ins.int_cnt_rx[4] -.sym 28793 smi_ctrl_ins.int_cnt_rx[3] -.sym 28794 w_rx_fifo_pulled_data[19] -.sym 28799 w_rx_09_fifo_data[21] -.sym 28800 w_rx_24_fifo_data[21] -.sym 28801 o_led1$SB_IO_OUT -.sym 28802 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 28803 smi_ctrl_ins.int_cnt_rx[4] -.sym 28804 smi_ctrl_ins.int_cnt_rx[3] -.sym 28805 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 28808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 28809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 28810 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 28811 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 28812 smi_ctrl_ins.int_cnt_rx[4] -.sym 28813 smi_ctrl_ins.int_cnt_rx[3] -.sym 28816 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 28817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 28820 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 28821 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 28822 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 28823 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 28768 w_rx_24_fifo_data[27] +.sym 28769 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28771 w_rx_09_fifo_data[31] +.sym 28772 w_rx_24_fifo_data[31] +.sym 28773 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28776 w_rx_24_fifo_data[26] +.sym 28777 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28780 w_rx_24_fifo_data[28] +.sym 28781 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28783 w_rx_24_fifo_data[28] +.sym 28784 w_rx_09_fifo_data[28] +.sym 28785 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28788 w_rx_24_fifo_data[19] +.sym 28789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28791 w_rx_09_fifo_data[29] +.sym 28792 w_rx_24_fifo_data[29] +.sym 28793 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28796 w_rx_24_fifo_data[29] +.sym 28797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28799 w_rx_09_fifo_data[30] +.sym 28800 w_rx_24_fifo_data[30] +.sym 28801 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 28806 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 28807 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 28808 smi_ctrl_ins.int_cnt_rx[4] +.sym 28809 smi_ctrl_ins.int_cnt_rx[3] +.sym 28814 w_rx_fifo_pulled_data[5] +.sym 28818 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 28819 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 28820 smi_ctrl_ins.int_cnt_rx[4] +.sym 28821 smi_ctrl_ins.int_cnt_rx[3] +.sym 28822 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 28823 smi_ctrl_ins.r_fifo_pulled_data[4] .sym 28824 smi_ctrl_ins.int_cnt_rx[4] .sym 28825 smi_ctrl_ins.int_cnt_rx[3] -.sym 28828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 28829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 28832 smi_ctrl_ins.int_cnt_rx[4] -.sym 28833 smi_ctrl_ins.int_cnt_rx[3] -.sym 28834 w_rx_fifo_pulled_data[27] -.sym 28838 w_rx_fifo_pulled_data[25] -.sym 28842 w_rx_fifo_pulled_data[4] -.sym 28846 w_rx_fifo_pulled_data[26] -.sym 28850 w_rx_fifo_pulled_data[6] -.sym 28854 w_rx_fifo_pulled_data[24] -.sym 28862 w_rx_fifo_pulled_data[5] -.sym 28874 w_rx_fifo_pulled_data[10] -.sym 28902 w_rx_fifo_pulled_data[9] -.sym 28906 w_rx_fifo_pulled_data[11] -.sym 28914 w_rx_fifo_pulled_data[8] -.sym 28918 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 28919 smi_ctrl_ins.int_cnt_rx[4] -.sym 28920 smi_ctrl_ins.int_cnt_rx[3] -.sym 28921 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 28922 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 28923 smi_ctrl_ins.int_cnt_rx[4] -.sym 28924 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 28925 smi_ctrl_ins.int_cnt_rx[3] -.sym 28926 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 28927 smi_ctrl_ins.int_cnt_rx[4] -.sym 28928 smi_ctrl_ins.int_cnt_rx[3] -.sym 28929 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 28930 w_rx_fifo_pulled_data[2] -.sym 28945 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 28950 w_rx_fifo_pulled_data[3] -.sym 28954 w_rx_fifo_pulled_data[1] -.sym 28958 w_rx_fifo_pulled_data[0] -.sym 28965 rx_fifo.rd_addr[1] -.sym 28968 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 28969 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 28970 rx_fifo.rd_addr[7] -.sym 28971 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 28972 rx_fifo.rd_addr[6] -.sym 28973 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 28974 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28975 rx_fifo.rd_addr[9] -.sym 28976 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 28977 rx_fifo.rd_addr[8] -.sym 28978 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 28984 rx_fifo.rd_addr[5] -.sym 28985 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 28990 rx_fifo.rd_addr[5] -.sym 28991 rx_fifo.rd_addr[4] -.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 28993 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] -.sym 28996 i_rst_b$SB_IO_IN -.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28998 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 28999 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 29001 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 29002 rx_fifo.wr_addr_gray_rd[6] -.sym 29006 rx_fifo.wr_addr_gray_rd[7] -.sym 29010 rx_fifo.wr_addr_gray_rd[5] -.sym 29014 rx_fifo.wr_addr_gray_rd[3] -.sym 29018 rx_fifo.wr_addr_gray_rd[2] -.sym 29022 rx_fifo.wr_addr_gray_rd[4] -.sym 29026 rx_fifo.wr_addr_gray[7] -.sym 29030 rx_fifo.wr_addr_gray[2] -.sym 29035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29040 i_rst_b$SB_IO_IN -.sym 29041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 29042 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -.sym 29043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -.sym 29044 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O -.sym 29045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] -.sym 29048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] -.sym 29049 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 29050 rx_fifo.rd_addr_gray_wr_r[7] -.sym 29051 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29052 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 29053 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 29056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] -.sym 29057 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29058 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29062 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29070 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29074 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29078 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29082 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 29088 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 29089 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29094 rx_fifo.wr_addr_gray_rd[8] -.sym 29098 rx_fifo.wr_addr_gray[8] -.sym 29106 rx_fifo.wr_addr_gray[4] -.sym 29110 rx_fifo.wr_addr_gray[6] -.sym 29114 rx_fifo.wr_addr_gray[3] -.sym 29118 rx_fifo.wr_addr_gray[5] -.sym 29126 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29138 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29171 w_rx_fifo_full -.sym 29172 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 29173 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 29176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 29177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 29194 rx_fifo.rd_addr_gray_wr[7] -.sym 29222 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 29223 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 29224 smi_ctrl_ins.int_cnt_rx[4] -.sym 29225 smi_ctrl_ins.int_cnt_rx[3] -.sym 29236 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 29237 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 29244 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 29245 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 29251 w_rx_24_fifo_data[27] -.sym 29252 w_rx_09_fifo_data[27] -.sym 29253 o_led1$SB_IO_OUT -.sym 29256 w_rx_09_fifo_data[27] -.sym 29257 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29264 w_rx_09_fifo_data[28] -.sym 29265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29267 w_rx_24_fifo_data[29] -.sym 29268 w_rx_09_fifo_data[29] -.sym 29269 o_led1$SB_IO_OUT -.sym 29271 w_rx_24_fifo_data[31] -.sym 29272 lvds_rx_09_inst.o_fifo_data[31] -.sym 29273 o_led1$SB_IO_OUT -.sym 29276 w_rx_09_fifo_data[29] -.sym 29277 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29280 w_rx_09_fifo_data[25] -.sym 29281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29282 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 29283 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 29284 smi_ctrl_ins.int_cnt_rx[4] -.sym 29285 smi_ctrl_ins.int_cnt_rx[3] -.sym 29286 w_rx_fifo_pulled_data[23] -.sym 29294 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 29295 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 29296 smi_ctrl_ins.int_cnt_rx[4] -.sym 29297 smi_ctrl_ins.int_cnt_rx[3] -.sym 29302 w_rx_fifo_pulled_data[22] -.sym 29310 w_rx_fifo_pulled_data[20] -.sym 29318 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 29319 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 29320 smi_ctrl_ins.int_cnt_rx[4] -.sym 29321 smi_ctrl_ins.int_cnt_rx[3] -.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 29323 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 29324 smi_ctrl_ins.int_cnt_rx[4] -.sym 29325 smi_ctrl_ins.int_cnt_rx[3] -.sym 29328 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 29332 smi_ctrl_ins.int_cnt_rx[4] -.sym 29333 smi_ctrl_ins.int_cnt_rx[3] -.sym 29343 w_rx_09_fifo_data[30] -.sym 29344 w_rx_24_fifo_data[30] -.sym 29345 o_led1$SB_IO_OUT -.sym 29347 w_rx_24_fifo_data[28] -.sym 29348 w_rx_09_fifo_data[28] -.sym 29349 o_led1$SB_IO_OUT -.sym 29350 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29354 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29362 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 29366 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29373 rx_fifo.rd_addr[0] +.sym 28826 w_rx_fifo_pulled_data[7] +.sym 28830 w_rx_fifo_pulled_data[4] +.sym 28835 rx_fifo.wr_addr[0] +.sym 28840 rx_fifo.wr_addr[1] +.sym 28841 rx_fifo.wr_addr[0] +.sym 28844 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 28845 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 28848 rx_fifo.wr_addr[3] +.sym 28849 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 28852 rx_fifo.wr_addr[4] +.sym 28853 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 28856 rx_fifo.wr_addr[5] +.sym 28857 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28860 rx_fifo.wr_addr[6] +.sym 28861 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28864 rx_fifo.wr_addr[7] +.sym 28865 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 28868 rx_fifo.wr_addr[8] +.sym 28869 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 28872 rx_fifo.wr_addr[9] +.sym 28873 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 28875 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 28876 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28877 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28878 rx_fifo.wr_addr_gray[0] +.sym 28883 rx_fifo.rd_addr_gray_wr_r[6] +.sym 28884 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28885 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28886 rx_fifo.wr_addr_gray_rd[5] +.sym 28892 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28893 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28894 rx_fifo.wr_addr_gray[5] +.sym 28898 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28902 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28903 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28904 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28905 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28906 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28910 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +.sym 28911 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 28912 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 28913 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 28914 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 28918 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 28925 rx_fifo.wr_addr[1] +.sym 28928 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 28929 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 28932 i_rst_b$SB_IO_IN +.sym 28933 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 28935 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +.sym 28936 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 28937 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 28938 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28939 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 28940 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 28941 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 28944 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28945 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28946 w_rx_fifo_pulled_data[12] +.sym 28950 rx_fifo.rd_addr_gray_wr_r[6] +.sym 28951 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 28952 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28953 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28954 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 28955 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 28956 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 28957 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 28960 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 28961 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28964 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 28965 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28969 rx_fifo.rd_addr[8] +.sym 28970 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28974 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28980 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28981 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 28984 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28985 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28986 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28990 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28994 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28995 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 28996 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28997 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28998 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28999 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 29000 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 29001 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 29002 rx_fifo.rd_addr_gray_wr[8] +.sym 29006 rx_fifo.rd_addr_gray[7] +.sym 29010 rx_fifo.rd_addr_gray[6] +.sym 29014 rx_fifo.rd_addr_gray[0] +.sym 29018 rx_fifo.rd_addr_gray_wr[6] +.sym 29022 rx_fifo.rd_addr_gray_wr[7] +.sym 29026 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29030 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29040 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29041 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29042 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29048 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29049 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29050 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 29054 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 29060 w_rx_09_fifo_data[0] +.sym 29061 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29222 w_rx_fifo_pulled_data[20] +.sym 29230 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29231 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 29232 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29233 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29234 w_rx_fifo_pulled_data[22] +.sym 29238 w_rx_fifo_pulled_data[23] +.sym 29246 w_rx_fifo_pulled_data[21] +.sym 29250 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 29251 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 29252 smi_ctrl_ins.int_cnt_rx[4] +.sym 29253 smi_ctrl_ins.int_cnt_rx[3] +.sym 29254 w_rx_fifo_pulled_data[28] +.sym 29258 w_rx_fifo_pulled_data[30] +.sym 29266 w_rx_fifo_pulled_data[29] +.sym 29270 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 29271 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 29272 smi_ctrl_ins.int_cnt_rx[4] +.sym 29273 smi_ctrl_ins.int_cnt_rx[3] +.sym 29274 w_rx_fifo_pulled_data[31] +.sym 29278 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 29279 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 29280 smi_ctrl_ins.int_cnt_rx[4] +.sym 29281 smi_ctrl_ins.int_cnt_rx[3] +.sym 29282 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29288 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29289 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29290 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 29296 i_rst_b$SB_IO_IN +.sym 29297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 29298 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 29302 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29306 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 29307 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 29308 smi_ctrl_ins.int_cnt_rx[4] +.sym 29309 smi_ctrl_ins.int_cnt_rx[3] +.sym 29316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 29320 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 29321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 29322 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 29323 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 29324 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 29325 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 29328 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 29330 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 29331 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] +.sym 29332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 29333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 29334 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 29335 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 29336 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 29337 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 29338 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 29339 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29340 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 29341 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 29344 smi_ctrl_ins.int_cnt_rx[4] +.sym 29345 smi_ctrl_ins.int_cnt_rx[3] +.sym 29346 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 29352 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29353 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 29354 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 29358 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29359 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 29360 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 29361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 29365 rx_fifo.rd_addr[0] +.sym 29366 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29370 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] .sym 29374 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29379 rx_fifo.rd_addr[0] -.sym 29384 rx_fifo.rd_addr[1] -.sym 29385 rx_fifo.rd_addr[0] -.sym 29388 rx_fifo.rd_addr[2] -.sym 29389 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 29392 rx_fifo.rd_addr[3] -.sym 29393 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29396 rx_fifo.rd_addr[4] -.sym 29397 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29400 rx_fifo.rd_addr[5] -.sym 29401 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 29404 rx_fifo.rd_addr[6] -.sym 29405 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29408 rx_fifo.rd_addr[7] -.sym 29409 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29412 rx_fifo.rd_addr[8] -.sym 29413 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 29416 rx_fifo.rd_addr[9] -.sym 29417 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29418 w_rx_fifo_pulled_data[31] -.sym 29424 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 29426 w_rx_fifo_pulled_data[30] -.sym 29430 w_rx_fifo_pulled_data[21] -.sym 29434 w_rx_fifo_pulled_data[29] -.sym 29438 w_rx_fifo_pulled_data[28] -.sym 29442 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29446 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 29453 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 29456 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 29457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29458 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 29462 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29463 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 29466 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29470 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 29471 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 29472 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 29473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 29475 rx_fifo.rd_addr[8] -.sym 29476 rx_fifo.rd_addr[7] -.sym 29477 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 29480 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29481 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29482 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 29483 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 29484 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 29485 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 29486 rx_fifo.rd_addr[2] -.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 29488 rx_fifo.rd_addr[1] -.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] -.sym 29492 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29493 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29494 rx_fifo.rd_addr[3] -.sym 29495 rx_fifo.rd_addr[2] -.sym 29496 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 29497 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] -.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 29499 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] -.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] -.sym 29502 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 29508 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29511 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 29512 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 29514 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 29515 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 29516 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 29517 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] -.sym 29521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 29523 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -.sym 29524 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 29525 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 29528 w_rx_fifo_full -.sym 29529 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] -.sym 29544 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 29545 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29547 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 29548 o_led1$SB_IO_OUT -.sym 29549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29554 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 29562 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 29574 rx_fifo.rd_addr_gray[6] -.sym 29578 rx_fifo.rd_addr_gray_wr[3] -.sym 29582 rx_fifo.rd_addr_gray[0] -.sym 29586 rx_fifo.rd_addr_gray_wr[6] -.sym 29590 rx_fifo.rd_addr_gray[3] -.sym 29594 rx_fifo.rd_addr_gray[5] -.sym 29606 rx_fifo.rd_addr_gray[4] -.sym 29610 rx_fifo.rd_addr_gray[2] -.sym 29614 rx_fifo.rd_addr_gray[1] -.sym 29618 rx_fifo.rd_addr_gray_wr[2] -.sym 29626 rx_fifo.rd_addr_gray_wr[4] -.sym 29630 rx_fifo.rd_addr_gray_wr[1] -.sym 29654 r_tx_data[2] -.sym 29678 rx_fifo.wr_addr_gray[1] -.sym 29690 rx_fifo.wr_addr_gray_rd[1] -.sym 29698 rx_fifo.rd_addr_gray[7] -.sym 29709 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 29741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29752 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 29753 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 29764 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 29766 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 29770 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 29785 tx_fifo.rd_addr[0] -.sym 29786 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 29790 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 29795 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29796 tx_fifo.rd_addr[1] -.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 29798 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29802 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29807 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29808 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29809 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29814 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29815 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 29816 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29817 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29818 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 29822 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29823 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 29824 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29825 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29826 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 29827 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29828 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 29829 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29830 tx_fifo.rd_addr_gray[3] -.sym 29835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29836 tx_fifo.rd_addr[1] -.sym 29837 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 29838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 29839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -.sym 29840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29841 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 29846 tx_fifo.rd_addr_gray_wr[3] -.sym 29854 tx_fifo.rd_addr_gray[2] -.sym 29862 w_tx_fifo_empty -.sym 29863 w_tx_fifo_pull -.sym 29864 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 29865 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 29866 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 29867 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 29868 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 29869 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 29870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 29871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] -.sym 29872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] -.sym 29873 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] -.sym 29874 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 29875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 29876 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 29877 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 29880 i_rst_b$SB_IO_IN -.sym 29881 w_tx_fifo_pull -.sym 29882 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 29883 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 29884 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 29885 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] -.sym 29887 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -.sym 29888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 29889 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 29901 w_tx_fifo_empty -.sym 29903 w_tx_fifo_pull -.sym 29904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 29905 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 29907 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 29908 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 29909 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 29917 i_rst_b$SB_IO_IN -.sym 29922 smi_ctrl_ins.w_fifo_pull_trigger -.sym 29926 smi_ctrl_ins.r_fifo_pull -.sym 29932 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 29933 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29934 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 29935 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 29936 smi_ctrl_ins.int_cnt_rx[4] -.sym 29937 smi_ctrl_ins.int_cnt_rx[3] -.sym 29951 w_rx_fifo_empty -.sym 29952 smi_ctrl_ins.r_fifo_pull -.sym 29953 smi_ctrl_ins.r_fifo_pull_1 -.sym 29956 rx_fifo.rd_addr[1] -.sym 29957 rx_fifo.wr_addr_gray_rd_r[0] -.sym 29959 rx_fifo.rd_addr[5] -.sym 29960 rx_fifo.rd_addr[4] -.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] -.sym 29964 rx_fifo.rd_addr[4] -.sym 29965 rx_fifo.rd_addr[3] -.sym 29966 o_led1$SB_IO_OUT -.sym 29974 w_tx_fifo_full -.sym 29978 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] -.sym 29979 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] -.sym 29980 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] -.sym 29981 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] -.sym 29983 w_rx_fifo_empty -.sym 29984 rx_fifo.wr_addr_gray_rd_r[0] -.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29987 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 29988 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 29989 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 29991 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 29992 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 29993 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 29994 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 29998 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 30004 spi_if_ins.state_if[1] -.sym 30005 spi_if_ins.state_if[0] -.sym 30007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30008 spi_if_ins.state_if[1] -.sym 30009 spi_if_ins.state_if[0] -.sym 30011 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30012 spi_if_ins.state_if[1] -.sym 30013 spi_if_ins.state_if[0] -.sym 30015 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30016 spi_if_ins.state_if[1] -.sym 30017 spi_if_ins.state_if[0] -.sym 30018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30022 i_rst_b$SB_IO_IN -.sym 30023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30024 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30025 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 30026 i_rst_b$SB_IO_IN -.sym 30027 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30028 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30031 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 30032 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30033 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30035 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30036 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30037 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30040 i_rst_b$SB_IO_IN -.sym 30041 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30042 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30043 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30045 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30047 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30049 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30052 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30053 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30060 spi_if_ins.w_rx_data[6] -.sym 30061 spi_if_ins.w_rx_data[5] -.sym 30065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 30068 spi_if_ins.w_rx_data[6] -.sym 30069 spi_if_ins.w_rx_data[5] -.sym 30080 spi_if_ins.w_rx_data[6] -.sym 30081 spi_if_ins.w_rx_data[5] -.sym 30082 w_tx_data_smi[1] -.sym 30083 w_tx_data_io[1] -.sym 30084 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 30085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30093 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 30095 io_pmod[6]$SB_IO_IN -.sym 30096 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30097 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30099 i_rst_b$SB_IO_IN -.sym 30100 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30101 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30104 i_rst_b$SB_IO_IN -.sym 30105 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 30106 w_tx_data_io[2] -.sym 30107 w_tx_data_smi[2] -.sym 30108 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 30109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30115 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 30116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30117 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 30118 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 30119 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 30120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30123 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 30124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30125 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 30126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 30127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 30128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30129 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30131 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 30132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30133 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 30134 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 30135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 30136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30137 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 30138 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 30139 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 30140 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30142 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 30143 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 30144 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30145 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 30148 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30149 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30152 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30156 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] -.sym 30157 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30160 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30161 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30164 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30165 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] -.sym 30169 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] -.sym 30173 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] -.sym 30177 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30243 tx_fifo.rd_addr[0] -.sym 30248 tx_fifo.rd_addr[1] -.sym 30249 tx_fifo.rd_addr[0] -.sym 30252 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 30253 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30256 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 30257 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 30260 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 30261 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 30264 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 30265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 30268 tx_fifo.rd_addr[6] -.sym 30269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30272 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 30273 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 30276 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 30277 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 30280 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 30281 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 30283 tx_fifo.wr_addr_gray_rd_r[6] -.sym 30284 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30287 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30292 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 30293 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 30296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30297 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30300 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 30301 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30302 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30308 tx_fifo.rd_addr[6] -.sym 30309 tx_fifo.wr_addr_gray_rd_r[6] -.sym 30310 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 30311 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 30312 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 30313 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 30314 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 30315 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 30316 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 30317 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 30320 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 30321 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 30326 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -.sym 30327 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -.sym 30328 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 30329 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 30332 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30337 rx_fifo.wr_addr[1] -.sym 30344 tx_fifo.rd_addr[6] -.sym 30345 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 30346 smi_ctrl_ins.w_fifo_push_trigger -.sym 30350 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] -.sym 30351 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] -.sym 30352 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] -.sym 30353 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] -.sym 30359 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 30360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 30361 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 30363 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -.sym 30364 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 30365 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -.sym 30366 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 30367 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 30368 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 30369 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 30370 tx_fifo.wr_addr_gray_rd[7] -.sym 30374 tx_fifo.wr_addr_gray_rd[8] -.sym 30378 tx_fifo.wr_addr_gray_rd[2] -.sym 30382 tx_fifo.wr_addr_gray_rd[3] -.sym 30386 tx_fifo.wr_addr_gray_rd[5] -.sym 30390 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 30391 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 30392 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 30393 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 30394 tx_fifo.wr_addr_gray_rd[1] -.sym 30398 tx_fifo.wr_addr_gray_rd[9] -.sym 30402 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30406 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -.sym 30407 tx_fifo.rd_addr[1] -.sym 30408 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 30409 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30410 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 30414 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30420 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30421 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30424 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30425 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30428 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30429 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30443 i_rst_b$SB_IO_IN -.sym 30444 smi_ctrl_ins.int_cnt_rx[4] -.sym 30445 smi_ctrl_ins.int_cnt_rx[3] -.sym 30449 smi_ctrl_ins.int_cnt_rx[3] -.sym 30456 smi_ctrl_ins.int_cnt_rx[4] -.sym 30457 smi_ctrl_ins.int_cnt_rx[3] -.sym 30482 w_rx_fifo_empty -.sym 30499 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30504 $PACKER_VCC_NET -.sym 30507 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30508 $PACKER_VCC_NET -.sym 30509 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 30510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30511 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 30512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 30513 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 30517 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30519 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30520 $PACKER_VCC_NET -.sym 30521 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30524 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30529 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30530 spi_if_ins.spi.r_tx_byte[6] -.sym 30531 spi_if_ins.spi.r_tx_byte[4] -.sym 30532 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30533 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30534 spi_if_ins.r_tx_byte[4] -.sym 30539 spi_if_ins.spi.r_tx_byte[1] -.sym 30540 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30541 spi_if_ins.spi.r_tx_byte[0] -.sym 30543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 30544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 30545 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 30546 spi_if_ins.r_tx_byte[7] -.sym 30551 spi_if_ins.spi.r_tx_byte[3] -.sym 30552 spi_if_ins.spi.r_tx_byte[2] -.sym 30553 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 30557 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 30558 spi_if_ins.spi.r_tx_byte[7] -.sym 30559 spi_if_ins.spi.r_tx_byte[5] -.sym 30560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30561 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30562 i_rst_b$SB_IO_IN -.sym 30563 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30565 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30566 spi_if_ins.r_tx_byte[0] -.sym 30570 spi_if_ins.r_tx_byte[2] -.sym 30574 w_cs[3] -.sym 30575 w_cs[2] -.sym 30576 w_cs[1] -.sym 30577 w_cs[0] -.sym 30578 spi_if_ins.r_tx_byte[5] -.sym 30582 spi_if_ins.r_tx_byte[6] -.sym 30586 spi_if_ins.r_tx_byte[3] -.sym 30590 spi_if_ins.r_tx_byte[1] -.sym 30594 w_cs[3] -.sym 30595 w_cs[2] -.sym 30596 w_cs[1] -.sym 30597 w_cs[0] -.sym 30598 w_cs[3] -.sym 30599 w_cs[2] -.sym 30600 w_cs[1] -.sym 30601 w_cs[0] -.sym 30602 w_rx_data[2] -.sym 30606 w_cs[3] -.sym 30607 w_cs[2] -.sym 30608 w_cs[1] +.sym 29381 rx_fifo.wr_addr[0] +.sym 29383 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 29384 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29385 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29388 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29389 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29390 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29394 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 29395 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] +.sym 29396 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] +.sym 29397 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 29400 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 29401 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29403 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 29404 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29405 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29406 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29411 rx_fifo.wr_addr[1] +.sym 29416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 29417 rx_fifo.wr_addr[1] +.sym 29420 rx_fifo.wr_addr[3] +.sym 29421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 29424 rx_fifo.wr_addr[4] +.sym 29425 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29428 rx_fifo.wr_addr[5] +.sym 29429 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 29432 rx_fifo.wr_addr[6] +.sym 29433 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29436 rx_fifo.wr_addr[7] +.sym 29437 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29440 rx_fifo.wr_addr[8] +.sym 29441 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29444 rx_fifo.wr_addr[9] +.sym 29445 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 29446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +.sym 29447 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 29448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.sym 29449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] +.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29453 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 29454 w_rx_data[5] +.sym 29458 rx_fifo.rd_addr_gray_wr_r[6] +.sym 29459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +.sym 29460 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 29461 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 29462 w_rx_data[0] +.sym 29467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 29468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 29469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] +.sym 29471 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 29472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 29473 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] +.sym 29474 rx_fifo.wr_addr_gray_rd[4] +.sym 29478 rx_fifo.wr_addr_gray[4] +.sym 29490 rx_fifo.wr_addr_gray[2] +.sym 29496 rx_fifo.rd_addr[8] +.sym 29497 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 29498 rx_fifo.rd_addr[7] +.sym 29499 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 29500 rx_fifo.rd_addr[6] +.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.sym 29502 rx_fifo.wr_addr_gray_rd[2] +.sym 29509 rx_fifo.rd_addr[1] +.sym 29510 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.sym 29516 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +.sym 29517 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 29518 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.sym 29522 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29538 rx_fifo.wr_addr_gray[6] +.sym 29542 rx_fifo.wr_addr_gray_rd[6] +.sym 29546 rx_fifo.wr_addr_gray_rd[3] +.sym 29550 rx_fifo.wr_addr[9] +.sym 29554 rx_fifo.wr_addr_gray[1] +.sym 29558 rx_fifo.wr_addr_gray[3] +.sym 29562 rx_fifo.wr_addr_gray_rd[1] +.sym 29566 rx_fifo.wr_addr_gray_rd[9] +.sym 29570 rx_fifo.wr_addr_gray_rd[7] +.sym 29574 rx_fifo.wr_addr_gray_rd[8] +.sym 29590 rx_fifo.wr_addr_gray[8] +.sym 29594 rx_fifo.wr_addr_gray[7] +.sym 29602 rx_fifo.rd_addr_gray[4] +.sym 29606 rx_fifo.rd_addr_gray_wr[1] +.sym 29630 rx_fifo.rd_addr_gray[1] +.sym 29725 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29734 tx_fifo.wr_addr_gray[6] +.sym 29738 tx_fifo.wr_addr_gray[2] +.sym 29746 tx_fifo.wr_addr_gray_rd[5] +.sym 29757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 29758 tx_fifo.wr_addr_gray[5] +.sym 29762 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29763 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 29764 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29766 tx_fifo.wr_addr_gray[4] +.sym 29770 tx_fifo.wr_addr_gray[3] +.sym 29775 i_rst_b$SB_IO_IN +.sym 29776 smi_ctrl_ins.int_cnt_rx[4] +.sym 29777 smi_ctrl_ins.int_cnt_rx[3] +.sym 29778 tx_fifo.wr_addr_gray_rd[6] +.sym 29784 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 29785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 29790 tx_fifo.wr_addr_gray_rd[4] +.sym 29802 tx_fifo.wr_addr[9] +.sym 29806 tx_fifo.wr_addr_gray_rd[3] +.sym 29814 tx_fifo.wr_addr_gray_rd[2] +.sym 29818 tx_fifo.wr_addr_gray_rd[1] +.sym 29822 tx_fifo.wr_addr_gray_rd[9] +.sym 29826 smi_ctrl_ins.r_fifo_pull +.sym 29830 smi_ctrl_ins.w_fifo_pull_trigger +.sym 29836 rx_fifo.rd_addr[1] +.sym 29837 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 29838 smi_ctrl_ins.w_fifo_push_trigger +.sym 29843 w_rx_fifo_empty +.sym 29844 smi_ctrl_ins.r_fifo_pull_1 +.sym 29845 smi_ctrl_ins.r_fifo_pull +.sym 29847 rx_fifo.rd_addr[3] +.sym 29848 rx_fifo.rd_addr[2] +.sym 29849 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 29852 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 29853 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29854 smi_ctrl_ins.r_fifo_push +.sym 29859 w_tx_fifo_full +.sym 29860 smi_ctrl_ins.r_fifo_push_1 +.sym 29861 smi_ctrl_ins.r_fifo_push +.sym 29863 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 29864 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29865 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +.sym 29866 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29867 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29868 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 29869 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 29870 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 29871 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29872 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 29873 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 29875 rx_fifo.rd_addr[2] +.sym 29876 rx_fifo.rd_addr[1] +.sym 29877 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29878 rx_fifo.rd_addr[2] +.sym 29879 rx_fifo.rd_addr[1] +.sym 29880 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29881 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 29884 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29885 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 29886 w_rx_fifo_empty +.sym 29887 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.sym 29888 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 29889 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] +.sym 29891 rx_fifo.rd_addr[0] +.sym 29896 rx_fifo.rd_addr[1] +.sym 29897 rx_fifo.rd_addr[0] +.sym 29900 rx_fifo.rd_addr[2] +.sym 29901 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 29904 rx_fifo.rd_addr[3] +.sym 29905 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 29908 rx_fifo.rd_addr[4] +.sym 29909 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29912 rx_fifo.rd_addr[5] +.sym 29913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29916 rx_fifo.rd_addr[6] +.sym 29917 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29920 rx_fifo.rd_addr[7] +.sym 29921 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29924 rx_fifo.rd_addr[8] +.sym 29925 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 29928 rx_fifo.rd_addr[9] +.sym 29929 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 29930 rx_fifo.rd_addr[5] +.sym 29931 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 29932 rx_fifo.rd_addr[4] +.sym 29933 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 29934 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.sym 29935 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.sym 29936 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 29937 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 29938 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 29942 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29946 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29950 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29956 rx_fifo.rd_addr[6] +.sym 29957 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 29958 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 29959 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 29960 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] +.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] +.sym 29962 rx_fifo.rd_addr[4] +.sym 29963 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 29964 rx_fifo.rd_addr[2] +.sym 29965 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 29967 rx_fifo.rd_addr[5] +.sym 29968 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.sym 29969 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.sym 29972 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 29973 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29974 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] +.sym 29975 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.sym 29976 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] +.sym 29977 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.sym 29978 rx_fifo.rd_addr_gray[5] +.sym 29982 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +.sym 29983 rx_fifo.rd_addr[9] +.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +.sym 29985 rx_fifo.rd_addr[8] +.sym 29986 rx_fifo.rd_addr_gray_wr[3] +.sym 29990 rx_fifo.rd_addr_gray_wr[5] +.sym 29996 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] +.sym 29997 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] +.sym 29998 rx_fifo.rd_addr_gray_wr[4] +.sym 30002 rx_fifo.rd_addr_gray[3] +.sym 30006 rx_fifo.rd_addr_gray[8] +.sym 30010 rx_fifo.rd_addr_gray_wr[2] +.sym 30014 rx_fifo.rd_addr_gray[2] +.sym 30033 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 30042 rx_fifo.rd_addr[4] +.sym 30043 rx_fifo.rd_addr[3] +.sym 30044 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 30045 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 30047 io_pmod[6]$SB_IO_IN +.sym 30048 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30049 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 30052 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 30053 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30059 io_pmod[7]$SB_IO_IN +.sym 30060 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30061 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 30062 rx_fifo.rd_addr[8] +.sym 30063 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] +.sym 30064 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.sym 30065 rx_fifo.rd_addr[6] +.sym 30082 w_rx_data[4] +.sym 30094 w_rx_data[6] +.sym 30098 w_rx_data[7] +.sym 30102 w_rx_data[3] +.sym 30106 w_rx_data[1] +.sym 30110 w_rx_data[2] +.sym 30116 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30117 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30120 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] +.sym 30121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30124 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30125 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30136 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] +.sym 30137 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30140 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30144 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] +.sym 30145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30147 o_rx_h_tx_l_b$SB_IO_OUT +.sym 30148 i_button_SB_LUT4_I0_O[1] +.sym 30149 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 30151 o_rx_h_tx_l$SB_IO_OUT +.sym 30152 i_button_SB_LUT4_I0_O[1] +.sym 30153 i_button_SB_LUT4_I0_O[2] +.sym 30165 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 30175 o_tr_vc1$SB_IO_OUT +.sym 30176 i_button_SB_LUT4_I0_O[1] +.sym 30177 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 30178 i_button$SB_IO_IN +.sym 30179 io_ctrl_ins.pmod_dir_state[7] +.sym 30180 o_led1_SB_LUT4_I1_I3[3] +.sym 30181 o_led1_SB_LUT4_I1_I2[2] +.sym 30182 i_config[2]$SB_IO_IN +.sym 30183 io_ctrl_ins.pmod_dir_state[5] +.sym 30184 o_led1_SB_LUT4_I1_I3[3] +.sym 30185 o_led1_SB_LUT4_I1_I2[2] +.sym 30190 w_rx_data[6] +.sym 30198 w_rx_data[7] +.sym 30202 i_config[3]$SB_IO_IN +.sym 30203 io_ctrl_ins.pmod_dir_state[6] +.sym 30204 o_led1_SB_LUT4_I1_I3[3] +.sym 30205 o_led1_SB_LUT4_I1_I2[2] +.sym 30206 w_rx_data[5] +.sym 30245 tx_fifo.wr_addr[0] +.sym 30246 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30250 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30256 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 30257 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30258 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30268 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30269 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 30270 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 30276 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 30277 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 30279 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 30280 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30281 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30282 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 30295 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 30296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30297 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30300 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 30301 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30304 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30305 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 30312 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 30313 tx_fifo.rd_addr[2] +.sym 30314 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 30315 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 30316 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 30317 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 30320 smi_ctrl_ins.int_cnt_rx[4] +.sym 30321 smi_ctrl_ins.int_cnt_rx[3] +.sym 30325 smi_ctrl_ins.int_cnt_rx[3] +.sym 30330 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30331 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 30332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30335 tx_fifo.rd_addr[2] +.sym 30336 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 30337 tx_fifo.rd_addr[1] +.sym 30340 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 30341 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 30342 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 30343 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30344 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 30345 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 30348 i_rst_b$SB_IO_IN +.sym 30349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 30350 tx_fifo.rd_addr_gray_wr[1] +.sym 30355 tx_fifo.rd_addr[2] +.sym 30356 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 30357 tx_fifo.rd_addr[1] +.sym 30358 rx_fifo.wr_addr_gray_rd[0] +.sym 30362 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 30363 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 30364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30366 tx_fifo.rd_addr_gray[1] +.sym 30371 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 30372 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 30373 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 30376 tx_fifo.rd_addr[8] +.sym 30377 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.sym 30382 tx_fifo.rd_addr[9] +.sym 30383 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 30384 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 30385 tx_fifo.rd_addr[8] +.sym 30386 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30393 tx_fifo.wr_addr[1] +.sym 30396 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 30397 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 30400 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 30401 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 30402 tx_fifo.wr_addr_gray[8] +.sym 30406 tx_fifo.wr_addr_gray_rd[8] +.sym 30414 tx_fifo.wr_addr_gray_rd[0] +.sym 30418 tx_fifo.wr_addr_gray_rd[7] +.sym 30426 tx_fifo.wr_addr_gray[7] +.sym 30430 tx_fifo.wr_addr_gray[0] +.sym 30434 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 30444 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 30445 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30446 w_tx_fifo_full +.sym 30454 w_rx_fifo_empty +.sym 30460 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30461 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 30468 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.sym 30469 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 30472 i_rst_b$SB_IO_IN +.sym 30473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30490 w_rx_data[0] +.sym 30495 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30496 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 30497 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30500 spi_if_ins.state_if[1] +.sym 30501 spi_if_ins.state_if[0] +.sym 30502 spi_if_ins.w_rx_data[4] +.sym 30507 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30508 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30509 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 30511 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30512 spi_if_ins.state_if[1] +.sym 30513 spi_if_ins.state_if[0] +.sym 30514 spi_if_ins.w_rx_data[5] +.sym 30518 i_rst_b$SB_IO_IN +.sym 30519 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30521 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30522 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 30527 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30528 spi_if_ins.state_if[1] +.sym 30529 spi_if_ins.state_if[0] +.sym 30531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30532 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 30533 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 30534 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 30539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30540 spi_if_ins.state_if[1] +.sym 30541 spi_if_ins.state_if[0] +.sym 30544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30547 i_rst_b$SB_IO_IN +.sym 30548 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30549 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 30551 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 30552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30553 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 30554 i_rst_b$SB_IO_IN +.sym 30555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30556 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 30557 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30558 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 30566 w_cs[2] +.sym 30567 w_fetch +.sym 30568 w_load +.sym 30569 o_led1_SB_LUT4_I1_I2[1] +.sym 30574 w_cs[2] +.sym 30575 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30576 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 30577 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 30578 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30579 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30580 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.sym 30581 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 30583 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30584 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30585 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 30588 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30589 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30594 w_rx_data[2] +.sym 30599 w_fetch +.sym 30600 w_cs[0] +.sym 30601 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.sym 30604 i_rst_b$SB_IO_IN +.sym 30605 w_fetch +.sym 30607 w_fetch +.sym 30608 w_load .sym 30609 w_cs[0] -.sym 30610 w_tx_data_smi[0] -.sym 30611 w_tx_data_io[0] -.sym 30612 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 30613 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30615 w_tx_data_io[7] -.sym 30616 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 30617 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30618 w_cs[3] -.sym 30619 w_cs[2] -.sym 30620 w_cs[1] -.sym 30621 w_cs[0] -.sym 30622 w_rx_data[0] -.sym 30626 r_tx_data[3] -.sym 30630 r_tx_data[4] -.sym 30634 r_tx_data[7] -.sym 30638 r_tx_data[1] -.sym 30642 r_tx_data[6] -.sym 30646 r_tx_data[0] -.sym 30651 w_tx_data_io[5] -.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] -.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30654 r_tx_data[5] -.sym 30658 w_rx_data[6] -.sym 30662 w_rx_data[3] -.sym 30666 w_rx_data[2] -.sym 30670 w_rx_data[5] -.sym 30674 w_rx_data[7] -.sym 30678 w_rx_data[1] -.sym 30683 w_fetch -.sym 30684 w_cs[0] -.sym 30685 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] -.sym 30686 w_rx_data[4] -.sym 30714 w_rx_data[0] -.sym 30745 r_counter -.sym 30758 tx_fifo.wr_addr_gray_rd[6] -.sym 30766 tx_fifo.wr_addr_gray_rd[0] -.sym 30772 i_smi_swe_srw$SB_IO_IN -.sym 30773 i_rst_b$SB_IO_IN -.sym 30774 tx_fifo.wr_addr_gray[4] -.sym 30778 tx_fifo.wr_addr_gray_rd[4] -.sym 30784 i_smi_soe_se$SB_IO_IN -.sym 30785 i_rst_b$SB_IO_IN -.sym 30787 tx_fifo.wr_addr[0] -.sym 30792 tx_fifo.wr_addr[1] -.sym 30793 tx_fifo.wr_addr[0] -.sym 30796 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 30800 tx_fifo.wr_addr[3] -.sym 30801 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30804 tx_fifo.wr_addr[4] -.sym 30805 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30808 tx_fifo.wr_addr[5] -.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 30812 tx_fifo.wr_addr[6] -.sym 30813 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30816 tx_fifo.wr_addr[7] -.sym 30817 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 30820 tx_fifo.wr_addr[8] -.sym 30821 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30824 tx_fifo.wr_addr[9] -.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 30826 tx_fifo.rd_addr_gray_wr[6] -.sym 30830 rx_fifo.wr_addr_gray[0] -.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 30836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 30838 tx_fifo.rd_addr_gray_wr[4] -.sym 30843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 30844 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 30845 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 30852 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 30853 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 30857 w_smi_data_input[7] -.sym 30860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 30867 tx_fifo.rd_addr_gray_wr_r[8] -.sym 30868 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 30869 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 30870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30871 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 30872 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 30873 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 30878 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 30879 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 30880 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30882 tx_fifo.rd_addr_gray_wr[8] -.sym 30886 tx_fifo.rd_addr_gray[4] -.sym 30890 tx_fifo.rd_addr_gray[8] -.sym 30894 tx_fifo.rd_addr_gray_wr[2] -.sym 30898 tx_fifo.rd_addr_gray[7] -.sym 30902 tx_fifo.rd_addr_gray_wr[1] -.sym 30906 tx_fifo.rd_addr_gray[1] -.sym 30910 tx_fifo.rd_addr_gray_wr[7] -.sym 30918 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 30930 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 30934 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 30945 tx_fifo.rd_addr[1] -.sym 30970 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -.sym 30974 tx_fifo.rd_addr_gray[6] -.sym 31006 rx_fifo.wr_addr_gray_rd[0] -.sym 31019 spi_if_ins.r_tx_byte[7] -.sym 31020 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31021 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31031 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 31032 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31033 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31058 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31064 i_ss$SB_IO_IN -.sym 31065 spi_if_ins.r_tx_data_valid -.sym 31068 i_ss$SB_IO_IN -.sym 31069 spi_if_ins.r_tx_data_valid -.sym 31074 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 31088 spi_if_ins.w_rx_data[6] -.sym 31089 spi_if_ins.w_rx_data[5] -.sym 31094 w_cs[2] -.sym 31095 w_ioc[1] -.sym 31096 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 31097 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31100 i_rst_b$SB_IO_IN -.sym 31101 w_fetch -.sym 31102 spi_if_ins.w_rx_data[0] -.sym 31106 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31111 w_ioc[1] -.sym 31112 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31113 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31123 w_load -.sym 31124 w_fetch -.sym 31125 w_cs[0] -.sym 31126 w_ioc[1] +.sym 30615 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30616 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30617 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 30618 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30619 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30620 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 30621 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 30622 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 30623 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30624 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 30625 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 30626 w_cs[1] +.sym 30627 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 30628 o_led1_SB_LUT4_I1_I2[1] +.sym 30629 o_led1_SB_LUT4_I1_I2[2] +.sym 30630 w_rx_data[1] +.sym 30637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 30642 w_cs[3] +.sym 30643 w_cs[2] +.sym 30644 w_cs[1] +.sym 30645 w_cs[0] +.sym 30650 w_rx_data[4] +.sym 30659 w_tx_data_io[5] +.sym 30660 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30661 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 30664 spi_if_ins.w_rx_data[6] +.sym 30665 spi_if_ins.w_rx_data[5] +.sym 30668 spi_if_ins.w_rx_data[6] +.sym 30669 spi_if_ins.w_rx_data[5] +.sym 30675 w_tx_data_io[7] +.sym 30676 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30677 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 30678 w_tx_data_smi[1] +.sym 30679 w_tx_data_io[1] +.sym 30680 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 30681 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30686 w_tx_data_io[2] +.sym 30687 w_tx_data_smi[2] +.sym 30688 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 30689 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30694 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 30695 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30696 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 30697 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 30699 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 30700 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30701 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 30703 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 30704 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30705 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 30706 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 30707 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 30708 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30709 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30714 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 30715 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 30716 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30717 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30719 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 30720 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30721 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 30725 r_counter +.sym 30741 i_config[3]$SB_IO_IN +.sym 30745 i_button$SB_IO_IN +.sym 30755 tx_fifo.rd_addr[0] +.sym 30760 tx_fifo.rd_addr[1] +.sym 30761 tx_fifo.rd_addr[0] +.sym 30764 tx_fifo.rd_addr[2] +.sym 30765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30768 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 30769 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 30772 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 30773 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 30776 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 30777 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 30780 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 30781 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 30784 tx_fifo.rd_addr[7] +.sym 30785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 30788 tx_fifo.rd_addr[8] +.sym 30789 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30792 tx_fifo.rd_addr[9] +.sym 30793 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 30795 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 30796 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 30800 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 30801 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 30802 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 30813 tx_fifo.rd_addr[0] +.sym 30814 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30818 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 30819 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 30820 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 30821 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 30822 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 30824 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 30825 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.sym 30826 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 30827 tx_fifo.rd_addr[1] +.sym 30828 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 30829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30830 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30831 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 30832 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30833 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 30834 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 30835 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 30836 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 30837 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 30839 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 30840 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 30841 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 30843 tx_fifo.rd_addr_gray_wr_r[8] +.sym 30844 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 30845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 30848 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30849 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30850 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 30854 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] +.sym 30855 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] +.sym 30856 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] +.sym 30857 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] +.sym 30858 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 30863 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.sym 30864 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] +.sym 30865 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 30866 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 30870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 30871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 30872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] +.sym 30873 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 30874 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 30875 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 30876 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.sym 30877 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30878 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 30882 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 30883 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 30884 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 30885 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 30887 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 30888 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 30889 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30890 tx_fifo.wr_addr_gray[1] +.sym 30894 w_tx_fifo_empty +.sym 30895 w_tx_fifo_pull +.sym 30896 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 30897 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 30901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 30906 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] +.sym 30907 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] +.sym 30908 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] +.sym 30909 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] +.sym 30910 tx_fifo.rd_addr[7] +.sym 30911 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 30912 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 30913 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 30914 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 30918 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30922 tx_fifo.rd_addr[9] +.sym 30923 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.sym 30924 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 30925 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30927 w_tx_fifo_pull +.sym 30928 tx_fifo.rd_addr[1] +.sym 30929 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.sym 30933 tx_fifo.rd_addr[1] +.sym 30934 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.sym 30938 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30944 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30945 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30947 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30951 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 30952 $PACKER_VCC_NET +.sym 30955 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 30956 $PACKER_VCC_NET +.sym 30957 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 30959 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 30960 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 30961 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 30963 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 30964 $PACKER_VCC_NET +.sym 30965 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30967 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 30968 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 30969 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30977 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30978 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30983 spi_if_ins.spi.r_tx_byte[1] +.sym 30984 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30985 spi_if_ins.spi.r_tx_byte[0] +.sym 30989 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 30993 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30994 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30995 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30996 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 30998 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 30999 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 31000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +.sym 31001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] +.sym 31005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31006 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +.sym 31007 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 31008 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 31009 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 31012 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31013 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31015 spi_if_ins.spi.r_tx_byte[7] +.sym 31016 spi_if_ins.spi.r_tx_byte[6] +.sym 31017 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31018 spi_if_ins.w_rx_data[2] +.sym 31022 spi_if_ins.w_rx_data[0] +.sym 31027 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 31028 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31030 spi_if_ins.w_rx_data[1] +.sym 31035 spi_if_ins.spi.r_tx_byte[5] +.sym 31036 spi_if_ins.spi.r_tx_byte[4] +.sym 31037 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31039 spi_if_ins.spi.r_tx_byte[3] +.sym 31040 spi_if_ins.spi.r_tx_byte[2] +.sym 31041 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31042 spi_if_ins.r_tx_byte[2] +.sym 31046 spi_if_ins.r_tx_byte[5] +.sym 31050 spi_if_ins.r_tx_byte[0] +.sym 31054 spi_if_ins.r_tx_byte[4] +.sym 31058 spi_if_ins.r_tx_byte[3] +.sym 31062 spi_if_ins.r_tx_byte[6] +.sym 31066 spi_if_ins.r_tx_byte[1] +.sym 31070 spi_if_ins.r_tx_byte[7] +.sym 31075 i_rst_b$SB_IO_IN +.sym 31076 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 31077 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 31078 w_cs[1] +.sym 31079 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 31080 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 31081 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31082 w_rx_data[2] +.sym 31087 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31088 io_pmod[2]$SB_IO_IN +.sym 31089 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31092 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 31093 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.sym 31094 w_rx_data[7] +.sym 31102 w_rx_data[5] +.sym 31107 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 31108 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31109 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 31110 o_shdn_tx_lna$SB_IO_OUT +.sym 31111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] +.sym 31112 i_button_SB_LUT4_I0_O[1] +.sym 31113 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] +.sym 31115 w_ioc[4] +.sym 31116 w_ioc[3] +.sym 31117 w_ioc[2] +.sym 31119 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 31120 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31121 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 31122 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 31123 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31124 o_led1_SB_LUT4_I1_I3[3] +.sym 31125 o_led0_SB_LUT4_I1_O[1] .sym 31127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31128 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 31129 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 31132 w_ioc[1] -.sym 31133 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 31134 w_cs[1] -.sym 31135 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 31136 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31137 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31140 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 31147 i_config[1]$SB_IO_IN -.sym 31148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31149 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31152 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31153 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31155 w_ioc[1] -.sym 31156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31157 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 31158 w_ioc[1] -.sym 31159 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31160 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 31161 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31163 w_ioc[1] -.sym 31164 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31165 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 31167 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 31170 w_cs[1] -.sym 31171 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 31172 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31173 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31174 o_tr_vc1_b$SB_IO_OUT -.sym 31175 io_ctrl_ins.pmod_dir_state[4] -.sym 31176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31177 i_button_SB_LUT4_I0_O[1] -.sym 31178 w_rx_data[7] -.sym 31182 w_ioc[1] -.sym 31183 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31184 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.sym 31185 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31186 w_rx_data[1] -.sym 31191 w_ioc[1] -.sym 31192 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31193 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -.sym 31194 w_rx_data[6] -.sym 31198 w_rx_data[4] -.sym 31203 o_rx_h_tx_l_b$SB_IO_OUT -.sym 31204 i_button_SB_LUT4_I0_O[1] -.sym 31205 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 31206 i_config[2]$SB_IO_IN -.sym 31207 io_ctrl_ins.pmod_dir_state[5] -.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31210 i_config[3]$SB_IO_IN -.sym 31211 io_ctrl_ins.pmod_dir_state[6] -.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31223 o_tr_vc1$SB_IO_OUT -.sym 31224 i_button_SB_LUT4_I0_O[1] -.sym 31225 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 31226 i_button$SB_IO_IN -.sym 31227 io_ctrl_ins.pmod_dir_state[7] -.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31231 o_rx_h_tx_l$SB_IO_OUT -.sym 31232 i_button_SB_LUT4_I0_O[1] -.sym 31233 i_button_SB_LUT4_I0_O[2] -.sym 31250 w_rx_data[5] -.sym 31270 tx_fifo.wr_addr_gray[6] -.sym 31294 tx_fifo.wr_addr_gray[0] -.sym 31301 tx_fifo.wr_addr[1] -.sym 31304 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 31305 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 31328 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31329 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 31332 i_rst_b$SB_IO_IN -.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 31336 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31337 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31342 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 31346 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31357 tx_fifo.wr_addr[0] -.sym 31360 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31361 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 31364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 31365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 31366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31367 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 31368 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 31369 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 31370 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 31374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 31380 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 31381 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -.sym 31382 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 31390 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 31394 tx_fifo.wr_addr_gray[1] -.sym 31398 tx_fifo.wr_addr_gray[3] -.sym 31402 tx_fifo.wr_addr_gray[2] -.sym 31406 tx_fifo.wr_addr_gray[8] -.sym 31418 tx_fifo.wr_addr_gray[5] -.sym 31422 tx_fifo.wr_addr_gray[7] -.sym 31426 tx_fifo.rd_addr_gray_wr[5] -.sym 31446 tx_fifo.rd_addr_gray[0] -.sym 31462 spi_if_ins.spi.r2_rx_done -.sym 31470 tx_fifo.rd_addr_gray[5] -.sym 31476 spi_if_ins.spi.r3_rx_done -.sym 31477 spi_if_ins.spi.r2_rx_done -.sym 31514 i_sck$SB_IO_IN -.sym 31522 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31538 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 31546 spi_if_ins.spi.SCKr[0] -.sym 31558 w_rx_data[0] -.sym 31563 i_rst_b$SB_IO_IN -.sym 31564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 31586 spi_if_ins.w_rx_data[1] -.sym 31598 spi_if_ins.w_rx_data[4] -.sym 31602 spi_if_ins.w_rx_data[3] -.sym 31607 w_ioc[4] -.sym 31608 w_ioc[3] -.sym 31609 w_ioc[2] -.sym 31611 w_ioc[4] -.sym 31612 w_ioc[3] -.sym 31613 w_ioc[2] -.sym 31614 spi_if_ins.w_rx_data[2] -.sym 31618 w_cs[2] -.sym 31619 w_load -.sym 31620 w_fetch -.sym 31621 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31624 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31625 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 31627 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31628 io_pmod[0]$SB_IO_IN -.sym 31629 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31630 w_cs[2] -.sym 31631 w_load -.sym 31632 w_fetch -.sym 31633 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31635 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31636 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31128 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 31129 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31131 w_ioc[4] +.sym 31132 w_ioc[3] +.sym 31133 w_ioc[2] +.sym 31135 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.sym 31136 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31137 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.sym 31138 spi_if_ins.w_rx_data[3] +.sym 31142 w_tx_data_smi[0] +.sym 31143 w_tx_data_io[0] +.sym 31144 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 31145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31146 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 31152 spi_if_ins.w_rx_data[6] +.sym 31153 spi_if_ins.w_rx_data[5] +.sym 31154 w_cs[2] +.sym 31155 w_fetch +.sym 31156 w_load +.sym 31157 o_led1_SB_LUT4_I1_I3[3] +.sym 31161 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 31166 spi_if_ins.w_rx_data[4] +.sym 31170 w_cs[3] +.sym 31171 w_cs[2] +.sym 31172 w_cs[1] +.sym 31173 w_cs[0] +.sym 31176 i_rst_b$SB_IO_IN +.sym 31177 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 31178 w_cs[3] +.sym 31179 w_cs[2] +.sym 31180 w_cs[1] +.sym 31181 w_cs[0] +.sym 31184 spi_if_ins.w_rx_data[6] +.sym 31185 spi_if_ins.w_rx_data[5] +.sym 31186 w_cs[3] +.sym 31187 w_cs[2] +.sym 31188 w_cs[1] +.sym 31189 w_cs[0] +.sym 31190 w_cs[3] +.sym 31191 w_cs[2] +.sym 31192 w_cs[1] +.sym 31193 w_cs[0] +.sym 31202 r_tx_data[5] +.sym 31206 r_tx_data[2] +.sym 31210 r_tx_data[3] +.sym 31214 r_tx_data[6] +.sym 31218 r_tx_data[4] +.sym 31222 r_tx_data[0] +.sym 31226 r_tx_data[7] +.sym 31230 r_tx_data[1] +.sym 31267 tx_fifo.wr_addr[0] +.sym 31272 tx_fifo.wr_addr[1] +.sym 31273 tx_fifo.wr_addr[0] +.sym 31276 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 31277 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 31280 tx_fifo.wr_addr[3] +.sym 31281 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 31284 tx_fifo.wr_addr[4] +.sym 31285 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 31288 tx_fifo.wr_addr[5] +.sym 31289 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 31292 tx_fifo.wr_addr[6] +.sym 31293 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 31296 tx_fifo.wr_addr[7] +.sym 31297 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31300 tx_fifo.wr_addr[8] +.sym 31301 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 31304 tx_fifo.wr_addr[9] +.sym 31305 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 31306 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 31319 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 31320 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31321 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 31328 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 31329 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31331 tx_fifo.wr_addr[1] +.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 31337 tx_fifo.wr_addr[1] +.sym 31340 tx_fifo.wr_addr[3] +.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31344 tx_fifo.wr_addr[4] +.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31348 tx_fifo.wr_addr[5] +.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31352 tx_fifo.wr_addr[6] +.sym 31353 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31356 tx_fifo.wr_addr[7] +.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31360 tx_fifo.wr_addr[8] +.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 31364 tx_fifo.wr_addr[9] +.sym 31365 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 31367 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31368 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31369 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31370 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] +.sym 31375 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31379 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.sym 31380 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.sym 31381 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31382 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +.sym 31383 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31385 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] +.sym 31386 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31390 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +.sym 31391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31393 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] +.sym 31396 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 31397 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 31398 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31399 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31400 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 31401 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 31402 tx_fifo.rd_addr_gray_wr[3] +.sym 31406 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31407 tx_fifo.rd_addr_gray_wr_r[8] +.sym 31408 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31409 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 31410 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31411 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31412 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31413 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 31414 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 31415 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 31416 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 31417 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 31418 tx_fifo.rd_addr_gray[0] +.sym 31422 tx_fifo.rd_addr_gray[7] +.sym 31427 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31432 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31433 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31436 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31437 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 31438 i_ss$SB_IO_IN +.sym 31439 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31440 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31441 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31449 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31451 w_rx_fifo_empty +.sym 31452 w_tx_fifo_full +.sym 31453 w_smi_data_direction +.sym 31458 tx_fifo.rd_addr_gray_wr[8] +.sym 31462 tx_fifo.rd_addr_gray_wr[7] +.sym 31466 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 31470 tx_fifo.rd_addr_gray[8] +.sym 31474 tx_fifo.rd_addr_gray_wr[9] +.sym 31479 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31480 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31481 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31482 tx_fifo.rd_addr_gray[3] +.sym 31486 tx_fifo.rd_addr[9] +.sym 31502 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 31513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 31516 i_ss$SB_IO_IN +.sym 31517 spi_if_ins.r_tx_data_valid +.sym 31520 i_ss$SB_IO_IN +.sym 31521 spi_if_ins.r_tx_data_valid +.sym 31545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 31546 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 31550 i_rst_b$SB_IO_IN +.sym 31551 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 31553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 31558 w_rx_data[2] +.sym 31570 w_rx_data[0] +.sym 31586 w_rx_data[0] +.sym 31590 w_rx_data[3] +.sym 31596 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 31597 i_button_SB_LUT4_I0_O[1] +.sym 31598 w_cs[1] +.sym 31599 w_fetch +.sym 31600 w_load +.sym 31601 o_led0_SB_LUT4_I1_O[1] +.sym 31602 w_rx_data[1] +.sym 31610 w_rx_data[4] +.sym 31614 w_rx_data[2] +.sym 31620 o_led1_SB_LUT4_I1_I2[1] +.sym 31621 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 31622 o_led1_SB_LUT4_I1_O[0] +.sym 31623 o_led0_SB_LUT4_I1_O[1] +.sym 31624 o_led1_SB_LUT4_I1_O[2] +.sym 31625 o_led1_SB_LUT4_I1_O[3] +.sym 31626 o_led0_SB_LUT4_I1_O[0] +.sym 31627 o_led0_SB_LUT4_I1_O[1] +.sym 31628 o_led0_SB_LUT4_I1_O[2] +.sym 31629 o_led0_SB_LUT4_I1_O[3] +.sym 31630 o_shdn_rx_lna$SB_IO_OUT +.sym 31631 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31632 io_pmod[1]$SB_IO_IN +.sym 31633 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31636 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] .sym 31637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31639 w_ioc[1] -.sym 31640 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31641 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 31643 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 31644 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 31645 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] -.sym 31646 o_shdn_rx_lna$SB_IO_OUT -.sym 31647 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31648 io_pmod[1]$SB_IO_IN -.sym 31649 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31650 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 31651 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 31652 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] -.sym 31653 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] -.sym 31655 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 31656 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 31657 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] -.sym 31659 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] -.sym 31660 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31661 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] -.sym 31662 w_cs[1] -.sym 31663 w_load -.sym 31664 w_fetch -.sym 31665 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 31666 io_ctrl_ins.mixer_en_state -.sym 31667 i_button_SB_LUT4_I0_O[1] -.sym 31668 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] -.sym 31669 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] -.sym 31670 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 31671 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.sym 31672 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 31673 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 31674 o_tr_vc2$SB_IO_OUT -.sym 31675 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31676 io_pmod[3]$SB_IO_IN -.sym 31677 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31678 o_shdn_tx_lna$SB_IO_OUT -.sym 31679 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31680 io_pmod[2]$SB_IO_IN -.sym 31681 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31682 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] -.sym 31683 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 31684 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31685 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31686 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] -.sym 31687 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] -.sym 31688 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31689 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31690 w_rx_data[3] -.sym 31694 w_cs[1] -.sym 31695 w_load -.sym 31696 w_fetch -.sym 31697 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31698 w_rx_data[2] -.sym 31702 i_config[0]$SB_IO_IN -.sym 31703 io_ctrl_ins.pmod_dir_state[3] -.sym 31704 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -.sym 31705 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31706 i_rst_b$SB_IO_IN -.sym 31707 w_cs[1] -.sym 31708 w_load -.sym 31709 w_fetch -.sym 31710 w_rx_data[0] -.sym 31718 w_rx_data[0] -.sym 31734 w_rx_data[1] -.sym 31740 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 31741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] -.sym 31783 i_rst_b$SB_IO_IN -.sym 31784 w_smi_data_input[7] -.sym 31785 smi_ctrl_ins.tx_reg_state[0] -.sym 31787 w_smi_data_input[7] -.sym 31788 smi_ctrl_ins.tx_reg_state[2] -.sym 31789 smi_ctrl_ins.tx_reg_state[1] -.sym 31791 i_rst_b$SB_IO_IN -.sym 31792 w_smi_data_input[7] -.sym 31793 smi_ctrl_ins.tx_reg_state[2] -.sym 31796 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 31797 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 31798 i_rst_b$SB_IO_IN -.sym 31799 w_smi_data_input[7] -.sym 31800 smi_ctrl_ins.tx_reg_state[3] -.sym 31801 smi_ctrl_ins.tx_reg_state[0] -.sym 31803 i_rst_b$SB_IO_IN -.sym 31804 smi_ctrl_ins.tx_reg_state[3] -.sym 31805 smi_ctrl_ins.tx_reg_state[0] -.sym 31807 i_rst_b$SB_IO_IN -.sym 31808 w_smi_data_input[7] -.sym 31809 smi_ctrl_ins.tx_reg_state[1] -.sym 31811 tx_fifo.wr_addr[1] -.sym 31816 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 31817 tx_fifo.wr_addr[1] -.sym 31820 tx_fifo.wr_addr[3] -.sym 31821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31824 tx_fifo.wr_addr[4] -.sym 31825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31828 tx_fifo.wr_addr[5] -.sym 31829 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31832 tx_fifo.wr_addr[6] -.sym 31833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31836 tx_fifo.wr_addr[7] -.sym 31837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31840 tx_fifo.wr_addr[8] -.sym 31841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 31844 tx_fifo.wr_addr[9] -.sym 31845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 31847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 31851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 31853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 31855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 31856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 31857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31858 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31859 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 31860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 31863 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31864 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31866 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 31870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 31871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 31874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 31875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 31876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 31877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 31878 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31883 tx_fifo.wr_addr[1] -.sym 31884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31885 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 31886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31887 tx_fifo.rd_addr_gray_wr_r[8] -.sym 31888 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31890 tx_fifo.wr_addr[9] -.sym 31896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 31897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 31899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 31900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 31901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 31903 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 31904 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 31905 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 31915 w_tx_fifo_full -.sym 31916 tx_fifo.wr_addr[1] -.sym 31917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31922 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 31923 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 31924 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 31925 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 31927 w_tx_fifo_full -.sym 31928 smi_ctrl_ins.r_fifo_push_1 -.sym 31929 smi_ctrl_ins.r_fifo_push -.sym 31934 smi_ctrl_ins.r_fifo_push -.sym 31938 tx_fifo.rd_addr_gray_wr[0] -.sym 31943 w_rx_fifo_empty -.sym 31944 w_tx_fifo_full -.sym 31945 o_led0$SB_IO_OUT -.sym 31946 spi_if_ins.spi.r_rx_done -.sym 31962 tx_fifo.rd_addr_gray_wr[9] -.sym 31974 i_mosi$SB_IO_IN -.sym 31985 o_miso_$_TBUF__Y_E -.sym 31986 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32002 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32006 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 32010 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 32014 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32018 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 32022 i_mosi$SB_IO_IN -.sym 32026 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32030 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31638 o_tr_vc2$SB_IO_OUT +.sym 31639 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31640 io_pmod[3]$SB_IO_IN +.sym 31641 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31642 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 31643 o_led0_SB_LUT4_I1_O[1] +.sym 31644 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 31645 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 31646 io_ctrl_ins.pmod_dir_state[0] +.sym 31647 o_led0$SB_IO_OUT +.sym 31648 o_led1_SB_LUT4_I1_I2[1] +.sym 31649 o_led1_SB_LUT4_I1_I3[3] +.sym 31652 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 31653 o_led1_SB_LUT4_I1_I3[3] +.sym 31654 w_cs[1] +.sym 31655 w_fetch +.sym 31656 w_load +.sym 31657 o_led1_SB_LUT4_I1_I2[1] +.sym 31662 io_ctrl_ins.pmod_dir_state[1] +.sym 31663 o_led1$SB_IO_OUT +.sym 31664 o_led1_SB_LUT4_I1_I2[1] +.sym 31665 o_led1_SB_LUT4_I1_I3[3] +.sym 31666 w_rx_data[0] +.sym 31674 i_rst_b$SB_IO_IN +.sym 31675 w_cs[1] +.sym 31676 w_fetch +.sym 31677 w_load +.sym 31678 i_config[0]$SB_IO_IN +.sym 31679 io_ctrl_ins.pmod_dir_state[3] +.sym 31680 o_led1_SB_LUT4_I1_I2[1] +.sym 31681 o_led1_SB_LUT4_I1_I3[3] +.sym 31686 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 31687 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 31688 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31689 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31699 o_led1_SB_LUT4_I1_I2[0] +.sym 31700 o_led1_SB_LUT4_I1_I2[1] +.sym 31701 o_led1_SB_LUT4_I1_I2[2] +.sym 31706 i_config[1]$SB_IO_IN +.sym 31707 o_led1_SB_LUT4_I1_I3[1] +.sym 31708 o_led1_SB_LUT4_I1_I2[1] +.sym 31709 o_led1_SB_LUT4_I1_I3[3] +.sym 31710 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 31711 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31712 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.sym 31713 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 31730 o_tr_vc1_b$SB_IO_OUT +.sym 31731 i_button_SB_LUT4_I0_O[1] +.sym 31732 i_config_SB_LUT4_I0_2_O[2] +.sym 31733 i_config_SB_LUT4_I0_2_O[3] +.sym 31782 tx_fifo.rd_addr_gray[4] +.sym 31793 i_smi_soe_se$SB_IO_IN +.sym 31794 tx_fifo.rd_addr_gray_wr[4] +.sym 31814 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 31818 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31824 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 31825 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31826 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 31830 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 31834 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 31842 tx_fifo.rd_addr_gray_wr[2] +.sym 31846 tx_fifo.rd_addr_gray[6] +.sym 31850 tx_fifo.rd_addr_gray_wr[6] +.sym 31854 tx_fifo.rd_addr_gray[2] +.sym 31862 tx_fifo.rd_addr_gray[5] +.sym 31870 tx_fifo.rd_addr_gray_wr[5] +.sym 31892 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 31893 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 31894 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 31896 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 31897 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 31898 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.sym 31907 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 31908 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 31909 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 31911 w_tx_fifo_full +.sym 31912 tx_fifo.wr_addr[1] +.sym 31913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31919 tx_fifo.wr_addr[1] +.sym 31920 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 31922 tx_fifo.rd_addr_gray_wr[0] +.sym 31928 i_rst_b$SB_IO_IN +.sym 31929 w_tx_fifo_pull +.sym 31962 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31995 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 31996 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31997 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31998 spi_if_ins.r_tx_byte[7] +.sym 31999 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 32001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32002 i_mosi$SB_IO_IN +.sym 32006 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 32013 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 32014 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 32024 i_ss$SB_IO_IN +.sym 32025 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 32030 spi_if_ins.spi.r_temp_rx_byte[4] .sym 32034 spi_if_ins.spi.r_rx_byte[5] -.sym 32038 spi_if_ins.spi.r_rx_byte[6] -.sym 32042 spi_if_ins.spi.r_rx_byte[2] -.sym 32046 spi_if_ins.spi.r_rx_byte[1] -.sym 32050 spi_if_ins.spi.r_rx_byte[4] -.sym 32054 spi_if_ins.spi.r_rx_byte[7] -.sym 32058 spi_if_ins.spi.r_rx_byte[0] -.sym 32062 spi_if_ins.spi.r_rx_byte[3] -.sym 32090 spi_if_ins.w_rx_data[0] -.sym 32094 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 32098 spi_if_ins.w_rx_data[2] -.sym 32102 spi_if_ins.w_rx_data[1] -.sym 32106 spi_if_ins.w_rx_data[5] -.sym 32110 spi_if_ins.w_rx_data[4] -.sym 32114 spi_if_ins.w_rx_data[6] -.sym 32122 spi_if_ins.w_rx_data[3] -.sym 32143 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 32144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 32038 spi_if_ins.spi.r_rx_byte[0] +.sym 32042 spi_if_ins.spi.r_rx_byte[4] +.sym 32046 spi_if_ins.spi.r_rx_byte[3] +.sym 32050 spi_if_ins.spi.r_rx_byte[7] +.sym 32054 spi_if_ins.spi.r_rx_byte[2] +.sym 32058 spi_if_ins.spi.r_rx_byte[6] +.sym 32062 spi_if_ins.spi.r_rx_byte[1] +.sym 32066 spi_if_ins.w_rx_data[2] +.sym 32070 spi_if_ins.w_rx_data[1] +.sym 32074 spi_if_ins.w_rx_data[0] +.sym 32082 spi_if_ins.w_rx_data[3] +.sym 32098 i_rst_b$SB_IO_IN +.sym 32099 o_led0_SB_LUT4_I1_O[0] +.sym 32100 o_led1_SB_LUT4_I1_I2[0] +.sym 32101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32102 w_rx_data[1] +.sym 32114 w_rx_data[4] +.sym 32123 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32124 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 32125 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 32126 w_rx_data[3] +.sym 32132 o_led1_SB_LUT4_I1_O[0] +.sym 32133 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] +.sym 32134 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +.sym 32135 o_led1_SB_LUT4_I1_I2[0] +.sym 32136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32137 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32143 io_pmod[0]$SB_IO_IN +.sym 32144 io_ctrl_ins.mixer_en_state .sym 32145 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 32158 w_rx_data[0] -.sym 32162 w_rx_data[0] -.sym 32166 w_rx_data[1] -.sym 32170 w_rx_data[4] -.sym 32176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 32177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 32178 w_rx_data[2] -.sym 32182 w_rx_data[3] -.sym 32186 i_rst_b$SB_IO_IN -.sym 32187 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 32188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32189 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32192 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 32194 w_rx_data[0] -.sym 32198 w_rx_data[4] -.sym 32202 w_rx_data[7] -.sym 32206 w_rx_data[6] -.sym 32210 w_rx_data[2] -.sym 32214 w_rx_data[3] -.sym 32218 w_rx_data[1] -.sym 32222 w_rx_data[5] -.sym 32252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 32253 i_button_SB_LUT4_I0_O[1] -.sym 32473 i_ss$SB_IO_IN -.sym 32474 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32483 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32488 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32489 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32492 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32493 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 32498 i_ss$SB_IO_IN -.sym 32499 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32500 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32501 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32505 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32507 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32508 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32509 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32514 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32526 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 32148 o_led1_SB_LUT4_I1_O[0] +.sym 32149 o_led0_SB_LUT4_I1_O[0] +.sym 32150 io_ctrl_ins.rf_pin_state[2] +.sym 32151 o_led1_SB_LUT4_I1_I2[0] +.sym 32152 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32159 io_ctrl_ins.rf_pin_state[1] +.sym 32160 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32161 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32162 io_ctrl_ins.rf_pin_state[0] +.sym 32163 o_led1_SB_LUT4_I1_I2[0] +.sym 32164 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32166 io_ctrl_ins.rf_pin_state[5] +.sym 32167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32168 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 32169 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32175 io_ctrl_ins.rf_pin_state[6] +.sym 32176 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 32180 o_led1_SB_LUT4_I1_I2[0] +.sym 32181 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 32182 o_led1_SB_LUT4_I1_I2[0] +.sym 32183 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 32184 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32185 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32186 io_ctrl_ins.rf_pin_state[4] +.sym 32187 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] +.sym 32188 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 32189 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32191 io_ctrl_ins.rf_pin_state[7] +.sym 32192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.sym 32193 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 32198 w_rx_data[0] +.sym 32214 w_rx_data[6] +.sym 32226 spi_if_ins.w_rx_data[6] +.sym 32328 i_smi_soe_se$SB_IO_IN +.sym 32329 i_rst_b$SB_IO_IN +.sym 32344 i_smi_swe_srw$SB_IO_IN +.sym 32345 i_rst_b$SB_IO_IN +.sym 32357 i_ss$SB_IO_IN +.sym 32359 w_smi_data_input[7] +.sym 32360 smi_ctrl_ins.tx_reg_state[2] +.sym 32361 smi_ctrl_ins.tx_reg_state[1] +.sym 32363 i_rst_b$SB_IO_IN +.sym 32364 w_smi_data_input[7] +.sym 32365 smi_ctrl_ins.tx_reg_state[1] +.sym 32366 i_rst_b$SB_IO_IN +.sym 32367 w_smi_data_input[7] +.sym 32368 smi_ctrl_ins.tx_reg_state[3] +.sym 32369 smi_ctrl_ins.tx_reg_state[0] +.sym 32371 i_rst_b$SB_IO_IN +.sym 32372 w_smi_data_input[7] +.sym 32373 smi_ctrl_ins.tx_reg_state[0] +.sym 32375 i_rst_b$SB_IO_IN +.sym 32376 smi_ctrl_ins.tx_reg_state[3] +.sym 32377 smi_ctrl_ins.tx_reg_state[0] +.sym 32380 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 32381 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 32383 i_rst_b$SB_IO_IN +.sym 32384 w_smi_data_input[7] +.sym 32385 smi_ctrl_ins.tx_reg_state[2] +.sym 32409 w_smi_data_input[7] +.sym 32421 w_tx_fifo_empty +.sym 32482 spi_if_ins.spi.r2_rx_done +.sym 32490 i_sck$SB_IO_IN +.sym 32494 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 32500 spi_if_ins.spi.r3_rx_done +.sym 32501 spi_if_ins.spi.r2_rx_done +.sym 32502 spi_if_ins.spi.r_rx_done +.sym 32506 spi_if_ins.spi.SCKr[0] +.sym 32514 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 32518 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 32522 i_mosi$SB_IO_IN +.sym 32526 spi_if_ins.spi.r_temp_rx_byte[3] .sym 32530 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32534 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 32540 i_ss$SB_IO_IN -.sym 32541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32542 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32614 w_rx_data[2] -.sym 32622 w_rx_data[1] -.sym 32630 w_rx_data[3] +.sym 32534 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 32538 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 32549 i_rst_b$SB_IO_IN +.sym 32550 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 32554 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 32562 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 32570 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 32602 w_rx_data[3] +.sym 32622 w_rx_data[2] +.sym 32630 w_rx_data[1] +.sym 32634 w_rx_data[0] +.sym 32650 w_rx_data[3] .sym 32670 w_rx_data[0] -.sym 32686 io_ctrl_ins.rf_pin_state[2] -.sym 32687 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32688 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32689 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32690 io_ctrl_ins.rf_pin_state[0] -.sym 32691 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32693 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32706 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32707 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 32708 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32709 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32710 io_ctrl_ins.rf_pin_state[5] -.sym 32711 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32712 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 32713 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32714 io_ctrl_ins.rf_pin_state[4] -.sym 32715 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32716 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 32717 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32718 io_ctrl_ins.rf_pin_state[3] -.sym 32719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32721 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32723 io_ctrl_ins.rf_pin_state[1] -.sym 32724 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.sym 32725 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32727 io_ctrl_ins.rf_pin_state[6] -.sym 32728 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32729 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 32732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -.sym 32733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] -.sym 32735 io_ctrl_ins.rf_pin_state[7] -.sym 32736 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32737 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 32674 w_rx_data[1] +.sym 32678 w_rx_data[0] +.sym 32717 o_rx_h_tx_l_b$SB_IO_OUT diff --git a/firmware/top.bin b/firmware/top.bin index 341c3ff..a4bf763 100644 Binary files a/firmware/top.bin and b/firmware/top.bin differ diff --git a/firmware/top.blif b/firmware/top.blif index 2d0c15c..29e9832 100644 --- a/firmware/top.blif +++ b/firmware/top.blif @@ -7,18 +7,30 @@ .names $true 1 .names $undef -.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=i_button_SB_LUT4_I0_O[2] +.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=i_button_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=i_config_SB_LUT4_I0_2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001101011111 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=i_config_SB_LUT4_I0_2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I2[2] O=i_config_SB_LUT4_I0_2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 .gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" @@ -38,140 +50,114 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.lna_rx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000111111001100 -.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011100000000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.lna_tx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001110101010 -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011100000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000101010101010 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.mixer_en_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.mixer_en_state I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I2=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] I3=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D +.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_pmod[0] I2=io_ctrl_ins.mixer_en_state I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=o_led0_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000111111111111 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011110011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E Q=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 +.param LUT_INIT 1110010000000000 .gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001011111111 .gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110110011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod[2] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=o_led1_SB_LUT4_I1_I3[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101111100010011 .gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000000111111 -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001011111111 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100111111111111 +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000100000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000101010101010 +.gate SB_LUT4 I0=$false I1=$false I2=o_led1_SB_LUT4_I1_I2[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 .gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001011111111 .gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" @@ -184,11 +170,11 @@ .gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[5] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000010001000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000100010000000 @@ -196,14 +182,6 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=i_config[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1101111100000000 .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" @@ -252,142 +230,70 @@ .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.rx_h_b_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000011111100 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.rx_h_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111111100001100 -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001100000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=i_config_SB_LUT4_I0_2_O[1] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_1_b_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.pmod_dir_state[4] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=i_config_SB_LUT4_I0_2_O[1] I2=i_config_SB_LUT4_I0_2_O[2] I3=i_config_SB_LUT4_I0_2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010011010101111 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111011100100000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=sys_ctrl_ins.i_cs O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state +.param LUT_INIT 1111111110001111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_1_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000001110101010 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_2_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[3] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1011100000000000 -.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.pmod_dir_state[3] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.pmod_dir_state[3] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001001101011111 @@ -403,22 +309,26 @@ .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_pmod_SB_DFFE_Q_E +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_pmod_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=i_config_SB_LUT4_I0_2_O[1] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=spi_if_ins.o_fetch_cmd O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_fetch_cmd I3=spi_if_ins.o_load_cmd O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000010000000 +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:288.7-293.4" @@ -467,7 +377,7 @@ .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000000000000 @@ -734,6 +644,10 @@ .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -961,30 +875,26 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[0] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110000001100 +.param LUT_INIT 1100110011000000 .gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 .gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000010000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 +.param LUT_INIT 0010101000010101 .gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -997,13 +907,48 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led0 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=o_led1_SB_DFFER_Q_E +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led0_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 +.param LUT_INIT 0001010100111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I2[1] O=o_led1_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010011010101111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000000011 +.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[1] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011100000000000 .gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso .attr src "top.v:150.19-150.43" .gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=tx_fifo.full_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req @@ -1023,14 +968,14 @@ .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6] .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -1040,43 +985,43 @@ .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5] .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001111 +.param LUT_INIT 0000000000111111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4] .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2] @@ -1085,15 +1030,15 @@ .gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] O=r_tx_data_SB_DFFE_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111011111111 +.param LUT_INIT 1111001011111111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] @@ -1106,36 +1051,40 @@ .gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O +.param LUT_INIT 1111001011111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001111 +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 .gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105" -.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D +.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] I1=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1110101010101010 @@ -1146,7 +1095,7 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111111110000000 -.gate SB_LUT4 I0=rx_fifo.full_o I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[1] +.gate SB_LUT4 I0=rx_fifo.full_o I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000101000000010 @@ -1166,76 +1115,60 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[8] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011001101011010 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110000000101 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[3] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.param LUT_INIT 1000001010111110 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[7] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[5] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[3] +.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[2] .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4] .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 .gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -1309,23 +1242,59 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] I2=o_led1 I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000001100 -.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I2[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.param LUT_INIT 0010000000000000 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.mem_i.0.0_WCLKE O=rx_fifo.wr_addr_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[16] I2=lvds_rx_09_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1346,23 +1315,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1383,23 +1352,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[22] I2=lvds_rx_09_inst.o_fifo_data[22] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[23] I2=lvds_rx_09_inst.o_fifo_data[23] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1420,23 +1389,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[26] I2=lvds_rx_09_inst.o_fifo_data[26] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[29] I2=lvds_rx_24_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[27] I2=lvds_rx_09_inst.o_fifo_data[27] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1457,23 +1426,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[0] I2=lvds_rx_24_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[31] I2=lvds_rx_09_inst.o_fifo_data[31] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1494,23 +1463,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1531,23 +1500,23 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[6] I2=lvds_rx_09_inst.o_fifo_data[6] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1568,300 +1537,279 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[10] I2=lvds_rx_09_inst.o_fifo_data[10] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[12] I2=lvds_rx_09_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[13] I2=lvds_rx_24_inst.o_fifo_data[13] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[15] I2=lvds_rx_24_inst.o_fifo_data[15] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.param LUT_INIT 1100110011110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[5] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[7] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[4] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[3] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[3] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[4] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[2] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.param LUT_INIT 1001000000000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 +.param LUT_INIT 1010001011110011 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[2] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 .gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[1] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[3] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001111111110110 -.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001111011 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110011101111110 -.gate SB_LUT4 I0=rx_fifo.rd_addr[3] I1=rx_fifo.rd_addr[2] I2=rx_fifo.wr_addr_gray_rd_r[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[8] I2=rx_fifo.rd_addr[7] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.wr_addr_gray_rd_r[5] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=rx_fifo.empty_o I1=rx_fifo.wr_addr_gray_rd_r[0] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000010000010 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[2] I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001100 +.param LUT_INIT 0000000000111100 +.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101101000001 +.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0111110101000001 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011001111 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110011101111110 +.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.rd_addr[1] I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001101111 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.rd_addr[3] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011101101 +.gate SB_LUT4 I0=rx_fifo.rd_addr[8] I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.wr_addr_gray_rd_r[6] I3=rx_fifo.rd_addr[6] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000000110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.wr_addr_gray_rd_r[5] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100110010000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[1] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000001000000001 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000001001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[7] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[6] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[5] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000101011001111 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.param LUT_INIT 1100111101000101 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000001000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001101010001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000010000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[8] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" @@ -1922,25 +1870,25 @@ .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] @@ -1983,7 +1931,7 @@ .param LUT_INIT 0110100110010110 .gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[1] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] @@ -1998,15 +1946,31 @@ .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[7] .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[5] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_8_D @@ -2045,23 +2009,23 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] @@ -2088,10 +2052,10 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] @@ -2110,17 +2074,17 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D @@ -2208,23 +2172,19 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=o_led1 E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 .gate SB_LUT4 I0=io_ctrl_ins.o_data_out[2] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -2284,10 +2244,10 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.r_fifo_pulled_data[3] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001000110000 +.param LUT_INIT 0010001100100000 .gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[27] I1=smi_ctrl_ins.r_fifo_pulled_data[19] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -2352,18 +2312,18 @@ .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 +.param LUT_INIT 0010000000000000 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=smi_ctrl_ins.r_fifo_pull I3=smi_ctrl_ins.r_fifo_pull_1 O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=smi_ctrl_ins.r_fifo_pull_1 I3=smi_ctrl_ins.r_fifo_pull O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 @@ -2523,26 +2483,6 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 .gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -2679,15 +2619,43 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000000100 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000010 .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000010 +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000010111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] @@ -2779,6 +2747,10 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=sys_ctrl_ins.i_cs O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 .gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[7] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" @@ -2873,31 +2845,31 @@ .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.o_spi_miso .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D +.gate SB_LUT4 I0=spi_if_ins.r_tx_byte[7] I1=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000100010001011 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000101000101 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010101000001000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[7] I2=spi_if_ins.spi.r_tx_byte[6] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011001111 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010100011111101 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[7] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101001100000000 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[6] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001010011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_byte[4] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_byte[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.param LUT_INIT 0011001100001111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_byte[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100111111000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 @@ -3089,6 +3061,14 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0111011100100000 .gate SB_DFFNSS C=lvds_clock D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105" @@ -3096,70 +3076,66 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1110101010101010 -.gate SB_LUT4 I0=tx_fifo.empty_o I1=lvds_tx_inst.r_pulled I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.wr_addr_gray_rd_r[9] O=tx_fifo.empty_o_SB_LUT4_I0_O[2] +.gate SB_LUT4 I0=tx_fifo.empty_o I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.empty_o_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001000000010 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I2=tx_fifo.empty_o_SB_LUT4_I0_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.param LUT_INIT 0010000000100010 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.empty_o_SB_LUT4_I0_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000010010000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[8] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110110101001000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001010101010 -.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101010100010100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[7] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.param LUT_INIT 1101110100001101 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr[6] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr[6] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010010111110 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000000111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr[8] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[7] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011101011 -.gate SB_LUT4 I0=tx_fifo.rd_addr[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.param LUT_INIT 0111110101000001 +.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111110100000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr[8] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.param LUT_INIT 0000000000001011 +.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001111101 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.param LUT_INIT 0000100101101111 +.gate SB_LUT4 I0=tx_fifo.rd_addr[3] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000001000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.param LUT_INIT 0000000000001110 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100110010000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[6] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=tx_fifo.empty_o_SB_LUT4_I0_O[3] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001100 +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=tx_fifo.rd_addr[8] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100010101011100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 .gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" @@ -3175,7 +3151,7 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -3187,6 +3163,26 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.full_o_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -3217,15 +3213,13 @@ .param LUT_INIT 0110100110010110 .gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[5] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[7] +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[6] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 @@ -3280,24 +3274,12 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111101000101 .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" @@ -3354,12 +3336,30 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111101000101 .gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[8] +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[8] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[7] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" @@ -3420,7 +3420,7 @@ .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O @@ -3432,6 +3432,14 @@ .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -3521,14 +3529,14 @@ .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 @@ -3559,11 +3567,11 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1100111101000101 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000001101001 @@ -3593,14 +3601,6 @@ .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" @@ -3746,15 +3746,17 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000011110000 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] 1 1 -.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] 1 1 -.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0] +.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] +.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +1 1 +.names io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] 1 1 .names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] 1 1 @@ -3762,155 +3764,11 @@ 1 1 .names tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] 1 1 -.names i_config[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0] -1 1 -.names tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] -1 1 -.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[0] -1 1 -.names smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[3] -1 1 -.names rx_fifo.rd_addr[7] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -1 1 -.names rx_fifo.rd_addr[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -1 1 -.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -1 1 .names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0] 1 1 .names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0] -1 1 -.names $true w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -1 1 -.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -1 1 -.names io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -1 1 -.names io_ctrl_ins.pmod_dir_state[0] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[3] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[2] -1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -1 1 -.names io_ctrl_ins.mixer_en_state io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -1 1 -.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -1 1 -.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -1 1 -.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[3] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -1 1 -.names tx_fifo.rd_addr[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[1] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] -1 1 -.names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0] -1 1 -.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[1] -1 1 -.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] -1 1 -.names tx_fifo.rd_addr[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[1] -1 1 -.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0] -1 1 -.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[1] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[0] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[1] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[0] -1 1 -.names io_ctrl_ins.pmod_dir_state[4] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] 1 1 .names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0] 1 1 @@ -3918,129 +3776,81 @@ 1 1 .names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3] 1 1 -.names spi_if_ins.o_ioc[1] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0] +.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0] 1 1 -.names spi_if_ins.o_ioc[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[3] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[0] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0] +.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[0] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I1_I3[1] +.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[2] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] 1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[0] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_6_D[1] +.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] 1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0] +.names tx_fifo.rd_addr[6] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] 1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[0] +.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] 1 1 -.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[0] -1 1 -.names $true rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[2] -1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] -1 1 -.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] -1 1 -.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] -1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0] -1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1] -1 1 -.names rx_fifo.wr_addr[2] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] -1 1 -.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -1 1 -.names o_led1 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] -1 1 -.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] -1 1 -.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] -1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] 1 1 .names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D[1] +.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] 1 1 -.names tx_fifo.rd_addr_gray[9] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.names tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] 1 1 -.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[1] 1 1 .names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] 1 1 -.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[2] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0] +.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +1 1 +.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[3] 1 1 .names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] 1 1 .names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] 1 1 -.names i_rst_b io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[1] +.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[1] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] 1 1 .names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[0] 1 1 @@ -4048,21 +3858,19 @@ 1 1 .names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] 1 1 -.names lvds_rx_24_inst.o_fifo_data[21] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] 1 1 -.names tx_fifo.rd_addr[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[0] +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] 1 1 -.names tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[1] +.names i_config[1] o_led1_SB_LUT4_I1_I3[0] 1 1 -.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I3[1] 1 1 -.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.names o_led1_SB_LUT4_I1_I2[1] o_led1_SB_LUT4_I1_I3[2] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] 1 1 .names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 @@ -4070,87 +3878,219 @@ 1 1 .names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] 1 1 -.names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] o_led1_SB_LUT4_I1_I2[0] 1 1 -.names io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0] +1 1 +.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1] 1 1 .names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 .names spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] 1 1 +.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] o_led1_SB_LUT4_I1_O[0] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] o_led1_SB_LUT4_I1_O[1] +1 1 +.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +1 1 .names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.names spi_if_ins.o_ioc[1] o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[1] +.names spi_if_ins.o_ioc[0] o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[2] +.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[0] +.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] 1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[1] +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[2] +.names io_ctrl_ins.lna_tx_shutdown_state io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[2] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[2] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[1] +.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.names o_led1_SB_LUT4_I1_I3[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] 1 1 -.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_D[1] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[0] +1 1 +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +1 1 +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[3] +1 1 +.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I1_I3[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[2] 1 1 .names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +1 1 +.names o_led1_SB_LUT4_I1_I2[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] 1 1 .names io_pmod[6] lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[0] 1 1 +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] +1 1 +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[1] +1 1 +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[2] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] +1 1 +.names i_rst_b io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +1 1 +.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +1 1 +.names lvds_rx_24_inst.o_fifo_data[29] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +1 1 +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0] +1 1 +.names $true w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2] +1 1 +.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +1 1 +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +1 1 +.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[0] +1 1 +.names sys_ctrl_ins.i_cs sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] +1 1 +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +1 1 +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[3] w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led0_SB_LUT4_I1_O[0] +1 1 +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] o_led0_SB_LUT4_I1_O[1] +1 1 +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[1] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[2] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +1 1 +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[1] +1 1 +.names rx_fifo.wr_addr[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] +1 1 +.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +1 1 +.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[1] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[2] +1 1 +.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[0] +1 1 +.names o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +1 1 +.names io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[3] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +1 1 +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0] +1 1 +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] +1 1 +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[1] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +1 1 .names tx_fifo.wr_addr[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] 1 1 .names tx_fifo.rd_addr_gray_wr_r[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[1] 1 1 -.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[1] 1 1 -.names rx_fifo.rd_addr[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[2] -1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[1] -1 1 -.names rx_fifo.rd_addr[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[0] -1 1 -.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[1] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[2] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.names rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] 1 1 .names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] 1 1 @@ -4158,89 +4098,117 @@ 1 1 .names tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] 1 1 +.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +1 1 +.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +1 1 .names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 +.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] +1 1 +.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +1 1 +.names rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[3] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +1 1 .names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names spi_if_ins.o_fetch_cmd io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[0] +.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] 1 1 -.names sys_ctrl_ins.i_cs io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[1] +.names rx_fifo.rd_addr[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.names rx_fifo.rd_addr[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] 1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[1] +.names io_ctrl_ins.tr_vc_1_b_state i_config_SB_LUT4_I0_2_O[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] 1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[3] w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.names tx_fifo.rd_addr[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[1] 1 1 -.names io_ctrl_ins.pmod_dir_state[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] +.names rx_fifo.rd_addr[5] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] +.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] +.names $true rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] +.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_D[1] +.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.names rx_fifo.rd_addr[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] 1 1 .names io_ctrl_ins.rx_h_state i_button_SB_LUT4_I0_O[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] i_button_SB_LUT4_I0_O[1] +.names i_config_SB_LUT4_I0_2_O[1] i_button_SB_LUT4_I0_O[1] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] 1 1 -.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] 1 1 -.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] +.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[2] 1 1 -.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] +1 1 +.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[0] +1 1 +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] 1 1 .names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] 1 1 .names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I0_O[0] +.names rx_fifo.empty_o rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[0] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.empty_o_SB_LUT4_I0_O[1] +.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[2] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] 1 1 .names tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] 1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1] +1 1 .names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1] +.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_6_D[1] 1 1 .names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] 1 1 -.names rx_fifo.rd_addr[5] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[0] +.names rx_fifo.rd_addr[7] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[1] +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.names rx_fifo.rd_addr[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[2] 1 1 .names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1] 1 1 @@ -4306,9 +4274,7 @@ 1 1 .names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] -1 1 -.names o_led1 channel +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] 1 1 .names spi_if_ins.spi.o_spi_miso int_miso 1 1 @@ -4356,6 +4322,14 @@ 1 1 .names r_counter io_ctrl_ins.i_sys_clk 1 1 +.names o_led0 io_ctrl_ins.led0_state +1 1 +.names o_led1 io_ctrl_ins.led1_state +1 1 +.names o_led0 io_ctrl_ins.o_led0 +1 1 +.names o_led1 io_ctrl_ins.o_led1 +1 1 .names $true io_ctrl_ins.o_mixer_en 1 1 .names $false io_ctrl_ins.o_mixer_fm @@ -4504,8 +4478,6 @@ 1 1 .names lvds_clock o_iq_tx_clk_p 1 1 -.names smi_ctrl_ins.r_dir o_led0 -1 1 .names $undef o_mixer_en 1 1 .names $undef o_mixer_fm @@ -4656,8 +4628,6 @@ 1 1 .names $false smi_ctrl_ins.int_cnt_rx[2] 1 1 -.names o_led1 smi_ctrl_ins.o_channel -1 1 .names $false smi_ctrl_ins.o_data_out[3] 1 1 .names $false smi_ctrl_ins.o_data_out[4] @@ -4736,8 +4706,6 @@ 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[31] 1 1 -.names o_led1 smi_ctrl_ins.r_channel -1 1 .names $false smi_ctrl_ins.r_fifo_pushed_data[0] 1 1 .names $false smi_ctrl_ins.r_fifo_pushed_data[1] @@ -5106,6 +5074,8 @@ 1 1 .names lvds_rx_09_inst.o_fifo_data[30] w_rx_09_fifo_data[30] 1 1 +.names lvds_rx_09_inst.o_fifo_data[31] w_rx_09_fifo_data[31] +1 1 .names lvds_clock w_rx_09_fifo_write_clk 1 1 .names lvds_rx_24_inst.o_fifo_data[0] w_rx_24_fifo_data[0] diff --git a/firmware/top.json b/firmware/top.json index 2cc1fcb..97da5f3 100644 --- a/firmware/top.json +++ b/firmware/top.json @@ -21,7 +21,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -404,7 +404,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8334": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8333": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -428,7 +428,7 @@ "Y": [ 78 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8335": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8334": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -452,7 +452,7 @@ "Y": [ 79 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8336": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8335": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -476,7 +476,7 @@ "Y": [ 80 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8337": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8336": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -819,28 +819,28 @@ } }, "netnames": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8334_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8333_Y": { "hide_name": 1, "bits": [ 78 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661.33-1661.44" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8335_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8334_Y": { "hide_name": 1, "bits": [ 79 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663.34-1663.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8336_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8335_Y": { "hide_name": 1, "bits": [ 80 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669.34-1669.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8337_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8336_Y": { "hide_name": 1, "bits": [ 81 ], "attributes": { @@ -952,7 +952,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1022,7 +1022,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1092,7 +1092,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1162,7 +1162,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1232,7 +1232,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1302,7 +1302,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1372,7 +1372,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1442,7 +1442,7 @@ } }, "cells": { - "$specify$8459": { + "$specify$8458": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -11427,6 +11427,81 @@ "O": [ 57 ] } }, + "i_config_SB_LUT4_I0_2": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0001001101011111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 19 ], + "I1": [ 58 ], + "I2": [ 59 ], + "I3": [ 51 ], + "O": [ 60 ] + } + }, + "i_config_SB_LUT4_I0_2_O_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 61 ], + "I3": [ 62 ], + "O": [ 63 ] + } + }, + "i_config_SB_LUT4_I0_2_O_SB_LUT4_O_1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000110000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 64 ], + "I2": [ 59 ], + "I3": [ 52 ], + "O": [ 65 ] + } + }, "i_rst_b_SB_LUT4_I1": { "hide_name": 0, "type": "SB_LUT4", @@ -11447,9 +11522,9 @@ "connections": { "I0": [ "0" ], "I1": [ 3 ], - "I2": [ 58 ], - "I3": [ 59 ], - "O": [ 60 ] + "I2": [ 66 ], + "I3": [ 67 ], + "O": [ 68 ] } }, "i_rst_b_SB_LUT4_I3": { @@ -11474,7 +11549,7 @@ "I1": [ "0" ], "I2": [ "0" ], "I3": [ 3 ], - "O": [ 61 ] + "O": [ 69 ] } }, "i_ss_SB_LUT4_I3": { @@ -11499,7 +11574,7 @@ "I1": [ "0" ], "I2": [ "0" ], "I3": [ 48 ], - "O": [ 62 ] + "O": [ 70 ] } }, "io_ctrl_ins.i_cs_SB_DFFESR_Q": { @@ -11519,11 +11594,11 @@ "R": "input" }, "connections": { - "C": [ 63 ], - "D": [ 64 ], - "E": [ 65 ], - "Q": [ 66 ], - "R": [ 67 ] + "C": [ 71 ], + "D": [ 72 ], + "E": [ 73 ], + "Q": [ 74 ], + "R": [ 75 ] } }, "io_ctrl_ins.i_cs_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -11546,9 +11621,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 68 ], - "I3": [ 69 ], - "O": [ 64 ] + "I2": [ 76 ], + "I3": [ 77 ], + "O": [ 72 ] } }, "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q": { @@ -11567,9 +11642,9 @@ "Q": "output" }, "connections": { - "C": [ 63 ], - "D": [ 70 ], - "E": [ 71 ], + "C": [ 71 ], + "D": [ 78 ], + "E": [ 79 ], "Q": [ 9 ] } }, @@ -11592,35 +11667,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 72 ], - "I2": [ 73 ], - "I3": [ 74 ], - "O": [ 70 ] - } - }, - "io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I0": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "1011100000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 9 ], - "I1": [ 75 ], - "I2": [ 24 ], - "I3": [ 76 ], - "O": [ 77 ] + "I1": [ 80 ], + "I2": [ 81 ], + "I3": [ 82 ], + "O": [ 78 ] } }, "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q": { @@ -11639,9 +11689,9 @@ "Q": "output" }, "connections": { - "C": [ 63 ], - "D": [ 78 ], - "E": [ 71 ], + "C": [ 71 ], + "D": [ 83 ], + "E": [ 79 ], "Q": [ 10 ] } }, @@ -11663,308 +11713,13 @@ "O": "output" }, "connections": { - "I0": [ 79 ], - "I1": [ 80 ], - "I2": [ 73 ], - "I3": [ 74 ], - "O": [ 78 ] - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "1011100000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 10 ], - "I1": [ 75 ], - "I2": [ 25 ], - "I3": [ 76 ], - "O": [ 81 ] - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000000000111111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ 82 ], - "I2": [ 51 ], - "I3": [ 81 ], + "I0": [ 84 ], + "I1": [ 64 ], + "I2": [ 81 ], + "I3": [ 82 ], "O": [ 83 ] } }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q": { - "hide_name": 0, - "type": "SB_DFFER", - "parameters": { - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" - }, - "port_directions": { - "C": "input", - "D": "input", - "E": "input", - "Q": "output", - "R": "input" - }, - "connections": { - "C": [ 63 ], - "D": [ 84 ], - "E": [ 85 ], - "Q": [ 86 ], - "R": [ 61 ] - } - }, - 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440 ] - } - }, - "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3_SB_LUT4_O": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0010100000111100" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 423 ], - "I1": [ 477 ], - "I2": [ 496 ], - "I3": [ 445 ], - "O": [ 495 ] - } - }, - "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "1111111100001111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" 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"port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 474 ], + "I2": [ 476 ], + "I3": [ 470 ], + "O": [ 409 ] + } + }, "rx_fifo.mem_i.0.0_WDATA_1_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", @@ -20357,10 +19894,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 211 ], - "I2": [ 288 ], - "I3": [ 32 ], - "O": [ 531 ] + "I1": [ 192 ], + "I2": [ 270 ], + "I3": [ 476 ], + "O": [ 512 ] } }, "rx_fifo.mem_i.0.0_WDATA_2_SB_LUT4_O": { @@ -20382,17 +19919,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 213 ], - "I2": [ 290 ], - "I3": [ 32 ], - "O": [ 530 ] + "I1": [ 194 ], + "I2": [ 272 ], + "I3": [ 476 ], + "O": [ 511 ] } }, "rx_fifo.mem_i.0.0_WDATA_3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20407,10 +19944,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 209 ], - "I2": [ 286 ], - "I3": [ 32 ], - "O": [ 529 ] + "I1": [ 268 ], + "I2": [ 190 ], + "I3": [ 476 ], + "O": [ 510 ] } }, "rx_fifo.mem_i.0.0_WDATA_SB_LUT4_O": { @@ -20432,10 +19969,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 292 ], - "I2": [ 215 ], - "I3": [ 32 ], - "O": [ 532 ] + "I1": [ 274 ], + "I2": [ 196 ], + "I3": [ 476 ], + "O": [ 513 ] } }, "rx_fifo.mem_i.0.1": { @@ -20480,15 +20017,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, "0" ], - "RCLK": [ 63 ], - "RCLKE": [ 508 ], - "RDATA": [ 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548 ], + "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], + "RCLK": [ 71 ], + "RCLKE": [ 488 ], + "RDATA": [ 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530 ], "RE": [ "1" ], - "WADDR": [ 459, 462, 471, 469, 465, 525, 526, 527, 460, 528, "0" ], + "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], "WCLK": [ 13 ], - "WCLKE": [ 424 ], - "WDATA": [ "0", 549, "0", "0", "0", 550, "0", "0", "0", 551, "0", "0", "0", 552, "0", "0" ], + "WCLKE": [ 409 ], + "WDATA": [ "0", 531, "0", "0", "0", 532, "0", "0", "0", 533, "0", "0", "0", 534, "0", "0" ], "WE": [ "1" ] } }, @@ -20511,17 +20048,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 219 ], - "I2": [ 296 ], - "I3": [ 32 ], - "O": [ 551 ] + "I1": [ 200 ], + "I2": [ 278 ], + "I3": [ 476 ], + "O": [ 533 ] } }, "rx_fifo.mem_i.0.1_WDATA_2_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20536,10 +20073,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 301 ], - "I2": [ 224 ], - "I3": [ 32 ], - "O": [ 550 ] + "I1": [ 205 ], + "I2": [ 283 ], + "I3": [ 476 ], + "O": [ 532 ] } }, "rx_fifo.mem_i.0.1_WDATA_3_SB_LUT4_O": { @@ -20561,17 +20098,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 217 ], - "I2": [ 294 ], - "I3": [ 32 ], - "O": [ 549 ] + "I1": [ 198 ], + "I2": [ 276 ], + "I3": [ 476 ], + "O": [ 531 ] } }, "rx_fifo.mem_i.0.1_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20586,10 +20123,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 303 ], - "I2": [ 226 ], - "I3": [ 32 ], - "O": [ 552 ] + "I1": [ 207 ], + "I2": [ 285 ], + "I3": [ 476 ], + "O": [ 534 ] } }, "rx_fifo.mem_i.0.2": { @@ -20634,15 +20171,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, "0" ], - "RCLK": [ 63 ], - "RCLKE": [ 508 ], - "RDATA": [ 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568 ], + "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], + "RCLK": [ 71 ], + "RCLKE": [ 488 ], + "RDATA": [ 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550 ], "RE": [ "1" ], - "WADDR": [ 459, 462, 471, 469, 465, 525, 526, 527, 460, 528, "0" ], + "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], "WCLK": [ 13 ], - "WCLKE": [ 424 ], - "WDATA": [ "0", 569, "0", "0", "0", 570, "0", "0", "0", 571, "0", "0", "0", 572, "0", "0" ], + "WCLKE": [ 409 ], + "WDATA": [ "0", 551, "0", "0", "0", 552, "0", "0", "0", 553, "0", "0", "0", 554, "0", "0" ], "WE": [ "1" ] } }, @@ -20665,17 +20202,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 307 ], - "I2": [ 230 ], - "I3": [ 32 ], - "O": [ 571 ] + "I1": [ 289 ], + "I2": [ 211 ], + "I3": [ 476 ], + "O": [ 553 ] } }, "rx_fifo.mem_i.0.2_WDATA_2_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20690,10 +20227,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 309 ], - "I2": [ 232 ], - "I3": [ 32 ], - "O": [ 570 ] + "I1": [ 213 ], + "I2": [ 291 ], + "I3": [ 476 ], + "O": [ 552 ] } }, "rx_fifo.mem_i.0.2_WDATA_3_SB_LUT4_O": { @@ -20715,17 +20252,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 228 ], - "I2": [ 305 ], - "I3": [ 32 ], - "O": [ 569 ] + "I1": [ 209 ], + "I2": [ 287 ], + "I3": [ 476 ], + "O": [ 551 ] } }, "rx_fifo.mem_i.0.2_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20740,10 +20277,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 311 ], - "I2": [ 234 ], - "I3": [ 32 ], - "O": [ 572 ] + "I1": [ 215 ], + "I2": [ 293 ], + "I3": [ 476 ], + "O": [ 554 ] } }, "rx_fifo.mem_i.0.3": { @@ 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"type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20819,10 +20356,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 315 ], - "I2": [ 238 ], - "I3": [ 32 ], - "O": [ 591 ] + "I1": [ 219 ], + "I2": [ 297 ], + "I3": [ 476 ], + "O": [ 573 ] } }, "rx_fifo.mem_i.0.3_WDATA_2_SB_LUT4_O": { @@ -20844,10 +20381,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 240 ], - "I2": [ 317 ], - "I3": [ 32 ], - "O": [ 590 ] + "I1": [ 221 ], + "I2": [ 299 ], + "I3": [ 476 ], + "O": [ 572 ] } }, "rx_fifo.mem_i.0.3_WDATA_3_SB_LUT4_O": { @@ -20869,17 +20406,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 313 ], - "I2": [ 236 ], - "I3": [ 32 ], - "O": [ 589 ] + "I1": [ 295 ], + "I2": [ 217 ], + "I3": [ 476 ], + "O": [ 571 ] } }, "rx_fifo.mem_i.0.3_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20894,10 +20431,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 319 ], - "I2": [ 242 ], - "I3": [ 32 ], - "O": [ 592 ] + "I1": [ 223 ], + "I2": [ 301 ], + "I3": [ 476 ], + "O": [ 574 ] } }, "rx_fifo.mem_q.0.0": { @@ -20942,15 +20479,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, "0" ], - "RCLK": [ 63 ], - "RCLKE": [ 508 ], - "RDATA": [ 593, 594, 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608 ], + "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], + "RCLK": [ 71 ], + "RCLKE": [ 488 ], + "RDATA": [ 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590 ], "RE": [ "1" ], - "WADDR": [ 459, 462, 471, 469, 465, 525, 526, 527, 460, 528, "0" ], + "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 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@@ -35837,8 +35837,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 186 ], - "O": [ 195 ] + "I3": [ 165 ], + "O": [ 176 ] } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O": { @@ -35863,7 +35863,7 @@ "I1": [ 1174 ], "I2": [ 1175 ], "I3": [ 1176 ], - "O": [ 492 ] + "O": [ 472 ] } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q": { @@ -35887,7 +35887,7 @@ "D": [ 1177 ], "E": [ 1178 ], "Q": [ 1176 ], - "R": [ 61 ] + "R": [ 69 ] } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1": { @@ -35911,7 +35911,7 @@ "D": [ 1179 ], "E": [ 1178 ], "Q": [ 1175 ], - "R": [ 61 ] + "R": [ 69 ] } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O": { @@ -35932,7 +35932,7 @@ "O": "output" }, "connections": { - "I0": [ 186 ], + "I0": [ 165 ], "I1": [ 1180 ], "I2": [ "1" ], "I3": [ 1181 ], @@ -36010,7 +36010,7 @@ "D": [ 1182 ], "E": [ 1178 ], "Q": [ 1174 ], - "R": [ 61 ] + "R": [ 69 ] } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O": { @@ -36033,7 +36033,7 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 186 ], + "I2": [ 165 ], "I3": [ 1183 ], "O": [ 1182 ] } @@ -36059,7 +36059,7 @@ "I0": [ 1174 ], "I1": [ 1175 ], "I2": [ 1176 ], - "I3": [ 185 ], + "I3": [ 164 ], "O": [ 1183 ] } }, @@ -36081,7 +36081,7 @@ "O": "output" }, "connections": { - "I0": [ 186 ], + "I0": [ 165 ], "I1": [ 1176 ], "I2": [ "1" ], "I3": [ 1184 ], @@ -36127,10 +36127,10 @@ "O": "output" }, "connections": { - "I0": [ 185 ], - "I1": [ 186 ], + "I0": [ 164 ], + "I1": [ 165 ], "I2": [ 1171 ], - "I3": [ 492 ], + "I3": [ 472 ], "O": [ 1178 ] } }, @@ -36152,10 +36152,10 @@ "O": "output" }, "connections": { - "I0": [ 181 ], - "I1": [ 180 ], - "I2": [ 262 ], - "I3": [ 264 ], + "I0": [ 160 ], + "I1": [ 159 ], + "I2": [ 243 ], + "I3": [ 245 ], "O": [ 1185 ] } }, @@ -36181,18 +36181,11 @@ "I1": [ "0" ], "I2": [ 3 ], "I3": [ 1185 ], - "O": [ 271 ] + "O": [ 253 ] } } }, "netnames": { - "channel": { - "hide_name": 0, - "bits": [ 32 ], - "attributes": { - "src": "top.v:450.8-450.15" - } - }, "i_button": { "hide_name": 0, "bits": [ 22 ], @@ -36202,7 +36195,7 @@ }, "i_button_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 4, 102, 53 ], + "bits": [ 4, 63, 53 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36215,6 +36208,14 @@ "src": "top.v:41.17-41.25" } }, + "i_config_SB_LUT4_I0_2_O": { + "hide_name": 0, + "bits": [ 7, 63, 60, 65 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "i_glob_clock": { "hide_name": 0, "bits": [ 2 ], @@ -36259,7 +36260,7 @@ }, "i_rst_b_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 61 ], + "bits": [ 69 ], "attributes": { } }, @@ -36307,7 +36308,7 @@ }, "int_miso": { "hide_name": 0, - "bits": [ 366 ], + "bits": [ 346 ], "attributes": { "src": "top.v:149.8-149.16" } @@ -36330,7 +36331,7 @@ }, "io_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 66 ], + "bits": [ 74 ], "attributes": { "hdlname": "io_ctrl_ins i_cs", "src": "io_ctrl.v:9.22-9.26" @@ -36338,13 +36339,13 @@ }, "io_ctrl_ins.i_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 64 ], + "bits": [ 72 ], "attributes": { } }, "io_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], + "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], "attributes": { "hdlname": "io_ctrl_ins i_data_in", "src": "io_ctrl.v:7.22-7.31" @@ -36352,7 +36353,7 @@ }, "io_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 95 ], + "bits": [ 118 ], "attributes": { "hdlname": "io_ctrl_ins i_fetch_cmd", "src": "io_ctrl.v:10.22-10.33" @@ -36360,7 +36361,7 @@ }, "io_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 75, 97, 173, 172, 171 ], + "bits": [ 61, 106, 345, 344, 343 ], "attributes": { "hdlname": "io_ctrl_ins i_ioc", "src": "io_ctrl.v:6.22-6.27" @@ -36368,7 +36369,7 @@ }, "io_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 94 ], + "bits": [ 119 ], "attributes": { "hdlname": "io_ctrl_ins i_load_cmd", "src": "io_ctrl.v:11.22-11.32" @@ -36384,12 +36385,28 @@ }, "io_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "io_ctrl_ins i_sys_clk", "src": "io_ctrl.v:4.22-4.31" } }, + "io_ctrl_ins.led0_state": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "hdlname": "io_ctrl_ins led0_state", + "src": "io_ctrl.v:73.17-73.27" + } + }, + "io_ctrl_ins.led1_state": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "hdlname": "io_ctrl_ins led1_state", + "src": "io_ctrl.v:74.17-74.27" + } + }, "io_ctrl_ins.lna_rx_shutdown_state": { "hide_name": 0, "bits": [ 9 ], @@ -36400,7 +36417,7 @@ }, "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 70 ], + "bits": [ 78 ], "attributes": { } }, @@ -36414,61 +36431,13 @@ }, "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 78 ], + "bits": [ 83 ], "attributes": { } }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 82, 51, 81 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 86, 96, 83 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 85 ], - "attributes": { - "defaultvalue": "1", - "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q": { - "hide_name": 0, - "bits": [ 3, 90, 80, 73 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q": { - "hide_name": 0, - "bits": [ 88, 90 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 88, 93 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.mixer_en_state": { "hide_name": 0, - "bits": [ 100 ], + "bits": [ 86 ], "attributes": { "hdlname": "io_ctrl_ins mixer_en_state", "src": "io_ctrl.v:78.17-78.31" @@ -36476,45 +36445,13 @@ }, "io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 99 ], + "bits": [ 85 ], "attributes": { } }, - "io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2": { - "hide_name": 0, - "bits": [ 100, 102, 103, 104 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3": { - "hide_name": 0, - "bits": [ 90, 96, 109 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1": { - "hide_name": 0, - "bits": [ 106, 107, 108, 51 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 110 ], - "attributes": { - "defaultvalue": "1", - "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, "io_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 126, 113, 121, 116, 128, 135, 133, 131 ], + "bits": [ 122, 91, 100, 94, 125, 132, 130, 128 ], "attributes": { "hdlname": "io_ctrl_ins o_data_out", "src": "io_ctrl.v:8.22-8.32" @@ -36522,25 +36459,33 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 115 ], + "bits": [ 93 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 98 ], "attributes": { } }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1": { + "hide_name": 0, + "bits": [ 10, 102, 63, 103 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E": { "hide_name": 0, - "bits": [ 120 ], + "bits": [ 99 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R": { "hide_name": 0, - "bits": [ 108, 122 ], + "bits": [ 59, 101 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36548,65 +36493,103 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 111 ], + "bits": [ 89 ], "attributes": { } }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2": { + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0": { "hide_name": 0, - "bits": [ 88, 96, 77, 123 ], + "bits": [ 108, 114 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1": { + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 124, 125, 108, 51 ], + "bits": [ 112 ], + "attributes": { + "defaultvalue": "1", + "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q": { + "hide_name": 0, + "bits": [ 104, 105, 51, 95 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q": { + "hide_name": 0, + "bits": [ 3, 114, 64, 81 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O": { + "hide_name": 0, + "bits": [ 146, 64, 81, 82 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3": { + "hide_name": 0, + "bits": [ 108, 120 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + } + }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 114 ], + "bits": [ 92 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 105 ], + "bits": [ 121 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 129 ], + "bits": [ 126 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D": { "hide_name": 0, - "bits": [ 132 ], + "bits": [ 129 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D": { "hide_name": 0, - "bits": [ 134 ], + "bits": [ 131 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E": { "hide_name": 0, - "bits": [ 130 ], + "bits": [ 127 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 66, 136, 98, 76 ], + "bits": [ 74, 133, 107, 62 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36614,7 +36597,7 @@ }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 97, 75, 112 ], + "bits": [ 106, 61, 90 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36622,16 +36605,24 @@ }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 127 ], + "bits": [ 124 ], "attributes": { } }, - "io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3": { + "io_ctrl_ins.o_led0": { "hide_name": 0, - "bits": [ 19, 108, 137 ], + "bits": [ 31 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + "hdlname": "io_ctrl_ins o_led0", + "src": "io_ctrl.v:16.22-16.28" + } + }, + "io_ctrl_ins.o_led1": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "hdlname": "io_ctrl_ins o_led1", + "src": "io_ctrl.v:17.22-17.28" } }, "io_ctrl_ins.o_mixer_en": { @@ -36716,7 +36707,7 @@ }, "io_ctrl_ins.pmod_dir_state": { "hide_name": 0, - "bits": [ 106, 124, 82, 144, 143, 56, 54, 50 ], + "bits": [ 140, 139, 104, 138, 58, 56, 54, 50 ], "attributes": { "hdlname": "io_ctrl_ins pmod_dir_state", "src": "io_ctrl.v:75.17-75.31" @@ -36732,7 +36723,7 @@ }, "io_ctrl_ins.rf_pin_state": { "hide_name": 0, - "bits": [ 101, 72, 79, 150, 149, 148, 147, 146 ], + "bits": [ 87, 80, 84, 146, 145, 144, 143, 142 ], "attributes": { "hdlname": "io_ctrl_ins rf_pin_state", "src": "io_ctrl.v:77.17-77.29" @@ -36748,13 +36739,13 @@ }, "io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 151 ], + "bits": [ 147 ], "attributes": { } }, "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3": { "hide_name": 0, - "bits": [ 5, 102, 55 ], + "bits": [ 5, 63, 55 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36770,32 +36761,18 @@ }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 153 ], + "bits": [ 149 ], "attributes": { } }, - "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 150, 80, 73, 74 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 146, 74, 152 ], + "bits": [ 142, 82, 148 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 71 ], - "attributes": { - } - }, "io_ctrl_ins.tr_vc_1_b_state": { "hide_name": 0, "bits": [ 7 ], @@ -36806,98 +36783,10 @@ }, "io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 154 ], + "bits": [ 150 ], "attributes": { } }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 80, 108, 52, 138 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2": { - "hide_name": 0, - "bits": [ 97, 156 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 95, 158, 157 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 159 ], - "attributes": { - "defaultvalue": "1", - "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O": { - "hide_name": 0, - "bits": [ 75, 76 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 7, 143, 51, 102 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 161, 160 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2": { - "hide_name": 0, - "bits": [ 165, 160 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2": { - "hide_name": 0, - "bits": [ 167, 160 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2": { - "hide_name": 0, - "bits": [ 169, 160 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2": { - "hide_name": 0, - "bits": [ 163, 160 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.tr_vc_1_state": { "hide_name": 0, "bits": [ 6 ], @@ -36908,13 +36797,13 @@ }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 174 ], + "bits": [ 152 ], "attributes": { } }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 149, 73, 155, 74 ], + "bits": [ 145, 81, 151, 82 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36922,7 +36811,7 @@ }, "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3": { "hide_name": 0, - "bits": [ 6, 102, 57 ], + "bits": [ 6, 63, 57 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36938,13 +36827,13 @@ }, "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 175 ], + "bits": [ 153 ], "attributes": { } }, "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 73, 96, 117, 118 ], + "bits": [ 81, 95, 96, 97 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36959,13 +36848,13 @@ }, "io_pmod_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 176 ], + "bits": [ 154 ], "attributes": { } }, "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 75, 177, 76 ], + "bits": [ 61, 155, 62 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36973,16 +36862,24 @@ }, "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O": { "hide_name": 0, - "bits": [ 145 ], + "bits": [ 141 ], "attributes": { } }, "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 140 ], + "bits": [ 135 ], "attributes": { } }, + "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 61, 62 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_smi_data": { "hide_name": 0, "bits": [ 37, 38, 39, 40, 41, 42, 43, 44 ], @@ -37014,7 +36911,7 @@ }, "lvds_rx_09_inst.i_ddr_data": { "hide_name": 0, - "bits": [ 179, 178 ], + "bits": [ 158, 157 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_data", "src": "lvds_rx.v:4.17-4.27" @@ -37022,7 +36919,7 @@ }, "lvds_rx_09_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 418 ], + "bits": [ 403 ], "attributes": { "hdlname": "lvds_rx_09_inst i_fifo_full", "src": "lvds_rx.v:6.23-6.34" @@ -37038,7 +36935,7 @@ }, "lvds_rx_09_inst.i_sync_input": { "hide_name": 0, - "bits": [ 182 ], + "bits": [ 161 ], "attributes": { "hdlname": "lvds_rx_09_inst i_sync_input", "src": "lvds_rx.v:10.23-10.35" @@ -37046,7 +36943,7 @@ }, "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 183 ], + "bits": [ 162 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37054,7 +36951,7 @@ }, "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 179, 184, 187 ], + "bits": [ 158, 163, 166 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37062,7 +36959,7 @@ }, "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 30, 189, 190 ], + "bits": [ 30, 168, 169 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37070,7 +36967,7 @@ }, "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 191 ], + "bits": [ 170 ], "attributes": { "defaultvalue": "1", "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37078,7 +36975,7 @@ }, "lvds_rx_09_inst.o_fifo_data": { "hide_name": 0, - "bits": [ 255, 220, 194, 197, 222, 244, 246, 248, 250, 252, 200, 203, 199, 202, 205, 207, 209, 211, 213, 215, 217, 219, 224, 226, 228, 230, 232, 234, 236, 238, 240, 242 ], + "bits": [ 236, 201, 175, 178, 203, 225, 227, 229, 231, 233, 181, 184, 180, 183, 186, 188, 190, 192, 194, 196, 198, 200, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_data", "src": "lvds_rx.v:9.23-9.34" @@ -37086,193 +36983,193 @@ }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D": { "hide_name": 0, - "bits": [ 198 ], + "bits": [ 179 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D": { "hide_name": 0, - "bits": [ 201 ], + "bits": [ 182 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D": { "hide_name": 0, - "bits": [ 204 ], + "bits": [ 185 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D": { "hide_name": 0, - "bits": [ 206 ], + "bits": [ 187 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D": { "hide_name": 0, - "bits": [ 208 ], + "bits": [ 189 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D": { "hide_name": 0, - "bits": [ 210 ], + "bits": [ 191 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D": { "hide_name": 0, - "bits": [ 212 ], + "bits": [ 193 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D": { "hide_name": 0, - "bits": [ 214 ], + "bits": [ 195 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D": { "hide_name": 0, - "bits": [ 216 ], + "bits": [ 197 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D": { "hide_name": 0, - "bits": [ 218 ], + "bits": [ 199 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 196 ], + "bits": [ 177 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D": { "hide_name": 0, - "bits": [ 223 ], + "bits": [ 204 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D": { "hide_name": 0, - "bits": [ 225 ], + "bits": [ 206 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D": { "hide_name": 0, - "bits": [ 227 ], + "bits": [ 208 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D": { "hide_name": 0, - "bits": [ 229 ], + "bits": [ 210 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D": { "hide_name": 0, - "bits": [ 231 ], + "bits": [ 212 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D": { "hide_name": 0, - "bits": [ 233 ], + "bits": [ 214 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D": { "hide_name": 0, - "bits": [ 235 ], + "bits": [ 216 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D": { "hide_name": 0, - "bits": [ 237 ], + "bits": [ 218 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D": { "hide_name": 0, - "bits": [ 239 ], + "bits": [ 220 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D": { "hide_name": 0, - "bits": [ 241 ], + "bits": [ 222 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 221 ], + "bits": [ 202 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 243 ], + "bits": [ 224 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 245 ], + "bits": [ 226 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 247 ], + "bits": [ 228 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 249 ], + "bits": [ 230 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 251 ], + "bits": [ 232 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 253 ], + "bits": [ 234 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 254 ], + "bits": [ 235 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 192 ], + "bits": [ 173 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 195 ], + "bits": [ 176 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 188 ], + "bits": [ 167 ], "attributes": { } }, @@ -37294,7 +37191,7 @@ }, "lvds_rx_24_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 418 ], + "bits": [ 403 ], "attributes": { "hdlname": "lvds_rx_24_inst i_fifo_full", "src": "lvds_rx.v:6.23-6.34" @@ -37310,7 +37207,7 @@ }, "lvds_rx_24_inst.i_sync_input": { "hide_name": 0, - "bits": [ 256 ], + "bits": [ 237 ], "attributes": { "hdlname": "lvds_rx_24_inst i_sync_input", "src": "lvds_rx.v:10.23-10.35" @@ -37318,7 +37215,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 257, 259 ], + "bits": [ 238, 240 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37326,7 +37223,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 260 ], + "bits": [ 241 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37334,7 +37231,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q": { "hide_name": 0, - "bits": [ 296, 264 ], + "bits": [ 297, 245 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37342,7 +37239,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D": { "hide_name": 0, - "bits": [ 263, 261 ], + "bits": [ 244, 242 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "lvds_rx.v:0.0-0.0|lvds_rx.v:43.7-82.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22" @@ -37350,7 +37247,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q": { "hide_name": 0, - "bits": [ 262, 264, 266 ], + "bits": [ 243, 245, 247 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37358,7 +37255,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 181, 258, 262, 259 ], + "bits": [ 160, 239, 243, 240 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37366,7 +37263,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 29, 268, 269 ], + "bits": [ 29, 249, 250 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37374,7 +37271,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E": { "hide_name": 0, - "bits": [ 162 ], + "bits": [ 171 ], "attributes": { "defaultvalue": "1", "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37382,7 +37279,7 @@ }, "lvds_rx_24_inst.o_fifo_data": { "hide_name": 0, - "bits": [ 332, 297, 272, 274, 299, 321, 323, 325, 327, 329, 277, 280, 276, 279, 282, 284, 286, 288, 290, 292, 294, 296, 301, 303, 305, 307, 309, 311, 313, 315, 317, 319 ], + "bits": [ 314, 279, 254, 256, 281, 303, 305, 307, 309, 311, 259, 262, 258, 261, 264, 266, 268, 270, 272, 274, 276, 278, 283, 285, 287, 289, 291, 293, 295, 297, 299, 301 ], "attributes": { "hdlname": "lvds_rx_24_inst o_fifo_data", "src": "lvds_rx.v:9.23-9.34" @@ -37390,199 +37287,199 @@ }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D": { "hide_name": 0, - "bits": [ 275 ], + "bits": [ 257 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D": { "hide_name": 0, - "bits": [ 278 ], + "bits": [ 260 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D": { "hide_name": 0, - "bits": [ 281 ], + "bits": [ 263 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D": { "hide_name": 0, - "bits": [ 283 ], + "bits": [ 265 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D": { "hide_name": 0, - "bits": [ 285 ], + "bits": [ 267 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D": { "hide_name": 0, - "bits": [ 287 ], + "bits": [ 269 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D": { "hide_name": 0, - "bits": [ 289 ], + "bits": [ 271 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D": { "hide_name": 0, - "bits": [ 291 ], + "bits": [ 273 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D": { "hide_name": 0, - "bits": [ 293 ], + "bits": [ 275 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D": { "hide_name": 0, - "bits": [ 295 ], + "bits": [ 277 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 273 ], + "bits": [ 255 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D": { "hide_name": 0, - "bits": [ 300 ], + "bits": [ 282 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D": { "hide_name": 0, - "bits": [ 302 ], + "bits": [ 284 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D": { "hide_name": 0, - "bits": [ 304 ], + "bits": [ 286 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D": { "hide_name": 0, - "bits": [ 306 ], + "bits": [ 288 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D": { "hide_name": 0, - "bits": [ 308 ], + "bits": [ 290 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D": { "hide_name": 0, - "bits": [ 310 ], + "bits": [ 292 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D": { "hide_name": 0, - "bits": [ 312 ], + "bits": [ 294 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D": { "hide_name": 0, - "bits": [ 314 ], + "bits": [ 296 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D": { "hide_name": 0, - "bits": [ 316 ], + "bits": [ 298 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D": { "hide_name": 0, - "bits": [ 318 ], + "bits": [ 300 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 298 ], + "bits": [ 280 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 320 ], + "bits": [ 302 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 322 ], + "bits": [ 304 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 324 ], + "bits": [ 306 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 326 ], + "bits": [ 308 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 328 ], + "bits": [ 310 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 330 ], + "bits": [ 312 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 331 ], + "bits": [ 313 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 270 ], + "bits": [ 252 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 265 ], + "bits": [ 246 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 267 ], + "bits": [ 248 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 333 ], + "bits": [ 315 ], "attributes": { } }, @@ -37604,7 +37501,7 @@ }, "lvds_tx_inst.i_fifo_empty": { "hide_name": 0, - "bits": [ 336 ], + "bits": [ 318 ], "attributes": { "hdlname": "lvds_tx_inst i_fifo_empty", "src": "lvds_tx.v:6.23-6.35" @@ -37636,7 +37533,7 @@ }, "lvds_tx_inst.o_fifo_pull": { "hide_name": 0, - "bits": [ 335 ], + "bits": [ 317 ], "attributes": { "hdlname": "lvds_tx_inst o_fifo_pull", "src": "lvds_tx.v:8.21-8.32" @@ -37668,7 +37565,7 @@ }, "lvds_tx_inst.r_pulled": { "hide_name": 0, - "bits": [ 335 ], + "bits": [ 317 ], "attributes": { "hdlname": "lvds_tx_inst r_pulled", "src": "lvds_tx.v:32.9-32.17" @@ -37676,13 +37573,13 @@ }, "lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D": { "hide_name": 0, - "bits": [ 334 ], + "bits": [ 316 ], "attributes": { } }, "lvds_tx_inst.r_pulled_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 340, 339, 341 ], + "bits": [ 321, 322, 323 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37690,7 +37587,7 @@ }, "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 347, 351, 356, 342 ], + "bits": [ 329, 1028, 334, 324 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37698,7 +37595,7 @@ }, "lvds_tx_inst.r_pulled_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 363 ], + "bits": [ 341 ], "attributes": { } }, @@ -37745,6 +37642,14 @@ "src": "top.v:44.12-44.18" } }, + "o_led0_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 114, 95, 88, 123 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "o_led1": { "hide_name": 0, "bits": [ 32 ], @@ -37754,10 +37659,42 @@ }, "o_led1_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 364 ], + "bits": [ 342 ], "attributes": { "defaultvalue": "1", - "src": "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "o_led1_SB_LUT4_I1_I2": { + "hide_name": 0, + "bits": [ 64, 59, 52 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "o_led1_SB_LUT4_I1_I3": { + "hide_name": 0, + "bits": [ 19, 58, 59, 51 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 106, 61, 156, 107 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "o_led1_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 108, 95, 109, 110 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "o_miso": { @@ -37769,7 +37706,7 @@ }, "o_miso_$_TBUF__Y_E": { "hide_name": 0, - "bits": [ 62 ], + "bits": [ 70 ], "attributes": { } }, @@ -37852,33 +37789,33 @@ }, "r_counter": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "src": "top.v:95.14-95.23" } }, "r_counter_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 369 ], + "bits": [ 350 ], "attributes": { } }, "r_tx_data": { "hide_name": 0, - "bits": [ 404, 398, 394, 391, 387, 381, 374, 372 ], + "bits": [ 388, 381, 377, 373, 369, 363, 355, 353 ], "attributes": { "src": "top.v:100.14-100.23" } }, "r_tx_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 373 ], + "bits": [ 354 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 133, 375, 376, 377 ], + "bits": [ 130, 356, 357, 358 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37886,13 +37823,13 @@ }, "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 378 ], + "bits": [ 359 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 379, 160 ], + "bits": [ 361, 251 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37900,13 +37837,13 @@ }, "r_tx_data_SB_DFFE_Q_2_D": { "hide_name": 0, - "bits": [ 380 ], + "bits": [ 362 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 382, 376, 383 ], + "bits": [ 364, 357, 365 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37914,19 +37851,19 @@ }, "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 384 ], + "bits": [ 366 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_3_D": { "hide_name": 0, - "bits": [ 386 ], + "bits": [ 368 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 128, 388, 376, 377 ], + "bits": [ 125, 370, 357, 358 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37934,19 +37871,19 @@ }, "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 389 ], + "bits": [ 371 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_4_D": { "hide_name": 0, - "bits": [ 390 ], + "bits": [ 372 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 116, 392, 376, 377 ], + "bits": [ 94, 374, 357, 358 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37954,19 +37891,19 @@ }, "r_tx_data_SB_DFFE_Q_5_D": { "hide_name": 0, - "bits": [ 393 ], + "bits": [ 376 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_6_D": { "hide_name": 0, - "bits": [ 397 ], + "bits": [ 380 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 399, 376, 400 ], + "bits": [ 382, 357, 383 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37974,13 +37911,13 @@ }, "r_tx_data_SB_DFFE_Q_7_D": { "hide_name": 0, - "bits": [ 403 ], + "bits": [ 387 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0": { "hide_name": 0, - "bits": [ 405, 385, 376, 406 ], + "bits": [ 389, 357, 367, 390 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37988,13 +37925,13 @@ }, "r_tx_data_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 370 ], + "bits": [ 351 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 408, 376, 409 ], + "bits": [ 393, 357, 394 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38002,13 +37939,21 @@ }, "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 410 ], + "bits": [ 395 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 411, 160 ], + "bits": [ 396, 251 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 172, 251 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38032,7 +37977,7 @@ }, "rx_fifo.empty_o": { "hide_name": 0, - "bits": [ 367 ], + "bits": [ 347 ], "attributes": { "hdlname": "rx_fifo empty_o", "src": "complex_fifo.v:17.19-17.26" @@ -38040,13 +37985,21 @@ }, "rx_fifo.empty_o_SB_DFFSS_Q_D": { "hide_name": 0, - "bits": [ 412 ], + "bits": [ 397 ], "attributes": { } }, + "rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 398, 399, 400, 401 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "rx_fifo.full_o": { "hide_name": 0, - "bits": [ 418 ], + "bits": [ 403 ], "attributes": { "hdlname": "rx_fifo full_o", "src": "complex_fifo.v:16.19-16.25" @@ -38054,13 +38007,13 @@ }, "rx_fifo.full_o_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 417 ], + "bits": [ 402 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 427, 426, 428 ], + "bits": [ 412, 411, 413 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38068,7 +38021,7 @@ }, "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 419, 420, 421, 422 ], + "bits": [ 404, 405, 406, 407 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38076,103 +38029,87 @@ }, "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0": { "hide_name": 0, - "bits": [ 437, 438, 439, 440 ], + "bits": [ 422, 423, 424, 425 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2": { + "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2": { "hide_name": 0, - "bits": [ 423, 445, 446, 447 ], + "bits": [ 431, 432 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1": { + "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 450, 451, 452 ], + "bits": [ 736, 442, 434 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1": { + 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"bits": [ 463 ], + "bits": [ 446, 451, 409, 452 ], "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "rx_fifo.full_o_SB_LUT4_I1_I3": { "hide_name": 0, - "bits": [ 479, 262, 264, 259 ], + "bits": [ 459, 243, 245, 240 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38180,7 +38117,7 @@ }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 481 ], + "bits": [ 461 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -38188,13 +38125,13 @@ }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D": { "hide_name": 0, - "bits": [ 484 ], + "bits": [ 464 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 264, 486, "1", 487 ], + "bits": [ 245, 466, "1", 467 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38202,7 +38139,7 @@ }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 487 ], + "bits": [ 467 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:8.8-8.10" @@ -38210,13 +38147,13 @@ }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D": { "hide_name": 0, - "bits": [ 482 ], + "bits": [ 462 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 488 ], + "bits": [ 468 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38224,13 +38161,13 @@ }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 480 ], + "bits": [ 460 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 485, 479, 483, 264 ], + "bits": [ 465, 459, 463, 245 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38238,13 +38175,13 @@ }, "rx_fifo.full_o_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 478 ], + "bits": [ 458 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 489 ], + "bits": [ 469 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -38252,7 +38189,7 @@ }, "rx_fifo.full_o_SB_LUT4_I2_I3": { "hide_name": 0, - "bits": [ 418, 187 ], + "bits": [ 403, 166 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38260,13 +38197,13 @@ }, "rx_fifo.full_o_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 491 ], + "bits": [ 471 ], "attributes": { } }, "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 493 ], + "bits": [ 473 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -38274,69 +38211,63 @@ }, "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 494, 32, 490 ], + "bits": [ 474, 476, 470 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O": { + "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 424 ], + "bits": [ 475 ], "attributes": { "defaultvalue": "1", - "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1494.16-1494.21" - } - }, - "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3": { - "hide_name": 0, - "bits": [ 459, 473, 424, 495 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 497 ], - "attributes": { + "src": "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" } }, "rx_fifo.mem_i.0.0_RDATA": { "hide_name": 0, - "bits": [ 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524 ], + "bits": [ 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" } }, + "rx_fifo.mem_i.0.0_WCLKE": { + "hide_name": 0, + "bits": [ 409 ], + "attributes": { + "defaultvalue": "1", + "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1494.16-1494.21" + } + }, "rx_fifo.mem_i.0.0_WDATA": { "hide_name": 0, - "bits": [ 532 ], + "bits": [ 513 ], "attributes": { } }, "rx_fifo.mem_i.0.0_WDATA_1": { "hide_name": 0, - "bits": [ 531 ], + "bits": [ 512 ], "attributes": { } }, "rx_fifo.mem_i.0.0_WDATA_2": { "hide_name": 0, - "bits": [ 530 ], + "bits": [ 511 ], "attributes": { } }, "rx_fifo.mem_i.0.0_WDATA_3": { "hide_name": 0, - "bits": [ 529 ], + "bits": [ 510 ], "attributes": { } }, "rx_fifo.mem_i.0.1_RDATA": { "hide_name": 0, - "bits": [ 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548 ], + "bits": [ 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38344,31 +38275,31 @@ }, "rx_fifo.mem_i.0.1_WDATA": { "hide_name": 0, - "bits": [ 552 ], + "bits": [ 534 ], "attributes": { } }, "rx_fifo.mem_i.0.1_WDATA_1": { "hide_name": 0, - "bits": [ 551 ], + "bits": [ 533 ], "attributes": { } }, "rx_fifo.mem_i.0.1_WDATA_2": { "hide_name": 0, - "bits": [ 550 ], + "bits": [ 532 ], "attributes": { } }, "rx_fifo.mem_i.0.1_WDATA_3": { "hide_name": 0, - "bits": [ 549 ], + "bits": [ 531 ], "attributes": { } }, "rx_fifo.mem_i.0.2_RDATA": { "hide_name": 0, - "bits": [ 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568 ], + "bits": [ 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38376,31 +38307,31 @@ }, "rx_fifo.mem_i.0.2_WDATA": { "hide_name": 0, - "bits": [ 572 ], + "bits": [ 554 ], "attributes": { } }, "rx_fifo.mem_i.0.2_WDATA_1": { "hide_name": 0, - "bits": [ 571 ], + "bits": [ 553 ], "attributes": { } }, "rx_fifo.mem_i.0.2_WDATA_2": { "hide_name": 0, - "bits": [ 570 ], + "bits": [ 552 ], "attributes": { } }, "rx_fifo.mem_i.0.2_WDATA_3": { "hide_name": 0, - "bits": [ 569 ], + "bits": [ 551 ], "attributes": { } }, "rx_fifo.mem_i.0.3_RDATA": { "hide_name": 0, - "bits": [ 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588 ], + "bits": [ 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38408,31 +38339,31 @@ }, "rx_fifo.mem_i.0.3_WDATA": { "hide_name": 0, - "bits": [ 592 ], + "bits": [ 574 ], "attributes": { } }, "rx_fifo.mem_i.0.3_WDATA_1": { "hide_name": 0, - "bits": [ 591 ], + "bits": [ 573 ], "attributes": { } }, "rx_fifo.mem_i.0.3_WDATA_2": { "hide_name": 0, - "bits": [ 590 ], + "bits": [ 572 ], "attributes": { } }, "rx_fifo.mem_i.0.3_WDATA_3": { "hide_name": 0, - "bits": [ 589 ], + "bits": [ 571 ], "attributes": { } }, "rx_fifo.mem_q.0.0_RDATA": { "hide_name": 0, - "bits": [ 593, 594, 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608 ], + "bits": [ 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38440,31 +38371,31 @@ }, "rx_fifo.mem_q.0.0_WDATA": { "hide_name": 0, - "bits": [ 612 ], + "bits": [ 594 ], "attributes": { } }, "rx_fifo.mem_q.0.0_WDATA_1": { "hide_name": 0, - "bits": [ 611 ], + "bits": [ 593 ], "attributes": { } }, "rx_fifo.mem_q.0.0_WDATA_2": { "hide_name": 0, - "bits": [ 610 ], + "bits": [ 592 ], "attributes": { } }, "rx_fifo.mem_q.0.0_WDATA_3": { "hide_name": 0, - "bits": [ 609 ], + "bits": [ 591 ], "attributes": { } }, "rx_fifo.mem_q.0.1_RDATA": { "hide_name": 0, - "bits": [ 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628 ], + "bits": [ 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38472,31 +38403,31 @@ }, "rx_fifo.mem_q.0.1_WDATA": { "hide_name": 0, - "bits": [ 632 ], + "bits": [ 614 ], "attributes": { } }, "rx_fifo.mem_q.0.1_WDATA_1": { "hide_name": 0, - "bits": [ 631 ], + "bits": [ 613 ], "attributes": { } }, "rx_fifo.mem_q.0.1_WDATA_2": { "hide_name": 0, - "bits": [ 630 ], + "bits": [ 612 ], "attributes": { } }, "rx_fifo.mem_q.0.1_WDATA_3": { "hide_name": 0, - "bits": [ 629 ], + "bits": [ 611 ], "attributes": { } }, "rx_fifo.mem_q.0.2_RDATA": { "hide_name": 0, - "bits": [ 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648 ], + "bits": [ 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, 629, 630 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1488.16-1488.21", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -38504,31 +38435,31 @@ }, "rx_fifo.mem_q.0.2_WDATA": { "hide_name": 0, - "bits": [ 652 ], + "bits": [ 634 ], "attributes": { } }, "rx_fifo.mem_q.0.2_WDATA_1": { "hide_name": 0, - "bits": [ 651 ], + "bits": [ 633 ], "attributes": { } }, "rx_fifo.mem_q.0.2_WDATA_2": { "hide_name": 0, - "bits": [ 650 ], + "bits": [ 632 ], "attributes": { } }, "rx_fifo.mem_q.0.2_WDATA_3": { "hide_name": 0, - "bits": [ 649 ], + "bits": [ 631 ], "attributes": { } }, "rx_fifo.mem_q.0.3_RDATA": { "hide_name": 0, - "bits": [ 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, 666, 667, 668 ], + "bits": [ 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650 ], "attributes": { "src": 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"bits": [ 661, 660 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3": { + "rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 678 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { - "hide_name": 0, - "bits": [ 679 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": { - "hide_name": 0, - "bits": [ 680 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 676, 675 ], + "bits": [ 673, 674, 662, 663 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { + "rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 683 ], + "bits": [ 664 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 686, 685 ], + "bits": [ 665 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": { + "hide_name": 0, + "bits": [ 666 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 660, 659 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38624,7 +38547,7 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 688, 686 ], + "bits": [ 668, 661 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38632,15 +38555,7 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 690, 689, 691 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 413, 414, 415, 416 ], + "bits": [ 670, 669, 671, 672 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38648,15 +38563,7 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 706 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { - "hide_name": 0, - "bits": [ 684 ], + "bits": [ 667 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38664,55 +38571,71 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 707, 688 ], + "bits": [ 675, 668 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3": { "hide_name": 0, - "bits": [ 710, 711, 712, 709 ], + "bits": [ 347, 677, 675, 678 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O": { "hide_name": 0, - "bits": [ 692, 693, 694, 695 ], + "bits": [ 681, 682, 679, 683 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3": { "hide_name": 0, - "bits": [ 501, 500, 715, 716 ], + "bits": [ 481, 686, 687 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 499, 498, 690, 718 ], + "bits": [ 691, 693, 688, 695 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3": { "hide_name": 0, - "bits": [ 498, 719, 506, 720 ], + "bits": [ 478, 486, 680, 692 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3": { + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3": { "hide_name": 0, - "bits": [ 503, 713, 502, 714 ], + "bits": [ 480, 479, 674, 694 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 483, 684, 482, 685 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 680, 676, 698, 699 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38720,13 +38643,29 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 722 ], + "bits": [ 703 ], "attributes": { } }, "rx_fifo.rd_addr_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 675, 673 ], + "bits": [ 657, 655 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 690, 705, 706, 707 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 696, 700, 701, 702 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38734,23 +38673,31 @@ }, "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 681 ], + "bits": [ 708 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { + "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 723 ], + "bits": [ 709 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { + "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 717, 724, 508, 704 ], + "bits": [ 710 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 684, 658, 657 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38758,21 +38705,15 @@ }, "rx_fifo.rd_addr_gray": { "hide_name": 0, - "bits": [ 738, 736, 734, 733, 732, 730, 728, 727, 726, 505 ], + "bits": [ 722, 720, 719, 718, 717, 716, 714, 712, 711, 485 ], "attributes": { "hdlname": "rx_fifo rd_addr_gray", "src": "complex_fifo.v:28.23-28.35" } }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D": { + "rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 725 ], - "attributes": { - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D": { - "hide_name": 0, - "bits": [ 700, 701, 702 ], + "bits": [ 684, 674, 662, 713 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38780,47 +38721,7 @@ }, "rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 721, 729 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 696, 697, 698, 699 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D": { - "hide_name": 0, - "bits": [ 715, 731 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D": { - "hide_name": 0, - "bits": [ 713, 710, 687, 682 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D": { - "hide_name": 0, - "bits": [ 719, 735 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 703, 673, 704, 705 ], + "bits": [ 697, 715 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38828,13 +38729,37 @@ }, "rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 737 ], + "bits": [ 721 ], "attributes": { } }, + "rx_fifo.rd_addr_gray_SB_DFFESR_Q_D": { + "hide_name": 0, + "bits": [ 655, 704 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1": { + "hide_name": 0, + "bits": [ 689, 723, 488, 704 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 724 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, "rx_fifo.rd_addr_gray_wr": { "hide_name": 0, - "bits": [ 748, 747, 746, 745, 744, 743, 742, 741, 740, 739 ], + "bits": [ 734, 733, 732, 731, 730, 729, 728, 727, 726, 725 ], "attributes": { "hdlname": "rx_fifo rd_addr_gray_wr", "src": "complex_fifo.v:29.23-29.38" @@ -38842,7 +38767,7 @@ }, "rx_fifo.rd_addr_gray_wr_r": { "hide_name": 0, - "bits": [ 477, 473, 464, 456, 453, 472, 441, 429, 448, 423 ], + "bits": [ 453, 451, 449, 736, 433, 735, 437, 414, 426, 408 ], "attributes": { "hdlname": "rx_fifo rd_addr_gray_wr_r", "src": "complex_fifo.v:30.23-30.40" @@ -38850,7 +38775,7 @@ }, "rx_fifo.rd_clk_i": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "rx_fifo rd_clk_i", "src": "complex_fifo.v:12.28-12.36" @@ -38858,7 +38783,7 @@ }, "rx_fifo.rd_data_o": { "hide_name": 0, - "bits": [ 594, 602, 598, 606, 614, 622, 618, 626, 634, 642, 638, 646, 654, 662, 658, 666, 510, 518, 514, 522, 534, 542, 538, 546, 554, 562, 558, 566, 574, 582, 578, 586 ], + "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], "attributes": { "hdlname": "rx_fifo rd_data_o", "src": "complex_fifo.v:14.32-14.41" @@ -38874,7 +38799,7 @@ }, "rx_fifo.wr_addr": { "hide_name": 0, - "bits": [ 528, 460, 459, 462, 471, 469, 465, 525, 526, 527 ], + "bits": [ 509, 445, 446, 440, 443, 447, 505, 506, 507, 508 ], "attributes": { "hdlname": "rx_fifo wr_addr", "src": "complex_fifo.v:23.23-23.30" @@ -38882,7 +38807,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 496, 755 ], + "bits": [ 454, 743 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38890,7 +38815,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 473, 474, 475, 476 ], + "bits": [ 451, 455, 456, 457 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38898,7 +38823,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 756 ], + "bits": [ 744 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38906,7 +38831,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 757 ], + "bits": [ 745 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38914,7 +38839,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 758 ], + "bits": [ 746 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38922,7 +38847,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 753, 752 ], + "bits": [ 741, 740 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38930,7 +38855,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 754, 753 ], + "bits": [ 742, 741 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38938,7 +38863,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 423, 477, 496, 445 ], + "bits": [ 408, 453, 454, 428 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38946,7 +38871,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 761 ], + "bits": [ 749 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38954,7 +38879,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 762 ], + "bits": [ 750 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38962,15 +38887,31 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 467 ], + "bits": [ 751 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, + "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { + "hide_name": 0, + "bits": [ 752 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 437, 438, 429, 439 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 429, 443, 449 ], + "bits": [ 414, 429, 427, 430 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38978,13 +38919,13 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 763 ], + "bits": [ 753 ], "attributes": { } }, "rx_fifo.wr_addr_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 750, 749 ], + "bits": [ 738, 737 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38992,7 +38933,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 764 ], + "bits": [ 754 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39000,7 +38941,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 765 ], + "bits": [ 755 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39008,7 +38949,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 448, 749, 425, 766 ], + "bits": [ 426, 737, 410, 756 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39016,7 +38957,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 767 ], + "bits": [ 757 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39024,7 +38965,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 768 ], + "bits": [ 758 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39032,7 +38973,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 759 ], + "bits": [ 747 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39040,15 +38981,21 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 751, 750 ], + "bits": [ 739, 738 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, + "rx_fifo.wr_addr_SB_DFFESR_Q_E": { + "hide_name": 0, + "bits": [ 514 ], + "attributes": { + } + }, "rx_fifo.wr_addr_gray": { "hide_name": 0, - "bits": [ 784, 782, 781, 779, 777, 775, 773, 772, 771, 527 ], + "bits": [ 774, 772, 771, 769, 767, 765, 763, 762, 761, 508 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray", "src": "complex_fifo.v:24.23-24.35" @@ -39056,13 +39003,13 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 770 ], + "bits": [ 760 ], "attributes": { } }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 472, 774 ], + "bits": [ 735, 764 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39070,7 +39017,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 433, 434, 435, 436 ], + "bits": [ 418, 419, 420, 421 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39078,7 +39025,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 448, 776, 749, 425 ], + "bits": [ 426, 766, 737, 410 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39086,7 +39033,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 441, 453, 760, 769 ], + "bits": [ 437, 433, 748, 759 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39094,7 +39041,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 456, 778 ], + "bits": [ 736, 768 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39102,7 +39049,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 429, 430, 431, 432 ], + "bits": [ 414, 415, 416, 417 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39110,19 +39057,19 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 780 ], + "bits": [ 770 ], "attributes": { } }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 783 ], + "bits": [ 773 ], "attributes": { } }, "rx_fifo.wr_addr_gray_rd": { "hide_name": 0, - "bits": [ 794, 793, 792, 791, 790, 789, 788, 787, 786, 785 ], + "bits": [ 784, 783, 782, 781, 780, 779, 778, 777, 776, 775 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd", "src": "complex_fifo.v:25.23-25.38" @@ -39130,7 +39077,7 @@ }, "rx_fifo.wr_addr_gray_rd_r": { "hide_name": 0, - "bits": [ 708, 719, 690, 710, 715, 721, 713, 700, 703, 717 ], + "bits": [ 677, 680, 670, 674, 673, 697, 684, 696, 690, 689 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd_r", "src": "complex_fifo.v:26.23-26.40" @@ -39154,7 +39101,7 @@ }, "smi_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 365 ], + "bits": [ 477 ], "attributes": { "hdlname": "smi_ctrl_ins i_cs", "src": "smi_ctrl.v:9.25-9.29" @@ -39162,13 +39109,13 @@ }, "smi_ctrl_ins.i_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 795 ], + "bits": [ 785 ], "attributes": { } }, "smi_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], + "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], "attributes": { "hdlname": "smi_ctrl_ins i_data_in", "src": "smi_ctrl.v:7.25-7.34" @@ -39176,7 +39123,7 @@ }, "smi_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 95 ], + "bits": [ 118 ], "attributes": { "hdlname": "smi_ctrl_ins i_fetch_cmd", "src": "smi_ctrl.v:10.25-10.36" @@ -39184,7 +39131,7 @@ }, "smi_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 75, 97, 173, 172, 171 ], + "bits": [ 61, 106, 345, 344, 343 ], "attributes": { "hdlname": "smi_ctrl_ins i_ioc", "src": "smi_ctrl.v:6.25-6.30" @@ -39192,7 +39139,7 @@ }, "smi_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 94 ], + "bits": [ 119 ], "attributes": { "hdlname": "smi_ctrl_ins i_load_cmd", "src": "smi_ctrl.v:11.25-11.35" @@ -39208,7 +39155,7 @@ }, "smi_ctrl_ins.i_rx_fifo_empty": { "hide_name": 0, - "bits": [ 367 ], + "bits": [ 347 ], "attributes": { "hdlname": "smi_ctrl_ins i_rx_fifo_empty", "src": "smi_ctrl.v:16.25-16.40" @@ -39216,7 +39163,7 @@ }, "smi_ctrl_ins.i_rx_fifo_pulled_data": { "hide_name": 0, - "bits": [ 594, 602, 598, 606, 614, 622, 618, 626, 634, 642, 638, 646, 654, 662, 658, 666, 510, 518, 514, 522, 534, 542, 538, 546, 554, 562, 558, 566, 574, 582, 578, 586 ], + "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], "attributes": { "hdlname": "smi_ctrl_ins i_rx_fifo_pulled_data", "src": "smi_ctrl.v:15.25-15.46" @@ -39224,7 +39171,7 @@ }, "smi_ctrl_ins.i_smi_data_in": { "hide_name": 0, - "bits": [ 933, 934, 935, 936, 937, 938, 939, 923 ], + "bits": [ 914, 915, 916, 917, 918, 919, 920, 904 ], "attributes": { "hdlname": "smi_ctrl_ins i_smi_data_in", "src": "smi_ctrl.v:27.25-27.38", @@ -39257,7 +39204,7 @@ }, "smi_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "smi_ctrl_ins i_sys_clk", "src": "smi_ctrl.v:4.25-4.34" @@ -39265,7 +39212,7 @@ }, "smi_ctrl_ins.i_tx_fifo_full": { "hide_name": 0, - "bits": [ 368 ], + "bits": [ 348 ], "attributes": { "hdlname": "smi_ctrl_ins i_tx_fifo_full", "src": "smi_ctrl.v:20.25-20.39" @@ -39273,7 +39220,7 @@ }, "smi_ctrl_ins.int_cnt_rx": { "hide_name": 0, - "bits": [ "0", "0", "0", 59, 58 ], + "bits": [ "0", "0", "0", 67, 66 ], "attributes": { "hdlname": "smi_ctrl_ins int_cnt_rx", "src": "smi_ctrl.v:110.15-110.25" @@ -39281,27 +39228,19 @@ }, "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D": { "hide_name": 0, - "bits": [ 798 ], + "bits": [ 788 ], "attributes": { } }, "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D": { "hide_name": 0, - "bits": [ 797 ], + "bits": [ 787 ], "attributes": { } }, - "smi_ctrl_ins.o_channel": { - "hide_name": 0, - "bits": [ 32 ], - "attributes": { - "hdlname": "smi_ctrl_ins o_channel", - "src": "smi_ctrl.v:31.25-31.34" - } - }, "smi_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 407, 401, 800, "0", "0", "0", "0", "0" ], + "bits": [ 392, 385, 790, "0", "0", "0", "0", "0" ], "attributes": { "hdlname": "smi_ctrl_ins o_data_out", "src": "smi_ctrl.v:8.25-8.35" @@ -39309,21 +39248,13 @@ }, "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E": { "hide_name": 0, - "bits": [ 799 ], + "bits": [ 789 ], "attributes": { } }, - "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 97, 75, 98 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "smi_ctrl_ins.o_dir": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 349 ], "attributes": { "hdlname": "smi_ctrl_ins o_dir", "src": "smi_ctrl.v:32.25-32.30" @@ -39331,7 +39262,7 @@ }, "smi_ctrl_ins.o_smi_data_out": { "hide_name": 0, - "bits": [ 852, 844, 836, 828, 820, 812, 804, 802 ], + "bits": [ 842, 834, 826, 818, 810, 802, 794, 792 ], "attributes": { "hdlname": "smi_ctrl_ins o_smi_data_out", "src": "smi_ctrl.v:26.25-26.39" @@ -39339,13 +39270,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D": { "hide_name": 0, - "bits": [ 803 ], + "bits": [ 793 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 805, 806 ], + "bits": [ 795, 796 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39353,13 +39284,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D": { "hide_name": 0, - "bits": [ 811 ], + "bits": [ 801 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 813, 814 ], + "bits": [ 803, 804 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39367,13 +39298,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D": { "hide_name": 0, - "bits": [ 819 ], + "bits": [ 809 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 821, 822 ], + "bits": [ 811, 812 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39381,13 +39312,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D": { "hide_name": 0, - "bits": [ 827 ], + "bits": [ 817 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 829, 830 ], + "bits": [ 819, 820 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39395,13 +39326,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D": { "hide_name": 0, - "bits": [ 835 ], + "bits": [ 825 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 837, 838 ], + "bits": [ 827, 828 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39409,13 +39340,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D": { "hide_name": 0, - "bits": [ 843 ], + "bits": [ 833 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 845, 846 ], + "bits": [ 835, 836 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39423,13 +39354,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D": { "hide_name": 0, - "bits": [ 851 ], + "bits": [ 841 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 853, 854 ], + "bits": [ 843, 844 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39437,13 +39368,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 801 ], + "bits": [ 791 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 859, 860 ], + "bits": [ 849, 850 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39451,7 +39382,7 @@ }, "smi_ctrl_ins.o_tx_fifo_clock": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "smi_ctrl_ins o_tx_fifo_clock", "src": "smi_ctrl.v:21.25-21.40" @@ -39465,17 +39396,9 @@ "src": "smi_ctrl.v:19.25-19.46" } }, - "smi_ctrl_ins.r_channel": { - "hide_name": 0, - "bits": [ 32 ], - "attributes": { - "hdlname": "smi_ctrl_ins r_channel", - "src": "smi_ctrl.v:115.9-115.18" - } - }, "smi_ctrl_ins.r_dir": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 349 ], "attributes": { "hdlname": "smi_ctrl_ins r_dir", "src": "smi_ctrl.v:116.9-116.14" @@ -39483,7 +39406,7 @@ }, "smi_ctrl_ins.r_dir_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 865 ], + "bits": [ 855 ], "attributes": { "defaultvalue": "1", "src": "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -39491,7 +39414,7 @@ }, "smi_ctrl_ins.r_fifo_pull": { "hide_name": 0, - "bits": [ 866 ], + "bits": [ 856 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pull", "src": "smi_ctrl.v:112.9-112.20" @@ -39499,29 +39422,29 @@ }, "smi_ctrl_ins.r_fifo_pull_1": { "hide_name": 0, - "bits": [ 867 ], + "bits": [ 857 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pull_1", "src": "smi_ctrl.v:113.9-113.22" } }, - "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O": { + "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 508 ], + "bits": [ 488 ], "attributes": { "defaultvalue": "1", "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1490.16-1490.21" } }, - "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O": { + "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 674 ], + "bits": [ 656 ], "attributes": { } }, "smi_ctrl_ins.r_fifo_pulled_data": { "hide_name": 0, - "bits": [ 856, 848, 840, 832, 824, 816, 808, 862, 855, 847, 839, 831, 823, 815, 807, 861, 858, 850, 842, 834, 826, 818, 810, 864, 857, 849, 841, 833, 825, 817, 809, 863 ], + "bits": [ 846, 838, 830, 822, 814, 806, 798, 852, 845, 837, 829, 821, 813, 805, 797, 851, 848, 840, 832, 824, 816, 808, 800, 854, 847, 839, 831, 823, 815, 807, 799, 853 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pulled_data", "src": "smi_ctrl.v:117.16-117.34" @@ -39529,13 +39452,13 @@ }, "smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E": { "hide_name": 0, - "bits": [ 60 ], + "bits": [ 68 ], "attributes": { } }, "smi_ctrl_ins.r_fifo_push": { "hide_name": 0, - "bits": [ 869 ], + "bits": [ 859 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_push", "src": "smi_ctrl.v:179.9-179.20" @@ -39543,7 +39466,7 @@ }, "smi_ctrl_ins.r_fifo_push_1": { "hide_name": 0, - "bits": [ 870 ], + "bits": [ 860 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_push_1", "src": "smi_ctrl.v:180.9-180.22" @@ -39551,7 +39474,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 873, 874, 871 ], + "bits": [ 863, 864, 861 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39559,7 +39482,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 875, 880, 883, 887 ], + "bits": [ 865, 870, 873, 877 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39567,7 +39490,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 876, 881, 882, 879 ], + "bits": [ 866, 871, 872, 869 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39575,7 +39498,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 889 ], + "bits": [ 879 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39583,7 +39506,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 890 ], + "bits": [ 880 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39591,7 +39514,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 892 ], + "bits": [ 882 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39599,7 +39522,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 894 ], + "bits": [ 884 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39607,7 +39530,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 896 ], + "bits": [ 886 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39615,7 +39538,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 898 ], + "bits": [ 888 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39623,7 +39546,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 900 ], + "bits": [ 890 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -39631,7 +39554,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 909, 904, 903 ], + "bits": [ 1073, 894, 893 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39639,39 +39562,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 916, 911, 905 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3": { - "hide_name": 0, - "bits": [ 906, 905, 885, 907 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 913, 908 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3": { - "hide_name": 0, - "bits": [ 910, 903, 911, 912 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 914, 915, 904 ], + "bits": [ 897, 896, 895 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39679,7 +39570,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 884, 885, 878, 886 ], + "bits": [ 874, 875, 868, 876 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39687,7 +39578,7 @@ }, "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 872 ], + "bits": [ 862 ], "attributes": { } }, @@ -39701,7 +39592,7 @@ }, "smi_ctrl_ins.soe_and_reset": { "hide_name": 0, - "bits": [ 796 ], + "bits": [ 786 ], "attributes": { "hdlname": "smi_ctrl_ins soe_and_reset", "src": "smi_ctrl.v:119.10-119.23" @@ -39709,7 +39600,7 @@ }, "smi_ctrl_ins.swe_and_reset": { "hide_name": 0, - "bits": [ 918 ], + "bits": [ 899 ], "attributes": { "hdlname": "smi_ctrl_ins swe_and_reset", "src": "smi_ctrl.v:182.10-182.23" @@ -39717,32 +39608,32 @@ }, "smi_ctrl_ins.tx_reg_state": { "hide_name": 0, - "bits": [ 924, 926, 922, 920 ], + "bits": [ 905, 907, 903, 901 ], "attributes": { "onehot": "00000000000000000000000000000001" } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D": { "hide_name": 0, - "bits": [ 921 ], + "bits": [ 902 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D": { "hide_name": 0, - "bits": [ 925 ], + "bits": [ 906 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D": { "hide_name": 0, - "bits": [ 927 ], + "bits": [ 908 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 928, 929 ], + "bits": [ 909, 910 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39750,13 +39641,13 @@ }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D": { "hide_name": 0, - "bits": [ 919 ], + "bits": [ 900 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_pull_trigger": { "hide_name": 0, - "bits": [ 868 ], + "bits": [ 858 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_pull_trigger", "src": "smi_ctrl.v:114.10-114.29" @@ -39764,13 +39655,13 @@ }, "smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 930 ], + "bits": [ 911 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_push_trigger": { "hide_name": 0, - "bits": [ 917 ], + "bits": [ 898 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_push_trigger", "src": "smi_ctrl.v:181.10-181.29" @@ -39778,19 +39669,19 @@ }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D": { "hide_name": 0, - "bits": [ 931 ], + "bits": [ 912 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R": { "hide_name": 0, - "bits": [ 932 ], + "bits": [ 913 ], "attributes": { } }, "spi_if_ins.i_data_out": { "hide_name": 0, - "bits": [ 404, 398, 394, 391, 387, 381, 374, 372 ], + "bits": [ 388, 381, 377, 373, 369, 363, 355, 353 ], "attributes": { "hdlname": "spi_if_ins i_data_out", "src": "spi_if.v:9.22-9.32" @@ -39830,7 +39721,7 @@ }, "spi_if_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "spi_if_ins i_sys_clk", "src": "spi_if.v:5.11-5.20" @@ -39838,7 +39729,7 @@ }, "spi_if_ins.o_cs": { "hide_name": 0, - "bits": [ 158, 66, 365, 941 ], + "bits": [ 923, 74, 477, 922 ], "attributes": { "hdlname": "spi_if_ins o_cs", "src": "spi_if.v:10.22-10.26" @@ -39846,13 +39737,13 @@ }, "spi_if_ins.o_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 940 ], + "bits": [ 921 ], "attributes": { } }, "spi_if_ins.o_cs_SB_LUT4_I0_3_O": { "hide_name": 0, - "bits": [ 395, 385, 376, 396 ], + "bits": [ 378, 357, 367, 379 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39860,13 +39751,53 @@ }, "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 164, 170, 168, 166 ], + "bits": [ 391, 384, 925, 375 ], "attributes": { } }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2": { + "hide_name": 0, + "bits": [ 927, 251 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2": { + "hide_name": 0, + "bits": [ 928, 251 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2": { + "hide_name": 0, + "bits": [ 929, 251 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 926, 251 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E": { + "hide_name": 0, + "bits": [ 360 ], + "attributes": { + "defaultvalue": "1", + "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, "spi_if_ins.o_cs_SB_LUT4_I0_4_O": { "hide_name": 0, - "bits": [ 121, 800, 402, 377 ], + "bits": [ 100, 790, 386, 358 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39874,7 +39805,7 @@ }, "spi_if_ins.o_cs_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 3, 942 ], + "bits": [ 3, 924 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39882,13 +39813,13 @@ }, "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 371 ], + "bits": [ 352 ], "attributes": { } }, "spi_if_ins.o_data_in": { "hide_name": 0, - "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], + "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], "attributes": { "hdlname": "spi_if_ins o_data_in", "src": "spi_if.v:8.22-8.31" @@ -39896,13 +39827,13 @@ }, "spi_if_ins.o_data_in_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 944 ], + "bits": [ 931 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd": { "hide_name": 0, - "bits": [ 95 ], + "bits": [ 118 ], "attributes": { "hdlname": "spi_if_ins o_fetch_cmd", "src": "spi_if.v:11.22-11.33" @@ -39910,7 +39841,7 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 958, 957, 950 ], + "bits": [ 945, 944, 937 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39918,13 +39849,13 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 951 ], + "bits": [ 938 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 3, 958, 959, 960 ], + "bits": [ 3, 945, 946, 947 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39932,7 +39863,7 @@ }, "spi_if_ins.o_ioc": { "hide_name": 0, - "bits": [ 75, 97, 173, 172, 171 ], + "bits": [ 61, 106, 345, 344, 343 ], "attributes": { "hdlname": "spi_if_ins o_ioc", "src": "spi_if.v:7.22-7.27" @@ -39940,13 +39871,13 @@ }, "spi_if_ins.o_ioc_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 65 ], + "bits": [ 73 ], "attributes": { } }, "spi_if_ins.o_load_cmd": { "hide_name": 0, - "bits": [ 94 ], + "bits": [ 119 ], "attributes": { "hdlname": "spi_if_ins o_load_cmd", "src": "spi_if.v:12.22-12.32" @@ -39954,7 +39885,7 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 953, 954 ], + "bits": [ 940, 941 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39962,13 +39893,13 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 961 ], + "bits": [ 948 ], "attributes": { } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 958, 953, 954, 963 ], + "bits": [ 945, 940, 941, 950 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39976,7 +39907,7 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 962, 963, 964 ], + "bits": [ 949, 950, 951 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39984,13 +39915,13 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 952 ], + "bits": [ 939 ], "attributes": { } }, "spi_if_ins.o_spi_miso": { "hide_name": 0, - "bits": [ 366 ], + "bits": [ 346 ], "attributes": { "hdlname": "spi_if_ins o_spi_miso", "src": "spi_if.v:16.12-16.22" @@ -39998,7 +39929,7 @@ }, "spi_if_ins.r_tx_byte": { "hide_name": 0, - "bits": [ 973, 972, 971, 970, 969, 968, 967, 966 ], + "bits": [ 960, 959, 958, 957, 956, 955, 954, 953 ], "attributes": { "hdlname": "spi_if_ins r_tx_byte", "src": "spi_if.v:33.14-33.23" @@ -40006,13 +39937,13 @@ }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 965 ], + "bits": [ 952 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid": { "hide_name": 0, - "bits": [ 975 ], + "bits": [ 962 ], "attributes": { "hdlname": "spi_if_ins r_tx_data_valid", "src": "spi_if.v:32.14-32.29" @@ -40020,19 +39951,19 @@ }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 974 ], + "bits": [ 961 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 977 ], + "bits": [ 964 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 982, 981, 976 ], + "bits": [ 969, 968, 963 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40040,7 +39971,7 @@ }, "spi_if_ins.spi.SCKr": { "hide_name": 0, - "bits": [ 983, 981, 982 ], + "bits": [ 970, 968, 969 ], "attributes": { "hdlname": "spi_if_ins spi SCKr", "src": "spi_slave.v:61.13-61.17" @@ -40072,7 +40003,7 @@ }, "spi_if_ins.spi.i_sys_clk": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "spi_if_ins spi i_sys_clk", "src": "spi_slave.v:3.22-3.31" @@ -40080,7 +40011,7 @@ }, "spi_if_ins.spi.i_tx_byte": { "hide_name": 0, - "bits": [ 973, 972, 971, 970, 969, 968, 967, 966 ], + "bits": [ 960, 959, 958, 957, 956, 955, 954, 953 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_byte", "src": "spi_slave.v:7.22-7.31" @@ -40088,7 +40019,7 @@ }, "spi_if_ins.spi.i_tx_data_valid": { "hide_name": 0, - "bits": [ 975 ], + "bits": [ 962 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_data_valid", "src": "spi_slave.v:6.22-6.37" @@ -40096,7 +40027,7 @@ }, "spi_if_ins.spi.o_rx_byte": { "hide_name": 0, - "bits": [ 949, 948, 947, 946, 945, 69, 68, 943 ], + "bits": [ 936, 935, 934, 933, 932, 77, 76, 930 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_byte", "src": "spi_slave.v:5.22-5.31" @@ -40104,7 +40035,7 @@ }, "spi_if_ins.spi.o_rx_data_valid": { "hide_name": 0, - "bits": [ 958 ], + "bits": [ 945 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_data_valid", "src": "spi_slave.v:4.22-4.37" @@ -40112,7 +40043,7 @@ }, "spi_if_ins.spi.o_spi_miso": { "hide_name": 0, - "bits": [ 366 ], + "bits": [ 346 ], "attributes": { "hdlname": "spi_if_ins spi o_spi_miso", "src": "spi_slave.v:11.16-11.26" @@ -40120,29 +40051,29 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 993 ], + "bits": [ 980 ], "attributes": { } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 966, 976, 994 ], + "bits": [ 953, 963, 981, 982 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2": { "hide_name": 0, - "bits": [ 995, 996, 997, 998 ], + "bits": [ 983, 984, 987, 988 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 1001, 1005, 1006 ], + "bits": [ 983, 984, 985, 986 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40150,7 +40081,7 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 976, 978, 979 ], + "bits": [ 963, 965, 966 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40158,7 +40089,7 @@ }, "spi_if_ins.spi.r2_rx_done": { "hide_name": 0, - "bits": [ 1012 ], + "bits": [ 999 ], "attributes": { "hdlname": "spi_if_ins spi r2_rx_done", "src": "spi_slave.v:21.7-21.17" @@ -40166,7 +40097,7 @@ }, "spi_if_ins.spi.r3_rx_done": { "hide_name": 0, - "bits": [ 1013 ], + "bits": [ 1000 ], "attributes": { "hdlname": "spi_if_ins spi r3_rx_done", "src": "spi_slave.v:22.7-22.17" @@ -40174,13 +40105,13 @@ }, "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 985 ], + "bits": [ 972 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count": { "hide_name": 0, - "bits": [ 1018, 1017, 1015 ], + "bits": [ 1005, 1004, 1002 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_bit_count", "src": "spi_slave.v:16.13-16.27" @@ -40188,25 +40119,25 @@ }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D": { "hide_name": 0, - "bits": [ 1016 ], + "bits": [ 1003 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D": { "hide_name": 0, - "bits": [ 1019 ], + "bits": [ 1006 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 1014 ], + "bits": [ 1001 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1020 ], + "bits": [ 1007 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40214,7 +40145,7 @@ }, "spi_if_ins.spi.r_rx_byte": { "hide_name": 0, - "bits": [ 992, 991, 990, 989, 988, 987, 986, 984 ], + "bits": [ 979, 978, 977, 976, 975, 974, 973, 971 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_byte", "src": "spi_slave.v:19.13-19.22" @@ -40222,7 +40153,7 @@ }, "spi_if_ins.spi.r_rx_done": { "hide_name": 0, - "bits": [ 1011 ], + "bits": [ 998 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_done", "src": "spi_slave.v:20.7-20.16" @@ -40230,7 +40161,7 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 48, 1029 ], + "bits": [ 48, 1016 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40238,19 +40169,19 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1022 ], + "bits": [ 1009 ], "attributes": { } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 1030 ], + "bits": [ 1017 ], "attributes": { } }, "spi_if_ins.spi.r_temp_rx_byte": { "hide_name": 0, - "bits": [ 1028, 1027, 1026, 1025, 1024, 1023, 1021, "x" ], + "bits": [ 1015, 1014, 1013, 1012, 1011, 1010, 1008, "x" ], "attributes": { "hdlname": "spi_if_ins spi r_temp_rx_byte", "src": "spi_slave.v:18.13-18.27" @@ -40258,7 +40189,7 @@ }, "spi_if_ins.spi.r_tx_bit_count": { "hide_name": 0, - "bits": [ 1002, 1001, 995 ], + "bits": [ 991, 984, 983 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_bit_count", "src": "spi_slave.v:17.13-17.27" @@ -40266,25 +40197,25 @@ }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 1031 ], + "bits": [ 1018 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D": { "hide_name": 0, - "bits": [ 1033 ], + "bits": [ 1020 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 1032 ], + "bits": [ 1019 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1034 ], + "bits": [ 1021 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40292,7 +40223,7 @@ }, "spi_if_ins.spi.r_tx_byte": { "hide_name": 0, - "bits": [ 1008, 1007, 1010, 1009, 1004, 1000, 1003, 999 ], + "bits": [ 995, 994, 997, 996, 993, 992, 990, 989 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_byte", "src": "spi_slave.v:23.13-23.22" @@ -40300,13 +40231,13 @@ }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 980 ], + "bits": [ 967 ], "attributes": { } }, "spi_if_ins.state_if": { "hide_name": 0, - "bits": [ 956, 955, 953 ], + "bits": [ 943, 942, 940 ], "attributes": { "hdlname": "spi_if_ins state_if", "src": "spi_if.v:29.14-29.22" @@ -40314,13 +40245,13 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 1037 ], + "bits": [ 1024 ], "attributes": { } }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 958, 959 ], + "bits": [ 945, 946 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40328,7 +40259,7 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 3, 962, 1035 ], + "bits": [ 3, 949, 1022 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40336,7 +40267,7 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 943, 959, 1038 ], + "bits": [ 930, 946, 1025 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40344,13 +40275,13 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 1036 ], + "bits": [ 1023 ], "attributes": { } }, "spi_if_ins.w_rx_data": { "hide_name": 0, - "bits": [ 949, 948, 947, 946, 945, 69, 68, 943 ], + "bits": [ 936, 935, 934, 933, 932, 77, 76, 930 ], "attributes": { "hdlname": "spi_if_ins w_rx_data", "src": "spi_if.v:31.14-31.23" @@ -40358,7 +40289,7 @@ }, "spi_if_ins.w_rx_data_valid": { "hide_name": 0, - "bits": [ 958 ], + "bits": [ 945 ], "attributes": { "hdlname": "spi_if_ins w_rx_data_valid", "src": "spi_if.v:30.14-30.29" @@ -40366,7 +40297,7 @@ }, "sys_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 158 ], + "bits": [ 923 ], "attributes": { "hdlname": "sys_ctrl_ins i_cs", "src": "sys_ctrl.v:9.29-9.33" @@ -40374,13 +40305,21 @@ }, "sys_ctrl_ins.i_cs_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 67 ], + "bits": [ 75 ], "attributes": { } }, + "sys_ctrl_ins.i_cs_SB_LUT4_I2_I3": { + "hide_name": 0, + "bits": [ 118, 923, 1026 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "sys_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], + "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], "attributes": { "hdlname": "sys_ctrl_ins i_data_in", "src": "sys_ctrl.v:7.29-7.38" @@ -40388,7 +40327,7 @@ }, "sys_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 95 ], + "bits": [ 118 ], "attributes": { "hdlname": "sys_ctrl_ins i_fetch_cmd", "src": "sys_ctrl.v:10.29-10.40" @@ -40396,7 +40335,7 @@ }, "sys_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 75, 97, 173, 172, 171 ], + "bits": [ 61, 106, 345, 344, 343 ], "attributes": { "hdlname": "sys_ctrl_ins i_ioc", "src": "sys_ctrl.v:6.29-6.34" @@ -40404,7 +40343,7 @@ }, "sys_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 94 ], + "bits": [ 119 ], "attributes": { "hdlname": "sys_ctrl_ins i_load_cmd", "src": "sys_ctrl.v:11.29-11.39" @@ -40420,7 +40359,7 @@ }, "sys_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "sys_ctrl_ins i_sys_clk", "src": "sys_ctrl.v:4.29-4.38" @@ -40460,7 +40399,7 @@ }, "tx_fifo.empty_o": { "hide_name": 0, - "bits": [ 336 ], + "bits": [ 318 ], "attributes": { "hdlname": "tx_fifo empty_o", "src": "complex_fifo.v:17.19-17.26" @@ -40468,77 +40407,53 @@ }, "tx_fifo.empty_o_SB_DFFNSS_Q_D": { "hide_name": 0, - "bits": [ 1039 ], + "bits": [ 1027 ], "attributes": { } }, "tx_fifo.empty_o_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 358, 1042, 1041, 1043 ], + "bits": [ 1032, 1030, 1036, 1047 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3": { "hide_name": 0, - "bits": [ 1049, 1054, 1055, 1044 ], + "bits": [ 1033, 1034, 1035 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1050, 1051, 1052, 1053 ], + "bits": [ 1043, 1046, 1040, 1038 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3": { "hide_name": 0, - "bits": [ 1045, 1046, 1047, 1048 ], + "bits": [ 1043, 1044, 1045, 1046 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 1046, 1048, 1057 ], + "bits": [ 325, 326, 327, 328 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 343, 344, 345, 346 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3": { - "hide_name": 0, - "bits": [ 1059, 1061, 1062, 1063 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 337, 348, 1045, 1064 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 1040, 348, 1045, 1060 ], + "bits": [ 1049, 1050, 1051, 1052 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40546,7 +40461,7 @@ }, "tx_fifo.full_o": { "hide_name": 0, - "bits": [ 368 ], + "bits": [ 348 ], "attributes": { "hdlname": "tx_fifo full_o", "src": "complex_fifo.v:16.19-16.25" @@ -40554,13 +40469,13 @@ }, "tx_fifo.full_o_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 1066 ], + "bits": [ 1055 ], "attributes": { } }, "tx_fifo.full_o_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 1071, 1072, 1073 ], + "bits": [ 1060, 1061, 1062 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40568,7 +40483,39 @@ }, "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 1067, 1068, 1069, 1070 ], + "bits": [ 1056, 1057, 1058, 1059 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 1063, 1064 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 1071, 895, 875, 1072 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1069, 893, 896, 1070 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 1074, 1075, 894 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40576,7 +40523,7 @@ }, "tx_fifo.rd_addr": { "hide_name": 0, - "bits": [ 1095, 357, 1062, 1059, 1052, 1050, 1056, 1046, 1045, 1040 ], + "bits": [ 1092, 319, 1039, 1049, 1044, 1043, 1034, 1037, 1041, 1031 ], "attributes": { "hdlname": "tx_fifo rd_addr", "src": "complex_fifo.v:27.23-27.30" @@ -40584,7 +40531,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D": { "hide_name": 0, - "bits": [ 1082, 1081 ], + "bits": [ 1080, 1079 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40592,7 +40539,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 359, 360, 361, 362 ], + "bits": [ 337, 338, 339, 340 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40600,7 +40547,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1084 ], + "bits": [ 1082 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40608,15 +40555,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 1085 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": { - "hide_name": 0, - "bits": [ 1086 ], + "bits": [ 1083 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40624,7 +40563,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1081, 1080 ], + "bits": [ 1079, 1078 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40632,7 +40571,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_4_D": { "hide_name": 0, - "bits": [ 1089, 1082 ], + "bits": [ 1086, 1080 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40640,7 +40579,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1088 ], + "bits": [ 1085 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40648,7 +40587,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_5_D": { "hide_name": 0, - "bits": [ 1083, 1091 ], + "bits": [ 1081, 1088 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40656,7 +40595,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1058, 1061, 1093, 1092 ], + "bits": [ 1048, 1053, 1090, 1089 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40664,7 +40603,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1090 ], + "bits": [ 1087 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40672,7 +40611,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 1094 ], + "bits": [ 1091 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40680,7 +40619,7 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1042, 1083 ], + "bits": [ 1029, 1081 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40688,57 +40627,41 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_8_D": { "hide_name": 0, - "bits": [ 1096 ], + "bits": [ 1093 ], "attributes": { } }, "tx_fifo.rd_addr_SB_DFFNESR_Q_D": { "hide_name": 0, - "bits": [ 1047, 1080, 1079 ], + "bits": [ 1042, 1078, 1077 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 1087 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, "tx_fifo.rd_addr_gray": { "hide_name": 0, - "bits": [ 1109, 1107, 1106, 1105, 1104, 1102, 1101, 1099, 1097, 1040 ], + "bits": [ 1107, 1105, 1104, 1103, 1102, 1100, 1099, 1097, 1095, 1031 ], "attributes": { "hdlname": "tx_fifo rd_addr_gray", "src": "complex_fifo.v:28.23-28.35" } }, - "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D": { - "hide_name": 0, - "bits": [ 348, 349, 350 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D": { "hide_name": 0, - "bits": [ 1098 ], + "bits": [ 1096 ], "attributes": { } }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D": { "hide_name": 0, - "bits": [ 1100 ], + "bits": [ 1098 ], "attributes": { } }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D": { "hide_name": 0, - "bits": [ 1051, 1103 ], + "bits": [ 1045, 1101 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40746,7 +40669,7 @@ }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 352, 353, 354, 355 ], + "bits": [ 330, 331, 332, 333 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40754,19 +40677,35 @@ }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D": { "hide_name": 0, - "bits": [ 1108 ], + "bits": [ 1106 ], "attributes": { } }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D": { "hide_name": 0, - "bits": [ 337, 357, 358, 338 ], + "bits": [ 335, 319, 320, 336 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1054, 1108, 1094 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1109 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, "bits": [ 1110 ], "attributes": { @@ -40774,6 +40713,14 @@ "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, + "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { + "hide_name": 0, + "bits": [ 1084 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, "tx_fifo.rd_addr_gray_wr": { "hide_name": 0, "bits": [ 1120, 1119, 1118, 1117, 1116, 1115, 1114, 1113, 1112, 1111 ], @@ -40784,7 +40731,7 @@ }, "tx_fifo.rd_addr_gray_wr_r": { "hide_name": 0, - "bits": [ 881, 874, 914, 909, 910, 916, 906, 884, 877, 876 ], + "bits": [ 871, 864, 1074, 1073, 1069, 897, 1071, 874, 867, 866 ], "attributes": { "hdlname": "tx_fifo rd_addr_gray_wr_r", "src": "complex_fifo.v:30.23-30.40" @@ -40792,7 +40739,7 @@ }, "tx_fifo.rd_en_i": { "hide_name": 0, - "bits": [ 335 ], + "bits": [ 317 ], "attributes": { "hdlname": "tx_fifo rd_en_i", "src": "complex_fifo.v:13.28-13.35" @@ -40808,7 +40755,7 @@ }, "tx_fifo.wr_addr": { "hide_name": 0, - "bits": [ 1137, 902, 873, 901, 899, 897, 895, 893, 891, 888 ], + "bits": [ 1139, 892, 863, 891, 889, 887, 885, 883, 881, 878 ], "attributes": { "hdlname": "tx_fifo wr_addr", "src": "complex_fifo.v:23.23-23.30" @@ -40816,7 +40763,15 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 910, 1130, 1124 ], + "bits": [ 1069, 1125, 1124 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 874, 1122, 1121, 1126 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40824,7 +40779,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1125 ], + "bits": [ 1128 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40832,7 +40787,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 1126 ], + "bits": [ 1129 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40840,7 +40795,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 906, 1123, 1122 ], + "bits": [ 1071, 1123, 1122 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40848,7 +40803,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 1128 ], + "bits": [ 1131 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40856,7 +40811,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1131, 1130 ], + "bits": [ 1133, 1125 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40864,7 +40819,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 914, 1132, 1131 ], + "bits": [ 1074, 1134, 1133 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40872,7 +40827,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 909, 1133, 1134, 1135 ], + "bits": [ 1073, 1135, 1136, 1137 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40880,7 +40835,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1136 ], + "bits": [ 1138 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40888,7 +40843,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 1129 ], + "bits": [ 1132 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40896,7 +40851,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 882, 1132 ], + "bits": [ 872, 1134 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40904,7 +40859,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 916, 874, 1138, 1139 ], + "bits": [ 897, 864, 1140, 1141 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40912,13 +40867,13 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 1140 ], + "bits": [ 1142 ], "attributes": { } }, "tx_fifo.wr_addr_gray": { "hide_name": 0, - "bits": [ 1156, 1154, 1152, 1150, 1149, 1147, 1146, 1144, 1142, 888 ], + "bits": [ 1157, 1155, 1154, 1152, 1151, 1149, 1148, 1146, 1144, 878 ], "attributes": { "hdlname": "tx_fifo wr_addr_gray", "src": "complex_fifo.v:24.23-24.35" @@ -40926,31 +40881,31 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 1141 ], + "bits": [ 1143 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 1143 ], + "bits": [ 1145 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 1145 ], + "bits": [ 1147 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 1148 ], + "bits": [ 1150 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 909, 914, 1151, 1134 ], + "bits": [ 1073, 1074, 1153, 1136 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40958,7 +40913,7 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 1074, 1075, 1076, 1077 ], + "bits": [ 1065, 1066, 1067, 1068 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40966,13 +40921,13 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 1155 ], + "bits": [ 1156 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 877, 1121, 1078 ], + "bits": [ 867, 1121, 1076 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40980,7 +40935,7 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1157 ], + "bits": [ 1158 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40988,7 +40943,7 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 1158 ], + "bits": [ 1127 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40996,20 +40951,12 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 1127 ], + "bits": [ 1130 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 884, 1122, 1121, 1153 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "tx_fifo.wr_addr_gray_rd": { "hide_name": 0, "bits": [ 1168, 1167, 1166, 1165, 1164, 1163, 1162, 1161, 1160, 1159 ], @@ -41020,7 +40967,7 @@ }, "tx_fifo.wr_addr_gray_rd_r": { "hide_name": 0, - "bits": [ 358, 360, 1061, 1058, 1051, 359, 1065, 1047, 348, 337 ], + "bits": [ 320, 338, 1053, 1048, 1045, 337, 1033, 1042, 1054, 335 ], "attributes": { "hdlname": "tx_fifo wr_addr_gray_rd_r", "src": "complex_fifo.v:26.23-26.40" @@ -41028,7 +40975,7 @@ }, "tx_fifo.wr_clk_i": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "hdlname": "tx_fifo wr_clk_i", "src": "complex_fifo.v:7.28-7.36" @@ -41059,14 +41006,14 @@ }, "w_clock_sys": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "src": "top.v:97.14-97.25" } }, "w_cs": { "hide_name": 0, - "bits": [ 158, 66, 365, 941 ], + "bits": [ 923, 74, 477, 922 ], "attributes": { "src": "top.v:101.14-101.18" } @@ -41080,35 +41027,35 @@ }, "w_fetch": { "hide_name": 0, - "bits": [ 95 ], + "bits": [ 118 ], "attributes": { "src": "top.v:102.14-102.21" } }, "w_ioc": { "hide_name": 0, - "bits": [ 75, 97, 173, 172, 171 ], + "bits": [ 61, 106, 345, 344, 343 ], "attributes": { "src": "top.v:98.14-98.19" } }, "w_load": { "hide_name": 0, - "bits": [ 94 ], + "bits": [ 119 ], "attributes": { "src": "top.v:103.14-103.20" } }, "w_lvds_rx_09_d0": { "hide_name": 0, - "bits": [ 178 ], + "bits": [ 157 ], "attributes": { "src": "top.v:330.8-330.23" } }, "w_lvds_rx_09_d0_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 186, 1169, 492 ], + "bits": [ 165, 1169, 472 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41116,13 +41063,13 @@ }, "w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 193 ], + "bits": [ 174 ], "attributes": { } }, "w_lvds_rx_09_d0_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 185, 186, 1171, 492 ], + "bits": [ 164, 165, 1171, 472 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41160,7 +41107,7 @@ }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 186, 1180, "1", 1181 ], + "bits": [ 165, 1180, "1", 1181 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41182,7 +41129,7 @@ }, "w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 186, 1183 ], + "bits": [ 165, 1183 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41212,21 +41159,21 @@ }, "w_lvds_rx_09_d1": { "hide_name": 0, - "bits": [ 179 ], + "bits": [ 158 ], "attributes": { "src": "top.v:331.8-331.23" } }, "w_lvds_rx_24_d0": { "hide_name": 0, - "bits": [ 180 ], + "bits": [ 159 ], "attributes": { "src": "top.v:332.8-332.23" } }, "w_lvds_rx_24_d1": { "hide_name": 0, - "bits": [ 181 ], + "bits": [ 160 ], "attributes": { "src": "top.v:333.8-333.23" } @@ -41241,7 +41188,7 @@ }, "w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 271 ], + "bits": [ 253 ], "attributes": { } }, @@ -41261,8 +41208,9 @@ }, "w_rx_09_fifo_data": { "hide_name": 0, - "bits": [ 255, 220, 194, 197, 222, 244, 246, 248, 250, 252, 200, 203, 199, 202, 205, 207, 209, 211, 213, 215, 217, 219, 224, 226, 228, 230, 232, 234, 236, 238, 240 ], + "bits": [ 236, 201, 175, 178, 203, 225, 227, 229, 231, 233, 181, 184, 180, 183, 186, 188, 190, 192, 194, 196, 198, 200, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223 ], "attributes": { + "src": "top.v:338.15-338.32" } }, "w_rx_09_fifo_write_clk": { @@ -41274,7 +41222,7 @@ }, "w_rx_24_fifo_data": { "hide_name": 0, - "bits": [ 332, 297, 272, 274, 299, 321, 323, 325, 327, 329, 277, 280, 276, 279, 282, 284, 286, 288, 290, 292, 294, 296, 301, 303, 305, 307, 309, 311, 313, 315, 317, 319 ], + "bits": [ 314, 279, 254, 256, 281, 303, 305, 307, 309, 311, 259, 262, 258, 261, 264, 266, 268, 270, 272, 274, 276, 278, 283, 285, 287, 289, 291, 293, 295, 297, 299, 301 ], "attributes": { "src": "top.v:342.15-342.32" } @@ -41288,28 +41236,28 @@ }, "w_rx_data": { "hide_name": 0, - "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], + "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], "attributes": { "src": "top.v:99.14-99.23" } }, "w_rx_fifo_empty": { "hide_name": 0, - "bits": [ 367 ], + "bits": [ 347 ], "attributes": { "src": "top.v:378.8-378.23" } }, "w_rx_fifo_full": { "hide_name": 0, - "bits": [ 418 ], + "bits": [ 403 ], "attributes": { "src": "top.v:377.8-377.22" } }, "w_rx_fifo_pulled_data": { "hide_name": 0, - "bits": [ 594, 602, 598, 606, 614, 622, 618, 626, 634, 642, 638, 646, 654, 662, 658, 666, 510, 518, 514, 522, 534, 542, 538, 546, 554, 562, 558, 566, 574, 582, 578, 586 ], + "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], "attributes": { "src": "top.v:376.15-376.36" } @@ -41323,28 +41271,28 @@ }, "w_rx_sync_input_09": { "hide_name": 0, - "bits": [ 182 ], + "bits": [ 161 ], "attributes": { "src": "top.v:119.8-119.26" } }, "w_rx_sync_input_24": { "hide_name": 0, - "bits": [ 256 ], + "bits": [ 237 ], "attributes": { "src": "top.v:120.8-120.26" } }, "w_smi_data_direction": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 349 ], "attributes": { "src": "top.v:451.8-451.28" } }, "w_smi_data_input": { "hide_name": 0, - "bits": [ 933, 934, 935, 936, 937, 938, 939, 923 ], + "bits": [ 914, 915, 916, 917, 918, 919, 920, 904 ], "attributes": { "src": "top.v:490.14-490.30", "unused_bits": "0 1 2 3 4 5 6" @@ -41352,27 +41300,27 @@ }, "w_smi_data_output": { "hide_name": 0, - "bits": [ 852, 844, 836, 828, 820, 812, 804, 802 ], + "bits": [ 842, 834, 826, 818, 810, 802, 794, 792 ], "attributes": { "src": "top.v:489.14-489.31" } }, "w_tx_data_io": { "hide_name": 0, - "bits": [ 126, 113, 121, 116, 128, 135, 133, 131 ], + "bits": [ 122, 91, 100, 94, 125, 132, 130, 128 ], "attributes": { "src": "top.v:106.14-106.26" } }, "w_tx_data_smi": { "hide_name": 0, - "bits": [ 407, 401, 800 ], + "bits": [ 392, 385, 790 ], "attributes": { } }, "w_tx_fifo_clock": { "hide_name": 0, - "bits": [ 63 ], + "bits": [ 71 ], "attributes": { "src": "top.v:424.8-424.23" } @@ -41386,21 +41334,21 @@ }, "w_tx_fifo_empty": { "hide_name": 0, - "bits": [ 336 ], + "bits": [ 318 ], "attributes": { "src": "top.v:421.8-421.23" } }, "w_tx_fifo_full": { "hide_name": 0, - "bits": [ 368 ], + "bits": [ 348 ], "attributes": { "src": "top.v:420.8-420.22" } }, "w_tx_fifo_pull": { "hide_name": 0, - "bits": [ 335 ], + "bits": [ 317 ], "attributes": { "src": "top.v:426.8-426.22" } diff --git a/firmware/top.v b/firmware/top.v index dd6d4c6..edce3e0 100644 --- a/firmware/top.v +++ b/firmware/top.v @@ -197,8 +197,8 @@ module top ( // Digital interfaces .i_button(i_button), .i_config(i_config), - .o_led0 (/*o_led0*/), - .o_led1 (/*o_led1*/), + .o_led0 (o_led0), + .o_led1 (o_led1), .o_pmod (io_pmod[3:0]), // Analog interfaces @@ -573,7 +573,7 @@ module top ( assign o_smi_read_req = (w_smi_data_direction) ? w_smi_read_req : w_smi_write_req; assign o_smi_write_req = 1'bZ; - assign o_led0 = w_smi_data_direction; - assign o_led1 = channel; + //assign o_led0 = w_smi_data_direction; + //assign o_led1 = channel; endmodule // top diff --git a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h index a45c7fd..a595825 100644 --- a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h +++ b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h @@ -18,12 +18,12 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure * Date: 2024-03-14 - * Time: 22:57:13 + * Time: 23:25:30 */ struct tm smi_stream_dev_date_time = { - .tm_sec = 13, - .tm_min = 57, - .tm_hour = 22, + .tm_sec = 30, + .tm_min = 25, + .tm_hour = 23, .tm_mday = 14, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ @@ -31,78 +31,77 @@ struct tm smi_stream_dev_date_time = { /* * Data blob of variable smi_stream_dev: - * Size: 35224 bytes + * Size: 34888 bytes * Original filename: /home/pi/cariboulite/driver/build/smi_stream_dev.ko */ uint8_t smi_stream_dev[] = { 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xB7, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x94, + 0x60, 0x0A, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x60, 0x62, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, + 0x60, 0x0A, 0x40, 0xB9, 0x21, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, + 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, + 0x00, 0x00, 0x80, 0x52, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, + 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, + 0xFD, 0x7B, 0xB9, 0xA9, 0x03, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, + 0x14, 0x00, 0x00, 0x90, 0xF3, 0x03, 0x02, 0xAA, 0xF5, 0x5B, 0x02, 0xA9, 0xF5, 0x03, 0x01, 0xAA, + 0x80, 0x02, 0x40, 0xF9, 0x61, 0xCC, 0x42, 0xF9, 0xE1, 0x37, 0x00, 0xF9, 0x01, 0x00, 0x80, 0xD2, + 0xFF, 0x3F, 0x00, 0xB9, 0x00, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x08, 0x00, 0x35, + 0x83, 0x02, 0x40, 0xF9, 0x60, 0x00, 0x01, 0x91, 0x66, 0x40, 0x40, 0xB9, 0x02, 0x90, 0x40, 0x29, + 0xC1, 0x00, 0x02, 0x4B, 0x9F, 0x00, 0x01, 0x6B, 0x82, 0x03, 0x00, 0x54, 0x96, 0x02, 0x00, 0x91, + 0xE0, 0x03, 0x01, 0x91, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x03, 0x00, 0x00, 0x14, + 0x25, 0x06, 0x00, 0xB5, 0x00, 0x00, 0x00, 0x94, 0xC0, 0x02, 0x40, 0xF9, 0xE1, 0x03, 0x01, 0x91, + 0x22, 0x00, 0x80, 0x52, 0x00, 0xE0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0xC3, 0x02, 0x40, 0xF9, + 0xE5, 0x03, 0x00, 0xAA, 0x60, 0x00, 0x01, 0x91, 0x66, 0x40, 0x40, 0xB9, 0x02, 0x90, 0x40, 0x29, + 0xC1, 0x00, 0x02, 0x4B, 0x9F, 0x00, 0x01, 0x6B, 0x43, 0xFE, 0xFF, 0x54, 0x60, 0xE0, 0x02, 0x91, + 0xE1, 0x03, 0x01, 0x91, 0x00, 0x00, 0x00, 0x94, 0xC3, 0x02, 0x40, 0xF9, 0x60, 0x00, 0x01, 0x91, + 0x66, 0x40, 0x40, 0xB9, 0x02, 0x90, 0x40, 0x29, 0x84, 0x00, 0x02, 0x0B, 0x22, 0x00, 0x80, 0x52, + 0x46, 0x00, 0x06, 0x4B, 0xC4, 0x00, 0x04, 0x0B, 0xE1, 0x03, 0x15, 0xAA, 0x9F, 0x00, 0x13, 0xEB, + 0xE3, 0xF3, 0x00, 0x91, 0x82, 0x90, 0x93, 0x9A, 0x00, 0x00, 0x00, 0x94, 0x13, 0x7C, 0x40, 0x93, + 0x81, 0x02, 0x40, 0xF9, 0x20, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x3F, 0x40, 0xB9, + 0x7F, 0x02, 0x00, 0x71, 0x00, 0x00, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, 0xE2, 0x37, 0x40, 0xF9, + 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, 0xA1, 0x01, 0x00, 0x54, + 0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x5B, 0x42, 0xA9, 0xFD, 0x7B, 0xC7, 0xA8, 0xBF, 0x23, 0x03, 0xD5, + 0xC0, 0x03, 0x5F, 0xD6, 0xA5, 0xFC, 0xFF, 0x34, 0x60, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, + 0x40, 0x01, 0x80, 0x92, 0xF1, 0xFF, 0xFF, 0x17, 0x40, 0x01, 0x80, 0x92, 0xEF, 0xFF, 0xFF, 0x17, + 0x00, 0x00, 0x00, 0x94, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, + 0xFD, 0x7B, 0xBC, 0xA9, 0x00, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, + 0x14, 0x00, 0x00, 0x90, 0x03, 0xCC, 0x42, 0xF9, 0xE3, 0x1F, 0x00, 0xF9, 0x03, 0x00, 0x80, 0xD2, + 0xFF, 0x37, 0x00, 0xB9, 0x80, 0x02, 0x40, 0xF9, 0x00, 0xC0, 0x01, 0x91, 0xC1, 0x03, 0x00, 0xB4, + 0xF3, 0x03, 0x01, 0xAA, 0xF5, 0x13, 0x00, 0xF9, 0xF5, 0x03, 0x02, 0xAA, 0x00, 0x00, 0x00, 0x94, + 0xA0, 0x04, 0x00, 0x35, 0x80, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x15, 0x2A, 0xE1, 0x03, 0x13, 0xAA, + 0xE3, 0xD3, 0x00, 0x91, 0x00, 0xA0, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, + 0x13, 0x7C, 0x40, 0x93, 0x20, 0xC0, 0x01, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x37, 0x40, 0xB9, + 0x7F, 0x02, 0x00, 0x71, 0xF5, 0x13, 0x40, 0xF9, 0x00, 0xA0, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, + 0xE2, 0x1F, 0x40, 0xF9, 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, + 0x81, 0x02, 0x00, 0x54, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC4, 0xA8, 0xBF, 0x23, 0x03, 0xD5, + 0xC0, 0x03, 0x5F, 0xD6, 0x00, 0x00, 0x00, 0x94, 0x80, 0x01, 0x00, 0x35, 0x81, 0x02, 0x40, 0xF9, + 0x20, 0xC0, 0x01, 0x91, 0x22, 0x28, 0x40, 0xB9, 0x22, 0x2C, 0x00, 0xB9, 0x00, 0x00, 0x00, 0x94, + 0x81, 0x02, 0x40, 0xF9, 0x22, 0x00, 0x80, 0x52, 0x00, 0x00, 0x80, 0xD2, 0x22, 0x18, 0x00, 0xB9, + 0xEB, 0xFF, 0xFF, 0x17, 0xF5, 0x13, 0x40, 0xF9, 0x60, 0x00, 0x80, 0x92, 0xE8, 0xFF, 0xFF, 0x17, + 0xF5, 0x13, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, + 0x04, 0x41, 0x38, 0xD5, 0x85, 0x2C, 0x40, 0xB9, 0xE3, 0x03, 0x00, 0xAA, 0xE0, 0x03, 0x02, 0xAA, + 0x45, 0x02, 0xA8, 0x36, 0x62, 0xDC, 0x40, 0x93, 0x62, 0x00, 0x02, 0x8A, 0x04, 0x10, 0xC0, 0xD2, + 0x84, 0x00, 0x00, 0xCB, 0x9F, 0x00, 0x02, 0xEB, 0x63, 0x01, 0x00, 0x54, 0x3F, 0x23, 0x03, 0xD5, + 0xFD, 0x7B, 0xBF, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0x63, 0xF8, 0x48, 0x92, 0xE2, 0x03, 0x00, 0xAA, + 0xE0, 0x03, 0x03, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xFD, 0x7B, 0xC1, 0xA8, 0xBF, 0x23, 0x03, 0xD5, + 0xC0, 0x03, 0x5F, 0xD6, 0xC0, 0x03, 0x5F, 0xD6, 0x84, 0x00, 0x40, 0xF9, 0xE2, 0x03, 0x03, 0xAA, + 0x9F, 0x00, 0x06, 0x72, 0xC0, 0xFD, 0xFF, 0x54, 0xEB, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0x01, 0x24, 0x40, 0xF9, 0x21, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE2, 0x03, 0x01, 0x2A, 0x42, 0x00, 0x02, 0xCA, 0x02, 0x00, 0x00, 0xB5, 0x22, 0x04, 0x80, 0x12, 0x21, 0x00, 0x02, 0x0A, 0x02, 0x24, 0x40, 0xF9, @@ -118,19 +117,19 @@ uint8_t smi_stream_dev[] = { 0x01, 0x00, 0x00, 0xB9, 0x9F, 0x3F, 0x03, 0xD5, 0x80, 0x26, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE1, 0x03, 0x00, 0x2A, 0x21, 0x00, 0x01, 0xCA, 0x01, 0x00, 0x00, 0xB5, 0x00, 0x00, 0x1D, 0x32, 0x00, 0x3C, 0x00, 0x12, 0x81, 0x26, 0x40, 0xF9, 0xBF, 0x32, 0x03, 0xD5, - 0x20, 0x00, 0x00, 0xB9, 0x9F, 0x3F, 0x03, 0xD5, 0x01, 0x00, 0x00, 0x90, 0x60, 0xE2, 0x00, 0x91, + 0x20, 0x00, 0x00, 0xB9, 0x9F, 0x3F, 0x03, 0xD5, 0x01, 0x00, 0x00, 0x90, 0x60, 0xA2, 0x00, 0x91, 0xC3, 0xFF, 0xBF, 0x12, 0x21, 0x00, 0x40, 0xF9, 0x3F, 0x20, 0x00, 0xB9, 0x02, 0x84, 0x40, 0x29, - 0x64, 0x3A, 0x40, 0xB9, 0x21, 0x00, 0x02, 0x0B, 0x62, 0xE2, 0x40, 0xB9, 0x21, 0x00, 0x04, 0x4B, - 0x21, 0x04, 0x00, 0x11, 0x3F, 0x00, 0x03, 0x6B, 0x88, 0x03, 0x00, 0x54, 0x60, 0xE6, 0x40, 0xB9, - 0x00, 0x04, 0x00, 0x11, 0x60, 0xE6, 0x00, 0xB9, 0x21, 0x85, 0x8B, 0x52, 0x00, 0x85, 0x8B, 0x52, + 0x64, 0x2A, 0x40, 0xB9, 0x21, 0x00, 0x02, 0x0B, 0x62, 0xD2, 0x40, 0xB9, 0x21, 0x00, 0x04, 0x4B, + 0x21, 0x04, 0x00, 0x11, 0x3F, 0x00, 0x03, 0x6B, 0x88, 0x03, 0x00, 0x54, 0x60, 0xD6, 0x40, 0xB9, + 0x00, 0x04, 0x00, 0x11, 0x60, 0xD6, 0x00, 0xB9, 0x21, 0x85, 0x8B, 0x52, 0x00, 0x85, 0x8B, 0x52, 0xE1, 0x51, 0xB8, 0x72, 0xE0, 0x51, 0xA0, 0x72, 0x42, 0x7C, 0x01, 0x1B, 0x42, 0x08, 0x82, 0x13, 0x5F, 0x00, 0x00, 0x6B, 0x09, 0x03, 0x00, 0x54, 0x80, 0xA2, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, - 0x20, 0x00, 0x80, 0x52, 0x60, 0xA2, 0x03, 0x39, 0x22, 0x00, 0x80, 0x52, 0x60, 0x22, 0x03, 0x91, - 0xE1, 0x03, 0x02, 0x2A, 0x03, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 0x60, 0xE2, 0x40, 0xB9, - 0x00, 0x04, 0x00, 0x11, 0x60, 0xE2, 0x00, 0xB9, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, + 0x20, 0x00, 0x80, 0x52, 0x60, 0x62, 0x03, 0x39, 0x22, 0x00, 0x80, 0x52, 0x60, 0xE2, 0x02, 0x91, + 0xE1, 0x03, 0x02, 0x2A, 0x03, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 0x60, 0xD2, 0x40, 0xB9, + 0x00, 0x04, 0x00, 0x11, 0x60, 0xD2, 0x00, 0xB9, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x83, 0x62, 0x40, 0xF9, 0x41, 0x04, 0x6F, 0xD3, - 0x42, 0x00, 0xA0, 0x52, 0x61, 0x00, 0x01, 0x8B, 0x00, 0x00, 0x00, 0x94, 0x62, 0xE2, 0x40, 0xB9, - 0xE2, 0xFF, 0xFF, 0x17, 0x62, 0xE6, 0x40, 0xB9, 0x01, 0x00, 0x00, 0x90, 0x83, 0xAE, 0x40, 0xB9, + 0x42, 0x00, 0xA0, 0x52, 0x61, 0x00, 0x01, 0x8B, 0x00, 0x00, 0x00, 0x94, 0x62, 0xD2, 0x40, 0xB9, + 0xE2, 0xFF, 0xFF, 0x17, 0x62, 0xD6, 0x40, 0xB9, 0x01, 0x00, 0x00, 0x90, 0x83, 0xAE, 0x40, 0xB9, 0x21, 0x00, 0x00, 0x91, 0x60, 0x02, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xE3, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0x01, 0x00, 0x00, 0x90, 0xFD, 0x7B, 0xBF, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0x20, 0x00, 0x40, 0xF9, 0x00, 0x04, 0x40, 0xF9, @@ -166,18 +165,18 @@ uint8_t smi_stream_dev[] = { 0xE1, 0x03, 0x00, 0x2A, 0x21, 0x00, 0x01, 0xCA, 0x01, 0x00, 0x00, 0xB5, 0x00, 0x00, 0x1D, 0x32, 0x00, 0x3C, 0x00, 0x12, 0xA1, 0x26, 0x40, 0xF9, 0xBF, 0x32, 0x03, 0xD5, 0x20, 0x00, 0x00, 0xB9, 0x9F, 0x3F, 0x03, 0xD5, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x40, 0xF9, 0x1F, 0x20, 0x00, 0xB9, - 0x82, 0xE2, 0x40, 0xB9, 0x80, 0x42, 0x01, 0x91, 0x83, 0x52, 0x40, 0xB9, 0xC4, 0xFF, 0xBF, 0x12, - 0x42, 0x04, 0x00, 0x11, 0x82, 0xE2, 0x00, 0xB9, 0x01, 0x04, 0x40, 0xB9, 0x53, 0x04, 0x6F, 0xD3, + 0x82, 0xD2, 0x40, 0xB9, 0x80, 0x02, 0x01, 0x91, 0x83, 0x42, 0x40, 0xB9, 0xC4, 0xFF, 0xBF, 0x12, + 0x42, 0x04, 0x00, 0x11, 0x82, 0xD2, 0x00, 0xB9, 0x01, 0x04, 0x40, 0xB9, 0x53, 0x04, 0x6F, 0xD3, 0xB6, 0x62, 0x40, 0xF9, 0x63, 0x00, 0x01, 0x4B, 0xC1, 0x02, 0x13, 0x8B, 0x7F, 0x00, 0x04, 0x6B, - 0x28, 0x03, 0x00, 0x54, 0x80, 0xE6, 0x40, 0xB9, 0x00, 0x04, 0x00, 0x11, 0x80, 0xE6, 0x00, 0xB9, + 0x28, 0x03, 0x00, 0x54, 0x80, 0xD6, 0x40, 0xB9, 0x00, 0x04, 0x00, 0x11, 0x80, 0xD6, 0x00, 0xB9, 0xE1, 0xD1, 0x8B, 0x52, 0xE0, 0x42, 0x8D, 0x52, 0x21, 0x63, 0xBB, 0x72, 0xC0, 0x49, 0xA0, 0x72, 0x42, 0x7C, 0x01, 0x1B, 0x5F, 0x00, 0x00, 0x6B, 0xE9, 0x02, 0x00, 0x54, 0xA0, 0xA2, 0x02, 0x91, - 0x00, 0x00, 0x00, 0x94, 0x20, 0x00, 0x80, 0x52, 0x80, 0xA6, 0x03, 0x39, 0x22, 0x00, 0x80, 0x52, - 0x80, 0x22, 0x03, 0x91, 0xE1, 0x03, 0x02, 0x2A, 0x03, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, + 0x00, 0x00, 0x00, 0x94, 0x20, 0x00, 0x80, 0x52, 0x80, 0x66, 0x03, 0x39, 0x22, 0x00, 0x80, 0x52, + 0x80, 0xE2, 0x02, 0x91, 0xE1, 0x03, 0x02, 0x2A, 0x03, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x5B, 0x42, 0xA9, 0xFD, 0x7B, 0xC3, 0xA8, 0xBF, 0x23, 0x03, 0xD5, - 0xC0, 0x03, 0x5F, 0xD6, 0x42, 0x00, 0xA0, 0x52, 0x00, 0x00, 0x00, 0x94, 0x82, 0xE2, 0x40, 0xB9, + 0xC0, 0x03, 0x5F, 0xD6, 0x42, 0x00, 0xA0, 0x52, 0x00, 0x00, 0x00, 0x94, 0x82, 0xD2, 0x40, 0xB9, 0xE8, 0xFF, 0xFF, 0x17, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, - 0xBF, 0xFF, 0xFF, 0x17, 0xC4, 0x6A, 0x73, 0xB8, 0x01, 0x00, 0x00, 0x90, 0x82, 0xE6, 0x40, 0xB9, + 0xBF, 0xFF, 0xFF, 0x17, 0xC4, 0x6A, 0x73, 0xB8, 0x01, 0x00, 0x00, 0x90, 0x82, 0xD6, 0x40, 0xB9, 0x21, 0x00, 0x00, 0x91, 0xA3, 0xAE, 0x40, 0xB9, 0x80, 0x02, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xE3, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBE, 0xA9, 0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, @@ -187,8 +186,8 @@ uint8_t smi_stream_dev[] = { 0x20, 0x00, 0x3F, 0xD6, 0xC0, 0x00, 0x00, 0x35, 0x80, 0x02, 0x40, 0xF9, 0x01, 0xA8, 0x40, 0xF9, 0x61, 0x00, 0x00, 0xB4, 0xE0, 0x03, 0x14, 0xAA, 0x20, 0x00, 0x3F, 0xD6, 0x60, 0x06, 0x40, 0xF9, 0x00, 0xE0, 0x05, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0xB1, 0xFE, 0xFF, 0x97, - 0x60, 0x06, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x7F, 0xAA, 0x03, 0x39, 0x7F, 0xB2, 0x03, 0x39, - 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, + 0x60, 0x06, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x7F, 0xB6, 0x01, 0x79, 0xF3, 0x53, 0x41, 0xA9, + 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBC, 0xA9, 0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0x21, 0x00, 0x00, 0x91, 0x22, 0x00, 0x80, 0x52, 0xF3, 0x53, 0x01, 0xA9, 0xF3, 0x03, 0x00, 0x2A, 0xF5, 0x5B, 0x02, 0xA9, 0x20, 0xCC, 0x40, 0xB9, @@ -199,180 +198,179 @@ uint8_t smi_stream_dev[] = { 0xC0, 0x03, 0x5F, 0xD6, 0x23, 0xC8, 0x40, 0xB9, 0x42, 0x20, 0xC3, 0x1A, 0x56, 0x00, 0x00, 0x2A, 0xF3, 0xFF, 0xFF, 0x17, 0x00, 0x00, 0x40, 0xF9, 0xE3, 0x03, 0x16, 0x2A, 0xE2, 0x03, 0x13, 0x2A, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, - 0x00, 0x00, 0x03, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x78, 0x40, 0xB9, + 0x00, 0xC0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x68, 0x40, 0xB9, 0x3F, 0x00, 0x13, 0x6B, 0xC0, 0x01, 0x00, 0x54, 0xF7, 0x1B, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x75, 0xFD, 0xFF, 0x97, - 0x15, 0x00, 0x1E, 0x12, 0xC0, 0x01, 0x10, 0x36, 0xE0, 0x02, 0x03, 0x91, 0x55, 0x01, 0x80, 0x12, - 0x00, 0x00, 0x00, 0x94, 0xF7, 0x1B, 0x40, 0xF9, 0xDD, 0xFF, 0xFF, 0x17, 0x00, 0x00, 0x03, 0x91, + 0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x79, 0xFD, 0xFF, 0x97, + 0x15, 0x00, 0x1E, 0x12, 0xC0, 0x01, 0x10, 0x36, 0xE0, 0xC2, 0x02, 0x91, 0x55, 0x01, 0x80, 0x12, + 0x00, 0x00, 0x00, 0x94, 0xF7, 0x1B, 0x40, 0xF9, 0xDD, 0xFF, 0xFF, 0x17, 0x00, 0xC0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xD5, 0xFF, 0xFF, 0x17, 0xE0, 0x06, 0x40, 0xF9, - 0xFF, 0x7A, 0x00, 0xB9, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x13, 0x02, 0x00, 0x34, + 0xFF, 0x6A, 0x00, 0xB9, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x13, 0x02, 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0x03, 0x14, 0xAA, 0x01, 0x00, 0x00, 0x90, 0xB3, 0x02, 0x80, 0x12, 0x21, 0x00, 0x00, 0x91, + 0x00, 0x00, 0x00, 0x94, 0xA0, 0x00, 0x00, 0x14, 0x1F, 0x00, 0x01, 0x6B, 0x21, 0x01, 0x00, 0x54, + 0x1F, 0x04, 0x00, 0x31, 0xE0, 0x00, 0x00, 0x54, 0xE0, 0x03, 0x14, 0xAA, 0x01, 0x00, 0x00, 0x90, + 0xB3, 0x02, 0x80, 0x12, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x96, 0x00, 0x00, 0x14, + 0x80, 0x26, 0x41, 0xF9, 0xE0, 0x00, 0x00, 0xB5, 0xE0, 0x03, 0x14, 0xAA, 0x01, 0x00, 0x00, 0x90, + 0xB3, 0x02, 0x80, 0x12, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x8E, 0x00, 0x00, 0x14, + 0x01, 0x00, 0x00, 0x90, 0xE5, 0x63, 0x01, 0x91, 0x21, 0x00, 0x00, 0x91, 0x04, 0x00, 0x80, 0x52, + 0x03, 0x00, 0x80, 0x52, 0x02, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 0x60, 0x00, 0x00, 0x35, + 0xF7, 0x2F, 0x40, 0xF9, 0xF7, 0x00, 0x00, 0xB5, 0xE0, 0x03, 0x14, 0xAA, 0x01, 0x00, 0x00, 0x90, + 0xB3, 0x00, 0x80, 0x12, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x7E, 0x00, 0x00, 0x14, + 0x16, 0x00, 0x00, 0x90, 0xE0, 0x03, 0x14, 0xAA, 0x02, 0xB8, 0x81, 0x52, 0x01, 0x1C, 0x80, 0xD2, + 0x00, 0x00, 0x00, 0x94, 0xC0, 0x02, 0x00, 0xF9, 0xF3, 0x03, 0x00, 0xAA, 0xD5, 0x02, 0x00, 0x91, + 0x40, 0x0E, 0x00, 0xB4, 0xE0, 0x03, 0x17, 0xAA, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x00, 0xF9, + 0xC0, 0x02, 0x40, 0xF9, 0x01, 0x04, 0x40, 0xF9, 0xC1, 0x0D, 0x00, 0xB4, 0x14, 0x00, 0x00, 0xF9, + 0x1A, 0x00, 0x00, 0x90, 0x5A, 0x03, 0x00, 0x91, 0xA0, 0x22, 0x00, 0x91, 0xE3, 0x03, 0x1A, 0xAA, + 0x22, 0x00, 0x80, 0x52, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x00, 0x01, 0x00, 0x34, + 0xC0, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x73, 0x01, 0x80, 0x12, 0x21, 0x00, 0x00, 0x91, + 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x5F, 0x00, 0x00, 0x14, 0xB7, 0x62, 0x00, 0x91, + 0x01, 0x00, 0x00, 0x90, 0xE0, 0x03, 0x17, 0xAA, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, + 0x18, 0x00, 0x00, 0x90, 0xA1, 0x0A, 0x40, 0xB9, 0x18, 0x03, 0x00, 0x91, 0xE0, 0x03, 0x17, 0xAA, + 0x22, 0x00, 0x80, 0x52, 0xF8, 0x22, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xF3, 0x03, 0x00, 0x2A, + 0x40, 0x01, 0x00, 0x34, 0xC0, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, + 0x73, 0x01, 0x80, 0x12, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x0A, 0x40, 0xB9, + 0x21, 0x00, 0x80, 0x52, 0x0F, 0x00, 0x00, 0x14, 0xB9, 0x02, 0x02, 0x91, 0xE0, 0x03, 0x18, 0xAA, + 0xE1, 0x03, 0x1A, 0xAA, 0xE2, 0x03, 0x19, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x0A, 0x00, 0xF9, + 0xF8, 0x03, 0x00, 0xAA, 0x1F, 0x04, 0x40, 0xB1, 0x89, 0x01, 0x00, 0x54, 0xE0, 0x03, 0x17, 0xAA, + 0x00, 0x00, 0x00, 0x94, 0xA0, 0x0A, 0x40, 0xB9, 0xF3, 0x03, 0x18, 0x2A, 0x21, 0x00, 0x80, 0x52, + 0x00, 0x00, 0x00, 0x94, 0xE0, 0x03, 0x14, 0xAA, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, + 0x00, 0x00, 0x00, 0x94, 0x34, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x91, + 0x00, 0x00, 0x00, 0x94, 0xA2, 0x0A, 0x40, 0xB9, 0x04, 0x00, 0x00, 0x90, 0xA0, 0x0A, 0x40, 0xF9, + 0x84, 0x00, 0x00, 0x91, 0x03, 0x00, 0x80, 0xD2, 0x01, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, + 0x1F, 0x04, 0x40, 0xB1, 0x29, 0x01, 0x00, 0x54, 0xF3, 0x03, 0x00, 0x2A, 0xA0, 0x0A, 0x40, 0xF9, + 0x00, 0x00, 0x00, 0x94, 0xE0, 0x03, 0x17, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x0A, 0x40, 0xB9, + 0x21, 0x00, 0x80, 0x52, 0xE7, 0xFF, 0xFF, 0x17, 0xC3, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x19, 0xAA, + 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x60, 0xE0, 0x02, 0x91, 0x7F, 0x0C, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xC3, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x19, 0xAA, 0x01, 0x00, 0x00, 0x90, - 0x21, 0x00, 0x00, 0x91, 0x60, 0x00, 0x02, 0x91, 0x7F, 0xE8, 0x00, 0xB9, 0x7F, 0xD8, 0x01, 0x79, + 0x21, 0x00, 0x00, 0x91, 0x60, 0xC0, 0x01, 0x91, 0x7F, 0xD8, 0x00, 0xB9, 0x7F, 0x70, 0x03, 0x39, 0x00, 0x00, 0x00, 0x94, 0xC0, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x19, 0xAA, 0x01, 0x00, 0x00, 0x90, - 0x21, 0x00, 0x00, 0x91, 0x00, 0x80, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0xC2, 0x02, 0x40, 0xF9, - 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x40, 0x00, 0x40, 0xF9, 0x5F, 0xC0, 0x00, 0xB9, + 0x21, 0x00, 0x00, 0x91, 0x00, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0xC2, 0x02, 0x40, 0xF9, + 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x40, 0x00, 0x40, 0xF9, 0x5F, 0xB0, 0x00, 0xB9, 0x00, 0x00, 0x00, 0x94, 0x04, 0x00, 0x00, 0x14, 0x73, 0x01, 0x80, 0x12, 0x02, 0x00, 0x00, 0x14, 0x93, 0x40, 0x80, 0x12, 0x00, 0x41, 0x38, 0xD5, 0xE1, 0x57, 0x40, 0xF9, 0x02, 0xCC, 0x42, 0xF9, 0x21, 0x00, 0x02, 0xEB, 0x02, 0x00, 0x80, 0xD2, 0x40, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00, 0x94, @@ -382,7 +380,7 @@ uint8_t smi_stream_dev[] = { 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 0xF3, 0x03, 0x00, 0xAA, 0xF5, 0x5B, 0x02, 0xA9, 0xF7, 0x63, 0x03, 0xA9, 0xF7, 0x03, 0x02, 0xAA, 0xF8, 0x03, 0x01, 0x2A, 0xF9, 0x23, 0x00, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0x60, 0x06, 0x40, 0xF9, 0x21, 0x00, 0x80, 0x52, 0x61, 0xAA, 0x03, 0x39, 0x00, 0x00, 0x00, 0x94, + 0x60, 0x06, 0x40, 0xF9, 0x21, 0x00, 0x80, 0x52, 0x61, 0x6A, 0x03, 0x39, 0x00, 0x00, 0x00, 0x94, 0x61, 0x06, 0x40, 0xF9, 0xE0, 0x00, 0x00, 0x34, 0x20, 0x00, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x80, 0x12, 0xAF, 0x00, 0x00, 0x14, 0x20, 0x24, 0x40, 0xF9, 0x00, 0x10, 0x00, 0x91, 0xBF, 0x32, 0x03, 0xD5, 0x1F, 0x00, 0x00, 0xB9, @@ -411,7 +409,7 @@ uint8_t smi_stream_dev[] = { 0x20, 0x00, 0x80, 0x12, 0x51, 0x00, 0x00, 0x14, 0xBF, 0x32, 0x03, 0xD5, 0x14, 0x00, 0x00, 0xB9, 0x9F, 0x3F, 0x03, 0xD5, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0x00, 0xE0, 0x05, 0x91, 0x00, 0x00, 0x00, 0x94, 0x74, 0x06, 0x40, 0xF9, - 0x7F, 0x72, 0x00, 0xF9, 0x96, 0xE2, 0x05, 0x91, 0xE0, 0x03, 0x16, 0xAA, 0x00, 0x00, 0x00, 0x94, + 0x7F, 0x6A, 0x00, 0xF9, 0x96, 0xE2, 0x05, 0x91, 0xE0, 0x03, 0x16, 0xAA, 0x00, 0x00, 0x00, 0x94, 0x80, 0x2E, 0x40, 0xF9, 0x81, 0x6E, 0x40, 0xF9, 0xE0, 0x00, 0x00, 0xB5, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x34, 0x00, 0x80, 0x52, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x17, 0x00, 0x00, 0x14, 0x02, 0x00, 0x40, 0xF9, 0x22, 0xFF, 0xFF, 0xB4, 0x46, 0x88, 0x40, 0xF9, @@ -433,17 +431,15 @@ uint8_t smi_stream_dev[] = { 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBD, 0xA9, 0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0xF5, 0x13, 0x00, 0xF9, 0x15, 0x00, 0x00, 0x90, 0xF3, 0x53, 0x01, 0xA9, 0x21, 0x00, 0x00, 0x91, 0xA2, 0x02, 0x40, 0xF9, - 0x14, 0x4C, 0x40, 0xB9, 0x40, 0x00, 0x40, 0xF9, 0x94, 0x4E, 0x00, 0x12, 0xE2, 0x03, 0x14, 0x2A, - 0x00, 0x00, 0x00, 0x94, 0x34, 0x01, 0x00, 0x34, 0xA0, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x14, 0x2A, + 0x13, 0x4C, 0x40, 0xB9, 0x40, 0x00, 0x40, 0xF9, 0x73, 0x4E, 0x00, 0x12, 0xE2, 0x03, 0x13, 0x2A, + 0x00, 0x00, 0x00, 0x94, 0x33, 0x01, 0x00, 0x34, 0xA0, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x13, 0x2A, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0xA0, 0x00, 0x80, 0x12, 0x19, 0x00, 0x00, 0x14, 0x00, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, - 0xA0, 0x02, 0x40, 0xF9, 0xF3, 0x03, 0x15, 0xAA, 0x00, 0x14, 0x40, 0xF9, 0x40, 0x00, 0x00, 0xB4, - 0x00, 0x00, 0x00, 0x94, 0x60, 0x02, 0x40, 0xF9, 0x00, 0x18, 0x40, 0xF9, 0x40, 0x00, 0x00, 0xB4, - 0x00, 0x00, 0x00, 0x94, 0x60, 0x02, 0x40, 0xF9, 0x00, 0x34, 0x40, 0xF9, 0x40, 0x00, 0x00, 0xB4, - 0x00, 0x00, 0x00, 0x94, 0x60, 0x02, 0x40, 0xF9, 0x00, 0x38, 0x40, 0xF9, 0x40, 0x00, 0x00, 0xB4, - 0x00, 0x00, 0x00, 0x94, 0x61, 0x02, 0x40, 0xF9, 0x00, 0x00, 0x80, 0x52, 0x3F, 0x14, 0x00, 0xB9, - 0x3F, 0xFC, 0x02, 0xA9, 0x3F, 0xFC, 0x06, 0xA9, 0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x13, 0x40, 0xF9, - 0xFD, 0x7B, 0xC3, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x21, 0xFC, 0xDF, 0x88, + 0xA0, 0x00, 0x80, 0x12, 0x10, 0x00, 0x00, 0x14, 0x00, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, + 0xA0, 0x02, 0x40, 0xF9, 0xF4, 0x03, 0x15, 0xAA, 0x00, 0x2C, 0x40, 0xF9, 0x40, 0x00, 0x00, 0xB4, + 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 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+1022,28 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0xA0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, @@ -1129,7 +1121,7 @@ uint8_t smi_stream_dev[] = { 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAB, 0x04, 0x00, 0x00, 0x01, 0x00, 0x14, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB8, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCA, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1153,7 +1145,7 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1705,7 +1690,7 @@ uint8_t smi_stream_dev[] = { 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, + 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, @@ -1773,7 +1758,7 @@ uint8_t smi_stream_dev[] = { 0x13, 0x01, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1B, 0x01, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1B, 0x01, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1786,9 +1771,9 @@ uint8_t smi_stream_dev[] = { 0x1C, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00, 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smi_stream_dev[] = { 0xA0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xBC, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x99, 0x00, 0x00, 0x00, + 0xBC, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x98, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x98, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xE8, 0x02, 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- .tm_min = 58, - .tm_hour = 22, + .tm_sec = 6, + .tm_min = 8, + .tm_hour = 23, .tm_mday = 14, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ @@ -38,394 +38,394 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xCA, 0x13, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xFE, 0x2D, 0x01, 0x06, 0x00, }; #ifdef __cplusplus