diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c index ef915b6..70d9465 100644 --- a/driver/smi_stream_dev.c +++ b/driver/smi_stream_dev.c @@ -152,6 +152,7 @@ static const char *const ioctl_names[] = static void write_smi_reg(struct bcm2835_smi_instance *inst, u32 val, unsigned reg) { writel(val, inst->smi_regs_ptr + reg); + mb(); } /***************************************************************************/ @@ -211,46 +212,50 @@ static inline int smi_is_active(struct bcm2835_smi_instance *inst) return read_smi_reg(inst, SMICS) & SMICS_ACTIVE; } -static long set_state(smi_stream_state_en new_state) +static int set_state(smi_stream_state_en new_state) { + int ret = -1; unsigned int new_address = calc_address_from_state(new_state); + if (inst == NULL) return 0; + dev_info(inst->dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); spin_lock(&inst->state_lock); - - if(new_state == inst->state) + + // in any case if we want to change the state + // then stop the current transfer and update the new state. + if(new_state != inst->state) { - spin_unlock(&inst->state_lock); - return 0; - } - - dev_info(inst->dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); - - if(inst->state != smi_stream_idle) - { - //exiting from current state - if (inst->state == smi_stream_tx_channel) - { - transfer_thread_stop(inst); - } - else - { - transfer_thread_stop(inst); - } + // stop the transter + transfer_thread_stop(inst); + if(smi_is_active(inst->smi_inst)) { spin_unlock(&inst->state_lock); - return -EAGAIN; + return -EAGAIN; } + + // update the state from current state inst->state = smi_stream_idle; - bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + + ret = 0; + //now state is idle } - //now state is idle - - if(new_state != smi_stream_idle) + // else if the state is the same, do nothing + else { - int ret = -1; - bcm2835_smi_set_address(inst->smi_inst, new_address); + spin_unlock(&inst->state_lock); + dev_info(inst->dev, "State is the same as before"); + return 0; + } + + + // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer + if(new_state != smi_stream_idle) + { + bcm2835_smi_set_address(inst->smi_inst, new_address); + if (new_state == smi_stream_tx_channel) { ret = transfer_thread_init(inst,DMA_MEM_TO_DEV,stream_smi_write_dma_callback); @@ -260,21 +265,24 @@ static long set_state(smi_stream_state_en new_state) ret = transfer_thread_init(inst,DMA_DEV_TO_MEM,stream_smi_read_dma_callback); } - if(!ret) + // if starting the transfer succeeded update the state + if (!ret) { - inst->state = new_state; + inst->state = new_state; } + // if failed, go back to idle else { bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + inst->state = smi_stream_idle; } } - - - + mb(); spin_unlock(&inst->state_lock); - return 0; + + // return the success + return ret; } /***************************************************************************/ @@ -297,25 +305,26 @@ static inline int smi_enabled(struct bcm2835_smi_instance *inst) static int smi_disable_sync(struct bcm2835_smi_instance *smi_inst) { - int smics_temp; + int smics_temp = 0; int success = 0; int errors = 0; - dev_info(inst->dev, "smi disable sync enter"); + //dev_info(inst->dev, "smi disable sync enter"); /* Disable the peripheral: */ smics_temp = read_smi_reg(smi_inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); write_smi_reg(smi_inst, smics_temp, SMICS); + // wait for the ENABLE to go low - BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 1000000U, success); + BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 100000U, success); if (!success) { - dev_info(inst->dev, "errore disable. %u %08X",smi_enabled(smi_inst),read_smi_reg(smi_inst, SMICS)); + //dev_info(inst->dev, "error disable sync. %u %08X", smi_enabled(smi_inst), read_smi_reg(smi_inst, SMICS)); errors = -1; } - print_smil_registers(); - dev_info(inst->dev, "smi disable sync exit"); + //print_smil_registers(); + //dev_info(inst->dev, "smi disable sync exit"); return errors; @@ -323,7 +332,7 @@ static int smi_disable_sync(struct bcm2835_smi_instance *smi_inst) static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers) { - int smics_temp; + int smics_temp = 0; //print_smil_registers_ext("refresh 1"); write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting //print_smil_registers_ext("refresh 2"); @@ -339,34 +348,38 @@ static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int n /***************************************************************************/ static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, enum dma_transfer_direction dma_dir,int num_transfers) { - int smics_temp; + int smics_temp = 0; int success = 0; - dev_info(inst->dev, "smi_init_programmed_read"); + dev_info(inst->dev, "smi_init_programmed_transfer"); print_smil_registers_ext("init 1"); - write_smi_reg(inst->smi_inst, 0, SMIL); + write_smi_reg(inst->smi_inst, 0x0, SMIL); + print_smil_registers_ext("init 2"); smics_temp = read_smi_reg(smi_inst, SMICS); + /* Program the transfer count: */ write_smi_reg(smi_inst, num_transfers, SMIL); -print_smil_registers_ext("init 3"); + + print_smil_registers_ext("init 3"); + /* re-enable and start: */ smics_temp |= SMICS_CLEAR; smics_temp |= SMICS_ENABLE; if(dma_dir == DMA_MEM_TO_DEV) { - smics_temp |= SMICS_WRITE; + smics_temp |= SMICS_WRITE; } write_smi_reg(smi_inst, smics_temp, SMICS); -print_smil_registers_ext("init 4"); - + print_smil_registers_ext("init 4"); /* IO barrier - to be sure that the last request have been dispatched in the correct order */ mb(); + // busy wait as long as the transaction is active (taking place) BUSY_WAIT_WHILE_TIMEOUT(smi_is_active(smi_inst), 1000000U, success); if (!success) @@ -379,6 +392,7 @@ print_smil_registers_ext("init 4"); // Clear the FIFO (reset it to zero contents) write_smi_reg(smi_inst, smics_temp, SMICS); print_smil_registers_ext("init 5"); + return 0; } @@ -570,7 +584,7 @@ static void stream_smi_read_dma_callback(void *param) } else { - inst->counter_missed++; + inst->counter_missed++; } if(!(inst->current_read_chunk % 100 )) @@ -594,17 +608,18 @@ static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) int i; for(i = 0; i < 1000; i++) { - if(!smi_is_active(smi_inst)) - break; - udelay(1); + if(!smi_is_active(smi_inst)) + { + break; + } + udelay(1); } if(i == 1000) { - print_smil_registers_ext("write dma callback errore 1000"); + print_smil_registers_ext("write dma callback error 1000"); } smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - } } @@ -685,13 +700,14 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe int ret; int success; - dev_info(inst->dev, "Enterred reader thread"); + dev_info(inst->dev, "Starting cyclic transfer"); inst->reader_thread_running = true; /* Disable the peripheral: */ if(smi_disable_sync(inst->smi_inst)) { - return -1; + dev_err(inst->smi_inst->dev, "smi_disable_sync failed"); + return -1; } write_smi_reg(inst->smi_inst, 0, SMIL); @@ -702,14 +718,13 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe if (ret != 0) { spin_unlock(&inst->smi_inst->transaction_lock); - dev_err(inst->smi_inst->dev, "smi_init_programmed_read returned %d", ret); + dev_err(inst->smi_inst->dev, "smi_init_programmed_transfer returned %d", ret); smi_disable_sync(inst->smi_inst); return -2; - } else { - spin_unlock(&inst->smi_inst->transaction_lock); + spin_unlock(&inst->smi_inst->transaction_lock); } inst->current_read_chunk = 0; inst->counter_missed = 0; @@ -738,18 +753,18 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe void transfer_thread_stop(struct bcm2835_smi_dev_instance *inst) { - int errors = 0; - dev_info(inst->dev, "Reader state became idle, terminating dma %u %u", (inst->address_changed) ,errors); + //int errors = 0; + //dev_info(inst->dev, "Reader state became idle, terminating dma %u %u", (inst->address_changed) ,errors); print_smil_registers_ext("thread stop 0"); spin_lock(&inst->smi_inst->transaction_lock); dmaengine_terminate_sync(inst->smi_inst->dma_chan); spin_unlock(&inst->smi_inst->transaction_lock); - dev_info(inst->dev, "Reader state became idle, terminating smi transaction"); + //dev_info(inst->dev, "Reader state became idle, terminating smi transaction"); smi_disable_sync(inst->smi_inst); bcm2835_smi_set_regs_from_settings(inst->smi_inst); - dev_info(inst->dev, "Left reader thread"); + //dev_info(inst->dev, "Left reader thread"); inst->reader_thread_running = false; inst->reader_waiting_sema = false; return ; @@ -802,8 +817,6 @@ static int smi_stream_open(struct inode *inode, struct file *file) // when file is being openned, stream state is still idle set_state(smi_stream_idle); - - inst->address_changed = 0; return 0; } @@ -845,7 +858,7 @@ static ssize_t smi_stream_read_file_fifo(struct file *file, char __user *buf, si int ret = 0; unsigned int copied = 0; - if (buf == NULL) + if (buf == NULL) { //dev_info(inst->dev, "Flushing internal rx_kfifo"); if (mutex_lock_interruptible(&inst->read_lock)) @@ -858,22 +871,13 @@ static ssize_t smi_stream_read_file_fifo(struct file *file, char __user *buf, si return 0; } - if (kfifo_is_empty(&inst->rx_fifo)) - { - int ret = wait_event_interruptible(inst->poll_event, !kfifo_is_empty(&inst->rx_fifo) ); - if (ret) - return ret; - } - - + if (mutex_lock_interruptible(&inst->read_lock)) { - if (mutex_lock_interruptible(&inst->read_lock)) - { - return -EINTR; - } - ret = kfifo_to_user(&inst->rx_fifo, buf, count, &copied); - mutex_unlock(&inst->read_lock); + return -EINTR; } + ret = kfifo_to_user(&inst->rx_fifo, buf, count, &copied); + mutex_unlock(&inst->read_lock); + return ret < 0 ? ret : (ssize_t)copied; } @@ -896,9 +900,7 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr { mutex_unlock(&inst->write_lock); return -EAGAIN; - } - - + } } // check how many bytes are available in the tx fifo diff --git a/firmware/Makefile b/firmware/Makefile index 7ab5f9c..6a2c314 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -5,7 +5,7 @@ pcf_file = ./io.pcf top.bin: yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v #nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc - nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 64 --parallel-refine --opt-timing --timing-allow-fail + nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 1 --timing-allow-fail #nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui icepack $(filename).asc $(filename).bin diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index acea638..5dcc3c6 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -17,16 +17,16 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2023-07-03 - * Time: 12:09:44 + * Date: 2024-03-14 + * Time: 22:58:51 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 44, - .tm_min = 9, - .tm_hour = 12, - .tm_mday = 3, - .tm_mon = 6, /* +1 */ - .tm_year = 123, /* +1900 */ + .tm_sec = 51, + .tm_min = 58, + .tm_hour = 22, + .tm_mday = 14, + .tm_mon = 2, /* +1 */ + .tm_year = 124, /* +1900 */ }; /* @@ -38,379 +38,379 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x02, 0x30, 0x00, 0x00, 0x80, 0x08, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x0C, 0x00, 0x00, 0x20, 0x01, + 0x40, 0x01, 0xF0, 0x00, 0x00, 0x80, 0x00, 0x04, 0x0F, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x98, 0xD0, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xCA, 0x13, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/firmware/io_ctrl.v b/firmware/io_ctrl.v index 82bf4b4..7fb3af2 100644 --- a/firmware/io_ctrl.v +++ b/firmware/io_ctrl.v @@ -15,7 +15,7 @@ module io_ctrl input [3:0] i_config, output o_led0, output o_led1, - output [7:0] o_pmod, + output [3:0] o_pmod, // Analog interfaces output o_mixer_fm, @@ -26,7 +26,7 @@ module io_ctrl output o_tr_vc2, output o_shdn_tx_lna, output o_shdn_rx_lna, - output o_mixer_en + output o_mixer_en ); @@ -73,7 +73,7 @@ module io_ctrl reg led0_state; reg led1_state; reg [7:0] pmod_dir_state; - reg [7:0] pmod_state; + reg [3:0] pmod_state; reg [7:0] rf_pin_state; reg mixer_en_state; @@ -146,7 +146,8 @@ module io_ctrl //---------------------------------------------- ioc_pmod_val: begin - o_data_out <= pmod_state; + o_data_out[3:0] <= pmod_state; + o_data_out[7:4] <= 4'b0000; end //---------------------------------------------- @@ -191,7 +192,7 @@ module io_ctrl //---------------------------------------------- ioc_pmod_val: begin - pmod_state <= i_data_in; + pmod_state[3:0] <= i_data_in[3:0]; end //---------------------------------------------- diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v index 520dc39..dba0505 100644 --- a/firmware/smi_ctrl.v +++ b/firmware/smi_ctrl.v @@ -29,7 +29,7 @@ module smi_ctrl output o_smi_write_req, input i_smi_test, output o_channel, - output o_dir, + output o_dir, // TX CONDITIONAL output reg o_cond_tx, diff --git a/firmware/sys_ctrl.v b/firmware/sys_ctrl.v index 4c3c85c..10de7e6 100644 --- a/firmware/sys_ctrl.v +++ b/firmware/sys_ctrl.v @@ -16,6 +16,16 @@ module sys_ctrl output o_debug_smi_test, output o_debug_loopback_tx, output [3:0] o_tx_sample_gap, + + output o_rx_sync_type09, + output o_rx_sync_type24, + output o_tx_sync_type09, + output o_tx_sync_type24, + + output o_rx_sync_09, + output o_rx_sync_24, + output o_tx_sync_09, + output o_tx_sync_24, ); // MODULE SPECIFIC IOC LIST @@ -26,7 +36,8 @@ module sys_ctrl ioc_manu_id = 5'b00010, // read only ioc_error_state = 5'b00011, // read only ioc_debug_modes = 5'b00101, // write only - ioc_tx_sample_gap = 5'b00110; // read / write + ioc_tx_sample_gap = 5'b00110, // read / write + ioc_soft_sync = 5'b00111; // write only // MODULE SPECIFIC PARAMS // ---------------------- @@ -40,12 +51,32 @@ module sys_ctrl reg debug_fifo_push; reg debug_fifo_pull; reg debug_smi_test; - reg debug_loopback_tx; - reg [3:0] tx_sample_gap; + reg debug_loopback_tx; + reg [3:0] tx_sample_gap; + + reg rx_sync_type09; + reg rx_sync_type24; + reg tx_sync_type09; + reg tx_sync_type24; + + reg rx_sync_09; + reg rx_sync_24; + reg tx_sync_09; + reg tx_sync_24; assign o_debug_fifo_push = debug_fifo_push; assign o_debug_fifo_pull = debug_fifo_pull; assign o_debug_smi_test = debug_smi_test; + assign o_rx_sync_type09 = rx_sync_type09; + assign o_tx_sync_type09 = tx_sync_type09; + assign o_rx_sync_type24 = rx_sync_type24; + assign o_tx_sync_type24 = tx_sync_type24; + + assign o_rx_sync_09 = rx_sync_09; + assign o_tx_sync_09 = tx_sync_09; + assign o_rx_sync_24 = rx_sync_24; + assign o_tx_sync_24 = tx_sync_24; + // MODULE MAIN PROCESS // ------------------- @@ -58,6 +89,17 @@ module sys_ctrl debug_smi_test <= 1'b0; debug_loopback_tx <= 1'b0; tx_sample_gap <= 4'd0; + + rx_sync_type09 <= 1'b0; + rx_sync_type24 <= 1'b0; + tx_sync_type09 <= 1'b0; + tx_sync_type24 <= 1'b0; + + rx_sync_09 <= 1'b0; + tx_sync_09 <= 1'b0; + rx_sync_24 <= 1'b0; + tx_sync_24 <= 1'b0; + end else if (i_cs == 1'b1) begin //============================================= // READ OPERATIONS @@ -70,7 +112,10 @@ module sys_ctrl //---------------------------------------------- ioc_tx_sample_gap: begin o_data_out[3:0] <= tx_sample_gap; - o_data_out[7:4] <= 4'd0; + o_data_out[4] <= rx_sync_type09; + o_data_out[5] <= rx_sync_type24; + o_data_out[6] <= tx_sync_type09; + o_data_out[7] <= tx_sync_type24; end endcase end @@ -89,6 +134,17 @@ module sys_ctrl //---------------------------------------------- ioc_tx_sample_gap: begin tx_sample_gap <= i_data_in[3:0]; + rx_sync_type09 <= i_data_in[4]; + rx_sync_type24 <= i_data_in[5]; + tx_sync_type09 <= i_data_in[6]; + tx_sync_type24 <= i_data_in[7]; + end + //---------------------------------------------- + ioc_soft_sync: begin + rx_sync_09 <= i_data_in[0]; + tx_sync_09 <= i_data_in[1]; + rx_sync_24 <= i_data_in[2]; + tx_sync_24 <= i_data_in[3]; end endcase end diff --git a/firmware/top.asc b/firmware/top.asc index 371c9ae..9482724 100644 --- a/firmware/top.asc +++ b/firmware/top.asc @@ -56,81 +56,81 @@ .io_tile 4 0 000000000000000010 -000001010000000000 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o_iq_tx_clk_p$SB_IO_OUT -.sym 852 o_iq_tx_clk_p$SB_IO_OUT -.sym 860 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] -.sym 861 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 862 rx_fifo.rd_addr_gray_wr_r[7] -.sym 863 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] -.sym 864 w_rx_fifo_data[1] -.sym 865 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 866 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 867 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 886 rx_fifo.wr_addr[2] -.sym 912 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 940 o_iq_tx_clk_p$SB_IO_OUT -.sym 944 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 970 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 975 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 976 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 977 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 978 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 979 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 980 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 981 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 993 o_led1$SB_IO_OUT -.sym 1000 rx_fifo.wr_addr[5] -.sym 1011 w_rx_fifo_data[1] -.sym 1018 rx_fifo.rd_addr_gray_wr[6] -.sym 1036 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 1051 $PACKER_VCC_NET -.sym 1054 w_lvds_rx_09_d0 +.sym 856 o_iq_tx_clk_p$SB_IO_OUT +.sym 861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.sym 862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 863 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 864 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 865 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 866 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 867 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 897 rx_fifo.wr_addr[6] +.sym 899 rx_fifo.wr_addr[4] +.sym 920 rx_fifo.rd_addr_gray_wr_r[8] +.sym 944 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 963 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 975 rx_fifo.wr_addr[1] +.sym 976 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 977 rx_fifo.wr_addr[5] +.sym 978 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 979 rx_fifo.wr_addr[7] +.sym 980 rx_fifo.wr_addr[3] +.sym 981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.sym 984 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 1009 rx_fifo.wr_addr[8] +.sym 1031 $PACKER_VCC_NET +.sym 1046 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1054 o_iq_tx_clk_p$SB_IO_OUT .sym 1055 $PACKER_VCC_NET -.sym 1056 o_led0$SB_IO_OUT .sym 1061 $PACKER_GND_NET .sym 1062 $PACKER_GND_NET .sym 1066 $PACKER_VCC_NET .sym 1067 $PACKER_VCC_NET .sym 1069 $PACKER_VCC_NET .sym 1071 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1078 $PACKER_VCC_NET -.sym 1079 $PACKER_GND_NET -.sym 1085 $PACKER_VCC_NET +.sym 1074 $PACKER_VCC_NET +.sym 1077 $PACKER_GND_NET +.sym 1085 $PACKER_GND_NET .sym 1086 $PACKER_VCC_NET -.sym 1087 $PACKER_GND_NET -.sym 1088 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 1089 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 1090 w_rx_09_fifo_data[0] -.sym 1091 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 1092 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 1093 w_rx_09_fifo_data[1] -.sym 1094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 1095 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 1116 $PACKER_VCC_NET -.sym 1160 $PACKER_VCC_NET -.sym 1168 o_iq_tx_clk_p$SB_IO_OUT +.sym 1088 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 1089 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 1090 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 1091 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 1092 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1094 w_rx_fifo_full +.sym 1095 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 1120 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 1121 rx_fifo.wr_addr[3] +.sym 1123 rx_fifo.wr_addr[5] +.sym 1125 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 1126 $PACKER_VCC_NET +.sym 1127 rx_fifo.wr_addr[7] +.sym 1129 rx_fifo.wr_addr[3] +.sym 1130 $PACKER_VCC_NET +.sym 1132 rx_fifo.wr_addr[9] +.sym 1136 rx_fifo.wr_addr[1] +.sym 1160 $PACKER_GND_NET +.sym 1165 rx_fifo.wr_addr[1] .sym 1173 w_lvds_rx_09_d0 .sym 1174 w_lvds_rx_09_d1 .sym 1183 $PACKER_VCC_NET .sym 1184 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1188 $PACKER_VCC_NET -.sym 1202 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 1203 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 1204 rx_fifo.wr_addr_gray[4] -.sym 1205 rx_fifo.wr_addr_gray[8] -.sym 1206 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 1207 rx_fifo.wr_addr[9] -.sym 1208 rx_fifo.wr_addr_gray[7] -.sym 1209 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 1211 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 1234 w_rx_24_fifo_data[30] -.sym 1253 $PACKER_VCC_NET +.sym 1196 $PACKER_VCC_NET +.sym 1202 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 1203 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 1204 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 1206 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 1208 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 1209 rx_fifo.rd_addr_gray_wr_r[0] +.sym 1230 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 1234 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 1235 w_rx_fifo_full +.sym 1242 i_rst_b$SB_IO_IN +.sym 1246 $PACKER_VCC_NET +.sym 1261 w_rx_fifo_full +.sym 1269 w_lvds_rx_09_d0 .sym 1271 w_lvds_rx_09_d1 -.sym 1278 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 1282 w_lvds_rx_24_d0 .sym 1287 o_iq_tx_clk_p$SB_IO_OUT .sym 1297 $PACKER_VCC_NET -.sym 1305 $PACKER_VCC_NET -.sym 1316 rx_fifo.wr_addr_gray_rd[9] -.sym 1319 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 1320 rx_fifo.wr_addr_gray_rd[7] -.sym 1321 rx_fifo.wr_addr_gray_rd[8] -.sym 1323 rx_fifo.wr_addr_gray_rd[4] -.sym 1325 io_ctrl_ins.o_data_out[5] -.sym 1355 rx_fifo.wr_addr[9] +.sym 1313 $PACKER_VCC_NET +.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 1317 w_rx_09_fifo_data[0] +.sym 1318 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1319 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 1320 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 1321 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 1322 w_rx_09_fifo_data[1] +.sym 1323 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 1343 rx_fifo.rd_addr_gray_wr[0] .sym 1401 w_lvds_rx_24_d0 .sym 1402 w_lvds_rx_24_d1 .sym 1411 $PACKER_VCC_NET .sym 1412 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1419 $PACKER_VCC_NET -.sym 1431 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 1432 w_lvds_rx_24_d1 -.sym 1433 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 1435 w_lvds_rx_24_d0 -.sym 1437 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 1450 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 1467 $PACKER_VCC_NET -.sym 1480 w_lvds_rx_09_d0 -.sym 1485 rx_fifo.wr_addr_gray_rd[4] -.sym 1510 o_led1$SB_IO_OUT -.sym 1512 o_led0$SB_IO_OUT -.sym 1551 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 1592 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 1625 o_shdn_tx_lna$SB_IO_OUT -.sym 1685 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 1697 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 1713 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 1879 w_rx_fifo_data[9] -.sym 1885 w_rx_fifo_data[7] -.sym 1886 w_rx_fifo_data[8] -.sym 1939 w_rx_09_fifo_data[5] -.sym 1950 w_rx_09_fifo_data[11] -.sym 1956 w_rx_09_fifo_data[16] -.sym 1973 w_rx_24_fifo_data[5] -.sym 1975 w_rx_09_fifo_data[7] -.sym 1979 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 1987 w_rx_09_fifo_data[9] -.sym 1991 w_rx_09_fifo_data[5] -.sym 1997 o_led1$SB_IO_OUT -.sym 2002 w_rx_24_fifo_data[5] -.sym 2003 o_led1$SB_IO_OUT -.sym 2004 w_rx_09_fifo_data[5] -.sym 2014 w_rx_09_fifo_data[7] -.sym 2017 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2026 w_rx_09_fifo_data[9] -.sym 2029 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2038 w_rx_09_fifo_data[5] -.sym 2039 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2048 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 2049 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2050 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2063 w_rx_fifo_data[14] -.sym 2065 w_rx_fifo_data[10] -.sym 2066 w_rx_24_fifo_data[12] -.sym 2067 w_rx_fifo_data[11] -.sym 2068 w_rx_24_fifo_data[13] -.sym 2070 w_rx_fifo_data[13] -.sym 2078 w_rx_fifo_push -.sym 2081 w_rx_24_fifo_data[7] -.sym 2096 w_rx_fifo_data[5] -.sym 2106 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2108 w_rx_24_fifo_data[5] -.sym 2113 w_rx_24_fifo_data[8] -.sym 2120 w_rx_24_fifo_data[13] -.sym 2123 w_rx_24_fifo_data[3] -.sym 2124 w_rx_24_fifo_data[9] -.sym 2125 w_rx_fifo_data[15] -.sym 2127 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2129 w_rx_24_fifo_data[15] -.sym 2141 o_led1$SB_IO_OUT -.sym 2152 w_rx_09_fifo_data[8] -.sym 2154 w_rx_09_fifo_data[4] -.sym 2158 w_rx_09_fifo_data[10] -.sym 2167 w_rx_09_fifo_data[6] -.sym 2175 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2176 w_rx_24_fifo_data[6] -.sym 2181 o_led1$SB_IO_OUT -.sym 2185 w_rx_09_fifo_data[6] -.sym 2186 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2197 o_led1$SB_IO_OUT -.sym 2198 w_rx_24_fifo_data[6] -.sym 2199 w_rx_09_fifo_data[6] -.sym 2204 w_rx_09_fifo_data[10] -.sym 2205 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2221 w_rx_09_fifo_data[8] -.sym 2224 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2228 w_rx_09_fifo_data[4] -.sym 2229 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2231 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 1416 $PACKER_VCC_NET +.sym 1430 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 1431 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 1432 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 1433 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 1434 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 1459 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 1463 i_rst_b$SB_IO_IN +.sym 1474 w_lvds_rx_24_d1 +.sym 1481 $PACKER_VCC_NET +.sym 1510 i_rst_b$SB_IO_IN +.sym 1545 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 1547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 1550 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 1699 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 1714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 1880 w_rx_09_fifo_data[13] +.sym 1882 w_rx_09_fifo_data[15] +.sym 1883 rx_fifo.mem_q.0.3_WDATA_1 +.sym 1884 w_rx_09_fifo_data[17] +.sym 1886 rx_fifo.mem_q.0.3_WDATA +.sym 1914 o_led0$SB_IO_OUT +.sym 1939 w_rx_09_fifo_data[10] +.sym 2063 w_rx_24_fifo_data[14] +.sym 2064 w_rx_24_fifo_data[16] +.sym 2065 w_rx_24_fifo_data[17] +.sym 2066 w_rx_24_fifo_data[22] +.sym 2067 w_rx_24_fifo_data[18] +.sym 2068 rx_fifo.mem_q.0.3_WDATA_2 +.sym 2069 rx_fifo.mem_q.0.3_WDATA_3 +.sym 2070 w_rx_24_fifo_data[15] +.sym 2072 rx_fifo.wr_addr[5] +.sym 2073 rx_fifo.wr_addr[5] +.sym 2079 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 2091 o_led1$SB_IO_OUT +.sym 2093 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2107 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2122 w_rx_09_fifo_data[11] +.sym 2124 w_rx_09_fifo_data[17] +.sym 2137 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2152 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2155 w_rx_09_fifo_data[10] +.sym 2180 w_rx_09_fifo_data[12] +.sym 2183 w_rx_09_fifo_data[14] +.sym 2209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2212 w_rx_09_fifo_data[10] +.sym 2221 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2223 w_rx_09_fifo_data[14] +.sym 2228 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2229 w_rx_09_fifo_data[12] +.sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2232 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2234 w_rx_24_fifo_data[6] -.sym 2235 w_rx_24_fifo_data[9] -.sym 2236 w_rx_24_fifo_data[5] -.sym 2237 w_rx_24_fifo_data[17] -.sym 2238 w_rx_24_fifo_data[8] -.sym 2239 w_rx_24_fifo_data[14] -.sym 2240 w_rx_24_fifo_data[11] -.sym 2241 w_rx_24_fifo_data[10] -.sym 2248 w_rx_09_fifo_data[4] -.sym 2259 w_rx_fifo_data[6] -.sym 2260 w_rx_24_fifo_data[12] -.sym 2261 w_rx_09_fifo_data[12] -.sym 2263 tx_fifo.wr_addr_gray_rd[7] -.sym 2266 rx_fifo.wr_addr[3] -.sym 2267 tx_fifo.wr_addr_gray_rd[1] -.sym 2269 tx_fifo.wr_addr_gray_rd[2] -.sym 2276 w_rx_09_fifo_data[17] -.sym 2281 w_rx_09_fifo_data[4] -.sym 2287 w_rx_09_fifo_data[11] -.sym 2289 w_rx_09_fifo_data[14] -.sym 2297 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2298 w_rx_09_fifo_data[12] -.sym 2303 w_rx_09_fifo_data[13] -.sym 2305 o_led1$SB_IO_OUT -.sym 2315 w_rx_09_fifo_data[15] -.sym 2318 w_rx_24_fifo_data[15] -.sym 2320 w_rx_09_fifo_data[11] -.sym 2323 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2327 w_rx_24_fifo_data[15] -.sym 2328 w_rx_09_fifo_data[15] -.sym 2329 o_led1$SB_IO_OUT -.sym 2332 w_rx_09_fifo_data[12] -.sym 2335 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2338 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2339 w_rx_09_fifo_data[14] -.sym 2344 w_rx_09_fifo_data[13] -.sym 2345 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2350 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2352 w_rx_09_fifo_data[15] -.sym 2366 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2234 w_rx_09_fifo_data[25] +.sym 2235 w_rx_09_fifo_data[19] +.sym 2236 w_rx_09_fifo_data[21] +.sym 2237 rx_fifo.mem_i.0.1_WDATA_2 +.sym 2238 rx_fifo.mem_i.0.0_WDATA_2 +.sym 2239 w_rx_09_fifo_data[23] +.sym 2240 rx_fifo.mem_i.0.0_WDATA_3 +.sym 2241 rx_fifo.mem_i.0.0_WDATA_1 +.sym 2242 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2244 w_rx_09_fifo_data[0] +.sym 2245 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2251 rx_fifo.rd_addr[1] +.sym 2254 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2256 o_led1$SB_IO_OUT +.sym 2258 w_rx_24_fifo_data[17] +.sym 2260 w_rx_24_fifo_data[22] +.sym 2262 w_rx_24_fifo_data[12] +.sym 2266 w_rx_24_fifo_data[13] +.sym 2270 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2293 w_rx_09_fifo_data[18] +.sym 2301 w_rx_09_fifo_data[16] +.sym 2310 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2316 w_rx_09_fifo_data[20] +.sym 2350 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2353 w_rx_09_fifo_data[18] +.sym 2357 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2359 w_rx_09_fifo_data[16] +.sym 2364 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2365 w_rx_09_fifo_data[20] +.sym 2366 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2367 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2369 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 2370 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 2371 w_rx_fifo_data[17] -.sym 2374 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 2375 w_rx_fifo_data[4] -.sym 2376 w_rx_fifo_data[12] -.sym 2394 w_rx_fifo_data[5] -.sym 2395 w_rx_24_fifo_data[17] -.sym 2396 w_rx_fifo_data[23] -.sym 2397 w_rx_24_fifo_data[4] -.sym 2403 w_rx_09_fifo_data[4] -.sym 2416 w_rx_09_fifo_data[5] -.sym 2422 w_rx_24_fifo_data[31] -.sym 2423 w_rx_09_fifo_data[31] -.sym 2425 w_rx_24_fifo_data[23] -.sym 2426 w_rx_24_fifo_data[25] -.sym 2427 w_rx_24_fifo_data[29] -.sym 2432 o_led1$SB_IO_OUT -.sym 2438 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2445 w_rx_24_fifo_data[27] -.sym 2448 w_rx_24_fifo_data[21] -.sym 2449 w_rx_24_fifo_data[18] -.sym 2455 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2456 w_rx_24_fifo_data[29] -.sym 2461 w_rx_09_fifo_data[31] -.sym 2462 w_rx_24_fifo_data[31] -.sym 2463 o_led1$SB_IO_OUT -.sym 2474 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2475 w_rx_24_fifo_data[21] -.sym 2479 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2480 w_rx_24_fifo_data[23] -.sym 2485 w_rx_24_fifo_data[27] -.sym 2488 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2491 w_rx_24_fifo_data[18] -.sym 2493 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2498 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2500 w_rx_24_fifo_data[25] -.sym 2501 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2369 w_rx_24_fifo_data[24] +.sym 2370 w_rx_24_fifo_data[26] +.sym 2371 rx_fifo.mem_i.0.0_WDATA +.sym 2372 w_rx_24_fifo_data[19] +.sym 2373 rx_fifo.mem_i.0.2_WDATA_3 +.sym 2374 w_rx_24_fifo_data[21] +.sym 2375 w_rx_24_fifo_data[30] +.sym 2376 w_rx_24_fifo_data[28] +.sym 2378 w_rx_fifo_pulled_data[22] +.sym 2383 w_rx_09_fifo_data[20] +.sym 2384 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2388 w_rx_09_fifo_data[25] +.sym 2392 o_led1$SB_IO_OUT +.sym 2394 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2396 w_rx_24_fifo_data[21] +.sym 2402 o_led1$SB_IO_OUT +.sym 2403 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2405 rx_fifo.mem_q.0.2_WDATA_2 +.sym 2407 w_rx_09_fifo_data[10] +.sym 2415 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2424 o_led1$SB_IO_OUT +.sym 2427 w_rx_09_fifo_data[9] +.sym 2429 w_rx_09_fifo_data[22] +.sym 2430 w_rx_24_fifo_data[9] +.sym 2442 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2445 w_rx_09_fifo_data[7] +.sym 2467 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2470 w_rx_09_fifo_data[9] +.sym 2485 w_rx_09_fifo_data[7] +.sym 2488 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2491 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2492 w_rx_09_fifo_data[22] +.sym 2497 w_rx_09_fifo_data[9] +.sym 2498 o_led1$SB_IO_OUT +.sym 2499 w_rx_24_fifo_data[9] +.sym 2501 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2502 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2503 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2504 w_rx_24_fifo_data[4] -.sym 2505 w_rx_24_fifo_data[22] -.sym 2506 w_rx_24_fifo_data[21] -.sym 2507 w_rx_24_fifo_data[24] -.sym 2508 w_rx_24_fifo_data[19] -.sym 2509 w_rx_24_fifo_data[26] -.sym 2510 w_rx_24_fifo_data[28] -.sym 2511 w_rx_fifo_data[22] -.sym 2513 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 2518 w_rx_24_fifo_data[29] -.sym 2519 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 2520 w_rx_fifo_data[31] -.sym 2523 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 2530 w_rx_fifo_data[21] -.sym 2531 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2535 w_rx_24_fifo_data[18] -.sym 2537 w_rx_24_fifo_data[2] -.sym 2544 w_rx_fifo_data[25] -.sym 2546 w_rx_09_fifo_data[16] -.sym 2557 w_rx_09_fifo_data[27] -.sym 2559 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2560 w_rx_24_fifo_data[23] -.sym 2561 w_rx_09_fifo_data[25] -.sym 2563 w_rx_09_fifo_data[29] -.sym 2564 w_rx_24_fifo_data[27] -.sym 2565 w_rx_09_fifo_data[21] -.sym 2567 w_rx_09_fifo_data[23] -.sym 2569 w_rx_24_fifo_data[25] -.sym 2571 w_rx_24_fifo_data[20] -.sym 2572 w_rx_09_fifo_data[20] -.sym 2573 o_led1$SB_IO_OUT -.sym 2575 w_rx_24_fifo_data[21] -.sym 2583 o_led1$SB_IO_OUT -.sym 2590 w_rx_09_fifo_data[25] -.sym 2592 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2597 w_rx_09_fifo_data[29] -.sym 2599 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2603 w_rx_24_fifo_data[20] -.sym 2604 w_rx_09_fifo_data[20] -.sym 2605 o_led1$SB_IO_OUT -.sym 2608 o_led1$SB_IO_OUT -.sym 2609 w_rx_09_fifo_data[27] -.sym 2610 w_rx_24_fifo_data[27] -.sym 2614 w_rx_09_fifo_data[25] -.sym 2615 w_rx_24_fifo_data[25] -.sym 2617 o_led1$SB_IO_OUT -.sym 2620 w_rx_09_fifo_data[21] -.sym 2622 o_led1$SB_IO_OUT -.sym 2623 w_rx_24_fifo_data[21] -.sym 2626 w_rx_09_fifo_data[27] -.sym 2628 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2632 w_rx_24_fifo_data[23] -.sym 2634 w_rx_09_fifo_data[23] -.sym 2635 o_led1$SB_IO_OUT -.sym 2636 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2504 rx_fifo.mem_q.0.2_WDATA +.sym 2505 w_rx_09_fifo_data[5] +.sym 2506 rx_fifo.mem_q.0.1_WDATA_1 +.sym 2507 rx_fifo.mem_q.0.1_WDATA +.sym 2508 rx_fifo.mem_i.0.2_WDATA_2 +.sym 2509 w_rx_09_fifo_data[26] +.sym 2510 w_rx_09_fifo_data[28] +.sym 2511 w_rx_09_fifo_data[7] +.sym 2513 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2514 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2516 rx_fifo.rd_addr[4] +.sym 2517 w_rx_24_fifo_data[30] +.sym 2518 o_led1$SB_IO_OUT +.sym 2520 rx_fifo.rd_addr[8] +.sym 2528 rx_fifo.wr_addr[5] +.sym 2530 rx_fifo.wr_addr[3] +.sym 2531 rx_fifo.wr_addr[1] +.sym 2534 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2542 w_rx_24_fifo_data[8] +.sym 2557 w_rx_24_fifo_data[9] +.sym 2561 o_iq_tx_clk_p$SB_IO_OUT +.sym 2568 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2570 w_rx_24_fifo_data[10] +.sym 2574 w_rx_24_fifo_data[11] +.sym 2575 w_rx_24_fifo_data[5] +.sym 2576 w_rx_24_fifo_data[8] +.sym 2580 w_rx_24_fifo_data[7] +.sym 2585 w_rx_24_fifo_data[6] +.sym 2587 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2591 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2593 w_rx_24_fifo_data[7] +.sym 2596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2597 w_rx_24_fifo_data[9] +.sym 2603 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2604 w_rx_24_fifo_data[10] +.sym 2608 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2610 w_rx_24_fifo_data[6] +.sym 2615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2617 w_rx_24_fifo_data[11] +.sym 2620 w_rx_24_fifo_data[8] +.sym 2622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2626 o_iq_tx_clk_p$SB_IO_OUT +.sym 2634 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2635 w_rx_24_fifo_data[5] +.sym 2636 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 2637 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2638 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2639 w_rx_09_fifo_data[22] -.sym 2640 w_rx_09_fifo_data[26] -.sym 2641 w_rx_fifo_data[28] -.sym 2642 w_rx_fifo_data[26] -.sym 2643 w_rx_09_fifo_data[24] -.sym 2644 w_rx_09_fifo_data[30] -.sym 2645 w_rx_fifo_data[19] -.sym 2646 w_rx_09_fifo_data[28] -.sym 2648 rx_fifo.wr_addr[9] -.sym 2649 rx_fifo.wr_addr[9] -.sym 2653 o_led0$SB_IO_OUT -.sym 2654 w_rx_24_fifo_data[24] -.sym 2656 w_rx_fifo_data[22] -.sym 2657 w_rx_fifo_data[20] -.sym 2663 w_rx_24_fifo_data[3] -.sym 2664 w_rx_09_fifo_data[24] -.sym 2666 w_rx_fifo_data[27] -.sym 2672 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 2676 w_rx_fifo_data[16] -.sym 2680 o_led1$SB_IO_OUT -.sym 2686 o_led0$SB_IO_OUT -.sym 2693 w_rx_09_fifo_data[2] -.sym 2698 w_rx_09_fifo_data[18] -.sym 2707 w_rx_09_fifo_data[17] -.sym 2709 w_rx_09_fifo_data[19] -.sym 2710 w_rx_09_fifo_data[23] -.sym 2712 o_iq_tx_clk_p$SB_IO_OUT -.sym 2715 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2716 w_rx_09_fifo_data[21] -.sym 2726 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2728 w_rx_09_fifo_data[19] -.sym 2731 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2734 w_rx_09_fifo_data[17] -.sym 2738 w_rx_09_fifo_data[21] -.sym 2740 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2749 w_rx_09_fifo_data[23] -.sym 2752 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2755 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2757 w_rx_09_fifo_data[2] -.sym 2763 o_iq_tx_clk_p$SB_IO_OUT -.sym 2767 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2770 w_rx_09_fifo_data[18] -.sym 2771 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2638 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2639 w_rx_24_fifo_data[2] +.sym 2640 rx_fifo.mem_q.0.0_WDATA_2 +.sym 2641 w_rx_24_fifo_data[5] +.sym 2642 rx_fifo.mem_q.0.0_WDATA +.sym 2643 w_rx_24_fifo_data[6] +.sym 2644 w_rx_24_fifo_data[3] +.sym 2645 w_rx_24_fifo_data[4] +.sym 2646 rx_fifo.mem_q.0.1_WDATA_3 +.sym 2652 w_rx_09_fifo_data[28] +.sym 2664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 2667 rx_fifo.rd_addr_gray_wr[9] +.sym 2671 rx_fifo.wr_addr[6] +.sym 2673 rx_fifo.wr_addr[4] +.sym 2676 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2678 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2693 w_rx_09_fifo_data[6] +.sym 2697 w_rx_24_fifo_data[10] +.sym 2701 w_rx_09_fifo_data[6] +.sym 2702 w_rx_09_fifo_data[1] +.sym 2704 o_led1$SB_IO_OUT +.sym 2705 w_rx_09_fifo_data[4] +.sym 2707 w_rx_09_fifo_data[10] +.sym 2708 w_rx_09_fifo_data[8] +.sym 2709 w_rx_09_fifo_data[0] +.sym 2710 w_rx_09_fifo_data[2] +.sym 2712 w_rx_24_fifo_data[6] +.sym 2716 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2725 w_rx_09_fifo_data[6] +.sym 2726 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2731 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2732 w_rx_09_fifo_data[4] +.sym 2738 w_rx_09_fifo_data[0] +.sym 2740 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2743 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2745 w_rx_09_fifo_data[1] +.sym 2749 w_rx_24_fifo_data[6] +.sym 2750 w_rx_09_fifo_data[6] +.sym 2752 o_led1$SB_IO_OUT +.sym 2757 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2758 w_rx_09_fifo_data[2] +.sym 2762 o_led1$SB_IO_OUT +.sym 2763 w_rx_09_fifo_data[10] +.sym 2764 w_rx_24_fifo_data[10] +.sym 2767 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2770 w_rx_09_fifo_data[8] +.sym 2771 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 2772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 2773 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2775 w_rx_fifo_data[2] -.sym 2776 w_rx_24_fifo_data[16] -.sym 2777 w_rx_24_fifo_data[18] -.sym 2778 w_rx_24_fifo_data[2] -.sym 2779 w_rx_fifo_data[3] -.sym 2780 w_rx_24_fifo_data[3] -.sym 2781 w_rx_fifo_data[18] -.sym 2801 rx_fifo.wr_addr[6] -.sym 2805 rx_fifo.wr_addr[3] -.sym 2809 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 2828 w_rx_09_fifo_data[0] -.sym 2829 w_rx_09_fifo_data[3] -.sym 2837 w_rx_09_fifo_data[16] -.sym 2838 w_rx_09_fifo_data[1] -.sym 2845 w_rx_24_fifo_data[16] -.sym 2853 o_led1$SB_IO_OUT -.sym 2854 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2868 w_rx_09_fifo_data[0] -.sym 2869 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2872 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2874 w_rx_09_fifo_data[1] -.sym 2884 w_rx_24_fifo_data[16] -.sym 2885 o_led1$SB_IO_OUT -.sym 2887 w_rx_09_fifo_data[16] -.sym 2891 w_rx_09_fifo_data[3] -.sym 2893 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2896 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2899 w_rx_09_fifo_data[16] -.sym 2906 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2774 rx_fifo.rd_addr_gray_wr[9] +.sym 2790 w_rx_09_fifo_data[1] +.sym 2792 o_led1$SB_IO_OUT +.sym 2794 rx_fifo.rd_addr[0] +.sym 2796 rx_fifo.rd_addr[1] +.sym 2799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 2802 rx_fifo.rd_addr[9] +.sym 2803 rx_fifo.mem_q.0.1_WDATA_2 +.sym 2807 w_rx_24_fifo_data[0] +.sym 2808 rx_fifo.mem_q.0.1_WDATA_3 +.sym 2814 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2818 w_rx_09_fifo_data[1] +.sym 2819 $PACKER_GND_NET +.sym 2833 w_rx_24_fifo_data[8] +.sym 2835 w_rx_09_fifo_data[8] +.sym 2842 o_led1$SB_IO_OUT +.sym 2845 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2847 w_lvds_rx_24_d0 +.sym 2893 w_lvds_rx_24_d0 +.sym 2903 o_led1$SB_IO_OUT +.sym 2904 w_rx_09_fifo_data[8] +.sym 2905 w_rx_24_fifo_data[8] +.sym 2906 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 2907 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2908 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2909 rx_fifo.wr_addr[2] -.sym 2911 $PACKER_GND_NET -.sym 2913 rx_fifo.wr_addr[7] -.sym 2914 rx_fifo.wr_addr[8] -.sym 2915 w_rx_fifo_data[0] -.sym 2920 o_led0$SB_IO_OUT -.sym 2926 w_rx_09_fifo_data[1] -.sym 2932 w_rx_09_fifo_data[0] -.sym 2933 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 2934 rx_fifo.wr_addr[7] -.sym 2937 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 2938 w_rx_24_fifo_data[0] -.sym 2941 w_rx_24_fifo_data[1] -.sym 2942 rx_fifo.wr_addr[2] -.sym 2947 rx_fifo.rd_addr_gray_wr[3] -.sym 2950 w_rx_09_fifo_data[0] -.sym 2956 w_rx_09_fifo_data[1] -.sym 2978 rx_fifo.wr_addr[5] -.sym 2979 rx_fifo.wr_addr[6] -.sym 2980 rx_fifo.wr_addr[4] -.sym 2983 rx_fifo.wr_addr[8] -.sym 2986 rx_fifo.wr_addr[2] -.sym 2989 rx_fifo.wr_addr[3] -.sym 2990 rx_fifo.wr_addr[7] -.sym 2991 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 2994 $nextpnr_ICESTORM_LC_7$O -.sym 2997 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 3000 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 3003 rx_fifo.wr_addr[2] -.sym 3006 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 3009 rx_fifo.wr_addr[3] -.sym 3010 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 3012 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 3014 rx_fifo.wr_addr[4] -.sym 3016 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 3018 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 3021 rx_fifo.wr_addr[5] -.sym 3022 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 3024 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 3027 rx_fifo.wr_addr[6] -.sym 3028 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 3030 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 3032 rx_fifo.wr_addr[7] -.sym 3034 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 3036 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 3039 rx_fifo.wr_addr[8] -.sym 3040 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 3044 rx_fifo.wr_addr[5] -.sym 3045 rx_fifo.wr_addr[6] -.sym 3046 rx_fifo.wr_addr[4] -.sym 3047 rx_fifo.wr_addr[3] -.sym 3048 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] -.sym 3049 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 3050 rx_fifo.wr_addr[0] -.sym 3051 rx_fifo.wr_addr_gray[5] -.sym 3060 w_rx_fifo_pulled_data[3] -.sym 3063 w_rx_fifo_data[25] -.sym 3067 w_rx_09_fifo_data[0] -.sym 3068 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3069 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] -.sym 3071 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 3072 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 3074 rx_fifo.wr_addr[8] -.sym 3075 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3079 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 3080 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3084 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3086 rx_fifo.rd_addr_gray_wr[7] -.sym 3088 w_rx_09_fifo_data[0] -.sym 3091 rx_fifo.wr_addr[9] -.sym 3092 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 3098 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 3101 o_led1$SB_IO_OUT -.sym 3102 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 3103 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 3104 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 3107 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3109 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 3112 rx_fifo.rd_addr_gray_wr[6] -.sym 3113 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3115 rx_fifo.rd_addr_gray_wr[7] -.sym 3116 rx_fifo.rd_addr_gray_wr[3] -.sym 3119 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 3123 w_rx_09_fifo_data[1] -.sym 3125 w_rx_24_fifo_data[1] -.sym 3128 rx_fifo.wr_addr[9] -.sym 3132 rx_fifo.wr_addr[9] -.sym 3133 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 3136 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 3137 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3144 rx_fifo.rd_addr_gray_wr[7] -.sym 3148 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3149 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 3150 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 3155 w_rx_09_fifo_data[1] -.sym 3156 o_led1$SB_IO_OUT -.sym 3157 w_rx_24_fifo_data[1] -.sym 3160 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 3161 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 3162 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 3163 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 3168 rx_fifo.rd_addr_gray_wr[6] -.sym 3174 rx_fifo.rd_addr_gray_wr[3] -.sym 3177 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3179 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 3180 w_rx_fifo_full -.sym 3181 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 3182 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 3183 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 3184 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 3185 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] -.sym 3186 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] -.sym 3194 w_rx_fifo_push -.sym 3199 w_rx_fifo_data[16] -.sym 3204 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 3205 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 3206 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 3207 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3208 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 3209 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 3210 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 3211 rx_fifo.rd_addr_gray_wr_r[9] -.sym 3212 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 3213 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 3214 w_rx_fifo_full -.sym 3216 i_rst_b$SB_IO_IN -.sym 3220 o_led1$SB_IO_OUT -.sym 3221 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 3222 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 3232 rx_fifo.wr_addr[5] -.sym 3233 rx_fifo.wr_addr[6] -.sym 3234 rx_fifo.wr_addr[4] -.sym 3237 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 3238 rx_fifo.wr_addr[0] -.sym 3240 rx_fifo.wr_addr[7] -.sym 3243 rx_fifo.wr_addr[3] -.sym 3246 rx_fifo.wr_addr[0] -.sym 3248 rx_fifo.wr_addr[2] -.sym 3264 $nextpnr_ICESTORM_LC_2$O -.sym 3266 rx_fifo.wr_addr[0] -.sym 3270 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 3273 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 3274 rx_fifo.wr_addr[0] -.sym 3276 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 3279 rx_fifo.wr_addr[2] -.sym 3280 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 3282 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 3284 rx_fifo.wr_addr[3] -.sym 3286 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 3288 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 3291 rx_fifo.wr_addr[4] -.sym 3292 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 3294 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 3296 rx_fifo.wr_addr[5] -.sym 3298 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 3300 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 3302 rx_fifo.wr_addr[6] -.sym 3304 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 3306 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 3309 rx_fifo.wr_addr[7] -.sym 3310 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 3314 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 3315 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] -.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] -.sym 3317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 3318 w_rx_24_fifo_data[30] -.sym 3319 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 3320 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 3321 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] -.sym 3326 $PACKER_VCC_NET -.sym 3327 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 3328 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 3332 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 3334 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 3335 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3336 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 3338 rx_fifo.rd_addr_gray_wr_r[2] -.sym 3339 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 3340 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 3345 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3349 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3362 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 3368 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 3369 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 3370 w_rx_fifo_push -.sym 3371 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3372 rx_fifo.wr_addr[9] -.sym 3373 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] -.sym 3374 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] -.sym 3375 w_lvds_rx_09_d0 -.sym 3376 w_lvds_rx_09_d1 -.sym 3378 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 3379 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 3380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 3381 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3382 rx_fifo.wr_addr[8] -.sym 3387 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 3389 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3390 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 3391 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3393 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 3399 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 3402 rx_fifo.wr_addr[8] -.sym 3403 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 3406 rx_fifo.wr_addr[9] -.sym 3409 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 3412 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3413 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3414 w_lvds_rx_09_d1 -.sym 3415 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 3419 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 3420 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 3424 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 3425 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 3426 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 3430 w_lvds_rx_09_d0 -.sym 3436 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 3437 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3438 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3439 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 3442 w_rx_fifo_push -.sym 3444 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] -.sym 3445 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] -.sym 3446 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 2910 rx_fifo.wr_addr_gray_rd[9] +.sym 2912 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 2913 rx_fifo.mem_q.0.0_WDATA_1 +.sym 2921 rx_fifo.wr_addr[4] +.sym 2922 rx_fifo.mem_q.0.2_WDATA_2 +.sym 2930 o_led1$SB_IO_OUT +.sym 2933 rx_fifo.wr_addr[6] +.sym 2935 rx_fifo.wr_addr[4] +.sym 2936 w_rx_09_fifo_data[0] +.sym 2937 rx_fifo.rd_addr_gray_wr_r[5] +.sym 2938 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 2939 rx_fifo.wr_addr[5] +.sym 2940 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 2941 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 2942 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2943 rx_fifo.wr_addr[7] +.sym 2945 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.sym 2951 rx_fifo.wr_addr[4] +.sym 2964 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 2970 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 2977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 2982 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 2985 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3008 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3009 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 3019 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3027 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3042 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3044 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.sym 3045 rx_fifo.mem_q.0.0_WDATA_3 +.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.sym 3047 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.sym 3048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] +.sym 3049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 3050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 3051 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.sym 3052 rx_fifo.wr_addr[6] +.sym 3057 rx_fifo.wr_addr[9] +.sym 3058 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3064 o_led1$SB_IO_OUT +.sym 3068 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3069 rx_fifo.wr_addr[3] +.sym 3070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 3072 w_rx_09_fifo_data[1] +.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 3075 rx_fifo.wr_addr[1] +.sym 3078 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3079 rx_fifo.wr_addr[5] +.sym 3101 rx_fifo.wr_addr[6] +.sym 3102 rx_fifo.wr_addr[7] +.sym 3103 rx_fifo.wr_addr[8] +.sym 3106 rx_fifo.wr_addr[1] +.sym 3108 rx_fifo.wr_addr[5] +.sym 3109 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 3110 rx_fifo.wr_addr[4] +.sym 3111 rx_fifo.wr_addr[3] +.sym 3129 $nextpnr_ICESTORM_LC_6$O +.sym 3132 rx_fifo.wr_addr[1] +.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3138 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 3139 rx_fifo.wr_addr[1] +.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 3143 rx_fifo.wr_addr[3] +.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3149 rx_fifo.wr_addr[4] +.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 3156 rx_fifo.wr_addr[5] +.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 3161 rx_fifo.wr_addr[6] +.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3167 rx_fifo.wr_addr[7] +.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 3173 rx_fifo.wr_addr[8] +.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3184 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3198 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3201 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 3202 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3203 rx_fifo.wr_addr[9] +.sym 3204 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3205 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3208 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3209 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.sym 3210 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3212 rx_fifo.rd_addr_gray_wr[9] +.sym 3213 rx_fifo.wr_addr[1] +.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3218 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3220 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 3232 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.sym 3234 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 3247 rx_fifo.wr_addr[9] +.sym 3249 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3250 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3255 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3259 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3261 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3265 rx_fifo.wr_addr[9] +.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 3311 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3312 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3313 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 3315 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 3317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3319 rx_fifo.wr_addr[0] +.sym 3320 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 3321 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 3322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 3329 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3330 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 3334 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3336 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 3337 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3338 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3341 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 3343 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 3346 $PACKER_VCC_NET +.sym 3347 w_rx_24_fifo_data[0] +.sym 3349 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 3350 w_rx_09_fifo_data[1] +.sym 3351 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3357 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3358 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3367 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3368 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 3369 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 3372 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3374 rx_fifo.rd_addr_gray_wr_r[0] +.sym 3375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 3376 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.sym 3377 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3378 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 3379 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 3380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 3381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3382 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3388 i_rst_b$SB_IO_IN +.sym 3389 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3390 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 3391 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3393 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.sym 3394 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 3398 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3400 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3402 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3403 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 3408 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3409 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3413 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 3414 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 3419 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 3420 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 3421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 3424 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3425 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 3426 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 3427 rx_fifo.rd_addr_gray_wr_r[0] +.sym 3431 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3432 i_rst_b$SB_IO_IN +.sym 3436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 3437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 3438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 3439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 3442 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.sym 3443 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.sym 3444 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 3445 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] .sym 3447 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3449 rx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 3450 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 3451 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 3452 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 3453 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 3455 rx_fifo.rd_addr_gray_wr_r[2] -.sym 3456 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 3464 w_rx_fifo_push -.sym 3466 rx_fifo.rd_addr_gray_wr[3] -.sym 3475 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3478 w_rx_24_fifo_data[0] -.sym 3480 w_rx_24_fifo_data[1] -.sym 3482 w_rx_fifo_push -.sym 3491 w_lvds_rx_09_d1 -.sym 3503 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 3505 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 3507 i_rst_b$SB_IO_IN -.sym 3509 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 3510 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3513 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 3514 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 3517 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 3518 w_lvds_rx_09_d0 -.sym 3521 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3522 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 3525 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3527 w_lvds_rx_09_d1 -.sym 3530 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 3533 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 3535 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 3536 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 3537 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 3538 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 3541 i_rst_b$SB_IO_IN -.sym 3543 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 3550 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 3555 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 3559 w_lvds_rx_09_d1 -.sym 3560 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3561 w_lvds_rx_09_d0 -.sym 3562 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3565 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 3572 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3573 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 3577 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 3579 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 3581 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 3448 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3449 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 3450 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 3451 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 3453 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 3454 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3455 rx_fifo.rd_addr_gray_wr[8] +.sym 3456 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 3462 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 3468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 3469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 3471 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.sym 3472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 3473 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 3476 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3480 w_rx_09_fifo_data[0] +.sym 3482 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3486 w_lvds_rx_09_d1 +.sym 3488 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3489 w_lvds_rx_09_d0 +.sym 3503 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 3508 w_rx_fifo_full +.sym 3511 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3516 rx_fifo.rd_addr_gray_wr[0] +.sym 3518 rx_fifo.rd_addr_gray_wr[9] +.sym 3519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3521 rx_fifo.wr_addr[1] +.sym 3522 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 3524 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3526 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3528 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 3530 w_lvds_rx_09_d0 +.sym 3531 w_lvds_rx_09_d1 +.sym 3532 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 3533 rx_fifo.rd_addr_gray_wr_r[0] +.sym 3535 w_lvds_rx_09_d1 +.sym 3536 w_lvds_rx_09_d0 +.sym 3537 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3538 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3542 rx_fifo.rd_addr_gray_wr[9] +.sym 3547 w_lvds_rx_09_d1 +.sym 3548 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3549 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3550 w_lvds_rx_09_d0 +.sym 3559 rx_fifo.rd_addr_gray_wr_r[0] +.sym 3560 rx_fifo.wr_addr[1] +.sym 3561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3565 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 3566 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 3567 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 3571 w_rx_fifo_full +.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 3573 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3574 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 3577 rx_fifo.rd_addr_gray_wr[0] .sym 3582 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3586 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 3587 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3588 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 3590 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 3591 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3597 rx_fifo.rd_addr_gray_wr[4] -.sym 3602 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 3603 rx_fifo.rd_addr_gray_wr_r[5] -.sym 3605 rx_fifo.rd_addr_gray_wr[7] -.sym 3609 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 3610 rx_fifo.wr_addr_gray_rd[8] -.sym 3612 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 3613 rx_fifo.rd_addr_gray_wr[2] -.sym 3615 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3639 rx_fifo.wr_addr_gray[4] -.sym 3642 rx_fifo.wr_addr[9] -.sym 3643 rx_fifo.wr_addr_gray[7] -.sym 3648 rx_fifo.wr_addr_gray[8] -.sym 3657 w_lvds_rx_09_d0 -.sym 3660 w_lvds_rx_09_d1 -.sym 3671 rx_fifo.wr_addr[9] -.sym 3688 w_lvds_rx_09_d1 -.sym 3689 w_lvds_rx_09_d0 -.sym 3696 rx_fifo.wr_addr_gray[7] -.sym 3701 rx_fifo.wr_addr_gray[8] -.sym 3713 rx_fifo.wr_addr_gray[4] -.sym 3717 r_counter_$glb_clk -.sym 3721 w_rx_24_fifo_data[0] -.sym 3722 w_rx_24_fifo_data[1] -.sym 3731 rx_fifo.wr_addr_gray_rd[9] -.sym 3732 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 3739 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 3740 i_rst_b$SB_IO_IN -.sym 3741 rx_fifo.wr_addr_gray_rd[7] -.sym 3746 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3753 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 3755 o_led1$SB_IO_OUT -.sym 3779 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3788 w_lvds_rx_24_d0 -.sym 3790 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 3793 w_lvds_rx_24_d1 -.sym 3795 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 3799 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3811 w_lvds_rx_24_d1 -.sym 3812 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3813 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3814 w_lvds_rx_24_d0 -.sym 3818 w_lvds_rx_24_d1 -.sym 3823 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 3824 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3825 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3836 w_lvds_rx_24_d0 -.sym 3847 w_lvds_rx_24_d1 -.sym 3848 w_lvds_rx_24_d0 -.sym 3851 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 3584 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 3586 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 3587 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 3588 w_rx_24_fifo_data[0] +.sym 3590 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3607 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 3609 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3612 w_rx_09_fifo_data[1] +.sym 3613 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3637 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3641 w_lvds_rx_24_d0 +.sym 3644 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3645 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3649 i_rst_b$SB_IO_IN +.sym 3650 w_lvds_rx_24_d1 +.sym 3652 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 3655 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 3659 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3661 w_lvds_rx_09_d1 +.sym 3663 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3666 w_lvds_rx_09_d0 +.sym 3667 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3670 w_lvds_rx_24_d1 +.sym 3671 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3672 w_lvds_rx_24_d0 +.sym 3673 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3676 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3677 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 3678 w_lvds_rx_09_d1 +.sym 3684 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 3685 i_rst_b$SB_IO_IN +.sym 3689 w_lvds_rx_24_d1 +.sym 3691 w_lvds_rx_24_d0 +.sym 3694 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3696 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3697 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3702 w_lvds_rx_09_d1 +.sym 3703 w_lvds_rx_09_d0 +.sym 3708 w_lvds_rx_09_d0 +.sym 3712 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3713 w_lvds_rx_24_d0 +.sym 3714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3715 w_lvds_rx_24_d1 +.sym 3716 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 3717 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3720 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 3721 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 3722 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 3723 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3724 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 3725 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3726 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 3732 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3740 o_shdn_tx_lna$SB_IO_OUT +.sym 3743 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3761 o_shdn_tx_lna$SB_IO_OUT +.sym 3772 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3775 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3780 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3783 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 3785 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3794 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3796 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3798 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3802 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3807 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3808 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3811 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3818 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3819 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3820 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3825 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 3829 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3830 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 3831 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 3832 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3851 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E .sym 3852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3854 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 3856 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 3857 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 3858 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 3859 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 3860 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 3874 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3884 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3910 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3922 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 3925 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 3930 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3982 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 3983 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 3984 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 3986 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 3855 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 3856 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 3857 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 3859 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 3860 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3861 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 3862 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 3874 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3911 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3916 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3918 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3921 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3929 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3934 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3947 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3948 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3959 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3965 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3976 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3977 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3978 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3986 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O .sym 3987 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3990 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 3991 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 3992 lvds_rx_24_inst.r_phase_count[1] -.sym 3993 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 4008 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 4138 o_led0$SB_IO_OUT -.sym 4207 o_led1$SB_IO_OUT -.sym 4238 w_rx_fifo_pulled_data[8] -.sym 4242 w_rx_fifo_pulled_data[10] -.sym 4251 w_rx_24_fifo_data[14] -.sym 4258 w_rx_24_fifo_data[28] -.sym 4280 o_led1$SB_IO_OUT -.sym 4281 o_led1$SB_IO_OUT -.sym 4285 w_rx_09_fifo_data[7] -.sym 4288 w_rx_24_fifo_data[7] -.sym 4289 w_rx_09_fifo_data[9] -.sym 4295 w_rx_24_fifo_data[8] -.sym 4297 o_led1$SB_IO_OUT -.sym 4303 w_rx_09_fifo_data[8] -.sym 4305 w_rx_24_fifo_data[9] -.sym 4313 w_rx_09_fifo_data[9] -.sym 4314 o_led1$SB_IO_OUT -.sym 4315 w_rx_24_fifo_data[9] -.sym 4348 w_rx_09_fifo_data[7] -.sym 4349 o_led1$SB_IO_OUT -.sym 4350 w_rx_24_fifo_data[7] -.sym 4354 w_rx_09_fifo_data[8] -.sym 4355 o_led1$SB_IO_OUT -.sym 4357 w_rx_24_fifo_data[8] -.sym 4366 w_rx_fifo_pulled_data[9] -.sym 4370 w_rx_fifo_pulled_data[11] -.sym 4377 $PACKER_VCC_NET -.sym 4379 tx_fifo.wr_addr_gray_rd[7] -.sym 4381 tx_fifo.wr_addr_gray_rd[1] -.sym 4383 tx_fifo.wr_addr_gray_rd[2] -.sym 4388 rx_fifo.wr_addr[3] -.sym 4390 rx_fifo.wr_addr[4] -.sym 4399 rx_fifo.wr_addr[5] -.sym 4403 rx_fifo.wr_addr[0] -.sym 4408 o_led1$SB_IO_OUT -.sym 4411 w_rx_fifo_data[7] -.sym 4417 o_led1$SB_IO_OUT -.sym 4419 rx_fifo.wr_addr[2] -.sym 4422 rx_fifo.wr_addr[8] -.sym 4425 w_rx_24_fifo_data[7] -.sym 4426 w_rx_fifo_data[13] -.sym 4427 rx_fifo.wr_addr[9] -.sym 4428 rx_fifo.wr_addr[7] -.sym 4429 w_rx_24_fifo_data[5] -.sym 4430 w_rx_fifo_pull -.sym 4447 w_rx_24_fifo_data[14] -.sym 4448 w_rx_09_fifo_data[10] -.sym 4449 w_rx_24_fifo_data[10] -.sym 4455 w_rx_24_fifo_data[13] -.sym 4456 w_rx_24_fifo_data[11] -.sym 4458 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4460 w_rx_09_fifo_data[14] -.sym 4462 w_rx_09_fifo_data[11] -.sym 4465 o_led1$SB_IO_OUT -.sym 4466 w_rx_09_fifo_data[13] -.sym 4476 o_led1$SB_IO_OUT -.sym 4477 w_rx_09_fifo_data[14] -.sym 4478 w_rx_24_fifo_data[14] -.sym 4487 w_rx_09_fifo_data[10] -.sym 4488 w_rx_24_fifo_data[10] -.sym 4490 o_led1$SB_IO_OUT -.sym 4493 w_rx_24_fifo_data[10] -.sym 4494 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4499 w_rx_09_fifo_data[11] -.sym 4500 w_rx_24_fifo_data[11] -.sym 4502 o_led1$SB_IO_OUT -.sym 4507 w_rx_24_fifo_data[11] -.sym 4508 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4517 o_led1$SB_IO_OUT -.sym 4519 w_rx_09_fifo_data[13] +.sym 4002 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 4005 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 4208 o_shdn_tx_lna$SB_IO_OUT +.sym 4238 w_rx_fifo_pulled_data[12] +.sym 4242 w_rx_fifo_pulled_data[14] +.sym 4285 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4286 w_rx_24_fifo_data[15] +.sym 4288 w_rx_24_fifo_data[13] +.sym 4290 w_rx_09_fifo_data[15] +.sym 4291 o_led1$SB_IO_OUT +.sym 4296 w_rx_09_fifo_data[13] +.sym 4303 w_rx_09_fifo_data[11] +.sym 4319 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4320 w_rx_09_fifo_data[11] +.sym 4332 w_rx_09_fifo_data[13] +.sym 4333 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4337 o_led1$SB_IO_OUT +.sym 4338 w_rx_24_fifo_data[13] +.sym 4339 w_rx_09_fifo_data[13] +.sym 4343 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4345 w_rx_09_fifo_data[15] +.sym 4354 o_led1$SB_IO_OUT +.sym 4355 w_rx_09_fifo_data[15] +.sym 4356 w_rx_24_fifo_data[15] +.sym 4358 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 4359 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 4360 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4366 w_rx_fifo_pulled_data[13] +.sym 4370 w_rx_fifo_pulled_data[15] +.sym 4388 w_rx_24_fifo_data[13] +.sym 4393 $PACKER_VCC_NET +.sym 4394 rx_fifo.wr_addr[1] +.sym 4396 rx_fifo.wr_addr[7] +.sym 4398 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 4402 rx_fifo.wr_addr[3] +.sym 4408 rx_fifo.wr_addr[0] +.sym 4414 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 4424 rx_fifo.wr_addr[4] +.sym 4427 rx_fifo.wr_addr[6] +.sym 4428 rx_fifo.rd_addr[4] +.sym 4444 w_rx_24_fifo_data[20] +.sym 4446 w_rx_09_fifo_data[12] +.sym 4447 o_led1$SB_IO_OUT +.sym 4448 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4451 w_rx_24_fifo_data[16] +.sym 4453 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4457 w_rx_09_fifo_data[14] +.sym 4458 w_rx_24_fifo_data[14] +.sym 4462 w_rx_24_fifo_data[13] +.sym 4466 w_rx_24_fifo_data[12] +.sym 4473 w_rx_24_fifo_data[15] +.sym 4477 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4478 w_rx_24_fifo_data[12] +.sym 4482 w_rx_24_fifo_data[14] +.sym 4484 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4487 w_rx_24_fifo_data[15] +.sym 4489 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4494 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4496 w_rx_24_fifo_data[20] +.sym 4499 w_rx_24_fifo_data[16] +.sym 4501 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4505 o_led1$SB_IO_OUT +.sym 4506 w_rx_09_fifo_data[14] +.sym 4508 w_rx_24_fifo_data[14] +.sym 4512 o_led1$SB_IO_OUT +.sym 4513 w_rx_09_fifo_data[12] +.sym 4514 w_rx_24_fifo_data[12] +.sym 4518 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 4520 w_rx_24_fifo_data[13] -.sym 4521 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 4521 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 4522 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 4523 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4525 w_rx_fifo_pulled_data[12] -.sym 4529 w_rx_fifo_pulled_data[14] -.sym 4546 w_rx_fifo_data[11] -.sym 4551 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 4552 rx_fifo.wr_addr[4] -.sym 4553 o_led1$SB_IO_OUT -.sym 4555 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 4556 $PACKER_VCC_NET -.sym 4557 rx_fifo.wr_addr[4] -.sym 4558 rx_fifo.wr_addr[6] -.sym 4566 w_rx_24_fifo_data[9] -.sym 4568 w_rx_24_fifo_data[12] -.sym 4573 w_rx_24_fifo_data[6] -.sym 4574 w_rx_24_fifo_data[3] -.sym 4578 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4580 w_rx_24_fifo_data[15] -.sym 4581 w_rx_24_fifo_data[4] -.sym 4585 w_rx_24_fifo_data[8] -.sym 4590 w_rx_24_fifo_data[7] -.sym 4598 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4600 w_rx_24_fifo_data[4] -.sym 4605 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4607 w_rx_24_fifo_data[7] -.sym 4610 w_rx_24_fifo_data[3] -.sym 4612 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4617 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4619 w_rx_24_fifo_data[15] -.sym 4622 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4625 w_rx_24_fifo_data[6] -.sym 4628 w_rx_24_fifo_data[12] -.sym 4631 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4635 w_rx_24_fifo_data[9] -.sym 4636 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4641 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4643 w_rx_24_fifo_data[8] -.sym 4644 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 4525 w_rx_fifo_pulled_data[16] +.sym 4529 w_rx_fifo_pulled_data[18] +.sym 4536 rx_fifo.rd_addr[0] +.sym 4537 o_led1$SB_IO_OUT +.sym 4538 w_rx_24_fifo_data[20] +.sym 4539 rx_fifo.rd_addr[8] +.sym 4540 rx_fifo.rd_addr[7] +.sym 4542 rx_fifo.rd_addr[2] +.sym 4543 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4544 rx_fifo.rd_addr[3] +.sym 4545 w_rx_24_fifo_data[21] +.sym 4546 w_rx_24_fifo_data[18] +.sym 4548 rx_fifo.mem_q.0.2_WDATA +.sym 4549 rx_fifo.rd_addr[5] +.sym 4550 rx_fifo.rd_addr[3] +.sym 4551 w_rx_24_fifo_data[28] +.sym 4554 rx_fifo.rd_addr[6] +.sym 4556 rx_fifo.rd_addr[0] +.sym 4558 rx_fifo.rd_addr[1] +.sym 4567 w_rx_24_fifo_data[17] +.sym 4568 o_led1$SB_IO_OUT +.sym 4569 w_rx_24_fifo_data[18] +.sym 4570 w_rx_09_fifo_data[23] +.sym 4571 w_rx_09_fifo_data[18] +.sym 4572 w_rx_09_fifo_data[22] +.sym 4574 w_rx_24_fifo_data[16] +.sym 4575 w_rx_09_fifo_data[17] +.sym 4576 w_rx_24_fifo_data[22] +.sym 4577 o_led1$SB_IO_OUT +.sym 4583 w_rx_09_fifo_data[21] +.sym 4586 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4587 w_rx_09_fifo_data[16] +.sym 4590 w_rx_09_fifo_data[19] +.sym 4599 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4601 w_rx_09_fifo_data[23] +.sym 4604 w_rx_09_fifo_data[17] +.sym 4606 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4610 w_rx_09_fifo_data[19] +.sym 4611 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4616 o_led1$SB_IO_OUT +.sym 4618 w_rx_09_fifo_data[22] +.sym 4619 w_rx_24_fifo_data[22] +.sym 4622 w_rx_24_fifo_data[18] +.sym 4623 o_led1$SB_IO_OUT +.sym 4624 w_rx_09_fifo_data[18] +.sym 4630 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4631 w_rx_09_fifo_data[21] +.sym 4634 w_rx_24_fifo_data[16] +.sym 4635 o_led1$SB_IO_OUT +.sym 4636 w_rx_09_fifo_data[16] +.sym 4640 o_led1$SB_IO_OUT +.sym 4642 w_rx_09_fifo_data[17] +.sym 4643 w_rx_24_fifo_data[17] +.sym 4644 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 4645 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4646 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4648 w_rx_fifo_pulled_data[13] -.sym 4652 w_rx_fifo_pulled_data[15] -.sym 4655 rx_fifo.wr_addr[0] -.sym 4658 rx_fifo.wr_addr[0] -.sym 4668 w_rx_fifo_push -.sym 4669 $PACKER_VCC_NET -.sym 4673 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 4676 rx_fifo.wr_addr[5] +.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4648 w_rx_fifo_pulled_data[17] +.sym 4652 w_rx_fifo_pulled_data[19] +.sym 4659 rx_fifo.mem_i.0.1_WDATA +.sym 4660 rx_fifo.wr_addr[5] +.sym 4661 w_rx_09_fifo_data[23] +.sym 4662 o_led1$SB_IO_OUT +.sym 4663 rx_fifo.wr_addr[1] +.sym 4664 rx_fifo.wr_addr[3] +.sym 4665 w_rx_09_fifo_data[21] +.sym 4667 rx_fifo.mem_i.0.1_WDATA_2 +.sym 4668 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 4671 $PACKER_VCC_NET +.sym 4672 rx_fifo.wr_addr[1] +.sym 4673 rx_fifo.mem_q.0.0_WDATA_2 +.sym 4674 rx_fifo.mem_i.0.2_WDATA +.sym 4676 rx_fifo.wr_addr[1] .sym 4678 rx_fifo.wr_addr[3] -.sym 4679 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 4680 rx_fifo.wr_addr[0] -.sym 4681 o_led1$SB_IO_OUT -.sym 4695 tx_fifo.wr_addr_gray_rd[2] -.sym 4696 w_rx_24_fifo_data[4] -.sym 4697 tx_fifo.wr_addr_gray_rd[7] -.sym 4699 w_rx_24_fifo_data[17] -.sym 4701 tx_fifo.wr_addr_gray_rd[1] -.sym 4702 w_rx_24_fifo_data[12] -.sym 4703 w_rx_09_fifo_data[12] -.sym 4709 w_rx_09_fifo_data[17] -.sym 4715 w_rx_09_fifo_data[4] -.sym 4719 o_led1$SB_IO_OUT -.sym 4723 tx_fifo.wr_addr_gray_rd[7] -.sym 4730 tx_fifo.wr_addr_gray_rd[1] -.sym 4733 w_rx_24_fifo_data[17] -.sym 4735 o_led1$SB_IO_OUT -.sym 4736 w_rx_09_fifo_data[17] -.sym 4753 tx_fifo.wr_addr_gray_rd[2] -.sym 4757 o_led1$SB_IO_OUT -.sym 4758 w_rx_24_fifo_data[4] -.sym 4759 w_rx_09_fifo_data[4] -.sym 4763 w_rx_24_fifo_data[12] -.sym 4764 w_rx_09_fifo_data[12] -.sym 4766 o_led1$SB_IO_OUT +.sym 4679 rx_fifo.mem_i.0.2_WDATA_1 +.sym 4680 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 4681 rx_fifo.wr_addr[7] +.sym 4689 w_rx_24_fifo_data[26] +.sym 4690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4692 w_rx_24_fifo_data[17] +.sym 4694 w_rx_09_fifo_data[24] +.sym 4695 o_led1$SB_IO_OUT +.sym 4697 w_rx_09_fifo_data[19] +.sym 4702 w_rx_24_fifo_data[22] +.sym 4704 w_rx_24_fifo_data[24] +.sym 4707 w_rx_24_fifo_data[19] +.sym 4711 w_rx_24_fifo_data[28] +.sym 4715 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4723 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4724 w_rx_24_fifo_data[22] +.sym 4728 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4730 w_rx_24_fifo_data[24] +.sym 4733 w_rx_09_fifo_data[19] +.sym 4734 o_led1$SB_IO_OUT +.sym 4736 w_rx_24_fifo_data[19] +.sym 4740 w_rx_24_fifo_data[17] +.sym 4742 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4745 w_rx_09_fifo_data[24] +.sym 4746 o_led1$SB_IO_OUT +.sym 4747 w_rx_24_fifo_data[24] +.sym 4751 w_rx_24_fifo_data[19] +.sym 4754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4758 w_rx_24_fifo_data[28] +.sym 4759 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4764 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4765 w_rx_24_fifo_data[26] +.sym 4767 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 4768 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4771 w_rx_fifo_pulled_data[4] -.sym 4775 w_rx_fifo_pulled_data[6] -.sym 4782 w_rx_fifo_data[15] -.sym 4784 w_rx_24_fifo_data[15] -.sym 4786 w_rx_24_fifo_data[13] -.sym 4789 w_rx_09_fifo_data[24] -.sym 4790 w_rx_fifo_pull -.sym 4792 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4795 w_rx_fifo_data[17] -.sym 4798 w_rx_fifo_data[7] -.sym 4802 rx_fifo.wr_addr[8] -.sym 4805 o_led1$SB_IO_OUT -.sym 4817 w_rx_24_fifo_data[17] -.sym 4818 o_led1$SB_IO_OUT -.sym 4819 w_rx_09_fifo_data[22] -.sym 4823 w_rx_24_fifo_data[19] -.sym 4827 w_rx_24_fifo_data[2] -.sym 4832 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4833 w_rx_24_fifo_data[20] -.sym 4836 w_rx_24_fifo_data[22] -.sym 4838 w_rx_24_fifo_data[24] -.sym 4840 w_rx_24_fifo_data[26] -.sym 4845 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4846 w_rx_24_fifo_data[2] -.sym 4851 w_rx_24_fifo_data[20] -.sym 4852 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4857 w_rx_24_fifo_data[19] -.sym 4859 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4862 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4863 w_rx_24_fifo_data[22] -.sym 4869 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4870 w_rx_24_fifo_data[17] -.sym 4874 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4875 w_rx_24_fifo_data[24] -.sym 4880 w_rx_24_fifo_data[26] -.sym 4883 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 4886 w_rx_09_fifo_data[22] -.sym 4887 w_rx_24_fifo_data[22] -.sym 4888 o_led1$SB_IO_OUT -.sym 4890 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 4769 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4771 w_rx_fifo_pulled_data[24] +.sym 4775 w_rx_fifo_pulled_data[26] +.sym 4784 w_smi_data_output[0] +.sym 4785 rx_fifo.wr_addr[4] +.sym 4786 rx_fifo.rd_addr[2] +.sym 4790 rx_fifo.rd_addr[6] +.sym 4793 rx_fifo.wr_addr[6] +.sym 4797 rx_fifo.wr_addr[0] +.sym 4801 w_rx_24_fifo_data[21] +.sym 4802 $PACKER_VCC_NET +.sym 4804 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 4805 rx_fifo.mem_q.0.0_WDATA +.sym 4812 w_rx_24_fifo_data[26] +.sym 4816 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4820 w_rx_24_fifo_data[11] +.sym 4821 w_rx_24_fifo_data[5] +.sym 4824 o_led1$SB_IO_OUT +.sym 4826 w_rx_24_fifo_data[7] +.sym 4828 w_rx_09_fifo_data[5] +.sym 4830 w_rx_09_fifo_data[3] +.sym 4832 w_rx_09_fifo_data[26] +.sym 4833 w_rx_09_fifo_data[24] +.sym 4834 w_rx_09_fifo_data[7] +.sym 4837 w_rx_09_fifo_data[11] +.sym 4844 o_led1$SB_IO_OUT +.sym 4845 w_rx_09_fifo_data[11] +.sym 4846 w_rx_24_fifo_data[11] +.sym 4850 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4852 w_rx_09_fifo_data[3] +.sym 4856 o_led1$SB_IO_OUT +.sym 4857 w_rx_09_fifo_data[5] +.sym 4859 w_rx_24_fifo_data[5] +.sym 4863 o_led1$SB_IO_OUT +.sym 4864 w_rx_09_fifo_data[7] +.sym 4865 w_rx_24_fifo_data[7] +.sym 4869 w_rx_24_fifo_data[26] +.sym 4870 o_led1$SB_IO_OUT +.sym 4871 w_rx_09_fifo_data[26] +.sym 4875 w_rx_09_fifo_data[24] +.sym 4876 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4881 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4883 w_rx_09_fifo_data[26] +.sym 4886 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 4888 w_rx_09_fifo_data[5] +.sym 4890 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 4891 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 4892 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4894 w_rx_fifo_pulled_data[5] -.sym 4898 w_rx_fifo_pulled_data[7] -.sym 4905 w_rx_fifo_data[6] -.sym 4909 rx_fifo.wr_addr[6] -.sym 4916 $PACKER_VCC_NET -.sym 4917 rx_fifo.wr_addr[2] -.sym 4918 rx_fifo.wr_addr[4] -.sym 4919 w_rx_fifo_pull -.sym 4920 w_rx_fifo_pulled_data[7] -.sym 4925 rx_fifo.wr_addr[7] -.sym 4927 rx_fifo.wr_addr[8] -.sym 4928 rx_fifo.wr_addr[9] -.sym 4935 w_rx_09_fifo_data[19] -.sym 4938 w_rx_24_fifo_data[19] -.sym 4939 w_rx_24_fifo_data[26] -.sym 4941 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 4943 w_rx_09_fifo_data[26] -.sym 4948 w_rx_24_fifo_data[28] -.sym 4949 w_rx_09_fifo_data[20] -.sym 4950 w_rx_09_fifo_data[22] -.sym 4962 w_rx_09_fifo_data[24] -.sym 4963 o_led1$SB_IO_OUT -.sym 4965 w_rx_09_fifo_data[28] -.sym 4968 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 4969 w_rx_09_fifo_data[20] -.sym 4973 w_rx_09_fifo_data[24] -.sym 4975 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 4979 w_rx_09_fifo_data[28] -.sym 4980 w_rx_24_fifo_data[28] -.sym 4981 o_led1$SB_IO_OUT +.sym 4892 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4894 w_rx_fifo_pulled_data[25] +.sym 4898 w_rx_fifo_pulled_data[27] +.sym 4905 $PACKER_VCC_NET +.sym 4908 rx_fifo.mem_q.0.1_WDATA_3 +.sym 4910 rx_fifo.rd_addr[2] +.sym 4911 rx_fifo.mem_q.0.1_WDATA_1 +.sym 4912 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 4913 rx_fifo.mem_q.0.1_WDATA +.sym 4914 rx_fifo.rd_addr[6] +.sym 4916 rx_fifo.mem_q.0.1_WDATA_2 +.sym 4917 rx_fifo.rd_addr[4] +.sym 4918 rx_fifo.wr_addr[6] +.sym 4920 rx_fifo.wr_addr[4] +.sym 4924 rx_fifo.wr_addr[6] +.sym 4936 w_rx_09_fifo_data[2] +.sym 4937 w_rx_09_fifo_data[3] +.sym 4939 w_rx_09_fifo_data[4] +.sym 4942 w_rx_24_fifo_data[2] +.sym 4943 o_led1$SB_IO_OUT +.sym 4944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4945 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4947 w_rx_24_fifo_data[3] +.sym 4955 w_rx_24_fifo_data[0] +.sym 4956 w_rx_24_fifo_data[4] +.sym 4963 w_rx_24_fifo_data[1] +.sym 4968 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4970 w_rx_24_fifo_data[0] +.sym 4973 w_rx_24_fifo_data[2] +.sym 4974 o_led1$SB_IO_OUT +.sym 4976 w_rx_09_fifo_data[2] +.sym 4979 w_rx_24_fifo_data[3] +.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 4986 o_led1$SB_IO_OUT -.sym 4987 w_rx_24_fifo_data[26] -.sym 4988 w_rx_09_fifo_data[26] -.sym 4991 w_rx_09_fifo_data[22] -.sym 4994 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 4998 w_rx_09_fifo_data[28] -.sym 4999 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5003 o_led1$SB_IO_OUT -.sym 5004 w_rx_09_fifo_data[19] -.sym 5005 w_rx_24_fifo_data[19] -.sym 5009 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5012 w_rx_09_fifo_data[26] -.sym 5013 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 4987 w_rx_09_fifo_data[3] +.sym 4988 w_rx_24_fifo_data[3] +.sym 4991 w_rx_24_fifo_data[4] +.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 4998 w_rx_24_fifo_data[1] +.sym 5004 w_rx_24_fifo_data[2] +.sym 5006 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 5010 o_led1$SB_IO_OUT +.sym 5011 w_rx_09_fifo_data[4] +.sym 5012 w_rx_24_fifo_data[4] +.sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5014 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5015 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5017 w_rx_fifo_pulled_data[0] -.sym 5021 w_rx_fifo_pulled_data[2] -.sym 5028 w_rx_fifo_data[5] -.sym 5030 w_rx_09_fifo_data[30] -.sym 5034 w_rx_fifo_data[28] -.sym 5036 w_rx_fifo_data[26] -.sym 5038 w_rx_fifo_data[23] -.sym 5039 $PACKER_VCC_NET -.sym 5040 $PACKER_VCC_NET -.sym 5041 w_rx_fifo_data[1] -.sym 5042 rx_fifo.wr_addr[6] -.sym 5044 rx_fifo.wr_addr[4] -.sym 5046 w_rx_fifo_data[18] -.sym 5049 o_led1$SB_IO_OUT -.sym 5050 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 5058 w_rx_09_fifo_data[2] -.sym 5063 w_rx_09_fifo_data[18] -.sym 5067 w_rx_09_fifo_data[3] -.sym 5070 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5073 o_led1$SB_IO_OUT -.sym 5074 w_rx_24_fifo_data[0] -.sym 5075 w_rx_24_fifo_data[14] -.sym 5077 w_rx_24_fifo_data[2] -.sym 5079 w_rx_24_fifo_data[3] -.sym 5083 w_rx_24_fifo_data[16] -.sym 5084 w_rx_24_fifo_data[18] -.sym 5085 w_rx_24_fifo_data[1] -.sym 5087 o_led1$SB_IO_OUT -.sym 5096 w_rx_09_fifo_data[2] -.sym 5097 w_rx_24_fifo_data[2] -.sym 5099 o_led1$SB_IO_OUT -.sym 5102 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5104 w_rx_24_fifo_data[14] -.sym 5108 w_rx_24_fifo_data[16] -.sym 5111 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5116 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5117 w_rx_24_fifo_data[0] -.sym 5120 w_rx_09_fifo_data[3] -.sym 5121 o_led1$SB_IO_OUT -.sym 5123 w_rx_24_fifo_data[3] -.sym 5126 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5127 w_rx_24_fifo_data[1] -.sym 5132 o_led1$SB_IO_OUT -.sym 5133 w_rx_09_fifo_data[18] -.sym 5135 w_rx_24_fifo_data[18] -.sym 5136 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 5017 w_rx_fifo_pulled_data[8] +.sym 5021 w_rx_fifo_pulled_data[10] +.sym 5029 rx_fifo.rd_addr[7] +.sym 5030 rx_fifo.rd_addr[2] +.sym 5031 rx_fifo.rd_addr[3] +.sym 5032 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 5033 o_led1$SB_IO_OUT +.sym 5034 rx_fifo.wr_addr[7] +.sym 5035 rx_fifo.rd_addr[8] +.sym 5036 rx_fifo.wr_addr[6] +.sym 5037 rx_fifo.wr_addr[5] +.sym 5038 rx_fifo.wr_addr[4] +.sym 5041 rx_fifo.rd_addr[5] +.sym 5043 rx_fifo.rd_addr[6] +.sym 5045 rx_fifo.mem_q.0.2_WDATA +.sym 5047 rx_fifo.rd_addr[1] +.sym 5049 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 5051 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5086 rx_fifo.rd_addr[9] +.sym 5090 rx_fifo.rd_addr[9] .sym 5137 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5138 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5140 w_rx_fifo_pulled_data[1] -.sym 5144 w_rx_fifo_pulled_data[3] -.sym 5150 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5152 $PACKER_VCC_NET -.sym 5155 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 5156 w_rx_fifo_data[21] -.sym 5160 w_rx_fifo_push -.sym 5164 rx_fifo.wr_addr[0] -.sym 5165 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5166 w_rx_fifo_data[19] -.sym 5168 rx_fifo.wr_addr[5] -.sym 5171 rx_fifo.wr_addr[2] -.sym 5173 o_led1$SB_IO_OUT +.sym 5140 w_rx_fifo_pulled_data[9] +.sym 5144 w_rx_fifo_pulled_data[11] +.sym 5153 rx_fifo.wr_addr[5] +.sym 5154 rx_fifo.wr_addr[1] +.sym 5158 rx_fifo.wr_addr[3] +.sym 5159 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 5163 rx_fifo.mem_q.0.0_WDATA_1 +.sym 5164 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 5165 o_led1$SB_IO_OUT +.sym 5166 rx_fifo.wr_addr[7] +.sym 5167 io_pmod[7]$SB_IO_IN +.sym 5168 rx_fifo.wr_addr[1] +.sym 5170 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 5172 rx_fifo.wr_addr[7] +.sym 5173 rx_fifo.mem_q.0.0_WDATA_2 .sym 5174 rx_fifo.wr_addr[3] -.sym 5191 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5192 w_rx_09_fifo_data[0] -.sym 5195 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 5200 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 5201 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5208 w_rx_24_fifo_data[0] -.sym 5209 o_led1$SB_IO_OUT -.sym 5214 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5237 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 5246 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 5250 w_rx_24_fifo_data[0] -.sym 5251 o_led1$SB_IO_OUT -.sym 5252 w_rx_09_fifo_data[0] -.sym 5259 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5260 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5263 w_rx_fifo_pulled_data[16] -.sym 5267 w_rx_fifo_pulled_data[18] -.sym 5274 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 5276 rx_fifo.wr_addr[8] -.sym 5278 w_rx_fifo_data[27] -.sym 5283 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 5284 rx_fifo.wr_addr[7] -.sym 5286 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 5287 $PACKER_GND_NET -.sym 5288 w_rx_fifo_data[17] -.sym 5290 rx_fifo.wr_addr[0] -.sym 5292 rx_fifo.wr_addr_gray[5] -.sym 5293 rx_fifo.wr_addr[8] -.sym 5296 rx_fifo.wr_addr[6] -.sym 5297 o_led1$SB_IO_OUT -.sym 5303 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 5305 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5309 rx_fifo.wr_addr[0] -.sym 5312 rx_fifo.rd_addr_gray_wr_r[2] -.sym 5320 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5330 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 5331 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5332 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 5333 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5336 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 5344 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5349 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5357 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 5360 rx_fifo.rd_addr_gray_wr_r[2] -.sym 5362 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 5368 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5372 rx_fifo.wr_addr[0] -.sym 5378 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 5382 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5183 o_led1$SB_IO_OUT +.sym 5184 rx_fifo.wr_addr[9] +.sym 5204 w_rx_09_fifo_data[1] +.sym 5205 rx_fifo.wr_addr_gray_rd[9] +.sym 5209 w_rx_24_fifo_data[1] +.sym 5220 rx_fifo.wr_addr[9] +.sym 5234 rx_fifo.wr_addr_gray_rd[9] +.sym 5238 w_rx_09_fifo_data[1] +.sym 5239 w_rx_24_fifo_data[1] +.sym 5240 o_led1$SB_IO_OUT +.sym 5260 r_counter_$glb_clk +.sym 5263 w_rx_fifo_pulled_data[0] +.sym 5267 w_rx_fifo_pulled_data[2] +.sym 5275 rx_fifo.rd_addr[0] +.sym 5277 rx_fifo.rd_addr[6] +.sym 5278 rx_fifo.rd_addr[2] +.sym 5281 rx_fifo.rd_addr[7] +.sym 5282 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5293 rx_fifo.mem_q.0.0_WDATA +.sym 5296 rx_fifo.wr_addr[0] +.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5303 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5304 w_rx_24_fifo_data[0] +.sym 5305 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 5306 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 5307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 5309 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 5310 w_rx_09_fifo_data[0] +.sym 5311 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5312 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.sym 5313 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 5314 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5316 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 5318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 5319 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.sym 5322 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.sym 5323 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] +.sym 5325 o_led1$SB_IO_OUT +.sym 5326 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.sym 5327 io_pmod[7]$SB_IO_IN +.sym 5330 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.sym 5336 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 5342 w_rx_09_fifo_data[0] +.sym 5344 w_rx_24_fifo_data[0] +.sym 5345 o_led1$SB_IO_OUT +.sym 5348 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5350 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 5351 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 5354 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 5355 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] +.sym 5356 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 5357 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.sym 5361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 5362 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5367 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 5368 io_pmod[7]$SB_IO_IN +.sym 5369 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 5373 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.sym 5374 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.sym 5375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.sym 5378 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 5382 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E .sym 5383 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5386 w_rx_fifo_pulled_data[17] -.sym 5390 w_rx_fifo_pulled_data[19] -.sym 5398 rx_fifo.rd_addr_gray_wr_r[2] -.sym 5399 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5401 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 5403 rx_fifo.wr_addr[4] -.sym 5405 rx_fifo.wr_addr[3] -.sym 5410 rx_fifo.wr_addr[4] -.sym 5411 w_rx_fifo_pull -.sym 5412 rx_fifo.wr_addr[9] -.sym 5413 rx_fifo.rd_addr[3] -.sym 5414 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5415 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 5417 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 5418 rx_fifo.wr_addr[0] -.sym 5426 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 5427 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] -.sym 5429 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 5430 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5431 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 5432 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 5433 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 5434 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 5435 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 5436 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5438 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] -.sym 5439 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] -.sym 5440 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5441 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] -.sym 5442 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] -.sym 5443 rx_fifo.wr_addr[2] -.sym 5445 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 5446 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 5449 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 5450 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 5451 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5453 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] -.sym 5454 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 5456 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 5457 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 5460 rx_fifo.wr_addr[2] -.sym 5462 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 5465 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 5466 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 5467 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 5468 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 5472 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5474 rx_fifo.rd_addr_gray_wr_r[5] -.sym 5477 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 5478 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5479 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 5480 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] -.sym 5483 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 5484 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 5485 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] -.sym 5486 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 5489 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] -.sym 5490 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 5491 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 5492 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5495 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 5496 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 5497 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] -.sym 5498 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 5501 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 5502 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 5503 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] -.sym 5504 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] -.sym 5506 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5507 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5524 w_rx_fifo_full -.sym 5532 $PACKER_VCC_NET -.sym 5535 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 5536 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 5537 $PACKER_VCC_NET -.sym 5539 i_rst_b$SB_IO_IN -.sym 5549 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5551 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 5552 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 5554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 5555 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 5558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 5562 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 5563 rx_fifo.rd_addr_gray_wr_r[2] -.sym 5564 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 5565 w_rx_24_fifo_data[28] -.sym 5566 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5567 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5570 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 5572 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 5573 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 5574 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5575 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] -.sym 5577 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5578 rx_fifo.wr_addr[0] -.sym 5579 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5582 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 5583 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] -.sym 5584 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 5585 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 5588 rx_fifo.rd_addr_gray_wr_r[2] -.sym 5591 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5594 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 5595 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 5596 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 5597 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 5600 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 5602 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 5606 w_rx_24_fifo_data[28] -.sym 5608 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5612 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5615 rx_fifo.wr_addr[0] -.sym 5618 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5619 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 5620 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 5621 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 5625 rx_fifo.wr_addr[0] -.sym 5627 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5628 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 5386 w_rx_fifo_pulled_data[1] +.sym 5390 w_rx_fifo_pulled_data[3] +.sym 5397 rx_fifo.rd_addr[9] +.sym 5398 w_rx_24_fifo_data[0] +.sym 5399 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5401 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 5402 $PACKER_VCC_NET +.sym 5406 $PACKER_VCC_NET +.sym 5407 rx_fifo.rd_addr_gray[0] +.sym 5410 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5412 rx_fifo.rd_addr[4] +.sym 5413 rx_fifo.wr_addr[6] +.sym 5414 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5415 rx_fifo.wr_addr[4] +.sym 5416 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5419 rx_fifo.wr_addr[8] +.sym 5420 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5427 rx_fifo.wr_addr[1] +.sym 5429 rx_fifo.wr_addr[4] +.sym 5431 rx_fifo.wr_addr[7] +.sym 5435 rx_fifo.wr_addr[6] +.sym 5437 rx_fifo.wr_addr[5] +.sym 5438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 5439 rx_fifo.wr_addr[0] +.sym 5440 rx_fifo.wr_addr[3] +.sym 5458 $nextpnr_ICESTORM_LC_8$O +.sym 5461 rx_fifo.wr_addr[0] +.sym 5464 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 5467 rx_fifo.wr_addr[1] +.sym 5468 rx_fifo.wr_addr[0] +.sym 5470 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5472 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 5476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 5479 rx_fifo.wr_addr[3] +.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5482 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5484 rx_fifo.wr_addr[4] +.sym 5486 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 5488 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5490 rx_fifo.wr_addr[5] +.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5494 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 5497 rx_fifo.wr_addr[6] +.sym 5498 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5500 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5503 rx_fifo.wr_addr[7] +.sym 5504 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 5523 rx_fifo.rd_addr[2] +.sym 5526 rx_fifo.rd_addr[7] +.sym 5527 rx_fifo.rd_addr[1] +.sym 5528 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5529 rx_fifo.rd_addr[3] +.sym 5530 rx_fifo.rd_addr[0] +.sym 5532 rx_fifo.rd_addr_gray[8] +.sym 5534 rx_fifo.rd_addr[5] +.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5536 rx_fifo.rd_addr[6] +.sym 5544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 5552 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5554 rx_fifo.wr_addr[0] +.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 5560 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5561 rx_fifo.wr_addr[9] +.sym 5562 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5579 rx_fifo.wr_addr[8] +.sym 5581 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5583 rx_fifo.wr_addr[8] +.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5590 rx_fifo.wr_addr[9] +.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5594 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5600 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5603 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5608 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 5614 rx_fifo.wr_addr[0] +.sym 5620 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5621 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5624 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5627 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5628 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O .sym 5629 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5630 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5646 $PACKER_VCC_NET -.sym 5649 rx_fifo.rd_addr_gray_wr[2] -.sym 5653 rx_fifo.wr_addr_gray_rd[8] -.sym 5655 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 5656 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 5658 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 5662 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 5664 o_led1$SB_IO_OUT -.sym 5666 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5672 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 5674 w_rx_fifo_full -.sym 5675 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 5676 rx_fifo.rd_addr_gray_wr[4] -.sym 5679 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 5680 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 5683 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5684 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5685 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5686 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 5688 w_rx_fifo_push -.sym 5689 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 5695 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 5696 rx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 5697 rx_fifo.rd_addr_gray_wr[2] -.sym 5701 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 5706 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 5707 w_rx_fifo_full -.sym 5708 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5711 rx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 5712 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 5713 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 5714 w_rx_fifo_push -.sym 5718 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 5719 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 5720 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 5723 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 5729 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 5731 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 5743 rx_fifo.rd_addr_gray_wr[2] -.sym 5748 rx_fifo.rd_addr_gray_wr[4] +.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5645 rx_fifo.wr_addr[0] +.sym 5649 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5651 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5653 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 5654 w_rx_fifo_full +.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 5661 $PACKER_VCC_NET +.sym 5662 $PACKER_VCC_NET +.sym 5672 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5673 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5674 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 5677 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 5678 rx_fifo.rd_addr_gray_wr[8] +.sym 5679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 5681 rx_fifo.rd_addr_gray_wr[5] +.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 5687 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 5689 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 5690 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5692 rx_fifo.rd_addr_gray[8] +.sym 5693 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5696 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 5697 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5700 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 5703 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 5705 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 5706 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5711 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 5712 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5714 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5717 rx_fifo.rd_addr_gray_wr[8] +.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 5729 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5730 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 5731 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 5738 rx_fifo.rd_addr_gray_wr[5] +.sym 5743 rx_fifo.rd_addr_gray[8] +.sym 5747 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5748 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5749 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 5750 rx_fifo.rd_addr_gray_wr_r[8] .sym 5752 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5768 w_rx_fifo_full -.sym 5770 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 5772 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5786 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 5789 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 5797 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 5798 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 5800 w_rx_fifo_push -.sym 5802 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5808 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 5809 i_rst_b$SB_IO_IN -.sym 5815 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 5822 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5823 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 5843 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 5846 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 5848 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5849 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5852 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 5853 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5854 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 5865 i_rst_b$SB_IO_IN -.sym 5867 w_rx_fifo_push -.sym 5870 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 5872 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5873 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5874 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 5766 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5773 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 5776 rx_fifo.wr_addr[9] +.sym 5777 rx_fifo.rd_addr_gray_wr[5] +.sym 5780 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 5786 $PACKER_VCC_NET +.sym 5789 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 5797 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 5798 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 5799 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 5800 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5801 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 5803 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 5804 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 5805 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5806 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 5807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5808 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 5814 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5815 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5819 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5821 w_lvds_rx_24_d1 +.sym 5826 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5828 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 5829 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 5831 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5840 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 5841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 5842 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 5843 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 5847 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 5852 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5853 w_lvds_rx_24_d1 +.sym 5854 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5866 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 5867 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5874 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 5875 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5876 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5893 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 5897 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5904 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5912 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5918 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 5920 w_lvds_rx_24_d1 -.sym 5921 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 5931 w_lvds_rx_24_d0 -.sym 5941 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5963 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 5964 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 5965 w_lvds_rx_24_d1 -.sym 5966 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 5970 w_lvds_rx_24_d0 -.sym 5997 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce +.sym 5892 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 5895 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5896 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 5898 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5900 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 5919 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 5921 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5922 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 5926 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5927 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 5929 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 5930 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 5932 $PACKER_VCC_NET +.sym 5933 $PACKER_VCC_NET +.sym 5936 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 5941 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5945 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 5947 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 5950 $nextpnr_ICESTORM_LC_2$O +.sym 5952 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 5956 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 5957 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5958 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 5959 $PACKER_VCC_NET +.sym 5960 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 5963 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 5964 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5965 $PACKER_VCC_NET +.sym 5966 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 5969 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5970 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 5971 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5972 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 5978 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5981 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 5988 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 5989 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 5990 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 5994 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 5995 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E .sym 5998 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6017 w_rx_fifo_push -.sym 6029 $PACKER_VCC_NET -.sym 6030 $PACKER_VCC_NET -.sym 6044 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6047 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6048 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6050 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 6051 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 6057 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6059 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 6060 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6062 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6064 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 6066 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 6068 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6070 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6074 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6075 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6076 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6086 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6087 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 6088 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6089 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6092 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 6093 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6094 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6095 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6098 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6100 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 6101 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6104 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6105 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6106 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6107 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6110 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 6111 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 6112 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 6113 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 6120 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 6042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6043 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 6044 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6050 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6051 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 6058 $PACKER_VCC_NET +.sym 6059 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O +.sym 6060 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 6062 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 6063 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6066 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 6070 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 6072 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 6073 $nextpnr_ICESTORM_LC_0$O +.sym 6075 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 6079 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 6080 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6081 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 6082 $PACKER_VCC_NET +.sym 6083 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 6086 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6087 $PACKER_VCC_NET +.sym 6088 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 6089 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 6092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6094 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 6095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6106 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 6110 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 6111 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 6112 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6113 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 6117 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 6120 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O .sym 6121 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6135 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 6151 o_led1$SB_IO_OUT -.sym 6152 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 6168 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6169 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6175 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6178 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6189 $PACKER_VCC_NET -.sym 6190 $PACKER_VCC_NET -.sym 6191 lvds_rx_24_inst.r_phase_count[1] -.sym 6192 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6196 $nextpnr_ICESTORM_LC_5$O -.sym 6198 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6202 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 6204 lvds_rx_24_inst.r_phase_count[1] -.sym 6205 $PACKER_VCC_NET -.sym 6206 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6209 $PACKER_VCC_NET -.sym 6211 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6212 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 6217 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6224 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6246 o_led1$SB_IO_OUT -.sym 6257 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] .sym 6294 o_shdn_tx_lna$SB_IO_OUT .sym 6305 o_shdn_tx_lna$SB_IO_OUT -.sym 6346 tx_fifo.wr_addr_gray_rd[3] -.sym 6347 tx_fifo.wr_addr_gray_rd[7] -.sym 6349 tx_fifo.wr_addr_gray_rd[6] -.sym 6351 tx_fifo.wr_addr_gray_rd[1] -.sym 6352 tx_fifo.wr_addr_gray_rd[2] -.sym 6376 o_led1$SB_IO_OUT -.sym 6379 $PACKER_VCC_NET -.sym 6380 w_smi_data_input[7] -.sym 6388 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 6390 rx_fifo.wr_addr[6] -.sym 6391 rx_fifo.wr_addr[0] -.sym 6395 rx_fifo.wr_addr[4] -.sym 6396 rx_fifo.wr_addr[5] +.sym 6346 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 6347 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 6348 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 6349 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 6351 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 6352 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 6353 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 6390 $PACKER_VCC_NET +.sym 6391 rx_fifo.wr_addr[5] +.sym 6393 rx_fifo.wr_addr[7] +.sym 6395 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 6398 rx_fifo.wr_addr[3] -.sym 6399 $PACKER_VCC_NET -.sym 6401 w_rx_fifo_data[8] -.sym 6404 w_rx_fifo_data[10] +.sym 6399 rx_fifo.wr_addr[1] +.sym 6402 rx_fifo.wr_addr[4] +.sym 6404 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O .sym 6405 rx_fifo.wr_addr[9] -.sym 6406 rx_fifo.wr_addr[2] -.sym 6413 w_rx_fifo_push -.sym 6414 rx_fifo.wr_addr[7] +.sym 6408 rx_fifo.mem_q.0.3_WDATA_3 +.sym 6412 rx_fifo.wr_addr[0] +.sym 6413 rx_fifo.wr_addr[6] +.sym 6415 rx_fifo.mem_q.0.3_WDATA_2 .sym 6417 rx_fifo.wr_addr[8] -.sym 6423 tx_fifo.wr_addr_gray[1] -.sym 6425 tx_fifo.wr_addr_gray[3] -.sym 6427 tx_fifo.wr_addr_gray[2] -.sym 6428 tx_fifo.wr_addr_gray[6] -.sym 6429 tx_fifo.wr_addr_gray[7] -.sym 6438 rx_fifo.wr_addr[2] +.sym 6422 w_rx_24_fifo_data[23] +.sym 6423 w_rx_24_fifo_data[20] +.sym 6424 w_rx_24_fifo_data[25] +.sym 6425 rx_fifo.wr_addr[9] +.sym 6426 w_rx_24_fifo_data[31] +.sym 6427 w_rx_24_fifo_data[27] +.sym 6428 w_rx_24_fifo_data[29] +.sym 6429 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 6439 rx_fifo.wr_addr[3] .sym 6441 rx_fifo.wr_addr[4] .sym 6442 rx_fifo.wr_addr[5] @@ -6086,97 +6052,90 @@ .sym 6444 rx_fifo.wr_addr[7] .sym 6445 rx_fifo.wr_addr[8] .sym 6446 rx_fifo.wr_addr[9] -.sym 6447 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6447 rx_fifo.wr_addr[1] .sym 6448 rx_fifo.wr_addr[0] .sym 6449 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6450 w_rx_fifo_push -.sym 6452 w_rx_fifo_data[8] -.sym 6456 w_rx_fifo_data[10] +.sym 6450 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6452 rx_fifo.mem_q.0.3_WDATA_3 +.sym 6456 rx_fifo.mem_q.0.3_WDATA_2 .sym 6459 $PACKER_VCC_NET -.sym 6468 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 6470 rx_fifo.wr_addr[6] -.sym 6472 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 6486 rx_fifo.rd_addr[6] -.sym 6487 rx_fifo.rd_addr[9] -.sym 6489 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6496 w_rx_fifo_pulled_data[10] -.sym 6502 tx_fifo.wr_addr_gray_rd[3] -.sym 6503 rx_fifo.rd_addr[0] -.sym 6505 w_rx_fifo_pulled_data[8] -.sym 6506 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 6507 rx_fifo.rd_addr[3] -.sym 6508 rx_fifo.rd_addr[3] -.sym 6509 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6512 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6513 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6516 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6517 w_rx_fifo_pulled_data[9] +.sym 6470 smi_ctrl_ins.int_cnt_rx[4] +.sym 6486 w_rx_fifo_pulled_data[7] +.sym 6502 smi_ctrl_ins.int_cnt_rx[3] +.sym 6514 w_smi_data_output[6] +.sym 6517 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 6518 rx_fifo.wr_addr[8] +.sym 6519 $PACKER_VCC_NET +.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6531 rx_fifo.rd_addr[3] -.sym 6532 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6535 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6537 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 6541 w_rx_fifo_data[11] -.sym 6542 rx_fifo.rd_addr[9] -.sym 6543 rx_fifo.rd_addr[6] -.sym 6544 w_rx_fifo_data[9] -.sym 6545 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6548 $PACKER_VCC_NET -.sym 6553 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6555 w_rx_fifo_pull -.sym 6556 rx_fifo.rd_addr[0] -.sym 6559 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 6560 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 6562 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 6563 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 6564 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] -.sym 6566 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 6576 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 6533 rx_fifo.rd_addr[0] +.sym 6534 rx_fifo.rd_addr[8] +.sym 6535 rx_fifo.rd_addr[7] +.sym 6537 rx_fifo.rd_addr[2] +.sym 6546 rx_fifo.rd_addr[6] +.sym 6548 rx_fifo.mem_q.0.3_WDATA_1 +.sym 6549 rx_fifo.rd_addr[5] +.sym 6553 rx_fifo.rd_addr[4] +.sym 6555 rx_fifo.rd_addr[1] +.sym 6557 $PACKER_VCC_NET +.sym 6558 rx_fifo.rd_addr[9] +.sym 6559 rx_fifo.mem_q.0.3_WDATA +.sym 6560 rx_fifo.mem_i.0.1_WDATA_3 +.sym 6561 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 6562 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 6563 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 6564 rx_fifo.mem_i.0.1_WDATA +.sym 6565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 6566 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 6567 rx_fifo.mem_i.0.1_WDATA_1 +.sym 6576 rx_fifo.rd_addr[2] .sym 6577 rx_fifo.rd_addr[3] -.sym 6579 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6580 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 6579 rx_fifo.rd_addr[4] +.sym 6580 rx_fifo.rd_addr[5] .sym 6581 rx_fifo.rd_addr[6] -.sym 6582 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6583 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 6582 rx_fifo.rd_addr[7] +.sym 6583 rx_fifo.rd_addr[8] .sym 6584 rx_fifo.rd_addr[9] -.sym 6585 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 6585 rx_fifo.rd_addr[1] .sym 6586 rx_fifo.rd_addr[0] .sym 6587 r_counter_$glb_clk -.sym 6588 w_rx_fifo_pull +.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6589 $PACKER_VCC_NET -.sym 6593 w_rx_fifo_data[11] -.sym 6597 w_rx_fifo_data[9] -.sym 6604 w_rx_fifo_pulled_data[11] -.sym 6607 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 6608 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 6612 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 6613 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 6614 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6615 o_led1$SB_IO_OUT -.sym 6617 rx_fifo.rd_addr[0] -.sym 6619 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6620 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 6622 tx_fifo.wr_addr_gray_rd[4] -.sym 6625 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 6632 w_rx_fifo_push -.sym 6633 rx_fifo.wr_addr[9] -.sym 6634 rx_fifo.wr_addr[2] -.sym 6642 rx_fifo.wr_addr[7] -.sym 6643 $PACKER_VCC_NET -.sym 6645 rx_fifo.wr_addr[8] -.sym 6646 w_rx_fifo_data[14] -.sym 6647 rx_fifo.wr_addr[5] -.sym 6648 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 6649 rx_fifo.wr_addr[3] -.sym 6651 rx_fifo.wr_addr[0] -.sym 6657 rx_fifo.wr_addr[6] -.sym 6659 rx_fifo.wr_addr[4] -.sym 6661 w_rx_fifo_data[12] -.sym 6663 w_rx_24_fifo_data[15] -.sym 6664 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 6665 w_rx_24_fifo_data[7] -.sym 6667 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6668 w_rx_fifo_data[24] -.sym 6678 rx_fifo.wr_addr[2] +.sym 6593 rx_fifo.mem_q.0.3_WDATA +.sym 6597 rx_fifo.mem_q.0.3_WDATA_1 +.sym 6607 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6612 rx_fifo.mem_i.0.2_WDATA +.sym 6614 rx_fifo.wr_addr[9] +.sym 6617 rx_fifo.rd_addr[7] +.sym 6619 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 6620 i_rst_b$SB_IO_IN +.sym 6622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 6623 $PACKER_VCC_NET +.sym 6624 rx_fifo.rd_addr[9] +.sym 6625 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 6630 rx_fifo.wr_addr[4] +.sym 6631 rx_fifo.wr_addr[9] +.sym 6632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6634 rx_fifo.mem_i.0.0_WDATA_2 +.sym 6636 rx_fifo.mem_i.0.0_WDATA_3 +.sym 6637 rx_fifo.wr_addr[0] +.sym 6641 rx_fifo.wr_addr[6] +.sym 6642 rx_fifo.wr_addr[5] +.sym 6644 rx_fifo.wr_addr[3] +.sym 6645 rx_fifo.wr_addr[1] +.sym 6650 $PACKER_VCC_NET +.sym 6659 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 6660 rx_fifo.wr_addr[7] +.sym 6661 rx_fifo.wr_addr[8] +.sym 6662 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 6663 w_smi_data_output[0] +.sym 6664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 6665 w_smi_data_output[6] +.sym 6666 w_smi_data_output[1] +.sym 6667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 6668 w_smi_data_output[3] +.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 6678 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 6679 rx_fifo.wr_addr[3] .sym 6681 rx_fifo.wr_addr[4] .sym 6682 rx_fifo.wr_addr[5] @@ -6184,88 +6143,79 @@ .sym 6684 rx_fifo.wr_addr[7] .sym 6685 rx_fifo.wr_addr[8] .sym 6686 rx_fifo.wr_addr[9] -.sym 6687 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6687 rx_fifo.wr_addr[1] .sym 6688 rx_fifo.wr_addr[0] .sym 6689 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6690 w_rx_fifo_push -.sym 6692 w_rx_fifo_data[12] -.sym 6696 w_rx_fifo_data[14] +.sym 6690 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6692 rx_fifo.mem_i.0.0_WDATA_3 +.sym 6696 rx_fifo.mem_i.0.0_WDATA_2 .sym 6699 $PACKER_VCC_NET -.sym 6706 w_rx_fifo_pulled_data[14] -.sym 6708 w_rx_fifo_pulled_data[12] -.sym 6710 tx_fifo.rd_addr_gray_wr[5] -.sym 6715 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 6716 rx_fifo.rd_addr[6] -.sym 6718 w_rx_fifo_pulled_data[15] -.sym 6721 rx_fifo.rd_addr[6] -.sym 6723 rx_fifo.rd_addr[9] -.sym 6724 rx_fifo.rd_addr[6] -.sym 6726 w_rx_fifo_pulled_data[13] -.sym 6727 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 6734 rx_fifo.rd_addr[6] -.sym 6736 $PACKER_VCC_NET -.sym 6740 rx_fifo.rd_addr[3] -.sym 6741 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 6742 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6743 w_rx_fifo_pull -.sym 6745 w_rx_fifo_data[15] -.sym 6746 rx_fifo.rd_addr[9] -.sym 6747 w_rx_fifo_data[13] -.sym 6748 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6751 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6752 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6755 rx_fifo.rd_addr[0] -.sym 6763 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 6770 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 6771 w_rx_fifo_data[29] -.sym 6780 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 6704 smi_ctrl_ins.int_cnt_rx[3] +.sym 6712 w_rx_24_fifo_data[21] +.sym 6713 rx_fifo.wr_addr[0] +.sym 6720 rx_fifo.wr_addr[5] +.sym 6721 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 6723 w_rx_fifo_pulled_data[5] +.sym 6734 rx_fifo.mem_i.0.0_WDATA +.sym 6737 rx_fifo.rd_addr[5] +.sym 6738 rx_fifo.rd_addr[1] +.sym 6743 rx_fifo.rd_addr[6] +.sym 6744 rx_fifo.rd_addr[0] +.sym 6746 rx_fifo.rd_addr[3] +.sym 6747 rx_fifo.rd_addr[2] +.sym 6748 rx_fifo.rd_addr[4] +.sym 6750 rx_fifo.rd_addr[8] +.sym 6755 rx_fifo.rd_addr[7] +.sym 6759 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6761 $PACKER_VCC_NET +.sym 6762 rx_fifo.rd_addr[9] +.sym 6763 rx_fifo.mem_i.0.0_WDATA_1 +.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 6780 rx_fifo.rd_addr[2] .sym 6781 rx_fifo.rd_addr[3] -.sym 6783 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6784 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 6783 rx_fifo.rd_addr[4] +.sym 6784 rx_fifo.rd_addr[5] .sym 6785 rx_fifo.rd_addr[6] -.sym 6786 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6787 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 6786 rx_fifo.rd_addr[7] +.sym 6787 rx_fifo.rd_addr[8] .sym 6788 rx_fifo.rd_addr[9] -.sym 6789 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 6789 rx_fifo.rd_addr[1] .sym 6790 rx_fifo.rd_addr[0] .sym 6791 r_counter_$glb_clk -.sym 6792 w_rx_fifo_pull +.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6793 $PACKER_VCC_NET -.sym 6797 w_rx_fifo_data[15] -.sym 6801 w_rx_fifo_data[13] -.sym 6806 i_rst_b_SB_LUT4_I3_O -.sym 6809 w_rx_24_fifo_data[7] -.sym 6810 w_rx_24_fifo_data[5] -.sym 6811 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 6813 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 6815 w_rx_fifo_pulled_data[7] -.sym 6817 rx_fifo.wr_addr[7] -.sym 6819 w_rx_24_fifo_data[30] -.sym 6820 w_rx_fifo_pulled_data[10] -.sym 6821 w_rx_fifo_pulled_data[8] -.sym 6834 rx_fifo.wr_addr[4] -.sym 6835 rx_fifo.wr_addr[5] -.sym 6836 w_rx_fifo_push +.sym 6797 rx_fifo.mem_i.0.0_WDATA +.sym 6801 rx_fifo.mem_i.0.0_WDATA_1 +.sym 6807 w_smi_data_output[3] +.sym 6809 smi_ctrl_ins.int_cnt_rx[3] +.sym 6813 smi_ctrl_ins.int_cnt_rx[3] +.sym 6819 smi_ctrl_ins.int_cnt_rx[4] +.sym 6821 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6825 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6827 smi_ctrl_ins.int_cnt_rx[3] +.sym 6829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 6834 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 6836 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O .sym 6837 rx_fifo.wr_addr[3] -.sym 6838 $PACKER_VCC_NET -.sym 6839 rx_fifo.wr_addr[0] -.sym 6845 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 6847 w_rx_fifo_data[6] -.sym 6849 rx_fifo.wr_addr[6] -.sym 6854 rx_fifo.wr_addr[2] -.sym 6856 w_rx_fifo_data[4] -.sym 6857 rx_fifo.wr_addr[9] -.sym 6859 rx_fifo.wr_addr[8] -.sym 6862 rx_fifo.wr_addr[7] -.sym 6866 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 6867 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 6868 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] -.sym 6869 w_rx_fifo_data[30] -.sym 6870 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] -.sym 6871 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 6872 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 6873 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] -.sym 6882 rx_fifo.wr_addr[2] +.sym 6838 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6843 rx_fifo.wr_addr[1] +.sym 6847 $PACKER_VCC_NET +.sym 6848 rx_fifo.wr_addr[7] +.sym 6854 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6855 rx_fifo.wr_addr[9] +.sym 6858 rx_fifo.wr_addr[5] +.sym 6860 rx_fifo.wr_addr[0] +.sym 6861 rx_fifo.wr_addr[8] +.sym 6863 rx_fifo.wr_addr[6] +.sym 6865 rx_fifo.wr_addr[4] +.sym 6868 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 6882 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 6883 rx_fifo.wr_addr[3] .sym 6885 rx_fifo.wr_addr[4] .sym 6886 rx_fifo.wr_addr[5] @@ -6273,89 +6223,92 @@ .sym 6888 rx_fifo.wr_addr[7] .sym 6889 rx_fifo.wr_addr[8] .sym 6890 rx_fifo.wr_addr[9] -.sym 6891 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6891 rx_fifo.wr_addr[1] .sym 6892 rx_fifo.wr_addr[0] .sym 6893 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6894 w_rx_fifo_push -.sym 6896 w_rx_fifo_data[4] -.sym 6900 w_rx_fifo_data[6] +.sym 6894 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 6896 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6900 rx_fifo.mem_i.0.2_WDATA_2 .sym 6903 $PACKER_VCC_NET -.sym 6904 o_led1$SB_IO_OUT -.sym 6907 o_led1$SB_IO_OUT -.sym 6908 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 6910 w_rx_fifo_push -.sym 6911 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 6913 w_rx_fifo_data[29] -.sym 6915 rx_fifo.wr_addr[4] -.sym 6919 $PACKER_VCC_NET -.sym 6921 rx_fifo.rd_addr[3] -.sym 6922 w_rx_fifo_pulled_data[1] -.sym 6923 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6925 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6927 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 6929 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6930 w_rx_fifo_pulled_data[5] -.sym 6931 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 6936 w_rx_fifo_data[7] +.sym 6908 rx_fifo.rd_addr[5] +.sym 6910 rx_fifo.rd_addr[3] +.sym 6912 rx_fifo.rd_addr[6] +.sym 6914 rx_fifo.rd_addr[0] +.sym 6916 rx_fifo.rd_addr[1] +.sym 6917 w_rx_fifo_pulled_data[6] +.sym 6918 w_rx_24_fifo_data[28] +.sym 6920 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 6921 rx_fifo.wr_addr[9] +.sym 6923 rx_fifo.wr_addr[8] +.sym 6924 rx_fifo.rd_addr[9] +.sym 6927 rx_fifo.wr_addr[8] +.sym 6929 rx_fifo.mem_q.0.2_WDATA_1 +.sym 6936 rx_fifo.rd_addr[8] +.sym 6938 rx_fifo.mem_i.0.2_WDATA .sym 6940 $PACKER_VCC_NET -.sym 6944 rx_fifo.rd_addr[3] -.sym 6945 rx_fifo.rd_addr[6] -.sym 6946 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 6948 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6949 w_rx_fifo_data[5] -.sym 6950 rx_fifo.rd_addr[9] -.sym 6952 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 6954 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 6956 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6959 rx_fifo.rd_addr[0] -.sym 6963 w_rx_fifo_pull -.sym 6967 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 6972 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 6984 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 6941 rx_fifo.rd_addr[9] +.sym 6945 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6948 rx_fifo.rd_addr[7] +.sym 6950 rx_fifo.rd_addr[3] +.sym 6951 rx_fifo.rd_addr[2] +.sym 6952 rx_fifo.rd_addr[1] +.sym 6957 rx_fifo.rd_addr[5] +.sym 6961 rx_fifo.rd_addr[4] +.sym 6963 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6966 rx_fifo.rd_addr[0] +.sym 6967 rx_fifo.rd_addr[6] +.sym 6969 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 6970 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 6972 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 6973 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 6974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 6975 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 6984 rx_fifo.rd_addr[2] .sym 6985 rx_fifo.rd_addr[3] -.sym 6987 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 6988 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 6987 rx_fifo.rd_addr[4] +.sym 6988 rx_fifo.rd_addr[5] .sym 6989 rx_fifo.rd_addr[6] -.sym 6990 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 6991 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 6990 rx_fifo.rd_addr[7] +.sym 6991 rx_fifo.rd_addr[8] .sym 6992 rx_fifo.rd_addr[9] -.sym 6993 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 6993 rx_fifo.rd_addr[1] .sym 6994 rx_fifo.rd_addr[0] .sym 6995 r_counter_$glb_clk -.sym 6996 w_rx_fifo_pull +.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6997 $PACKER_VCC_NET -.sym 7001 w_rx_fifo_data[7] -.sym 7005 w_rx_fifo_data[5] -.sym 7014 i_rst_b$SB_IO_IN -.sym 7016 o_led1$SB_IO_OUT -.sym 7017 rx_fifo.wr_addr[0] -.sym 7022 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7023 o_led1$SB_IO_OUT -.sym 7025 rx_fifo.rd_addr[0] -.sym 7030 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7032 w_rx_fifo_pulled_data[18] -.sym 7033 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 7040 w_rx_fifo_push +.sym 7001 rx_fifo.mem_i.0.2_WDATA +.sym 7005 rx_fifo.mem_i.0.2_WDATA_1 +.sym 7011 $PACKER_VCC_NET +.sym 7015 rx_fifo.wr_addr[3] +.sym 7017 io_pmod[7]$SB_IO_IN +.sym 7021 i_rst_b_SB_LUT4_I3_O +.sym 7022 $PACKER_VCC_NET +.sym 7024 rx_fifo.rd_addr[7] +.sym 7026 rx_fifo.wr_addr[9] +.sym 7027 i_rst_b$SB_IO_IN +.sym 7028 rx_fifo.rd_addr[3] +.sym 7029 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 7031 rx_fifo.rd_addr[9] .sym 7042 $PACKER_VCC_NET -.sym 7045 rx_fifo.wr_addr[9] -.sym 7047 w_rx_fifo_data[2] -.sym 7049 rx_fifo.wr_addr[6] -.sym 7051 rx_fifo.wr_addr[4] -.sym 7054 rx_fifo.wr_addr[2] -.sym 7055 rx_fifo.wr_addr[5] -.sym 7059 rx_fifo.wr_addr[0] -.sym 7060 w_rx_fifo_data[0] -.sym 7061 rx_fifo.wr_addr[3] -.sym 7065 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 7066 rx_fifo.wr_addr[7] -.sym 7067 rx_fifo.wr_addr[8] -.sym 7070 rx_fifo.rd_addr[3] -.sym 7071 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 7072 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7074 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 7075 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 7076 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7086 rx_fifo.wr_addr[2] +.sym 7044 rx_fifo.wr_addr[1] +.sym 7045 rx_fifo.wr_addr[5] +.sym 7046 rx_fifo.wr_addr[3] +.sym 7048 rx_fifo.wr_addr[0] +.sym 7049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 7051 rx_fifo.wr_addr[6] +.sym 7053 rx_fifo.wr_addr[4] +.sym 7059 rx_fifo.wr_addr[9] +.sym 7060 rx_fifo.mem_q.0.2_WDATA_3 +.sym 7061 rx_fifo.wr_addr[7] +.sym 7063 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7065 rx_fifo.wr_addr[8] +.sym 7067 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 7073 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 7077 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 7086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 7087 rx_fifo.wr_addr[3] .sym 7089 rx_fifo.wr_addr[4] .sym 7090 rx_fifo.wr_addr[5] @@ -6363,90 +6316,86 @@ .sym 7092 rx_fifo.wr_addr[7] .sym 7093 rx_fifo.wr_addr[8] .sym 7094 rx_fifo.wr_addr[9] -.sym 7095 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 7095 rx_fifo.wr_addr[1] .sym 7096 rx_fifo.wr_addr[0] .sym 7097 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7098 w_rx_fifo_push -.sym 7100 w_rx_fifo_data[0] -.sym 7104 w_rx_fifo_data[2] +.sym 7098 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 7100 rx_fifo.mem_q.0.2_WDATA_3 +.sym 7104 rx_fifo.mem_q.0.2_WDATA_2 .sym 7107 $PACKER_VCC_NET -.sym 7114 w_rx_fifo_pulled_data[2] -.sym 7115 rx_fifo.wr_addr[6] -.sym 7116 w_rx_fifo_pulled_data[0] -.sym 7119 rx_fifo.wr_addr[0] -.sym 7124 rx_fifo.rd_addr[6] -.sym 7129 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7130 rx_fifo.rd_addr[0] -.sym 7131 rx_fifo.rd_addr[9] -.sym 7134 w_rx_fifo_pulled_data[19] -.sym 7144 $PACKER_VCC_NET -.sym 7147 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 7149 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7151 w_rx_fifo_pull -.sym 7153 w_rx_fifo_data[1] -.sym 7154 rx_fifo.rd_addr[9] -.sym 7157 rx_fifo.rd_addr[0] -.sym 7158 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 7160 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 7162 rx_fifo.rd_addr[6] -.sym 7164 rx_fifo.rd_addr[3] -.sym 7166 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7169 w_rx_fifo_data[3] -.sym 7171 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 7172 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 7173 rx_fifo.rd_addr[0] -.sym 7174 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 7175 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 7177 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 7178 rx_fifo.rd_addr[6] -.sym 7179 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 7188 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 7115 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7118 $PACKER_VCC_NET +.sym 7124 rx_fifo.wr_addr[1] +.sym 7126 w_rx_fifo_pulled_data[1] +.sym 7128 rx_fifo.wr_addr[5] +.sym 7130 rx_fifo.wr_addr[3] +.sym 7134 w_rx_fifo_pulled_data[3] +.sym 7140 rx_fifo.rd_addr[4] +.sym 7142 rx_fifo.rd_addr[8] +.sym 7145 rx_fifo.rd_addr[5] +.sym 7146 rx_fifo.rd_addr[6] +.sym 7148 rx_fifo.rd_addr[7] +.sym 7149 rx_fifo.mem_q.0.2_WDATA +.sym 7151 rx_fifo.rd_addr[1] +.sym 7152 rx_fifo.rd_addr[0] +.sym 7155 rx_fifo.rd_addr[2] +.sym 7156 rx_fifo.mem_q.0.2_WDATA_1 +.sym 7160 $PACKER_VCC_NET +.sym 7166 rx_fifo.rd_addr[3] +.sym 7167 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7168 rx_fifo.rd_addr[9] +.sym 7172 rx_fifo.rd_addr_gray[0] +.sym 7173 rx_fifo.rd_addr_gray[8] +.sym 7174 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 7175 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 7176 rx_fifo.rd_addr[9] +.sym 7177 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 7179 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 7188 rx_fifo.rd_addr[2] .sym 7189 rx_fifo.rd_addr[3] -.sym 7191 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7192 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 7191 rx_fifo.rd_addr[4] +.sym 7192 rx_fifo.rd_addr[5] .sym 7193 rx_fifo.rd_addr[6] -.sym 7194 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7195 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 7194 rx_fifo.rd_addr[7] +.sym 7195 rx_fifo.rd_addr[8] .sym 7196 rx_fifo.rd_addr[9] -.sym 7197 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 7197 rx_fifo.rd_addr[1] .sym 7198 rx_fifo.rd_addr[0] .sym 7199 r_counter_$glb_clk -.sym 7200 w_rx_fifo_pull +.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 7201 $PACKER_VCC_NET -.sym 7205 w_rx_fifo_data[3] -.sym 7209 w_rx_fifo_data[1] -.sym 7211 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 7215 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7218 rx_fifo.wr_addr[9] -.sym 7219 w_rx_fifo_pull -.sym 7221 rx_fifo.rd_addr[3] -.sym 7223 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 7225 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7227 w_rx_24_fifo_data[30] -.sym 7228 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 7233 w_rx_fifo_pulled_data[17] -.sym 7236 w_rx_fifo_pulled_data[16] -.sym 7244 rx_fifo.wr_addr[4] -.sym 7245 rx_fifo.wr_addr[3] -.sym 7246 $PACKER_VCC_NET -.sym 7250 rx_fifo.wr_addr[5] -.sym 7251 rx_fifo.wr_addr[6] -.sym 7255 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 7256 rx_fifo.wr_addr[0] -.sym 7257 w_rx_fifo_data[18] -.sym 7258 rx_fifo.wr_addr[2] -.sym 7264 w_rx_fifo_data[16] -.sym 7265 rx_fifo.wr_addr[9] -.sym 7269 w_rx_fifo_push -.sym 7270 rx_fifo.wr_addr[7] -.sym 7271 rx_fifo.wr_addr[8] -.sym 7274 rx_fifo.rd_addr_gray[0] -.sym 7275 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 7276 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] -.sym 7277 rx_fifo.rd_addr[9] -.sym 7279 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 7280 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 7290 rx_fifo.wr_addr[2] +.sym 7205 rx_fifo.mem_q.0.2_WDATA +.sym 7209 rx_fifo.mem_q.0.2_WDATA_1 +.sym 7216 rx_fifo.rd_addr[8] +.sym 7224 rx_fifo.rd_addr[4] +.sym 7227 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7229 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 7233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7234 rx_fifo.wr_addr_gray_rd[5] +.sym 7236 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 7244 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 7248 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7249 rx_fifo.wr_addr[7] +.sym 7251 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7253 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 7255 $PACKER_VCC_NET +.sym 7258 rx_fifo.wr_addr[6] +.sym 7260 rx_fifo.wr_addr[4] +.sym 7261 rx_fifo.wr_addr[0] +.sym 7262 rx_fifo.wr_addr[1] +.sym 7263 rx_fifo.wr_addr[9] +.sym 7266 rx_fifo.wr_addr[5] +.sym 7268 rx_fifo.wr_addr[3] +.sym 7269 rx_fifo.wr_addr[8] +.sym 7274 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 7275 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 7276 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 7277 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 7278 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 7279 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 7280 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 7281 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 7290 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 7291 rx_fifo.wr_addr[3] .sym 7293 rx_fifo.wr_addr[4] .sym 7294 rx_fifo.wr_addr[5] @@ -6454,1213 +6403,1313 @@ .sym 7296 rx_fifo.wr_addr[7] .sym 7297 rx_fifo.wr_addr[8] .sym 7298 rx_fifo.wr_addr[9] -.sym 7299 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 7299 rx_fifo.wr_addr[1] .sym 7300 rx_fifo.wr_addr[0] .sym 7301 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7302 w_rx_fifo_push -.sym 7304 w_rx_fifo_data[16] -.sym 7308 w_rx_fifo_data[18] +.sym 7302 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 7304 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7308 rx_fifo.mem_q.0.0_WDATA_2 .sym 7311 $PACKER_VCC_NET -.sym 7315 o_led1$SB_IO_OUT -.sym 7317 $PACKER_VCC_NET -.sym 7318 $PACKER_VCC_NET -.sym 7322 $PACKER_VCC_NET -.sym 7325 rx_fifo.rd_addr[0] -.sym 7329 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 7336 rx_fifo.rd_addr[6] -.sym 7345 rx_fifo.rd_addr[0] -.sym 7346 w_rx_fifo_data[19] -.sym 7350 w_rx_fifo_data[17] -.sym 7353 rx_fifo.rd_addr[6] -.sym 7355 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 7357 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 7361 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7362 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7363 rx_fifo.rd_addr[9] -.sym 7364 $PACKER_VCC_NET -.sym 7365 rx_fifo.rd_addr[3] -.sym 7367 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 7369 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 7371 w_rx_fifo_pull -.sym 7376 rx_fifo.rd_addr_gray_wr[5] -.sym 7377 rx_fifo.rd_addr_gray_wr[1] -.sym 7378 rx_fifo.rd_addr_gray_wr[4] -.sym 7379 rx_fifo.rd_addr_gray_wr[3] -.sym 7380 rx_fifo.rd_addr_gray_wr[0] -.sym 7381 rx_fifo.rd_addr_gray_wr[6] -.sym 7382 rx_fifo.rd_addr_gray_wr[2] -.sym 7383 rx_fifo.rd_addr_gray_wr[9] -.sym 7392 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 7321 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 7322 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7323 $PACKER_VCC_NET +.sym 7325 rx_fifo.rd_addr_gray[8] +.sym 7329 rx_fifo.wr_addr[9] +.sym 7332 rx_fifo.rd_addr[9] +.sym 7333 rx_fifo.rd_addr_gray_wr_r[7] +.sym 7334 rx_fifo.rd_addr[8] +.sym 7335 rx_fifo.wr_addr[8] +.sym 7344 rx_fifo.rd_addr[1] +.sym 7345 rx_fifo.rd_addr[7] +.sym 7348 $PACKER_VCC_NET +.sym 7349 rx_fifo.rd_addr[0] +.sym 7350 rx_fifo.rd_addr[2] +.sym 7353 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7354 rx_fifo.rd_addr[3] +.sym 7355 rx_fifo.mem_q.0.0_WDATA +.sym 7356 rx_fifo.rd_addr[9] +.sym 7359 rx_fifo.rd_addr[8] +.sym 7360 rx_fifo.rd_addr[6] +.sym 7362 rx_fifo.rd_addr[4] +.sym 7371 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7374 rx_fifo.rd_addr[5] +.sym 7376 rx_fifo.wr_addr_gray_rd[7] +.sym 7377 rx_fifo.wr_addr_gray_rd[2] +.sym 7378 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 7379 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 7380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 7381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 7382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 7383 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 7392 rx_fifo.rd_addr[2] .sym 7393 rx_fifo.rd_addr[3] -.sym 7395 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 7396 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 7395 rx_fifo.rd_addr[4] +.sym 7396 rx_fifo.rd_addr[5] .sym 7397 rx_fifo.rd_addr[6] -.sym 7398 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7399 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 7398 rx_fifo.rd_addr[7] +.sym 7399 rx_fifo.rd_addr[8] .sym 7400 rx_fifo.rd_addr[9] -.sym 7401 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 7401 rx_fifo.rd_addr[1] .sym 7402 rx_fifo.rd_addr[0] .sym 7403 r_counter_$glb_clk -.sym 7404 w_rx_fifo_pull +.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 7405 $PACKER_VCC_NET -.sym 7409 w_rx_fifo_data[19] -.sym 7413 w_rx_fifo_data[17] -.sym 7421 rx_fifo.rd_addr[9] -.sym 7433 rx_fifo.rd_addr_gray_wr[6] -.sym 7434 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 7435 o_led1$SB_IO_OUT -.sym 7478 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 7480 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 7481 rx_fifo.rd_addr_gray_wr_r[0] -.sym 7482 rx_fifo.rd_addr_gray_wr_r[5] -.sym 7483 rx_fifo.rd_addr_gray_wr[7] -.sym 7484 rx_fifo.rd_addr_gray_wr_r[9] -.sym 7485 rx_fifo.rd_addr_gray_wr[8] -.sym 7529 rx_fifo.wr_addr_gray[5] -.sym 7534 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 7580 rx_fifo.wr_addr_gray_rd[6] -.sym 7583 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 7584 rx_fifo.wr_addr_gray_rd[3] -.sym 7585 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 7587 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 7625 rx_fifo.rd_addr_gray_wr_r[0] -.sym 7631 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 7635 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 7644 rx_fifo.rd_addr_gray_wr[8] -.sym 7683 rx_fifo.wr_addr_gray[2] -.sym 7684 rx_fifo.wr_addr_gray[0] -.sym 7685 rx_fifo.wr_addr_gray[3] -.sym 7686 rx_fifo.wr_addr_gray[6] -.sym 7687 rx_fifo.wr_addr_gray[1] -.sym 7724 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 7728 rx_fifo.wr_addr_gray_rd[5] -.sym 7730 $PACKER_VCC_NET -.sym 7732 i_rst_b$SB_IO_IN -.sym 7784 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 7788 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 7826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 7828 o_led1$SB_IO_OUT -.sym 7832 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 7834 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 7835 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 7836 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 7838 o_led1$SB_IO_OUT -.sym 7935 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 8028 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 8088 o_led1$SB_IO_OUT -.sym 8089 o_shdn_tx_lna$SB_IO_OUT +.sym 7409 rx_fifo.mem_q.0.0_WDATA +.sym 7413 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7418 $PACKER_VCC_NET +.sym 7420 o_led1$SB_IO_OUT +.sym 7424 $PACKER_VCC_NET +.sym 7425 i_rst_b$SB_IO_IN +.sym 7427 $PACKER_VCC_NET +.sym 7429 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 7433 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 7434 rx_fifo.wr_addr[9] +.sym 7435 i_rst_b$SB_IO_IN +.sym 7439 rx_fifo.wr_addr_gray_rd[4] +.sym 7440 rx_fifo.wr_addr[8] +.sym 7441 rx_fifo.wr_addr_gray_rd[6] +.sym 7478 rx_fifo.wr_addr[9] +.sym 7479 rx_fifo.wr_addr_gray[4] +.sym 7480 rx_fifo.wr_addr_gray[8] +.sym 7481 rx_fifo.wr_addr[8] +.sym 7482 rx_fifo.wr_addr_gray[3] +.sym 7483 rx_fifo.wr_addr_gray[7] +.sym 7484 rx_fifo.wr_addr_gray[6] +.sym 7485 rx_fifo.wr_addr_gray[2] +.sym 7516 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 7522 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7525 $PACKER_VCC_NET +.sym 7527 i_rst_b$SB_IO_IN +.sym 7531 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 7532 rx_fifo.wr_addr_gray_rd[3] +.sym 7534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 7536 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 7541 rx_fifo.wr_addr[9] +.sym 7581 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 7582 rx_fifo.wr_addr_gray_rd[8] +.sym 7584 rx_fifo.wr_addr_gray_rd[4] +.sym 7585 rx_fifo.wr_addr_gray_rd[6] +.sym 7586 rx_fifo.wr_addr_gray_rd[3] +.sym 7587 rx_fifo.wr_addr_gray_rd[5] +.sym 7622 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 7624 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 7625 rx_fifo.wr_addr[8] +.sym 7628 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 7629 rx_fifo.wr_addr[9] +.sym 7630 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7634 w_rx_fifo_full +.sym 7638 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 7641 rx_fifo.wr_addr_gray_rd[5] +.sym 7643 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 7683 rx_fifo.wr_addr_gray[1] +.sym 7686 rx_fifo.wr_addr_gray[5] +.sym 7741 rx_fifo.rd_addr_gray_wr_r[7] +.sym 7788 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 7789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 7826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 7830 spi_if_ins.r_tx_byte[2] +.sym 7838 i_rst_b$SB_IO_IN +.sym 7888 rx_fifo.rd_addr_gray_wr_r[7] .sym 8093 w_smi_data_output[6] .sym 8095 o_led0$SB_IO_OUT .sym 8099 $PACKER_VCC_NET -.sym 8102 w_smi_data_output[6] -.sym 8112 o_led0$SB_IO_OUT -.sym 8115 $PACKER_VCC_NET -.sym 8118 w_smi_data_output[6] -.sym 8119 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 8121 tx_fifo.rd_addr[6] -.sym 8125 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 8135 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 8136 rx_fifo.rd_addr[0] -.sym 8152 o_led0$SB_IO_OUT -.sym 8161 tx_fifo.wr_addr_gray[1] -.sym 8165 tx_fifo.wr_addr_gray[2] -.sym 8166 tx_fifo.wr_addr_gray[6] -.sym 8167 tx_fifo.wr_addr_gray[7] -.sym 8171 tx_fifo.wr_addr_gray[3] -.sym 8195 tx_fifo.wr_addr_gray[3] -.sym 8201 tx_fifo.wr_addr_gray[7] -.sym 8212 tx_fifo.wr_addr_gray[6] -.sym 8225 tx_fifo.wr_addr_gray[1] -.sym 8230 tx_fifo.wr_addr_gray[2] -.sym 8240 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8246 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 8247 tx_fifo.rd_addr[5] -.sym 8248 tx_fifo.rd_addr[7] -.sym 8249 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 8250 tx_fifo.rd_addr_gray[0] -.sym 8251 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 8252 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 8253 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 8262 smi_ctrl_ins.tx_reg_state[0] -.sym 8263 tx_fifo.wr_addr_gray_rd[4] -.sym 8266 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 8267 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 8269 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 8278 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8281 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 8295 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 8297 w_smi_data_output[1] -.sym 8301 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 8302 tx_fifo.rd_addr[6] -.sym 8303 tx_fifo.wr_addr_gray_rd[6] -.sym 8308 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 8312 tx_fifo.rd_addr[5] -.sym 8313 $PACKER_VCC_NET -.sym 8324 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 8332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 8333 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 8336 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8337 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 8338 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 8341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 8363 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 8364 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 8374 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 8386 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 8392 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 8399 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8402 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 8403 r_counter_$glb_clk -.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8405 tx_fifo.rd_addr_gray_wr[7] -.sym 8406 tx_fifo.rd_addr_gray_wr_r[6] -.sym 8407 tx_fifo.rd_addr_gray_wr[2] -.sym 8408 tx_fifo.rd_addr_gray_wr[4] -.sym 8409 tx_fifo.rd_addr_gray_wr[3] -.sym 8410 tx_fifo.rd_addr_gray_wr[6] -.sym 8411 tx_fifo.rd_addr_gray_wr[5] -.sym 8412 tx_fifo.rd_addr_gray_wr[0] -.sym 8420 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 8421 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 8422 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 8426 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 8428 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 8429 tx_fifo.rd_addr[7] -.sym 8431 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 8432 $PACKER_VCC_NET -.sym 8433 w_rx_fifo_push -.sym 8437 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 8438 tx_fifo.wr_addr_gray_rd[0] -.sym 8439 w_rx_24_fifo_data[24] -.sym 8440 w_rx_24_fifo_data[7] -.sym 8451 tx_fifo.wr_addr_gray_rd[5] -.sym 8454 tx_fifo.wr_addr_gray_rd[3] -.sym 8456 tx_fifo.rd_addr[7] -.sym 8463 tx_fifo.wr_addr_gray_rd[4] -.sym 8464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 8468 tx_fifo.rd_addr[6] -.sym 8469 tx_fifo.wr_addr_gray_rd[6] -.sym 8480 tx_fifo.wr_addr_gray_rd[5] -.sym 8494 tx_fifo.wr_addr_gray_rd[6] -.sym 8499 tx_fifo.wr_addr_gray_rd[3] -.sym 8503 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 8504 tx_fifo.rd_addr[7] -.sym 8505 tx_fifo.rd_addr[6] -.sym 8518 tx_fifo.wr_addr_gray_rd[4] -.sym 8526 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8528 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8529 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] -.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 8532 i_rst_b_SB_LUT4_I3_O -.sym 8534 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -.sym 8535 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -.sym 8540 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 8547 tx_fifo.wr_addr_gray_rd[5] -.sym 8548 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 8549 tx_fifo.rd_addr_gray_wr_r[6] -.sym 8552 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 8553 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 8557 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -.sym 8561 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 8569 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8572 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 8573 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] -.sym 8575 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8582 o_led1$SB_IO_OUT -.sym 8583 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 8584 w_rx_24_fifo_data[5] -.sym 8587 w_rx_24_fifo_data[13] -.sym 8590 w_rx_09_fifo_data[24] -.sym 8591 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 8593 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 8599 w_rx_24_fifo_data[24] -.sym 8608 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 8609 w_rx_24_fifo_data[13] -.sym 8614 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8616 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8620 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 8623 w_rx_24_fifo_data[5] -.sym 8632 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 8633 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 8634 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 8635 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] -.sym 8639 w_rx_09_fifo_data[24] -.sym 8640 o_led1$SB_IO_OUT -.sym 8641 w_rx_24_fifo_data[24] -.sym 8648 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 8649 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8650 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 8654 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 8655 i_rst_b$SB_IO_IN -.sym 8656 lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E -.sym 8657 smi_ctrl_ins.int_cnt_rx[4] -.sym 8658 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 8663 rx_fifo.rd_addr[3] -.sym 8665 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8666 w_rx_fifo_pulled_data[5] -.sym 8669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 8670 w_rx_fifo_pulled_data[9] -.sym 8673 w_rx_fifo_pulled_data[1] -.sym 8675 w_smi_data_output[1] -.sym 8679 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 8684 w_rx_fifo_data[24] -.sym 8686 w_rx_fifo_data[30] -.sym 8703 o_led1$SB_IO_OUT -.sym 8704 w_rx_09_fifo_data[29] -.sym 8708 tx_fifo.wr_addr_gray_rd[0] -.sym 8723 w_rx_24_fifo_data[29] -.sym 8761 tx_fifo.wr_addr_gray_rd[0] -.sym 8767 w_rx_09_fifo_data[29] -.sym 8768 w_rx_24_fifo_data[29] -.sym 8770 o_led1$SB_IO_OUT -.sym 8772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8774 w_smi_data_output[3] -.sym 8775 w_smi_data_output[0] -.sym 8776 w_smi_data_output[2] -.sym 8777 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] -.sym 8778 w_smi_data_output[6] -.sym 8780 w_smi_data_output[1] -.sym 8787 smi_ctrl_ins.int_cnt_rx[4] -.sym 8789 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 8791 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 8792 w_rx_09_fifo_data[29] -.sym 8795 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 8800 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 8801 w_rx_fifo_pulled_data[3] -.sym 8802 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8804 smi_ctrl_ins.int_cnt_rx[3] -.sym 8806 smi_ctrl_ins.int_cnt_rx[4] -.sym 8807 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 8808 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 8809 w_rx_24_fifo_data[29] -.sym 8817 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 8818 w_rx_fifo_pulled_data[15] -.sym 8820 w_rx_24_fifo_data[30] -.sym 8821 w_rx_fifo_pulled_data[10] -.sym 8824 o_led1$SB_IO_OUT -.sym 8826 w_rx_fifo_pulled_data[13] -.sym 8830 w_rx_fifo_pulled_data[8] -.sym 8836 w_rx_fifo_pulled_data[6] -.sym 8837 w_rx_fifo_pulled_data[18] -.sym 8840 w_rx_fifo_pulled_data[4] -.sym 8841 w_rx_09_fifo_data[30] -.sym 8848 w_rx_fifo_pulled_data[18] -.sym 8856 w_rx_fifo_pulled_data[15] -.sym 8863 w_rx_fifo_pulled_data[6] -.sym 8866 w_rx_24_fifo_data[30] -.sym 8867 o_led1$SB_IO_OUT -.sym 8868 w_rx_09_fifo_data[30] -.sym 8874 w_rx_fifo_pulled_data[10] -.sym 8879 w_rx_fifo_pulled_data[4] -.sym 8884 w_rx_fifo_pulled_data[13] -.sym 8891 w_rx_fifo_pulled_data[8] -.sym 8894 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 8107 $PACKER_VCC_NET +.sym 8109 o_led0$SB_IO_OUT +.sym 8113 w_smi_data_output[6] +.sym 8119 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 8122 w_smi_data_output[4] +.sym 8124 w_smi_data_output[7] +.sym 8133 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 8137 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 8142 rx_fifo.wr_addr[9] +.sym 8151 $PACKER_VCC_NET +.sym 8152 w_smi_data_input[7] +.sym 8161 smi_ctrl_ins.int_cnt_rx[4] +.sym 8165 w_rx_fifo_pulled_data[14] +.sym 8169 w_rx_fifo_pulled_data[12] +.sym 8170 w_rx_fifo_pulled_data[7] +.sym 8172 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8176 smi_ctrl_ins.int_cnt_rx[3] +.sym 8177 w_rx_fifo_pulled_data[13] +.sym 8178 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 8181 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 8185 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8189 w_rx_fifo_pulled_data[15] +.sym 8194 w_rx_fifo_pulled_data[13] +.sym 8200 w_rx_fifo_pulled_data[12] +.sym 8206 w_rx_fifo_pulled_data[7] +.sym 8211 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 8212 smi_ctrl_ins.int_cnt_rx[3] +.sym 8213 smi_ctrl_ins.int_cnt_rx[4] +.sym 8214 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 8226 w_rx_fifo_pulled_data[15] +.sym 8229 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8230 smi_ctrl_ins.int_cnt_rx[4] +.sym 8231 smi_ctrl_ins.int_cnt_rx[3] +.sym 8232 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8235 w_rx_fifo_pulled_data[14] +.sym 8239 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 8240 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8241 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8246 rx_fifo.mem_i.0.2_WDATA +.sym 8247 w_rx_09_fifo_data[29] +.sym 8249 w_rx_09_fifo_data[30] +.sym 8250 rx_fifo.mem_i.0.3_WDATA_1 +.sym 8251 rx_fifo.mem_i.0.3_WDATA +.sym 8252 lvds_rx_09_inst.o_fifo_data[31] +.sym 8253 w_rx_09_fifo_data[27] +.sym 8264 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8265 $PACKER_VCC_NET +.sym 8267 i_rst_b$SB_IO_IN +.sym 8274 o_led1$SB_IO_OUT +.sym 8278 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 8287 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 8292 w_rx_09_fifo_data[25] +.sym 8294 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 8299 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8303 rx_fifo.mem_i.0.1_WDATA_1 +.sym 8308 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 8309 w_smi_data_output[1] +.sym 8315 w_smi_data_output[2] +.sym 8323 w_rx_24_fifo_data[23] +.sym 8332 o_led1$SB_IO_OUT +.sym 8337 w_rx_24_fifo_data[29] +.sym 8339 w_rx_24_fifo_data[18] +.sym 8347 w_rx_09_fifo_data[25] +.sym 8349 w_rx_24_fifo_data[25] +.sym 8350 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8351 rx_fifo.wr_addr[9] +.sym 8352 w_rx_24_fifo_data[27] +.sym 8353 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8354 w_rx_24_fifo_data[21] +.sym 8356 w_rx_24_fifo_data[21] +.sym 8359 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8362 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8363 w_rx_24_fifo_data[18] +.sym 8370 w_rx_24_fifo_data[23] +.sym 8371 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8374 rx_fifo.wr_addr[9] +.sym 8381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8383 w_rx_24_fifo_data[29] +.sym 8386 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8388 w_rx_24_fifo_data[25] +.sym 8394 w_rx_24_fifo_data[27] +.sym 8395 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 8398 w_rx_09_fifo_data[25] +.sym 8399 o_led1$SB_IO_OUT +.sym 8400 w_rx_24_fifo_data[25] +.sym 8402 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8403 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 8404 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 8405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 8406 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 8408 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 8410 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 8412 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 8421 w_rx_fifo_pulled_data[7] +.sym 8429 w_rx_09_fifo_data[28] +.sym 8435 i_rst_b$SB_IO_IN +.sym 8438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 8439 w_smi_data_output[2] +.sym 8447 w_rx_fifo_pulled_data[16] +.sym 8448 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 8449 smi_ctrl_ins.int_cnt_rx[4] +.sym 8451 smi_ctrl_ins.int_cnt_rx[3] +.sym 8454 w_rx_24_fifo_data[23] +.sym 8455 w_rx_24_fifo_data[20] +.sym 8457 w_rx_24_fifo_data[21] +.sym 8459 w_rx_fifo_pulled_data[18] +.sym 8464 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 8467 w_rx_fifo_pulled_data[19] +.sym 8469 w_rx_09_fifo_data[20] +.sym 8471 w_rx_fifo_pulled_data[17] +.sym 8472 w_rx_09_fifo_data[23] +.sym 8474 w_rx_09_fifo_data[21] +.sym 8475 o_led1$SB_IO_OUT +.sym 8479 o_led1$SB_IO_OUT +.sym 8480 w_rx_09_fifo_data[20] +.sym 8481 w_rx_24_fifo_data[20] +.sym 8488 w_rx_fifo_pulled_data[18] +.sym 8492 w_rx_fifo_pulled_data[16] +.sym 8498 w_rx_fifo_pulled_data[17] +.sym 8503 o_led1$SB_IO_OUT +.sym 8504 w_rx_24_fifo_data[23] +.sym 8506 w_rx_09_fifo_data[23] +.sym 8509 smi_ctrl_ins.int_cnt_rx[4] +.sym 8510 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 8511 smi_ctrl_ins.int_cnt_rx[3] +.sym 8512 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 8518 w_rx_fifo_pulled_data[19] +.sym 8521 w_rx_09_fifo_data[21] +.sym 8522 o_led1$SB_IO_OUT +.sym 8524 w_rx_24_fifo_data[21] +.sym 8525 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 8526 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8529 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 8531 w_smi_data_output[2] +.sym 8532 smi_ctrl_ins.w_fifo_pull_trigger +.sym 8535 rx_fifo.mem_i.0.3_WDATA_2 +.sym 8537 rx_fifo.wr_addr[8] +.sym 8538 rx_fifo.wr_addr[8] +.sym 8540 rx_fifo.mem_i.0.1_WDATA_3 +.sym 8543 smi_ctrl_ins.int_cnt_rx[4] +.sym 8549 smi_ctrl_ins.int_cnt_rx[3] +.sym 8552 rx_fifo.rd_addr[0] +.sym 8554 rx_fifo.rd_addr[1] +.sym 8555 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 8559 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 8560 rx_fifo.rd_addr[7] +.sym 8561 o_led1$SB_IO_OUT +.sym 8562 rx_fifo.rd_addr[2] +.sym 8569 smi_ctrl_ins.int_cnt_rx[3] +.sym 8570 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 8571 i_rst_b$SB_IO_IN +.sym 8572 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 8573 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 8575 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 8577 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 8578 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 8580 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 8581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 8582 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 8583 smi_ctrl_ins.int_cnt_rx[3] +.sym 8585 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 8587 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 8590 smi_ctrl_ins.int_cnt_rx[4] +.sym 8592 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 8595 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 8597 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 8598 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 8600 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 8602 smi_ctrl_ins.int_cnt_rx[3] +.sym 8603 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 8604 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 8605 smi_ctrl_ins.int_cnt_rx[4] +.sym 8609 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 8610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 8614 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 8615 smi_ctrl_ins.int_cnt_rx[4] +.sym 8616 smi_ctrl_ins.int_cnt_rx[3] +.sym 8617 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 8622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 8623 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 8628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 8629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 8632 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 8633 smi_ctrl_ins.int_cnt_rx[3] +.sym 8634 smi_ctrl_ins.int_cnt_rx[4] +.sym 8635 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 8638 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 8639 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 8644 smi_ctrl_ins.int_cnt_rx[3] +.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 8646 smi_ctrl_ins.int_cnt_rx[4] +.sym 8647 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 8648 i_rst_b$SB_IO_IN +.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8651 rx_fifo.mem_i.0.3_WDATA_3 +.sym 8652 rx_fifo.rd_addr[3] +.sym 8653 rx_fifo.rd_addr[7] +.sym 8654 rx_fifo.rd_addr[2] +.sym 8655 rx_fifo.rd_addr[5] +.sym 8656 rx_fifo.rd_addr[6] +.sym 8657 rx_fifo.rd_addr[0] +.sym 8658 rx_fifo.rd_addr[1] +.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 8667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8671 tx_fifo.rd_addr_gray_wr[2] +.sym 8678 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 8680 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 8681 smi_ctrl_ins.int_cnt_rx[4] +.sym 8684 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 8685 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8686 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 8693 w_rx_fifo_pulled_data[24] +.sym 8697 w_rx_fifo_pulled_data[26] +.sym 8701 w_rx_fifo_pulled_data[4] +.sym 8702 w_rx_fifo_pulled_data[6] +.sym 8703 w_rx_fifo_pulled_data[5] +.sym 8713 w_rx_fifo_pulled_data[27] +.sym 8717 w_rx_fifo_pulled_data[25] +.sym 8726 w_rx_fifo_pulled_data[27] +.sym 8732 w_rx_fifo_pulled_data[25] +.sym 8739 w_rx_fifo_pulled_data[4] +.sym 8743 w_rx_fifo_pulled_data[26] +.sym 8750 w_rx_fifo_pulled_data[6] +.sym 8757 w_rx_fifo_pulled_data[24] +.sym 8770 w_rx_fifo_pulled_data[5] +.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8775 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 8776 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 8777 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8778 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 8779 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 8780 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 8781 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8787 w_rx_fifo_pulled_data[4] +.sym 8790 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8791 $PACKER_VCC_NET +.sym 8795 rx_fifo.rd_addr[3] +.sym 8797 rx_fifo.rd_addr[7] +.sym 8799 rx_fifo.rd_addr[4] +.sym 8800 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 8801 rx_fifo.rd_addr[8] +.sym 8804 rx_fifo.rd_addr[6] +.sym 8806 w_rx_fifo_pulled_data[21] +.sym 8836 w_rx_fifo_pulled_data[10] +.sym 8863 w_rx_fifo_pulled_data[10] +.sym 8894 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 8895 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8897 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] -.sym 8898 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 8899 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] -.sym 8900 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] -.sym 8901 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 8902 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 8903 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] -.sym 8904 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 8909 rx_fifo.rd_addr[0] -.sym 8910 rx_fifo.rd_addr[6] -.sym 8911 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 8912 rx_fifo.rd_addr[9] -.sym 8913 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 8915 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 8916 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 8919 smi_ctrl_ins.int_cnt_rx[3] -.sym 8921 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 8924 w_rx_fifo_push -.sym 8926 rx_fifo.rd_addr[3] -.sym 8929 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 8930 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 8949 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 8960 w_rx_fifo_pulled_data[19] -.sym 8995 w_rx_fifo_pulled_data[19] -.sym 9017 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 8897 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 8898 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 8899 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 8900 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 8901 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 8902 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 8903 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 8904 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 8917 w_rx_fifo_pulled_data[5] +.sym 8921 rx_fifo.wr_addr[8] +.sym 8923 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 8924 rx_fifo.rd_addr[5] +.sym 8925 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 8926 rx_fifo.rd_addr[6] +.sym 8927 i_rst_b$SB_IO_IN +.sym 8929 rx_fifo.rd_addr[9] +.sym 8930 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 8931 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8932 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 8939 w_rx_fifo_pulled_data[8] +.sym 8943 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 8945 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 8948 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 8949 smi_ctrl_ins.int_cnt_rx[3] +.sym 8952 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 8953 smi_ctrl_ins.int_cnt_rx[4] +.sym 8955 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 8959 w_rx_fifo_pulled_data[11] +.sym 8963 w_rx_fifo_pulled_data[9] +.sym 8966 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 8978 w_rx_fifo_pulled_data[9] +.sym 8984 w_rx_fifo_pulled_data[11] +.sym 8996 w_rx_fifo_pulled_data[8] +.sym 9001 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 9002 smi_ctrl_ins.int_cnt_rx[3] +.sym 9003 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 9004 smi_ctrl_ins.int_cnt_rx[4] +.sym 9007 smi_ctrl_ins.int_cnt_rx[4] +.sym 9008 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 9009 smi_ctrl_ins.int_cnt_rx[3] +.sym 9010 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 9013 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 9014 smi_ctrl_ins.int_cnt_rx[4] +.sym 9015 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 9016 smi_ctrl_ins.int_cnt_rx[3] +.sym 9017 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 9018 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9021 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 9022 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9023 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9024 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 9025 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 9026 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 9027 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 9038 w_rx_fifo_pulled_data[16] -.sym 9039 w_rx_fifo_pulled_data[26] -.sym 9040 w_rx_fifo_pulled_data[17] -.sym 9044 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 9046 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 9048 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 9051 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 9052 rx_fifo.rd_addr[3] -.sym 9053 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9054 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 9055 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 9063 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9081 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 9086 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 9087 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9088 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9090 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 9092 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 9096 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9103 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 9106 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 9121 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9125 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 9132 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 9140 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9141 r_counter_$glb_clk +.sym 9020 rx_fifo.rd_addr[4] +.sym 9021 rx_fifo.rd_addr[8] +.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 9023 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 9024 rx_fifo.rd_addr_gray[4] +.sym 9025 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 9026 rx_fifo.rd_addr_gray[5] +.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 9036 w_rx_fifo_pulled_data[30] +.sym 9037 smi_ctrl_ins.int_cnt_rx[3] +.sym 9039 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9040 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9041 smi_ctrl_ins.int_cnt_rx[4] +.sym 9044 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 9046 rx_fifo.rd_addr[1] +.sym 9048 rx_fifo.rd_addr[7] +.sym 9051 rx_fifo.rd_addr[1] +.sym 9052 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 9054 rx_fifo.rd_addr[2] +.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 9062 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 9078 w_rx_fifo_pulled_data[0] +.sym 9080 w_rx_fifo_pulled_data[1] +.sym 9082 w_rx_fifo_pulled_data[2] +.sym 9088 w_rx_fifo_pulled_data[3] +.sym 9095 w_rx_fifo_pulled_data[2] +.sym 9114 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 9125 w_rx_fifo_pulled_data[3] +.sym 9133 w_rx_fifo_pulled_data[1] +.sym 9138 w_rx_fifo_pulled_data[0] +.sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9143 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 9144 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 9146 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 9147 r_counter -.sym 9149 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 9150 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 9153 rx_fifo.rd_addr_gray_wr[1] -.sym 9155 rx_fifo.rd_addr[3] -.sym 9157 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9159 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 9160 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 9161 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 9163 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 9165 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 9166 rx_fifo.rd_addr[6] -.sym 9168 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 9169 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 9172 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 9176 w_rx_data[0] -.sym 9185 rx_fifo.rd_addr[0] -.sym 9189 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 9193 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 9194 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9195 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9196 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 9197 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 9198 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 9200 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 9211 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9217 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 9218 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9225 rx_fifo.rd_addr[0] -.sym 9230 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 9232 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 9236 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 9250 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 9256 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 9259 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 9260 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9263 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9143 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 9144 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] +.sym 9147 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 9150 w_rx_fifo_empty +.sym 9162 rx_fifo.rd_addr[4] +.sym 9164 rx_fifo.rd_addr[8] +.sym 9168 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9170 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 9171 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9172 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 9173 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9174 w_rx_fifo_empty +.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 9184 rx_fifo.rd_addr[4] +.sym 9185 rx_fifo.rd_addr[8] +.sym 9186 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 9187 rx_fifo.rd_addr[7] +.sym 9188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9194 rx_fifo.rd_addr[5] +.sym 9195 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 9196 rx_fifo.rd_addr[6] +.sym 9197 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 9200 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9202 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9203 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 9206 rx_fifo.rd_addr[1] +.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 9212 rx_fifo.rd_addr[9] +.sym 9219 rx_fifo.rd_addr[1] +.sym 9224 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9226 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9229 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 9230 rx_fifo.rd_addr[7] +.sym 9231 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 9232 rx_fifo.rd_addr[6] +.sym 9235 rx_fifo.rd_addr[8] +.sym 9236 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 9237 rx_fifo.rd_addr[9] +.sym 9238 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9249 rx_fifo.rd_addr[5] +.sym 9250 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 9259 rx_fifo.rd_addr[5] +.sym 9260 rx_fifo.rd_addr[4] +.sym 9261 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 9262 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 9264 r_counter_$glb_clk .sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9266 rx_fifo.empty_o_SB_LUT4_I3_I1[1] -.sym 9267 w_rx_fifo_empty -.sym 9269 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 9271 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 9273 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 9279 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 9281 smi_ctrl_ins.r_channel_SB_DFFER_Q_E -.sym 9287 $PACKER_VCC_NET -.sym 9288 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 9291 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9297 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 9298 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 9299 rx_fifo.rd_addr_gray_wr[4] -.sym 9300 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 9301 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 9308 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 9309 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9316 rx_fifo.rd_addr[0] -.sym 9318 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 9319 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 9324 rx_fifo.rd_addr[3] -.sym 9326 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 9330 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 9331 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 9332 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 9334 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9338 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 9340 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 9347 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9348 rx_fifo.rd_addr[3] -.sym 9353 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 9354 rx_fifo.rd_addr[0] -.sym 9360 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 9370 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 9371 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 9372 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 9373 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 9376 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 9377 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 9378 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 9379 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 9386 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9266 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 9268 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 9269 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 9271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 9272 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9273 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 9280 rx_fifo.wr_addr[9] +.sym 9283 w_rx_fifo_empty +.sym 9288 $PACKER_VCC_NET +.sym 9290 rx_fifo.wr_addr[9] +.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 9294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 9295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 9298 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9301 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9307 i_rst_b$SB_IO_IN +.sym 9308 rx_fifo.wr_addr_gray_rd[2] +.sym 9311 rx_fifo.wr_addr_gray_rd[5] +.sym 9313 rx_fifo.wr_addr_gray_rd[3] +.sym 9315 rx_fifo.wr_addr_gray_rd[7] +.sym 9320 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9321 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9330 rx_fifo.wr_addr_gray_rd[6] +.sym 9331 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9334 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.sym 9336 rx_fifo.wr_addr_gray_rd[4] +.sym 9338 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9342 i_rst_b$SB_IO_IN +.sym 9346 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 9347 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 9348 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9349 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.sym 9353 rx_fifo.wr_addr_gray_rd[6] +.sym 9358 rx_fifo.wr_addr_gray_rd[7] +.sym 9364 rx_fifo.wr_addr_gray_rd[5] +.sym 9373 rx_fifo.wr_addr_gray_rd[3] +.sym 9377 rx_fifo.wr_addr_gray_rd[2] +.sym 9383 rx_fifo.wr_addr_gray_rd[4] .sym 9387 r_counter_$glb_clk -.sym 9388 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9389 sys_ctrl_ins.tx_sample_gap[1] -.sym 9390 sys_ctrl_ins.tx_sample_gap[0] -.sym 9392 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 9393 sys_ctrl_ins.tx_sample_gap[3] -.sym 9394 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 9395 sys_ctrl_ins.tx_sample_gap[2] -.sym 9396 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 9405 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9406 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 9407 w_tx_data_sys[3] -.sym 9409 spi_if_ins.r_tx_byte[7] -.sym 9414 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 9416 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 9418 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 9419 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 9420 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9421 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 9422 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 9423 w_rx_fifo_push -.sym 9424 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 9438 rx_fifo.rd_addr_gray[0] -.sym 9441 rx_fifo.rd_addr[9] -.sym 9447 rx_fifo.rd_addr_gray[2] -.sym 9451 rx_fifo.rd_addr_gray[4] -.sym 9452 rx_fifo.rd_addr_gray[5] -.sym 9456 rx_fifo.rd_addr_gray[3] -.sym 9458 rx_fifo.rd_addr_gray[6] -.sym 9461 rx_fifo.rd_addr_gray[1] -.sym 9465 rx_fifo.rd_addr_gray[5] -.sym 9472 rx_fifo.rd_addr_gray[1] -.sym 9478 rx_fifo.rd_addr_gray[4] -.sym 9483 rx_fifo.rd_addr_gray[3] -.sym 9488 rx_fifo.rd_addr_gray[0] -.sym 9495 rx_fifo.rd_addr_gray[6] -.sym 9500 rx_fifo.rd_addr_gray[2] -.sym 9506 rx_fifo.rd_addr[9] -.sym 9510 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9512 rx_fifo.rd_addr_gray[8] -.sym 9513 rx_fifo.rd_addr_gray[2] -.sym 9514 rx_fifo.rd_addr_gray[3] -.sym 9515 rx_fifo.rd_addr_gray[7] -.sym 9516 rx_fifo.rd_addr_gray[6] -.sym 9517 rx_fifo.rd_addr_gray[4] -.sym 9518 rx_fifo.rd_addr_gray[5] -.sym 9519 rx_fifo.rd_addr_gray[1] -.sym 9525 sys_ctrl_ins.tx_sample_gap[2] -.sym 9528 w_rx_data[3] -.sym 9529 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 9535 w_ioc[2] -.sym 9536 rx_fifo.rd_addr_gray_wr_r[5] -.sym 9538 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 9541 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 9544 rx_fifo.wr_addr_gray_rd_r[9] -.sym 9545 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 9546 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 9553 rx_fifo.rd_addr_gray_wr[5] -.sym 9554 rx_fifo.rd_addr[6] -.sym 9560 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 9561 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 9562 rx_fifo.rd_addr[6] -.sym 9565 rx_fifo.rd_addr_gray_wr[0] -.sym 9566 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 9568 rx_fifo.rd_addr_gray_wr[9] -.sym 9572 rx_fifo.rd_addr_gray[7] -.sym 9577 rx_fifo.rd_addr_gray[8] -.sym 9587 rx_fifo.rd_addr[6] -.sym 9588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 9598 rx_fifo.rd_addr[6] -.sym 9599 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 9601 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 9606 rx_fifo.rd_addr_gray_wr[0] -.sym 9610 rx_fifo.rd_addr_gray_wr[5] -.sym 9616 rx_fifo.rd_addr_gray[7] -.sym 9624 rx_fifo.rd_addr_gray_wr[9] -.sym 9630 rx_fifo.rd_addr_gray[8] +.sym 9389 rx_fifo.rd_addr_gray[6] +.sym 9390 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 9391 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9392 rx_fifo.rd_addr_gray[2] +.sym 9393 rx_fifo.rd_addr_gray[3] +.sym 9394 rx_fifo.rd_addr_gray[1] +.sym 9395 rx_fifo.rd_addr_gray[7] +.sym 9409 rx_fifo.wr_addr_gray_rd[3] +.sym 9413 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 9415 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 9418 i_rst_b$SB_IO_IN +.sym 9422 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 9423 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9424 rx_fifo.wr_addr[8] +.sym 9435 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 9437 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9438 i_rst_b$SB_IO_IN +.sym 9439 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9443 rx_fifo.wr_addr_gray[7] +.sym 9445 rx_fifo.wr_addr_gray[2] +.sym 9446 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 9450 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 9451 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.sym 9452 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 9454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9456 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9458 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9459 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 9460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9461 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 9465 rx_fifo.wr_addr_gray[7] +.sym 9472 rx_fifo.wr_addr_gray[2] +.sym 9475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9477 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9481 i_rst_b$SB_IO_IN +.sym 9483 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9487 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 9488 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.sym 9489 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 9490 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9495 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 9499 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9501 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 9502 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 9506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 9507 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9510 r_counter_$glb_clk +.sym 9513 rx_fifo.rd_addr_gray_wr[6] +.sym 9514 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 9515 rx_fifo.rd_addr_gray_wr[0] +.sym 9516 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 9517 rx_fifo.rd_addr_gray_wr[3] +.sym 9518 rx_fifo.rd_addr_gray_wr[5] +.sym 9525 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 9527 $PACKER_VCC_NET +.sym 9534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 9535 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 9536 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 9537 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 9538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 9539 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9542 rx_fifo.rd_addr_gray[1] +.sym 9543 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9545 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 9546 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9564 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9566 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9568 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9569 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9570 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9577 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9595 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9605 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9610 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 9616 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 9623 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9629 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9630 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O .sym 9633 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9635 rx_fifo.wr_addr_gray_rd[2] -.sym 9636 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 9637 rx_fifo.wr_addr_gray_rd_r[9] -.sym 9638 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9639 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 9640 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 9642 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 9669 w_rx_fifo_push -.sym 9679 rx_fifo.wr_addr_gray[3] -.sym 9684 rx_fifo.wr_addr_gray_rd[6] -.sym 9688 rx_fifo.wr_addr_gray[6] -.sym 9691 rx_fifo.wr_addr_gray_rd[5] -.sym 9697 rx_fifo.wr_addr_gray_rd[7] -.sym 9710 rx_fifo.wr_addr_gray[6] -.sym 9729 rx_fifo.wr_addr_gray_rd[7] -.sym 9734 rx_fifo.wr_addr_gray[3] -.sym 9742 rx_fifo.wr_addr_gray_rd[5] -.sym 9751 rx_fifo.wr_addr_gray_rd[6] +.sym 9634 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 9636 rx_fifo.rd_addr_gray_wr[4] +.sym 9637 rx_fifo.rd_addr_gray_wr[2] +.sym 9638 rx_fifo.rd_addr_gray_wr[1] +.sym 9639 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 9641 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 9642 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 9660 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 9664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9678 rx_fifo.wr_addr_gray[8] +.sym 9680 rx_fifo.wr_addr_gray[3] +.sym 9682 rx_fifo.wr_addr_gray[6] +.sym 9685 rx_fifo.wr_addr_gray[4] +.sym 9688 rx_fifo.wr_addr_gray[5] +.sym 9702 rx_fifo.wr_addr_gray_rd[8] +.sym 9717 rx_fifo.wr_addr_gray_rd[8] +.sym 9723 rx_fifo.wr_addr_gray[8] +.sym 9733 rx_fifo.wr_addr_gray[4] +.sym 9742 rx_fifo.wr_addr_gray[6] +.sym 9745 rx_fifo.wr_addr_gray[3] +.sym 9751 rx_fifo.wr_addr_gray[5] .sym 9756 r_counter_$glb_clk -.sym 9758 rx_fifo.wr_addr_gray_rd[1] -.sym 9761 w_rx_fifo_push -.sym 9764 rx_fifo.wr_addr_gray_rd[0] -.sym 9773 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 9778 rx_fifo.wr_addr_gray_rd[4] -.sym 9787 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 9801 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9804 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 9810 rx_fifo.wr_en_i_SB_LUT4_I2_O -.sym 9811 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 9812 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 9815 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 9818 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 9838 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 9840 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 9846 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 9852 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 9853 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 9857 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 9863 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9878 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 9763 spi_if_ins.r_tx_byte[2] +.sym 9782 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 9810 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 9812 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9824 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 9858 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9878 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O .sym 9879 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9882 w_rx_24_fifo_push -.sym 9884 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 9900 w_rx_09_fifo_push +.sym 9884 rx_fifo.wr_addr_gray_rd[1] +.sym 9887 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 9889 o_shdn_rx_lna$SB_IO_OUT +.sym 9892 o_shdn_rx_lna$SB_IO_OUT .sym 9905 i_rst_b$SB_IO_IN -.sym 9907 w_rx_fifo_push -.sym 9925 rx_fifo.rd_addr_gray_wr[8] -.sym 9940 rx_fifo.rd_addr_gray_wr[1] -.sym 9957 rx_fifo.rd_addr_gray_wr[1] -.sym 9982 rx_fifo.rd_addr_gray_wr[8] +.sym 9914 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9924 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 9931 w_rx_fifo_full +.sym 9941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 9942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 9945 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 9979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 9980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 9981 w_rx_fifo_full +.sym 9985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 9987 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 10001 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E .sym 10002 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10019 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 10027 w_ioc[2] -.sym 10038 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] +.sym 10003 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10004 rx_fifo.rd_addr_gray_wr[7] +.sym 10006 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10018 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 10069 rx_fifo.rd_addr_gray_wr[7] +.sym 10091 rx_fifo.rd_addr_gray_wr[7] +.sym 10125 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 10150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10181 o_shdn_rx_lna$SB_IO_OUT -.sym 10197 o_shdn_rx_lna$SB_IO_OUT -.sym 10199 o_led0$SB_IO_OUT +.sym 10192 o_shdn_rx_lna$SB_IO_OUT +.sym 10197 i_rst_b$SB_IO_IN .sym 10201 w_smi_data_output[2] .sym 10203 o_led0$SB_IO_OUT .sym 10204 w_smi_data_output[1] .sym 10206 o_led0$SB_IO_OUT .sym 10207 $PACKER_VCC_NET -.sym 10211 w_smi_data_output[1] -.sym 10215 $PACKER_VCC_NET -.sym 10216 o_led0$SB_IO_OUT -.sym 10224 o_led0$SB_IO_OUT +.sym 10213 o_led0$SB_IO_OUT +.sym 10221 o_led0$SB_IO_OUT +.sym 10222 w_smi_data_output[1] +.sym 10223 $PACKER_VCC_NET .sym 10225 w_smi_data_output[2] -.sym 10226 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 10227 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 10228 smi_ctrl_ins.tx_reg_state[3] -.sym 10229 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] -.sym 10231 smi_ctrl_ins.tx_reg_state[0] -.sym 10232 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 10233 smi_ctrl_ins.tx_reg_state[1] -.sym 10241 w_smi_data_output[2] -.sym 10245 w_smi_data_output[6] -.sym 10250 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10272 i_rst_b$SB_IO_IN -.sym 10279 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 10287 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10289 smi_ctrl_ins.tx_reg_state[0] -.sym 10290 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 10294 smi_ctrl_ins.tx_reg_state[3] -.sym 10295 w_smi_data_output[6] -.sym 10296 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10299 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 10301 w_smi_data_output[6] -.sym 10307 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10308 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 10309 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10322 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 10343 smi_ctrl_ins.tx_reg_state[3] -.sym 10344 i_rst_b$SB_IO_IN -.sym 10345 smi_ctrl_ins.tx_reg_state[0] -.sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 10348 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10228 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10231 w_smi_data_output[5] +.sym 10261 o_led0$SB_IO_OUT +.sym 10268 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 10270 i_rst_b$SB_IO_IN +.sym 10271 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 10274 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 10276 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 10283 smi_ctrl_ins.int_cnt_rx[3] +.sym 10284 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 10290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10296 smi_ctrl_ins.int_cnt_rx[4] +.sym 10307 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 10308 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 10309 smi_ctrl_ins.int_cnt_rx[4] +.sym 10310 smi_ctrl_ins.int_cnt_rx[3] +.sym 10325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 10327 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 10337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10340 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 10347 i_rst_b$SB_IO_IN +.sym 10348 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 10352 w_smi_data_input[7] -.sym 10355 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10356 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10357 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10358 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10359 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 10360 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 10361 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 10364 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 10369 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 10370 tx_fifo.wr_addr_gray_rd[0] -.sym 10371 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 10373 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 10374 smi_ctrl_ins.swe_and_reset -.sym 10382 w_smi_data_input[7] -.sym 10384 w_smi_data_output[0] -.sym 10387 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 10389 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 10391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 10393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 10395 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 10398 tx_fifo.rd_addr_gray_wr_r[6] -.sym 10403 w_smi_data_output[3] +.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 10355 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 10356 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10358 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 10359 tx_fifo.rd_addr[0] +.sym 10360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 10361 tx_fifo.rd_addr[1] +.sym 10364 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10365 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 10376 w_smi_data_output[4] +.sym 10380 $PACKER_VCC_NET +.sym 10381 smi_ctrl_ins.soe_and_reset +.sym 10386 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10403 smi_ctrl_ins.int_cnt_rx[3] +.sym 10405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] .sym 10408 w_smi_data_input[7] -.sym 10411 tx_fifo.rd_addr_gray_wr[0] -.sym 10417 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 10419 smi_ctrl_ins.tx_reg_state[1] -.sym 10421 $PACKER_VCC_NET -.sym 10423 w_smi_data_output[7] -.sym 10424 smi_ctrl_ins.swe_and_reset -.sym 10436 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 10445 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 10449 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10450 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10451 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10454 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 10456 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10458 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 10460 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 10466 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10473 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 10479 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 10482 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10489 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 10496 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 10500 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10507 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10510 lvds_tx_inst.r_pulled_SB_LUT4_I2_O +.sym 10412 w_smi_data_input[7] +.sym 10414 w_smi_data_output[0] +.sym 10416 w_rx_fifo_pulled_data[23] +.sym 10431 w_rx_09_fifo_data[25] +.sym 10435 w_rx_24_fifo_data[31] +.sym 10437 w_rx_24_fifo_data[29] +.sym 10439 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10440 w_rx_09_fifo_data[29] +.sym 10443 o_led1$SB_IO_OUT +.sym 10444 w_rx_24_fifo_data[27] +.sym 10451 w_rx_09_fifo_data[28] +.sym 10453 lvds_rx_09_inst.o_fifo_data[31] +.sym 10454 w_rx_09_fifo_data[27] +.sym 10465 w_rx_09_fifo_data[27] +.sym 10466 w_rx_24_fifo_data[27] +.sym 10467 o_led1$SB_IO_OUT +.sym 10470 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10472 w_rx_09_fifo_data[27] +.sym 10482 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10483 w_rx_09_fifo_data[28] +.sym 10488 w_rx_24_fifo_data[29] +.sym 10489 o_led1$SB_IO_OUT +.sym 10490 w_rx_09_fifo_data[29] +.sym 10494 o_led1$SB_IO_OUT +.sym 10495 lvds_rx_09_inst.o_fifo_data[31] +.sym 10497 w_rx_24_fifo_data[31] +.sym 10502 w_rx_09_fifo_data[29] +.sym 10503 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10506 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 10507 w_rx_09_fifo_data[25] +.sym 10510 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce .sym 10511 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10513 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 10514 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 10515 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 10516 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 10517 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 10518 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 10519 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -.sym 10520 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] -.sym 10525 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 10526 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 10527 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 10529 tx_fifo.rd_addr[5] -.sym 10532 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 10534 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10537 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10540 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 10542 w_smi_data_output[7] -.sym 10544 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 10546 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 10547 lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E -.sym 10558 tx_fifo.rd_addr_gray[0] -.sym 10572 tx_fifo.rd_addr_gray[3] -.sym 10573 tx_fifo.rd_addr_gray[4] -.sym 10574 tx_fifo.rd_addr_gray[5] -.sym 10577 tx_fifo.rd_addr_gray[6] -.sym 10579 tx_fifo.rd_addr_gray[7] -.sym 10583 tx_fifo.rd_addr_gray_wr[6] -.sym 10584 tx_fifo.rd_addr_gray[2] -.sym 10587 tx_fifo.rd_addr_gray[7] -.sym 10594 tx_fifo.rd_addr_gray_wr[6] -.sym 10602 tx_fifo.rd_addr_gray[2] -.sym 10605 tx_fifo.rd_addr_gray[4] -.sym 10613 tx_fifo.rd_addr_gray[3] -.sym 10617 tx_fifo.rd_addr_gray[6] -.sym 10623 tx_fifo.rd_addr_gray[5] -.sym 10630 tx_fifo.rd_addr_gray[0] -.sym 10634 r_counter_$glb_clk -.sym 10636 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 10637 tx_fifo.rd_addr_gray[7] -.sym 10638 tx_fifo.rd_addr_gray[3] -.sym 10639 tx_fifo.rd_addr_gray[4] -.sym 10640 tx_fifo.rd_addr_gray[5] -.sym 10641 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 10642 tx_fifo.rd_addr_gray[2] -.sym 10643 tx_fifo.rd_addr_gray[6] -.sym 10648 tx_fifo.rd_addr_gray_wr[7] -.sym 10652 tx_fifo.rd_addr_gray_wr_r[6] -.sym 10653 w_rx_fifo_data[30] -.sym 10654 tx_fifo.rd_addr_gray_wr[2] -.sym 10655 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 10657 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 10658 tx_fifo.rd_addr_gray_wr[3] -.sym 10661 smi_ctrl_ins.int_cnt_rx[4] -.sym 10662 w_smi_data_output[0] -.sym 10665 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 10668 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -.sym 10670 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] -.sym 10678 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 10679 tx_fifo.rd_addr[5] -.sym 10680 tx_fifo.rd_addr[6] -.sym 10681 tx_fifo.rd_addr[7] -.sym 10685 w_rx_fifo_pulled_data[9] -.sym 10689 i_rst_b$SB_IO_IN -.sym 10690 w_rx_fifo_pulled_data[1] -.sym 10691 w_rx_fifo_pulled_data[5] -.sym 10693 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10695 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 10710 tx_fifo.rd_addr[7] -.sym 10711 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 10717 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10718 tx_fifo.rd_addr[6] -.sym 10719 tx_fifo.rd_addr[5] -.sym 10725 w_rx_fifo_pulled_data[5] -.sym 10735 i_rst_b$SB_IO_IN -.sym 10747 w_rx_fifo_pulled_data[9] -.sym 10755 w_rx_fifo_pulled_data[1] -.sym 10756 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10512 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 10513 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 10514 tx_fifo.rd_addr_gray[3] +.sym 10515 tx_fifo.rd_addr_gray[2] +.sym 10516 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 10518 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10519 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 10520 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 10524 rx_fifo.rd_addr_gray[5] +.sym 10529 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 10530 tx_fifo.rd_addr[1] +.sym 10531 o_led1$SB_IO_OUT +.sym 10535 o_led1$SB_IO_OUT +.sym 10539 rx_fifo.rd_addr[3] +.sym 10540 w_rx_09_fifo_data[30] +.sym 10542 rx_fifo.mem_i.0.3_WDATA_1 +.sym 10543 $PACKER_VCC_NET +.sym 10544 rx_fifo.mem_i.0.3_WDATA +.sym 10545 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 10548 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10555 w_rx_fifo_pulled_data[22] +.sym 10558 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 10560 smi_ctrl_ins.int_cnt_rx[4] +.sym 10561 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10563 w_rx_fifo_pulled_data[20] +.sym 10564 smi_ctrl_ins.int_cnt_rx[3] +.sym 10565 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10571 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 10581 w_rx_fifo_pulled_data[23] +.sym 10587 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10588 smi_ctrl_ins.int_cnt_rx[3] +.sym 10589 smi_ctrl_ins.int_cnt_rx[4] +.sym 10590 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10594 w_rx_fifo_pulled_data[23] +.sym 10605 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 10606 smi_ctrl_ins.int_cnt_rx[4] +.sym 10607 smi_ctrl_ins.int_cnt_rx[3] +.sym 10608 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 10617 w_rx_fifo_pulled_data[22] +.sym 10630 w_rx_fifo_pulled_data[20] +.sym 10633 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 10634 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10635 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10636 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 10637 tx_fifo.rd_addr_gray_wr[3] +.sym 10638 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 10639 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 10641 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10643 tx_fifo.rd_addr_gray_wr[2] +.sym 10645 w_rx_fifo_pulled_data[20] +.sym 10653 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 10654 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 10659 o_led1$SB_IO_OUT +.sym 10660 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 10661 rx_fifo.rd_addr[0] +.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 10663 rx_fifo.rd_addr[1] +.sym 10665 w_tx_fifo_pull +.sym 10666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10667 rx_fifo.rd_addr[3] +.sym 10669 rx_fifo.rd_addr[7] +.sym 10670 rx_fifo.rd_addr[8] +.sym 10671 rx_fifo.rd_addr[2] +.sym 10677 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 10679 i_rst_b$SB_IO_IN +.sym 10689 w_rx_24_fifo_data[30] +.sym 10690 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 10693 o_led1$SB_IO_OUT +.sym 10694 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 10696 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10698 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 10700 w_rx_09_fifo_data[30] +.sym 10702 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10703 smi_ctrl_ins.int_cnt_rx[4] +.sym 10704 smi_ctrl_ins.int_cnt_rx[3] +.sym 10716 smi_ctrl_ins.int_cnt_rx[4] +.sym 10717 smi_ctrl_ins.int_cnt_rx[3] +.sym 10718 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10719 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10722 smi_ctrl_ins.int_cnt_rx[3] +.sym 10723 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 10725 smi_ctrl_ins.int_cnt_rx[4] +.sym 10729 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 10735 smi_ctrl_ins.int_cnt_rx[4] +.sym 10736 smi_ctrl_ins.int_cnt_rx[3] +.sym 10752 w_rx_24_fifo_data[30] +.sym 10754 w_rx_09_fifo_data[30] +.sym 10755 o_led1$SB_IO_OUT +.sym 10756 i_rst_b$SB_IO_IN .sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 10758 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10759 w_tx_fifo_pull -.sym 10760 tx_fifo.empty_o_SB_LUT4_I3_O[3] -.sym 10761 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 10762 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 10764 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] -.sym 10766 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] -.sym 10772 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 10773 w_rx_fifo_data[31] -.sym 10776 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 10777 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 10778 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 10779 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 10781 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 10783 w_rx_fifo_push -.sym 10787 smi_ctrl_ins.int_cnt_rx[4] -.sym 10788 w_smi_data_output[3] -.sym 10790 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 10791 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 10794 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -.sym 10801 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 10804 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10809 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10812 i_rst_b$SB_IO_IN -.sym 10813 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 10824 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 10825 tx_fifo.empty_o_SB_LUT4_I3_O[3] -.sym 10826 smi_ctrl_ins.int_cnt_rx[3] -.sym 10830 smi_ctrl_ins.int_cnt_rx[4] -.sym 10851 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 10852 tx_fifo.empty_o_SB_LUT4_I3_O[3] -.sym 10853 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 10854 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 10858 i_rst_b$SB_IO_IN -.sym 10863 i_rst_b$SB_IO_IN -.sym 10870 smi_ctrl_ins.int_cnt_rx[3] -.sym 10872 smi_ctrl_ins.int_cnt_rx[4] -.sym 10876 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 10878 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 10880 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10760 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 10761 w_tx_fifo_empty +.sym 10762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 10763 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 10764 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10765 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 10766 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 10773 o_led1$SB_IO_OUT +.sym 10775 rx_fifo.mem_i.0.1_WDATA_1 +.sym 10776 w_rx_fifo_pulled_data[21] +.sym 10777 w_rx_24_fifo_data[30] +.sym 10778 rx_fifo.rd_addr[4] +.sym 10783 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 10788 smi_ctrl_ins.w_fifo_pull_trigger +.sym 10790 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 10791 rx_fifo.mem_i.0.3_WDATA_3 +.sym 10793 smi_ctrl_ins.int_cnt_rx[3] +.sym 10794 rx_fifo.mem_i.0.3_WDATA_2 +.sym 10801 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10802 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10803 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10805 o_led1$SB_IO_OUT +.sym 10811 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 10812 w_rx_09_fifo_data[28] +.sym 10813 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 10814 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10815 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10816 w_rx_24_fifo_data[28] +.sym 10830 rx_fifo.rd_addr[0] +.sym 10833 w_rx_24_fifo_data[28] +.sym 10834 o_led1$SB_IO_OUT +.sym 10836 w_rx_09_fifo_data[28] +.sym 10839 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10847 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10852 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 10857 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 10863 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 10870 rx_fifo.rd_addr[0] +.sym 10877 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10879 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 10880 r_counter_$glb_clk .sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10882 tx_fifo.wr_addr[9] -.sym 10885 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] -.sym 10886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] -.sym 10888 tx_fifo.wr_addr_gray[8] -.sym 10890 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10892 w_rx_fifo_push -.sym 10896 w_tx_fifo_empty -.sym 10898 $PACKER_VCC_NET -.sym 10899 w_rx_fifo_data[22] -.sym 10900 w_rx_fifo_data[20] -.sym 10902 o_led0$SB_IO_OUT -.sym 10904 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 10906 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 10908 w_rx_fifo_pulled_data[25] -.sym 10909 smi_ctrl_ins.int_cnt_rx[3] -.sym 10912 smi_ctrl_ins.int_cnt_rx[3] -.sym 10913 w_rx_fifo_pull -.sym 10916 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 10924 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 10925 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] -.sym 10926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] -.sym 10927 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] -.sym 10928 smi_ctrl_ins.int_cnt_rx[3] -.sym 10929 smi_ctrl_ins.int_cnt_rx[4] -.sym 10930 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] -.sym 10931 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] -.sym 10933 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] -.sym 10934 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] -.sym 10935 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -.sym 10937 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] -.sym 10938 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] -.sym 10940 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -.sym 10941 i_rst_b$SB_IO_IN -.sym 10942 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] -.sym 10943 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 10947 smi_ctrl_ins.int_cnt_rx[4] -.sym 10950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] -.sym 10951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] -.sym 10954 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -.sym 10956 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] -.sym 10957 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] -.sym 10958 smi_ctrl_ins.int_cnt_rx[4] -.sym 10959 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] -.sym 10962 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] -.sym 10963 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] -.sym 10964 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] -.sym 10965 smi_ctrl_ins.int_cnt_rx[4] -.sym 10968 smi_ctrl_ins.int_cnt_rx[4] -.sym 10969 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] -.sym 10970 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] -.sym 10971 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] -.sym 10974 smi_ctrl_ins.int_cnt_rx[3] -.sym 10975 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 10976 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 10977 smi_ctrl_ins.int_cnt_rx[4] -.sym 10980 smi_ctrl_ins.int_cnt_rx[4] -.sym 10981 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] -.sym 10982 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] -.sym 10983 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -.sym 10992 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] -.sym 10993 smi_ctrl_ins.int_cnt_rx[4] -.sym 10994 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -.sym 10995 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -.sym 11002 i_rst_b$SB_IO_IN -.sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 11007 tx_fifo.wr_addr_gray_rd[9] -.sym 11008 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 11011 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 11012 tx_fifo.wr_addr_gray_rd[8] -.sym 11017 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 11019 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 11020 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 11021 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 11025 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11027 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 11028 rx_fifo.rd_addr[3] -.sym 11049 w_rx_fifo_pulled_data[17] -.sym 11050 smi_ctrl_ins.int_cnt_rx[4] -.sym 11054 w_rx_fifo_pulled_data[26] -.sym 11055 w_rx_fifo_pulled_data[16] -.sym 11061 w_rx_fifo_pulled_data[3] -.sym 11064 w_rx_fifo_pulled_data[2] -.sym 11068 w_rx_fifo_pulled_data[25] -.sym 11069 smi_ctrl_ins.int_cnt_rx[3] -.sym 11070 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 11071 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 11072 w_rx_fifo_pulled_data[0] -.sym 11073 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 11079 w_rx_fifo_pulled_data[3] -.sym 11085 w_rx_fifo_pulled_data[26] -.sym 11094 w_rx_fifo_pulled_data[0] -.sym 11097 smi_ctrl_ins.int_cnt_rx[3] -.sym 11098 smi_ctrl_ins.int_cnt_rx[4] -.sym 11099 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 11100 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 11105 w_rx_fifo_pulled_data[25] -.sym 11109 w_rx_fifo_pulled_data[17] -.sym 11115 w_rx_fifo_pulled_data[2] -.sym 11122 w_rx_fifo_pulled_data[16] -.sym 11125 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10884 w_tx_fifo_pull +.sym 10885 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 10888 i_rst_b_SB_LUT4_I3_O +.sym 10893 rx_fifo.rd_addr_gray[7] +.sym 10895 rx_fifo.wr_addr[8] +.sym 10896 rx_fifo.rd_addr[6] +.sym 10900 w_rx_09_fifo_data[28] +.sym 10904 rx_fifo.rd_addr[5] +.sym 10906 w_rx_fifo_pulled_data[31] +.sym 10907 rx_fifo.rd_addr[7] +.sym 10908 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 10909 rx_fifo.rd_addr[2] +.sym 10910 w_rx_fifo_pulled_data[29] +.sym 10911 rx_fifo.rd_addr[5] +.sym 10913 rx_fifo.rd_addr[6] +.sym 10915 rx_fifo.rd_addr[0] +.sym 10916 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 10917 rx_fifo.rd_addr[1] +.sym 10924 rx_fifo.rd_addr[3] +.sym 10925 rx_fifo.rd_addr[7] +.sym 10929 rx_fifo.rd_addr[0] +.sym 10934 rx_fifo.rd_addr[2] +.sym 10935 rx_fifo.rd_addr[5] +.sym 10936 rx_fifo.rd_addr[6] +.sym 10938 rx_fifo.rd_addr[1] +.sym 10947 rx_fifo.rd_addr[4] +.sym 10955 $nextpnr_ICESTORM_LC_5$O +.sym 10958 rx_fifo.rd_addr[0] +.sym 10961 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 10963 rx_fifo.rd_addr[1] +.sym 10965 rx_fifo.rd_addr[0] +.sym 10967 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10970 rx_fifo.rd_addr[2] +.sym 10971 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 10973 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 10976 rx_fifo.rd_addr[3] +.sym 10977 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10979 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 10981 rx_fifo.rd_addr[4] +.sym 10983 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 10985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10988 rx_fifo.rd_addr[5] +.sym 10989 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 10991 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10994 rx_fifo.rd_addr[6] +.sym 10995 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 10999 rx_fifo.rd_addr[7] +.sym 11001 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11005 smi_ctrl_ins.r_fifo_pull +.sym 11006 smi_ctrl_ins.r_fifo_pull_1 +.sym 11007 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11008 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 11012 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11018 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11021 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 11022 rx_fifo.rd_addr[7] +.sym 11023 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 11026 rx_fifo.rd_addr[0] +.sym 11027 o_led1$SB_IO_OUT +.sym 11028 rx_fifo.rd_addr[1] +.sym 11030 $PACKER_VCC_NET +.sym 11032 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 11035 $PACKER_VCC_NET +.sym 11036 rx_fifo.rd_addr[3] +.sym 11038 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11039 w_tx_data_smi[2] +.sym 11041 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 11047 rx_fifo.rd_addr[8] +.sym 11050 w_rx_fifo_pulled_data[21] +.sym 11053 w_rx_fifo_pulled_data[30] +.sym 11055 w_rx_fifo_pulled_data[28] +.sym 11058 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11059 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 11063 rx_fifo.rd_addr[9] +.sym 11066 w_rx_fifo_pulled_data[31] +.sym 11070 w_rx_fifo_pulled_data[29] +.sym 11078 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 11080 rx_fifo.rd_addr[8] +.sym 11082 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 11085 rx_fifo.rd_addr[9] +.sym 11088 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 11093 w_rx_fifo_pulled_data[31] +.sym 11097 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11098 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 11106 w_rx_fifo_pulled_data[30] +.sym 11112 w_rx_fifo_pulled_data[21] +.sym 11116 w_rx_fifo_pulled_data[29] +.sym 11124 w_rx_fifo_pulled_data[28] +.sym 11125 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 11126 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 11127 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11128 w_tx_data_smi[1] -.sym 11131 w_rx_fifo_pull -.sym 11132 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 11134 w_tx_data_smi[2] -.sym 11135 w_tx_data_smi[0] -.sym 11150 w_rx_fifo_data[24] -.sym 11153 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11154 w_rx_fifo_empty -.sym 11156 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 11157 w_tx_data_smi[2] -.sym 11158 w_rx_fifo_push -.sym 11161 w_ioc[3] -.sym 11162 w_ioc[1] -.sym 11163 w_ioc[4] -.sym 11169 rx_fifo.rd_addr[3] -.sym 11171 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 11173 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11174 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 11175 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 11178 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 11186 rx_fifo.rd_addr[0] -.sym 11191 rx_fifo.rd_addr[6] -.sym 11194 rx_fifo.rd_addr[0] -.sym 11201 $nextpnr_ICESTORM_LC_1$O -.sym 11203 rx_fifo.rd_addr[0] -.sym 11207 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 11210 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 11211 rx_fifo.rd_addr[0] -.sym 11213 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 11216 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11217 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 11219 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 11221 rx_fifo.rd_addr[3] -.sym 11223 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 11225 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 11228 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 11229 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 11231 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 11233 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 11235 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 11237 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 11240 rx_fifo.rd_addr[6] -.sym 11241 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 11243 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 11245 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 11247 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 11251 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 11252 smi_ctrl_ins.o_channel -.sym 11256 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 11257 rx_fifo.empty_o_SB_LUT4_I3_I1[0] -.sym 11258 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 11266 w_rx_fifo_pull -.sym 11271 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 11272 smi_ctrl_ins.int_cnt_rx[3] -.sym 11273 w_rx_fifo_data[25] -.sym 11274 w_cs[0] -.sym 11275 w_rx_fifo_push -.sym 11276 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 11278 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 11279 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11282 w_rx_fifo_empty -.sym 11283 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11284 rx_fifo.wr_addr_gray_rd[8] -.sym 11286 sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E -.sym 11287 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 11292 i_glob_clock$SB_IO_IN -.sym 11293 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 11299 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 11301 rx_fifo.rd_addr[0] -.sym 11304 r_counter -.sym 11305 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 11307 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 11316 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 11319 rx_fifo.rd_addr[9] -.sym 11321 w_ioc[3] -.sym 11322 w_ioc[1] -.sym 11323 w_ioc[4] -.sym 11324 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 11327 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 11328 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 11332 rx_fifo.rd_addr[9] -.sym 11334 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 11344 rx_fifo.rd_addr[0] -.sym 11345 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 11350 r_counter -.sym 11361 w_ioc[4] -.sym 11362 w_ioc[1] -.sym 11363 w_ioc[3] -.sym 11364 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 11369 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 11370 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 11372 i_glob_clock$SB_IO_IN +.sym 11128 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.sym 11130 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.sym 11131 w_tx_data_smi[2] +.sym 11133 w_tx_data_smi[1] +.sym 11134 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] +.sym 11137 w_rx_fifo_pulled_data[28] +.sym 11140 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11144 smi_ctrl_ins.int_cnt_rx[4] +.sym 11145 rx_fifo.wr_addr[4] +.sym 11148 w_rx_fifo_empty +.sym 11149 o_led1$SB_IO_OUT +.sym 11152 rx_fifo.rd_addr_gray[4] +.sym 11155 rx_fifo.rd_addr[3] +.sym 11156 rx_fifo.rd_addr[1] +.sym 11157 rx_fifo.rd_addr[7] +.sym 11159 rx_fifo.rd_addr[2] +.sym 11160 rx_fifo.rd_addr[4] +.sym 11161 rx_fifo.rd_addr[0] +.sym 11162 rx_fifo.rd_addr[8] +.sym 11169 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11170 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 11171 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11172 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11179 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11182 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11187 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 11188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 11193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11194 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 11196 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11200 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11209 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11216 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 11217 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 11221 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11223 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 11229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 11232 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11240 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11244 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 11245 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 11246 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 11247 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11249 r_counter_$glb_clk +.sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 11251 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 11252 spi_if_ins.state_if[1] +.sym 11253 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 11254 spi_if_ins.state_if[0] +.sym 11255 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 11256 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 11258 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 11264 rx_fifo.rd_addr[6] +.sym 11265 o_led1$SB_IO_OUT +.sym 11267 rx_fifo.rd_addr[8] +.sym 11268 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 11274 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 11275 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 11276 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 11279 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 11281 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 11282 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 11283 w_rx_fifo_full +.sym 11285 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11286 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 11292 rx_fifo.rd_addr[7] +.sym 11293 rx_fifo.rd_addr[8] +.sym 11294 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 11295 rx_fifo.rd_addr[1] +.sym 11298 rx_fifo.rd_addr[2] +.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 11302 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 11303 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11304 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 11305 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11306 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 11307 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 11308 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11309 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11310 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11311 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] +.sym 11312 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11313 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 11315 rx_fifo.rd_addr[3] +.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 11319 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11321 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 11322 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 11325 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11326 rx_fifo.rd_addr[8] +.sym 11327 rx_fifo.rd_addr[7] +.sym 11333 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 11334 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11337 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 11339 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11340 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11343 rx_fifo.rd_addr[1] +.sym 11344 rx_fifo.rd_addr[2] +.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 11349 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11351 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11355 rx_fifo.rd_addr[3] +.sym 11356 rx_fifo.rd_addr[2] +.sym 11357 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] +.sym 11358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 11364 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 11369 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 11372 r_counter_$glb_clk .sym 11373 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11374 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 11376 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] -.sym 11377 spi_if_ins.r_tx_byte[6] -.sym 11378 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] -.sym 11380 spi_if_ins.r_tx_byte[1] -.sym 11381 spi_if_ins.r_tx_byte[7] -.sym 11386 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 11388 rx_fifo.rd_addr[3] -.sym 11390 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 11391 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 11395 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 11396 i_glob_clock$SB_IO_IN -.sym 11402 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11403 r_counter -.sym 11404 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 11407 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 11408 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 11415 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 11418 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 11420 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 11421 rx_fifo.empty_o_SB_LUT4_I3_I1[0] -.sym 11422 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11423 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 11424 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11425 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] -.sym 11426 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 11428 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 11430 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 11431 rx_fifo.empty_o_SB_LUT4_I3_I1[1] -.sym 11432 w_rx_fifo_empty -.sym 11433 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 11438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 11439 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 11441 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 11442 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11446 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 11448 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 11449 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 11450 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 11451 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] -.sym 11454 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 11455 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 11456 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 11457 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 11466 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 11467 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 11468 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 11469 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 11478 w_rx_fifo_empty -.sym 11479 rx_fifo.empty_o_SB_LUT4_I3_I1[1] -.sym 11481 rx_fifo.empty_o_SB_LUT4_I3_I1[0] -.sym 11490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11491 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 11492 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 11493 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11495 r_counter_$glb_clk +.sym 11374 spi_if_ins.r_tx_data_valid +.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 11379 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 11380 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 11385 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 11388 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 11398 i_glob_clock$SB_IO_IN +.sym 11406 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 11409 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 11416 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11419 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11420 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 11424 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 11426 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11428 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11429 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 11431 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 11435 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 11438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11441 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11442 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 11443 w_rx_fifo_full +.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11446 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 11450 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 11455 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 11456 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 11457 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 11460 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11461 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11462 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11463 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 11469 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 11473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11474 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11475 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11480 w_rx_fifo_full +.sym 11481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 11487 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 11494 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 11495 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11497 rx_fifo.wr_addr_gray_rd[5] -.sym 11499 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 11500 rx_fifo.wr_addr_gray_rd_r[8] -.sym 11502 sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E -.sym 11503 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] -.sym 11509 $PACKER_VCC_NET -.sym 11511 io_ctrl_ins.o_data_out[3] -.sym 11513 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11514 w_tx_data_sys[2] -.sym 11516 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 11519 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 11525 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11529 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 11530 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 11531 w_cs[1] -.sym 11538 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 11539 w_rx_data[1] -.sym 11541 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 11543 w_rx_data[2] -.sym 11545 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 11546 w_rx_data[0] -.sym 11549 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 11553 w_rx_data[3] -.sym 11556 sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E -.sym 11557 rx_fifo.wr_addr_gray_rd_r[8] -.sym 11560 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 11561 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 11564 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 11565 rx_fifo.rd_addr[9] -.sym 11566 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11567 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 11572 w_rx_data[1] -.sym 11579 w_rx_data[0] -.sym 11589 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 11590 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 11591 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 11592 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 11597 w_rx_data[3] -.sym 11601 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 11602 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 11603 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 11604 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 11610 w_rx_data[2] -.sym 11613 rx_fifo.wr_addr_gray_rd_r[8] -.sym 11614 rx_fifo.rd_addr[9] -.sym 11615 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11616 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 11617 sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E +.sym 11497 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 11499 w_cs[1] +.sym 11500 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 11501 w_cs[2] +.sym 11504 w_cs[3] +.sym 11521 rx_fifo.rd_addr_gray[0] +.sym 11524 w_tx_data_smi[2] +.sym 11525 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 11527 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 11530 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 11531 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 11540 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 11545 o_led1$SB_IO_OUT +.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 11553 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11555 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 11557 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11565 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11577 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 11578 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 11584 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 11585 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 11586 o_led1$SB_IO_OUT +.sym 11591 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 11598 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 11602 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 11609 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 11618 r_counter_$glb_clk .sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11622 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 11623 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 11624 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 11625 io_ctrl_ins.led1_state -.sym 11627 io_ctrl_ins.led0_state -.sym 11632 sys_ctrl_ins.tx_sample_gap[1] -.sym 11633 w_rx_data[1] -.sym 11634 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11636 sys_ctrl_ins.tx_sample_gap[0] -.sym 11637 w_rx_data[0] -.sym 11639 w_rx_data[2] -.sym 11641 w_ioc[1] -.sym 11642 sys_ctrl_ins.tx_sample_gap[3] -.sym 11646 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11650 w_rx_fifo_push -.sym 11651 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 11661 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11664 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11666 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 11667 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 11670 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 11671 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 11673 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 11674 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 11677 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 11679 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 11680 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 11687 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 11694 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 11697 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 11700 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 11703 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 11709 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 11712 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 11719 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 11726 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 11727 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 11730 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 11737 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 11740 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 11741 r_counter_$glb_clk -.sym 11742 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11744 io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] -.sym 11745 io_ctrl_ins.pmod_dir_state[0] -.sym 11749 io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] -.sym 11750 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11756 w_rx_data[1] -.sym 11757 w_rx_data[0] -.sym 11766 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11767 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 11771 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 11774 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11778 w_rx_fifo_push -.sym 11784 rx_fifo.wr_addr_gray_rd[2] -.sym 11787 rx_fifo.wr_addr_gray_rd[9] -.sym 11792 rx_fifo.wr_addr_gray_rd[1] -.sym 11795 rx_fifo.wr_addr_gray_rd[4] -.sym 11796 rx_fifo.wr_addr_gray_rd[3] -.sym 11798 rx_fifo.wr_addr_gray_rd[0] -.sym 11809 rx_fifo.wr_addr_gray[2] -.sym 11819 rx_fifo.wr_addr_gray[2] -.sym 11825 rx_fifo.wr_addr_gray_rd[0] -.sym 11830 rx_fifo.wr_addr_gray_rd[9] -.sym 11837 rx_fifo.wr_addr_gray_rd[3] -.sym 11841 rx_fifo.wr_addr_gray_rd[2] -.sym 11850 rx_fifo.wr_addr_gray_rd[4] -.sym 11859 rx_fifo.wr_addr_gray_rd[1] -.sym 11864 r_counter_$glb_clk -.sym 11866 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 11869 w_tx_data_io -.sym 11871 io_ctrl_ins.o_data_out[1] -.sym 11882 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 11883 rx_fifo.wr_addr_gray_rd[9] -.sym 11886 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 11888 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 11895 o_shdn_rx_lna$SB_IO_OUT -.sym 11901 w_rx_fifo_full -.sym 11907 w_rx_09_fifo_push -.sym 11916 w_rx_24_fifo_push -.sym 11917 rx_fifo.wr_addr_gray[0] -.sym 11920 rx_fifo.wr_addr_gray[1] -.sym 11933 o_led1$SB_IO_OUT -.sym 11942 rx_fifo.wr_addr_gray[1] -.sym 11958 o_led1$SB_IO_OUT -.sym 11959 w_rx_09_fifo_push -.sym 11961 w_rx_24_fifo_push -.sym 11977 rx_fifo.wr_addr_gray[0] +.sym 11620 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 11622 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11623 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11624 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 11626 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 11634 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 11637 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 11639 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 11641 o_led1$SB_IO_OUT +.sym 11642 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 11643 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 11645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 11647 rx_fifo.rd_addr_gray[2] +.sym 11652 rx_fifo.rd_addr_gray[4] +.sym 11661 rx_fifo.rd_addr_gray[6] +.sym 11665 rx_fifo.rd_addr_gray[3] +.sym 11670 rx_fifo.rd_addr_gray_wr[6] +.sym 11681 rx_fifo.rd_addr_gray[0] +.sym 11689 rx_fifo.rd_addr_gray[5] +.sym 11690 rx_fifo.rd_addr_gray_wr[3] +.sym 11701 rx_fifo.rd_addr_gray[6] +.sym 11708 rx_fifo.rd_addr_gray_wr[3] +.sym 11713 rx_fifo.rd_addr_gray[0] +.sym 11720 rx_fifo.rd_addr_gray_wr[6] +.sym 11727 rx_fifo.rd_addr_gray[3] +.sym 11731 rx_fifo.rd_addr_gray[5] +.sym 11741 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11743 r_tx_data[1] +.sym 11744 r_tx_data[4] +.sym 11745 r_tx_data[7] +.sym 11746 r_tx_data[6] +.sym 11747 r_tx_data[5] +.sym 11748 r_tx_data[2] +.sym 11749 r_tx_data[3] +.sym 11750 r_tx_data[0] +.sym 11776 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 11787 rx_fifo.rd_addr_gray_wr[1] +.sym 11794 rx_fifo.rd_addr_gray[1] +.sym 11807 rx_fifo.rd_addr_gray[2] +.sym 11809 rx_fifo.rd_addr_gray_wr[4] +.sym 11810 rx_fifo.rd_addr_gray_wr[2] +.sym 11812 rx_fifo.rd_addr_gray[4] +.sym 11823 rx_fifo.rd_addr_gray[4] +.sym 11832 rx_fifo.rd_addr_gray[2] +.sym 11837 rx_fifo.rd_addr_gray[1] +.sym 11844 rx_fifo.rd_addr_gray_wr[2] +.sym 11853 rx_fifo.rd_addr_gray_wr[4] +.sym 11859 rx_fifo.rd_addr_gray_wr[1] +.sym 11864 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11866 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 11867 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 11868 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 11869 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 11870 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 11871 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 11872 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 11873 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 11879 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 11881 o_shdn_tx_lna$SB_IO_OUT +.sym 11893 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11895 i_glob_clock$SB_IO_IN +.sym 11897 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 11909 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11912 r_tx_data[2] +.sym 11972 r_tx_data[2] +.sym 11986 spi_if_ins.r_tx_byte_SB_DFFE_Q_E .sym 11987 r_counter_$glb_clk -.sym 11992 io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] -.sym 11994 io_ctrl_ins.debug_mode[0] -.sym 12009 w_tx_data_io_SB_DFFESS_Q_E -.sym 12031 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 12036 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 12044 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 12057 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 12060 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 12061 w_rx_fifo_full -.sym 12069 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 12070 w_rx_fifo_full -.sym 12071 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 12072 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 12081 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 12083 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 12109 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 12110 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12111 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12114 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 12115 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 12124 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 12125 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 12132 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 11997 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 12014 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 12041 rx_fifo.wr_addr_gray_rd[1] +.sym 12055 rx_fifo.wr_addr_gray[1] +.sym 12084 rx_fifo.wr_addr_gray[1] +.sym 12101 rx_fifo.wr_addr_gray_rd[1] +.sym 12110 r_counter_$glb_clk +.sym 12128 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 12172 rx_fifo.rd_addr_gray[7] +.sym 12176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 12189 rx_fifo.rd_addr_gray[7] +.sym 12199 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 12233 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 12305 i_rst_b$SB_IO_IN .sym 12309 smi_ctrl_ins.soe_and_reset .sym 12310 w_smi_data_output[0] @@ -7668,2841 +7717,2386 @@ .sym 12313 w_smi_data_output[7] .sym 12315 o_led0$SB_IO_OUT .sym 12316 $PACKER_VCC_NET -.sym 12321 o_led0$SB_IO_OUT -.sym 12324 $PACKER_VCC_NET -.sym 12325 w_smi_data_output[0] -.sym 12326 w_smi_data_output[7] -.sym 12327 smi_ctrl_ins.soe_and_reset -.sym 12329 o_led0$SB_IO_OUT -.sym 12335 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 12336 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] -.sym 12337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] -.sym 12338 tx_fifo.wr_addr_gray_rd[4] -.sym 12340 tx_fifo.wr_addr_gray_rd[0] -.sym 12341 tx_fifo.wr_addr_gray_rd[5] -.sym 12342 smi_ctrl_ins.swe_and_reset -.sym 12367 smi_ctrl_ins.soe_and_reset -.sym 12368 w_smi_data_output[3] -.sym 12377 smi_ctrl_ins.swe_and_reset -.sym 12378 i_rst_b$SB_IO_IN -.sym 12379 w_smi_data_input[7] -.sym 12381 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 12383 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 12384 smi_ctrl_ins.tx_reg_state[1] -.sym 12385 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 12386 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 12387 w_smi_data_input[7] -.sym 12390 smi_ctrl_ins.tx_reg_state[2] -.sym 12391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 12394 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 12321 $PACKER_VCC_NET +.sym 12322 smi_ctrl_ins.soe_and_reset +.sym 12326 o_led0$SB_IO_OUT +.sym 12328 w_smi_data_output[0] +.sym 12333 w_smi_data_output[7] +.sym 12334 o_led0$SB_IO_OUT +.sym 12336 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 12337 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12338 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 12339 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 12340 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 12341 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 12342 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12377 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 12386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 12394 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] .sym 12395 i_rst_b$SB_IO_IN -.sym 12396 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] -.sym 12398 smi_ctrl_ins.tx_reg_state[0] -.sym 12399 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 12400 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 12401 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 12403 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 12404 tx_fifo.rd_addr_gray_wr_r[6] -.sym 12407 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 12410 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 12411 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 12416 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 12418 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 12423 w_smi_data_input[7] -.sym 12424 i_rst_b$SB_IO_IN -.sym 12425 smi_ctrl_ins.tx_reg_state[1] -.sym 12428 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 12429 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 12430 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 12431 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 12440 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] -.sym 12442 smi_ctrl_ins.tx_reg_state[0] -.sym 12443 w_smi_data_input[7] -.sym 12446 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 12447 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 12448 tx_fifo.rd_addr_gray_wr_r[6] -.sym 12449 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 12452 i_rst_b$SB_IO_IN -.sym 12453 smi_ctrl_ins.tx_reg_state[2] -.sym 12454 w_smi_data_input[7] -.sym 12457 smi_ctrl_ins.swe_and_reset -.sym 12463 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 12464 w_tx_fifo_full -.sym 12466 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] -.sym 12467 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 12468 smi_ctrl_ins.r_fifo_pull -.sym 12469 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 12470 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 12475 $PACKER_VCC_NET -.sym 12478 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 12480 smi_ctrl_ins.swe_and_reset -.sym 12496 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 12497 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 12499 $PACKER_VCC_NET -.sym 12505 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 12508 tx_fifo.rd_addr[8] -.sym 12509 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 12511 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 12512 w_tx_fifo_full -.sym 12514 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] +.sym 12424 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 12441 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 12442 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 12456 i_rst_b$SB_IO_IN +.sym 12457 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 12463 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 12465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12466 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 12468 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 12469 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 12470 tx_fifo.rd_addr[6] +.sym 12473 w_tx_data_smi[1] +.sym 12477 w_smi_data_output[5] +.sym 12481 w_smi_data_input[7] +.sym 12483 smi_ctrl_ins.soe_and_reset +.sym 12486 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12506 tx_fifo.rd_addr[1] +.sym 12509 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 12512 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] .sym 12515 i_rst_b$SB_IO_IN -.sym 12518 i_rst_b_SB_LUT4_I3_O -.sym 12519 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 12520 smi_ctrl_ins.r_fifo_pull -.sym 12522 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 12524 w_rx_fifo_pulled_data[7] -.sym 12525 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12528 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 12529 w_tx_fifo_full -.sym 12530 smi_ctrl_ins.tx_reg_state[2] -.sym 12532 $PACKER_VCC_NET -.sym 12543 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 12545 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 12547 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 12548 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 12549 tx_fifo.rd_addr[5] -.sym 12550 tx_fifo.rd_addr[7] -.sym 12553 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 12554 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 12567 tx_fifo.rd_addr[6] -.sym 12572 $nextpnr_ICESTORM_LC_4$O -.sym 12574 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 12578 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 12581 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 12582 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 12584 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 12586 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 12588 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 12590 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 12593 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 12594 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 12596 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 12598 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 12600 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 12602 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 12604 tx_fifo.rd_addr[5] -.sym 12606 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 12608 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 12611 tx_fifo.rd_addr[6] -.sym 12612 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 12614 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 12617 tx_fifo.rd_addr[7] -.sym 12618 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 12622 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12623 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 12624 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.sym 12625 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 12626 tx_fifo.rd_addr_gray_wr_r[4] -.sym 12627 tx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 12628 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.sym 12629 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] -.sym 12634 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 12635 w_smi_data_input[7] -.sym 12636 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 12637 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 12642 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 12645 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 12648 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 12649 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 12651 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 12652 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 12653 $PACKER_VCC_NET -.sym 12654 smi_ctrl_ins.tx_reg_state[2] -.sym 12656 $PACKER_VCC_NET -.sym 12657 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 12658 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 12669 smi_ctrl_ins.tx_reg_state[1] -.sym 12675 tx_fifo.rd_addr[8] -.sym 12677 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 12678 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 12681 smi_ctrl_ins.tx_reg_state[2] -.sym 12685 w_rx_fifo_pulled_data[11] -.sym 12686 w_rx_fifo_pulled_data[12] -.sym 12689 w_rx_fifo_pulled_data[7] -.sym 12690 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12693 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 12694 w_rx_fifo_pulled_data[14] -.sym 12695 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 12697 tx_fifo.rd_addr[8] -.sym 12699 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 12702 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 12705 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 12709 w_rx_fifo_pulled_data[12] -.sym 12716 w_rx_fifo_pulled_data[7] -.sym 12720 smi_ctrl_ins.tx_reg_state[2] -.sym 12722 smi_ctrl_ins.tx_reg_state[1] -.sym 12727 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 12728 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 12732 w_rx_fifo_pulled_data[14] -.sym 12741 w_rx_fifo_pulled_data[11] -.sym 12742 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12743 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 12516 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12517 w_smi_data_output[3] +.sym 12518 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12520 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12524 tx_fifo.rd_addr[1] +.sym 12528 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 12542 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12543 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 12545 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 12549 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12569 tx_fifo.rd_addr[0] +.sym 12574 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 12579 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 12585 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12591 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 12606 tx_fifo.rd_addr[0] +.sym 12610 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 12618 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 12619 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12620 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 12622 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 12623 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] +.sym 12624 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] +.sym 12625 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12627 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] +.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 12629 rx_fifo.wr_addr_gray[0] +.sym 12641 o_led1$SB_IO_OUT +.sym 12643 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 12647 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 12649 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 12650 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 12651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 12652 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 12653 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12656 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12657 smi_ctrl_ins.int_cnt_rx[4] +.sym 12663 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12665 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12669 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12670 tx_fifo.rd_addr[1] +.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12680 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12681 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12683 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12690 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12691 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12698 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12699 tx_fifo.rd_addr[1] +.sym 12703 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12710 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12714 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 12715 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12716 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12717 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12726 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12727 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12728 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12729 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12735 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 12738 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12739 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 12740 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12741 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 12742 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12743 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12745 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 12746 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 12747 smi_ctrl_ins.tx_reg_state[2] -.sym 12748 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 12749 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] -.sym 12750 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 12751 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 12752 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 12757 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 12758 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.sym 12762 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 12764 $PACKER_VCC_NET -.sym 12769 tx_fifo.wr_addr[9] -.sym 12770 w_rx_fifo_pulled_data[23] -.sym 12771 w_rx_fifo_pulled_data[11] -.sym 12774 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 12776 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 12777 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 12786 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12787 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] -.sym 12791 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 12794 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 12795 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 12796 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 12797 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12798 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 12801 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 12804 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 12806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 12809 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 12811 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 12817 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 12819 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12821 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12826 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 12827 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 12831 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 12834 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 12838 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12845 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 12849 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] -.sym 12850 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 12851 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 12852 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 12856 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 12858 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 12863 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 12865 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 12866 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12868 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 12869 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 12870 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 12871 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 12872 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] -.sym 12873 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 12874 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 12875 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 12881 w_smi_data_input[7] -.sym 12883 w_rx_fifo_pull -.sym 12884 tx_fifo.rd_addr_gray_wr[0] -.sym 12888 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 12889 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 12894 w_tx_fifo_full -.sym 12897 tx_fifo.wr_addr[9] -.sym 12898 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 12900 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 12901 tx_fifo.rd_addr[8] +.sym 12746 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 12747 smi_ctrl_ins.r_fifo_push +.sym 12748 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.sym 12750 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 12751 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 12752 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.sym 12757 rx_fifo.mem_i.0.1_WDATA +.sym 12761 rx_fifo.mem_i.0.1_WDATA_2 +.sym 12762 rx_fifo.wr_addr[3] +.sym 12764 rx_fifo.wr_addr[1] +.sym 12767 o_led1$SB_IO_OUT +.sym 12769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12770 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12771 i_rst_b_SB_LUT4_I3_O +.sym 12773 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 12777 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12787 tx_fifo.rd_addr_gray[3] +.sym 12788 tx_fifo.rd_addr_gray[2] +.sym 12792 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 12800 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12801 tx_fifo.rd_addr[1] +.sym 12803 tx_fifo.rd_addr_gray_wr[3] +.sym 12804 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12805 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 12811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 12812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12813 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12816 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 12821 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12822 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12825 tx_fifo.rd_addr_gray[3] +.sym 12832 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12833 tx_fifo.rd_addr[1] +.sym 12834 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 12838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 12839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 12851 tx_fifo.rd_addr_gray_wr[3] +.sym 12864 tx_fifo.rd_addr_gray[2] +.sym 12866 r_counter_$glb_clk +.sym 12868 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 12869 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 12870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 12871 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 12872 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 12873 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 12874 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 12875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12880 rx_fifo.rd_addr[7] +.sym 12881 rx_fifo.rd_addr[0] +.sym 12882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 12883 rx_fifo.rd_addr[6] +.sym 12884 rx_fifo.wr_addr[4] +.sym 12887 rx_fifo.wr_addr[6] +.sym 12888 w_rx_fifo_pulled_data[23] +.sym 12889 w_smi_data_input[7] +.sym 12894 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 12896 tx_fifo.rd_addr[1] +.sym 12899 smi_ctrl_ins.int_cnt_rx[3] +.sym 12901 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 12902 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] .sym 12903 i_rst_b$SB_IO_IN -.sym 12910 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 12912 tx_fifo.rd_addr[8] -.sym 12916 w_tx_fifo_empty -.sym 12920 lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E -.sym 12923 smi_ctrl_ins.int_cnt_rx[4] -.sym 12925 w_tx_fifo_pull -.sym 12927 smi_ctrl_ins.int_cnt_rx[3] -.sym 12928 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 12929 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 12931 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 12933 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 12937 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12938 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 12943 w_tx_fifo_empty -.sym 12948 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 12949 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 12950 w_tx_fifo_empty -.sym 12951 w_tx_fifo_pull -.sym 12955 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12960 tx_fifo.rd_addr[8] -.sym 12962 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 12972 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 12973 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 12974 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 12975 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 12984 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 12985 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 12986 smi_ctrl_ins.int_cnt_rx[4] -.sym 12987 smi_ctrl_ins.int_cnt_rx[3] -.sym 12988 lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E +.sym 12910 w_tx_fifo_pull +.sym 12911 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 12912 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 12913 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12914 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 12916 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12917 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 12919 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 12920 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.sym 12923 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12927 i_rst_b$SB_IO_IN +.sym 12928 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12929 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 12931 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 12932 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12934 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 12935 w_tx_fifo_empty +.sym 12936 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12940 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12948 w_tx_fifo_empty +.sym 12949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12950 w_tx_fifo_pull +.sym 12951 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12954 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12955 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12956 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12957 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 12961 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 12962 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 12963 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.sym 12966 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12967 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12968 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 12969 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 12974 w_tx_fifo_pull +.sym 12975 i_rst_b$SB_IO_IN +.sym 12978 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 12979 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12980 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 12981 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 12984 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 12985 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 12987 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] .sym 12989 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 12990 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 12995 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12998 smi_ctrl_ins.r_fifo_push_1 -.sym 13004 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 13005 rx_fifo.wr_addr[6] -.sym 13007 w_rx_fifo_pulled_data[30] -.sym 13008 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 13009 w_smi_data_output[7] -.sym 13012 w_rx_fifo_pulled_data[29] -.sym 13013 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 13014 $PACKER_VCC_NET -.sym 13015 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 13016 w_rx_fifo_pulled_data[27] -.sym 13018 smi_ctrl_ins.r_fifo_pull -.sym 13020 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 13021 w_rx_fifo_pulled_data[31] -.sym 13024 rx_fifo.wr_addr[9] -.sym 13026 w_tx_fifo_full -.sym 13035 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 13036 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 13043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 13044 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 13049 smi_ctrl_ins.int_cnt_rx[3] -.sym 13052 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 13053 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 13054 smi_ctrl_ins.int_cnt_rx[4] -.sym 13063 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 13065 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 13083 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 13084 smi_ctrl_ins.int_cnt_rx[4] -.sym 13085 smi_ctrl_ins.int_cnt_rx[3] -.sym 13086 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 13089 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 13090 smi_ctrl_ins.int_cnt_rx[3] -.sym 13091 smi_ctrl_ins.int_cnt_rx[4] -.sym 13092 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 13102 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 13111 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 13112 r_counter_$glb_clk +.sym 12991 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12992 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 12993 tx_fifo.rd_addr_gray[4] +.sym 12994 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 12995 tx_fifo.rd_addr_gray[7] +.sym 12996 tx_fifo.rd_addr_gray[6] +.sym 12997 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 13003 rx_fifo.mem_i.0.3_WDATA +.sym 13004 tx_fifo.wr_addr_gray_rd[2] +.sym 13005 rx_fifo.mem_i.0.3_WDATA_1 +.sym 13006 rx_fifo.mem_q.0.1_WDATA_3 +.sym 13007 rx_fifo.mem_q.0.1_WDATA +.sym 13008 tx_fifo.wr_addr_gray_rd[8] +.sym 13009 rx_fifo.mem_q.0.1_WDATA_1 +.sym 13011 rx_fifo.rd_addr[2] +.sym 13012 rx_fifo.rd_addr[6] +.sym 13014 rx_fifo.mem_q.0.1_WDATA_2 +.sym 13018 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 13019 rx_fifo.wr_addr[9] +.sym 13022 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 13025 smi_ctrl_ins.int_cnt_rx[3] +.sym 13033 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 13034 w_tx_fifo_pull +.sym 13042 w_tx_fifo_empty +.sym 13043 i_rst_b_SB_LUT4_I3_O +.sym 13045 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 13047 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 13051 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 13057 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 13063 i_rst_b$SB_IO_IN +.sym 13078 w_tx_fifo_empty +.sym 13083 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 13084 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 13086 w_tx_fifo_pull +.sym 13089 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 13091 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 13092 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 13103 i_rst_b$SB_IO_IN +.sym 13111 i_rst_b_SB_LUT4_I3_O +.sym 13112 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 13113 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13115 smi_ctrl_ins.int_cnt_rx[3] -.sym 13118 tx_fifo.rd_addr[8] -.sym 13126 smi_ctrl_ins.int_cnt_rx[4] -.sym 13128 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 13129 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 13130 smi_ctrl_ins.r_fifo_push -.sym 13131 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 13132 w_rx_fifo_data[28] -.sym 13134 $PACKER_VCC_NET -.sym 13135 w_rx_fifo_push -.sym 13136 w_rx_fifo_data[23] -.sym 13137 w_rx_fifo_data[26] -.sym 13140 $PACKER_VCC_NET -.sym 13144 rx_fifo.rd_addr[0] -.sym 13145 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 13149 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 13163 tx_fifo.wr_addr[9] -.sym 13165 tx_fifo.wr_addr_gray_rd[9] -.sym 13169 tx_fifo.wr_addr_gray[8] -.sym 13186 tx_fifo.wr_addr_gray_rd[8] -.sym 13203 tx_fifo.wr_addr[9] -.sym 13209 tx_fifo.wr_addr_gray_rd[8] -.sym 13227 tx_fifo.wr_addr_gray_rd[9] -.sym 13230 tx_fifo.wr_addr_gray[8] -.sym 13235 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 13238 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 13239 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 13240 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 13241 r_tx_data[6] -.sym 13242 r_tx_data[7] -.sym 13252 w_rx_fifo_empty -.sym 13253 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 13254 w_rx_fifo_data[21] -.sym 13256 $PACKER_VCC_NET -.sym 13262 r_tx_data[6] -.sym 13264 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 13266 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 13267 io_ctrl_ins.o_data_out[1] -.sym 13268 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 13270 i_rst_b$SB_IO_IN -.sym 13271 w_cs[1] -.sym 13272 w_tx_data_io -.sym 13278 smi_ctrl_ins.r_fifo_pull_1 -.sym 13287 smi_ctrl_ins.o_channel -.sym 13288 smi_ctrl_ins.r_fifo_pull -.sym 13289 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13290 w_cs[0] -.sym 13296 w_tx_fifo_full -.sym 13297 w_rx_fifo_empty -.sym 13298 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 13303 w_cs[2] -.sym 13305 w_cs[1] -.sym 13306 w_cs[3] -.sym 13311 w_tx_fifo_full -.sym 13329 smi_ctrl_ins.r_fifo_pull -.sym 13330 smi_ctrl_ins.r_fifo_pull_1 -.sym 13331 w_rx_fifo_empty -.sym 13335 w_cs[1] -.sym 13336 w_cs[0] -.sym 13337 w_cs[2] -.sym 13338 w_cs[3] -.sym 13347 smi_ctrl_ins.o_channel -.sym 13353 w_rx_fifo_empty +.sym 13116 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 13117 smi_ctrl_ins.int_cnt_rx[3] +.sym 13119 smi_ctrl_ins.int_cnt_rx[4] +.sym 13126 rx_fifo.rd_addr[3] +.sym 13128 rx_fifo.rd_addr[2] +.sym 13129 rx_fifo.rd_addr[8] +.sym 13130 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 13131 o_led1$SB_IO_OUT +.sym 13132 rx_fifo.wr_addr[7] +.sym 13134 rx_fifo.wr_addr[6] +.sym 13135 rx_fifo.wr_addr[5] +.sym 13136 rx_fifo.wr_addr[4] +.sym 13137 rx_fifo.rd_addr[4] +.sym 13141 smi_ctrl_ins.int_cnt_rx[4] +.sym 13144 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 13147 i_rst_b_SB_LUT4_I3_O +.sym 13148 w_tx_fifo_full +.sym 13158 w_rx_fifo_empty +.sym 13159 smi_ctrl_ins.w_fifo_pull_trigger +.sym 13160 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 13161 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 13164 smi_ctrl_ins.r_fifo_pull_1 +.sym 13171 smi_ctrl_ins.r_fifo_pull +.sym 13174 smi_ctrl_ins.int_cnt_rx[3] +.sym 13176 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 13184 smi_ctrl_ins.int_cnt_rx[4] +.sym 13185 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 13190 smi_ctrl_ins.w_fifo_pull_trigger +.sym 13197 smi_ctrl_ins.r_fifo_pull +.sym 13201 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 13203 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 13206 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 13207 smi_ctrl_ins.int_cnt_rx[4] +.sym 13208 smi_ctrl_ins.int_cnt_rx[3] +.sym 13209 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 13230 w_rx_fifo_empty +.sym 13231 smi_ctrl_ins.r_fifo_pull +.sym 13233 smi_ctrl_ins.r_fifo_pull_1 +.sym 13235 r_counter_$glb_clk +.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13241 w_tx_data_smi[0] +.sym 13245 io_pmod[6]$SB_IO_IN +.sym 13248 io_pmod[6]$SB_IO_IN +.sym 13251 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 13252 smi_ctrl_ins.int_cnt_rx[3] +.sym 13253 rx_fifo.wr_addr[1] +.sym 13255 rx_fifo.mem_i.0.3_WDATA_2 +.sym 13256 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 13257 rx_fifo.wr_addr[5] +.sym 13258 rx_fifo.wr_addr[1] +.sym 13259 rx_fifo.wr_addr[3] +.sym 13260 rx_fifo.mem_i.0.3_WDATA_3 +.sym 13263 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 13267 $PACKER_VCC_NET +.sym 13272 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 13278 rx_fifo.rd_addr[4] +.sym 13280 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 13281 rx_fifo.rd_addr[3] +.sym 13282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 13284 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 13285 o_led1$SB_IO_OUT +.sym 13286 rx_fifo.rd_addr[4] +.sym 13288 rx_fifo.rd_addr[1] +.sym 13289 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 13290 rx_fifo.rd_addr[5] +.sym 13292 rx_fifo.wr_addr_gray_rd_r[0] +.sym 13295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.sym 13296 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13301 w_rx_fifo_empty +.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.sym 13308 w_tx_fifo_full +.sym 13309 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] +.sym 13312 rx_fifo.wr_addr_gray_rd_r[0] +.sym 13314 rx_fifo.rd_addr[1] +.sym 13317 rx_fifo.rd_addr[4] +.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 13319 rx_fifo.rd_addr[5] +.sym 13324 rx_fifo.rd_addr[3] +.sym 13325 rx_fifo.rd_addr[4] +.sym 13331 o_led1$SB_IO_OUT +.sym 13341 w_tx_fifo_full +.sym 13347 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 13348 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.sym 13349 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] +.sym 13350 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.sym 13353 rx_fifo.wr_addr_gray_rd_r[0] +.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 13355 w_rx_fifo_empty .sym 13357 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E .sym 13358 r_counter_$glb_clk -.sym 13359 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 13360 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 13361 w_cs[2] -.sym 13362 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 13363 w_cs[1] -.sym 13364 w_cs[3] -.sym 13365 w_tx_data_io_SB_LUT4_I3_O[3] -.sym 13366 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 13367 smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] -.sym 13369 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 13372 smi_ctrl_ins.r_fifo_pull_1 -.sym 13373 rx_fifo.wr_addr[8] -.sym 13374 w_rx_fifo_pulled_data[25] -.sym 13375 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 13376 smi_ctrl_ins.int_cnt_rx[3] -.sym 13377 spi_if_ins.w_rx_data[6] -.sym 13378 rx_fifo.wr_addr[7] -.sym 13379 w_rx_fifo_data[27] -.sym 13380 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13381 spi_if_ins.w_rx_data[5] -.sym 13382 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 13383 r_counter -.sym 13384 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 13385 spi_if_ins.r_tx_byte[1] -.sym 13387 w_rx_fifo_pull -.sym 13390 r_tx_data[7] -.sym 13391 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 13392 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 13394 w_rx_data[0] -.sym 13395 w_tx_data_sys[1] -.sym 13401 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13403 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 13407 w_ioc[1] -.sym 13408 rx_fifo.rd_addr[3] -.sym 13412 w_rx_fifo_pull -.sym 13415 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 13417 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 13420 w_rx_data[0] -.sym 13421 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 13422 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 13423 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 13424 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 13428 smi_ctrl_ins.r_channel_SB_DFFER_Q_E -.sym 13432 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 13434 w_ioc[1] -.sym 13436 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13437 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 13440 w_rx_data[0] -.sym 13464 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 13465 w_rx_fifo_pull -.sym 13466 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 13467 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 13470 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 13471 rx_fifo.rd_addr[3] -.sym 13472 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 13477 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 13479 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 13480 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 13359 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 13361 $PACKER_VCC_NET +.sym 13362 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 13363 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 13364 spi_if_ins.spi.r_tx_bit_count[0] +.sym 13365 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 13366 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13367 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 13372 rx_fifo.rd_addr[7] +.sym 13373 w_rx_fifo_pulled_data[31] +.sym 13374 rx_fifo.rd_addr[1] +.sym 13377 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 13378 rx_fifo.rd_addr[5] +.sym 13379 w_rx_fifo_pulled_data[29] +.sym 13380 rx_fifo.wr_addr_gray_rd_r[0] +.sym 13381 i_glob_clock$SB_IO_IN +.sym 13382 rx_fifo.rd_addr[0] +.sym 13384 spi_if_ins.w_rx_data[5] +.sym 13385 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13393 spi_if_ins.w_rx_data[6] +.sym 13395 $PACKER_VCC_NET +.sym 13402 spi_if_ins.state_if[1] +.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 13406 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13408 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13416 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13417 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13419 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13420 spi_if_ins.state_if[0] +.sym 13423 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13425 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 13434 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13436 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13437 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13440 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13442 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 13443 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13446 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13454 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 13459 spi_if_ins.state_if[1] +.sym 13461 spi_if_ins.state_if[0] +.sym 13464 spi_if_ins.state_if[0] +.sym 13465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13466 spi_if_ins.state_if[1] +.sym 13471 spi_if_ins.state_if[1] +.sym 13472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13473 spi_if_ins.state_if[0] +.sym 13476 spi_if_ins.state_if[0] +.sym 13478 spi_if_ins.state_if[1] +.sym 13479 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E .sym 13481 r_counter_$glb_clk .sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13483 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 13484 r_tx_data[1] -.sym 13485 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13486 r_tx_data[3] -.sym 13487 r_tx_data[2] -.sym 13488 i_button_SB_LUT4_I1_I0[0] -.sym 13489 w_cs[0] -.sym 13490 r_tx_data[0] -.sym 13495 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 13496 spi_if_ins.spi.r_tx_bit_count[2] -.sym 13497 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 13498 w_cs[1] -.sym 13499 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 13501 rx_fifo.wr_addr[4] -.sym 13502 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 13503 rx_fifo.wr_addr[3] -.sym 13506 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 13507 i_glob_clock$SB_IO_IN +.sym 13483 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 13484 spi_if_ins.spi.r_tx_byte[4] +.sym 13485 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 13486 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 13487 spi_if_ins.spi.r_tx_byte[7] +.sym 13488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 13489 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 13490 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 13497 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13500 rx_fifo.rd_addr[9] +.sym 13502 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13504 $PACKER_VCC_NET +.sym 13507 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .sym 13508 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13509 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 13513 spi_if_ins.r_tx_byte[7] -.sym 13514 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13515 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 13516 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 13525 w_cs[2] -.sym 13526 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 13531 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13532 r_tx_data[6] -.sym 13535 rx_fifo.wr_addr_gray_rd_r[8] -.sym 13539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 13540 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 13541 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 13544 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 13545 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 13546 i_rst_b$SB_IO_IN -.sym 13548 rx_fifo.wr_addr_gray_rd_r[9] -.sym 13549 r_tx_data[1] -.sym 13550 r_tx_data[7] -.sym 13551 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 13552 w_fetch -.sym 13557 i_rst_b$SB_IO_IN -.sym 13558 w_cs[2] -.sym 13559 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 13560 w_fetch -.sym 13569 rx_fifo.wr_addr_gray_rd_r[8] -.sym 13570 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 13571 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 13572 rx_fifo.wr_addr_gray_rd_r[9] -.sym 13577 r_tx_data[6] -.sym 13581 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 13582 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 13583 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 13584 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13593 r_tx_data[1] -.sym 13601 r_tx_data[7] -.sym 13603 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O +.sym 13511 rx_fifo.wr_addr[9] +.sym 13512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13516 w_cs[1] +.sym 13517 rx_fifo.wr_addr[8] +.sym 13526 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13528 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13535 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 13536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13538 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13540 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13545 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13551 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 13554 i_rst_b$SB_IO_IN +.sym 13555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13563 i_rst_b$SB_IO_IN +.sym 13564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 13569 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13570 i_rst_b$SB_IO_IN +.sym 13571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13572 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13575 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 13576 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 13583 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13584 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13589 i_rst_b$SB_IO_IN +.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13594 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13596 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 13599 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13600 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13603 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .sym 13604 r_counter_$glb_clk -.sym 13606 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] -.sym 13608 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 13609 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 13610 w_fetch -.sym 13611 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 13612 smi_ctrl_ins.r_channel_SB_DFFER_Q_E -.sym 13613 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 13618 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13620 w_ioc[4] -.sym 13621 r_tx_data[3] -.sym 13622 w_rx_fifo_full -.sym 13623 r_tx_data[0] -.sym 13624 w_tx_data_smi[2] -.sym 13626 w_ioc[1] -.sym 13627 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 13628 w_ioc[3] -.sym 13631 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 13632 i_rst_b$SB_IO_IN -.sym 13633 spi_if_ins.r_tx_byte[6] -.sym 13635 $PACKER_VCC_NET -.sym 13636 i_button_SB_LUT4_I1_I0[0] -.sym 13638 rx_fifo.wr_addr_gray_rd[5] -.sym 13639 i_rst_b$SB_IO_IN -.sym 13649 w_ioc[1] -.sym 13651 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] -.sym 13653 w_cs[0] -.sym 13655 rx_fifo.wr_addr_gray_rd[8] -.sym 13657 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 13664 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 13666 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13667 w_fetch -.sym 13668 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 13671 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] -.sym 13672 w_ioc[2] -.sym 13673 rx_fifo.wr_addr_gray[5] -.sym 13674 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 13675 w_load -.sym 13683 rx_fifo.wr_addr_gray[5] -.sym 13692 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 13693 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] -.sym 13694 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] -.sym 13695 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 13700 rx_fifo.wr_addr_gray_rd[8] -.sym 13710 w_load -.sym 13711 w_fetch -.sym 13712 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 13713 w_cs[0] -.sym 13716 w_ioc[2] -.sym 13717 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 13718 w_ioc[1] -.sym 13719 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] +.sym 13605 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13606 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 13607 spi_if_ins.spi.r_tx_byte[0] +.sym 13608 spi_if_ins.spi.r_tx_byte[2] +.sym 13609 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 13610 spi_if_ins.spi.r_tx_byte[5] +.sym 13611 spi_if_ins.spi.r_tx_byte[6] +.sym 13612 spi_if_ins.spi.r_tx_byte[3] +.sym 13613 spi_if_ins.spi.r_tx_byte[1] +.sym 13618 spi_if_ins.r_tx_data_valid +.sym 13622 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 13627 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 13631 spi_if_ins.r_tx_byte[3] +.sym 13632 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13633 spi_if_ins.r_tx_byte[4] +.sym 13634 w_tx_data_io[0] +.sym 13635 spi_if_ins.r_tx_byte[7] +.sym 13637 spi_if_ins.r_tx_byte[1] +.sym 13639 w_tx_data_io[1] +.sym 13640 i_rst_b$SB_IO_IN +.sym 13641 spi_if_ins.r_tx_byte[0] +.sym 13648 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 13649 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 13651 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 13655 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13656 spi_if_ins.w_rx_data[5] +.sym 13661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13663 spi_if_ins.w_rx_data[6] +.sym 13681 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13683 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 13692 spi_if_ins.w_rx_data[5] +.sym 13694 spi_if_ins.w_rx_data[6] +.sym 13698 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 13704 spi_if_ins.w_rx_data[5] +.sym 13706 spi_if_ins.w_rx_data[6] +.sym 13723 spi_if_ins.w_rx_data[6] +.sym 13725 spi_if_ins.w_rx_data[5] +.sym 13726 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 13727 r_counter_$glb_clk -.sym 13732 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 13733 w_load -.sym 13734 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 13735 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 13736 w_rx_data[0] -.sym 13738 spi_if_ins.spi.r_tx_byte[6] -.sym 13741 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 13742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 13743 w_rx_fifo_push -.sym 13744 $PACKER_VCC_NET -.sym 13745 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 13746 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 13747 spi_if_ins.spi.r_tx_byte[2] -.sym 13748 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 13754 w_load -.sym 13756 w_cs[1] -.sym 13757 w_fetch -.sym 13759 w_tx_data_io -.sym 13761 w_ioc[2] -.sym 13762 i_rst_b$SB_IO_IN -.sym 13763 io_ctrl_ins.o_data_out[1] -.sym 13773 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 13774 w_fetch -.sym 13777 w_rx_data[0] -.sym 13781 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 13782 w_rx_data[1] -.sym 13784 w_cs[1] -.sym 13790 w_load -.sym 13796 i_button_SB_LUT4_I1_I0[0] -.sym 13798 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 13818 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 13821 w_cs[1] -.sym 13822 w_fetch -.sym 13823 i_button_SB_LUT4_I1_I0[0] -.sym 13824 w_load -.sym 13828 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 13833 w_rx_data[1] -.sym 13847 w_rx_data[0] -.sym 13849 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 13850 r_counter_$glb_clk +.sym 13728 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 13729 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 13730 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 13731 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13733 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 13735 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13742 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13743 rx_fifo.wr_addr[0] +.sym 13745 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13747 w_cs[1] +.sym 13748 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 13751 w_cs[2] +.sym 13753 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 13754 w_cs[1] +.sym 13755 spi_if_ins.r_tx_byte[5] +.sym 13756 spi_if_ins.r_tx_byte[2] +.sym 13757 i_rst_b$SB_IO_IN +.sym 13760 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13761 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 13770 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13771 w_tx_data_io[2] +.sym 13772 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13781 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 13784 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13785 w_tx_data_smi[2] +.sym 13787 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 13788 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13789 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13796 w_tx_data_smi[1] +.sym 13798 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 13799 w_tx_data_io[1] +.sym 13800 i_rst_b$SB_IO_IN +.sym 13801 io_pmod[6]$SB_IO_IN +.sym 13803 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 13804 w_tx_data_smi[1] +.sym 13805 w_tx_data_io[1] +.sym 13806 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13816 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 13821 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13822 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13824 io_pmod[6]$SB_IO_IN +.sym 13827 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 13828 i_rst_b$SB_IO_IN +.sym 13829 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 13833 i_rst_b$SB_IO_IN +.sym 13835 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 13839 w_tx_data_smi[2] +.sym 13840 w_tx_data_io[2] +.sym 13841 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 13842 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13849 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13850 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13852 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 13853 io_ctrl_ins.pmod_dir_state[1] -.sym 13854 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] -.sym 13855 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 13856 w_tx_data_io_SB_DFFESS_Q_S -.sym 13858 i_button_SB_LUT4_I1_I0[2] -.sym 13865 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 13868 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 13869 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 13875 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 13876 w_rx_data[3] -.sym 13881 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 13884 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 13886 w_rx_data[0] -.sym 13898 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 13899 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 13900 w_rx_data[0] -.sym 13904 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13906 io_ctrl_ins.led1_state -.sym 13908 io_ctrl_ins.led0_state -.sym 13910 io_ctrl_ins.pmod_dir_state[1] -.sym 13919 io_ctrl_ins.pmod_dir_state[0] -.sym 13920 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 13921 w_ioc[2] -.sym 13932 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 13933 io_ctrl_ins.led1_state -.sym 13934 io_ctrl_ins.pmod_dir_state[1] -.sym 13935 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13939 w_rx_data[0] -.sym 13962 io_ctrl_ins.led0_state -.sym 13963 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 13964 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 13965 io_ctrl_ins.pmod_dir_state[0] -.sym 13969 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 13970 w_ioc[2] -.sym 13972 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 13973 r_counter_$glb_clk -.sym 13975 io_ctrl_ins.led0_state_SB_LUT4_I0_O[0] -.sym 13976 io_ctrl_ins.led1_state_SB_LUT4_I0_O[0] -.sym 13977 io_ctrl_ins.o_pmod[2] -.sym 13978 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] -.sym 13979 io_ctrl_ins.o_pmod[4] -.sym 13980 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] -.sym 13995 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 14010 o_shdn_tx_lna$SB_IO_OUT -.sym 14017 io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] -.sym 14019 io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] -.sym 14020 w_tx_data_io_SB_DFFESS_Q_S -.sym 14022 i_button_SB_LUT4_I1_I0[2] -.sym 14024 w_load -.sym 14026 w_cs[1] -.sym 14027 w_tx_data_io_SB_DFFESS_Q_E -.sym 14029 w_fetch -.sym 14030 io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] -.sym 14031 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 14032 io_ctrl_ins.led0_state_SB_LUT4_I0_O[0] -.sym 14037 io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] -.sym 14041 io_ctrl_ins.led1_state_SB_LUT4_I0_O[0] -.sym 14049 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 14050 w_cs[1] -.sym 14051 w_fetch -.sym 14052 w_load -.sym 14067 io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] -.sym 14068 io_ctrl_ins.led0_state_SB_LUT4_I0_O[0] -.sym 14069 io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] -.sym 14070 i_button_SB_LUT4_I1_I0[2] -.sym 14079 io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] -.sym 14080 io_ctrl_ins.led1_state_SB_LUT4_I0_O[0] -.sym 14081 io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] -.sym 14082 i_button_SB_LUT4_I1_I0[2] -.sym 14095 w_tx_data_io_SB_DFFESS_Q_E +.sym 13852 spi_if_ins.r_tx_byte[3] +.sym 13853 spi_if_ins.r_tx_byte[4] +.sym 13854 spi_if_ins.r_tx_byte[7] +.sym 13855 spi_if_ins.r_tx_byte[1] +.sym 13856 spi_if_ins.r_tx_byte[6] +.sym 13857 spi_if_ins.r_tx_byte[0] +.sym 13858 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 13859 spi_if_ins.r_tx_byte[5] +.sym 13874 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 13875 w_tx_data_io[2] +.sym 13880 w_cs[0] +.sym 13881 w_rx_data[1] +.sym 13883 w_rx_data[2] +.sym 13886 i_rst_b$SB_IO_IN +.sym 13893 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 13894 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 13895 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 13896 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13897 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 13898 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 13899 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13900 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 13901 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 13904 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 13905 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 13906 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 13907 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 13908 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 13909 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 13913 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 13917 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 13918 i_glob_clock$SB_IO_IN +.sym 13920 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 13921 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 13923 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 13926 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 13927 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 13928 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13932 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 13933 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 13934 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13935 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13938 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 13939 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 13940 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13944 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13945 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13946 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 13947 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 13950 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13951 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 13952 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 13956 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 13957 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13958 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 13959 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 13962 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13963 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 13964 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 13965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13968 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 13969 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13970 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 13971 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 13972 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 13973 i_glob_clock$SB_IO_IN +.sym 13975 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13976 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] +.sym 13977 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] +.sym 13978 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13979 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13980 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] +.sym 13981 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13982 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13987 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 13996 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 14000 i_glob_clock$SB_IO_IN +.sym 14001 w_rx_data[0] +.sym 14003 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 14027 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14033 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] +.sym 14035 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 14036 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 14037 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] +.sym 14040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 14042 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] +.sym 14045 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14046 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] +.sym 14047 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 14049 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14052 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 14056 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 14058 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14063 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14064 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] +.sym 14068 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14070 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 14075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14076 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 14079 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] +.sym 14082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14088 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] +.sym 14093 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] +.sym 14094 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 14095 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 14096 r_counter_$glb_clk -.sym 14097 w_tx_data_io_SB_DFFESS_Q_S -.sym 14098 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 14099 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 14100 io_ctrl_ins.debug_mode[1] -.sym 14101 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 14102 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 14103 io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] -.sym 14105 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 14123 i_rst_b$SB_IO_IN -.sym 14129 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 14140 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 14148 o_shdn_rx_lna$SB_IO_OUT -.sym 14150 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 14156 w_ioc[2] -.sym 14157 io_ctrl_ins.debug_mode[1] -.sym 14158 w_rx_data[0] -.sym 14190 w_ioc[2] -.sym 14191 o_shdn_rx_lna$SB_IO_OUT -.sym 14192 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 14193 io_ctrl_ins.debug_mode[1] -.sym 14202 w_rx_data[0] -.sym 14218 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 14219 r_counter_$glb_clk -.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14222 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 14224 io_ctrl_ins.mixer_en_state -.sym 14226 o_shdn_tx_lna$SB_IO_OUT -.sym 14234 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 14236 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 14238 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14104 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] +.sym 14131 i_rst_b$SB_IO_IN +.sym 14226 r_counter +.sym 14243 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] .sym 14249 i_rst_b$SB_IO_IN -.sym 14277 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 14278 i_rst_b$SB_IO_IN -.sym 14285 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 14307 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 14309 i_rst_b$SB_IO_IN -.sym 14313 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] .sym 14344 i_rst_b$SB_IO_IN -.sym 14358 o_shdn_rx_lna$SB_IO_OUT -.sym 14361 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 14370 o_shdn_tx_lna$SB_IO_OUT -.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14401 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14418 i_rst_b_SB_LUT4_I3_O +.sym 14373 i_rst_b$SB_IO_IN +.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14408 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14418 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .sym 14419 w_smi_data_output[3] .sym 14421 o_led0$SB_IO_OUT .sym 14425 $PACKER_VCC_NET -.sym 14433 i_rst_b_SB_LUT4_I3_O -.sym 14438 $PACKER_VCC_NET -.sym 14441 w_smi_data_output[3] -.sym 14442 o_led0$SB_IO_OUT -.sym 14445 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14446 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 14447 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 14448 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 14449 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 14450 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 14451 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 14457 smi_ctrl_ins.r_fifo_pull -.sym 14458 smi_ctrl_ins.swe_and_reset -.sym 14463 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 14474 i_rst_b$SB_IO_IN -.sym 14478 w_smi_data_input[7] -.sym 14490 i_smi_swe_srw$SB_IO_IN -.sym 14492 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 14496 tx_fifo.wr_addr_gray[5] -.sym 14497 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] -.sym 14503 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14504 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 14505 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 14507 tx_fifo.wr_addr[0] -.sym 14510 i_rst_b$SB_IO_IN -.sym 14513 tx_fifo.wr_addr_gray[0] -.sym 14515 tx_fifo.rd_addr_gray_wr_r[2] -.sym 14516 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 14517 tx_fifo.wr_addr_gray[4] -.sym 14520 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14522 tx_fifo.wr_addr[0] -.sym 14526 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 14528 tx_fifo.rd_addr_gray_wr_r[2] -.sym 14531 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 14532 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 14533 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] -.sym 14534 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 14538 tx_fifo.wr_addr_gray[4] -.sym 14550 tx_fifo.wr_addr_gray[0] -.sym 14556 tx_fifo.wr_addr_gray[5] -.sym 14561 i_rst_b$SB_IO_IN -.sym 14564 i_smi_swe_srw$SB_IO_IN -.sym 14566 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14430 $PACKER_VCC_NET +.sym 14431 o_led0$SB_IO_OUT +.sym 14432 w_smi_data_output[3] +.sym 14438 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14445 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14447 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14448 smi_ctrl_ins.swe_and_reset +.sym 14449 tx_fifo.wr_addr_gray_rd[4] +.sym 14450 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14451 smi_ctrl_ins.soe_and_reset +.sym 14456 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14458 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 14462 $PACKER_VCC_NET +.sym 14468 w_tx_data_smi[0] +.sym 14501 tx_fifo.rd_addr[6] +.sym 14503 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14504 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14507 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 14508 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 14509 tx_fifo.rd_addr[1] +.sym 14514 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 14515 tx_fifo.rd_addr[0] +.sym 14518 $nextpnr_ICESTORM_LC_7$O +.sym 14521 tx_fifo.rd_addr[0] +.sym 14524 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 14527 tx_fifo.rd_addr[1] +.sym 14528 tx_fifo.rd_addr[0] +.sym 14530 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 14532 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 14534 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 14536 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 14539 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 14540 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 14542 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 14544 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14546 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 14548 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 14550 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 14552 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 14554 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 14557 tx_fifo.rd_addr[6] +.sym 14558 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 14560 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 14562 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14564 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO .sym 14568 i_smi_swe_srw$SB_IO_IN -.sym 14572 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 14573 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 14574 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 14575 tx_fifo.wr_addr_gray[0] -.sym 14576 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 14577 tx_fifo.wr_addr[0] -.sym 14578 tx_fifo.wr_addr[3] -.sym 14579 tx_fifo.wr_addr_gray[4] +.sym 14573 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 14574 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 14575 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14576 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 14577 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 14578 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14579 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 14580 i_rst_b$SB_IO_IN .sym 14583 i_rst_b$SB_IO_IN -.sym 14586 tx_fifo.wr_addr_gray[5] -.sym 14588 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 14593 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14595 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 14606 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14609 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 14610 tx_fifo.rd_addr_gray_wr_r[2] -.sym 14613 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 14615 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 14618 tx_fifo.wr_addr_gray_rd[5] -.sym 14620 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 14623 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 14624 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 14625 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] -.sym 14626 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 14628 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 14632 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 14633 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 14636 tx_fifo.rd_addr_gray_wr_r[0] -.sym 14637 w_tx_fifo_full -.sym 14638 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 14649 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 14651 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] -.sym 14653 w_smi_data_input[7] -.sym 14655 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 14656 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 14657 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 14659 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 14660 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 14661 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 14662 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 14664 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 14665 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 14666 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 14667 smi_ctrl_ins.tx_reg_state[3] -.sym 14670 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 14672 i_rst_b$SB_IO_IN -.sym 14673 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 14675 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 14677 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 14678 smi_ctrl_ins.w_fifo_pull_trigger -.sym 14680 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 14682 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 14683 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 14684 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 14688 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 14689 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] -.sym 14690 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 14691 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 14700 i_rst_b$SB_IO_IN -.sym 14701 smi_ctrl_ins.tx_reg_state[3] -.sym 14702 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 14703 w_smi_data_input[7] -.sym 14707 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 14708 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 14709 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 14713 smi_ctrl_ins.w_fifo_pull_trigger -.sym 14718 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 14719 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 14724 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 14725 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 14726 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 14727 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 14729 r_counter_$glb_clk +.sym 14588 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14597 i_smi_soe_se$SB_IO_IN +.sym 14609 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 14611 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14617 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14624 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14627 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14628 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14634 tx_fifo.rd_addr_gray_wr[6] +.sym 14637 rx_fifo.wr_addr_gray_rd[0] +.sym 14638 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 14641 $PACKER_VCC_NET +.sym 14644 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 14650 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14653 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14654 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14655 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14656 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14657 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14658 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14659 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 14663 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14667 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14673 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14681 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 14683 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14685 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 14690 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 14695 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14702 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 14703 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14707 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 14708 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14713 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14714 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14718 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 14725 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14729 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14731 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] -.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 14733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 14734 spi_if_ins.spi.r2_rx_done -.sym 14735 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] -.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 14737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] -.sym 14743 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 14744 tx_fifo.wr_addr[9] -.sym 14753 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 14757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 14758 smi_ctrl_ins.tx_reg_state[0] -.sym 14759 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 14761 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 14763 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 14764 smi_ctrl_ins.w_fifo_pull_trigger -.sym 14765 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 14766 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 14773 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 14774 tx_fifo.rd_addr_gray_wr[4] -.sym 14777 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 14780 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 14781 w_tx_fifo_full -.sym 14786 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 14788 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 14791 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 14792 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 14793 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 14794 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 14795 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 14796 tx_fifo.rd_addr_gray_wr[7] -.sym 14797 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 14799 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 14801 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 14802 tx_fifo.rd_addr_gray_wr_r[9] -.sym 14803 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 14806 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 14807 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 14811 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 14812 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 14813 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 14817 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 14819 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 14825 tx_fifo.rd_addr_gray_wr[7] -.sym 14831 tx_fifo.rd_addr_gray_wr[4] -.sym 14835 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 14837 tx_fifo.rd_addr_gray_wr_r[9] -.sym 14838 w_tx_fifo_full -.sym 14841 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 14842 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 14843 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 14844 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 14848 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 14849 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 14850 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 14852 r_counter_$glb_clk -.sym 14854 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 14855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 14856 tx_fifo.rd_addr_gray_wr[8] -.sym 14857 tx_fifo.rd_addr_gray_wr[9] -.sym 14858 tx_fifo.rd_addr_gray_wr_r[0] -.sym 14859 tx_fifo.rd_addr_gray_wr[1] -.sym 14860 tx_fifo.rd_addr_gray_wr_r[9] -.sym 14861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 14872 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.sym 14873 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 14874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 14875 tx_fifo.rd_addr_gray_wr[5] -.sym 14876 tx_fifo.rd_addr_gray_wr_r[4] -.sym 14877 tx_fifo.wr_addr[9] -.sym 14879 tx_fifo.rd_addr_gray_wr_r[2] -.sym 14880 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 14881 tx_fifo.rd_addr_gray_wr[1] -.sym 14883 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 14884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 14885 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.sym 14887 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 14888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 14889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 14898 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 14899 w_smi_data_input[7] -.sym 14901 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 14902 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] -.sym 14905 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14906 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 14907 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] -.sym 14908 tx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 14911 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 14912 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 14913 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 14914 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 14915 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] -.sym 14918 smi_ctrl_ins.tx_reg_state[0] -.sym 14919 w_tx_fifo_pull -.sym 14920 smi_ctrl_ins.swe_and_reset -.sym 14921 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 14922 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 14923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 14924 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] -.sym 14925 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 14926 i_rst_b$SB_IO_IN -.sym 14929 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 14934 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 14935 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] -.sym 14936 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] -.sym 14937 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 14940 w_smi_data_input[7] -.sym 14942 i_rst_b$SB_IO_IN -.sym 14943 smi_ctrl_ins.tx_reg_state[0] -.sym 14947 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 14948 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 14953 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 14954 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 14955 w_tx_fifo_pull -.sym 14958 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 14959 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 14960 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] -.sym 14961 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] -.sym 14965 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 14970 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 14971 tx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 14972 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 14973 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 14975 smi_ctrl_ins.swe_and_reset -.sym 14978 w_smi_data_output[5] -.sym 14979 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 14980 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 14981 smi_ctrl_ins.w_fifo_pull_trigger -.sym 14982 w_smi_data_output[4] -.sym 14983 w_smi_data_output[7] -.sym 14989 rx_fifo.wr_addr[7] -.sym 14990 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 14998 w_rx_fifo_pulled_data[31] -.sym 14999 rx_fifo.wr_addr[9] -.sym 15001 tx_fifo.rd_addr_gray_wr[8] -.sym 15007 spi_if_ins.w_rx_data[1] -.sym 15009 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 15018 i_rst_b$SB_IO_IN -.sym 15020 w_rx_fifo_pulled_data[29] -.sym 15023 w_rx_fifo_pulled_data[23] -.sym 15025 w_rx_fifo_pulled_data[30] -.sym 15026 w_tx_fifo_pull -.sym 15029 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 15033 w_rx_fifo_pulled_data[22] -.sym 15035 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 15036 w_rx_fifo_pulled_data[31] -.sym 15039 w_rx_fifo_pulled_data[27] -.sym 15045 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 15046 smi_ctrl_ins.int_cnt_rx[4] -.sym 15049 smi_ctrl_ins.int_cnt_rx[3] -.sym 15054 w_rx_fifo_pulled_data[27] -.sym 15058 w_rx_fifo_pulled_data[29] -.sym 15065 i_rst_b$SB_IO_IN -.sym 15066 w_tx_fifo_pull -.sym 15072 w_rx_fifo_pulled_data[22] -.sym 15075 smi_ctrl_ins.int_cnt_rx[3] -.sym 15076 smi_ctrl_ins.int_cnt_rx[4] -.sym 15077 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 15078 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 15083 w_rx_fifo_pulled_data[30] -.sym 15088 w_rx_fifo_pulled_data[23] -.sym 15094 w_rx_fifo_pulled_data[31] -.sym 15097 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 15098 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15100 tx_fifo.rd_addr_gray_wr_r[2] -.sym 15101 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 15102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 15103 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.sym 15104 tx_fifo.rd_addr_gray_wr_r[8] -.sym 15106 spi_if_ins.spi.r3_rx_done -.sym 15107 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] -.sym 15108 i_rst_b$SB_IO_IN +.sym 14731 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 14733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 14734 rx_fifo.wr_addr_gray_rd[0] +.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 14737 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 14738 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 14743 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14745 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 14758 tx_fifo.rd_addr_gray_wr[4] +.sym 14761 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 14762 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 14763 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 14765 $PACKER_VCC_NET +.sym 14766 tx_fifo.rd_addr[6] +.sym 14774 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 14776 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14778 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 14779 tx_fifo.rd_addr[6] +.sym 14780 rx_fifo.wr_addr[1] +.sym 14781 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 14783 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14784 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14788 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14789 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14790 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14794 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 14796 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 14798 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 14807 tx_fifo.wr_addr_gray_rd_r[6] +.sym 14808 tx_fifo.rd_addr[6] +.sym 14811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 14812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 14813 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14814 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14817 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 14818 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 14820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 14825 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14836 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 14837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 14838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14843 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 14847 rx_fifo.wr_addr[1] +.sym 14851 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O +.sym 14852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14854 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 14855 smi_ctrl_ins.w_fifo_push_trigger +.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14858 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 14859 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14861 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 14866 tx_fifo.wr_addr[8] +.sym 14868 rx_fifo.wr_addr[0] +.sym 14870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 14871 i_rst_b$SB_IO_IN +.sym 14872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 14876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14878 tx_fifo.wr_addr_gray_rd[9] +.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14881 w_rx_fifo_pulled_data[7] +.sym 14882 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 14884 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14895 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 14896 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] +.sym 14897 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] +.sym 14898 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14899 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 14900 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14902 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 14906 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14908 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] +.sym 14911 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 14912 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 14918 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.sym 14920 smi_ctrl_ins.w_fifo_push_trigger +.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 14925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 14926 tx_fifo.rd_addr[6] +.sym 14935 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 14937 tx_fifo.rd_addr[6] +.sym 14942 smi_ctrl_ins.w_fifo_push_trigger +.sym 14946 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] +.sym 14947 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] +.sym 14948 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.sym 14949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] +.sym 14958 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 14959 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 14960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 14964 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 14965 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 14967 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 14970 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 14971 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 14972 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 14973 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 14975 r_counter_$glb_clk +.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14977 tx_fifo.rd_addr_gray_wr_r[8] +.sym 14978 tx_fifo.rd_addr_gray_wr[4] +.sym 14979 tx_fifo.rd_addr_gray_wr[8] +.sym 14980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 14981 tx_fifo.rd_addr_gray_wr[7] +.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 14983 tx_fifo.rd_addr_gray_wr[1] +.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14995 smi_ctrl_ins.r_fifo_push +.sym 14996 rx_fifo.wr_addr[9] +.sym 14998 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 15007 smi_ctrl_ins.int_cnt_rx[3] +.sym 15011 smi_ctrl_ins.int_cnt_rx[4] +.sym 15018 tx_fifo.wr_addr_gray_rd[1] +.sym 15020 tx_fifo.wr_addr_gray_rd[3] +.sym 15022 tx_fifo.wr_addr_gray_rd[5] +.sym 15024 tx_fifo.wr_addr_gray_rd[8] +.sym 15025 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 15030 tx_fifo.wr_addr_gray_rd[2] +.sym 15031 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 15032 tx_fifo.wr_addr_gray_rd[7] +.sym 15038 tx_fifo.wr_addr_gray_rd[9] +.sym 15040 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 15046 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 15054 tx_fifo.wr_addr_gray_rd[7] +.sym 15060 tx_fifo.wr_addr_gray_rd[8] +.sym 15066 tx_fifo.wr_addr_gray_rd[2] +.sym 15072 tx_fifo.wr_addr_gray_rd[3] +.sym 15075 tx_fifo.wr_addr_gray_rd[5] +.sym 15081 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 15082 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 15083 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 15084 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 15089 tx_fifo.wr_addr_gray_rd[1] +.sym 15094 tx_fifo.wr_addr_gray_rd[9] +.sym 15098 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15101 tx_fifo.rd_addr_gray[1] +.sym 15104 tx_fifo.rd_addr_gray[8] +.sym 15105 tx_fifo.rd_addr_gray[5] +.sym 15107 tx_fifo.rd_addr_gray[0] .sym 15111 i_rst_b$SB_IO_IN -.sym 15112 rx_fifo.rd_addr[0] -.sym 15115 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 15117 w_rx_fifo_data[29] -.sym 15118 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 15121 w_rx_fifo_pulled_data[22] -.sym 15122 rx_fifo.wr_addr[4] -.sym 15124 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 15126 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15127 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 15128 spi_if_ins.w_rx_data[6] -.sym 15129 io_ctrl_ins.o_data_out[6] -.sym 15132 rx_fifo.rd_addr[6] -.sym 15135 smi_ctrl_ins.int_cnt_rx[3] -.sym 15142 smi_ctrl_ins.int_cnt_rx[3] -.sym 15146 smi_ctrl_ins.int_cnt_rx[4] -.sym 15155 w_tx_fifo_full -.sym 15156 smi_ctrl_ins.r_fifo_push -.sym 15164 smi_ctrl_ins.r_fifo_push_1 -.sym 15172 i_rst_b$SB_IO_IN -.sym 15186 smi_ctrl_ins.r_fifo_push -.sym 15187 smi_ctrl_ins.r_fifo_push_1 -.sym 15189 w_tx_fifo_full -.sym 15198 i_rst_b$SB_IO_IN -.sym 15199 smi_ctrl_ins.int_cnt_rx[3] -.sym 15201 smi_ctrl_ins.int_cnt_rx[4] -.sym 15217 smi_ctrl_ins.r_fifo_push -.sym 15221 r_counter_$glb_clk +.sym 15112 rx_fifo.rd_addr[5] +.sym 15113 rx_fifo.rd_addr[3] +.sym 15114 tx_fifo.wr_addr_gray_rd[3] +.sym 15115 w_tx_fifo_full +.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 15118 tx_fifo.wr_addr_gray_rd[5] +.sym 15120 tx_fifo.wr_addr_gray_rd[7] +.sym 15121 w_rx_fifo_pulled_data[6] +.sym 15122 tx_fifo.wr_addr_gray_rd[1] +.sym 15123 rx_fifo.rd_addr[1] +.sym 15126 tx_fifo.rd_addr_gray_wr[6] +.sym 15127 rx_fifo.wr_addr_gray_rd[0] +.sym 15128 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 15131 tx_fifo.rd_addr_gray_wr[2] +.sym 15133 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 15147 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 15148 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 15149 tx_fifo.rd_addr[1] +.sym 15154 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 15155 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 15156 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 15159 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 15160 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 15161 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 15162 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15177 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 15180 tx_fifo.rd_addr[1] +.sym 15181 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 15182 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 15183 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 15186 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 15195 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 15200 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 15201 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15204 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 15206 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15212 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 15213 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 15220 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 15221 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 15222 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15230 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15236 rx_fifo.wr_addr[0] -.sym 15243 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 15244 w_rx_fifo_pulled_data[23] -.sym 15248 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 15250 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 15254 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 15256 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15258 io_ctrl_ins.o_data_out[7] -.sym 15273 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 15282 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 15285 smi_ctrl_ins.int_cnt_rx[3] -.sym 15303 smi_ctrl_ins.int_cnt_rx[3] -.sym 15321 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 15343 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 15344 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15229 tx_fifo.rd_addr_gray_wr[9] +.sym 15230 tx_fifo.rd_addr_gray_wr[6] +.sym 15237 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 15238 rx_fifo.wr_addr[3] +.sym 15242 io_pmod[7]$SB_IO_IN +.sym 15244 $PACKER_VCC_NET +.sym 15249 $PACKER_VCC_NET +.sym 15252 rx_fifo.wr_addr[9] +.sym 15253 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 15255 w_rx_fifo_empty +.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15267 smi_ctrl_ins.int_cnt_rx[3] +.sym 15292 i_rst_b$SB_IO_IN +.sym 15293 smi_ctrl_ins.int_cnt_rx[4] +.sym 15309 smi_ctrl_ins.int_cnt_rx[4] +.sym 15310 smi_ctrl_ins.int_cnt_rx[3] +.sym 15312 i_rst_b$SB_IO_IN +.sym 15315 smi_ctrl_ins.int_cnt_rx[3] +.sym 15327 smi_ctrl_ins.int_cnt_rx[3] +.sym 15330 smi_ctrl_ins.int_cnt_rx[4] +.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15347 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 15348 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 15350 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 15351 smi_ctrl_ins.int_cnt_rx[3] -.sym 15352 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] -.sym 15353 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 15355 smi_ctrl_ins.r_fifo_pull -.sym 15358 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 15362 rx_fifo.wr_addr[6] -.sym 15368 rx_fifo.wr_addr[0] -.sym 15370 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15371 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 15373 smi_ctrl_ins.int_cnt_rx[3] -.sym 15376 spi_if_ins.w_rx_data[3] -.sym 15377 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15378 spi_if_ins.w_rx_data[6] -.sym 15380 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15381 w_cs[1] -.sym 15389 spi_if_ins.w_rx_data[5] -.sym 15391 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15393 spi_if_ins.w_rx_data[6] -.sym 15394 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15396 i_glob_clock$SB_IO_IN -.sym 15397 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15398 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 15399 io_ctrl_ins.o_data_out[6] -.sym 15401 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15408 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15418 io_ctrl_ins.o_data_out[7] -.sym 15426 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15432 spi_if_ins.w_rx_data[6] -.sym 15434 spi_if_ins.w_rx_data[5] -.sym 15438 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15445 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15447 io_ctrl_ins.o_data_out[6] -.sym 15450 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15451 io_ctrl_ins.o_data_out[7] -.sym 15452 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15466 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 15467 i_glob_clock$SB_IO_IN -.sym 15468 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15469 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15470 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 15472 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15473 spi_if_ins.state_if[0] -.sym 15474 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15475 spi_if_ins.state_if[1] -.sym 15476 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 15481 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15482 i_glob_clock$SB_IO_IN -.sym 15485 rx_fifo.wr_addr[9] -.sym 15486 w_rx_fifo_pull -.sym 15487 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 15488 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 15489 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15490 w_rx_fifo_pulled_data[27] -.sym 15491 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 15492 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 15494 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15495 spi_if_ins.w_rx_data[0] -.sym 15499 spi_if_ins.w_rx_data[1] -.sym 15500 spi_if_ins.w_rx_data[5] -.sym 15501 w_ioc[2] -.sym 15503 w_cs[2] -.sym 15504 spi_if_ins.w_rx_data[1] -.sym 15510 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 15513 w_cs[1] -.sym 15514 w_cs[3] -.sym 15518 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 15519 i_rst_b$SB_IO_IN -.sym 15520 io_ctrl_ins.o_data_out[1] -.sym 15521 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 15524 spi_if_ins.w_rx_data[5] -.sym 15525 w_tx_data_io -.sym 15526 w_tx_data_smi[1] -.sym 15529 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15530 spi_if_ins.state_if[0] -.sym 15531 w_cs[0] -.sym 15532 spi_if_ins.state_if[1] -.sym 15533 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15534 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15535 w_cs[2] -.sym 15537 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15538 spi_if_ins.w_rx_data[6] -.sym 15539 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15540 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15541 w_tx_data_smi[0] -.sym 15543 w_cs[2] -.sym 15544 w_cs[0] -.sym 15545 w_cs[3] -.sym 15546 w_cs[1] -.sym 15549 spi_if_ins.w_rx_data[6] -.sym 15551 spi_if_ins.w_rx_data[5] -.sym 15555 spi_if_ins.state_if[0] -.sym 15556 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15557 spi_if_ins.state_if[1] -.sym 15558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15561 spi_if_ins.w_rx_data[6] -.sym 15563 spi_if_ins.w_rx_data[5] -.sym 15568 spi_if_ins.w_rx_data[6] -.sym 15570 spi_if_ins.w_rx_data[5] -.sym 15573 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 15574 w_tx_data_io -.sym 15575 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15576 w_tx_data_smi[0] -.sym 15579 i_rst_b$SB_IO_IN -.sym 15580 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15581 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 15585 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15586 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 15587 io_ctrl_ins.o_data_out[1] -.sym 15588 w_tx_data_smi[1] -.sym 15589 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15353 rx_fifo.wr_addr_gray_rd_r[0] +.sym 15359 tx_fifo.rd_addr_gray_wr[9] +.sym 15369 spi_if_ins.spi.r2_rx_done +.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15400 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 15405 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15415 w_rx_fifo_empty +.sym 15445 w_rx_fifo_empty +.sym 15466 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15467 r_counter_$glb_clk +.sym 15468 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 15471 int_miso +.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15487 rx_fifo.wr_addr[8] +.sym 15488 rx_fifo.wr_addr[9] +.sym 15493 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15495 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15499 i_ss$SB_IO_IN +.sym 15503 $PACKER_VCC_NET +.sym 15510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 15512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 15514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 15520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15522 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 15527 $PACKER_VCC_NET +.sym 15528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15535 $PACKER_VCC_NET +.sym 15539 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15542 $nextpnr_ICESTORM_LC_9$O +.sym 15544 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15548 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 15550 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15551 $PACKER_VCC_NET +.sym 15555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 15557 $PACKER_VCC_NET +.sym 15558 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 15561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 15562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 15563 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 15564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 15570 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15573 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15576 $PACKER_VCC_NET +.sym 15579 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15585 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15586 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 15588 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15589 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 15590 r_counter_$glb_clk -.sym 15591 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15592 w_ioc[3] -.sym 15593 w_ioc[4] -.sym 15594 w_ioc[2] -.sym 15595 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15596 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 15597 w_cs[0] -.sym 15598 smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] -.sym 15599 w_ioc[1] -.sym 15604 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15605 i_rst_b$SB_IO_IN -.sym 15606 $PACKER_VCC_NET -.sym 15609 i_rst_b$SB_IO_IN -.sym 15611 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15612 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 15613 rx_fifo.rd_addr[0] -.sym 15616 spi_if_ins.w_rx_data[6] -.sym 15617 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 15618 i_button_SB_LUT4_I1_I0[0] -.sym 15619 w_cs[1] -.sym 15620 spi_if_ins.w_rx_data[2] -.sym 15621 io_ctrl_ins.o_data_out[6] -.sym 15623 w_ioc[1] -.sym 15624 spi_if_ins.w_rx_data[4] -.sym 15625 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15627 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 15633 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15634 w_cs[2] -.sym 15635 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 15636 w_cs[1] -.sym 15637 w_cs[3] -.sym 15638 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15640 smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] -.sym 15641 w_tx_data_io_SB_LUT4_I3_O[0] -.sym 15644 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 15645 spi_if_ins.state_if[0] -.sym 15646 w_tx_data_io_SB_LUT4_I3_O[3] -.sym 15647 spi_if_ins.state_if[1] -.sym 15648 w_tx_data_sys[1] -.sym 15649 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15650 w_tx_data_sys[3] -.sym 15651 io_ctrl_ins.o_data_out[3] -.sym 15652 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15654 w_cs[0] -.sym 15655 smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] -.sym 15657 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15658 i_glob_clock$SB_IO_IN -.sym 15660 w_tx_data_sys[2] -.sym 15661 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 15662 w_cs[0] -.sym 15666 w_cs[3] -.sym 15667 w_cs[2] -.sym 15668 w_cs[0] -.sym 15669 w_cs[1] -.sym 15672 smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] -.sym 15673 w_tx_data_sys[1] -.sym 15675 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15678 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15679 spi_if_ins.state_if[0] -.sym 15681 spi_if_ins.state_if[1] -.sym 15684 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15685 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15686 w_tx_data_sys[3] -.sym 15687 io_ctrl_ins.o_data_out[3] -.sym 15690 smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] -.sym 15691 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15692 w_tx_data_sys[2] -.sym 15693 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15698 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 15699 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 15705 w_cs[0] -.sym 15708 w_tx_data_io_SB_LUT4_I3_O[0] -.sym 15709 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15710 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 15711 w_tx_data_io_SB_LUT4_I3_O[3] -.sym 15712 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 15713 i_glob_clock$SB_IO_IN -.sym 15715 w_rx_data[6] -.sym 15716 w_rx_data[3] -.sym 15717 w_rx_data[1] -.sym 15718 w_rx_data[0] -.sym 15719 w_rx_data[2] -.sym 15720 w_rx_data[7] -.sym 15721 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 15722 w_rx_data[4] -.sym 15723 r_tx_data[2] -.sym 15727 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 15730 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 15731 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 15733 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 15735 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 15736 rx_fifo.rd_addr[9] -.sym 15737 w_tx_data_io_SB_LUT4_I3_O[0] -.sym 15738 w_ioc[2] -.sym 15739 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 15740 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 15743 smi_ctrl_ins.r_channel_SB_DFFER_Q_E -.sym 15744 i_button$SB_IO_IN -.sym 15745 io_ctrl_ins.o_data_out[7] -.sym 15746 i_button_SB_LUT4_I1_I0[0] -.sym 15747 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15748 w_rx_data[6] -.sym 15750 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 15757 spi_if_ins.spi.r_tx_byte[2] -.sym 15758 spi_if_ins.spi.r_tx_byte[6] -.sym 15759 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15760 w_load -.sym 15761 i_button_SB_LUT4_I1_I0[0] -.sym 15762 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 15763 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 15764 w_ioc[3] -.sym 15765 w_ioc[4] -.sym 15766 w_rx_fifo_pull -.sym 15767 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15768 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 15769 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 15770 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.sym 15772 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15773 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15774 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] -.sym 15775 w_cs[2] -.sym 15776 w_fetch -.sym 15783 i_rst_b$SB_IO_IN -.sym 15784 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 15785 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15789 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 15790 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 15791 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] -.sym 15792 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 15801 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 15802 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 15803 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15804 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.sym 15809 w_rx_fifo_pull -.sym 15810 i_rst_b$SB_IO_IN -.sym 15816 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15819 w_ioc[3] -.sym 15822 w_ioc[4] -.sym 15825 w_fetch -.sym 15826 i_button_SB_LUT4_I1_I0[0] -.sym 15827 w_load -.sym 15828 w_cs[2] -.sym 15831 spi_if_ins.spi.r_tx_byte[2] -.sym 15833 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15834 spi_if_ins.spi.r_tx_byte[6] -.sym 15835 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 15591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15592 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 15596 w_fetch +.sym 15597 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15598 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15602 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 15608 $PACKER_VCC_NET +.sym 15614 i_rst_b_SB_LUT4_I3_O +.sym 15615 int_miso +.sym 15619 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 15623 w_tx_data_io[7] +.sym 15627 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 15634 spi_if_ins.spi.r_tx_byte[0] +.sym 15635 spi_if_ins.spi.r_tx_byte[2] +.sym 15637 spi_if_ins.spi.r_tx_byte[5] +.sym 15640 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 15644 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15645 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15646 spi_if_ins.spi.r_tx_byte[6] +.sym 15647 spi_if_ins.spi.r_tx_byte[3] +.sym 15648 spi_if_ins.spi.r_tx_byte[1] +.sym 15650 spi_if_ins.spi.r_tx_byte[4] +.sym 15651 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 15653 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15654 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 15655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15656 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15658 spi_if_ins.r_tx_byte[7] +.sym 15661 spi_if_ins.spi.r_tx_byte[7] +.sym 15662 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15664 spi_if_ins.r_tx_byte[4] +.sym 15666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15667 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15668 spi_if_ins.spi.r_tx_byte[6] +.sym 15669 spi_if_ins.spi.r_tx_byte[4] +.sym 15673 spi_if_ins.r_tx_byte[4] +.sym 15679 spi_if_ins.spi.r_tx_byte[0] +.sym 15680 spi_if_ins.spi.r_tx_byte[1] +.sym 15681 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15684 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 15686 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 15687 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15692 spi_if_ins.r_tx_byte[7] +.sym 15696 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15697 spi_if_ins.spi.r_tx_byte[2] +.sym 15698 spi_if_ins.spi.r_tx_byte[3] +.sym 15702 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 15704 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 15708 spi_if_ins.spi.r_tx_byte[7] +.sym 15709 spi_if_ins.spi.r_tx_byte[5] +.sym 15710 spi_if_ins.spi.r_tx_bit_count[0] +.sym 15711 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 15712 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15713 r_counter_$glb_clk +.sym 15714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15715 w_cs[0] +.sym 15718 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15720 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15721 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 15722 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 15728 $PACKER_VCC_NET +.sym 15729 o_led1$SB_IO_OUT +.sym 15734 i_rst_b$SB_IO_IN +.sym 15741 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 15743 spi_if_ins.r_tx_byte[7] +.sym 15747 spi_if_ins.r_tx_byte[6] +.sym 15757 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15758 w_cs[1] +.sym 15760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15763 w_cs[3] +.sym 15767 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15768 w_cs[2] +.sym 15769 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15772 w_cs[0] +.sym 15773 spi_if_ins.r_tx_byte[6] +.sym 15776 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15778 spi_if_ins.r_tx_byte[1] +.sym 15780 spi_if_ins.r_tx_byte[3] +.sym 15782 spi_if_ins.r_tx_byte[0] +.sym 15784 i_rst_b$SB_IO_IN +.sym 15786 spi_if_ins.r_tx_byte[5] +.sym 15787 spi_if_ins.r_tx_byte[2] +.sym 15789 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15790 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15792 i_rst_b$SB_IO_IN +.sym 15795 spi_if_ins.r_tx_byte[0] +.sym 15801 spi_if_ins.r_tx_byte[2] +.sym 15807 w_cs[2] +.sym 15808 w_cs[1] +.sym 15809 w_cs[3] +.sym 15810 w_cs[0] +.sym 15814 spi_if_ins.r_tx_byte[5] +.sym 15819 spi_if_ins.r_tx_byte[6] +.sym 15826 spi_if_ins.r_tx_byte[3] +.sym 15834 spi_if_ins.r_tx_byte[1] +.sym 15835 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 15836 r_counter_$glb_clk -.sym 15837 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15838 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 15839 io_ctrl_ins.o_data_out[7] -.sym 15840 io_ctrl_ins.o_data_out[6] -.sym 15841 i_button_SB_LUT4_I1_I0[2] -.sym 15842 w_tx_data_io_SB_DFFESS_Q_E -.sym 15843 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] -.sym 15844 i_button_SB_LUT4_I1_O[1] -.sym 15845 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 15850 spi_if_ins.r_tx_byte[1] -.sym 15851 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 15852 w_tx_data_sys[1] -.sym 15853 w_rx_data[0] -.sym 15854 spi_if_ins.w_rx_data[3] -.sym 15855 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15856 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 15858 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.sym 15859 w_rx_data[3] -.sym 15860 w_fetch -.sym 15861 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 15862 w_rx_data[1] -.sym 15863 w_tx_data_io_SB_DFFESS_Q_E -.sym 15864 w_rx_data[0] -.sym 15865 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 15866 w_rx_data[2] -.sym 15868 w_rx_data[7] -.sym 15871 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 15872 w_rx_data[4] -.sym 15873 w_cs[1] -.sym 15879 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15882 w_rx_data[0] -.sym 15883 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15885 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 15889 w_cs[1] -.sym 15890 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 15891 w_fetch -.sym 15892 i_rst_b$SB_IO_IN -.sym 15893 w_ioc[1] -.sym 15901 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] -.sym 15906 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 15907 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] +.sym 15837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 15838 w_load +.sym 15839 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 15842 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 15843 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 15844 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 15845 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 15850 w_rx_data[2] +.sym 15852 w_rx_data[1] +.sym 15853 i_rst_b$SB_IO_IN +.sym 15855 spi_if_ins.w_rx_data[6] +.sym 15856 spi_if_ins.w_rx_data[0] +.sym 15857 w_cs[0] +.sym 15859 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15860 spi_if_ins.w_rx_data[5] +.sym 15865 w_fetch +.sym 15866 w_rx_data[7] +.sym 15868 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15871 w_load +.sym 15872 w_rx_data[7] +.sym 15879 w_tx_data_io[0] +.sym 15884 w_rx_data[2] +.sym 15887 w_cs[0] +.sym 15888 w_rx_data[0] +.sym 15890 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 15893 w_tx_data_io[7] +.sym 15895 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 15897 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 15898 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15899 w_cs[2] +.sym 15903 w_tx_data_smi[0] +.sym 15905 w_cs[1] +.sym 15910 w_cs[3] +.sym 15912 w_cs[2] +.sym 15913 w_cs[1] +.sym 15914 w_cs[3] +.sym 15915 w_cs[0] +.sym 15918 w_cs[0] +.sym 15919 w_cs[2] +.sym 15920 w_cs[1] +.sym 15921 w_cs[3] +.sym 15927 w_rx_data[2] .sym 15930 w_cs[1] -.sym 15932 w_fetch -.sym 15933 i_rst_b$SB_IO_IN -.sym 15936 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15943 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] -.sym 15945 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 15949 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 15950 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 15951 w_ioc[1] -.sym 15956 w_rx_data[0] -.sym 15958 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 15931 w_cs[3] +.sym 15932 w_cs[0] +.sym 15933 w_cs[2] +.sym 15936 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 15937 w_tx_data_smi[0] +.sym 15938 w_tx_data_io[0] +.sym 15939 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15942 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15944 w_tx_data_io[7] +.sym 15945 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 15948 w_cs[2] +.sym 15949 w_cs[1] +.sym 15950 w_cs[3] +.sym 15951 w_cs[0] +.sym 15957 w_rx_data[0] +.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E .sym 15959 r_counter_$glb_clk -.sym 15960 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15961 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 15962 i_button_SB_LUT4_I1_I0[3] -.sym 15963 io_ctrl_ins.o_pmod[6] -.sym 15964 io_ctrl_ins.o_pmod[7] -.sym 15965 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 15966 w_tx_data_io_SB_DFFESS_Q_S -.sym 15967 io_ctrl_ins.o_pmod[3] -.sym 15968 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] -.sym 15974 spi_if_ins.r_tx_byte[7] -.sym 15975 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 15978 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 15987 i_button_SB_LUT4_I1_I0[2] -.sym 15988 w_rx_data[2] -.sym 15989 w_rx_data[4] -.sym 15990 w_rx_data[7] -.sym 15992 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 15993 w_ioc[2] -.sym 15995 i_config[3]$SB_IO_IN -.sym 15996 w_rx_data[1] -.sym 16002 i_rst_b$SB_IO_IN -.sym 16005 i_button_SB_LUT4_I1_I0[2] -.sym 16010 w_fetch -.sym 16014 w_load -.sym 16020 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 16022 w_rx_data[1] -.sym 16026 w_rx_data[2] -.sym 16029 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 16031 w_tx_data_io_SB_DFFESS_Q_S -.sym 16033 w_cs[1] -.sym 16035 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 16036 i_button_SB_LUT4_I1_I0[2] -.sym 16042 w_rx_data[1] -.sym 16050 w_rx_data[2] -.sym 16053 w_load -.sym 16054 i_rst_b$SB_IO_IN -.sym 16055 w_fetch -.sym 16056 w_cs[1] -.sym 16061 w_tx_data_io_SB_DFFESS_Q_S -.sym 16072 i_button_SB_LUT4_I1_I0[2] -.sym 16081 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15961 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 15963 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 15964 i_button_SB_LUT4_I0_O[1] +.sym 15965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15966 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] +.sym 15967 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 15968 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 15974 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 15979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15980 w_rx_data[2] +.sym 15981 i_glob_clock$SB_IO_IN +.sym 15982 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 15983 w_cs[1] +.sym 15984 w_rx_data[0] +.sym 15987 w_rx_data[3] +.sym 15989 w_ioc[1] +.sym 15991 w_rx_data[5] +.sym 15992 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 15993 w_rx_data[4] +.sym 15996 w_tx_data_io[5] +.sym 16002 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 16003 w_tx_data_io[5] +.sym 16005 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16006 r_tx_data[5] +.sym 16008 r_tx_data[3] +.sym 16010 r_tx_data[1] +.sym 16011 r_tx_data[4] +.sym 16012 r_tx_data[7] +.sym 16013 r_tx_data[6] +.sym 16017 r_tx_data[0] +.sym 16020 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 16035 r_tx_data[3] +.sym 16042 r_tx_data[4] +.sym 16048 r_tx_data[7] +.sym 16055 r_tx_data[1] +.sym 16059 r_tx_data[6] +.sym 16066 r_tx_data[0] +.sym 16071 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 16072 w_tx_data_io[5] +.sym 16074 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 16080 r_tx_data[5] +.sym 16081 spi_if_ins.r_tx_byte_SB_DFFE_Q_E .sym 16082 r_counter_$glb_clk -.sym 16085 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E -.sym 16086 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 16088 io_ctrl_ins.o_data_out[2] -.sym 16089 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R -.sym 16091 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] +.sym 16084 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 16085 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.sym 16086 io_ctrl_ins.pmod_dir_state[7] +.sym 16087 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.sym 16089 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 16090 io_ctrl_ins.pmod_dir_state[6] +.sym 16091 io_ctrl_ins.pmod_dir_state[4] .sym 16095 i_rst_b$SB_IO_IN -.sym 16096 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 16100 spi_if_ins.r_tx_byte[6] -.sym 16102 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 16134 w_rx_data[1] -.sym 16136 w_rx_data[0] -.sym 16138 w_rx_data[2] -.sym 16140 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 16143 io_ctrl_ins.o_pmod[2] -.sym 16144 w_rx_data[4] -.sym 16147 i_button_SB_LUT4_I1_I0[2] -.sym 16148 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 16151 o_shdn_tx_lna$SB_IO_OUT -.sym 16152 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 16156 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 16160 w_rx_data[0] -.sym 16167 w_rx_data[1] -.sym 16170 w_rx_data[2] -.sym 16176 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 16177 io_ctrl_ins.o_pmod[2] -.sym 16178 o_shdn_tx_lna$SB_IO_OUT -.sym 16179 i_button_SB_LUT4_I1_I0[2] -.sym 16183 w_rx_data[4] -.sym 16189 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 16191 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 16204 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 16096 w_tx_data_io[0] +.sym 16097 i_rst_b$SB_IO_IN +.sym 16098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 16099 i_button_SB_LUT4_I0_O[1] +.sym 16106 w_tx_data_io[1] +.sym 16110 w_tx_data_io[7] +.sym 16125 w_cs[0] +.sym 16126 w_rx_data[1] +.sym 16128 w_rx_data[2] +.sym 16130 w_rx_data[6] +.sym 16135 w_fetch +.sym 16138 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] +.sym 16144 w_rx_data[7] +.sym 16147 w_rx_data[3] +.sym 16151 w_rx_data[5] +.sym 16152 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 16153 w_rx_data[4] +.sym 16159 w_rx_data[6] +.sym 16165 w_rx_data[3] +.sym 16171 w_rx_data[2] +.sym 16178 w_rx_data[5] +.sym 16185 w_rx_data[7] +.sym 16188 w_rx_data[1] +.sym 16194 w_cs[0] +.sym 16196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] +.sym 16197 w_fetch +.sym 16200 w_rx_data[4] +.sym 16204 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E .sym 16205 r_counter_$glb_clk -.sym 16207 io_ctrl_ins.rf_pin_state[6] -.sym 16208 io_ctrl_ins.rf_pin_state[2] -.sym 16209 io_ctrl_ins.rf_pin_state[7] -.sym 16210 io_ctrl_ins.rf_pin_state[0] -.sym 16211 io_ctrl_ins.rf_pin_state[4] -.sym 16212 io_ctrl_ins.rf_pin_state[1] -.sym 16213 io_ctrl_ins.rf_pin_state[5] -.sym 16214 io_ctrl_ins.rf_pin_state[3] -.sym 16219 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 16229 io_ctrl_ins.o_pmod[4] -.sym 16231 o_shdn_rx_lna$SB_IO_OUT -.sym 16236 i_button$SB_IO_IN -.sym 16249 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 16250 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 16252 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 16253 io_ctrl_ins.debug_mode[0] -.sym 16257 w_rx_data[3] -.sym 16258 w_rx_data[2] -.sym 16259 io_ctrl_ins.mixer_en_state -.sym 16261 w_rx_data[4] -.sym 16265 w_ioc[2] -.sym 16266 w_rx_data[1] -.sym 16274 io_ctrl_ins.debug_mode[1] -.sym 16283 w_rx_data[4] -.sym 16290 w_rx_data[3] -.sym 16295 w_rx_data[1] -.sym 16299 io_ctrl_ins.debug_mode[1] -.sym 16301 io_ctrl_ins.debug_mode[0] -.sym 16306 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 16308 io_ctrl_ins.debug_mode[1] -.sym 16311 io_ctrl_ins.debug_mode[0] -.sym 16312 io_ctrl_ins.mixer_en_state -.sym 16313 w_ioc[2] -.sym 16314 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 16325 w_rx_data[2] -.sym 16327 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 16206 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16207 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 16208 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 16209 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 16212 w_tx_data_io[5] +.sym 16213 i_button_SB_LUT4_I0_O[2] +.sym 16214 w_tx_data_io[7] +.sym 16219 w_cs[1] +.sym 16221 i_rst_b$SB_IO_IN +.sym 16226 w_rx_data[6] +.sym 16232 i_config[3]$SB_IO_IN +.sym 16238 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 16262 w_rx_data[0] +.sym 16266 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 16318 w_rx_data[0] +.sym 16327 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E .sym 16328 r_counter_$glb_clk .sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16333 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 16336 o_shdn_rx_lna$SB_IO_OUT -.sym 16337 o_tr_vc2$SB_IO_OUT -.sym 16342 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 16344 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 16346 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 16350 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 16371 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 16372 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 16374 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 16375 i_rst_b$SB_IO_IN -.sym 16380 io_ctrl_ins.rf_pin_state[2] -.sym 16382 io_ctrl_ins.rf_pin_state[0] -.sym 16392 io_ctrl_ins.debug_mode[0] -.sym 16398 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 16410 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 16411 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 16412 io_ctrl_ins.debug_mode[0] -.sym 16413 i_rst_b$SB_IO_IN -.sym 16422 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 16423 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 16424 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 16425 io_ctrl_ins.rf_pin_state[0] -.sym 16434 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 16435 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 16436 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 16437 io_ctrl_ins.rf_pin_state[2] -.sym 16450 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 16451 r_counter_$glb_clk +.sym 16334 io_ctrl_ins.pmod_dir_state[5] +.sym 16354 i_button$SB_IO_IN +.sym 16361 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 16371 i_glob_clock$SB_IO_IN +.sym 16400 r_counter +.sym 16437 r_counter +.sym 16451 i_glob_clock$SB_IO_IN +.sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN -.sym 16482 i_config[3]$SB_IO_IN -.sym 16497 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16517 w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16523 o_led1$SB_IO_OUT -.sym 16553 tx_fifo.wr_addr[6] -.sym 16554 tx_fifo.wr_addr_gray[5] -.sym 16555 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 16556 tx_fifo.wr_addr[8] -.sym 16557 smi_ctrl_ins.soe_and_reset -.sym 16558 tx_fifo.wr_addr[2] -.sym 16559 tx_fifo.wr_addr[4] -.sym 16560 tx_fifo.wr_addr[7] -.sym 16587 o_led0$SB_IO_OUT -.sym 16600 tx_fifo.wr_addr[0] -.sym 16601 tx_fifo.wr_addr[3] -.sym 16608 tx_fifo.wr_addr[0] -.sym 16613 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 16616 tx_fifo.wr_addr[2] -.sym 16617 tx_fifo.wr_addr[4] -.sym 16618 tx_fifo.wr_addr[7] -.sym 16619 tx_fifo.wr_addr[6] -.sym 16626 tx_fifo.wr_addr[5] -.sym 16627 $nextpnr_ICESTORM_LC_0$O -.sym 16629 tx_fifo.wr_addr[0] -.sym 16633 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 16635 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 16637 tx_fifo.wr_addr[0] -.sym 16639 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 16641 tx_fifo.wr_addr[2] -.sym 16643 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 16645 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 16647 tx_fifo.wr_addr[3] -.sym 16649 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 16651 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 16654 tx_fifo.wr_addr[4] -.sym 16655 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 16657 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 16659 tx_fifo.wr_addr[5] -.sym 16661 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 16663 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 16665 tx_fifo.wr_addr[6] -.sym 16667 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 16669 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 16672 tx_fifo.wr_addr[7] -.sym 16673 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 16682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 16683 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] -.sym 16684 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 16686 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 16687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 16688 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 16695 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 16716 w_smi_data_output[5] -.sym 16725 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 16727 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 16729 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16734 w_smi_data_output[4] -.sym 16735 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 16736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 16741 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 16743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 16744 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16747 tx_fifo.wr_addr[5] -.sym 16753 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 16758 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 16760 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 16761 tx_fifo.wr_addr[8] -.sym 16763 tx_fifo.wr_addr[0] -.sym 16769 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 16770 tx_fifo.wr_addr[9] -.sym 16773 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 16779 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 16782 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 16785 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16790 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 16792 tx_fifo.wr_addr[8] -.sym 16794 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 16799 tx_fifo.wr_addr[9] -.sym 16800 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 16803 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 16805 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 16809 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 16815 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 16817 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 16823 tx_fifo.wr_addr[0] -.sym 16829 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 16833 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16838 r_counter_$glb_clk -.sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] -.sym 16841 w_tx_fifo_empty -.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 16843 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 16845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 16861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 16865 o_led0$SB_IO_OUT -.sym 16867 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16871 tx_fifo.wr_addr[0] -.sym 16874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 16875 w_tx_fifo_empty -.sym 16881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] -.sym 16882 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 16883 tx_fifo.rd_addr_gray_wr[5] -.sym 16884 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] -.sym 16885 tx_fifo.rd_addr_gray_wr_r[4] -.sym 16886 tx_fifo.rd_addr_gray_wr_r[0] -.sym 16887 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 16888 tx_fifo.rd_addr_gray_wr_r[6] -.sym 16889 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 16890 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 16891 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 16892 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 16893 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 16894 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 16895 spi_if_ins.spi.r_rx_done -.sym 16896 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] -.sym 16897 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 16900 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.sym 16902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 16903 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 16904 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 16905 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 16906 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 16908 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 16909 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16912 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 16914 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 16915 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 16916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 16917 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 16920 tx_fifo.rd_addr_gray_wr_r[6] -.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 16922 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 16926 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] -.sym 16927 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 16928 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] -.sym 16929 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] -.sym 16932 spi_if_ins.spi.r_rx_done -.sym 16938 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 16939 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.sym 16940 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 16941 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 16944 tx_fifo.rd_addr_gray_wr_r[0] -.sym 16945 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 16946 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 16947 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 16950 tx_fifo.rd_addr_gray_wr[5] -.sym 16956 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 16957 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 16958 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 16959 tx_fifo.rd_addr_gray_wr_r[4] +.sym 16479 w_rx_data[5] +.sym 16497 r_counter +.sym 16512 r_counter +.sym 16554 tx_fifo.wr_addr_gray_rd[6] +.sym 16560 tx_fifo.wr_addr_gray_rd[0] +.sym 16585 i_smi_soe_se$SB_IO_IN +.sym 16586 $PACKER_VCC_NET +.sym 16587 w_smi_data_input[7] +.sym 16596 i_smi_soe_se$SB_IO_IN +.sym 16599 i_smi_swe_srw$SB_IO_IN +.sym 16600 tx_fifo.wr_addr_gray_rd[4] +.sym 16606 i_rst_b$SB_IO_IN +.sym 16612 tx_fifo.wr_addr_gray[4] +.sym 16618 tx_fifo.wr_addr_gray_rd[0] +.sym 16620 tx_fifo.wr_addr_gray_rd[6] +.sym 16635 tx_fifo.wr_addr_gray_rd[6] +.sym 16648 tx_fifo.wr_addr_gray_rd[0] +.sym 16652 i_smi_swe_srw$SB_IO_IN +.sym 16654 i_rst_b$SB_IO_IN +.sym 16658 tx_fifo.wr_addr_gray[4] +.sym 16667 tx_fifo.wr_addr_gray_rd[4] +.sym 16670 i_smi_soe_se$SB_IO_IN +.sym 16671 i_rst_b$SB_IO_IN +.sym 16675 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16681 tx_fifo.wr_addr_gray[0] +.sym 16682 tx_fifo.wr_addr_gray[4] +.sym 16683 tx_fifo.wr_addr[6] +.sym 16684 tx_fifo.wr_addr[7] +.sym 16685 tx_fifo.wr_addr[4] +.sym 16686 tx_fifo.wr_addr[3] +.sym 16687 tx_fifo.wr_addr[5] +.sym 16688 tx_fifo.wr_addr_gray[6] +.sym 16703 smi_ctrl_ins.swe_and_reset +.sym 16704 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 16723 smi_ctrl_ins.swe_and_reset +.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 16743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16751 w_smi_data_output[4] +.sym 16776 tx_fifo.wr_addr[1] +.sym 16777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16778 tx_fifo.wr_addr[4] +.sym 16779 tx_fifo.wr_addr[3] +.sym 16780 tx_fifo.wr_addr[0] +.sym 16784 tx_fifo.wr_addr[6] +.sym 16785 tx_fifo.wr_addr[7] +.sym 16788 tx_fifo.wr_addr[5] +.sym 16790 $nextpnr_ICESTORM_LC_3$O +.sym 16793 tx_fifo.wr_addr[0] +.sym 16796 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 16798 tx_fifo.wr_addr[1] +.sym 16800 tx_fifo.wr_addr[0] +.sym 16802 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 16808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16811 tx_fifo.wr_addr[3] +.sym 16812 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16814 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 16817 tx_fifo.wr_addr[4] +.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16820 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16823 tx_fifo.wr_addr[5] +.sym 16824 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 16826 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16828 tx_fifo.wr_addr[6] +.sym 16830 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16832 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16834 tx_fifo.wr_addr[7] +.sym 16836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 16841 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 16842 tx_fifo.wr_addr[1] +.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16844 tx_fifo.wr_addr[8] +.sym 16845 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 16846 tx_fifo.wr_addr[0] +.sym 16847 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 16853 tx_fifo.wr_addr[5] +.sym 16865 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 16867 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 16875 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 16876 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16882 tx_fifo.wr_addr[9] +.sym 16883 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 16884 tx_fifo.rd_addr_gray_wr[6] +.sym 16885 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16886 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 16888 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16895 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 16896 rx_fifo.wr_addr_gray[0] +.sym 16903 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16907 tx_fifo.rd_addr_gray_wr[4] +.sym 16909 tx_fifo.wr_addr[8] +.sym 16910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 16911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 16913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 16915 tx_fifo.wr_addr[8] +.sym 16917 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16920 tx_fifo.wr_addr[9] +.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 16929 tx_fifo.rd_addr_gray_wr[6] +.sym 16933 rx_fifo.wr_addr_gray[0] +.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 16940 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 16944 tx_fifo.rd_addr_gray_wr[4] +.sym 16950 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 16952 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 16953 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] .sym 16961 r_counter_$glb_clk -.sym 16965 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 16967 o_smi_read_req$SB_IO_OUT -.sym 16968 tx_fifo.wr_addr[5] -.sym 16969 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] -.sym 16974 w_rx_data[2] -.sym 16976 spi_if_ins.w_rx_data[1] -.sym 16983 spi_if_ins.spi.r_rx_done -.sym 16984 tx_fifo.rd_addr_gray_wr_r[6] -.sym 16987 tx_fifo.rd_addr_gray_wr_r[2] -.sym 16988 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 16990 spi_if_ins.spi.r2_rx_done -.sym 16991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 16993 tx_fifo.rd_addr[5] -.sym 16994 w_smi_data_output[5] -.sym 16995 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16998 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 17009 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 17010 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 17013 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 17015 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 17016 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 17022 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 17023 tx_fifo.rd_addr_gray_wr[9] -.sym 17024 tx_fifo.rd_addr_gray_wr[3] -.sym 17025 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 17027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 17030 tx_fifo.rd_addr_gray_wr[0] -.sym 17032 tx_fifo.rd_addr_gray[8] -.sym 17033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] -.sym 17035 tx_fifo.rd_addr_gray[1] -.sym 17037 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 17038 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 17039 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 17040 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 17043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 17044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 17045 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 17046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] -.sym 17050 tx_fifo.rd_addr_gray[8] -.sym 17058 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 17064 tx_fifo.rd_addr_gray_wr[0] -.sym 17068 tx_fifo.rd_addr_gray[1] -.sym 17076 tx_fifo.rd_addr_gray_wr[9] -.sym 17080 tx_fifo.rd_addr_gray_wr[3] -.sym 17084 r_counter_$glb_clk -.sym 17087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 17088 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 17090 tx_fifo.rd_addr_gray[8] -.sym 17091 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] -.sym 17092 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] -.sym 17093 tx_fifo.rd_addr_gray[1] -.sym 17096 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 17099 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 17101 w_tx_fifo_full -.sym 17102 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 17105 spi_if_ins.w_rx_data[6] -.sym 17107 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 17108 rx_fifo.rd_addr[3] -.sym 17109 rx_fifo.rd_addr[6] -.sym 17110 tx_fifo.rd_addr_gray_wr[3] -.sym 17111 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 17112 w_smi_data_output[4] -.sym 17115 tx_fifo.rd_addr_gray_wr[2] -.sym 17116 w_rx_fifo_pulled_data[28] -.sym 17117 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17119 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17121 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 17128 smi_ctrl_ins.int_cnt_rx[4] -.sym 17131 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] -.sym 17132 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 17134 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] -.sym 17136 smi_ctrl_ins.int_cnt_rx[4] -.sym 17137 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 17138 i_rst_b$SB_IO_IN -.sym 17142 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 17143 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 17148 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 17149 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 17150 smi_ctrl_ins.int_cnt_rx[3] -.sym 17151 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 17156 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 17157 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] -.sym 17158 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 17166 smi_ctrl_ins.int_cnt_rx[4] -.sym 17167 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 17168 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 17169 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] -.sym 17175 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 17178 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 17179 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 17185 smi_ctrl_ins.int_cnt_rx[4] -.sym 17187 smi_ctrl_ins.int_cnt_rx[3] -.sym 17190 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] -.sym 17191 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 17192 smi_ctrl_ins.int_cnt_rx[4] -.sym 17193 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 17196 smi_ctrl_ins.int_cnt_rx[4] -.sym 17197 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 17198 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 17199 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] -.sym 17206 i_rst_b$SB_IO_IN -.sym 17207 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 17212 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 17213 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 17215 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 17216 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 17221 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 17222 smi_ctrl_ins.int_cnt_rx[4] -.sym 17225 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17226 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 17227 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 17230 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 17233 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17243 smi_ctrl_ins.int_cnt_rx[3] -.sym 17252 tx_fifo.rd_addr_gray_wr[1] -.sym 17253 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 17254 tx_fifo.rd_addr_gray_wr[8] -.sym 17256 spi_if_ins.spi.r3_rx_done -.sym 17260 spi_if_ins.spi.r2_rx_done -.sym 17265 tx_fifo.rd_addr[5] -.sym 17266 smi_ctrl_ins.int_cnt_rx[4] -.sym 17268 smi_ctrl_ins.int_cnt_rx[3] -.sym 17275 tx_fifo.rd_addr_gray_wr[2] -.sym 17278 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 17280 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 17281 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 17283 tx_fifo.rd_addr_gray_wr[2] -.sym 17290 spi_if_ins.spi.r3_rx_done -.sym 17291 spi_if_ins.spi.r2_rx_done -.sym 17297 tx_fifo.rd_addr_gray_wr[1] -.sym 17302 tx_fifo.rd_addr[5] -.sym 17303 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 17304 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 17309 tx_fifo.rd_addr_gray_wr[8] -.sym 17322 spi_if_ins.spi.r2_rx_done -.sym 17325 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 17326 smi_ctrl_ins.int_cnt_rx[4] -.sym 17327 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 17328 smi_ctrl_ins.int_cnt_rx[3] -.sym 17330 r_counter_$glb_clk -.sym 17336 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 17338 smi_ctrl_ins.r_fifo_pull_1 -.sym 17342 w_rx_data[4] -.sym 17345 spi_if_ins.w_rx_data[3] -.sym 17348 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17349 spi_if_ins.w_rx_data[6] -.sym 17350 rx_fifo.rd_addr[6] -.sym 17353 rx_fifo.rd_addr[9] -.sym 17354 rx_fifo.rd_addr[0] -.sym 17357 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 17358 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 17359 $PACKER_VCC_NET -.sym 17361 i_rst_b$SB_IO_IN -.sym 17362 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 17374 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17448 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 16963 tx_fifo.wr_addr_gray[8] +.sym 16964 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 16965 tx_fifo.wr_addr_gray[2] +.sym 16966 tx_fifo.wr_addr_gray[1] +.sym 16967 tx_fifo.wr_addr_gray[7] +.sym 16968 tx_fifo.wr_addr_gray[3] +.sym 16970 tx_fifo.wr_addr_gray[5] +.sym 16977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 16979 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 16980 rx_fifo.mem_i.0.1_WDATA_3 +.sym 16981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 16986 tx_fifo.wr_addr[9] +.sym 16988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16989 tx_fifo.rd_addr[1] +.sym 16990 o_led1$SB_IO_OUT +.sym 16993 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 16998 o_led1$SB_IO_OUT +.sym 17004 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 17005 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 17008 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 17009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 17011 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 17012 tx_fifo.rd_addr_gray_wr_r[8] +.sym 17013 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 17014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 17015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 17016 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 17019 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 17020 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 17022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17024 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 17025 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 17026 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 17027 w_smi_data_input[7] +.sym 17029 smi_ctrl_ins.swe_and_reset +.sym 17030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17037 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 17038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 17040 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 17045 w_smi_data_input[7] +.sym 17050 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 17052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 17061 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 17063 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 17064 tx_fifo.rd_addr_gray_wr_r[8] +.sym 17067 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 17068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17069 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 17070 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 17079 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 17080 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 17081 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 17082 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 17084 smi_ctrl_ins.swe_and_reset +.sym 17085 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 17086 tx_fifo.wr_addr_gray_rd[1] +.sym 17087 tx_fifo.wr_addr_gray_rd[3] +.sym 17088 tx_fifo.wr_addr_gray_rd[2] +.sym 17089 tx_fifo.wr_addr_gray_rd[8] +.sym 17092 tx_fifo.wr_addr_gray_rd[5] +.sym 17093 tx_fifo.wr_addr_gray_rd[7] +.sym 17098 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 17102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17112 o_led1$SB_IO_OUT +.sym 17115 smi_ctrl_ins.swe_and_reset +.sym 17129 tx_fifo.rd_addr_gray_wr[8] +.sym 17131 tx_fifo.rd_addr_gray[8] +.sym 17136 tx_fifo.rd_addr_gray[1] +.sym 17141 tx_fifo.rd_addr_gray_wr[1] +.sym 17145 tx_fifo.rd_addr_gray[4] +.sym 17147 tx_fifo.rd_addr_gray[7] +.sym 17154 tx_fifo.rd_addr_gray_wr[2] +.sym 17155 tx_fifo.rd_addr_gray_wr[7] +.sym 17160 tx_fifo.rd_addr_gray_wr[8] +.sym 17169 tx_fifo.rd_addr_gray[4] +.sym 17172 tx_fifo.rd_addr_gray[8] +.sym 17181 tx_fifo.rd_addr_gray_wr[2] +.sym 17184 tx_fifo.rd_addr_gray[7] +.sym 17192 tx_fifo.rd_addr_gray_wr[1] +.sym 17198 tx_fifo.rd_addr_gray[1] +.sym 17204 tx_fifo.rd_addr_gray_wr[7] +.sym 17207 r_counter_$glb_clk +.sym 17209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17214 tx_fifo.rd_addr_gray_wr[0] +.sym 17221 tx_fifo.rd_addr_gray_wr_r[8] +.sym 17223 w_rx_fifo_pulled_data[4] +.sym 17229 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 17232 rx_fifo.wr_addr[9] +.sym 17240 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 17242 rx_fifo.rd_addr[8] +.sym 17244 o_led1$SB_IO_OUT +.sym 17261 tx_fifo.rd_addr[1] +.sym 17263 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 17264 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 17265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 17268 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 17292 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 17308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 17316 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 17326 tx_fifo.rd_addr[1] +.sym 17329 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 17330 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 17333 spi_if_ins.spi.r3_rx_done +.sym 17335 tx_fifo.rd_addr_gray_wr[5] +.sym 17336 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17343 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17345 tx_fifo.wr_addr_gray_rd[9] +.sym 17346 w_rx_fifo_pulled_data[5] +.sym 17348 w_rx_fifo_pulled_data[7] +.sym 17394 tx_fifo.rd_addr_gray[6] +.sym 17397 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 17445 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 17448 tx_fifo.rd_addr_gray[6] .sym 17453 r_counter_$glb_clk -.sym 17456 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 17457 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 17459 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 17461 spi_if_ins.r_tx_data_valid -.sym 17462 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17466 w_rx_data[6] -.sym 17467 spi_if_ins.w_rx_data[5] -.sym 17471 w_rx_fifo_pulled_data[26] -.sym 17472 spi_if_ins.w_rx_data[0] -.sym 17479 w_ioc[3] -.sym 17480 io_ctrl_ins.o_data_out[2] -.sym 17481 w_ioc[4] -.sym 17482 spi_if_ins.w_rx_data[4] -.sym 17483 w_ioc[2] -.sym 17484 spi_if_ins.w_rx_data[2] -.sym 17485 $PACKER_VCC_NET -.sym 17487 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 17489 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 17490 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17496 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17497 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 17500 spi_if_ins.state_if[0] -.sym 17502 spi_if_ins.state_if[1] -.sym 17504 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17509 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17511 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17513 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 17514 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 17519 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17521 i_rst_b$SB_IO_IN -.sym 17524 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 17525 smi_ctrl_ins.int_cnt_rx[3] -.sym 17535 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17536 spi_if_ins.state_if[0] -.sym 17538 spi_if_ins.state_if[1] -.sym 17542 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 17543 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 17544 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 17553 i_rst_b$SB_IO_IN -.sym 17554 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 17560 smi_ctrl_ins.int_cnt_rx[3] -.sym 17565 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17566 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17568 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17572 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17573 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 17574 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17576 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 17577 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17579 $PACKER_VCC_NET -.sym 17580 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17582 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17583 $PACKER_VCC_NET -.sym 17584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 17585 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 17588 w_rx_data[3] -.sym 17590 rx_fifo.rd_addr[6] -.sym 17591 spi_if_ins.r_tx_data_valid -.sym 17593 spi_if_ins.w_rx_data[2] -.sym 17595 spi_if_ins.w_rx_data[4] -.sym 17596 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 17597 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 17599 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 17600 rx_fifo.rd_addr[3] -.sym 17601 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17604 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 17605 w_ioc[1] -.sym 17607 sys_ctrl_ins.tx_sample_gap[3] -.sym 17608 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 17611 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 17612 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17613 sys_ctrl_ins.tx_sample_gap[0] -.sym 17620 w_cs[2] -.sym 17621 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 17622 w_cs[1] -.sym 17623 w_cs[3] -.sym 17625 i_rst_b$SB_IO_IN -.sym 17626 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17628 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 17629 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17630 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 17632 w_cs[0] -.sym 17633 i_rst_b$SB_IO_IN -.sym 17636 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 17637 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17642 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 17643 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17645 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17650 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17653 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 17659 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 17660 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17670 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17671 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17672 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17673 i_rst_b$SB_IO_IN -.sym 17679 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 17682 w_cs[2] -.sym 17683 w_cs[0] -.sym 17684 w_cs[1] -.sym 17685 w_cs[3] -.sym 17688 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 17689 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 17691 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17695 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17696 i_rst_b$SB_IO_IN -.sym 17697 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17698 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 17461 spi_if_ins.spi.SCKr[0] +.sym 17471 w_rx_fifo_pulled_data[30] +.sym 17473 $PACKER_VCC_NET +.sym 17476 i_ss$SB_IO_IN +.sym 17482 o_led1$SB_IO_OUT +.sym 17487 w_fetch +.sym 17506 rx_fifo.wr_addr_gray_rd[0] +.sym 17573 rx_fifo.wr_addr_gray_rd[0] +.sym 17576 r_counter_$glb_clk +.sym 17578 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 17582 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17584 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 17591 rx_fifo.rd_addr[4] +.sym 17594 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 17598 i_sck$SB_IO_IN +.sym 17603 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17608 o_led1$SB_IO_OUT +.sym 17610 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17621 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17624 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17630 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 17632 spi_if_ins.r_tx_byte[7] +.sym 17635 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 17641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 17664 spi_if_ins.r_tx_byte[7] +.sym 17666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 17667 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17682 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17683 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 17685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 17698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 17699 r_counter_$glb_clk -.sym 17700 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17701 w_tx_data_io_SB_LUT4_I3_O[0] -.sym 17703 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 17706 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 17707 w_tx_data_sys[3] -.sym 17708 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 17713 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 17714 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 17715 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 17718 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 17722 $PACKER_VCC_NET -.sym 17724 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17727 w_cs[0] -.sym 17728 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 17731 w_ioc[1] -.sym 17734 w_rx_data[1] -.sym 17736 w_rx_data[0] -.sym 17744 spi_if_ins.w_rx_data[1] -.sym 17749 spi_if_ins.w_rx_data[3] -.sym 17750 io_ctrl_ins.o_data_out[2] -.sym 17752 spi_if_ins.w_rx_data[4] -.sym 17753 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 17754 spi_if_ins.w_rx_data[2] -.sym 17755 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 17756 spi_if_ins.w_rx_data[0] -.sym 17758 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 17761 w_cs[1] -.sym 17762 w_cs[3] -.sym 17763 w_cs[0] -.sym 17767 w_cs[2] -.sym 17769 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 17770 w_tx_data_smi[2] -.sym 17776 spi_if_ins.w_rx_data[3] -.sym 17783 spi_if_ins.w_rx_data[4] -.sym 17790 spi_if_ins.w_rx_data[2] -.sym 17793 w_cs[0] -.sym 17794 w_cs[3] -.sym 17795 w_cs[1] -.sym 17796 w_cs[2] -.sym 17802 spi_if_ins.w_rx_data[0] -.sym 17806 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 17811 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 17812 io_ctrl_ins.o_data_out[2] -.sym 17813 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 17814 w_tx_data_smi[2] -.sym 17818 spi_if_ins.w_rx_data[1] -.sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17702 o_led1$SB_IO_OUT +.sym 17703 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17720 spi_if_ins.r_tx_byte[7] +.sym 17721 w_rx_fifo_empty +.sym 17727 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 17728 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17736 o_led1$SB_IO_OUT +.sym 17746 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17752 i_ss$SB_IO_IN +.sym 17755 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17764 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 17766 spi_if_ins.r_tx_data_valid +.sym 17777 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17799 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 17805 i_ss$SB_IO_IN +.sym 17807 spi_if_ins.r_tx_data_valid +.sym 17812 spi_if_ins.r_tx_data_valid +.sym 17814 i_ss$SB_IO_IN +.sym 17821 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .sym 17822 r_counter_$glb_clk -.sym 17824 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] -.sym 17825 w_tx_data_sys[1] -.sym 17827 w_tx_data_sys[2] -.sym 17828 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 17829 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 17831 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.sym 17834 w_rx_data[0] -.sym 17837 w_tx_data_sys[3] -.sym 17840 spi_if_ins.r_tx_byte[7] -.sym 17844 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 17845 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 17848 i_rst_b$SB_IO_IN -.sym 17849 w_ioc[2] -.sym 17850 w_rx_data[7] -.sym 17851 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 17853 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 17854 w_rx_data[4] -.sym 17856 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 17857 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 17858 w_rx_data[3] -.sym 17865 spi_if_ins.w_rx_data[2] -.sym 17867 spi_if_ins.w_rx_data[1] -.sym 17869 spi_if_ins.w_rx_data[4] -.sym 17872 w_ioc[1] -.sym 17875 w_ioc[2] -.sym 17876 spi_if_ins.w_rx_data[0] -.sym 17877 spi_if_ins.w_rx_data[6] -.sym 17878 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 17880 spi_if_ins.w_rx_data[3] -.sym 17883 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 17884 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17899 spi_if_ins.w_rx_data[6] -.sym 17905 spi_if_ins.w_rx_data[3] -.sym 17912 spi_if_ins.w_rx_data[1] -.sym 17919 spi_if_ins.w_rx_data[0] -.sym 17922 spi_if_ins.w_rx_data[2] -.sym 17928 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 17934 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 17935 w_ioc[1] -.sym 17937 w_ioc[2] -.sym 17943 spi_if_ins.w_rx_data[4] -.sym 17944 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O +.sym 17823 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17824 w_ioc[1] +.sym 17827 w_ioc[4] +.sym 17828 w_ioc[3] +.sym 17829 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 17830 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 17831 w_ioc[2] +.sym 17836 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17839 w_rx_data[7] +.sym 17846 w_fetch +.sym 17847 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17849 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 17853 w_fetch +.sym 17855 spi_if_ins.w_rx_data[4] +.sym 17857 w_ioc[1] +.sym 17858 i_config[1]$SB_IO_IN +.sym 17868 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 17870 spi_if_ins.w_rx_data[5] +.sym 17871 i_rst_b$SB_IO_IN +.sym 17874 spi_if_ins.w_rx_data[0] +.sym 17876 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17877 w_fetch +.sym 17879 spi_if_ins.w_rx_data[6] +.sym 17881 w_ioc[1] +.sym 17889 w_cs[2] +.sym 17894 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 17895 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 17901 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 17916 spi_if_ins.w_rx_data[5] +.sym 17918 spi_if_ins.w_rx_data[6] +.sym 17928 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 17929 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 17930 w_cs[2] +.sym 17931 w_ioc[1] +.sym 17936 i_rst_b$SB_IO_IN +.sym 17937 w_fetch +.sym 17941 spi_if_ins.w_rx_data[0] +.sym 17944 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 17945 r_counter_$glb_clk -.sym 17950 sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] -.sym 17952 io_ctrl_ins.o_data_out[5] -.sym 17960 spi_if_ins.spi.r_tx_byte[7] -.sym 17961 w_rx_data[7] -.sym 17963 w_rx_data[3] -.sym 17964 spi_if_ins.spi.r_tx_byte[5] -.sym 17965 w_rx_data[1] -.sym 17968 spi_if_ins.spi.r_tx_byte[4] -.sym 17969 w_rx_data[2] -.sym 17970 sys_ctrl_ins.tx_sample_gap[2] -.sym 17971 w_tx_data_io_SB_DFFESS_Q_E -.sym 17972 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 17973 w_tx_data_sys[2] -.sym 17976 i_button_SB_LUT4_I1_I0[1] -.sym 17978 io_ctrl_ins.o_data_out[4] -.sym 17979 io_ctrl_ins.o_data_out[2] -.sym 17980 i_config[1]$SB_IO_IN -.sym 17982 io_ctrl_ins.o_data_out[3] -.sym 17988 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 17990 io_ctrl_ins.o_pmod[6] -.sym 17991 i_button_SB_LUT4_I1_I0[0] -.sym 17993 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] -.sym 17994 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 17995 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 17996 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 17997 i_button$SB_IO_IN -.sym 17998 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 17999 io_ctrl_ins.o_pmod[7] -.sym 18001 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 18002 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 18003 w_ioc[1] -.sym 18007 i_button_SB_LUT4_I1_I0[2] -.sym 18008 i_button_SB_LUT4_I1_O[0] -.sym 18009 w_ioc[2] -.sym 18010 i_config[3]$SB_IO_IN -.sym 18011 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 18013 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 18015 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 18017 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 18018 i_button_SB_LUT4_I1_O[1] -.sym 18022 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] -.sym 18024 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 18029 i_button_SB_LUT4_I1_O[1] -.sym 18030 i_button_SB_LUT4_I1_O[0] -.sym 18035 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 18036 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 18040 w_ioc[1] -.sym 18041 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 18042 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 18045 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 18046 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 18048 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 18051 w_ioc[2] -.sym 18052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 18053 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 18054 w_ioc[1] -.sym 18057 i_button$SB_IO_IN -.sym 18058 i_button_SB_LUT4_I1_I0[2] -.sym 18059 io_ctrl_ins.o_pmod[7] -.sym 18060 i_button_SB_LUT4_I1_I0[0] -.sym 18063 i_button_SB_LUT4_I1_I0[0] -.sym 18064 i_config[3]$SB_IO_IN -.sym 18065 i_button_SB_LUT4_I1_I0[2] -.sym 18066 io_ctrl_ins.o_pmod[6] -.sym 18067 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 17947 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 17948 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 17949 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] +.sym 17950 o_led1_SB_DFFER_Q_E +.sym 17951 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 17952 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 17953 w_tx_data_io[2] +.sym 17954 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] +.sym 17959 spi_if_ins.w_rx_data[3] +.sym 17960 w_rx_data[5] +.sym 17964 w_rx_data[4] +.sym 17966 w_ioc[1] +.sym 17970 w_rx_data[3] +.sym 17971 o_tr_vc1_b$SB_IO_OUT +.sym 17972 w_fetch +.sym 17973 o_tr_vc2$SB_IO_OUT +.sym 17976 w_rx_data[0] +.sym 17977 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 17979 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 17980 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 17981 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 17982 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17988 w_cs[0] +.sym 17990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 17993 w_cs[1] +.sym 17994 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 17995 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 17996 w_ioc[1] +.sym 17997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 18001 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18002 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 18003 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18008 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 18010 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 18012 w_load +.sym 18013 w_fetch +.sym 18016 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 18021 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 18027 w_ioc[1] +.sym 18029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18030 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18045 w_cs[0] +.sym 18047 w_fetch +.sym 18048 w_load +.sym 18051 w_ioc[1] +.sym 18052 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18053 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 18054 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18058 w_ioc[1] +.sym 18059 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18063 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 18064 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18065 w_cs[1] +.sym 18066 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 18067 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .sym 18068 r_counter_$glb_clk -.sym 18069 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 18070 io_ctrl_ins.pmod_dir_state[7] -.sym 18071 io_ctrl_ins.pmod_dir_state[4] -.sym 18072 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18073 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] -.sym 18074 i_button_SB_LUT4_I1_O[0] -.sym 18075 io_ctrl_ins.pmod_dir_state[3] -.sym 18076 io_ctrl_ins.pmod_dir_state[6] -.sym 18077 io_ctrl_ins.pmod_dir_state[5] -.sym 18093 i_button_SB_LUT4_I1_I0[0] -.sym 18096 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18097 i_button_SB_LUT4_I1_I0[2] -.sym 18101 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E -.sym 18102 w_rx_data[5] -.sym 18111 w_rx_data[6] -.sym 18112 w_rx_data[5] -.sym 18113 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 18114 i_button_SB_LUT4_I1_I0[2] -.sym 18117 i_button_SB_LUT4_I1_I0[0] -.sym 18120 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18121 w_rx_data[7] -.sym 18122 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 18126 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 18127 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 18128 i_button_SB_LUT4_I1_I0[3] -.sym 18129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18130 w_rx_data[3] -.sym 18133 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18136 i_button_SB_LUT4_I1_I0[1] -.sym 18137 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18141 io_ctrl_ins.pmod_dir_state[6] -.sym 18144 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 18145 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18146 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18147 io_ctrl_ins.pmod_dir_state[6] -.sym 18150 w_rx_data[5] -.sym 18158 w_rx_data[6] -.sym 18164 w_rx_data[7] -.sym 18168 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18170 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 18174 i_button_SB_LUT4_I1_I0[2] -.sym 18175 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18177 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 18181 w_rx_data[3] -.sym 18186 i_button_SB_LUT4_I1_I0[3] -.sym 18187 i_button_SB_LUT4_I1_I0[0] -.sym 18188 i_button_SB_LUT4_I1_I0[2] -.sym 18189 i_button_SB_LUT4_I1_I0[1] -.sym 18190 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 18069 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 18070 w_tx_data_io[1] +.sym 18071 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] +.sym 18072 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 18073 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 18074 w_tx_data_io[0] +.sym 18075 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 18076 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 18077 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 18078 io_pmod[0]$SB_IO_IN +.sym 18090 o_shdn_rx_lna$SB_IO_OUT +.sym 18094 io_pmod[1]$SB_IO_IN +.sym 18097 w_rx_data[2] +.sym 18099 w_rx_data[1] +.sym 18102 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 18104 io_pmod[2]$SB_IO_IN +.sym 18105 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18112 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18114 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18115 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 18117 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 18120 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 18123 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 18126 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18127 w_ioc[1] +.sym 18130 i_config[1]$SB_IO_IN +.sym 18133 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18137 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18139 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18141 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 18146 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 18156 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18157 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18159 i_config[1]$SB_IO_IN +.sym 18163 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 18165 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18168 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18170 w_ioc[1] +.sym 18174 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18175 w_ioc[1] +.sym 18176 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18177 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18180 w_ioc[1] +.sym 18181 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18182 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18186 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18187 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.sym 18188 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18189 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 18191 r_counter_$glb_clk -.sym 18196 io_ctrl_ins.o_data_out[4] -.sym 18197 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 18198 io_ctrl_ins.o_data_out[3] -.sym 18200 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18201 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 18209 w_rx_data[6] -.sym 18215 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 18216 w_rx_data[5] -.sym 18219 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18220 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18223 o_rx_h_tx_l$SB_IO_OUT -.sym 18227 o_tr_vc1$SB_IO_OUT -.sym 18236 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 18239 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] -.sym 18240 i_button_SB_LUT4_I1_I0[2] -.sym 18244 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18245 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] -.sym 18246 w_ioc[2] -.sym 18250 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 18252 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] -.sym 18256 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18261 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 18263 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R -.sym 18265 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 18274 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 18276 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 18281 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 18291 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] -.sym 18292 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18293 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] -.sym 18294 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] -.sym 18297 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 18298 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18300 i_button_SB_LUT4_I1_I0[2] -.sym 18309 w_ioc[2] -.sym 18312 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 18313 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E +.sym 18193 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] +.sym 18194 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] +.sym 18195 io_ctrl_ins.pmod_dir_state[3] +.sym 18196 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 18197 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 18198 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 18199 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18200 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] +.sym 18205 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 18206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18214 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18220 i_button_SB_LUT4_I0_O[1] +.sym 18226 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 18234 w_rx_data[6] +.sym 18237 i_button_SB_LUT4_I0_O[1] +.sym 18239 w_rx_data[7] +.sym 18242 w_ioc[1] +.sym 18243 o_tr_vc1_b$SB_IO_OUT +.sym 18245 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18246 w_rx_data[4] +.sym 18247 w_cs[1] +.sym 18248 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18249 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18250 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 18251 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18253 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18259 w_rx_data[1] +.sym 18265 io_ctrl_ins.pmod_dir_state[4] +.sym 18267 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 18268 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18269 w_cs[1] +.sym 18270 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 18273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18274 io_ctrl_ins.pmod_dir_state[4] +.sym 18275 i_button_SB_LUT4_I0_O[1] +.sym 18276 o_tr_vc1_b$SB_IO_OUT +.sym 18282 w_rx_data[7] +.sym 18285 w_ioc[1] +.sym 18286 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18287 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 18288 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18291 w_rx_data[1] +.sym 18297 w_ioc[1] +.sym 18298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 18300 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18303 w_rx_data[6] +.sym 18311 w_rx_data[4] +.sym 18313 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 18314 r_counter_$glb_clk -.sym 18315 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R -.sym 18316 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 18317 o_rx_h_tx_l$SB_IO_OUT -.sym 18318 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18319 o_tr_vc1$SB_IO_OUT -.sym 18320 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 18321 o_tr_vc1_b$SB_IO_OUT -.sym 18322 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 18323 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18332 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 18335 w_rx_09_fifo_push -.sym 18336 w_tx_data_io_SB_DFFESS_Q_E -.sym 18339 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 18340 i_rst_b$SB_IO_IN -.sym 18349 w_ioc[2] -.sym 18359 w_rx_data[1] -.sym 18369 w_rx_data[7] -.sym 18373 w_rx_data[6] -.sym 18374 w_rx_data[5] -.sym 18379 w_rx_data[0] -.sym 18381 w_rx_data[2] -.sym 18383 w_rx_data[3] -.sym 18384 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E -.sym 18387 w_rx_data[4] -.sym 18390 w_rx_data[6] -.sym 18398 w_rx_data[2] -.sym 18403 w_rx_data[7] -.sym 18409 w_rx_data[0] -.sym 18415 w_rx_data[4] -.sym 18421 w_rx_data[1] -.sym 18429 w_rx_data[5] -.sym 18434 w_rx_data[3] -.sym 18436 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 18317 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] +.sym 18321 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] +.sym 18322 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18328 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 18332 w_load +.sym 18345 i_config[2]$SB_IO_IN +.sym 18349 i_config[1]$SB_IO_IN +.sym 18359 io_ctrl_ins.pmod_dir_state[7] +.sym 18360 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18361 i_config[2]$SB_IO_IN +.sym 18362 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18363 io_ctrl_ins.pmod_dir_state[6] +.sym 18368 o_rx_h_tx_l$SB_IO_OUT +.sym 18369 io_ctrl_ins.pmod_dir_state[5] +.sym 18370 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18372 o_tr_vc1$SB_IO_OUT +.sym 18373 i_config[3]$SB_IO_IN +.sym 18374 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 18375 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 18377 i_button$SB_IO_IN +.sym 18380 i_button_SB_LUT4_I0_O[1] +.sym 18383 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18384 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 18387 i_button_SB_LUT4_I0_O[2] +.sym 18390 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 18391 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18393 i_button_SB_LUT4_I0_O[1] +.sym 18396 io_ctrl_ins.pmod_dir_state[5] +.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18398 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18399 i_config[2]$SB_IO_IN +.sym 18402 io_ctrl_ins.pmod_dir_state[6] +.sym 18403 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18404 i_config[3]$SB_IO_IN +.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18420 i_button_SB_LUT4_I0_O[1] +.sym 18421 o_tr_vc1$SB_IO_OUT +.sym 18422 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 18426 i_button$SB_IO_IN +.sym 18427 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 18428 io_ctrl_ins.pmod_dir_state[7] +.sym 18429 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 18432 i_button_SB_LUT4_I0_O[1] +.sym 18434 i_button_SB_LUT4_I0_O[2] +.sym 18435 o_rx_h_tx_l$SB_IO_OUT +.sym 18436 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E .sym 18437 r_counter_$glb_clk -.sym 18456 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18463 i_button_SB_LUT4_I1_I0[1] -.sym 18467 i_config[1]$SB_IO_IN -.sym 18469 o_tr_vc2$SB_IO_OUT -.sym 18491 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 18493 io_ctrl_ins.rf_pin_state[1] -.sym 18495 io_ctrl_ins.rf_pin_state[3] -.sym 18496 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 18497 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 18499 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 18500 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 18534 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 18550 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 18551 io_ctrl_ins.rf_pin_state[1] -.sym 18552 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 18555 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 18556 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 18557 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 18558 io_ctrl_ins.rf_pin_state[3] -.sym 18559 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 18451 w_rx_data[0] +.sym 18452 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18456 o_rx_h_tx_l$SB_IO_OUT +.sym 18460 o_tr_vc1$SB_IO_OUT +.sym 18469 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18482 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18506 w_rx_data[5] +.sym 18538 w_rx_data[5] +.sym 18559 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 18560 r_counter_$glb_clk .sym 18562 i_config[1]$SB_IO_IN -.sym 18564 i_button_SB_LUT4_I1_I0[1] -.sym 18633 o_led0$SB_IO_OUT +.sym 18564 i_config[2]$SB_IO_IN .sym 18636 w_smi_data_output[4] .sym 18638 o_led0$SB_IO_OUT .sym 18642 $PACKER_VCC_NET -.sym 18655 $PACKER_VCC_NET -.sym 18656 w_smi_data_output[4] -.sym 18659 o_led0$SB_IO_OUT -.sym 18679 $PACKER_VCC_NET -.sym 18696 w_smi_data_output[5] -.sym 18703 i_smi_soe_se$SB_IO_IN -.sym 18704 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 18705 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 18707 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 18708 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 18709 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 18710 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 18713 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 18715 i_rst_b$SB_IO_IN -.sym 18727 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 18736 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 18743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 18744 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 18749 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 18756 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 18762 i_smi_soe_se$SB_IO_IN -.sym 18763 i_rst_b$SB_IO_IN -.sym 18768 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 18774 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 18780 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 18782 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 18783 r_counter_$glb_clk -.sym 18784 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 18645 w_smi_data_output[4] +.sym 18648 o_led0$SB_IO_OUT +.sym 18658 $PACKER_VCC_NET +.sym 18687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18691 tx_fifo.wr_addr[1] +.sym 18694 o_miso_$_TBUF__Y_E +.sym 18696 o_led0$SB_IO_OUT +.sym 18703 tx_fifo.wr_addr_gray[0] +.sym 18710 tx_fifo.wr_addr_gray[6] +.sym 18744 tx_fifo.wr_addr_gray[6] +.sym 18779 tx_fifo.wr_addr_gray[0] +.sym 18783 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18805 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 18812 smi_ctrl_ins.swe_and_reset -.sym 18825 $PACKER_VCC_NET -.sym 18831 smi_ctrl_ins.soe_and_reset -.sym 18845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 18850 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 18854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 18855 rx_fifo.wr_addr[8] -.sym 18866 tx_fifo.wr_addr[6] -.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 18869 tx_fifo.wr_addr[8] -.sym 18872 tx_fifo.wr_addr[3] -.sym 18873 tx_fifo.wr_addr[7] -.sym 18876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 18879 tx_fifo.wr_addr[2] -.sym 18880 tx_fifo.wr_addr[4] -.sym 18892 tx_fifo.wr_addr[5] -.sym 18898 $nextpnr_ICESTORM_LC_8$O -.sym 18900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 18904 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 18906 tx_fifo.wr_addr[2] -.sym 18908 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 18910 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 18913 tx_fifo.wr_addr[3] -.sym 18914 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 18916 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 18919 tx_fifo.wr_addr[4] -.sym 18920 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 18922 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 18924 tx_fifo.wr_addr[5] -.sym 18926 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 18928 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 18930 tx_fifo.wr_addr[6] -.sym 18932 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 18934 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 18936 tx_fifo.wr_addr[7] -.sym 18938 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 18940 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 18943 tx_fifo.wr_addr[8] -.sym 18944 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 18949 w_rx_fifo_pulled_data[28] -.sym 18953 w_rx_fifo_pulled_data[30] -.sym 18973 rx_fifo.wr_addr[3] -.sym 18975 w_rx_fifo_pulled_data[30] -.sym 18976 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 18977 rx_fifo.wr_addr[6] -.sym 18978 w_rx_fifo_pulled_data[29] -.sym 18979 $PACKER_VCC_NET -.sym 18981 $PACKER_VCC_NET -.sym 18982 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 18984 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] -.sym 18992 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 18993 tx_fifo.rd_addr_gray_wr_r[8] -.sym 18994 tx_fifo.rd_addr_gray_wr_r[6] -.sym 18995 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] -.sym 18997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] -.sym 18998 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 19000 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 19001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 19002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 19004 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 19005 tx_fifo.rd_addr_gray_wr_r[4] -.sym 19006 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 19009 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.sym 19013 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 19014 tx_fifo.wr_addr[9] -.sym 19015 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 19017 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.sym 19019 tx_fifo.rd_addr_gray_wr_r[9] -.sym 19020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 19024 tx_fifo.wr_addr[9] -.sym 19025 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 19028 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 19029 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] -.sym 19030 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.sym 19031 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.sym 19035 tx_fifo.rd_addr_gray_wr_r[6] -.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 19040 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 19042 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 19047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 19048 tx_fifo.rd_addr_gray_wr_r[4] -.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 19053 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 19055 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 19058 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19059 tx_fifo.rd_addr_gray_wr_r[9] -.sym 19060 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] -.sym 19064 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 19065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] -.sym 19066 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 19069 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 18815 $PACKER_VCC_NET +.sym 18846 rx_fifo.wr_addr[4] +.sym 18847 w_smi_data_output[5] +.sym 18853 tx_fifo.wr_addr[1] +.sym 18854 rx_fifo.wr_addr[6] +.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 18868 tx_fifo.wr_addr[1] +.sym 18871 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 18872 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18877 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18878 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 18881 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 18893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18899 tx_fifo.wr_addr[1] +.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 18907 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 18911 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 18930 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18938 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 18942 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 18944 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18946 r_counter_$glb_clk +.sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 18949 w_rx_fifo_pulled_data[20] +.sym 18953 w_rx_fifo_pulled_data[22] +.sym 18962 tx_fifo.wr_addr[3] +.sym 18966 tx_fifo.wr_addr[6] +.sym 18968 tx_fifo.wr_addr[7] +.sym 18970 tx_fifo.wr_addr[4] +.sym 18978 rx_fifo.rd_addr[6] +.sym 18979 rx_fifo.rd_addr[2] +.sym 18980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18982 rx_fifo.rd_addr[9] +.sym 18983 $PACKER_VCC_NET +.sym 18989 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18995 tx_fifo.wr_addr[0] +.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 19008 i_rst_b$SB_IO_IN +.sym 19011 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19012 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 19015 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 19016 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19017 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 19018 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 19019 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 19025 i_rst_b$SB_IO_IN +.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 19029 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19030 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 19042 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 19048 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 19055 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 19058 tx_fifo.wr_addr[0] +.sym 19064 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 19067 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 19069 r_counter_$glb_clk .sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19072 w_rx_fifo_pulled_data[29] -.sym 19076 w_rx_fifo_pulled_data[31] -.sym 19082 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 19086 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19088 w_rx_fifo_data[30] -.sym 19090 tx_fifo.rd_addr_gray_wr_r[6] -.sym 19092 w_rx_fifo_pulled_data[28] -.sym 19093 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 19096 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 19098 smi_ctrl_ins.r_fifo_push -.sym 19101 w_rx_fifo_push -.sym 19102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 19103 $PACKER_VCC_NET -.sym 19106 w_rx_fifo_data[28] -.sym 19112 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 19114 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 19116 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 19118 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 19120 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 19122 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 19124 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 19125 o_led0$SB_IO_OUT -.sym 19126 w_tx_fifo_full -.sym 19131 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 19136 w_rx_fifo_empty -.sym 19137 tx_fifo.rd_addr_gray_wr_r[2] -.sym 19142 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 19159 tx_fifo.rd_addr_gray_wr_r[2] -.sym 19160 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 19165 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 19166 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 19170 w_rx_fifo_empty -.sym 19171 o_led0$SB_IO_OUT -.sym 19172 w_tx_fifo_full -.sym 19176 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 19181 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 19182 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 19184 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 19191 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 19072 w_rx_fifo_pulled_data[21] +.sym 19076 w_rx_fifo_pulled_data[23] +.sym 19081 o_led1_SB_DFFER_Q_E +.sym 19095 rx_fifo.wr_addr[5] +.sym 19096 tx_fifo.wr_addr[1] +.sym 19098 rx_fifo.wr_addr[4] +.sym 19100 rx_fifo.wr_addr[7] +.sym 19102 rx_fifo.wr_addr[6] +.sym 19104 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 19105 o_led1$SB_IO_OUT +.sym 19117 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 19119 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 19122 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 19125 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 19127 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19136 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 19137 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 19141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 19147 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 19148 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 19151 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 19152 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19153 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 19154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 19157 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 19165 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 19169 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 19170 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 19175 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 19189 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 19191 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 19192 r_counter_$glb_clk .sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19195 w_rx_fifo_pulled_data[20] -.sym 19199 w_rx_fifo_pulled_data[22] -.sym 19207 w_rx_fifo_data[31] -.sym 19211 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 19212 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 19216 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 19220 w_rx_fifo_data[21] -.sym 19222 w_rx_fifo_empty -.sym 19223 o_smi_read_req$SB_IO_OUT -.sym 19228 $PACKER_VCC_NET -.sym 19236 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 19237 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 19239 smi_ctrl_ins.int_cnt_rx[4] -.sym 19240 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 19241 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 19243 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 19247 i_rst_b$SB_IO_IN -.sym 19249 tx_fifo.wr_addr[0] -.sym 19251 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 19255 tx_fifo.rd_addr_gray_wr_r[0] -.sym 19257 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 19265 smi_ctrl_ins.int_cnt_rx[3] -.sym 19274 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 19276 i_rst_b$SB_IO_IN -.sym 19280 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 19293 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 19300 tx_fifo.wr_addr[0] -.sym 19301 tx_fifo.rd_addr_gray_wr_r[0] -.sym 19304 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 19305 smi_ctrl_ins.int_cnt_rx[3] -.sym 19306 smi_ctrl_ins.int_cnt_rx[4] -.sym 19307 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 19313 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 19314 lvds_tx_inst.r_pulled_SB_LUT4_I2_O +.sym 19195 w_rx_fifo_pulled_data[4] +.sym 19199 w_rx_fifo_pulled_data[6] +.sym 19206 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 19207 rx_fifo.rd_addr[4] +.sym 19208 rx_fifo.mem_i.0.1_WDATA_1 +.sym 19209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 19210 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 19214 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 19215 w_rx_fifo_pulled_data[21] +.sym 19216 rx_fifo.rd_addr[8] +.sym 19219 rx_fifo.wr_addr[0] +.sym 19221 o_led1$SB_IO_OUT +.sym 19222 rx_fifo.mem_i.0.1_WDATA +.sym 19223 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 19227 rx_fifo.wr_addr[1] +.sym 19228 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 19235 tx_fifo.wr_addr_gray[8] +.sym 19238 tx_fifo.wr_addr_gray[1] +.sym 19239 tx_fifo.wr_addr_gray[7] +.sym 19245 tx_fifo.wr_addr_gray[2] +.sym 19248 tx_fifo.wr_addr_gray[3] +.sym 19250 tx_fifo.wr_addr_gray[5] +.sym 19271 tx_fifo.wr_addr_gray[1] +.sym 19275 tx_fifo.wr_addr_gray[3] +.sym 19281 tx_fifo.wr_addr_gray[2] +.sym 19287 tx_fifo.wr_addr_gray[8] +.sym 19306 tx_fifo.wr_addr_gray[5] +.sym 19313 tx_fifo.wr_addr_gray[7] .sym 19315 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 19316 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19318 w_rx_fifo_pulled_data[21] -.sym 19322 w_rx_fifo_pulled_data[23] -.sym 19329 w_rx_fifo_data[20] -.sym 19333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 19337 w_rx_fifo_data[22] -.sym 19342 smi_ctrl_ins.r_fifo_pull_1 -.sym 19344 spi_if_ins.w_rx_data[5] -.sym 19346 rx_fifo.wr_addr[7] -.sym 19347 rx_fifo.wr_addr[8] -.sym 19352 spi_if_ins.w_rx_data[6] -.sym 19360 w_rx_fifo_pulled_data[28] -.sym 19367 w_rx_fifo_pulled_data[20] -.sym 19369 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 19375 w_rx_fifo_pulled_data[21] -.sym 19383 w_rx_fifo_pulled_data[24] -.sym 19412 w_rx_fifo_pulled_data[24] -.sym 19415 w_rx_fifo_pulled_data[28] -.sym 19429 w_rx_fifo_pulled_data[20] -.sym 19435 w_rx_fifo_pulled_data[21] -.sym 19437 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 19438 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19439 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19441 w_rx_fifo_pulled_data[24] -.sym 19445 w_rx_fifo_pulled_data[26] -.sym 19452 $PACKER_VCC_NET -.sym 19453 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 19454 spi_if_ins.w_rx_data[2] -.sym 19456 spi_if_ins.w_rx_data[4] -.sym 19457 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 19458 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 19460 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 19461 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 19463 rx_fifo.rd_addr[3] -.sym 19465 rx_fifo.wr_addr[3] -.sym 19466 $PACKER_VCC_NET -.sym 19467 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 19468 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19472 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 19474 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19475 rx_fifo.wr_addr[4] -.sym 19494 smi_ctrl_ins.r_fifo_pull -.sym 19496 w_ioc[1] -.sym 19497 w_ioc[2] -.sym 19509 w_ioc[3] -.sym 19511 w_ioc[4] -.sym 19538 w_ioc[1] -.sym 19539 w_ioc[4] -.sym 19540 w_ioc[2] -.sym 19541 w_ioc[3] -.sym 19550 smi_ctrl_ins.r_fifo_pull +.sym 19318 w_rx_fifo_pulled_data[5] +.sym 19322 w_rx_fifo_pulled_data[7] +.sym 19325 tx_fifo.wr_addr[1] +.sym 19330 rx_fifo.wr_addr[8] +.sym 19333 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 19344 rx_fifo.rd_addr[0] +.sym 19346 rx_fifo.wr_addr[6] +.sym 19351 rx_fifo.rd_addr[6] +.sym 19361 tx_fifo.rd_addr_gray_wr[5] +.sym 19365 tx_fifo.rd_addr_gray[0] +.sym 19394 tx_fifo.rd_addr_gray_wr[5] +.sym 19421 tx_fifo.rd_addr_gray[0] +.sym 19438 r_counter_$glb_clk +.sym 19441 w_rx_fifo_pulled_data[28] +.sym 19445 w_rx_fifo_pulled_data[30] +.sym 19454 tx_fifo.rd_addr_gray_wr[0] +.sym 19459 rx_fifo.rd_addr[1] +.sym 19460 rx_fifo.rd_addr[7] +.sym 19461 rx_fifo.rd_addr[0] +.sym 19464 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19465 rx_fifo.mem_i.0.3_WDATA +.sym 19466 rx_fifo.rd_addr[9] +.sym 19467 rx_fifo.mem_q.0.1_WDATA +.sym 19470 $PACKER_VCC_NET +.sym 19472 rx_fifo.mem_q.0.1_WDATA_1 +.sym 19474 rx_fifo.rd_addr[2] +.sym 19475 rx_fifo.mem_i.0.3_WDATA_1 +.sym 19498 spi_if_ins.spi.r3_rx_done +.sym 19506 spi_if_ins.spi.r2_rx_done +.sym 19510 tx_fifo.rd_addr_gray[5] +.sym 19521 spi_if_ins.spi.r2_rx_done +.sym 19533 tx_fifo.rd_addr_gray[5] +.sym 19538 spi_if_ins.spi.r2_rx_done +.sym 19539 spi_if_ins.spi.r3_rx_done .sym 19561 r_counter_$glb_clk -.sym 19562 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19564 w_rx_fifo_pulled_data[25] -.sym 19568 w_rx_fifo_pulled_data[27] -.sym 19578 w_rx_fifo_data[24] -.sym 19584 w_ioc[1] -.sym 19590 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 19592 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 19594 $PACKER_VCC_NET -.sym 19595 w_rx_fifo_data[26] -.sym 19608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19610 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] -.sym 19613 i_rst_b$SB_IO_IN -.sym 19624 spi_if_ins.state_if[0] -.sym 19626 spi_if_ins.state_if[1] -.sym 19627 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19628 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 19629 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 19631 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 19632 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 19634 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 19644 spi_if_ins.state_if[1] -.sym 19645 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 19646 spi_if_ins.state_if[0] -.sym 19649 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 19650 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 19651 i_rst_b$SB_IO_IN -.sym 19652 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 19661 i_rst_b$SB_IO_IN -.sym 19662 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19663 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] -.sym 19664 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 19675 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 19680 spi_if_ins.state_if[0] -.sym 19682 spi_if_ins.state_if[1] -.sym 19683 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 19564 w_rx_fifo_pulled_data[29] +.sym 19568 w_rx_fifo_pulled_data[31] +.sym 19583 rx_fifo.wr_addr[4] +.sym 19588 rx_fifo.rd_addr[3] +.sym 19589 o_led1$SB_IO_OUT +.sym 19592 rx_fifo.wr_addr[7] +.sym 19593 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 19615 i_sck$SB_IO_IN +.sym 19673 i_sck$SB_IO_IN .sym 19684 r_counter_$glb_clk -.sym 19685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19707 w_rx_fifo_pull -.sym 19708 w_rx_fifo_data[25] -.sym 19712 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 19714 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19719 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 19720 $PACKER_VCC_NET -.sym 19721 w_rx_fifo_push -.sym 19729 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 19736 $PACKER_VCC_NET -.sym 19739 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19740 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 19744 $PACKER_VCC_NET -.sym 19745 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19749 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19754 i_rst_b$SB_IO_IN -.sym 19756 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 19759 $nextpnr_ICESTORM_LC_6$O -.sym 19762 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19765 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 19767 $PACKER_VCC_NET -.sym 19768 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19773 $PACKER_VCC_NET -.sym 19774 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19775 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 19785 $PACKER_VCC_NET -.sym 19786 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19787 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19792 $PACKER_VCC_NET -.sym 19796 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19803 i_rst_b$SB_IO_IN -.sym 19805 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 19806 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 19699 rx_fifo.rd_addr[6] +.sym 19705 rx_fifo.rd_addr[8] +.sym 19710 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19715 rx_fifo.wr_addr[0] +.sym 19717 o_led1$SB_IO_OUT +.sym 19736 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19741 spi_if_ins.spi.SCKr[0] +.sym 19757 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19761 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19784 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19799 spi_if_ins.spi.SCKr[0] .sym 19807 r_counter_$glb_clk -.sym 19808 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 19821 i_glob_clock$SB_IO_IN -.sym 19823 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 19825 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 19830 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 19831 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19834 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19835 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 19838 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 19842 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 19850 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] -.sym 19851 sys_ctrl_ins.tx_sample_gap[3] -.sym 19852 w_ioc[2] -.sym 19857 sys_ctrl_ins.tx_sample_gap[0] -.sym 19858 w_ioc[3] -.sym 19859 w_ioc[4] -.sym 19860 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19861 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 19862 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19864 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19872 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 19877 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 19878 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 19884 sys_ctrl_ins.tx_sample_gap[0] -.sym 19886 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 19895 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 19896 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19897 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] -.sym 19898 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19914 w_ioc[4] -.sym 19915 w_ioc[3] -.sym 19916 w_ioc[2] -.sym 19920 sys_ctrl_ins.tx_sample_gap[3] -.sym 19922 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 19925 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19928 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 19929 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 19821 spi_if_ins.w_rx_data[4] +.sym 19825 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 19833 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 19854 w_rx_data[0] +.sym 19862 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19868 o_led1_SB_DFFER_Q_E +.sym 19871 i_rst_b$SB_IO_IN +.sym 19881 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 19892 w_rx_data[0] +.sym 19896 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19897 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 19898 i_rst_b$SB_IO_IN +.sym 19929 o_led1_SB_DFFER_Q_E .sym 19930 r_counter_$glb_clk .sym 19931 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19952 io_ctrl_ins.o_data_out[4] -.sym 19957 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 19973 spi_if_ins.spi.r_tx_byte[0] -.sym 19975 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 19976 sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] -.sym 19977 spi_if_ins.spi.r_tx_byte[7] -.sym 19979 spi_if_ins.spi.r_tx_byte[5] -.sym 19981 spi_if_ins.spi.r_tx_byte[1] -.sym 19983 spi_if_ins.spi.r_tx_byte[4] -.sym 19984 sys_ctrl_ins.tx_sample_gap[1] -.sym 19985 sys_ctrl_ins.tx_sample_gap[2] -.sym 19986 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 19987 spi_if_ins.spi.r_tx_byte[3] -.sym 19994 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19997 w_fetch -.sym 19998 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 20002 w_cs[0] -.sym 20007 spi_if_ins.spi.r_tx_bit_count[2] -.sym 20008 spi_if_ins.spi.r_tx_byte[7] -.sym 20009 spi_if_ins.spi.r_tx_byte[3] -.sym 20013 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 20015 sys_ctrl_ins.tx_sample_gap[1] -.sym 20024 sys_ctrl_ins.tx_sample_gap[2] -.sym 20025 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 20031 sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] -.sym 20032 w_cs[0] -.sym 20033 w_fetch -.sym 20036 spi_if_ins.spi.r_tx_bit_count[2] -.sym 20037 spi_if_ins.spi.r_tx_byte[0] -.sym 20038 spi_if_ins.spi.r_tx_byte[4] -.sym 20039 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 20048 spi_if_ins.spi.r_tx_bit_count[2] -.sym 20049 spi_if_ins.spi.r_tx_byte[5] -.sym 20050 spi_if_ins.spi.r_tx_byte[1] -.sym 20051 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 20052 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 19950 w_rx_data[0] +.sym 19960 spi_if_ins.w_rx_data[1] +.sym 19964 spi_if_ins.w_rx_data[2] +.sym 19967 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 19975 spi_if_ins.w_rx_data[2] +.sym 19976 w_ioc[4] +.sym 19977 w_ioc[3] +.sym 19978 spi_if_ins.w_rx_data[3] +.sym 19984 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 19986 spi_if_ins.w_rx_data[1] +.sym 19995 spi_if_ins.w_rx_data[4] +.sym 20004 w_ioc[2] +.sym 20006 spi_if_ins.w_rx_data[1] +.sym 20025 spi_if_ins.w_rx_data[4] +.sym 20031 spi_if_ins.w_rx_data[3] +.sym 20036 w_ioc[4] +.sym 20037 w_ioc[2] +.sym 20039 w_ioc[3] +.sym 20042 w_ioc[2] +.sym 20044 w_ioc[3] +.sym 20045 w_ioc[4] +.sym 20051 spi_if_ins.w_rx_data[2] +.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 20053 r_counter_$glb_clk -.sym 20054 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 20067 spi_if_ins.spi.r_tx_byte[1] -.sym 20069 sys_ctrl_ins.tx_sample_gap[0] -.sym 20071 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 20072 sys_ctrl_ins.tx_sample_gap[1] -.sym 20073 sys_ctrl_ins.tx_sample_gap[3] -.sym 20075 spi_if_ins.spi.r_tx_byte[3] -.sym 20076 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 20077 spi_if_ins.spi.r_tx_byte[0] -.sym 20078 w_rx_data[5] -.sym 20084 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20085 w_rx_fifo_full -.sym 20099 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] -.sym 20108 i_button_SB_LUT4_I1_I0[0] -.sym 20114 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20116 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 20117 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 20118 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 20127 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] -.sym 20147 i_button_SB_LUT4_I1_I0[0] -.sym 20148 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 20149 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 20159 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] -.sym 20160 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] -.sym 20175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 20068 io_pmod[1]$SB_IO_IN +.sym 20069 w_rx_data[1] +.sym 20070 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 20072 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 20074 io_pmod[2]$SB_IO_IN +.sym 20075 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 20077 w_rx_data[2] +.sym 20079 io_pmod[3]$SB_IO_IN +.sym 20096 w_ioc[1] +.sym 20097 w_fetch +.sym 20098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 20099 o_shdn_rx_lna$SB_IO_OUT +.sym 20100 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 20101 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 20103 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20104 w_load +.sym 20105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20106 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 20107 io_pmod[0]$SB_IO_IN +.sym 20109 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 20110 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20116 io_pmod[1]$SB_IO_IN +.sym 20118 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20119 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20123 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20125 w_cs[2] +.sym 20127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20129 w_cs[2] +.sym 20130 w_fetch +.sym 20131 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20132 w_load +.sym 20136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 20138 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20141 io_pmod[0]$SB_IO_IN +.sym 20142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20147 w_fetch +.sym 20148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20149 w_load +.sym 20150 w_cs[2] +.sym 20153 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 20154 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20159 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20160 w_ioc[1] +.sym 20161 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 20167 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20168 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 20171 o_shdn_rx_lna$SB_IO_OUT +.sym 20172 io_pmod[1]$SB_IO_IN +.sym 20173 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20174 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E .sym 20176 r_counter_$glb_clk -.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 20206 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 20220 w_rx_data[7] -.sym 20222 w_rx_data[3] -.sym 20223 w_rx_data[5] -.sym 20226 w_rx_data[4] -.sym 20227 io_ctrl_ins.pmod_dir_state[7] -.sym 20230 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.sym 20231 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 20234 w_rx_data[6] -.sym 20237 o_rx_h_tx_l$SB_IO_OUT -.sym 20241 o_tr_vc1$SB_IO_OUT -.sym 20242 io_ctrl_ins.pmod_dir_state[5] -.sym 20244 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20245 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 20250 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 20253 w_rx_data[7] -.sym 20258 w_rx_data[4] -.sym 20265 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 20266 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20270 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 20271 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 20272 io_ctrl_ins.pmod_dir_state[5] -.sym 20273 o_tr_vc1$SB_IO_OUT -.sym 20276 o_rx_h_tx_l$SB_IO_OUT -.sym 20277 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 20278 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 20279 io_ctrl_ins.pmod_dir_state[7] -.sym 20282 w_rx_data[3] -.sym 20288 w_rx_data[6] -.sym 20295 w_rx_data[5] -.sym 20298 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 20192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 20194 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20198 o_led0$SB_IO_OUT +.sym 20200 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20202 w_rx_data[3] +.sym 20203 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20208 w_rx_data[1] +.sym 20209 o_led1$SB_IO_OUT +.sym 20210 w_cs[1] +.sym 20211 w_cs[2] +.sym 20219 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 20220 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] +.sym 20221 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 20222 i_button_SB_LUT4_I0_O[1] +.sym 20223 w_fetch +.sym 20224 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 20226 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20227 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] +.sym 20228 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] +.sym 20229 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] +.sym 20230 o_shdn_tx_lna$SB_IO_OUT +.sym 20231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 20232 io_ctrl_ins.mixer_en_state +.sym 20233 o_tr_vc2$SB_IO_OUT +.sym 20234 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] +.sym 20236 w_cs[1] +.sym 20237 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20238 io_pmod[2]$SB_IO_IN +.sym 20239 io_pmod[3]$SB_IO_IN +.sym 20240 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20241 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20243 w_load +.sym 20244 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20245 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 20248 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20249 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 20250 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 20252 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] +.sym 20253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] +.sym 20254 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 20259 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 20260 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] +.sym 20261 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20264 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 20265 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 20267 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20270 w_load +.sym 20271 w_fetch +.sym 20272 w_cs[1] +.sym 20273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20276 io_ctrl_ins.mixer_en_state +.sym 20277 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] +.sym 20278 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] +.sym 20279 i_button_SB_LUT4_I0_O[1] +.sym 20282 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 20283 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 20284 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 20285 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 20288 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20289 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20290 io_pmod[3]$SB_IO_IN +.sym 20291 o_tr_vc2$SB_IO_OUT +.sym 20294 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20295 o_shdn_tx_lna$SB_IO_OUT +.sym 20296 io_pmod[2]$SB_IO_IN +.sym 20297 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 20298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 20299 r_counter_$glb_clk -.sym 20321 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 20324 w_rx_data[7] -.sym 20342 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 20346 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20347 io_ctrl_ins.pmod_dir_state[3] -.sym 20349 i_button_SB_LUT4_I1_I0[2] -.sym 20350 i_config[1]$SB_IO_IN -.sym 20351 io_ctrl_ins.pmod_dir_state[4] -.sym 20353 w_tx_data_io_SB_DFFESS_Q_E -.sym 20354 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20356 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 20357 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 20358 io_ctrl_ins.o_pmod[4] -.sym 20364 io_ctrl_ins.o_pmod[3] +.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20313 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 20318 o_shdn_tx_lna$SB_IO_OUT +.sym 20320 io_ctrl_ins.mixer_en_state +.sym 20323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 20329 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20342 w_fetch +.sym 20343 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] +.sym 20344 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20346 w_rx_data[0] +.sym 20347 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20349 w_rx_data[2] +.sym 20354 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.sym 20355 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] +.sym 20357 w_load +.sym 20360 io_ctrl_ins.pmod_dir_state[3] +.sym 20362 w_rx_data[3] +.sym 20364 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] .sym 20367 i_config[0]$SB_IO_IN -.sym 20370 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20371 w_tx_data_io_SB_DFFESS_Q_S -.sym 20393 i_button_SB_LUT4_I1_I0[2] -.sym 20394 io_ctrl_ins.o_pmod[4] -.sym 20395 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 20396 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 20399 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 20400 io_ctrl_ins.pmod_dir_state[3] -.sym 20401 i_config[0]$SB_IO_IN -.sym 20402 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20405 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20406 io_ctrl_ins.o_pmod[3] -.sym 20407 i_button_SB_LUT4_I1_I0[2] -.sym 20408 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20417 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 20418 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 20419 i_config[1]$SB_IO_IN -.sym 20420 io_ctrl_ins.pmod_dir_state[4] -.sym 20421 w_tx_data_io_SB_DFFESS_Q_E +.sym 20368 i_rst_b$SB_IO_IN +.sym 20370 w_cs[1] +.sym 20372 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20373 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] +.sym 20375 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20376 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.sym 20377 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] +.sym 20378 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20381 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] +.sym 20382 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20383 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20384 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] +.sym 20389 w_rx_data[3] +.sym 20393 w_cs[1] +.sym 20394 w_fetch +.sym 20395 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20396 w_load +.sym 20402 w_rx_data[2] +.sym 20405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20406 i_config[0]$SB_IO_IN +.sym 20407 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 20408 io_ctrl_ins.pmod_dir_state[3] +.sym 20411 w_load +.sym 20412 i_rst_b$SB_IO_IN +.sym 20413 w_fetch +.sym 20414 w_cs[1] +.sym 20418 w_rx_data[0] +.sym 20421 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 20422 r_counter_$glb_clk -.sym 20423 w_tx_data_io_SB_DFFESS_Q_S -.sym 20445 o_tr_vc2$SB_IO_OUT +.sym 20437 o_tr_vc1_b$SB_IO_OUT +.sym 20440 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20441 o_tr_vc2$SB_IO_OUT +.sym 20445 o_rx_h_tx_l_b$SB_IO_OUT .sym 20453 i_config[0]$SB_IO_IN -.sym 20458 o_rx_h_tx_l$SB_IO_OUT -.sym 20465 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 20467 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20470 o_tr_vc1_b$SB_IO_OUT -.sym 20472 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 20473 io_ctrl_ins.rf_pin_state[6] -.sym 20475 io_ctrl_ins.rf_pin_state[7] -.sym 20476 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 20477 io_ctrl_ins.rf_pin_state[4] -.sym 20478 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 20479 io_ctrl_ins.rf_pin_state[5] -.sym 20481 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 20483 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20487 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 20489 w_ioc[2] -.sym 20491 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20495 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20496 o_tr_vc2$SB_IO_OUT -.sym 20498 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 20500 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 20504 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20505 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20506 io_ctrl_ins.rf_pin_state[7] -.sym 20510 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 20511 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20512 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 20513 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20516 io_ctrl_ins.rf_pin_state[5] -.sym 20517 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 20518 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20519 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20522 o_tr_vc2$SB_IO_OUT -.sym 20523 w_ioc[2] -.sym 20524 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20525 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 20528 io_ctrl_ins.rf_pin_state[4] -.sym 20529 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 20530 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20531 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 20534 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 20535 w_ioc[2] -.sym 20536 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 20537 o_tr_vc1_b$SB_IO_OUT -.sym 20540 io_ctrl_ins.rf_pin_state[6] -.sym 20541 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20542 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 20544 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 20471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20476 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E +.sym 20478 w_rx_data[0] +.sym 20480 w_rx_data[1] +.sym 20486 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20507 w_rx_data[0] +.sym 20531 w_rx_data[1] +.sym 20536 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20537 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 20544 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E .sym 20545 r_counter_$glb_clk -.sym 20561 o_tr_vc1_b$SB_IO_OUT -.sym 20564 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 20567 o_tr_vc1$SB_IO_OUT +.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 20672 i_config[0]$SB_IO_IN +.sym 20698 o_led1$SB_IO_OUT .sym 20748 w_smi_data_output[5] .sym 20750 o_led0$SB_IO_OUT .sym 20751 $PACKER_VCC_NET -.sym 20756 o_led0$SB_IO_OUT -.sym 20761 w_smi_data_output[5] -.sym 20764 $PACKER_VCC_NET -.sym 20770 smi_ctrl_ins.w_fifo_push_trigger -.sym 20785 rx_fifo.wr_addr[2] -.sym 20786 rx_fifo.wr_addr[5] +.sym 20756 $PACKER_VCC_NET +.sym 20766 w_smi_data_output[5] +.sym 20769 o_led0$SB_IO_OUT +.sym 20771 smi_ctrl_ins.tx_reg_state[2] +.sym 20772 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 20773 smi_ctrl_ins.tx_reg_state[1] +.sym 20774 smi_ctrl_ins.tx_reg_state[0] +.sym 20775 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 20776 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 20777 smi_ctrl_ins.tx_reg_state[3] .sym 20844 i_mosi$SB_IO_IN -.sym 20848 spi_if_ins.spi.r_rx_byte[5] -.sym 20850 spi_if_ins.spi.r_rx_byte[7] -.sym 20851 spi_if_ins.spi.r_rx_byte[0] -.sym 20904 i_mosi$SB_IO_IN -.sym 20905 w_smi_data_input[7] -.sym 20911 int_miso -.sym 20929 i_ss_SB_LUT4_I3_O -.sym 20931 rx_fifo.wr_addr[7] -.sym 20933 rx_fifo.wr_addr[9] -.sym 20935 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 20984 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 20986 spi_if_ins.w_rx_data[1] -.sym 21036 smi_ctrl_ins.r_fifo_push -.sym 21039 rx_fifo.rd_addr[0] -.sym 21040 w_rx_fifo_data[29] -.sym 21041 rx_fifo.wr_addr[4] -.sym 21042 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 21056 rx_fifo.wr_addr[4] +.sym 20847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.sym 20848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 20849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 20850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 20851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 20852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 20853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 20888 w_smi_data_input[7] +.sym 20912 int_miso +.sym 20924 tx_fifo.wr_addr[8] +.sym 20927 i_rst_b$SB_IO_IN +.sym 20941 rx_fifo.wr_addr[9] +.sym 20984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 20985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 20986 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 20987 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.sym 20988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 20989 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.sym 20990 tx_fifo.wr_addr[9] +.sym 20991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 21026 tx_fifo.wr_addr[1] +.sym 21033 tx_fifo.wr_addr[1] +.sym 21039 rx_fifo.rd_addr[5] +.sym 21040 rx_fifo.rd_addr[1] +.sym 21043 $PACKER_VCC_NET +.sym 21044 rx_fifo.rd_addr[3] +.sym 21045 int_miso +.sym 21046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 21047 $PACKER_VCC_NET +.sym 21048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 21056 rx_fifo.mem_i.0.1_WDATA_2 .sym 21058 $PACKER_VCC_NET -.sym 21060 w_rx_fifo_data[30] -.sym 21062 rx_fifo.wr_addr[0] -.sym 21067 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 21069 rx_fifo.wr_addr[8] -.sym 21072 w_rx_fifo_push -.sym 21074 rx_fifo.wr_addr[6] -.sym 21075 rx_fifo.wr_addr[7] -.sym 21077 rx_fifo.wr_addr[9] -.sym 21078 rx_fifo.wr_addr[3] -.sym 21081 rx_fifo.wr_addr[2] +.sym 21060 rx_fifo.wr_addr[6] +.sym 21063 rx_fifo.wr_addr[1] +.sym 21065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21067 rx_fifo.wr_addr[8] +.sym 21068 rx_fifo.wr_addr[3] +.sym 21069 rx_fifo.wr_addr[4] +.sym 21071 rx_fifo.wr_addr[7] +.sym 21077 rx_fifo.wr_addr[0] +.sym 21081 rx_fifo.mem_i.0.1_WDATA_3 .sym 21082 rx_fifo.wr_addr[5] -.sym 21085 w_rx_fifo_data[28] -.sym 21086 spi_if_ins.spi.r_rx_byte[1] -.sym 21088 spi_if_ins.spi.r_rx_byte[4] -.sym 21089 spi_if_ins.spi.r_rx_byte[6] -.sym 21090 spi_if_ins.spi.r_rx_byte[2] -.sym 21092 spi_if_ins.spi.r_rx_byte[3] -.sym 21093 i_ss_SB_LUT4_I3_O -.sym 21102 rx_fifo.wr_addr[2] +.sym 21083 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 21084 rx_fifo.wr_addr[9] +.sym 21086 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 21087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 21088 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 21089 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 21090 tx_fifo.wr_addr_gray_rd[9] +.sym 21091 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 21092 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 21093 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 21102 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 21103 rx_fifo.wr_addr[3] .sym 21105 rx_fifo.wr_addr[4] .sym 21106 rx_fifo.wr_addr[5] @@ -10510,80 +10104,84 @@ .sym 21108 rx_fifo.wr_addr[7] .sym 21109 rx_fifo.wr_addr[8] .sym 21110 rx_fifo.wr_addr[9] -.sym 21111 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21111 rx_fifo.wr_addr[1] .sym 21112 rx_fifo.wr_addr[0] .sym 21113 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21114 w_rx_fifo_push -.sym 21116 w_rx_fifo_data[28] -.sym 21120 w_rx_fifo_data[30] +.sym 21114 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21116 rx_fifo.mem_i.0.1_WDATA_3 +.sym 21120 rx_fifo.mem_i.0.1_WDATA_2 .sym 21123 $PACKER_VCC_NET -.sym 21134 $PACKER_VCC_NET -.sym 21139 o_smi_read_req$SB_IO_OUT -.sym 21140 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 21142 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 21145 rx_fifo.rd_addr[9] -.sym 21146 rx_fifo.wr_addr[0] -.sym 21147 int_miso -.sym 21160 w_rx_fifo_data[31] -.sym 21161 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21162 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 21165 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 21167 w_rx_fifo_pull -.sym 21168 rx_fifo.rd_addr[9] -.sym 21169 $PACKER_VCC_NET -.sym 21170 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 21174 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 21176 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21177 rx_fifo.rd_addr[0] -.sym 21178 w_rx_fifo_data[29] -.sym 21180 rx_fifo.rd_addr[3] -.sym 21181 rx_fifo.rd_addr[6] -.sym 21189 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 21190 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 21191 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 21192 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 21193 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 21194 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 21195 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 21204 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 21129 rx_fifo.wr_addr[1] +.sym 21131 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21132 rx_fifo.mem_i.0.1_WDATA_2 +.sym 21136 rx_fifo.wr_addr[3] +.sym 21139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 21140 $PACKER_VCC_NET +.sym 21141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 21146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 21150 rx_fifo.wr_addr[3] +.sym 21151 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21157 rx_fifo.rd_addr[0] +.sym 21158 rx_fifo.rd_addr[6] +.sym 21160 rx_fifo.rd_addr[4] +.sym 21164 rx_fifo.rd_addr[7] +.sym 21167 rx_fifo.rd_addr[2] +.sym 21169 rx_fifo.rd_addr[8] +.sym 21170 rx_fifo.rd_addr[9] +.sym 21171 rx_fifo.mem_i.0.1_WDATA_1 +.sym 21172 rx_fifo.mem_i.0.1_WDATA +.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21177 rx_fifo.rd_addr[5] +.sym 21178 rx_fifo.rd_addr[1] +.sym 21182 rx_fifo.rd_addr[3] +.sym 21185 $PACKER_VCC_NET +.sym 21190 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 21192 w_tx_fifo_full +.sym 21193 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 21195 smi_ctrl_ins.r_fifo_push_1 +.sym 21204 rx_fifo.rd_addr[2] .sym 21205 rx_fifo.rd_addr[3] -.sym 21207 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21208 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 21207 rx_fifo.rd_addr[4] +.sym 21208 rx_fifo.rd_addr[5] .sym 21209 rx_fifo.rd_addr[6] -.sym 21210 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21211 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 21210 rx_fifo.rd_addr[7] +.sym 21211 rx_fifo.rd_addr[8] .sym 21212 rx_fifo.rd_addr[9] -.sym 21213 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 21213 rx_fifo.rd_addr[1] .sym 21214 rx_fifo.rd_addr[0] .sym 21215 r_counter_$glb_clk -.sym 21216 w_rx_fifo_pull +.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 21217 $PACKER_VCC_NET -.sym 21221 w_rx_fifo_data[31] -.sym 21225 w_rx_fifo_data[29] -.sym 21232 spi_if_ins.w_rx_data[6] -.sym 21233 w_rx_fifo_pull -.sym 21234 spi_if_ins.w_rx_data[5] -.sym 21242 spi_if_ins.spi.r_rx_byte[4] -.sym 21250 spi_if_ins.w_rx_data[3] -.sym 21252 i_ss_SB_LUT4_I3_O -.sym 21260 w_rx_fifo_push -.sym 21262 $PACKER_VCC_NET -.sym 21263 rx_fifo.wr_addr[3] -.sym 21264 rx_fifo.wr_addr[6] -.sym 21268 rx_fifo.wr_addr[9] -.sym 21269 w_rx_fifo_data[22] -.sym 21271 w_rx_fifo_data[20] -.sym 21275 rx_fifo.wr_addr[7] -.sym 21276 rx_fifo.wr_addr[8] -.sym 21280 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 21282 rx_fifo.wr_addr[5] -.sym 21284 rx_fifo.wr_addr[0] -.sym 21287 rx_fifo.wr_addr[4] -.sym 21289 rx_fifo.wr_addr[2] -.sym 21291 spi_if_ins.w_rx_data[2] -.sym 21292 spi_if_ins.w_rx_data[3] -.sym 21295 spi_if_ins.w_rx_data[4] -.sym 21306 rx_fifo.wr_addr[2] +.sym 21221 rx_fifo.mem_i.0.1_WDATA +.sym 21225 rx_fifo.mem_i.0.1_WDATA_1 +.sym 21232 w_rx_fifo_pulled_data[23] +.sym 21234 tx_fifo.wr_addr[1] +.sym 21236 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 21240 rx_fifo.rd_addr[7] +.sym 21241 rx_fifo.rd_addr[0] +.sym 21242 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 21245 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 21248 tx_fifo.rd_addr_gray_wr[9] +.sym 21250 spi_if_ins.spi.r2_rx_done +.sym 21259 rx_fifo.wr_addr[7] +.sym 21260 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21262 rx_fifo.wr_addr[8] +.sym 21267 rx_fifo.mem_q.0.1_WDATA_2 +.sym 21269 rx_fifo.wr_addr[6] +.sym 21270 rx_fifo.wr_addr[5] +.sym 21271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 21273 rx_fifo.wr_addr[4] +.sym 21274 rx_fifo.wr_addr[1] +.sym 21275 rx_fifo.wr_addr[9] +.sym 21278 $PACKER_VCC_NET +.sym 21282 rx_fifo.wr_addr[0] +.sym 21285 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21288 rx_fifo.wr_addr[3] +.sym 21290 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 21291 o_smi_read_req$SB_IO_OUT +.sym 21292 spi_if_ins.spi.r2_rx_done +.sym 21296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 21306 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 21307 rx_fifo.wr_addr[3] .sym 21309 rx_fifo.wr_addr[4] .sym 21310 rx_fifo.wr_addr[5] @@ -10591,71 +10189,81 @@ .sym 21312 rx_fifo.wr_addr[7] .sym 21313 rx_fifo.wr_addr[8] .sym 21314 rx_fifo.wr_addr[9] -.sym 21315 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21315 rx_fifo.wr_addr[1] .sym 21316 rx_fifo.wr_addr[0] .sym 21317 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21318 w_rx_fifo_push -.sym 21320 w_rx_fifo_data[20] -.sym 21324 w_rx_fifo_data[22] +.sym 21318 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21320 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21324 rx_fifo.mem_q.0.1_WDATA_2 .sym 21327 $PACKER_VCC_NET -.sym 21337 $PACKER_VCC_NET -.sym 21339 rx_fifo.wr_addr[3] -.sym 21340 rx_fifo.wr_addr[6] -.sym 21347 rx_fifo.wr_addr[9] -.sym 21348 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21352 w_rx_fifo_pull -.sym 21353 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 21360 w_rx_fifo_data[23] -.sym 21362 w_rx_fifo_pull -.sym 21364 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21365 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21366 w_rx_fifo_data[21] -.sym 21369 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 21370 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 21371 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 21372 rx_fifo.rd_addr[3] -.sym 21373 $PACKER_VCC_NET -.sym 21380 rx_fifo.rd_addr[6] -.sym 21382 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 21383 rx_fifo.rd_addr[9] -.sym 21384 rx_fifo.rd_addr[0] -.sym 21408 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 21336 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21343 rx_fifo.mem_q.0.1_WDATA_2 +.sym 21348 rx_fifo.wr_addr[9] +.sym 21349 smi_ctrl_ins.r_fifo_push +.sym 21355 rx_fifo.wr_addr[8] +.sym 21360 rx_fifo.rd_addr[1] +.sym 21362 rx_fifo.rd_addr[8] +.sym 21363 rx_fifo.rd_addr[7] +.sym 21368 rx_fifo.rd_addr[3] +.sym 21369 rx_fifo.rd_addr[2] +.sym 21370 rx_fifo.rd_addr[0] +.sym 21373 rx_fifo.rd_addr[4] +.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21380 rx_fifo.mem_q.0.1_WDATA_1 +.sym 21381 rx_fifo.rd_addr[5] +.sym 21387 rx_fifo.rd_addr[6] +.sym 21389 $PACKER_VCC_NET +.sym 21390 rx_fifo.rd_addr[9] +.sym 21391 rx_fifo.mem_q.0.1_WDATA +.sym 21393 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 21395 o_miso_$_TBUF__Y_E +.sym 21396 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 21408 rx_fifo.rd_addr[2] .sym 21409 rx_fifo.rd_addr[3] -.sym 21411 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21412 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 21411 rx_fifo.rd_addr[4] +.sym 21412 rx_fifo.rd_addr[5] .sym 21413 rx_fifo.rd_addr[6] -.sym 21414 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21415 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 21414 rx_fifo.rd_addr[7] +.sym 21415 rx_fifo.rd_addr[8] .sym 21416 rx_fifo.rd_addr[9] -.sym 21417 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 21417 rx_fifo.rd_addr[1] .sym 21418 rx_fifo.rd_addr[0] .sym 21419 r_counter_$glb_clk -.sym 21420 w_rx_fifo_pull +.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 21421 $PACKER_VCC_NET -.sym 21425 w_rx_fifo_data[23] -.sym 21429 w_rx_fifo_data[21] -.sym 21442 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 21444 w_rx_fifo_data[23] -.sym 21452 rx_fifo.rd_addr[0] -.sym 21463 rx_fifo.wr_addr[7] -.sym 21464 rx_fifo.wr_addr[8] -.sym 21466 $PACKER_VCC_NET -.sym 21468 w_rx_fifo_data[24] -.sym 21473 w_rx_fifo_push -.sym 21475 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 21480 rx_fifo.wr_addr[4] -.sym 21482 w_rx_fifo_data[26] -.sym 21483 rx_fifo.wr_addr[0] -.sym 21485 rx_fifo.wr_addr[9] -.sym 21486 rx_fifo.wr_addr[3] -.sym 21489 rx_fifo.wr_addr[2] -.sym 21490 rx_fifo.wr_addr[5] -.sym 21493 rx_fifo.wr_addr[6] -.sym 21494 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 21495 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 21496 spi_if_ins.spi.SCKr[0] -.sym 21497 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 21510 rx_fifo.wr_addr[2] +.sym 21425 rx_fifo.mem_q.0.1_WDATA +.sym 21429 rx_fifo.mem_q.0.1_WDATA_1 +.sym 21434 rx_fifo.rd_addr[3] +.sym 21435 rx_fifo.rd_addr[2] +.sym 21438 rx_fifo.rd_addr[8] +.sym 21441 rx_fifo.rd_addr[4] +.sym 21447 rx_fifo.rd_addr[5] +.sym 21448 int_miso +.sym 21455 $PACKER_VCC_NET +.sym 21456 o_led0$SB_IO_OUT +.sym 21462 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21463 rx_fifo.wr_addr[5] +.sym 21464 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21470 rx_fifo.wr_addr[3] +.sym 21471 rx_fifo.wr_addr[6] +.sym 21473 rx_fifo.wr_addr[4] +.sym 21474 rx_fifo.wr_addr[0] +.sym 21475 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21477 rx_fifo.wr_addr[1] +.sym 21479 rx_fifo.wr_addr[7] +.sym 21480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 21482 $PACKER_VCC_NET +.sym 21486 rx_fifo.wr_addr[9] +.sym 21493 rx_fifo.wr_addr[8] +.sym 21494 spi_if_ins.spi.r_rx_byte[4] +.sym 21495 spi_if_ins.spi.r_rx_byte[5] +.sym 21496 spi_if_ins.spi.r_rx_byte[2] +.sym 21497 spi_if_ins.spi.r_rx_byte[6] +.sym 21498 spi_if_ins.spi.r_rx_byte[7] +.sym 21499 spi_if_ins.spi.r_rx_byte[0] +.sym 21500 spi_if_ins.spi.r_rx_byte[3] +.sym 21501 spi_if_ins.spi.r_rx_byte[1] +.sym 21510 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] .sym 21511 rx_fifo.wr_addr[3] .sym 21513 rx_fifo.wr_addr[4] .sym 21514 rx_fifo.wr_addr[5] @@ -10663,2159 +10271,2432 @@ .sym 21516 rx_fifo.wr_addr[7] .sym 21517 rx_fifo.wr_addr[8] .sym 21518 rx_fifo.wr_addr[9] -.sym 21519 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21519 rx_fifo.wr_addr[1] .sym 21520 rx_fifo.wr_addr[0] .sym 21521 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21522 w_rx_fifo_push -.sym 21524 w_rx_fifo_data[24] -.sym 21528 w_rx_fifo_data[26] +.sym 21522 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21524 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21528 rx_fifo.mem_i.0.3_WDATA_2 .sym 21531 $PACKER_VCC_NET -.sym 21541 w_rx_fifo_push -.sym 21542 $PACKER_VCC_NET -.sym 21543 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 21548 rx_fifo.rd_addr[9] -.sym 21550 int_miso -.sym 21564 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 21565 rx_fifo.rd_addr[9] -.sym 21566 w_rx_fifo_pull -.sym 21570 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 21573 w_rx_fifo_data[27] -.sym 21577 w_rx_fifo_data[25] -.sym 21580 rx_fifo.rd_addr[6] -.sym 21584 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 21585 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 21587 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 21536 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 21542 rx_fifo.wr_addr[0] +.sym 21543 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21545 rx_fifo.wr_addr[1] +.sym 21546 rx_fifo.wr_addr[3] +.sym 21547 rx_fifo.wr_addr[5] +.sym 21564 rx_fifo.rd_addr[8] +.sym 21568 rx_fifo.rd_addr[6] +.sym 21570 rx_fifo.rd_addr[2] +.sym 21571 rx_fifo.rd_addr[5] +.sym 21572 rx_fifo.rd_addr[7] +.sym 21573 rx_fifo.rd_addr[1] +.sym 21574 rx_fifo.rd_addr[0] +.sym 21575 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21577 rx_fifo.mem_i.0.3_WDATA +.sym 21578 rx_fifo.rd_addr[9] +.sym 21579 rx_fifo.mem_i.0.3_WDATA_1 .sym 21588 rx_fifo.rd_addr[3] -.sym 21589 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21590 rx_fifo.rd_addr[0] +.sym 21589 rx_fifo.rd_addr[4] .sym 21593 $PACKER_VCC_NET -.sym 21597 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 21599 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 21601 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 21602 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 21603 int_miso -.sym 21612 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] +.sym 21596 spi_if_ins.w_rx_data[5] +.sym 21597 spi_if_ins.w_rx_data[6] +.sym 21598 spi_if_ins.w_rx_data[2] +.sym 21599 spi_if_ins.w_rx_data[1] +.sym 21600 spi_if_ins.w_rx_data[4] +.sym 21601 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 21602 spi_if_ins.w_rx_data[0] +.sym 21603 spi_if_ins.w_rx_data[3] +.sym 21612 rx_fifo.rd_addr[2] .sym 21613 rx_fifo.rd_addr[3] -.sym 21615 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 21616 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 21615 rx_fifo.rd_addr[4] +.sym 21616 rx_fifo.rd_addr[5] .sym 21617 rx_fifo.rd_addr[6] -.sym 21618 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 21619 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 21618 rx_fifo.rd_addr[7] +.sym 21619 rx_fifo.rd_addr[8] .sym 21620 rx_fifo.rd_addr[9] -.sym 21621 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] +.sym 21621 rx_fifo.rd_addr[1] .sym 21622 rx_fifo.rd_addr[0] .sym 21623 r_counter_$glb_clk -.sym 21624 w_rx_fifo_pull +.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 21625 $PACKER_VCC_NET -.sym 21629 w_rx_fifo_data[27] -.sym 21633 w_rx_fifo_data[25] -.sym 21639 w_rx_fifo_data[27] -.sym 21642 w_rx_fifo_pulled_data[25] -.sym 21649 r_counter -.sym 21655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 21658 spi_if_ins.w_rx_data[3] -.sym 21661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 21698 spi_if_ins.r_tx_byte[2] -.sym 21700 spi_if_ins.r_tx_byte[5] -.sym 21701 spi_if_ins.r_tx_byte[0] -.sym 21704 spi_if_ins.r_tx_byte[3] -.sym 21705 spi_if_ins.r_tx_byte[4] -.sym 21744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 21748 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 21751 spi_if_ins.spi.r_tx_bit_count[2] -.sym 21752 spi_if_ins.r_tx_byte[7] -.sym 21761 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 21800 spi_if_ins.spi.r_tx_byte[0] -.sym 21801 spi_if_ins.spi.r_tx_byte[6] -.sym 21802 spi_if_ins.spi.r_tx_byte[7] -.sym 21803 spi_if_ins.spi.r_tx_byte[5] -.sym 21804 spi_if_ins.spi.r_tx_byte[1] -.sym 21805 spi_if_ins.spi.r_tx_byte[4] -.sym 21806 spi_if_ins.spi.r_tx_byte[2] -.sym 21807 spi_if_ins.spi.r_tx_byte[3] -.sym 21845 r_tx_data[0] -.sym 21846 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 21851 r_tx_data[3] -.sym 21856 $PACKER_VCC_NET -.sym 21863 spi_if_ins.r_tx_byte[6] -.sym 21864 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 21903 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 21904 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 21905 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 21906 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 21907 lvds_rx_09_inst.r_phase_count[1] -.sym 21908 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 21945 spi_if_ins.spi.r_tx_byte[2] -.sym 22005 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 22006 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 22011 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 22049 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 22060 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 22110 w_rx_09_fifo_push -.sym 22112 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 22152 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 22154 o_rx_h_tx_l$SB_IO_OUT -.sym 22251 w_rx_fifo_full +.sym 21629 rx_fifo.mem_i.0.3_WDATA +.sym 21633 rx_fifo.mem_i.0.3_WDATA_1 +.sym 21634 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 21639 rx_fifo.rd_addr[1] +.sym 21640 w_rx_fifo_pulled_data[31] +.sym 21641 rx_fifo.wr_addr[6] +.sym 21642 w_rx_fifo_pulled_data[29] +.sym 21643 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21644 i_glob_clock$SB_IO_IN +.sym 21647 rx_fifo.rd_addr[5] +.sym 21648 rx_fifo.rd_addr[7] +.sym 21652 w_rx_data[7] +.sym 21653 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 21655 spi_if_ins.w_rx_data[0] +.sym 21659 spi_if_ins.w_rx_data[5] +.sym 21661 spi_if_ins.w_rx_data[6] +.sym 21704 w_rx_data[0] +.sym 21705 w_rx_data[7] +.sym 21743 spi_if_ins.w_rx_data[1] +.sym 21749 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 21751 spi_if_ins.w_rx_data[2] +.sym 21752 i_glob_clock$SB_IO_IN +.sym 21756 w_rx_data[2] +.sym 21757 w_rx_data[0] +.sym 21800 w_rx_data[2] +.sym 21801 w_rx_data[1] +.sym 21802 w_rx_data[5] +.sym 21803 w_rx_data[4] +.sym 21804 w_rx_data[6] +.sym 21806 w_rx_data[3] +.sym 21843 io_pmod[3]$SB_IO_IN +.sym 21856 o_led0$SB_IO_OUT +.sym 21863 w_rx_data[2] +.sym 21865 w_rx_data[1] +.sym 21905 io_pmod_SB_DFFE_Q_E +.sym 21909 o_led0$SB_IO_OUT +.sym 21945 w_rx_data[3] +.sym 21953 w_rx_data[1] +.sym 21958 w_rx_data[4] +.sym 21960 w_rx_data[6] +.sym 22004 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 22005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 22006 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 22007 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 22008 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 22009 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 22010 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] +.sym 22011 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 22053 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 22055 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 22059 w_rx_data[2] +.sym 22060 w_rx_data[7] +.sym 22061 w_rx_data[1] +.sym 22106 io_ctrl_ins.rf_pin_state[0] +.sym 22107 io_ctrl_ins.rf_pin_state[4] +.sym 22108 io_ctrl_ins.rf_pin_state[7] +.sym 22109 io_ctrl_ins.rf_pin_state[6] +.sym 22110 io_ctrl_ins.rf_pin_state[2] +.sym 22111 io_ctrl_ins.rf_pin_state[3] +.sym 22112 io_ctrl_ins.rf_pin_state[1] +.sym 22113 io_ctrl_ins.rf_pin_state[5] +.sym 22156 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 22214 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 22272 i_button_SB_LUT4_I0_O[1] +.sym 22352 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 22372 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O .sym 22487 o_led1$SB_IO_OUT -.sym 22500 o_led1$SB_IO_OUT +.sym 22505 o_led1$SB_IO_OUT .sym 22517 int_miso -.sym 22519 i_ss_SB_LUT4_I3_O -.sym 22529 i_ss_SB_LUT4_I3_O -.sym 22537 int_miso -.sym 22542 i_sck$SB_IO_IN -.sym 22549 spi_if_ins.spi.r_rx_done +.sym 22519 o_miso_$_TBUF__Y_E +.sym 22527 o_miso_$_TBUF__Y_E +.sym 22528 int_miso .sym 22554 i_mosi$SB_IO_IN -.sym 22589 w_smi_data_input[7] -.sym 22597 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 22609 smi_ctrl_ins.swe_and_reset -.sym 22618 w_smi_data_input[7] +.sym 22563 i_mosi$SB_IO_IN +.sym 22587 smi_ctrl_ins.tx_reg_state[1] +.sym 22588 smi_ctrl_ins.tx_reg_state[0] +.sym 22589 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 22592 i_rst_b$SB_IO_IN +.sym 22593 smi_ctrl_ins.tx_reg_state[2] +.sym 22597 w_smi_data_input[7] +.sym 22599 smi_ctrl_ins.tx_reg_state[3] +.sym 22600 smi_ctrl_ins.swe_and_reset +.sym 22601 i_rst_b$SB_IO_IN +.sym 22602 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 22605 w_smi_data_input[7] +.sym 22623 i_rst_b$SB_IO_IN +.sym 22625 w_smi_data_input[7] +.sym 22626 smi_ctrl_ins.tx_reg_state[0] +.sym 22630 smi_ctrl_ins.tx_reg_state[1] +.sym 22631 smi_ctrl_ins.tx_reg_state[2] +.sym 22632 w_smi_data_input[7] +.sym 22635 w_smi_data_input[7] +.sym 22636 smi_ctrl_ins.tx_reg_state[2] +.sym 22637 i_rst_b$SB_IO_IN +.sym 22641 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 22644 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 22647 w_smi_data_input[7] +.sym 22648 smi_ctrl_ins.tx_reg_state[0] +.sym 22649 i_rst_b$SB_IO_IN +.sym 22650 smi_ctrl_ins.tx_reg_state[3] +.sym 22653 smi_ctrl_ins.tx_reg_state[3] +.sym 22655 smi_ctrl_ins.tx_reg_state[0] +.sym 22656 i_rst_b$SB_IO_IN +.sym 22659 smi_ctrl_ins.tx_reg_state[1] +.sym 22661 i_rst_b$SB_IO_IN +.sym 22662 w_smi_data_input[7] .sym 22664 smi_ctrl_ins.swe_and_reset -.sym 22665 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN -.sym 22670 smi_ctrl_ins.r_fifo_push -.sym 22680 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 22689 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 22704 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 22707 i_ss$SB_IO_IN -.sym 22718 spi_if_ins.spi.r_rx_done -.sym 22724 i_ss$SB_IO_IN -.sym 22726 spi_if_ins.spi.r_rx_byte[0] +.sym 22699 w_smi_data_input[7] +.sym 22715 i_ss$SB_IO_IN +.sym 22720 i_sck$SB_IO_IN +.sym 22723 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] .sym 22729 i_sck$SB_IO_IN -.sym 22734 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 22740 i_sck$SB_IO_IN -.sym 22747 i_sck$SB_IO_IN -.sym 22748 i_mosi$SB_IO_IN -.sym 22756 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 22758 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 22774 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 22794 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 22806 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 22810 i_mosi$SB_IO_IN -.sym 22826 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 22827 i_sck$SB_IO_IN -.sym 22831 spi_if_ins.spi.r_rx_bit_count[2] -.sym 22832 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 22833 spi_if_ins.spi.r_rx_bit_count[1] -.sym 22836 spi_if_ins.spi.r_rx_bit_count[0] -.sym 22842 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 22846 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 22854 spi_if_ins.spi.r_rx_byte[5] -.sym 22858 i_sck$SB_IO_IN -.sym 22861 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 22862 i_sck$SB_IO_IN -.sym 22870 spi_if_ins.spi.r_rx_byte[1] -.sym 22874 spi_if_ins.spi.r_rx_byte[7] -.sym 22897 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 22903 spi_if_ins.spi.r_rx_byte[7] -.sym 22915 spi_if_ins.spi.r_rx_byte[1] -.sym 22949 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 22733 i_ss$SB_IO_IN +.sym 22734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22740 smi_ctrl_ins.swe_and_reset +.sym 22747 tx_fifo.wr_addr[1] +.sym 22750 tx_fifo.wr_addr[8] +.sym 22760 tx_fifo.wr_addr[1] +.sym 22763 tx_fifo.wr_addr[4] +.sym 22765 tx_fifo.wr_addr[3] +.sym 22767 tx_fifo.wr_addr[5] +.sym 22769 tx_fifo.wr_addr[7] +.sym 22775 tx_fifo.wr_addr[6] +.sym 22777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 22779 $nextpnr_ICESTORM_LC_1$O +.sym 22782 tx_fifo.wr_addr[1] +.sym 22785 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22788 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 22789 tx_fifo.wr_addr[1] +.sym 22791 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22794 tx_fifo.wr_addr[3] +.sym 22795 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22797 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22799 tx_fifo.wr_addr[4] +.sym 22801 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22803 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22806 tx_fifo.wr_addr[5] +.sym 22807 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22809 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22812 tx_fifo.wr_addr[6] +.sym 22813 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22815 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 22818 tx_fifo.wr_addr[7] +.sym 22819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 22821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 22824 tx_fifo.wr_addr[8] +.sym 22825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 22854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 22860 tx_fifo.rd_addr_gray_wr_r[8] +.sym 22865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 22870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 22871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.sym 22872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 22877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 22881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 22882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22887 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22891 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.sym 22893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 22895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 22897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.sym 22899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22900 tx_fifo.wr_addr[9] +.sym 22901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 22904 tx_fifo.wr_addr[9] +.sym 22906 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 22909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 22916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.sym 22917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 22918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 22923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.sym 22924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22927 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 22928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 22930 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22936 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 22939 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 22945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 22946 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 22947 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 22948 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.sym 22949 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 22950 r_counter_$glb_clk -.sym 22953 spi_if_ins.w_rx_data[6] -.sym 22955 spi_if_ins.w_rx_data[0] -.sym 22956 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 22957 spi_if_ins.w_rx_data[5] -.sym 22958 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 22976 spi_if_ins.spi.r_rx_byte[2] -.sym 22979 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 22981 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 22987 spi_if_ins.w_rx_data[6] -.sym 22994 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 22995 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 22996 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23002 i_ss$SB_IO_IN -.sym 23004 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23005 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23006 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23018 i_sck$SB_IO_IN -.sym 23027 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23038 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23045 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23051 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23065 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23071 i_ss$SB_IO_IN -.sym 23072 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23073 i_sck$SB_IO_IN -.sym 23101 spi_if_ins.w_rx_data[0] -.sym 23105 spi_if_ins.w_rx_data[5] -.sym 23108 spi_if_ins.spi.r_rx_byte[3] -.sym 23118 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23119 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23128 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23132 i_sck$SB_IO_IN -.sym 23133 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23137 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23143 i_ss_SB_LUT4_I3_O -.sym 23144 i_mosi$SB_IO_IN -.sym 23146 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23155 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23164 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23169 i_mosi$SB_IO_IN -.sym 23176 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23179 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23185 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23191 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23195 i_ss_SB_LUT4_I3_O -.sym 23196 i_sck$SB_IO_IN -.sym 23224 spi_if_ins.w_rx_data[4] -.sym 23227 i_ss$SB_IO_IN -.sym 23231 i_sck$SB_IO_IN -.sym 23232 spi_if_ins.w_rx_data[2] -.sym 23243 spi_if_ins.spi.r_rx_byte[4] -.sym 23248 spi_if_ins.spi.r_rx_byte[2] -.sym 23250 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23268 spi_if_ins.spi.r_rx_byte[3] -.sym 23279 spi_if_ins.spi.r_rx_byte[2] -.sym 23286 spi_if_ins.spi.r_rx_byte[3] -.sym 23305 spi_if_ins.spi.r_rx_byte[4] -.sym 23318 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 22967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 22976 tx_fifo.wr_addr_gray_rd[9] +.sym 22995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 22996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 22998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 22999 tx_fifo.wr_addr[9] +.sym 23000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 23001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 23002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 23003 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 23005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 23007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 23008 tx_fifo.wr_addr[1] +.sym 23009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 23011 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 23013 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 23017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 23019 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 23020 tx_fifo.rd_addr_gray_wr_r[8] +.sym 23021 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 23024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 23026 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 23027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 23028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 23029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 23032 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 23034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 23035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23038 tx_fifo.wr_addr[1] +.sym 23039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23040 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 23041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 23045 tx_fifo.rd_addr_gray_wr_r[8] +.sym 23046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 23047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 23050 tx_fifo.wr_addr[9] +.sym 23056 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 23059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 23063 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 23064 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 23065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 23068 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 23069 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 23070 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 23073 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 23086 w_rx_data[0] +.sym 23100 i_ss$SB_IO_IN +.sym 23104 i_sck$SB_IO_IN +.sym 23105 i_ss$SB_IO_IN +.sym 23106 o_smi_read_req$SB_IO_OUT +.sym 23108 i_sck$SB_IO_IN +.sym 23116 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 23120 tx_fifo.wr_addr[1] +.sym 23121 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 23124 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23131 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 23136 w_tx_fifo_full +.sym 23139 smi_ctrl_ins.r_fifo_push_1 +.sym 23141 smi_ctrl_ins.r_fifo_push +.sym 23142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 23161 w_tx_fifo_full +.sym 23162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 23163 tx_fifo.wr_addr[1] +.sym 23173 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 23174 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 23175 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 23176 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 23179 smi_ctrl_ins.r_fifo_push_1 +.sym 23180 smi_ctrl_ins.r_fifo_push +.sym 23182 w_tx_fifo_full +.sym 23194 smi_ctrl_ins.r_fifo_push +.sym 23196 r_counter_$glb_clk +.sym 23197 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 23203 o_miso_$_TBUF__Y_E +.sym 23204 spi_if_ins.spi.r_rx_done +.sym 23220 w_tx_fifo_full +.sym 23222 i_sck$SB_IO_IN +.sym 23223 i_ss$SB_IO_IN +.sym 23225 o_miso_$_TBUF__Y_E +.sym 23226 i_sck$SB_IO_IN +.sym 23230 i_ss$SB_IO_IN +.sym 23241 tx_fifo.rd_addr_gray_wr[9] +.sym 23251 w_tx_fifo_full +.sym 23261 o_led0$SB_IO_OUT +.sym 23265 tx_fifo.rd_addr_gray_wr[0] +.sym 23266 w_rx_fifo_empty +.sym 23269 spi_if_ins.spi.r_rx_done +.sym 23273 tx_fifo.rd_addr_gray_wr[0] +.sym 23278 w_tx_fifo_full +.sym 23279 w_rx_fifo_empty +.sym 23281 o_led0$SB_IO_OUT +.sym 23285 spi_if_ins.spi.r_rx_done +.sym 23310 tx_fifo.rd_addr_gray_wr[9] .sym 23319 r_counter_$glb_clk -.sym 23468 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 23477 spi_if_ins.r_tx_byte[7] -.sym 23497 i_ss$SB_IO_IN -.sym 23501 i_sck$SB_IO_IN -.sym 23503 spi_if_ins.spi.SCKr[0] -.sym 23505 spi_if_ins.r_tx_data_valid -.sym 23512 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23520 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23526 i_ss$SB_IO_IN -.sym 23527 spi_if_ins.r_tx_data_valid -.sym 23532 i_sck$SB_IO_IN -.sym 23537 spi_if_ins.spi.SCKr[0] -.sym 23565 r_counter_$glb_clk -.sym 23567 r_tx_data[5] -.sym 23568 i_glob_clock$SB_IO_IN -.sym 23572 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23322 spi_if_ins.spi.r_rx_bit_count[1] +.sym 23323 spi_if_ins.spi.r_rx_bit_count[2] +.sym 23325 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23326 spi_if_ins.spi.r_rx_bit_count[0] +.sym 23327 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23344 io_pmod[7]$SB_IO_IN +.sym 23352 w_rx_fifo_empty +.sym 23367 o_miso_$_TBUF__Y_E +.sym 23373 o_miso_$_TBUF__Y_E +.sym 23378 i_sck$SB_IO_IN +.sym 23379 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23386 i_mosi$SB_IO_IN +.sym 23403 i_mosi$SB_IO_IN +.sym 23413 o_miso_$_TBUF__Y_E +.sym 23422 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23441 o_miso_$_TBUF__Y_E +.sym 23442 i_sck$SB_IO_IN +.sym 23444 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23447 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23448 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 23449 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23450 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23451 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23454 o_led0$SB_IO_OUT +.sym 23470 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23486 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23494 i_sck$SB_IO_IN +.sym 23496 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23497 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23501 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23504 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23505 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 23506 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23508 i_mosi$SB_IO_IN +.sym 23516 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23518 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23525 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23533 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23538 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23542 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 23548 i_mosi$SB_IO_IN +.sym 23555 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23560 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 23565 i_sck$SB_IO_IN .sym 23580 i_glob_clock$SB_IO_IN -.sym 23583 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23597 spi_if_ins.w_rx_data[5] -.sym 23608 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23609 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23610 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 23615 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 23616 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23619 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23620 spi_if_ins.spi.r_tx_bit_count[2] -.sym 23624 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 23627 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 23628 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 23636 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 23637 spi_if_ins.r_tx_byte[7] -.sym 23647 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 23648 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23659 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23660 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23661 spi_if_ins.spi.r_tx_bit_count[2] -.sym 23662 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 23671 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23672 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23673 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23678 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23679 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 23680 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 23683 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 23684 spi_if_ins.r_tx_byte[7] -.sym 23685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23687 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23591 spi_if_ins.w_rx_data[4] +.sym 23592 w_rx_data[0] +.sym 23597 spi_if_ins.w_rx_data[3] +.sym 23602 $io_pmod[3]$iobuf_i +.sym 23608 spi_if_ins.spi.r_rx_byte[4] +.sym 23609 spi_if_ins.spi.r_rx_byte[5] +.sym 23610 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23612 spi_if_ins.spi.r_rx_byte[7] +.sym 23614 spi_if_ins.spi.r_rx_byte[3] +.sym 23615 spi_if_ins.spi.r_rx_byte[1] +.sym 23618 spi_if_ins.spi.r_rx_byte[2] +.sym 23619 spi_if_ins.spi.r_rx_byte[6] +.sym 23621 spi_if_ins.spi.r_rx_byte[0] +.sym 23642 spi_if_ins.spi.r_rx_byte[5] +.sym 23648 spi_if_ins.spi.r_rx_byte[6] +.sym 23656 spi_if_ins.spi.r_rx_byte[2] +.sym 23661 spi_if_ins.spi.r_rx_byte[1] +.sym 23667 spi_if_ins.spi.r_rx_byte[4] +.sym 23674 spi_if_ins.spi.r_rx_byte[7] +.sym 23677 spi_if_ins.spi.r_rx_byte[0] +.sym 23686 spi_if_ins.spi.r_rx_byte[3] +.sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 23688 r_counter_$glb_clk -.sym 23693 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 23694 r_tx_data[4] -.sym 23704 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 23712 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23719 i_glob_clock$SB_IO_IN -.sym 23731 r_tx_data[5] -.sym 23737 r_tx_data[0] -.sym 23739 r_tx_data[2] -.sym 23741 r_tx_data[3] -.sym 23758 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O -.sym 23759 r_tx_data[4] -.sym 23765 r_tx_data[2] -.sym 23776 r_tx_data[5] -.sym 23785 r_tx_data[0] -.sym 23803 r_tx_data[3] -.sym 23806 r_tx_data[4] -.sym 23810 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O +.sym 23708 i_rst_b_SB_LUT4_I3_O +.sym 23715 spi_if_ins.w_rx_data[2] +.sym 23717 spi_if_ins.w_rx_data[1] +.sym 23742 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23744 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 23745 spi_if_ins.w_rx_data[0] +.sym 23803 spi_if_ins.w_rx_data[0] +.sym 23807 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 23810 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 23811 r_counter_$glb_clk -.sym 23819 w_rx_data[5] -.sym 23825 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 23828 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 23842 w_rx_data[5] -.sym 23854 spi_if_ins.r_tx_byte[2] -.sym 23856 spi_if_ins.r_tx_byte[5] -.sym 23857 spi_if_ins.r_tx_byte[0] -.sym 23858 spi_if_ins.r_tx_byte[7] -.sym 23862 spi_if_ins.r_tx_byte[1] -.sym 23865 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 23867 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23868 spi_if_ins.r_tx_byte[3] -.sym 23869 spi_if_ins.r_tx_byte[4] -.sym 23870 spi_if_ins.r_tx_byte[6] -.sym 23888 spi_if_ins.r_tx_byte[0] -.sym 23894 spi_if_ins.r_tx_byte[6] -.sym 23899 spi_if_ins.r_tx_byte[7] -.sym 23906 spi_if_ins.r_tx_byte[5] -.sym 23914 spi_if_ins.r_tx_byte[1] -.sym 23918 spi_if_ins.r_tx_byte[4] -.sym 23925 spi_if_ins.r_tx_byte[2] -.sym 23929 spi_if_ins.r_tx_byte[3] -.sym 23933 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23814 $io_pmod[2]$iobuf_i +.sym 23816 $io_pmod[1]$iobuf_i +.sym 23818 $io_pmod[3]$iobuf_i +.sym 23846 w_rx_data[0] +.sym 23854 spi_if_ins.w_rx_data[5] +.sym 23863 spi_if_ins.w_rx_data[4] +.sym 23864 spi_if_ins.w_rx_data[6] +.sym 23869 spi_if_ins.w_rx_data[3] +.sym 23875 spi_if_ins.w_rx_data[2] +.sym 23877 spi_if_ins.w_rx_data[1] +.sym 23881 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23888 spi_if_ins.w_rx_data[2] +.sym 23893 spi_if_ins.w_rx_data[1] +.sym 23899 spi_if_ins.w_rx_data[5] +.sym 23906 spi_if_ins.w_rx_data[4] +.sym 23914 spi_if_ins.w_rx_data[6] +.sym 23925 spi_if_ins.w_rx_data[3] +.sym 23933 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 23934 r_counter_$glb_clk -.sym 23935 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23948 spi_if_ins.r_tx_byte[1] -.sym 23962 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 23979 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 23980 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 23984 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 23986 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 23989 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 23990 lvds_rx_09_inst.r_phase_count[1] -.sym 23991 $PACKER_VCC_NET -.sym 23995 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 23999 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 24002 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 24003 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24004 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24009 $nextpnr_ICESTORM_LC_3$O -.sym 24012 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 24015 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 24017 lvds_rx_09_inst.r_phase_count[1] -.sym 24018 $PACKER_VCC_NET -.sym 24019 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 24022 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 24023 $PACKER_VCC_NET -.sym 24025 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 24028 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 24029 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 24030 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 24034 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24035 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24036 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 24037 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24040 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 24046 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24047 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24048 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 24049 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24056 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 24057 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 23943 $io_pmod[0]$iobuf_i +.sym 23948 w_rx_data[2] +.sym 23952 w_rx_data[1] +.sym 23961 w_rx_data[5] +.sym 23969 w_rx_data[3] +.sym 23977 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 23978 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 23979 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 23989 w_rx_data[0] +.sym 23993 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24028 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 24029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 24031 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24052 w_rx_data[0] +.sym 24056 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 24057 r_counter_$glb_clk .sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24076 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24102 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 24107 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24111 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24123 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 24125 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24130 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 24139 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 24145 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24146 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 24147 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24148 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24175 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24176 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24177 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 24178 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24179 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 24180 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 24062 o_shdn_tx_lna$SB_IO_OUT +.sym 24063 io_ctrl_ins.mixer_en_state +.sym 24072 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 24084 w_rx_data[0] +.sym 24085 o_rx_h_tx_l$SB_IO_OUT +.sym 24089 o_tr_vc1$SB_IO_OUT +.sym 24100 w_rx_data[2] +.sym 24102 w_rx_data[1] +.sym 24104 i_rst_b$SB_IO_IN +.sym 24106 w_rx_data[4] +.sym 24108 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24109 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 24113 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 24116 w_rx_data[0] +.sym 24126 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 24129 w_rx_data[3] +.sym 24130 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] +.sym 24135 w_rx_data[0] +.sym 24142 w_rx_data[1] +.sym 24147 w_rx_data[4] +.sym 24151 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] +.sym 24154 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 24159 w_rx_data[2] +.sym 24164 w_rx_data[3] +.sym 24169 i_rst_b$SB_IO_IN +.sym 24170 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 24171 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 24172 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 24179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 24180 r_counter_$glb_clk .sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24192 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24223 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24234 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 24235 w_rx_fifo_full -.sym 24237 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24245 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24280 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24281 w_rx_fifo_full -.sym 24282 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24283 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 24292 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 24294 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 24302 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 24303 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 24304 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24317 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 24182 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 24183 o_tr_vc1$SB_IO_OUT +.sym 24184 o_tr_vc1_b$SB_IO_OUT +.sym 24185 o_tr_vc2$SB_IO_OUT +.sym 24186 o_shdn_rx_lna$SB_IO_OUT +.sym 24187 o_rx_h_tx_l_b$SB_IO_OUT +.sym 24188 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 24189 o_rx_h_tx_l$SB_IO_OUT +.sym 24198 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 24200 i_rst_b$SB_IO_IN +.sym 24207 o_shdn_rx_lna$SB_IO_OUT +.sym 24225 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 24226 w_rx_data[4] +.sym 24228 w_rx_data[6] +.sym 24229 w_rx_data[7] +.sym 24230 w_rx_data[1] +.sym 24231 w_rx_data[5] +.sym 24236 w_rx_data[2] +.sym 24239 w_rx_data[3] +.sym 24251 w_rx_data[0] +.sym 24257 w_rx_data[0] +.sym 24264 w_rx_data[4] +.sym 24270 w_rx_data[7] +.sym 24274 w_rx_data[6] +.sym 24282 w_rx_data[2] +.sym 24287 w_rx_data[3] +.sym 24293 w_rx_data[1] +.sym 24298 w_rx_data[5] +.sym 24302 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 24303 r_counter_$glb_clk +.sym 24321 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 24351 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 24373 i_button_SB_LUT4_I0_O[1] +.sym 24415 i_button_SB_LUT4_I0_O[1] +.sym 24416 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] .sym 24596 o_led0$SB_IO_OUT -.sym 24611 o_led0$SB_IO_OUT -.sym 24666 io_ctrl_ins.o_data_out[5] -.sym 24685 i_sck$SB_IO_IN -.sym 24687 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 24689 i_ss$SB_IO_IN -.sym 24714 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 24720 i_sck$SB_IO_IN -.sym 24763 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 24764 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 24765 i_sck$SB_IO_IN -.sym 24766 i_ss$SB_IO_IN -.sym 24876 smi_ctrl_ins.w_fifo_push_trigger -.sym 24886 smi_ctrl_ins.w_fifo_push_trigger -.sym 24932 r_counter_$glb_clk -.sym 24933 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 25007 i_sck$SB_IO_IN -.sym 25011 i_ss$SB_IO_IN -.sym 25019 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25022 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25025 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25035 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25039 $nextpnr_ICESTORM_LC_9$O -.sym 25042 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25045 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 25048 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25054 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25055 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 25059 i_ss$SB_IO_IN -.sym 25060 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 25065 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25066 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25083 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25087 i_sck$SB_IO_IN -.sym 25088 i_ss$SB_IO_IN -.sym 25165 spi_if_ins.spi.r_rx_byte[6] -.sym 25171 i_ss$SB_IO_IN -.sym 25172 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25173 spi_if_ins.spi.r_rx_byte[0] -.sym 25174 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25175 spi_if_ins.spi.r_rx_byte[5] -.sym 25177 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25180 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 25203 spi_if_ins.spi.r_rx_byte[6] -.sym 25214 spi_if_ins.spi.r_rx_byte[0] -.sym 25219 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25220 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25222 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25228 spi_if_ins.spi.r_rx_byte[5] -.sym 25231 i_ss$SB_IO_IN -.sym 25232 spi_if_ins.spi.r_rx_bit_count[1] -.sym 25233 spi_if_ins.spi.r_rx_bit_count[0] -.sym 25234 spi_if_ins.spi.r_rx_bit_count[2] -.sym 25241 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 25242 r_counter_$glb_clk -.sym 25256 spi_if_ins.w_rx_data[6] +.sym 24618 o_led0$SB_IO_OUT +.sym 24655 i_ss$SB_IO_IN +.sym 24664 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 25100 o_smi_read_req$SB_IO_OUT +.sym 25261 o_miso_$_TBUF__Y_E +.sym 25401 io_pmod[7]$SB_IO_IN +.sym 25478 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 25481 i_sck$SB_IO_IN +.sym 25485 i_ss$SB_IO_IN +.sym 25491 i_ss$SB_IO_IN +.sym 25499 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 25537 i_ss$SB_IO_IN +.sym 25541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 25551 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 25552 i_sck$SB_IO_IN +.sym 25553 i_ss$SB_IO_IN +.sym 25554 io_pmod[3]$SB_IO_IN +.sym 25556 io_pmod[6]$SB_IO_IN +.sym 25627 i_sck$SB_IO_IN +.sym 25631 i_ss$SB_IO_IN +.sym 25636 spi_if_ins.spi.r_rx_bit_count[1] +.sym 25640 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25651 i_ss$SB_IO_IN +.sym 25653 spi_if_ins.spi.r_rx_bit_count[2] +.sym 25659 $nextpnr_ICESTORM_LC_4$O +.sym 25662 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25665 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 25667 spi_if_ins.spi.r_rx_bit_count[1] +.sym 25669 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25673 spi_if_ins.spi.r_rx_bit_count[2] +.sym 25675 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 25684 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25685 spi_if_ins.spi.r_rx_bit_count[2] +.sym 25686 spi_if_ins.spi.r_rx_bit_count[1] +.sym 25687 i_ss$SB_IO_IN +.sym 25693 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25696 spi_if_ins.spi.r_rx_bit_count[0] +.sym 25697 spi_if_ins.spi.r_rx_bit_count[2] +.sym 25698 spi_if_ins.spi.r_rx_bit_count[1] +.sym 25707 i_sck$SB_IO_IN +.sym 25708 i_ss$SB_IO_IN .sym 25711 i_glob_clock$SB_IO_IN -.sym 25878 i_glob_clock$SB_IO_IN -.sym 25941 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 25943 i_glob_clock$SB_IO_IN -.sym 25946 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 25948 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 25955 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 25959 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 25962 i_glob_clock$SB_IO_IN -.sym 25967 io_ctrl_ins.o_data_out[5] -.sym 25970 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 25972 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 25973 io_ctrl_ins.o_data_out[5] -.sym 25977 i_glob_clock$SB_IO_IN -.sym 26003 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 26016 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 26017 i_glob_clock$SB_IO_IN -.sym 26018 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 26028 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 26030 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 26101 i_glob_clock$SB_IO_IN -.sym 26105 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 26106 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 26110 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 26114 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 26119 io_ctrl_ins.o_data_out[4] -.sym 26146 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 26151 io_ctrl_ins.o_data_out[4] -.sym 26152 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 26171 spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.sym 26172 i_glob_clock$SB_IO_IN -.sym 26173 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 26262 spi_if_ins.w_rx_data[5] -.sym 26265 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.sym 26318 spi_if_ins.w_rx_data[5] -.sym 26326 spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O +.sym 25719 $io_pmod[3]$iobuf_i +.sym 25782 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25784 o_miso_$_TBUF__Y_E +.sym 25788 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 25790 i_ss$SB_IO_IN +.sym 25791 i_sck$SB_IO_IN +.sym 25795 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 25801 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 25802 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 25805 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 25817 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 25833 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 25840 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 25846 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 25851 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 25852 i_ss$SB_IO_IN +.sym 25858 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 25861 o_miso_$_TBUF__Y_E +.sym 25862 i_sck$SB_IO_IN +.sym 25879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 26174 io_pmod[2]$SB_IO_IN +.sym 26176 io_pmod[1]$SB_IO_IN +.sym 26247 w_rx_data[2] +.sym 26248 w_rx_data[1] +.sym 26261 w_rx_data[3] +.sym 26274 io_pmod_SB_DFFE_Q_E +.sym 26287 w_rx_data[2] +.sym 26300 w_rx_data[1] +.sym 26310 w_rx_data[3] +.sym 26326 io_pmod_SB_DFFE_Q_E .sym 26327 r_counter_$glb_clk -.sym 26965 o_rx_h_tx_l_b$SB_IO_OUT +.sym 26329 io_pmod[0]$SB_IO_IN +.sym 26413 io_pmod_SB_DFFE_Q_E +.sym 26415 w_rx_data[0] +.sym 26480 w_rx_data[0] +.sym 26481 io_pmod_SB_DFFE_Q_E +.sym 26482 r_counter_$glb_clk +.sym 26559 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26562 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26564 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26568 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26570 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26573 io_ctrl_ins.rf_pin_state[0] +.sym 26585 io_ctrl_ins.rf_pin_state[2] +.sym 26608 io_ctrl_ins.rf_pin_state[2] +.sym 26609 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26610 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26611 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26614 io_ctrl_ins.rf_pin_state[0] +.sym 26615 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26616 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26617 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26636 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26637 r_counter_$glb_clk +.sym 26715 io_ctrl_ins.rf_pin_state[6] +.sym 26719 io_ctrl_ins.rf_pin_state[5] +.sym 26720 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26721 io_ctrl_ins.rf_pin_state[4] +.sym 26722 io_ctrl_ins.rf_pin_state[7] +.sym 26725 io_ctrl_ins.rf_pin_state[3] +.sym 26726 io_ctrl_ins.rf_pin_state[1] +.sym 26732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 26733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26738 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26739 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26742 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 26743 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26745 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 26746 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26747 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26751 io_ctrl_ins.rf_pin_state[5] +.sym 26752 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26753 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 26754 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26757 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26758 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 26759 io_ctrl_ins.rf_pin_state[4] +.sym 26760 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26763 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26764 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26765 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26766 io_ctrl_ins.rf_pin_state[3] +.sym 26770 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 26771 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26772 io_ctrl_ins.rf_pin_state[1] +.sym 26775 io_ctrl_ins.rf_pin_state[6] +.sym 26777 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26778 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26782 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 26783 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 26787 io_ctrl_ins.rf_pin_state[7] +.sym 26789 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26790 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 26791 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26792 r_counter_$glb_clk .sym 27283 o_smi_read_req$SB_IO_OUT -.sym 27290 o_smi_read_req$SB_IO_OUT -.sym 27367 i_glob_clock$SB_IO_IN -.sym 27429 r_counter -.sym 27440 r_counter -.sym 27459 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 27474 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 27547 o_tr_vc1$SB_IO_OUT +.sym 27292 o_smi_read_req$SB_IO_OUT +.sym 27338 o_led0$SB_IO_OUT +.sym 27395 io_pmod[3]$SB_IO_IN +.sym 27400 $io_pmod[3]$iobuf_i +.sym 27411 $io_pmod[3]$iobuf_i +.sym 27429 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 27444 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 27458 o_led0$SB_IO_OUT +.sym 27459 i_rst_b_SB_LUT4_I3_O +.sym 27470 i_rst_b_SB_LUT4_I3_O +.sym 27519 $io_pmod[2]$iobuf_i +.sym 27522 $io_pmod[1]$iobuf_i +.sym 27531 $io_pmod[1]$iobuf_i +.sym 27537 $io_pmod[2]$iobuf_i +.sym 27549 $io_pmod[0]$iobuf_i +.sym 27573 $io_pmod[0]$iobuf_i .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27600 o_rx_h_tx_l$SB_IO_OUT +.sym 27595 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27624 o_tr_vc2$SB_IO_OUT -.sym 27629 o_tr_vc1$SB_IO_OUT +.sym 27617 o_tr_vc2$SB_IO_OUT +.sym 27623 o_tr_vc1$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27646 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27647 o_tr_vc1_b$SB_IO_OUT -.sym 27683 w_rx_09_fifo_data[5] -.sym 27684 w_rx_24_fifo_data[5] -.sym 27685 o_led1$SB_IO_OUT -.sym 27692 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27693 w_rx_09_fifo_data[7] -.sym 27700 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27701 w_rx_09_fifo_data[9] -.sym 27708 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27709 w_rx_09_fifo_data[5] -.sym 27716 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27717 w_rx_09_fifo_data[6] -.sym 27723 w_rx_09_fifo_data[6] -.sym 27724 w_rx_24_fifo_data[6] -.sym 27725 o_led1$SB_IO_OUT -.sym 27728 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27729 w_rx_09_fifo_data[10] -.sym 27740 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27741 w_rx_09_fifo_data[8] -.sym 27744 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27745 w_rx_09_fifo_data[4] -.sym 27748 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27749 w_rx_09_fifo_data[11] -.sym 27751 w_rx_09_fifo_data[15] -.sym 27752 w_rx_24_fifo_data[15] -.sym 27753 o_led1$SB_IO_OUT -.sym 27756 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27757 w_rx_09_fifo_data[12] -.sym 27760 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27761 w_rx_09_fifo_data[14] -.sym 27764 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27765 w_rx_09_fifo_data[13] -.sym 27768 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27769 w_rx_09_fifo_data[15] -.sym 27780 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27781 w_rx_24_fifo_data[29] -.sym 27783 w_rx_09_fifo_data[31] -.sym 27784 w_rx_24_fifo_data[31] -.sym 27785 o_led1$SB_IO_OUT -.sym 27792 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27793 w_rx_24_fifo_data[21] -.sym 27796 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27797 w_rx_24_fifo_data[23] -.sym 27800 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27801 w_rx_24_fifo_data[27] -.sym 27804 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27805 w_rx_24_fifo_data[18] -.sym 27808 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 27809 w_rx_24_fifo_data[25] -.sym 27812 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27813 w_rx_09_fifo_data[25] -.sym 27816 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27817 w_rx_09_fifo_data[29] -.sym 27819 w_rx_09_fifo_data[20] -.sym 27820 w_rx_24_fifo_data[20] -.sym 27821 o_led1$SB_IO_OUT -.sym 27823 w_rx_09_fifo_data[27] -.sym 27824 w_rx_24_fifo_data[27] -.sym 27825 o_led1$SB_IO_OUT -.sym 27827 w_rx_09_fifo_data[25] -.sym 27828 w_rx_24_fifo_data[25] -.sym 27829 o_led1$SB_IO_OUT -.sym 27831 w_rx_09_fifo_data[21] -.sym 27832 w_rx_24_fifo_data[21] -.sym 27833 o_led1$SB_IO_OUT -.sym 27836 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27837 w_rx_09_fifo_data[27] -.sym 27839 w_rx_09_fifo_data[23] -.sym 27840 w_rx_24_fifo_data[23] -.sym 27841 o_led1$SB_IO_OUT -.sym 27844 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27845 w_rx_09_fifo_data[19] -.sym 27848 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27849 w_rx_09_fifo_data[17] -.sym 27852 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27853 w_rx_09_fifo_data[21] -.sym 27860 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27861 w_rx_09_fifo_data[23] -.sym 27864 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27865 w_rx_09_fifo_data[2] -.sym 27869 o_iq_tx_clk_p$SB_IO_OUT -.sym 27872 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27873 w_rx_09_fifo_data[18] -.sym 27880 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27881 w_rx_09_fifo_data[0] -.sym 27884 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27885 w_rx_09_fifo_data[1] -.sym 27891 w_rx_09_fifo_data[16] -.sym 27892 w_rx_24_fifo_data[16] -.sym 27893 o_led1$SB_IO_OUT -.sym 27896 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27897 w_rx_09_fifo_data[3] -.sym 27900 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27901 w_rx_09_fifo_data[16] -.sym 27907 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 27912 rx_fifo.wr_addr[2] -.sym 27916 rx_fifo.wr_addr[3] -.sym 27917 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 27920 rx_fifo.wr_addr[4] -.sym 27921 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 27924 rx_fifo.wr_addr[5] -.sym 27925 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 27928 rx_fifo.wr_addr[6] -.sym 27929 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 27932 rx_fifo.wr_addr[7] -.sym 27933 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 27936 rx_fifo.wr_addr[8] -.sym 27937 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 27940 rx_fifo.wr_addr[9] -.sym 27941 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 27944 rx_fifo.rd_addr_gray_wr_r[5] -.sym 27945 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 27946 rx_fifo.rd_addr_gray_wr[7] -.sym 27951 rx_fifo.rd_addr_gray_wr_r[7] -.sym 27952 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 27953 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 27955 w_rx_09_fifo_data[1] -.sym 27956 w_rx_24_fifo_data[1] -.sym 27957 o_led1$SB_IO_OUT -.sym 27958 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 27959 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 27960 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 27961 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 27962 rx_fifo.rd_addr_gray_wr[6] -.sym 27966 rx_fifo.rd_addr_gray_wr[3] -.sym 27971 rx_fifo.wr_addr[0] -.sym 27976 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 27977 rx_fifo.wr_addr[0] -.sym 27980 rx_fifo.wr_addr[2] -.sym 27981 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 27984 rx_fifo.wr_addr[3] -.sym 27985 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 27988 rx_fifo.wr_addr[4] -.sym 27989 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 27992 rx_fifo.wr_addr[5] -.sym 27993 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 27996 rx_fifo.wr_addr[6] -.sym 27997 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 28000 rx_fifo.wr_addr[7] -.sym 28001 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 28004 rx_fifo.wr_addr[8] -.sym 28005 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 28008 rx_fifo.wr_addr[9] -.sym 28009 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 28010 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 28011 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28012 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28013 w_lvds_rx_09_d1 -.sym 28016 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 28017 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 28019 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 28020 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 28021 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 28022 w_lvds_rx_09_d0 -.sym 28026 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 28027 rx_fifo.rd_addr_gray_wr_r[7] -.sym 28028 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 28029 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 28031 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] -.sym 28032 w_rx_fifo_push -.sym 28033 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] -.sym 28034 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 28035 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 28036 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 28037 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 28040 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 28041 i_rst_b$SB_IO_IN -.sym 28042 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 28046 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 28050 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28051 w_lvds_rx_09_d1 -.sym 28052 w_lvds_rx_09_d0 -.sym 28053 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28054 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 28060 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 28061 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 28064 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 28065 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 28066 rx_fifo.wr_addr[9] -.sym 28080 w_lvds_rx_09_d0 -.sym 28081 w_lvds_rx_09_d1 -.sym 28082 rx_fifo.wr_addr_gray[7] -.sym 28086 rx_fifo.wr_addr_gray[8] -.sym 28094 rx_fifo.wr_addr_gray[4] -.sym 28102 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28103 w_lvds_rx_24_d0 -.sym 28104 w_lvds_rx_24_d1 -.sym 28105 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28109 w_lvds_rx_24_d1 -.sym 28111 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28112 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28113 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 28121 w_lvds_rx_24_d0 -.sym 28128 w_lvds_rx_24_d1 -.sym 28129 w_lvds_rx_24_d0 -.sym 28159 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28160 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 28161 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28195 w_rx_09_fifo_data[9] -.sym 28196 w_rx_24_fifo_data[9] -.sym 28197 o_led1$SB_IO_OUT -.sym 28219 w_rx_09_fifo_data[7] -.sym 28220 w_rx_24_fifo_data[7] -.sym 28221 o_led1$SB_IO_OUT -.sym 28223 w_rx_09_fifo_data[8] -.sym 28224 w_rx_24_fifo_data[8] +.sym 27650 o_tr_vc1_b$SB_IO_OUT +.sym 27653 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27732 w_rx_09_fifo_data[10] +.sym 27733 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27740 w_rx_09_fifo_data[14] +.sym 27741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27744 w_rx_09_fifo_data[12] +.sym 27745 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27768 w_rx_09_fifo_data[18] +.sym 27769 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27772 w_rx_09_fifo_data[16] +.sym 27773 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27776 w_rx_09_fifo_data[20] +.sym 27777 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27788 w_rx_09_fifo_data[9] +.sym 27789 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27800 w_rx_09_fifo_data[7] +.sym 27801 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27804 w_rx_09_fifo_data[22] +.sym 27805 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27807 w_rx_09_fifo_data[9] +.sym 27808 w_rx_24_fifo_data[9] +.sym 27809 o_led1$SB_IO_OUT +.sym 27812 w_rx_24_fifo_data[7] +.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27816 w_rx_24_fifo_data[9] +.sym 27817 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27820 w_rx_24_fifo_data[10] +.sym 27821 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27824 w_rx_24_fifo_data[6] +.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27828 w_rx_24_fifo_data[11] +.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27832 w_rx_24_fifo_data[8] +.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27837 o_iq_tx_clk_p$SB_IO_OUT +.sym 27840 w_rx_24_fifo_data[5] +.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27844 w_rx_09_fifo_data[6] +.sym 27845 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27848 w_rx_09_fifo_data[4] +.sym 27849 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27852 w_rx_09_fifo_data[0] +.sym 27853 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27856 w_rx_09_fifo_data[1] +.sym 27857 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27859 w_rx_24_fifo_data[6] +.sym 27860 w_rx_09_fifo_data[6] +.sym 27861 o_led1$SB_IO_OUT +.sym 27864 w_rx_09_fifo_data[2] +.sym 27865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27867 w_rx_24_fifo_data[10] +.sym 27868 w_rx_09_fifo_data[10] +.sym 27869 o_led1$SB_IO_OUT +.sym 27872 w_rx_09_fifo_data[8] +.sym 27873 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 27897 w_lvds_rx_24_d0 +.sym 27903 w_rx_24_fifo_data[8] +.sym 27904 w_rx_09_fifo_data[8] +.sym 27905 o_led1$SB_IO_OUT +.sym 27916 rx_fifo.rd_addr_gray_wr_r[8] +.sym 27917 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 27922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 27939 rx_fifo.wr_addr[1] +.sym 27944 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 27945 rx_fifo.wr_addr[1] +.sym 27948 rx_fifo.wr_addr[3] +.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 27952 rx_fifo.wr_addr[4] +.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 27956 rx_fifo.wr_addr[5] +.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 27960 rx_fifo.wr_addr[6] +.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 27964 rx_fifo.wr_addr[7] +.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 27968 rx_fifo.wr_addr[8] +.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 27972 rx_fifo.wr_addr[9] +.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 +.sym 27974 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.sym 27982 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 27986 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 27990 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 27994 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 28003 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 28004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28005 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28008 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28009 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28012 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 28013 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28014 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.sym 28015 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.sym 28016 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.sym 28017 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.sym 28018 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 28019 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28020 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.sym 28021 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 28024 i_rst_b$SB_IO_IN +.sym 28025 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 28026 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 28027 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 28028 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 28029 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 28030 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 28031 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.sym 28032 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.sym 28033 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.sym 28034 w_lvds_rx_09_d0 +.sym 28035 w_lvds_rx_09_d1 +.sym 28036 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28037 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28038 rx_fifo.rd_addr_gray_wr[9] +.sym 28042 w_lvds_rx_09_d0 +.sym 28043 w_lvds_rx_09_d1 +.sym 28044 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28045 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 28051 rx_fifo.wr_addr[1] +.sym 28052 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28055 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 28056 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 28057 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 28058 w_rx_fifo_full +.sym 28059 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.sym 28060 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 28061 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28062 rx_fifo.rd_addr_gray_wr[0] +.sym 28066 w_lvds_rx_24_d1 +.sym 28067 w_lvds_rx_24_d0 +.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28071 w_lvds_rx_09_d1 +.sym 28072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 28073 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 28076 i_rst_b$SB_IO_IN +.sym 28077 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 28080 w_lvds_rx_24_d1 +.sym 28081 w_lvds_rx_24_d0 +.sym 28083 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28084 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 28085 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28088 w_lvds_rx_09_d0 +.sym 28089 w_lvds_rx_09_d1 +.sym 28090 w_lvds_rx_09_d0 +.sym 28094 w_lvds_rx_24_d1 +.sym 28095 w_lvds_rx_24_d0 +.sym 28096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28097 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28100 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28101 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 28104 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 28105 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28107 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28108 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28109 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28110 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] +.sym 28114 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28115 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28116 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28117 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28136 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28137 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28142 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28147 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28148 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28149 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28154 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28156 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28157 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28200 w_rx_09_fifo_data[11] +.sym 28201 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28208 w_rx_09_fifo_data[13] +.sym 28209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28211 w_rx_09_fifo_data[13] +.sym 28212 w_rx_24_fifo_data[13] +.sym 28213 o_led1$SB_IO_OUT +.sym 28216 w_rx_09_fifo_data[15] +.sym 28217 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28223 w_rx_09_fifo_data[15] +.sym 28224 w_rx_24_fifo_data[15] .sym 28225 o_led1$SB_IO_OUT -.sym 28227 w_rx_09_fifo_data[14] -.sym 28228 w_rx_24_fifo_data[14] -.sym 28229 o_led1$SB_IO_OUT -.sym 28235 w_rx_09_fifo_data[10] -.sym 28236 w_rx_24_fifo_data[10] -.sym 28237 o_led1$SB_IO_OUT -.sym 28240 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28241 w_rx_24_fifo_data[10] -.sym 28243 w_rx_09_fifo_data[11] -.sym 28244 w_rx_24_fifo_data[11] -.sym 28245 o_led1$SB_IO_OUT -.sym 28248 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28249 w_rx_24_fifo_data[11] -.sym 28255 w_rx_09_fifo_data[13] +.sym 28228 w_rx_24_fifo_data[12] +.sym 28229 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28232 w_rx_24_fifo_data[14] +.sym 28233 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28236 w_rx_24_fifo_data[15] +.sym 28237 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28240 w_rx_24_fifo_data[20] +.sym 28241 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28244 w_rx_24_fifo_data[16] +.sym 28245 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28247 w_rx_09_fifo_data[14] +.sym 28248 w_rx_24_fifo_data[14] +.sym 28249 o_led1$SB_IO_OUT +.sym 28251 w_rx_09_fifo_data[12] +.sym 28252 w_rx_24_fifo_data[12] +.sym 28253 o_led1$SB_IO_OUT .sym 28256 w_rx_24_fifo_data[13] -.sym 28257 o_led1$SB_IO_OUT -.sym 28260 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28261 w_rx_24_fifo_data[4] -.sym 28264 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28265 w_rx_24_fifo_data[7] -.sym 28268 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28269 w_rx_24_fifo_data[3] -.sym 28272 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28273 w_rx_24_fifo_data[15] -.sym 28276 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28277 w_rx_24_fifo_data[6] -.sym 28280 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28281 w_rx_24_fifo_data[12] -.sym 28284 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28285 w_rx_24_fifo_data[9] -.sym 28288 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28289 w_rx_24_fifo_data[8] -.sym 28290 tx_fifo.wr_addr_gray_rd[7] -.sym 28294 tx_fifo.wr_addr_gray_rd[1] -.sym 28299 w_rx_09_fifo_data[17] -.sym 28300 w_rx_24_fifo_data[17] +.sym 28257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28260 w_rx_09_fifo_data[23] +.sym 28261 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28264 w_rx_09_fifo_data[17] +.sym 28265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28268 w_rx_09_fifo_data[19] +.sym 28269 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28271 w_rx_24_fifo_data[22] +.sym 28272 w_rx_09_fifo_data[22] +.sym 28273 o_led1$SB_IO_OUT +.sym 28275 w_rx_09_fifo_data[18] +.sym 28276 w_rx_24_fifo_data[18] +.sym 28277 o_led1$SB_IO_OUT +.sym 28280 w_rx_09_fifo_data[21] +.sym 28281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28283 w_rx_09_fifo_data[16] +.sym 28284 w_rx_24_fifo_data[16] +.sym 28285 o_led1$SB_IO_OUT +.sym 28287 w_rx_09_fifo_data[17] +.sym 28288 w_rx_24_fifo_data[17] +.sym 28289 o_led1$SB_IO_OUT +.sym 28292 w_rx_24_fifo_data[22] +.sym 28293 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28296 w_rx_24_fifo_data[24] +.sym 28297 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28299 w_rx_24_fifo_data[19] +.sym 28300 w_rx_09_fifo_data[19] .sym 28301 o_led1$SB_IO_OUT -.sym 28310 tx_fifo.wr_addr_gray_rd[2] -.sym 28315 w_rx_09_fifo_data[4] -.sym 28316 w_rx_24_fifo_data[4] -.sym 28317 o_led1$SB_IO_OUT -.sym 28319 w_rx_09_fifo_data[12] -.sym 28320 w_rx_24_fifo_data[12] -.sym 28321 o_led1$SB_IO_OUT -.sym 28324 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28325 w_rx_24_fifo_data[2] -.sym 28328 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28329 w_rx_24_fifo_data[20] -.sym 28332 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28333 w_rx_24_fifo_data[19] -.sym 28336 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28337 w_rx_24_fifo_data[22] -.sym 28340 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28341 w_rx_24_fifo_data[17] -.sym 28344 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28345 w_rx_24_fifo_data[24] -.sym 28348 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28349 w_rx_24_fifo_data[26] -.sym 28351 w_rx_09_fifo_data[22] -.sym 28352 w_rx_24_fifo_data[22] -.sym 28353 o_led1$SB_IO_OUT -.sym 28356 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28357 w_rx_09_fifo_data[20] -.sym 28360 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28361 w_rx_09_fifo_data[24] -.sym 28363 w_rx_09_fifo_data[28] -.sym 28364 w_rx_24_fifo_data[28] -.sym 28365 o_led1$SB_IO_OUT -.sym 28367 w_rx_09_fifo_data[26] -.sym 28368 w_rx_24_fifo_data[26] +.sym 28304 w_rx_24_fifo_data[17] +.sym 28305 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28307 w_rx_09_fifo_data[24] +.sym 28308 w_rx_24_fifo_data[24] +.sym 28309 o_led1$SB_IO_OUT +.sym 28312 w_rx_24_fifo_data[19] +.sym 28313 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28316 w_rx_24_fifo_data[28] +.sym 28317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28320 w_rx_24_fifo_data[26] +.sym 28321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28323 w_rx_09_fifo_data[11] +.sym 28324 w_rx_24_fifo_data[11] +.sym 28325 o_led1$SB_IO_OUT +.sym 28328 w_rx_09_fifo_data[3] +.sym 28329 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28331 w_rx_09_fifo_data[5] +.sym 28332 w_rx_24_fifo_data[5] +.sym 28333 o_led1$SB_IO_OUT +.sym 28335 w_rx_09_fifo_data[7] +.sym 28336 w_rx_24_fifo_data[7] +.sym 28337 o_led1$SB_IO_OUT +.sym 28339 w_rx_24_fifo_data[26] +.sym 28340 w_rx_09_fifo_data[26] +.sym 28341 o_led1$SB_IO_OUT +.sym 28344 w_rx_09_fifo_data[24] +.sym 28345 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28348 w_rx_09_fifo_data[26] +.sym 28349 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28352 w_rx_09_fifo_data[5] +.sym 28353 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28356 w_rx_24_fifo_data[0] +.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28359 w_rx_24_fifo_data[2] +.sym 28360 w_rx_09_fifo_data[2] +.sym 28361 o_led1$SB_IO_OUT +.sym 28364 w_rx_24_fifo_data[3] +.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28367 w_rx_09_fifo_data[3] +.sym 28368 w_rx_24_fifo_data[3] .sym 28369 o_led1$SB_IO_OUT -.sym 28372 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28373 w_rx_09_fifo_data[22] -.sym 28376 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28377 w_rx_09_fifo_data[28] -.sym 28379 w_rx_09_fifo_data[19] -.sym 28380 w_rx_24_fifo_data[19] -.sym 28381 o_led1$SB_IO_OUT -.sym 28384 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28385 w_rx_09_fifo_data[26] -.sym 28391 w_rx_09_fifo_data[2] -.sym 28392 w_rx_24_fifo_data[2] -.sym 28393 o_led1$SB_IO_OUT -.sym 28396 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28397 w_rx_24_fifo_data[14] -.sym 28400 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28401 w_rx_24_fifo_data[16] -.sym 28404 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28405 w_rx_24_fifo_data[0] -.sym 28407 w_rx_09_fifo_data[3] -.sym 28408 w_rx_24_fifo_data[3] -.sym 28409 o_led1$SB_IO_OUT -.sym 28412 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28413 w_rx_24_fifo_data[1] -.sym 28415 w_rx_09_fifo_data[18] -.sym 28416 w_rx_24_fifo_data[18] -.sym 28417 o_led1$SB_IO_OUT -.sym 28418 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 28434 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 28438 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 28443 w_rx_09_fifo_data[0] -.sym 28444 w_rx_24_fifo_data[0] -.sym 28445 o_led1$SB_IO_OUT -.sym 28450 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 28454 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 28458 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 28462 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 28468 rx_fifo.rd_addr_gray_wr_r[2] -.sym 28469 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 28470 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 28477 rx_fifo.wr_addr[0] -.sym 28480 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 28481 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 28484 rx_fifo.wr_addr[2] -.sym 28485 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 28486 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 28487 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 28488 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 28489 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 28492 rx_fifo.rd_addr_gray_wr_r[5] -.sym 28493 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 28494 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 28495 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28496 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] -.sym 28497 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.sym 28498 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] -.sym 28499 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -.sym 28500 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -.sym 28501 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -.sym 28502 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] -.sym 28503 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 28504 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 28505 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 28506 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] -.sym 28507 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 28508 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 28509 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] -.sym 28510 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] -.sym 28511 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] -.sym 28512 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] -.sym 28513 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] -.sym 28514 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] -.sym 28515 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 28516 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 28517 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 28520 rx_fifo.rd_addr_gray_wr_r[2] -.sym 28521 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 28522 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] -.sym 28523 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 28524 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 28525 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -.sym 28528 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.sym 28529 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 28532 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28533 w_rx_24_fifo_data[28] -.sym 28536 rx_fifo.wr_addr[0] -.sym 28537 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 28538 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 28539 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28540 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 28541 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 28544 rx_fifo.wr_addr[0] -.sym 28545 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28547 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 28548 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28549 w_rx_fifo_full -.sym 28550 w_rx_fifo_push -.sym 28551 rx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 28552 rx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 28553 rx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 28555 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 28556 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 28557 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 28560 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 28564 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.sym 28565 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 28570 rx_fifo.rd_addr_gray_wr[2] -.sym 28574 rx_fifo.rd_addr_gray_wr[4] -.sym 28589 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 28591 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28592 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28593 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 28595 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28596 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 28597 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.sym 28604 w_rx_fifo_push -.sym 28605 i_rst_b$SB_IO_IN -.sym 28607 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28608 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 28609 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28618 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28619 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28620 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28621 w_lvds_rx_24_d1 -.sym 28625 w_lvds_rx_24_d0 -.sym 28643 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28644 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28645 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28650 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.sym 28651 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28652 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28653 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28654 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28655 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28656 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 28657 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28659 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28660 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28661 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 28662 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28663 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28664 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28665 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28666 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 28667 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 28668 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 28669 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28675 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28679 lvds_rx_24_inst.r_phase_count[1] -.sym 28680 $PACKER_VCC_NET -.sym 28681 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28682 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28684 $PACKER_VCC_NET -.sym 28685 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 28689 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28693 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28706 tx_fifo.wr_addr_gray[3] -.sym 28710 tx_fifo.wr_addr_gray[7] -.sym 28718 tx_fifo.wr_addr_gray[6] -.sym 28726 tx_fifo.wr_addr_gray[1] -.sym 28730 tx_fifo.wr_addr_gray[2] -.sym 28744 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 28745 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 28750 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 28758 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 28762 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 28766 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 28770 tx_fifo.wr_addr_gray_rd[5] -.sym 28778 tx_fifo.wr_addr_gray_rd[6] -.sym 28782 tx_fifo.wr_addr_gray_rd[3] -.sym 28787 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 28788 tx_fifo.rd_addr[6] -.sym 28789 tx_fifo.rd_addr[7] -.sym 28794 tx_fifo.wr_addr_gray_rd[4] -.sym 28808 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28809 w_rx_24_fifo_data[13] -.sym 28812 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28813 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 28816 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 28817 w_rx_24_fifo_data[5] -.sym 28822 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] -.sym 28823 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 28824 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 28825 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 28827 w_rx_09_fifo_data[24] -.sym 28828 w_rx_24_fifo_data[24] -.sym 28829 o_led1$SB_IO_OUT -.sym 28858 tx_fifo.wr_addr_gray_rd[0] -.sym 28863 w_rx_09_fifo_data[29] -.sym 28864 w_rx_24_fifo_data[29] -.sym 28865 o_led1$SB_IO_OUT -.sym 28866 w_rx_fifo_pulled_data[18] -.sym 28870 w_rx_fifo_pulled_data[15] -.sym 28874 w_rx_fifo_pulled_data[6] -.sym 28879 w_rx_09_fifo_data[30] -.sym 28880 w_rx_24_fifo_data[30] -.sym 28881 o_led1$SB_IO_OUT -.sym 28882 w_rx_fifo_pulled_data[10] -.sym 28886 w_rx_fifo_pulled_data[4] -.sym 28890 w_rx_fifo_pulled_data[13] -.sym 28894 w_rx_fifo_pulled_data[8] -.sym 28914 w_rx_fifo_pulled_data[19] -.sym 28930 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 28934 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28938 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 28946 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 28950 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 28954 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 28964 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 28965 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 28969 rx_fifo.rd_addr[0] -.sym 28972 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28973 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 28977 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 28982 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28986 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 28992 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 28993 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 28994 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 29000 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29001 rx_fifo.rd_addr[3] -.sym 29004 rx_fifo.rd_addr[0] -.sym 29005 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 29006 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 29014 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 29015 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 29016 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 29017 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 29018 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 29019 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 29020 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 29021 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 29026 rx_fifo.rd_addr_gray[5] -.sym 29030 rx_fifo.rd_addr_gray[1] -.sym 29034 rx_fifo.rd_addr_gray[4] -.sym 29038 rx_fifo.rd_addr_gray[3] -.sym 29042 rx_fifo.rd_addr_gray[0] -.sym 29046 rx_fifo.rd_addr_gray[6] -.sym 29050 rx_fifo.rd_addr_gray[2] -.sym 29054 rx_fifo.rd_addr[9] -.sym 29060 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 29061 rx_fifo.rd_addr[6] -.sym 29067 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 29068 rx_fifo.rd_addr[6] -.sym 29069 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 29070 rx_fifo.rd_addr_gray_wr[0] -.sym 29074 rx_fifo.rd_addr_gray_wr[5] -.sym 29078 rx_fifo.rd_addr_gray[7] -.sym 29082 rx_fifo.rd_addr_gray_wr[9] -.sym 29086 rx_fifo.rd_addr_gray[8] -.sym 29090 rx_fifo.wr_addr_gray[6] -.sym 29102 rx_fifo.wr_addr_gray_rd[7] -.sym 29106 rx_fifo.wr_addr_gray[3] -.sym 29110 rx_fifo.wr_addr_gray_rd[5] -.sym 29118 rx_fifo.wr_addr_gray_rd[6] -.sym 29128 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.sym 29129 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 29130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 29136 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -.sym 29137 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -.sym 29138 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.sym 29142 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 29154 rx_fifo.rd_addr_gray_wr[1] -.sym 29170 rx_fifo.rd_addr_gray_wr[8] -.sym 29221 w_smi_data_output[6] -.sym 29223 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 29224 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29225 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29230 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 29247 smi_ctrl_ins.tx_reg_state[0] -.sym 29248 smi_ctrl_ins.tx_reg_state[3] -.sym 29249 i_rst_b$SB_IO_IN -.sym 29250 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 29254 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 29258 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 29262 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29266 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 29273 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 29274 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 29278 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29282 tx_fifo.rd_addr_gray[7] -.sym 29286 tx_fifo.rd_addr_gray_wr[6] -.sym 29290 tx_fifo.rd_addr_gray[2] -.sym 29294 tx_fifo.rd_addr_gray[4] -.sym 29298 tx_fifo.rd_addr_gray[3] -.sym 29302 tx_fifo.rd_addr_gray[6] -.sym 29306 tx_fifo.rd_addr_gray[5] -.sym 29310 tx_fifo.rd_addr_gray[0] -.sym 29316 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 29317 tx_fifo.rd_addr[7] -.sym 29319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 29320 tx_fifo.rd_addr[5] -.sym 29321 tx_fifo.rd_addr[6] -.sym 29322 w_rx_fifo_pulled_data[5] -.sym 29333 i_rst_b$SB_IO_IN -.sym 29338 w_rx_fifo_pulled_data[9] -.sym 29342 w_rx_fifo_pulled_data[1] -.sym 29358 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 29359 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 29360 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 29361 tx_fifo.empty_o_SB_LUT4_I3_O[3] -.sym 29365 i_rst_b$SB_IO_IN -.sym 29369 i_rst_b$SB_IO_IN -.sym 29372 smi_ctrl_ins.int_cnt_rx[4] -.sym 29373 smi_ctrl_ins.int_cnt_rx[3] -.sym 29376 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 29377 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 29378 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] -.sym 29379 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] -.sym 29380 smi_ctrl_ins.int_cnt_rx[4] -.sym 29381 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] -.sym 29382 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] -.sym 29383 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] -.sym 29384 smi_ctrl_ins.int_cnt_rx[4] -.sym 29385 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] -.sym 29386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] -.sym 29387 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] -.sym 29388 smi_ctrl_ins.int_cnt_rx[4] -.sym 29389 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] -.sym 29390 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 29391 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 29392 smi_ctrl_ins.int_cnt_rx[4] -.sym 29393 smi_ctrl_ins.int_cnt_rx[3] -.sym 29394 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] -.sym 29395 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -.sym 29396 smi_ctrl_ins.int_cnt_rx[4] -.sym 29397 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] -.sym 29402 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -.sym 29403 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -.sym 29404 smi_ctrl_ins.int_cnt_rx[4] -.sym 29405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] -.sym 29410 w_rx_fifo_pulled_data[3] -.sym 29414 w_rx_fifo_pulled_data[26] -.sym 29418 w_rx_fifo_pulled_data[0] -.sym 29422 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 29423 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 29424 smi_ctrl_ins.int_cnt_rx[4] -.sym 29425 smi_ctrl_ins.int_cnt_rx[3] -.sym 29426 w_rx_fifo_pulled_data[25] -.sym 29430 w_rx_fifo_pulled_data[17] -.sym 29434 w_rx_fifo_pulled_data[2] -.sym 29438 w_rx_fifo_pulled_data[16] -.sym 29443 rx_fifo.rd_addr[0] -.sym 29448 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 29449 rx_fifo.rd_addr[0] -.sym 29452 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 29453 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 29456 rx_fifo.rd_addr[3] -.sym 29457 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 29460 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -.sym 29461 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 29464 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 29465 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 29468 rx_fifo.rd_addr[6] -.sym 29469 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 29472 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 29473 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 29476 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 29477 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 29480 rx_fifo.rd_addr[9] -.sym 29481 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 29488 rx_fifo.rd_addr[0] -.sym 29489 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 29493 r_counter -.sym 29498 w_ioc[1] -.sym 29499 w_ioc[4] -.sym 29500 w_ioc[3] -.sym 29501 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 29504 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 29505 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 29506 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 29507 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -.sym 29508 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] -.sym 29509 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 29510 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 29511 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 29512 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 29513 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 29518 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 29519 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -.sym 29520 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 29521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 29527 rx_fifo.empty_o_SB_LUT4_I3_I1[0] -.sym 29528 rx_fifo.empty_o_SB_LUT4_I3_I1[1] -.sym 29529 w_rx_fifo_empty -.sym 29534 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 29535 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29536 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 29537 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29538 w_rx_data[1] -.sym 29542 w_rx_data[0] -.sym 29550 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29551 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 29552 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 29553 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 29554 w_rx_data[3] -.sym 29558 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 29559 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 29560 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 29561 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 29562 w_rx_data[2] -.sym 29566 rx_fifo.wr_addr_gray_rd_r[8] -.sym 29567 rx_fifo.rd_addr[9] -.sym 29568 rx_fifo.wr_addr_gray_rd_r[9] -.sym 29569 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 29572 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 29573 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 29576 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 29577 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 29578 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 29582 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.sym 29586 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 29592 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29593 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 29594 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29598 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 29602 rx_fifo.wr_addr_gray[2] -.sym 29606 rx_fifo.wr_addr_gray_rd[0] -.sym 29610 rx_fifo.wr_addr_gray_rd[9] -.sym 29614 rx_fifo.wr_addr_gray_rd[3] -.sym 29618 rx_fifo.wr_addr_gray_rd[2] -.sym 29622 rx_fifo.wr_addr_gray_rd[4] -.sym 29630 rx_fifo.wr_addr_gray_rd[1] -.sym 29634 rx_fifo.wr_addr_gray[1] -.sym 29647 w_rx_24_fifo_push -.sym 29648 w_rx_09_fifo_push -.sym 29649 o_led1$SB_IO_OUT -.sym 29658 rx_fifo.wr_addr_gray[0] -.sym 29670 w_rx_fifo_full -.sym 29671 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 29672 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 29673 w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -.sym 29680 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 29681 w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -.sym 29732 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 29733 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 29736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.sym 29737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 29739 w_smi_data_input[7] -.sym 29740 i_rst_b$SB_IO_IN -.sym 29741 smi_ctrl_ins.tx_reg_state[1] -.sym 29742 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 29743 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.sym 29744 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 29745 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 29751 w_smi_data_input[7] -.sym 29752 smi_ctrl_ins.tx_reg_state[0] -.sym 29753 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] -.sym 29754 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] -.sym 29755 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 29756 tx_fifo.rd_addr_gray_wr_r[6] -.sym 29757 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 29759 w_smi_data_input[7] -.sym 29760 i_rst_b$SB_IO_IN -.sym 29761 smi_ctrl_ins.tx_reg_state[2] -.sym 29763 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 29768 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 29769 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 29772 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 29773 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 29776 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 29777 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 29780 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 29781 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 29784 tx_fifo.rd_addr[5] -.sym 29785 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 29788 tx_fifo.rd_addr[6] -.sym 29789 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 29792 tx_fifo.rd_addr[7] -.sym 29793 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 29796 tx_fifo.rd_addr[8] -.sym 29797 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 29800 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 29801 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 29802 w_rx_fifo_pulled_data[12] -.sym 29806 w_rx_fifo_pulled_data[7] -.sym 29812 smi_ctrl_ins.tx_reg_state[1] -.sym 29813 smi_ctrl_ins.tx_reg_state[2] -.sym 29816 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 29817 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 29818 w_rx_fifo_pulled_data[14] -.sym 29822 w_rx_fifo_pulled_data[11] -.sym 29828 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 29829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 29832 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 29833 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 29836 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29837 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29838 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 29842 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 29846 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] -.sym 29847 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 29848 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -.sym 29849 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -.sym 29852 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 29853 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29854 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 29861 w_tx_fifo_empty -.sym 29862 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 29863 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 29864 w_tx_fifo_pull -.sym 29865 w_tx_fifo_empty -.sym 29869 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 29872 tx_fifo.rd_addr[8] -.sym 29873 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 29878 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 29879 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 29880 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 29881 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 29886 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 29887 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 29888 smi_ctrl_ins.int_cnt_rx[4] -.sym 29889 smi_ctrl_ins.int_cnt_rx[3] -.sym 29890 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 29902 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 29903 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 29904 smi_ctrl_ins.int_cnt_rx[4] -.sym 29905 smi_ctrl_ins.int_cnt_rx[3] -.sym 29906 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 29907 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 29908 smi_ctrl_ins.int_cnt_rx[4] -.sym 29909 smi_ctrl_ins.int_cnt_rx[3] -.sym 29914 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 29930 tx_fifo.wr_addr[9] -.sym 29934 tx_fifo.wr_addr_gray_rd[8] -.sym 29946 tx_fifo.wr_addr_gray_rd[9] -.sym 29950 tx_fifo.wr_addr_gray[8] -.sym 29954 w_tx_fifo_full -.sym 29967 smi_ctrl_ins.r_fifo_pull_1 -.sym 29968 w_rx_fifo_empty -.sym 29969 smi_ctrl_ins.r_fifo_pull -.sym 29970 w_cs[1] -.sym 29971 w_cs[2] -.sym 29972 w_cs[3] -.sym 29973 w_cs[0] -.sym 29978 smi_ctrl_ins.o_channel -.sym 29982 w_rx_fifo_empty -.sym 29987 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 29988 w_ioc[1] -.sym 29989 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 29990 w_rx_data[0] -.sym 30006 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 30007 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 30008 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 30009 w_rx_fifo_pull -.sym 30011 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 30012 rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -.sym 30013 rx_fifo.rd_addr[3] -.sym 30016 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 30017 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 30018 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 30019 i_rst_b$SB_IO_IN -.sym 30020 w_cs[2] -.sym 30021 w_fetch -.sym 30026 rx_fifo.wr_addr_gray_rd_r[8] -.sym 30027 rx_fifo.wr_addr_gray_rd_r[9] -.sym 30028 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 30029 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 30030 r_tx_data[6] -.sym 30034 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 30035 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 30036 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 30037 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -.sym 30042 r_tx_data[1] -.sym 30046 r_tx_data[7] -.sym 30050 rx_fifo.wr_addr_gray[5] -.sym 30058 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.sym 30059 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] -.sym 30060 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 30061 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] -.sym 30062 rx_fifo.wr_addr_gray_rd[8] -.sym 30070 w_fetch -.sym 30071 w_cs[0] -.sym 30072 w_load -.sym 30073 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 30074 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 30075 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 30076 w_ioc[2] -.sym 30077 w_ioc[1] -.sym 30093 rx_fifo.rd_en_i_SB_LUT4_I2_O -.sym 30094 w_fetch -.sym 30095 w_cs[1] -.sym 30096 w_load -.sym 30097 i_button_SB_LUT4_I1_I0[0] -.sym 30101 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 30102 w_rx_data[1] -.sym 30110 w_rx_data[0] -.sym 30118 io_ctrl_ins.led1_state -.sym 30119 io_ctrl_ins.pmod_dir_state[1] -.sym 30120 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 30121 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 30122 w_rx_data[0] -.sym 30138 io_ctrl_ins.led0_state -.sym 30139 io_ctrl_ins.pmod_dir_state[0] -.sym 30140 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 30141 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 30144 w_ioc[2] -.sym 30145 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 30146 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 30147 w_fetch -.sym 30148 w_load -.sym 30149 w_cs[1] -.sym 30158 io_ctrl_ins.led0_state_SB_LUT4_I0_O[0] -.sym 30159 i_button_SB_LUT4_I1_I0[2] -.sym 30160 io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] -.sym 30161 io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] -.sym 30166 io_ctrl_ins.led1_state_SB_LUT4_I0_O[0] -.sym 30167 i_button_SB_LUT4_I1_I0[2] -.sym 30168 io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] -.sym 30169 io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] -.sym 30190 io_ctrl_ins.debug_mode[1] -.sym 30191 o_shdn_rx_lna$SB_IO_OUT -.sym 30192 w_ioc[2] -.sym 30193 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 30198 w_rx_data[0] -.sym 30220 w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.sym 30221 i_rst_b$SB_IO_IN -.sym 30225 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 30244 tx_fifo.wr_addr[0] -.sym 30245 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 30248 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.sym 30249 tx_fifo.rd_addr_gray_wr_r[2] -.sym 30250 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] -.sym 30251 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.sym 30252 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] -.sym 30253 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.sym 30254 tx_fifo.wr_addr_gray[4] -.sym 30262 tx_fifo.wr_addr_gray[0] -.sym 30266 tx_fifo.wr_addr_gray[5] -.sym 30272 i_rst_b$SB_IO_IN -.sym 30273 i_smi_swe_srw$SB_IO_IN -.sym 30275 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -.sym 30276 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.sym 30277 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 30278 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 30279 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 30280 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 30281 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] -.sym 30286 w_smi_data_input[7] -.sym 30287 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 30288 smi_ctrl_ins.tx_reg_state[3] -.sym 30289 i_rst_b$SB_IO_IN -.sym 30291 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] -.sym 30292 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 30293 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 30294 smi_ctrl_ins.w_fifo_pull_trigger -.sym 30300 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 30301 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 30302 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.sym 30303 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] -.sym 30304 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] -.sym 30305 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 30308 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 30309 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 30311 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 30312 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 30313 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 30316 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 30317 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 30318 tx_fifo.rd_addr_gray_wr[7] -.sym 30322 tx_fifo.rd_addr_gray_wr[4] -.sym 30327 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 30328 tx_fifo.rd_addr_gray_wr_r[9] -.sym 30329 w_tx_fifo_full -.sym 30330 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 30331 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 30332 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 30333 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 30335 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 30336 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 30337 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -.sym 30341 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 30342 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] -.sym 30343 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 30344 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.sym 30345 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] -.sym 30347 i_rst_b$SB_IO_IN -.sym 30348 w_smi_data_input[7] -.sym 30349 smi_ctrl_ins.tx_reg_state[0] -.sym 30352 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 30353 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 30355 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] -.sym 30356 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 30357 w_tx_fifo_pull -.sym 30358 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] -.sym 30359 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 30360 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] -.sym 30361 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] -.sym 30365 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 30366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 30367 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 30368 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 30369 tx_fifo.full_o_SB_LUT4_I3_O[3] -.sym 30370 w_rx_fifo_pulled_data[27] -.sym 30374 w_rx_fifo_pulled_data[29] -.sym 30380 w_tx_fifo_pull -.sym 30381 i_rst_b$SB_IO_IN -.sym 30382 w_rx_fifo_pulled_data[22] -.sym 30386 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 30387 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 30388 smi_ctrl_ins.int_cnt_rx[4] -.sym 30389 smi_ctrl_ins.int_cnt_rx[3] -.sym 30390 w_rx_fifo_pulled_data[30] -.sym 30394 w_rx_fifo_pulled_data[23] -.sym 30398 w_rx_fifo_pulled_data[31] -.sym 30411 smi_ctrl_ins.r_fifo_push_1 -.sym 30412 w_tx_fifo_full -.sym 30413 smi_ctrl_ins.r_fifo_push -.sym 30419 smi_ctrl_ins.int_cnt_rx[4] -.sym 30420 smi_ctrl_ins.int_cnt_rx[3] -.sym 30421 i_rst_b$SB_IO_IN -.sym 30430 smi_ctrl_ins.r_fifo_push -.sym 30441 smi_ctrl_ins.int_cnt_rx[3] -.sym 30450 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] -.sym 30473 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 30476 spi_if_ins.w_rx_data[5] -.sym 30477 spi_if_ins.w_rx_data[6] -.sym 30481 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30484 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 30485 io_ctrl_ins.o_data_out[6] -.sym 30487 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 30488 io_ctrl_ins.o_data_out[7] -.sym 30489 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 30498 w_cs[1] -.sym 30499 w_cs[3] -.sym 30500 w_cs[0] -.sym 30501 w_cs[2] -.sym 30504 spi_if_ins.w_rx_data[5] -.sym 30505 spi_if_ins.w_rx_data[6] -.sym 30506 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30507 spi_if_ins.state_if[0] -.sym 30508 spi_if_ins.state_if[1] -.sym 30509 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30512 spi_if_ins.w_rx_data[6] -.sym 30513 spi_if_ins.w_rx_data[5] -.sym 30516 spi_if_ins.w_rx_data[5] -.sym 30517 spi_if_ins.w_rx_data[6] -.sym 30518 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 30519 w_tx_data_smi[0] -.sym 30520 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 30521 w_tx_data_io -.sym 30523 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 30524 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 30525 i_rst_b$SB_IO_IN -.sym 30526 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 30527 w_tx_data_smi[1] -.sym 30528 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 30529 io_ctrl_ins.o_data_out[1] -.sym 30530 w_cs[1] -.sym 30531 w_cs[2] -.sym 30532 w_cs[3] -.sym 30533 w_cs[0] -.sym 30535 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 30536 w_tx_data_sys[1] -.sym 30537 smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] -.sym 30539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30540 spi_if_ins.state_if[0] -.sym 30541 spi_if_ins.state_if[1] -.sym 30542 w_tx_data_sys[3] -.sym 30543 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 30544 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 30545 io_ctrl_ins.o_data_out[3] -.sym 30546 w_tx_data_sys[2] -.sym 30547 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 30548 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 30549 smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] -.sym 30552 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 30553 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 30557 w_cs[0] -.sym 30558 w_tx_data_io_SB_LUT4_I3_O[0] -.sym 30559 w_tx_data_io_SB_LUT4_I3_O[1] -.sym 30560 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 30561 w_tx_data_io_SB_LUT4_I3_O[3] -.sym 30562 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] -.sym 30563 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] -.sym 30564 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] -.sym 30565 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] -.sym 30570 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.sym 30572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.sym 30573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.sym 30576 w_rx_fifo_pull -.sym 30577 i_rst_b$SB_IO_IN -.sym 30578 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30584 w_ioc[4] -.sym 30585 w_ioc[3] -.sym 30586 w_fetch -.sym 30587 w_cs[2] -.sym 30588 w_load -.sym 30589 i_button_SB_LUT4_I1_I0[0] -.sym 30591 spi_if_ins.spi.r_tx_byte[2] -.sym 30592 spi_if_ins.spi.r_tx_byte[6] -.sym 30593 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30607 i_rst_b$SB_IO_IN +.sym 28372 w_rx_24_fifo_data[4] +.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28376 w_rx_24_fifo_data[1] +.sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28380 w_rx_24_fifo_data[2] +.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28383 w_rx_24_fifo_data[4] +.sym 28384 w_rx_09_fifo_data[4] +.sym 28385 o_led1$SB_IO_OUT +.sym 28386 rx_fifo.rd_addr[9] +.sym 28422 rx_fifo.wr_addr[9] +.sym 28430 rx_fifo.wr_addr_gray_rd[9] +.sym 28435 w_rx_24_fifo_data[1] +.sym 28436 w_rx_09_fifo_data[1] +.sym 28437 o_led1$SB_IO_OUT +.sym 28452 rx_fifo.rd_addr_gray_wr_r[5] +.sym 28453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 28455 w_rx_24_fifo_data[0] +.sym 28456 w_rx_09_fifo_data[0] +.sym 28457 o_led1$SB_IO_OUT +.sym 28459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 28460 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 28461 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.sym 28462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 28463 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 28464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] +.sym 28465 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] +.sym 28467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 28468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.sym 28469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.sym 28471 io_pmod[7]$SB_IO_IN +.sym 28472 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 28473 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 28475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.sym 28476 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.sym 28477 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.sym 28479 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28480 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] +.sym 28481 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 28483 rx_fifo.wr_addr[0] +.sym 28488 rx_fifo.wr_addr[1] +.sym 28489 rx_fifo.wr_addr[0] +.sym 28492 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 28496 rx_fifo.wr_addr[3] +.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 28500 rx_fifo.wr_addr[4] +.sym 28501 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 28504 rx_fifo.wr_addr[5] +.sym 28505 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28508 rx_fifo.wr_addr[6] +.sym 28509 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28512 rx_fifo.wr_addr[7] +.sym 28513 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 28516 rx_fifo.wr_addr[8] +.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 28520 rx_fifo.wr_addr[9] +.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28528 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28529 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28532 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28533 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28537 rx_fifo.wr_addr[0] +.sym 28540 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28543 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28548 rx_fifo.rd_addr_gray_wr_r[5] +.sym 28549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 28550 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28551 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 28552 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28553 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28554 rx_fifo.rd_addr_gray_wr[8] +.sym 28558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 28559 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 28560 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 28562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] +.sym 28563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 28564 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28566 rx_fifo.rd_addr_gray_wr[5] +.sym 28570 rx_fifo.rd_addr_gray[8] +.sym 28574 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28576 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28579 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.sym 28580 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 28581 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28586 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 28587 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 28588 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 28589 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 28593 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.sym 28594 w_lvds_rx_24_d1 +.sym 28595 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 28596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28597 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28603 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28604 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28605 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] +.sym 28611 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28614 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28615 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 28616 $PACKER_VCC_NET +.sym 28617 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28618 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28619 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28620 $PACKER_VCC_NET +.sym 28621 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 28622 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28623 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28624 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28625 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28629 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28633 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28635 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 28636 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 28637 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 28640 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 28641 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] +.sym 28643 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 28646 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28647 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 28648 $PACKER_VCC_NET +.sym 28649 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.sym 28650 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28651 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 28652 $PACKER_VCC_NET +.sym 28653 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 +.sym 28654 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28656 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28657 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28665 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28666 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 28667 rx_fifo.full_o_SB_LUT4_I1_I3[0] +.sym 28668 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] +.sym 28669 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28673 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] +.sym 28706 w_rx_fifo_pulled_data[13] +.sym 28710 w_rx_fifo_pulled_data[12] +.sym 28714 w_rx_fifo_pulled_data[7] +.sym 28718 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 28719 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 28720 smi_ctrl_ins.int_cnt_rx[4] +.sym 28721 smi_ctrl_ins.int_cnt_rx[3] +.sym 28726 w_rx_fifo_pulled_data[15] +.sym 28730 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 28731 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 28732 smi_ctrl_ins.int_cnt_rx[4] +.sym 28733 smi_ctrl_ins.int_cnt_rx[3] +.sym 28734 w_rx_fifo_pulled_data[14] +.sym 28740 w_rx_24_fifo_data[21] +.sym 28741 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28744 w_rx_24_fifo_data[18] +.sym 28745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28748 w_rx_24_fifo_data[23] +.sym 28749 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28753 rx_fifo.wr_addr[9] +.sym 28756 w_rx_24_fifo_data[29] +.sym 28757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28760 w_rx_24_fifo_data[25] +.sym 28761 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28764 w_rx_24_fifo_data[27] +.sym 28765 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28767 w_rx_24_fifo_data[25] +.sym 28768 w_rx_09_fifo_data[25] +.sym 28769 o_led1$SB_IO_OUT +.sym 28771 w_rx_09_fifo_data[20] +.sym 28772 w_rx_24_fifo_data[20] +.sym 28773 o_led1$SB_IO_OUT +.sym 28774 w_rx_fifo_pulled_data[18] +.sym 28778 w_rx_fifo_pulled_data[16] +.sym 28782 w_rx_fifo_pulled_data[17] +.sym 28787 w_rx_24_fifo_data[23] +.sym 28788 w_rx_09_fifo_data[23] +.sym 28789 o_led1$SB_IO_OUT +.sym 28790 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 28791 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 28792 smi_ctrl_ins.int_cnt_rx[4] +.sym 28793 smi_ctrl_ins.int_cnt_rx[3] +.sym 28794 w_rx_fifo_pulled_data[19] +.sym 28799 w_rx_09_fifo_data[21] +.sym 28800 w_rx_24_fifo_data[21] +.sym 28801 o_led1$SB_IO_OUT +.sym 28802 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 28803 smi_ctrl_ins.int_cnt_rx[4] +.sym 28804 smi_ctrl_ins.int_cnt_rx[3] +.sym 28805 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 28808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 28809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 28810 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 28811 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 28812 smi_ctrl_ins.int_cnt_rx[4] +.sym 28813 smi_ctrl_ins.int_cnt_rx[3] +.sym 28816 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 28817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 28820 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 28821 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 28822 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 28823 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 28824 smi_ctrl_ins.int_cnt_rx[4] +.sym 28825 smi_ctrl_ins.int_cnt_rx[3] +.sym 28828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 28829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 28832 smi_ctrl_ins.int_cnt_rx[4] +.sym 28833 smi_ctrl_ins.int_cnt_rx[3] +.sym 28834 w_rx_fifo_pulled_data[27] +.sym 28838 w_rx_fifo_pulled_data[25] +.sym 28842 w_rx_fifo_pulled_data[4] +.sym 28846 w_rx_fifo_pulled_data[26] +.sym 28850 w_rx_fifo_pulled_data[6] +.sym 28854 w_rx_fifo_pulled_data[24] +.sym 28862 w_rx_fifo_pulled_data[5] +.sym 28874 w_rx_fifo_pulled_data[10] +.sym 28902 w_rx_fifo_pulled_data[9] +.sym 28906 w_rx_fifo_pulled_data[11] +.sym 28914 w_rx_fifo_pulled_data[8] +.sym 28918 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 28919 smi_ctrl_ins.int_cnt_rx[4] +.sym 28920 smi_ctrl_ins.int_cnt_rx[3] +.sym 28921 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 28922 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 28923 smi_ctrl_ins.int_cnt_rx[4] +.sym 28924 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 28925 smi_ctrl_ins.int_cnt_rx[3] +.sym 28926 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 28927 smi_ctrl_ins.int_cnt_rx[4] +.sym 28928 smi_ctrl_ins.int_cnt_rx[3] +.sym 28929 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 28930 w_rx_fifo_pulled_data[2] +.sym 28945 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 28950 w_rx_fifo_pulled_data[3] +.sym 28954 w_rx_fifo_pulled_data[1] +.sym 28958 w_rx_fifo_pulled_data[0] +.sym 28965 rx_fifo.rd_addr[1] +.sym 28968 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 28969 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28970 rx_fifo.rd_addr[7] +.sym 28971 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 28972 rx_fifo.rd_addr[6] +.sym 28973 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.sym 28974 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28975 rx_fifo.rd_addr[9] +.sym 28976 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 28977 rx_fifo.rd_addr[8] +.sym 28978 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28984 rx_fifo.rd_addr[5] +.sym 28985 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 28990 rx_fifo.rd_addr[5] +.sym 28991 rx_fifo.rd_addr[4] +.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 28993 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 28996 i_rst_b$SB_IO_IN +.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28998 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 28999 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 29001 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.sym 29002 rx_fifo.wr_addr_gray_rd[6] +.sym 29006 rx_fifo.wr_addr_gray_rd[7] +.sym 29010 rx_fifo.wr_addr_gray_rd[5] +.sym 29014 rx_fifo.wr_addr_gray_rd[3] +.sym 29018 rx_fifo.wr_addr_gray_rd[2] +.sym 29022 rx_fifo.wr_addr_gray_rd[4] +.sym 29026 rx_fifo.wr_addr_gray[7] +.sym 29030 rx_fifo.wr_addr_gray[2] +.sym 29035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29040 i_rst_b$SB_IO_IN +.sym 29041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 29042 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +.sym 29043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +.sym 29044 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.sym 29045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] +.sym 29048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.sym 29049 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 29050 rx_fifo.rd_addr_gray_wr_r[7] +.sym 29051 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 29052 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 29053 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 29056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] +.sym 29057 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 29058 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29062 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29070 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29074 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 29078 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 29082 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 29088 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 29089 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29094 rx_fifo.wr_addr_gray_rd[8] +.sym 29098 rx_fifo.wr_addr_gray[8] +.sym 29106 rx_fifo.wr_addr_gray[4] +.sym 29110 rx_fifo.wr_addr_gray[6] +.sym 29114 rx_fifo.wr_addr_gray[3] +.sym 29118 rx_fifo.wr_addr_gray[5] +.sym 29126 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29138 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29171 w_rx_fifo_full +.sym 29172 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 29173 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 29176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 29177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 29194 rx_fifo.rd_addr_gray_wr[7] +.sym 29222 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 29223 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 29224 smi_ctrl_ins.int_cnt_rx[4] +.sym 29225 smi_ctrl_ins.int_cnt_rx[3] +.sym 29236 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 29237 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 29244 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 29245 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 29251 w_rx_24_fifo_data[27] +.sym 29252 w_rx_09_fifo_data[27] +.sym 29253 o_led1$SB_IO_OUT +.sym 29256 w_rx_09_fifo_data[27] +.sym 29257 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29264 w_rx_09_fifo_data[28] +.sym 29265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29267 w_rx_24_fifo_data[29] +.sym 29268 w_rx_09_fifo_data[29] +.sym 29269 o_led1$SB_IO_OUT +.sym 29271 w_rx_24_fifo_data[31] +.sym 29272 lvds_rx_09_inst.o_fifo_data[31] +.sym 29273 o_led1$SB_IO_OUT +.sym 29276 w_rx_09_fifo_data[29] +.sym 29277 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29280 w_rx_09_fifo_data[25] +.sym 29281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29282 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 29283 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 29284 smi_ctrl_ins.int_cnt_rx[4] +.sym 29285 smi_ctrl_ins.int_cnt_rx[3] +.sym 29286 w_rx_fifo_pulled_data[23] +.sym 29294 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 29295 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 29296 smi_ctrl_ins.int_cnt_rx[4] +.sym 29297 smi_ctrl_ins.int_cnt_rx[3] +.sym 29302 w_rx_fifo_pulled_data[22] +.sym 29310 w_rx_fifo_pulled_data[20] +.sym 29318 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 29319 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 29320 smi_ctrl_ins.int_cnt_rx[4] +.sym 29321 smi_ctrl_ins.int_cnt_rx[3] +.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 29323 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 29324 smi_ctrl_ins.int_cnt_rx[4] +.sym 29325 smi_ctrl_ins.int_cnt_rx[3] +.sym 29328 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 29332 smi_ctrl_ins.int_cnt_rx[4] +.sym 29333 smi_ctrl_ins.int_cnt_rx[3] +.sym 29343 w_rx_09_fifo_data[30] +.sym 29344 w_rx_24_fifo_data[30] +.sym 29345 o_led1$SB_IO_OUT +.sym 29347 w_rx_24_fifo_data[28] +.sym 29348 w_rx_09_fifo_data[28] +.sym 29349 o_led1$SB_IO_OUT +.sym 29350 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29354 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29362 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 29366 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29373 rx_fifo.rd_addr[0] +.sym 29374 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 29379 rx_fifo.rd_addr[0] +.sym 29384 rx_fifo.rd_addr[1] +.sym 29385 rx_fifo.rd_addr[0] +.sym 29388 rx_fifo.rd_addr[2] +.sym 29389 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 29392 rx_fifo.rd_addr[3] +.sym 29393 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29396 rx_fifo.rd_addr[4] +.sym 29397 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29400 rx_fifo.rd_addr[5] +.sym 29401 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 29404 rx_fifo.rd_addr[6] +.sym 29405 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29408 rx_fifo.rd_addr[7] +.sym 29409 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29412 rx_fifo.rd_addr[8] +.sym 29413 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 29416 rx_fifo.rd_addr[9] +.sym 29417 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29418 w_rx_fifo_pulled_data[31] +.sym 29424 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 29426 w_rx_fifo_pulled_data[30] +.sym 29430 w_rx_fifo_pulled_data[21] +.sym 29434 w_rx_fifo_pulled_data[29] +.sym 29438 w_rx_fifo_pulled_data[28] +.sym 29442 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 29446 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 29453 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29456 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 29457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29458 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29462 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29463 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 29466 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29470 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 29471 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 29472 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 29473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 29475 rx_fifo.rd_addr[8] +.sym 29476 rx_fifo.rd_addr[7] +.sym 29477 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 29480 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29481 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 29482 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 29483 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 29484 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 29485 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 29486 rx_fifo.rd_addr[2] +.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 29488 rx_fifo.rd_addr[1] +.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 29492 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29493 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29494 rx_fifo.rd_addr[3] +.sym 29495 rx_fifo.rd_addr[2] +.sym 29496 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 29497 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] +.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 29499 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 29502 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 29508 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29511 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 29512 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 29514 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 29515 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 29516 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 29517 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 29521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 29523 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 29524 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 29525 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 29528 w_rx_fifo_full +.sym 29529 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 29544 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 29545 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29547 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] +.sym 29548 o_led1$SB_IO_OUT +.sym 29549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] +.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 29554 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 29562 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 29574 rx_fifo.rd_addr_gray[6] +.sym 29578 rx_fifo.rd_addr_gray_wr[3] +.sym 29582 rx_fifo.rd_addr_gray[0] +.sym 29586 rx_fifo.rd_addr_gray_wr[6] +.sym 29590 rx_fifo.rd_addr_gray[3] +.sym 29594 rx_fifo.rd_addr_gray[5] +.sym 29606 rx_fifo.rd_addr_gray[4] +.sym 29610 rx_fifo.rd_addr_gray[2] +.sym 29614 rx_fifo.rd_addr_gray[1] +.sym 29618 rx_fifo.rd_addr_gray_wr[2] +.sym 29626 rx_fifo.rd_addr_gray_wr[4] +.sym 29630 rx_fifo.rd_addr_gray_wr[1] +.sym 29654 r_tx_data[2] +.sym 29678 rx_fifo.wr_addr_gray[1] +.sym 29690 rx_fifo.wr_addr_gray_rd[1] +.sym 29698 rx_fifo.rd_addr_gray[7] +.sym 29709 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 29741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 29752 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 29753 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 29764 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 29766 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 29770 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.sym 29785 tx_fifo.rd_addr[0] +.sym 29786 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 29790 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 29795 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29796 tx_fifo.rd_addr[1] +.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 29798 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29802 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29807 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.sym 29808 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29809 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29814 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29815 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 29816 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29817 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29818 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 29822 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29823 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 29824 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29825 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29826 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 29827 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29828 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 29829 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29830 tx_fifo.rd_addr_gray[3] +.sym 29835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29836 tx_fifo.rd_addr[1] +.sym 29837 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 29838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 29839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.sym 29840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 29841 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 29846 tx_fifo.rd_addr_gray_wr[3] +.sym 29854 tx_fifo.rd_addr_gray[2] +.sym 29862 w_tx_fifo_empty +.sym 29863 w_tx_fifo_pull +.sym 29864 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 29865 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 29866 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29867 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29868 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 29869 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 29870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 29871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 29872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 29873 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.sym 29874 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 29875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 29876 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 29877 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 29880 i_rst_b$SB_IO_IN +.sym 29881 w_tx_fifo_pull +.sym 29882 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 29883 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 29884 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 29885 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 29887 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 29888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 29889 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 29901 w_tx_fifo_empty +.sym 29903 w_tx_fifo_pull +.sym 29904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 29905 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 29907 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 29908 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 29909 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 29917 i_rst_b$SB_IO_IN +.sym 29922 smi_ctrl_ins.w_fifo_pull_trigger +.sym 29926 smi_ctrl_ins.r_fifo_pull +.sym 29932 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.sym 29933 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29934 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 29935 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 29936 smi_ctrl_ins.int_cnt_rx[4] +.sym 29937 smi_ctrl_ins.int_cnt_rx[3] +.sym 29951 w_rx_fifo_empty +.sym 29952 smi_ctrl_ins.r_fifo_pull +.sym 29953 smi_ctrl_ins.r_fifo_pull_1 +.sym 29956 rx_fifo.rd_addr[1] +.sym 29957 rx_fifo.wr_addr_gray_rd_r[0] +.sym 29959 rx_fifo.rd_addr[5] +.sym 29960 rx_fifo.rd_addr[4] +.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] +.sym 29964 rx_fifo.rd_addr[4] +.sym 29965 rx_fifo.rd_addr[3] +.sym 29966 o_led1$SB_IO_OUT +.sym 29974 w_tx_fifo_full +.sym 29978 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] +.sym 29979 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.sym 29980 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.sym 29981 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] +.sym 29983 w_rx_fifo_empty +.sym 29984 rx_fifo.wr_addr_gray_rd_r[0] +.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.sym 29987 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 29988 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 29989 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 29991 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 29992 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 29993 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 29994 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 29998 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 30004 spi_if_ins.state_if[1] +.sym 30005 spi_if_ins.state_if[0] +.sym 30007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30008 spi_if_ins.state_if[1] +.sym 30009 spi_if_ins.state_if[0] +.sym 30011 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30012 spi_if_ins.state_if[1] +.sym 30013 spi_if_ins.state_if[0] +.sym 30015 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30016 spi_if_ins.state_if[1] +.sym 30017 spi_if_ins.state_if[0] +.sym 30018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30022 i_rst_b$SB_IO_IN +.sym 30023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30024 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30025 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 30026 i_rst_b$SB_IO_IN +.sym 30027 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30028 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 30029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30031 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 30032 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30033 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30035 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30036 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 30037 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30040 i_rst_b$SB_IO_IN +.sym 30041 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30042 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30043 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30045 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.sym 30047 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30049 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 30052 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30053 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 30060 spi_if_ins.w_rx_data[6] +.sym 30061 spi_if_ins.w_rx_data[5] +.sym 30065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 30068 spi_if_ins.w_rx_data[6] +.sym 30069 spi_if_ins.w_rx_data[5] +.sym 30080 spi_if_ins.w_rx_data[6] +.sym 30081 spi_if_ins.w_rx_data[5] +.sym 30082 w_tx_data_smi[1] +.sym 30083 w_tx_data_io[1] +.sym 30084 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 30085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30093 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 30095 io_pmod[6]$SB_IO_IN +.sym 30096 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30097 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 30099 i_rst_b$SB_IO_IN +.sym 30100 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.sym 30101 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.sym 30104 i_rst_b$SB_IO_IN +.sym 30105 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 30106 w_tx_data_io[2] +.sym 30107 w_tx_data_smi[2] +.sym 30108 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 30109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30115 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 30116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30117 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 30118 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 30119 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 30120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30123 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 30124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30125 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 30126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 30127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 30128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30129 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30131 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] +.sym 30132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30133 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.sym 30134 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] +.sym 30135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 30136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30137 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 30138 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 30139 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 30140 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30142 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 30143 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 30144 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30145 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 30148 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30149 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30152 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30156 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] +.sym 30157 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30160 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30161 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30164 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30165 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] +.sym 30169 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] +.sym 30173 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] +.sym 30177 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30243 tx_fifo.rd_addr[0] +.sym 30248 tx_fifo.rd_addr[1] +.sym 30249 tx_fifo.rd_addr[0] +.sym 30252 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.sym 30253 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30256 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 30257 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 +.sym 30260 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 30261 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 +.sym 30264 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 30265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 +.sym 30268 tx_fifo.rd_addr[6] +.sym 30269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 30272 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 30273 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 30276 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 30277 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 30280 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 30281 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 +.sym 30283 tx_fifo.wr_addr_gray_rd_r[6] +.sym 30284 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30287 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30292 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 30293 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +.sym 30296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 30297 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30300 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.sym 30301 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.sym 30302 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30308 tx_fifo.rd_addr[6] +.sym 30309 tx_fifo.wr_addr_gray_rd_r[6] +.sym 30310 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 30311 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 30312 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +.sym 30313 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 30314 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 30315 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 30316 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 30317 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 30320 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 30321 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 30326 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +.sym 30327 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +.sym 30328 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 30329 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.sym 30332 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30337 rx_fifo.wr_addr[1] +.sym 30344 tx_fifo.rd_addr[6] +.sym 30345 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 30346 smi_ctrl_ins.w_fifo_push_trigger +.sym 30350 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] +.sym 30351 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] +.sym 30352 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] +.sym 30353 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.sym 30359 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +.sym 30360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.sym 30361 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 30363 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +.sym 30364 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 30365 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.sym 30366 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 30367 tx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 30368 tx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 30369 tx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 30370 tx_fifo.wr_addr_gray_rd[7] +.sym 30374 tx_fifo.wr_addr_gray_rd[8] +.sym 30378 tx_fifo.wr_addr_gray_rd[2] +.sym 30382 tx_fifo.wr_addr_gray_rd[3] +.sym 30386 tx_fifo.wr_addr_gray_rd[5] +.sym 30390 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +.sym 30391 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +.sym 30392 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 30393 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 30394 tx_fifo.wr_addr_gray_rd[1] +.sym 30398 tx_fifo.wr_addr_gray_rd[9] +.sym 30402 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30406 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 30407 tx_fifo.rd_addr[1] +.sym 30408 tx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 30409 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30410 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.sym 30414 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30420 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30421 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30424 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.sym 30425 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30428 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.sym 30429 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.sym 30443 i_rst_b$SB_IO_IN +.sym 30444 smi_ctrl_ins.int_cnt_rx[4] +.sym 30445 smi_ctrl_ins.int_cnt_rx[3] +.sym 30449 smi_ctrl_ins.int_cnt_rx[3] +.sym 30456 smi_ctrl_ins.int_cnt_rx[4] +.sym 30457 smi_ctrl_ins.int_cnt_rx[3] +.sym 30482 w_rx_fifo_empty +.sym 30499 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30504 $PACKER_VCC_NET +.sym 30507 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 30508 $PACKER_VCC_NET +.sym 30509 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 30510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 30511 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 30512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 30513 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 30517 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30519 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30520 $PACKER_VCC_NET +.sym 30521 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30524 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 30528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30529 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30530 spi_if_ins.spi.r_tx_byte[6] +.sym 30531 spi_if_ins.spi.r_tx_byte[4] +.sym 30532 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30533 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30534 spi_if_ins.r_tx_byte[4] +.sym 30539 spi_if_ins.spi.r_tx_byte[1] +.sym 30540 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30541 spi_if_ins.spi.r_tx_byte[0] +.sym 30543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 30544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 30545 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 30546 spi_if_ins.r_tx_byte[7] +.sym 30551 spi_if_ins.spi.r_tx_byte[3] +.sym 30552 spi_if_ins.spi.r_tx_byte[2] +.sym 30553 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 30557 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 30558 spi_if_ins.spi.r_tx_byte[7] +.sym 30559 spi_if_ins.spi.r_tx_byte[5] +.sym 30560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 30561 spi_if_ins.spi.r_tx_bit_count[0] +.sym 30562 i_rst_b$SB_IO_IN +.sym 30563 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30565 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30566 spi_if_ins.r_tx_byte[0] +.sym 30570 spi_if_ins.r_tx_byte[2] +.sym 30574 w_cs[3] +.sym 30575 w_cs[2] +.sym 30576 w_cs[1] +.sym 30577 w_cs[0] +.sym 30578 spi_if_ins.r_tx_byte[5] +.sym 30582 spi_if_ins.r_tx_byte[6] +.sym 30586 spi_if_ins.r_tx_byte[3] +.sym 30590 spi_if_ins.r_tx_byte[1] +.sym 30594 w_cs[3] +.sym 30595 w_cs[2] +.sym 30596 w_cs[1] +.sym 30597 w_cs[0] +.sym 30598 w_cs[3] +.sym 30599 w_cs[2] +.sym 30600 w_cs[1] +.sym 30601 w_cs[0] +.sym 30602 w_rx_data[2] +.sym 30606 w_cs[3] +.sym 30607 w_cs[2] .sym 30608 w_cs[1] -.sym 30609 w_fetch -.sym 30610 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30616 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] -.sym 30617 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 30619 w_ioc[1] -.sym 30620 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 30621 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 30625 w_rx_data[0] -.sym 30628 i_button_SB_LUT4_I1_I0[2] -.sym 30629 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 30630 w_rx_data[1] -.sym 30634 w_rx_data[2] -.sym 30638 w_fetch -.sym 30639 w_cs[1] -.sym 30640 w_load -.sym 30641 i_rst_b$SB_IO_IN -.sym 30645 w_tx_data_io_SB_DFFESS_Q_S -.sym 30653 i_button_SB_LUT4_I1_I0[2] -.sym 30658 w_rx_data[0] -.sym 30662 w_rx_data[1] +.sym 30609 w_cs[0] +.sym 30610 w_tx_data_smi[0] +.sym 30611 w_tx_data_io[0] +.sym 30612 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.sym 30613 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30615 w_tx_data_io[7] +.sym 30616 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 30617 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30618 w_cs[3] +.sym 30619 w_cs[2] +.sym 30620 w_cs[1] +.sym 30621 w_cs[0] +.sym 30622 w_rx_data[0] +.sym 30626 r_tx_data[3] +.sym 30630 r_tx_data[4] +.sym 30634 r_tx_data[7] +.sym 30638 r_tx_data[1] +.sym 30642 r_tx_data[6] +.sym 30646 r_tx_data[0] +.sym 30651 w_tx_data_io[5] +.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30654 r_tx_data[5] +.sym 30658 w_rx_data[6] +.sym 30662 w_rx_data[3] .sym 30666 w_rx_data[2] -.sym 30670 o_shdn_tx_lna$SB_IO_OUT -.sym 30671 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 30672 i_button_SB_LUT4_I1_I0[2] -.sym 30673 io_ctrl_ins.o_pmod[2] -.sym 30674 w_rx_data[4] -.sym 30680 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 30681 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30690 w_rx_data[4] -.sym 30694 w_rx_data[3] -.sym 30698 w_rx_data[1] -.sym 30704 io_ctrl_ins.debug_mode[0] -.sym 30705 io_ctrl_ins.debug_mode[1] -.sym 30708 io_ctrl_ins.debug_mode[1] -.sym 30709 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 30710 io_ctrl_ins.debug_mode[0] -.sym 30711 io_ctrl_ins.mixer_en_state -.sym 30712 w_ioc[2] -.sym 30713 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 30718 w_rx_data[2] -.sym 30726 io_ctrl_ins.debug_mode[0] -.sym 30727 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30728 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 30729 i_rst_b$SB_IO_IN -.sym 30734 io_ctrl_ins.rf_pin_state[0] -.sym 30735 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 30736 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30737 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 30742 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30743 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 30744 io_ctrl_ins.rf_pin_state[2] -.sym 30745 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 30755 tx_fifo.wr_addr[0] -.sym 30760 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 30761 tx_fifo.wr_addr[0] -.sym 30764 tx_fifo.wr_addr[2] -.sym 30765 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 30768 tx_fifo.wr_addr[3] -.sym 30769 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 30772 tx_fifo.wr_addr[4] -.sym 30773 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 30776 tx_fifo.wr_addr[5] -.sym 30777 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 30780 tx_fifo.wr_addr[6] -.sym 30781 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 30784 tx_fifo.wr_addr[7] -.sym 30785 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 30788 tx_fifo.wr_addr[8] -.sym 30789 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 30792 tx_fifo.wr_addr[9] -.sym 30793 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] -.sym 30796 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 30797 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 30798 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 30804 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 30805 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 30809 tx_fifo.wr_addr[0] -.sym 30810 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.sym 30814 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 30818 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 30819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 30820 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 30821 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 30823 tx_fifo.rd_addr_gray_wr_r[6] -.sym 30824 tx_fifo.rd_addr_gray_wr_r[8] -.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 30826 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] -.sym 30827 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] -.sym 30828 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.sym 30829 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] -.sym 30830 spi_if_ins.spi.r_rx_done -.sym 30834 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 30835 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 30836 tx_fifo.empty_o_SB_LUT4_I3_O[1] -.sym 30837 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.sym 30838 tx_fifo.rd_addr_gray_wr_r[0] -.sym 30839 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 30840 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 30841 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 30842 tx_fifo.rd_addr_gray_wr[5] -.sym 30846 tx_fifo.rd_addr_gray_wr_r[4] -.sym 30847 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 30848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.sym 30849 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 30850 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -.sym 30851 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.sym 30852 tx_fifo.empty_o_SB_LUT4_I3_O[0] -.sym 30853 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 30854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 30855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -.sym 30856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 30857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] -.sym 30858 tx_fifo.rd_addr_gray[8] -.sym 30862 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 30866 tx_fifo.rd_addr_gray_wr[0] -.sym 30870 tx_fifo.rd_addr_gray[1] -.sym 30874 tx_fifo.rd_addr_gray_wr[9] -.sym 30878 tx_fifo.rd_addr_gray_wr[3] -.sym 30886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] -.sym 30887 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] -.sym 30888 smi_ctrl_ins.int_cnt_rx[4] -.sym 30889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] -.sym 30893 lvds_tx_inst.r_pulled_SB_LUT4_I2_O -.sym 30896 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -.sym 30897 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.sym 30900 smi_ctrl_ins.int_cnt_rx[4] -.sym 30901 smi_ctrl_ins.int_cnt_rx[3] -.sym 30902 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] -.sym 30903 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] -.sym 30904 smi_ctrl_ins.int_cnt_rx[4] -.sym 30905 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] -.sym 30906 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] -.sym 30907 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] -.sym 30908 smi_ctrl_ins.int_cnt_rx[4] -.sym 30909 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] -.sym 30914 tx_fifo.rd_addr_gray_wr[2] -.sym 30920 spi_if_ins.spi.r3_rx_done -.sym 30921 spi_if_ins.spi.r2_rx_done -.sym 30922 tx_fifo.rd_addr_gray_wr[1] -.sym 30927 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 30928 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -.sym 30929 tx_fifo.rd_addr[5] -.sym 30930 tx_fifo.rd_addr_gray_wr[8] -.sym 30938 spi_if_ins.spi.r2_rx_done -.sym 30942 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 30943 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 30944 smi_ctrl_ins.int_cnt_rx[4] -.sym 30945 smi_ctrl_ins.int_cnt_rx[3] -.sym 30974 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 30983 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30984 spi_if_ins.state_if[1] -.sym 30985 spi_if_ins.state_if[0] -.sym 30987 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 30988 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 30989 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 30996 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 30997 i_rst_b$SB_IO_IN -.sym 31001 smi_ctrl_ins.int_cnt_rx[3] -.sym 31003 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 31004 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31005 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31006 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31008 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31009 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.sym 31010 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 31015 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31016 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 31017 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31022 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31024 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31025 i_rst_b$SB_IO_IN -.sym 31026 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 31030 w_cs[1] -.sym 31031 w_cs[2] -.sym 31032 w_cs[0] -.sym 31033 w_cs[3] -.sym 31035 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 31036 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 31037 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 31039 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31040 i_rst_b$SB_IO_IN -.sym 31041 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31042 spi_if_ins.w_rx_data[3] -.sym 31046 spi_if_ins.w_rx_data[4] -.sym 31050 spi_if_ins.w_rx_data[2] -.sym 31054 w_cs[2] -.sym 31055 w_cs[3] -.sym 31056 w_cs[0] -.sym 31057 w_cs[1] -.sym 31058 spi_if_ins.w_rx_data[0] -.sym 31062 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 31066 spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.sym 31067 w_tx_data_smi[2] -.sym 31068 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 31069 io_ctrl_ins.o_data_out[2] -.sym 31070 spi_if_ins.w_rx_data[1] -.sym 31074 spi_if_ins.w_rx_data[6] -.sym 31078 spi_if_ins.w_rx_data[3] -.sym 31082 spi_if_ins.w_rx_data[1] -.sym 31086 spi_if_ins.w_rx_data[0] -.sym 31090 spi_if_ins.w_rx_data[2] -.sym 31094 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -.sym 31099 w_ioc[1] -.sym 31100 w_ioc[2] -.sym 31101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 31102 spi_if_ins.w_rx_data[4] -.sym 31108 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] -.sym 31109 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 31112 i_button_SB_LUT4_I1_O[0] -.sym 31113 i_button_SB_LUT4_I1_O[1] -.sym 31116 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 31117 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 31119 w_ioc[1] -.sym 31120 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 31121 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.sym 31123 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 31124 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 31125 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] -.sym 31126 w_ioc[2] -.sym 31127 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 31128 w_ioc[1] -.sym 31129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -.sym 31130 i_button_SB_LUT4_I1_I0[0] -.sym 31131 i_button$SB_IO_IN -.sym 31132 i_button_SB_LUT4_I1_I0[2] -.sym 31133 io_ctrl_ins.o_pmod[7] -.sym 31134 i_button_SB_LUT4_I1_I0[0] -.sym 31135 i_config[3]$SB_IO_IN -.sym 31136 i_button_SB_LUT4_I1_I0[2] -.sym 31137 io_ctrl_ins.o_pmod[6] -.sym 31138 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31139 io_ctrl_ins.pmod_dir_state[6] -.sym 31140 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 31141 o_rx_h_tx_l_b$SB_IO_OUT -.sym 31142 w_rx_data[5] -.sym 31146 w_rx_data[6] -.sym 31150 w_rx_data[7] -.sym 31156 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31157 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 31159 i_button_SB_LUT4_I1_I0[2] -.sym 31160 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 31161 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 31162 w_rx_data[3] -.sym 31166 i_button_SB_LUT4_I1_I0[0] -.sym 31167 i_button_SB_LUT4_I1_I0[1] -.sym 31168 i_button_SB_LUT4_I1_I0[2] -.sym 31169 i_button_SB_LUT4_I1_I0[3] -.sym 31176 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 31177 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] -.sym 31181 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 31186 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] -.sym 31187 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31188 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] -.sym 31189 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] -.sym 31191 i_button_SB_LUT4_I1_I0[2] -.sym 31192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31193 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 31200 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 31201 w_ioc[2] -.sym 31202 w_rx_data[6] -.sym 31206 w_rx_data[2] -.sym 31210 w_rx_data[7] -.sym 31214 w_rx_data[0] -.sym 31218 w_rx_data[4] -.sym 31222 w_rx_data[1] -.sym 31226 w_rx_data[5] -.sym 31230 w_rx_data[3] -.sym 31249 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 31259 io_ctrl_ins.rf_pin_state[1] -.sym 31260 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31261 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31262 io_ctrl_ins.rf_pin_state[3] -.sym 31263 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 31264 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31265 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31266 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 31272 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 31273 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 31274 tx_fifo.full_o_SB_LUT4_I3_O[1] -.sym 31278 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 31284 i_rst_b$SB_IO_IN -.sym 31285 i_smi_soe_se$SB_IO_IN -.sym 31286 tx_fifo.full_o_SB_LUT4_I3_O[2] -.sym 31290 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 31294 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.sym 31299 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 31304 tx_fifo.wr_addr[2] -.sym 31305 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -.sym 31308 tx_fifo.wr_addr[3] -.sym 31309 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 31312 tx_fifo.wr_addr[4] -.sym 31313 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 31316 tx_fifo.wr_addr[5] -.sym 31317 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 31320 tx_fifo.wr_addr[6] -.sym 31321 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 31324 tx_fifo.wr_addr[7] -.sym 31325 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 31328 tx_fifo.wr_addr[8] -.sym 31329 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 31332 tx_fifo.wr_addr[9] -.sym 31333 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 31334 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.sym 31335 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.sym 31336 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] -.sym 31337 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.sym 31340 tx_fifo.rd_addr_gray_wr_r[6] -.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 31344 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.sym 31345 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.sym 31347 tx_fifo.rd_addr_gray_wr_r[4] -.sym 31348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 31352 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.sym 31353 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 31354 tx_fifo.rd_addr_gray_wr_r[8] -.sym 31355 tx_fifo.rd_addr_gray_wr_r[9] -.sym 31356 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] -.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.sym 31358 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 31359 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] -.sym 31360 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.sym 31372 tx_fifo.rd_addr_gray_wr_r[2] -.sym 31373 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.sym 31374 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 31375 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.sym 31379 w_rx_fifo_empty -.sym 31380 w_tx_fifo_full -.sym 31381 o_led0$SB_IO_OUT -.sym 31382 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 31387 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.sym 31388 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.sym 31389 tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.sym 31400 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] -.sym 31401 i_rst_b$SB_IO_IN -.sym 31402 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 31410 lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.sym 31416 tx_fifo.wr_addr[0] -.sym 31417 tx_fifo.rd_addr_gray_wr_r[0] -.sym 31418 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 31419 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 31420 smi_ctrl_ins.int_cnt_rx[4] -.sym 31421 smi_ctrl_ins.int_cnt_rx[3] -.sym 31422 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.sym 31438 w_rx_fifo_pulled_data[24] -.sym 31442 w_rx_fifo_pulled_data[28] -.sym 31450 w_rx_fifo_pulled_data[20] -.sym 31454 w_rx_fifo_pulled_data[21] -.sym 31474 w_ioc[2] -.sym 31475 w_ioc[4] -.sym 31476 w_ioc[3] -.sym 31477 w_ioc[1] -.sym 31482 smi_ctrl_ins.r_fifo_pull -.sym 31495 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31496 spi_if_ins.state_if[0] -.sym 31497 spi_if_ins.state_if[1] -.sym 31498 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 31499 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 31500 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.sym 31501 i_rst_b$SB_IO_IN -.sym 31506 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31507 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] -.sym 31508 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 31509 i_rst_b$SB_IO_IN -.sym 31514 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 31520 spi_if_ins.state_if[0] -.sym 31521 spi_if_ins.state_if[1] -.sym 31523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31527 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31528 $PACKER_VCC_NET -.sym 31531 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31532 $PACKER_VCC_NET -.sym 31533 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 31539 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31540 $PACKER_VCC_NET -.sym 31541 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31545 $PACKER_VCC_NET -.sym 31549 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31552 spi_if_ins.o_cs_SB_LUT4_I2_O[0] -.sym 31553 i_rst_b$SB_IO_IN -.sym 31556 sys_ctrl_ins.tx_sample_gap[0] -.sym 31557 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 31562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] -.sym 31563 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] -.sym 31564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31565 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31575 w_ioc[4] -.sym 31576 w_ioc[3] -.sym 31577 w_ioc[2] -.sym 31580 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 31581 sys_ctrl_ins.tx_sample_gap[3] -.sym 31584 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] -.sym 31585 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31587 spi_if_ins.spi.r_tx_byte[3] -.sym 31588 spi_if_ins.spi.r_tx_byte[7] -.sym 31589 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31592 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 31593 sys_ctrl_ins.tx_sample_gap[1] -.sym 31600 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 31601 sys_ctrl_ins.tx_sample_gap[2] -.sym 31603 sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] -.sym 31604 w_cs[0] -.sym 31605 w_fetch -.sym 31606 spi_if_ins.spi.r_tx_byte[0] -.sym 31607 spi_if_ins.spi.r_tx_byte[4] -.sym 31608 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31609 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31614 spi_if_ins.spi.r_tx_byte[1] -.sym 31615 spi_if_ins.spi.r_tx_byte[5] -.sym 31616 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31617 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 31631 sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.sym 31632 i_button_SB_LUT4_I1_I0[0] -.sym 31633 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 31640 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] -.sym 31641 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] -.sym 31650 w_rx_data[7] -.sym 31654 w_rx_data[4] -.sym 31660 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 31661 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 31662 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31663 io_ctrl_ins.pmod_dir_state[5] -.sym 31664 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 31665 o_tr_vc1$SB_IO_OUT -.sym 31666 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -.sym 31667 io_ctrl_ins.pmod_dir_state[7] -.sym 31668 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] -.sym 31669 o_rx_h_tx_l$SB_IO_OUT -.sym 31670 w_rx_data[3] -.sym 31674 w_rx_data[6] -.sym 31678 w_rx_data[5] -.sym 31694 io_ctrl_ins.o_pmod[4] -.sym 31695 i_button_SB_LUT4_I1_I0[2] -.sym 31696 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31697 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] -.sym 31698 i_config[0]$SB_IO_IN -.sym 31699 io_ctrl_ins.pmod_dir_state[3] -.sym 31700 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 31701 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 31702 io_ctrl_ins.o_pmod[3] -.sym 31703 i_button_SB_LUT4_I1_I0[2] -.sym 31704 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 31705 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 31710 i_config[1]$SB_IO_IN -.sym 31711 io_ctrl_ins.pmod_dir_state[4] -.sym 31712 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] -.sym 31713 i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] -.sym 31716 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 31717 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 31719 io_ctrl_ins.rf_pin_state[7] -.sym 31720 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31721 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31722 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31723 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 31724 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 31725 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31726 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 31727 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31728 io_ctrl_ins.rf_pin_state[5] -.sym 31729 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31730 o_tr_vc2$SB_IO_OUT -.sym 31731 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31732 w_ioc[2] -.sym 31733 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 31734 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 31735 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 31736 io_ctrl_ins.rf_pin_state[4] -.sym 31737 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31738 o_tr_vc1_b$SB_IO_OUT -.sym 31739 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -.sym 31740 w_ioc[2] -.sym 31741 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] -.sym 31743 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 31744 io_ctrl_ins.rf_pin_state[6] -.sym 31745 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31781 w_smi_data_input[7] -.sym 31818 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 31826 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 31830 i_mosi$SB_IO_IN -.sym 31842 spi_if_ins.spi.r_rx_byte[7] -.sym 31850 spi_if_ins.spi.r_rx_byte[1] -.sym 31874 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 31882 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 31886 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 31890 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 31898 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 31905 i_ss$SB_IO_IN -.sym 31910 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 31914 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 31918 i_mosi$SB_IO_IN -.sym 31922 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 31926 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 31930 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 31934 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 31942 spi_if_ins.spi.r_rx_byte[2] -.sym 31946 spi_if_ins.spi.r_rx_byte[3] -.sym 31958 spi_if_ins.spi.r_rx_byte[4] -.sym 32002 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 32008 i_ss$SB_IO_IN -.sym 32009 spi_if_ins.r_tx_data_valid -.sym 32010 i_sck$SB_IO_IN -.sym 32014 spi_if_ins.spi.SCKr[0] -.sym 32040 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 32041 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 32046 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 32047 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] -.sym 32048 spi_if_ins.spi.r_tx_bit_count[2] -.sym 32049 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 32055 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 32056 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 32057 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32059 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 32060 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 32061 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32063 spi_if_ins.r_tx_byte[7] -.sym 32064 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 32065 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32066 r_tx_data[2] -.sym 32074 r_tx_data[5] -.sym 32078 r_tx_data[0] -.sym 32090 r_tx_data[3] -.sym 32094 r_tx_data[4] -.sym 32098 spi_if_ins.r_tx_byte[0] -.sym 32102 spi_if_ins.r_tx_byte[6] -.sym 32106 spi_if_ins.r_tx_byte[7] -.sym 32110 spi_if_ins.r_tx_byte[5] -.sym 32114 spi_if_ins.r_tx_byte[1] -.sym 32118 spi_if_ins.r_tx_byte[4] -.sym 32122 spi_if_ins.r_tx_byte[2] -.sym 32126 spi_if_ins.r_tx_byte[3] -.sym 32131 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 32135 lvds_rx_09_inst.r_phase_count[1] -.sym 32136 $PACKER_VCC_NET -.sym 32137 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 32138 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 32140 $PACKER_VCC_NET -.sym 32141 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 32143 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 32144 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 32145 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 32146 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32147 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 32148 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 32149 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32153 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 32154 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32155 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 32156 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 32157 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32169 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 32170 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 32171 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 32172 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32173 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32190 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32191 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 32192 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 32193 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32210 w_rx_fifo_full -.sym 32211 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32212 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32213 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -.sym 32220 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 32221 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 32293 i_sck$SB_IO_IN -.sym 32318 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32322 smi_ctrl_ins.w_fifo_push_trigger -.sym 32355 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32360 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32364 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32365 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 32368 i_ss$SB_IO_IN -.sym 32369 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32372 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32373 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32385 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32390 spi_if_ins.spi.r_rx_byte[6] -.sym 32398 spi_if_ins.spi.r_rx_byte[0] -.sym 32403 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32404 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32405 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32406 spi_if_ins.spi.r_rx_byte[5] -.sym 32410 i_ss$SB_IO_IN -.sym 32411 spi_if_ins.spi.r_rx_bit_count[0] -.sym 32412 spi_if_ins.spi.r_rx_bit_count[2] -.sym 32413 spi_if_ins.spi.r_rx_bit_count[1] -.sym 32547 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 32548 io_ctrl_ins.o_data_out[5] -.sym 32549 w_tx_data_io_SB_LUT4_I3_O[2] -.sym 32553 i_glob_clock$SB_IO_IN -.sym 32569 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -.sym 32593 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 32596 spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.sym 32597 io_ctrl_ins.o_data_out[4] -.sym 32634 spi_if_ins.w_rx_data[5] +.sym 30670 w_rx_data[5] +.sym 30674 w_rx_data[7] +.sym 30678 w_rx_data[1] +.sym 30683 w_fetch +.sym 30684 w_cs[0] +.sym 30685 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] +.sym 30686 w_rx_data[4] +.sym 30714 w_rx_data[0] +.sym 30745 r_counter +.sym 30758 tx_fifo.wr_addr_gray_rd[6] +.sym 30766 tx_fifo.wr_addr_gray_rd[0] +.sym 30772 i_smi_swe_srw$SB_IO_IN +.sym 30773 i_rst_b$SB_IO_IN +.sym 30774 tx_fifo.wr_addr_gray[4] +.sym 30778 tx_fifo.wr_addr_gray_rd[4] +.sym 30784 i_smi_soe_se$SB_IO_IN +.sym 30785 i_rst_b$SB_IO_IN +.sym 30787 tx_fifo.wr_addr[0] +.sym 30792 tx_fifo.wr_addr[1] +.sym 30793 tx_fifo.wr_addr[0] +.sym 30796 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 +.sym 30800 tx_fifo.wr_addr[3] +.sym 30801 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 30804 tx_fifo.wr_addr[4] +.sym 30805 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30808 tx_fifo.wr_addr[5] +.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 30812 tx_fifo.wr_addr[6] +.sym 30813 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 30816 tx_fifo.wr_addr[7] +.sym 30817 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 30820 tx_fifo.wr_addr[8] +.sym 30821 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30824 tx_fifo.wr_addr[9] +.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 30826 tx_fifo.rd_addr_gray_wr[6] +.sym 30830 rx_fifo.wr_addr_gray[0] +.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 30836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 30838 tx_fifo.rd_addr_gray_wr[4] +.sym 30843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 30844 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 30845 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 30852 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30853 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30857 w_smi_data_input[7] +.sym 30860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 30867 tx_fifo.rd_addr_gray_wr_r[8] +.sym 30868 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30869 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 30870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30871 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 30872 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30873 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 30878 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 30879 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 30880 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30882 tx_fifo.rd_addr_gray_wr[8] +.sym 30886 tx_fifo.rd_addr_gray[4] +.sym 30890 tx_fifo.rd_addr_gray[8] +.sym 30894 tx_fifo.rd_addr_gray_wr[2] +.sym 30898 tx_fifo.rd_addr_gray[7] +.sym 30902 tx_fifo.rd_addr_gray_wr[1] +.sym 30906 tx_fifo.rd_addr_gray[1] +.sym 30910 tx_fifo.rd_addr_gray_wr[7] +.sym 30918 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.sym 30930 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 30934 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.sym 30945 tx_fifo.rd_addr[1] +.sym 30970 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +.sym 30974 tx_fifo.rd_addr_gray[6] +.sym 31006 rx_fifo.wr_addr_gray_rd[0] +.sym 31019 spi_if_ins.r_tx_byte[7] +.sym 31020 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31021 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31031 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 31032 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31033 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31058 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 31064 i_ss$SB_IO_IN +.sym 31065 spi_if_ins.r_tx_data_valid +.sym 31068 i_ss$SB_IO_IN +.sym 31069 spi_if_ins.r_tx_data_valid +.sym 31074 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 31088 spi_if_ins.w_rx_data[6] +.sym 31089 spi_if_ins.w_rx_data[5] +.sym 31094 w_cs[2] +.sym 31095 w_ioc[1] +.sym 31096 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 31097 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31100 i_rst_b$SB_IO_IN +.sym 31101 w_fetch +.sym 31102 spi_if_ins.w_rx_data[0] +.sym 31106 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31111 w_ioc[1] +.sym 31112 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31113 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31123 w_load +.sym 31124 w_fetch +.sym 31125 w_cs[0] +.sym 31126 w_ioc[1] +.sym 31127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31128 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 31129 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 31132 w_ioc[1] +.sym 31133 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 31134 w_cs[1] +.sym 31135 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 31136 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31137 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31140 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 31147 i_config[1]$SB_IO_IN +.sym 31148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31149 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31152 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31153 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31155 w_ioc[1] +.sym 31156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31157 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 31158 w_ioc[1] +.sym 31159 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31160 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 31161 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31163 w_ioc[1] +.sym 31164 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31165 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 31167 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 31169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.sym 31170 w_cs[1] +.sym 31171 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.sym 31172 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31173 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 31174 o_tr_vc1_b$SB_IO_OUT +.sym 31175 io_ctrl_ins.pmod_dir_state[4] +.sym 31176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31177 i_button_SB_LUT4_I0_O[1] +.sym 31178 w_rx_data[7] +.sym 31182 w_ioc[1] +.sym 31183 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31184 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.sym 31185 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31186 w_rx_data[1] +.sym 31191 w_ioc[1] +.sym 31192 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31193 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31194 w_rx_data[6] +.sym 31198 w_rx_data[4] +.sym 31203 o_rx_h_tx_l_b$SB_IO_OUT +.sym 31204 i_button_SB_LUT4_I0_O[1] +.sym 31205 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 31206 i_config[2]$SB_IO_IN +.sym 31207 io_ctrl_ins.pmod_dir_state[5] +.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 31210 i_config[3]$SB_IO_IN +.sym 31211 io_ctrl_ins.pmod_dir_state[6] +.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 31223 o_tr_vc1$SB_IO_OUT +.sym 31224 i_button_SB_LUT4_I0_O[1] +.sym 31225 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.sym 31226 i_button$SB_IO_IN +.sym 31227 io_ctrl_ins.pmod_dir_state[7] +.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.sym 31231 o_rx_h_tx_l$SB_IO_OUT +.sym 31232 i_button_SB_LUT4_I0_O[1] +.sym 31233 i_button_SB_LUT4_I0_O[2] +.sym 31250 w_rx_data[5] +.sym 31270 tx_fifo.wr_addr_gray[6] +.sym 31294 tx_fifo.wr_addr_gray[0] +.sym 31301 tx_fifo.wr_addr[1] +.sym 31304 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 31305 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 31328 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31329 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 31332 i_rst_b$SB_IO_IN +.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 31336 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31337 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 31342 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 31346 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31357 tx_fifo.wr_addr[0] +.sym 31360 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31361 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.sym 31364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 31365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 31366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31367 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 31368 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 31369 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 31370 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 31374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 31380 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 31381 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 31382 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 31390 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 31394 tx_fifo.wr_addr_gray[1] +.sym 31398 tx_fifo.wr_addr_gray[3] +.sym 31402 tx_fifo.wr_addr_gray[2] +.sym 31406 tx_fifo.wr_addr_gray[8] +.sym 31418 tx_fifo.wr_addr_gray[5] +.sym 31422 tx_fifo.wr_addr_gray[7] +.sym 31426 tx_fifo.rd_addr_gray_wr[5] +.sym 31446 tx_fifo.rd_addr_gray[0] +.sym 31462 spi_if_ins.spi.r2_rx_done +.sym 31470 tx_fifo.rd_addr_gray[5] +.sym 31476 spi_if_ins.spi.r3_rx_done +.sym 31477 spi_if_ins.spi.r2_rx_done +.sym 31514 i_sck$SB_IO_IN +.sym 31522 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31538 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 31546 spi_if_ins.spi.SCKr[0] +.sym 31558 w_rx_data[0] +.sym 31563 i_rst_b$SB_IO_IN +.sym 31564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 31586 spi_if_ins.w_rx_data[1] +.sym 31598 spi_if_ins.w_rx_data[4] +.sym 31602 spi_if_ins.w_rx_data[3] +.sym 31607 w_ioc[4] +.sym 31608 w_ioc[3] +.sym 31609 w_ioc[2] +.sym 31611 w_ioc[4] +.sym 31612 w_ioc[3] +.sym 31613 w_ioc[2] +.sym 31614 spi_if_ins.w_rx_data[2] +.sym 31618 w_cs[2] +.sym 31619 w_load +.sym 31620 w_fetch +.sym 31621 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31624 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31625 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 31627 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31628 io_pmod[0]$SB_IO_IN +.sym 31629 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31630 w_cs[2] +.sym 31631 w_load +.sym 31632 w_fetch +.sym 31633 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31635 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31636 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] +.sym 31637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31639 w_ioc[1] +.sym 31640 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31641 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 31643 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 31644 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 31645 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 31646 o_shdn_rx_lna$SB_IO_OUT +.sym 31647 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31648 io_pmod[1]$SB_IO_IN +.sym 31649 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31650 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 31651 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 31652 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] +.sym 31653 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] +.sym 31655 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31656 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 31657 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] +.sym 31659 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 31660 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31661 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 31662 w_cs[1] +.sym 31663 w_load +.sym 31664 w_fetch +.sym 31665 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 31666 io_ctrl_ins.mixer_en_state +.sym 31667 i_button_SB_LUT4_I0_O[1] +.sym 31668 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] +.sym 31669 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] +.sym 31670 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31671 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.sym 31672 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 31673 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 31674 o_tr_vc2$SB_IO_OUT +.sym 31675 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31676 io_pmod[3]$SB_IO_IN +.sym 31677 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31678 o_shdn_tx_lna$SB_IO_OUT +.sym 31679 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31680 io_pmod[2]$SB_IO_IN +.sym 31681 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 31682 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.sym 31683 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] +.sym 31684 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31685 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31686 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] +.sym 31687 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] +.sym 31688 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31689 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31690 w_rx_data[3] +.sym 31694 w_cs[1] +.sym 31695 w_load +.sym 31696 w_fetch +.sym 31697 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31698 w_rx_data[2] +.sym 31702 i_config[0]$SB_IO_IN +.sym 31703 io_ctrl_ins.pmod_dir_state[3] +.sym 31704 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +.sym 31705 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31706 i_rst_b$SB_IO_IN +.sym 31707 w_cs[1] +.sym 31708 w_load +.sym 31709 w_fetch +.sym 31710 w_rx_data[0] +.sym 31718 w_rx_data[0] +.sym 31734 w_rx_data[1] +.sym 31740 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 31741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +.sym 31783 i_rst_b$SB_IO_IN +.sym 31784 w_smi_data_input[7] +.sym 31785 smi_ctrl_ins.tx_reg_state[0] +.sym 31787 w_smi_data_input[7] +.sym 31788 smi_ctrl_ins.tx_reg_state[2] +.sym 31789 smi_ctrl_ins.tx_reg_state[1] +.sym 31791 i_rst_b$SB_IO_IN +.sym 31792 w_smi_data_input[7] +.sym 31793 smi_ctrl_ins.tx_reg_state[2] +.sym 31796 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 31797 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 31798 i_rst_b$SB_IO_IN +.sym 31799 w_smi_data_input[7] +.sym 31800 smi_ctrl_ins.tx_reg_state[3] +.sym 31801 smi_ctrl_ins.tx_reg_state[0] +.sym 31803 i_rst_b$SB_IO_IN +.sym 31804 smi_ctrl_ins.tx_reg_state[3] +.sym 31805 smi_ctrl_ins.tx_reg_state[0] +.sym 31807 i_rst_b$SB_IO_IN +.sym 31808 w_smi_data_input[7] +.sym 31809 smi_ctrl_ins.tx_reg_state[1] +.sym 31811 tx_fifo.wr_addr[1] +.sym 31816 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 31817 tx_fifo.wr_addr[1] +.sym 31820 tx_fifo.wr_addr[3] +.sym 31821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31824 tx_fifo.wr_addr[4] +.sym 31825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31828 tx_fifo.wr_addr[5] +.sym 31829 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31832 tx_fifo.wr_addr[6] +.sym 31833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31836 tx_fifo.wr_addr[7] +.sym 31837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31840 tx_fifo.wr_addr[8] +.sym 31841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 31844 tx_fifo.wr_addr[9] +.sym 31845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 31847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.sym 31851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 31853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.sym 31855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.sym 31856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.sym 31857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31858 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31859 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.sym 31860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.sym 31863 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31864 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31866 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 31870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.sym 31871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 31873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.sym 31874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.sym 31875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] +.sym 31876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.sym 31877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.sym 31878 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.sym 31881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 31882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31883 tx_fifo.wr_addr[1] +.sym 31884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31885 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.sym 31886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31887 tx_fifo.rd_addr_gray_wr_r[8] +.sym 31888 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.sym 31889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 31890 tx_fifo.wr_addr[9] +.sym 31896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 31897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 31899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] +.sym 31900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] +.sym 31901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.sym 31903 tx_fifo.full_o_SB_LUT4_I1_O[0] +.sym 31904 tx_fifo.full_o_SB_LUT4_I1_O[1] +.sym 31905 tx_fifo.full_o_SB_LUT4_I1_O[2] +.sym 31915 w_tx_fifo_full +.sym 31916 tx_fifo.wr_addr[1] +.sym 31917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31922 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 31923 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 31924 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 31925 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 31927 w_tx_fifo_full +.sym 31928 smi_ctrl_ins.r_fifo_push_1 +.sym 31929 smi_ctrl_ins.r_fifo_push +.sym 31934 smi_ctrl_ins.r_fifo_push +.sym 31938 tx_fifo.rd_addr_gray_wr[0] +.sym 31943 w_rx_fifo_empty +.sym 31944 w_tx_fifo_full +.sym 31945 o_led0$SB_IO_OUT +.sym 31946 spi_if_ins.spi.r_rx_done +.sym 31962 tx_fifo.rd_addr_gray_wr[9] +.sym 31974 i_mosi$SB_IO_IN +.sym 31985 o_miso_$_TBUF__Y_E +.sym 31986 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 32002 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 32006 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 32010 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 32014 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 32018 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 32022 i_mosi$SB_IO_IN +.sym 32026 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 32030 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 32034 spi_if_ins.spi.r_rx_byte[5] +.sym 32038 spi_if_ins.spi.r_rx_byte[6] +.sym 32042 spi_if_ins.spi.r_rx_byte[2] +.sym 32046 spi_if_ins.spi.r_rx_byte[1] +.sym 32050 spi_if_ins.spi.r_rx_byte[4] +.sym 32054 spi_if_ins.spi.r_rx_byte[7] +.sym 32058 spi_if_ins.spi.r_rx_byte[0] +.sym 32062 spi_if_ins.spi.r_rx_byte[3] +.sym 32090 spi_if_ins.w_rx_data[0] +.sym 32094 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 32098 spi_if_ins.w_rx_data[2] +.sym 32102 spi_if_ins.w_rx_data[1] +.sym 32106 spi_if_ins.w_rx_data[5] +.sym 32110 spi_if_ins.w_rx_data[4] +.sym 32114 spi_if_ins.w_rx_data[6] +.sym 32122 spi_if_ins.w_rx_data[3] +.sym 32143 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 32145 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.sym 32158 w_rx_data[0] +.sym 32162 w_rx_data[0] +.sym 32166 w_rx_data[1] +.sym 32170 w_rx_data[4] +.sym 32176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 32177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] +.sym 32178 w_rx_data[2] +.sym 32182 w_rx_data[3] +.sym 32186 i_rst_b$SB_IO_IN +.sym 32187 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 32188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32189 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32192 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] +.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 32194 w_rx_data[0] +.sym 32198 w_rx_data[4] +.sym 32202 w_rx_data[7] +.sym 32206 w_rx_data[6] +.sym 32210 w_rx_data[2] +.sym 32214 w_rx_data[3] +.sym 32218 w_rx_data[1] +.sym 32222 w_rx_data[5] +.sym 32252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 32253 i_button_SB_LUT4_I0_O[1] +.sym 32473 i_ss$SB_IO_IN +.sym 32474 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 32483 spi_if_ins.spi.r_rx_bit_count[0] +.sym 32488 spi_if_ins.spi.r_rx_bit_count[1] +.sym 32489 spi_if_ins.spi.r_rx_bit_count[0] +.sym 32492 spi_if_ins.spi.r_rx_bit_count[2] +.sym 32493 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 32498 i_ss$SB_IO_IN +.sym 32499 spi_if_ins.spi.r_rx_bit_count[2] +.sym 32500 spi_if_ins.spi.r_rx_bit_count[1] +.sym 32501 spi_if_ins.spi.r_rx_bit_count[0] +.sym 32505 spi_if_ins.spi.r_rx_bit_count[0] +.sym 32507 spi_if_ins.spi.r_rx_bit_count[2] +.sym 32508 spi_if_ins.spi.r_rx_bit_count[1] +.sym 32509 spi_if_ins.spi.r_rx_bit_count[0] +.sym 32514 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 32526 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 32530 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 32534 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 32540 i_ss$SB_IO_IN +.sym 32541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 32542 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 32614 w_rx_data[2] +.sym 32622 w_rx_data[1] +.sym 32630 w_rx_data[3] +.sym 32670 w_rx_data[0] +.sym 32686 io_ctrl_ins.rf_pin_state[2] +.sym 32687 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32688 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32689 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32690 io_ctrl_ins.rf_pin_state[0] +.sym 32691 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32693 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32706 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32707 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 32708 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32709 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32710 io_ctrl_ins.rf_pin_state[5] +.sym 32711 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32712 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 32713 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32714 io_ctrl_ins.rf_pin_state[4] +.sym 32715 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32716 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.sym 32717 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32718 io_ctrl_ins.rf_pin_state[3] +.sym 32719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32721 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32723 io_ctrl_ins.rf_pin_state[1] +.sym 32724 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 32725 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32727 io_ctrl_ins.rf_pin_state[6] +.sym 32728 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32729 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 32732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 32733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 32735 io_ctrl_ins.rf_pin_state[7] +.sym 32736 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.sym 32737 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] diff --git a/firmware/top.bin b/firmware/top.bin index 57ff8e7..341c3ff 100644 Binary files a/firmware/top.bin and b/firmware/top.bin differ diff --git a/firmware/top.blif b/firmware/top.blif index 53b0d31..2d0c15c 100644 --- a/firmware/top.blif +++ b/firmware/top.blif @@ -1,2322 +1,2572 @@ -# Generated by Yosys 0.29+42 (git sha1 43b807fe6, gcc 10.2.1-6 -fPIC -Os) +# Generated by Yosys 0.39+0 (git sha1 18cec2d9a, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) .model top .inputs i_glob_clock i_rst_b i_iq_rx_09_p i_iq_rx_24_n i_iq_rx_clk_p i_config[0] i_config[1] i_config[2] i_config[3] i_button io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] i_smi_a2 i_smi_a3 i_smi_soe_se i_smi_swe_srw io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] i_mosi i_sck i_ss -.outputs o_rx_h_tx_l o_rx_h_tx_l_b o_tr_vc1 o_tr_vc1_b o_tr_vc2 o_shdn_rx_lna o_shdn_tx_lna o_iq_tx_p o_iq_tx_n o_iq_tx_clk_p o_iq_tx_clk_n o_mixer_fm o_mixer_en o_led0 o_led1 io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] o_smi_write_req o_smi_read_req o_miso +.outputs o_rx_h_tx_l o_rx_h_tx_l_b o_tr_vc1 o_tr_vc1_b o_tr_vc2 o_shdn_rx_lna o_shdn_tx_lna o_iq_tx_p o_iq_tx_n o_iq_tx_clk_p o_iq_tx_clk_n o_mixer_fm o_mixer_en io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] o_led0 o_led1 io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] o_smi_write_req o_smi_read_req o_miso .names $false .names $true 1 .names $undef -.gate SB_LUT4 I0=i_button_SB_LUT4_I1_I0[0] I1=i_button I2=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I3=io_ctrl_ins.pmod_state[7] O=i_button_SB_LUT4_I1_O[1] +.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=i_button_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=i_button_SB_LUT4_I1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] I3=spi_if_ins.o_ioc[0] O=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[2] I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[1] O=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111001100110011 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_rst_b O=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_ss O=i_ss_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_ss O=o_miso_$_TBUF__Y_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.debug_mode[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=io_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.debug_mode[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.debug_mode[0] I1=io_ctrl_ins.rf_mode[1] I2=io_ctrl_ins.rf_mode[2] I3=i_rst_b O=io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.debug_mode[0] I3=io_ctrl_ins.debug_mode[1] O=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.debug_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] O=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=io_ctrl_ins.i_cs_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[9] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=io_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.led1_state_SB_DFFER_Q_E Q=io_ctrl_ins.led0_state R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.led0_state I1=io_ctrl_ins.pmod_dir_state[0] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.led1_state_SB_DFFER_Q_E Q=io_ctrl_ins.led1_state R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=i_button_SB_LUT4_I1_I0[0] O=io_ctrl_ins.led1_state_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=io_ctrl_ins.led1_state I1=io_ctrl_ins.pmod_dir_state[1] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_LUT4 I0=io_ctrl_ins.debug_mode[1] I1=io_ctrl_ins.lna_rx_shutdown_state I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.lna_rx_shutdown_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000111111001100 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.lna_tx_shutdown_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_mode[1] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_pin_state[2] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011101111110000 -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] I2=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I3=io_ctrl_ins.pmod_state[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] +.param LUT_INIT 1011100000000000 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.mixer_en_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D +.param LUT_INIT 1111001110101010 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.debug_mode[0] I1=io_ctrl_ins.mixer_en_state I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] +.param LUT_INIT 1011100000000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=w_tx_data_io_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[1] R=w_tx_data_io_SB_DFFESS_Q_S -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=w_tx_data_io_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[3] R=w_tx_data_io_SB_DFFESS_Q_S -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[3] I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000111111111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=w_tx_data_io_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[4] R=w_tx_data_io_SB_DFFESS_Q_S -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[4] I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000111111111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[2] I1=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100011111111 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] I3=io_ctrl_ins.rf_mode[0] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] +.param LUT_INIT 1000101010101010 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[2] I1=spi_if_ins.o_ioc[0] I2=spi_if_ins.o_ioc[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011000011111111 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] I2=spi_if_ins.o_ioc[2] I3=spi_if_ins.o_ioc[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001100111011 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] O=w_tx_data_io_SB_DFFESS_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111100000000 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=spi_if_ins.o_ioc[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] O=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[4] I3=spi_if_ins.o_ioc[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[1] +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000001000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_4_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E Q=io_ctrl_ins.o_data_out[5] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.param LUT_INIT 1100111111111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_4_D +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E Q=io_ctrl_ins.o_data_out[6] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E Q=io_ctrl_ins.o_data_out[7] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=i_button_SB_LUT4_I1_O[0] I3=i_button_SB_LUT4_I1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111111111 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[1] I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=io_ctrl_ins.led1_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.led1_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011110010101010 +.gate SB_LUT4 I0=io_ctrl_ins.mixer_en_state I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I2=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] I3=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000111111111111 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[7] +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_dir_state[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I3=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] O=io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I3=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E Q=io_ctrl_ins.rf_pin_state[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] I3=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] O=io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.rx_h_b_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] I2=io_ctrl_ins.rf_pin_state[6] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111100110000 -.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I1=io_ctrl_ins.pmod_dir_state[6] I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] I3=io_ctrl_ins.rx_h_b_state O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] +.param LUT_INIT 0000000011110011 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E Q=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_LUT4 I0=i_button_SB_LUT4_I1_I0[0] I1=i_config[3] I2=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I3=io_ctrl_ins.pmod_state[6] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] +.param LUT_INIT 0000100000000000 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.rx_h_state +.param LUT_INIT 1111001011111111 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111001100000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001011111111 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000010001000 +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000100010000000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=i_config[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1101111100000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000011111100 -.gate SB_LUT4 I0=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] I1=io_ctrl_ins.rf_mode[0] I2=io_ctrl_ins.rf_mode[2] I3=io_ctrl_ins.rf_mode[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100001100 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010100000101010 -.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I1=io_ctrl_ins.pmod_dir_state[7] I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] I3=io_ctrl_ins.rx_h_state O=i_button_SB_LUT4_I1_O[0] +.param LUT_INIT 0001100000000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_1_b_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] I1=io_ctrl_ins.rf_mode[1] I2=io_ctrl_ins.rf_pin_state[4] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D +.param LUT_INIT 1111110010101010 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.pmod_dir_state[4] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110111011110000 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.rf_mode[2] I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3] +.param LUT_INIT 0001010100111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101001111111111 -.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.param LUT_INIT 0010011010101111 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_1_state +.param LUT_INIT 0111011100100000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] I1=io_ctrl_ins.rf_mode[1] I2=io_ctrl_ins.rf_pin_state[5] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=sys_ctrl_ins.i_cs O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001000111110000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.rf_mode[0] I3=io_ctrl_ins.rf_mode[2] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] +.param LUT_INIT 0000001110101010 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] I1=io_ctrl_ins.pmod_dir_state[5] I2=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] I3=io_ctrl_ins.tr_vc_1_state O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_LUT4 I0=i_button_SB_LUT4_I1_I0[0] I1=i_config[2] I2=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I3=io_ctrl_ins.pmod_state[5] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_2_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:209.5-307.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=io_ctrl_ins.rf_mode[1] I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[3] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101001111111111 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] I3=spi_if_ins.o_ioc[2] O=io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[2] +.param LUT_INIT 1011100000000000 +.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.pmod_dir_state[3] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001101011111 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] O=io_pmod_SB_DFFE_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[0] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] +.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=spi_if_ins.o_fetch_cmd O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 -.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.pmod_dir_state[3] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.param LUT_INIT 0000000010000000 +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011010111111111 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=i_iq_rx_09_p -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:256.7-261.4" +.attr src "top.v:288.7-293.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=i_iq_rx_24_n +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_24_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:241.7-247.4" +.attr src "top.v:273.7-279.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=i_iq_rx_clk_p +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=lvds_clock PACKAGE_PIN=i_iq_rx_clk_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:223.7-226.4" +.attr src "top.v:255.7-258.4" .param IO_STANDARD "SB_LVDS_INPUT" .param PIN_TYPE 000001 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_n +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=lvds_clock PACKAGE_PIN=o_iq_tx_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:282.5-287.4" +.attr src "top.v:314.5-319.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_p +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=lvds_clock PACKAGE_PIN=o_iq_tx_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:271.5-276.4" +.attr src "top.v:303.5-308.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[1] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[2] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[11] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000010 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[12] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=io_pmod[7] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[13] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100111111000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[14] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[15] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[16] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[17] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[18] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[19] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[20] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[3] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[21] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[22] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[23] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[24] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[25] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[26] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[27] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[28] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[29] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[30] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[4] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[5] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[6] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[7] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[8] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[9] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[10] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.r_state_if[0] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D[0] E=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_D E=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E Q=lvds_rx_09_inst.o_fifo_push R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.r_state_if[1] O=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] O=lvds_rx_09_inst.r_phase_count[0] +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFE C=lvds_clock D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] O=lvds_rx_09_inst.r_phase_count[1] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[1] E=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_09_inst.r_state_if[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[0] E=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_09_inst.r_state_if[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[1] I2=lvds_rx_09_inst.r_state_if[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=lvds_rx_09_inst.r_state_if[0] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[0] +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d1 I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000010 +.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100010101010101 +.gate SB_LUT4 I0=$false I1=io_pmod[6] I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_24_inst.i_sync_input .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000011111111 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[0] I2=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I3=w_lvds_rx_09_d1_SB_LUT4_I1_O[2] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.param LUT_INIT 1100111111000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[29] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[30] +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[28] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[29] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[19] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[20] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[18] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[19] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[17] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[18] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[16] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[17] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[15] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[16] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[14] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[15] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[13] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[14] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[12] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[13] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[11] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[12] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[10] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[11] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[27] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[28] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[9] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[10] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[8] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[9] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[7] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[8] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[6] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[7] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[5] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[6] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[4] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[5] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[4] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[2] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[3] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[2] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[0] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[1] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[26] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[27] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[25] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[26] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[24] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[25] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[23] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[24] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[22] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[23] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[21] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[22] +.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[20] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[21] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.i_ddr_data[1] +.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[1] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_DFFNESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[2] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[11] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[12] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[13] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[14] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[15] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[16] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[17] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[18] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[19] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[20] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[3] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[21] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[22] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[23] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[24] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[25] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[26] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[27] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[28] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[29] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[30] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[4] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[5] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[6] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[7] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[8] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[9] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[10] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.i_ddr_data[1] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D[0] E=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_D E=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E Q=lvds_rx_24_inst.o_fifo_push R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.r_state_if[1] O=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] O=lvds_rx_24_inst.r_phase_count[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] O=lvds_rx_24_inst.r_phase_count[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[1] E=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_state_if[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[0] E=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_state_if[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[1] I2=lvds_rx_24_inst.r_state_if[0] I3=w_lvds_rx_24_d1_SB_LUT4_I2_O[0] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[1] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O[0] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000011111111 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[0] I2=rx_fifo.full_o_SB_LUT4_I0_I3[1] I3=w_lvds_rx_24_d0_SB_LUT4_I1_O[0] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[29] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[30] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[28] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[29] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[19] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[20] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[18] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[19] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[17] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[18] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[16] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[17] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[15] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[16] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[14] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[15] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[13] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[14] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[12] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[13] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[11] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[12] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[10] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[11] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[27] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[28] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[9] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[10] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[8] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[7] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[6] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[5] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[4] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[2] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[0] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[26] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[27] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[25] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[26] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[24] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[25] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[23] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[24] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[22] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[23] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[21] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[22] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[20] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[21] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D E=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:375.11-389.4|lvds_tx.v:56.3-123.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "lvds_tx.v:56.3-123.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.empty_o O=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_rst_b O=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_E +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110000001100 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000010000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=lvds_tx_inst.r_pulled O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=o_iq_tx_clk_n .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_pulled I3=i_rst_b O=lvds_tx_inst.r_pulled_SB_LUT4_I2_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=lvds_tx_inst.r_pulled O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=o_led1_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=tx_fifo.wr_addr_gray_rd_r[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_ddr_clk O=o_iq_tx_clk_n -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=i_ss_SB_LUT4_I3_O Y=o_miso -.attr src "top.v:129.19-129.43" -.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=tx_fifo.full_o I3=i_smi_a2 O=o_smi_read_req +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 +.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso +.attr src "top.v:150.19-150.43" +.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=tx_fifo.full_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011001100001111 .gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=i_glob_clock D=r_tx_data_SB_DFFESR_Q_D[28] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[4] R=w_tx_data_io_SB_LUT4_I3_O[1] +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=i_glob_clock D=r_tx_data_SB_DFFESR_Q_3_D[5] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[5] R=w_tx_data_io_SB_LUT4_I3_O[1] +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=i_glob_clock D=r_tx_data_SB_DFFESR_Q_D[30] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[6] R=w_tx_data_io_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=i_glob_clock D=r_tx_data_SB_DFFESR_Q_3_D[7] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[7] R=w_tx_data_io_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I2=io_ctrl_ins.o_data_out[5] I3=w_tx_data_io_SB_LUT4_I3_O[2] O=r_tx_data_SB_DFFESR_Q_3_D[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111111000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I2=io_ctrl_ins.o_data_out[7] I3=w_tx_data_io_SB_LUT4_I3_O[2] O=r_tx_data_SB_DFFESR_Q_3_D[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111111000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=io_ctrl_ins.o_data_out[6] O=r_tx_data_SB_DFFESR_Q_D[30] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=io_ctrl_ins.o_data_out[4] O=r_tx_data_SB_DFFESR_Q_D[28] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D[3] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D[2] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D[1] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D[0] E=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O Q=r_tx_data[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:192.3-206.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105" -.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] I1=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] I1=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.param LUT_INIT 1010111000001100 +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110011111111 +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100001111 +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010111000001100 +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010111000001100 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] O=r_tx_data_SB_DFFE_Q_5_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111011111111 +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110011111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001101011111 +.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_7_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111011111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001101011111 +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110011111111 +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100001111 +.gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105" +.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101010101010 +.gate SB_DFFSR C=lvds_clock D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111110000000 +.gate SB_LUT4 I0=rx_fifo.full_o I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101000000010 +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O[0] I2=rx_fifo.full_o_SB_LUT4_I0_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[7] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000001001 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] I1=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] I3=rx_fifo.rd_en_i O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] +.param LUT_INIT 0011001101011010 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.wr_addr_gray_rd_r[9] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001010000001 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000001001 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.rd_addr[7] I2=rx_fifo.rd_addr[8] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110000000001011 -.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] I3=rx_fifo.rd_addr[5] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111000000001011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr[6] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr[7] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.param LUT_INIT 0000110000000101 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[9] I3=rx_fifo.rd_addr[8] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[3] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001010000001 -.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o_SB_LUT4_I3_I1[0] I2=rx_fifo.empty_o_SB_LUT4_I3_I1[1] I3=rx_fifo.empty_o O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[5] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[3] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000001001 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.wr_addr[1] I2=rx_fifo.rd_addr_gray_wr_r[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[1] I1=rx_fifo.rd_addr[1] I2=rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] I3=rx_fifo.rd_addr[2] O=rx_fifo.empty_o_SB_LUT4_I3_I1[1] +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001010000001 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[2] I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr[3] O=rx_fifo.empty_o_SB_LUT4_I3_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[0] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFSR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] O=rx_fifo.full_o_SB_DFFSR_Q_D +.param LUT_INIT 0111001101010000 +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.param LUT_INIT 0101000011011101 +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] I2=rx_fifo.wr_en_i I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[2] I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100010000001 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[3] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[6] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[2] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[1] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[5] I2=rx_fifo.rd_addr_gray_wr_r[6] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[6] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100010000001 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[1] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000100101000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[0] I3=rx_fifo.rd_addr_gray_wr_r[0] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001010000001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=rx_fifo.full_o I1=lvds_rx_24_inst.r_state_if[0] I2=lvds_rx_24_inst.r_state_if[1] I3=rx_fifo.full_o_SB_LUT4_I0_I3[1] O=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o I1=lvds_rx_09_inst.r_state_if[0] I2=lvds_rx_09_inst.r_state_if[1] I3=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] O=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I2=rx_fifo.rd_addr_gray_wr_r[9] I3=rx_fifo.full_o O=rx_fifo.full_o_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=rx_fifo.wr_en_i I1=rx_fifo.full_o_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.full_o_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=rx_fifo.full_o_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[16] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[18] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[17] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[19] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[20] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[22] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[21] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[23] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[24] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[26] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[25] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[27] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[28] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[30] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[29] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[31] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[0] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[2] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[1] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[3] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[4] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[6] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[5] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[7] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[8] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[10] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[9] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[11] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[12] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[14] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[13] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[15] WDATA[14]=$undef WDATA[15]=$undef WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param READ_MODE 10 -.param WRITE_MODE 10 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[5] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] I3=rx_fifo.wr_addr_gray_rd_r[6] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000001001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] E=rx_fifo.rd_en_i_SB_LUT4_I2_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000001001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[0] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] I0=$false I1=rx_fifo.rd_addr[8] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=rx_fifo.rd_addr[7] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=rx_fifo.rd_addr[6] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=rx_fifo.rd_addr[5] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=rx_fifo.rd_addr[4] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=rx_fifo.rd_addr[3] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=rx_fifo.rd_addr[2] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=rx_fifo.rd_addr[1] -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100010000010 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] I2=$true I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7] +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001000101000 +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] I1=$true +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_en_i I3=i_rst_b O=rx_fifo.rd_en_i_SB_LUT4_I2_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_pull_1 I2=rx_fifo.empty_o I3=smi_ctrl_ins.r_fifo_pull O=rx_fifo.rd_en_i -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.full_o_SB_LUT4_I3_O[1] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[6] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] I2=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_I3[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=rx_fifo.full_o_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] I2=o_led1 I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000001100 +.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110000000001011 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.param LUT_INIT 0110000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] I3=rx_fifo.rd_addr_gray_wr_r[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] I1=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100010000001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.param LUT_INIT 1111111100001111 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] E=rx_fifo.wr_en_i_SB_LUT4_I2_O Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[0] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] I3=rx_fifo.rd_addr_gray_wr_r[4] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011000010111011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] I0=$false I1=rx_fifo.wr_addr[8] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] I0=$false I1=rx_fifo.wr_addr[7] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] I0=$false I1=rx_fifo.wr_addr[6] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] I0=$false I1=rx_fifo.wr_addr[5] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] I0=$false I1=rx_fifo.wr_addr[4] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] I0=$false I1=rx_fifo.wr_addr[3] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] I0=$false I1=rx_fifo.wr_addr[2] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] I0=$false I1=rx_fifo.wr_addr[1] -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=rx_fifo.wr_addr[8] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=rx_fifo.wr_addr[7] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=rx_fifo.wr_addr[6] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=rx_fifo.wr_addr[5] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=rx_fifo.wr_addr[4] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=rx_fifo.wr_addr[3] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=rx_fifo.wr_addr[2] -.attr src "top.v:354.5-367.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[9] Q=rx_fifo.wr_addr_gray_rd[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[8] Q=rx_fifo.wr_addr_gray_rd[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[7] Q=rx_fifo.wr_addr_gray_rd[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[6] Q=rx_fifo.wr_addr_gray_rd[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[5] Q=rx_fifo.wr_addr_gray_rd[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[4] Q=rx_fifo.wr_addr_gray_rd[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[3] Q=rx_fifo.wr_addr_gray_rd[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[2] Q=rx_fifo.wr_addr_gray_rd[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[1] Q=rx_fifo.wr_addr_gray_rd[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[0] Q=rx_fifo.wr_addr_gray_rd[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[9] Q=rx_fifo.wr_addr_gray_rd_r[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[8] Q=rx_fifo.wr_addr_gray_rd_r[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[7] Q=rx_fifo.wr_addr_gray_rd_r[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[6] Q=rx_fifo.wr_addr_gray_rd_r[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[5] Q=rx_fifo.wr_addr_gray_rd_r[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[4] Q=rx_fifo.wr_addr_gray_rd_r[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[3] Q=rx_fifo.wr_addr_gray_rd_r[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[2] Q=rx_fifo.wr_addr_gray_rd_r[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[1] Q=rx_fifo.wr_addr_gray_rd_r[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[0] Q=rx_fifo.wr_addr_gray_rd_r[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:354.5-367.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=i_smi_a3 O=rx_fifo.wr_data_i[31] +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=i_smi_a3 O=rx_fifo.wr_data_i[30] +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=i_smi_a3 O=rx_fifo.wr_data_i[21] +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=i_smi_a3 O=rx_fifo.wr_data_i[20] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[19] I2=lvds_rx_24_inst.o_fifo_data[19] I3=i_smi_a3 O=rx_fifo.wr_data_i[19] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=i_smi_a3 O=rx_fifo.wr_data_i[18] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=i_smi_a3 O=rx_fifo.wr_data_i[17] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=i_smi_a3 O=rx_fifo.wr_data_i[16] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[15] I2=lvds_rx_24_inst.o_fifo_data[15] I3=i_smi_a3 O=rx_fifo.wr_data_i[15] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=i_smi_a3 O=rx_fifo.wr_data_i[14] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[13] I2=lvds_rx_24_inst.o_fifo_data[13] I3=i_smi_a3 O=rx_fifo.wr_data_i[13] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=i_smi_a3 O=rx_fifo.wr_data_i[12] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[29] I2=lvds_rx_24_inst.o_fifo_data[29] I3=i_smi_a3 O=rx_fifo.wr_data_i[29] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=i_smi_a3 O=rx_fifo.wr_data_i[11] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=i_smi_a3 O=rx_fifo.wr_data_i[10] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=i_smi_a3 O=rx_fifo.wr_data_i[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[8] I2=lvds_rx_24_inst.o_fifo_data[8] I3=i_smi_a3 O=rx_fifo.wr_data_i[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=i_smi_a3 O=rx_fifo.wr_data_i[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=i_smi_a3 O=rx_fifo.wr_data_i[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=i_smi_a3 O=rx_fifo.wr_data_i[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[4] I2=lvds_rx_24_inst.o_fifo_data[4] I3=i_smi_a3 O=rx_fifo.wr_data_i[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=i_smi_a3 O=rx_fifo.wr_data_i[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[2] I2=lvds_rx_24_inst.o_fifo_data[2] I3=i_smi_a3 O=rx_fifo.wr_data_i[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[28] I2=lvds_rx_24_inst.o_fifo_data[28] I3=i_smi_a3 O=rx_fifo.wr_data_i[28] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[1] I2=lvds_rx_24_inst.o_fifo_data[1] I3=i_smi_a3 O=rx_fifo.wr_data_i[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[0] I2=lvds_rx_24_inst.o_fifo_data[0] I3=i_smi_a3 O=rx_fifo.wr_data_i[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=i_smi_a3 O=rx_fifo.wr_data_i[27] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=i_smi_a3 O=rx_fifo.wr_data_i[26] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[25] I2=lvds_rx_24_inst.o_fifo_data[25] I3=i_smi_a3 O=rx_fifo.wr_data_i[25] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=i_smi_a3 O=rx_fifo.wr_data_i[24] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=i_smi_a3 O=rx_fifo.wr_data_i[23] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=i_smi_a3 O=rx_fifo.wr_data_i[22] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_en_i I3=i_rst_b O=rx_fifo.wr_en_i_SB_LUT4_I2_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_push I2=lvds_rx_09_inst.o_fifo_push I3=i_smi_a3 O=rx_fifo.wr_en_i +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=o_led1 O=rx_fifo.mem_i.0.0_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[6] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D[1] Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D[0] Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[22] I2=lvds_rx_09_inst.o_fifo_data[22] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D[0] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[23] I2=lvds_rx_09_inst.o_fifo_data[23] I3=o_led1 O=rx_fifo.mem_i.0.1_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[26] I2=lvds_rx_09_inst.o_fifo_data[26] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[27] I2=lvds_rx_09_inst.o_fifo_data[27] I3=o_led1 O=rx_fifo.mem_i.0.2_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[31] I2=lvds_rx_09_inst.o_fifo_data[31] I3=o_led1 O=rx_fifo.mem_i.0.3_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=o_led1 O=rx_fifo.mem_q.0.0_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[6] I2=lvds_rx_09_inst.o_fifo_data[6] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=o_led1 O=rx_fifo.mem_q.0.1_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[10] I2=lvds_rx_09_inst.o_fifo_data[10] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=o_led1 O=rx_fifo.mem_q.0.2_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[13] I2=lvds_rx_24_inst.o_fifo_data[13] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_2 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[15] I2=lvds_rx_24_inst.o_fifo_data[15] I3=o_led1 O=rx_fifo.mem_q.0.3_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[5] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[7] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=i_rst_b O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFESR C=r_counter D=smi_ctrl_ins.r_channel E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[4] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[3] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I1=i_rst_b I2=smi_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I1_O[0] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=io_ctrl_ins.o_data_out[2] O=smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I1_O[0] I1=smi_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=io_ctrl_ins.o_data_out[1] O=smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[7] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[6] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[6] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[5] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[5] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[2] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[4] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[3] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[2] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[1] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[0] E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[7] I1=smi_ctrl_ins.r_fifo_pulled_data[15] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[6] I1=smi_ctrl_ins.r_fifo_pulled_data[14] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[22] I1=smi_ctrl_ins.r_fifo_pulled_data[30] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[5] I1=smi_ctrl_ins.r_fifo_pulled_data[13] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[21] I1=smi_ctrl_ins.r_fifo_pulled_data[29] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[4] I1=smi_ctrl_ins.r_fifo_pulled_data[12] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[20] I1=smi_ctrl_ins.r_fifo_pulled_data[28] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[3] I1=smi_ctrl_ins.r_fifo_pulled_data[11] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[19] I1=smi_ctrl_ins.r_fifo_pulled_data[27] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[2] I1=smi_ctrl_ins.r_fifo_pulled_data[10] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[18] I1=smi_ctrl_ins.r_fifo_pulled_data[26] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[1] I1=smi_ctrl_ins.r_fifo_pulled_data[9] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[17] I1=smi_ctrl_ins.r_fifo_pulled_data[25] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[0] I1=smi_ctrl_ins.r_fifo_pulled_data[8] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110000001010 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[16] I1=smi_ctrl_ins.r_fifo_pulled_data[24] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[23] I1=smi_ctrl_ins.r_fifo_pulled_data[31] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110100000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_channel_SB_DFFER_Q_E Q=smi_ctrl_ins.r_channel R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=smi_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=i_button_SB_LUT4_I1_I0[0] O=smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0100000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[2] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[1] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[3] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001111111110110 +.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001111011 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110011101111110 +.gate SB_LUT4 I0=rx_fifo.rd_addr[3] I1=rx_fifo.rd_addr[2] I2=rx_fifo.wr_addr_gray_rd_r[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[8] I2=rx_fifo.rd_addr[7] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.wr_addr_gray_rd_r[5] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100001100 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_8_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000101011001111 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000001000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001101010001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[2] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[3] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[1] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[8] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[7] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_8_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[7] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001100110001 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010001011110011 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011101011 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[4] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[9] Q=rx_fifo.wr_addr_gray_rd[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[8] Q=rx_fifo.wr_addr_gray_rd[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[7] Q=rx_fifo.wr_addr_gray_rd[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[6] Q=rx_fifo.wr_addr_gray_rd[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[5] Q=rx_fifo.wr_addr_gray_rd[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[4] Q=rx_fifo.wr_addr_gray_rd[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[3] Q=rx_fifo.wr_addr_gray_rd[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[2] Q=rx_fifo.wr_addr_gray_rd[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[1] Q=rx_fifo.wr_addr_gray_rd[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[0] Q=rx_fifo.wr_addr_gray_rd[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[9] Q=rx_fifo.wr_addr_gray_rd_r[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[8] Q=rx_fifo.wr_addr_gray_rd_r[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[7] Q=rx_fifo.wr_addr_gray_rd_r[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[6] Q=rx_fifo.wr_addr_gray_rd_r[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[5] Q=rx_fifo.wr_addr_gray_rd_r[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[4] Q=rx_fifo.wr_addr_gray_rd_r[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[3] Q=rx_fifo.wr_addr_gray_rd_r[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[2] Q=rx_fifo.wr_addr_gray_rd_r[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[1] Q=rx_fifo.wr_addr_gray_rd_r[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[0] Q=rx_fifo.wr_addr_gray_rd_r[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFESR C=r_counter D=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" +.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=o_led1 E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000000011 +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[2] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[14] I1=smi_ctrl_ins.r_fifo_pulled_data[6] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101000001100 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[30] I1=smi_ctrl_ins.r_fifo_pulled_data[22] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[13] I1=smi_ctrl_ins.r_fifo_pulled_data[5] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101000001100 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[29] I1=smi_ctrl_ins.r_fifo_pulled_data[21] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[12] I1=smi_ctrl_ins.r_fifo_pulled_data[4] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101000001100 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[28] I1=smi_ctrl_ins.r_fifo_pulled_data[20] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.r_fifo_pulled_data[3] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010001000110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[27] I1=smi_ctrl_ins.r_fifo_pulled_data[19] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[10] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[2] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010001100100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[26] I1=smi_ctrl_ins.r_fifo_pulled_data[18] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[9] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010001100100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[25] I1=smi_ctrl_ins.r_fifo_pulled_data[17] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[8] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[0] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010001100100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[24] I1=smi_ctrl_ins.r_fifo_pulled_data[16] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[15] I1=smi_ctrl_ins.r_fifo_pulled_data[7] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101000001100 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[31] I1=smi_ctrl_ins.r_fifo_pulled_data[23] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010000011000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=smi_ctrl_ins.r_fifo_pull I3=smi_ctrl_ins.r_fifo_pull_1 O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000110000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_pull_trigger Q=smi_ctrl_ins.r_fifo_pull R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[31] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[31] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[30] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[30] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[21] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[21] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[20] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[20] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[19] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[19] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[18] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[18] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[17] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[17] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[16] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[16] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[15] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[15] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[14] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[14] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[13] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[13] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[12] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[12] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[29] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[29] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[11] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[11] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[10] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[10] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[9] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[8] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[7] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[6] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[5] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[4] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[3] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[2] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[28] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[28] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[1] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[0] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[27] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[27] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[26] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[26] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[25] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[25] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[24] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[24] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[23] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[23] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[22] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[22] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_push Q=smi_ctrl_ins.r_fifo_push_1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_push_1 I2=tx_fifo.full_o I3=smi_ctrl_ins.r_fifo_push O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] +.attr src "smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push_1 I3=smi_ctrl_ins.r_fifo_push O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] I3=i_rst_b O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr[1] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010010000010 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[0] I3=tx_fifo.rd_addr_gray_wr_r[0] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[8] I1=tx_fifo.rd_addr_gray_wr_r[9] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001010000001 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] I2=tx_fifo.rd_addr_gray_wr_r[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100010000001 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] I1=tx_fifo.rd_addr_gray_wr_r[5] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr[2] I2=tx_fifo.rd_addr_gray_wr_r[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] I2=tx_fifo.rd_addr_gray_wr_r[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0] +.param LUT_INIT 0011110000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100010000001 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.param LUT_INIT 1000001010111110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[4] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[5] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_push_trigger Q=smi_ctrl_ins.r_fifo_push R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=i_smi_soe_se O=smi_ctrl_ins.soe_and_reset +.attr src "smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=$false I2=i_smi_soe_se I3=i_rst_b O=smi_ctrl_ins.soe_and_reset .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=i_smi_swe_srw O=smi_ctrl_ins.swe_and_reset +.gate SB_LUT4 I0=$false I1=$false I2=i_smi_swe_srw I3=i_rst_b O=smi_ctrl_ins.swe_and_reset .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -2333,1871 +2583,1664 @@ .gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D Q=smi_ctrl_ins.tx_reg_state[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=i_rst_b I3=smi_ctrl_ins.tx_reg_state[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D +.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 +.param LUT_INIT 0000110000000000 .gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D Q=smi_ctrl_ins.tx_reg_state[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[0] I3=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000011111111 -.gate SB_LUT4 I0=smi_ctrl_ins.i_smi_data_in[7] I1=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.tx_reg_state[3] I3=i_rst_b O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110100000000 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.tx_reg_state[1] I3=smi_ctrl_ins.tx_reg_state[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=i_rst_b I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=i_rst_b I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000001010 +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[2] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 +.param LUT_INIT 1100110011000000 +.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.w_fifo_pull_trigger .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" +.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 .gate SB_DFFNSR C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D Q=smi_ctrl_ins.w_fifo_push_trigger R=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:421.12-453.4|smi_ctrl.v:189.5-264.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" +.attr src "smi_ctrl.v:189.5-264.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.i_smi_data_in[7] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.tx_reg_state[0] I2=smi_ctrl_ins.tx_reg_state[3] I3=i_rst_b O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001111111111 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[0] +.param LUT_INIT 0011001100111111 +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:471.5-476.4" +.attr src "top.v:503.5-508.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[1] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:480.5-485.4" +.attr src "top.v:512.5-517.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[2] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:489.5-494.4" +.attr src "top.v:521.5-526.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[3] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:498.5-503.4" +.attr src "top.v:530.5-535.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[4] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:507.5-512.4" +.attr src "top.v:539.5-544.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[5] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:516.5-521.4" +.attr src "top.v:548.5-553.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[6] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:525.5-530.4" +.attr src "top.v:557.5-562.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=i_smi_a2 PACKAGE_PIN=io_smi_data[7] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:534.5-539.4" +.attr src "top.v:566.5-571.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[3] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[5] I3=spi_if_ins.spi.o_rx_byte[6] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[5] I3=spi_if_ins.spi.o_rx_byte[6] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[3] +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_cs[3] I2=sys_ctrl_ins.i_cs I3=smi_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_cs[3] I2=sys_ctrl_ins.i_cs I3=io_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=smi_ctrl_ins.i_cs I2=spi_if_ins.o_cs[3] I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I2_O[0] +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111111011101000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I3=i_rst_b O=spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[7] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[6] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[5] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_fetch_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I3=spi_if_ins.state_if[2] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] I3=i_rst_b O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110100000000 +.param LUT_INIT 0000000000000100 +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000010 +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000010111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000010000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_cs_SB_LUT4_I0_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[7] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[6] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[5] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_fetch_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010100000100000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011110011 .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_load_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_load_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I1=spi_if_ins.state_if[2] I2=spi_if_ins.spi.o_rx_data_valid I3=i_rst_b O=spi_if_ins.o_ioc_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 +.param LUT_INIT 0000000000110000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011000000 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=i_rst_b O=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1] +.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=io_ctrl_ins.i_cs O=io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=sys_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] O=sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O Q=spi_if_ins.r_tx_byte[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I1=spi_if_ins.state_if[2] I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001111100000000 +.param LUT_INIT 0101011100000000 .gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] O=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000000000 .gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[1] Q=spi_if_ins.spi.SCKr[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[0] Q=spi_if_ins.spi.SCKr[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=i_sck Q=spi_if_ins.spi.SCKr[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_LUT4 I0=spi_if_ins.spi.SCKr[2] I1=spi_if_ins.spi.r_tx_bit_count[0] I2=spi_if_ins.spi.r_tx_bit_count[2] I3=spi_if_ins.spi.SCKr[1] O=spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.SCKr[2] I2=spi_if_ins.spi.SCKr[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100110000 .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[7] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[6] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[5] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[4] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[3] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[2] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[1] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[0] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFF C=r_counter D=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_data_valid .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.o_spi_miso -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[1] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_ioc_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011111110 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[1] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100101000000000 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[0] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_bit_count[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110000001010 -.gate SB_LUT4 I0=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_bit_count[1] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100101000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[2] I2=spi_if_ins.spi.r_tx_byte[6] I3=spi_if_ins.spi.r_tx_bit_count[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.param LUT_INIT 0000000000001000 +.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_data_in_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000111100110011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[7] I3=spi_if_ins.spi.r_tx_bit_count[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.param LUT_INIT 1100000000000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.o_spi_miso +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000111100110011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.SCKr[2] I2=spi_if_ins.spi.SCKr[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.param LUT_INIT 1100000011001111 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010100011111101 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[7] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101001100000000 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[6] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001010011 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000011111111 +.param LUT_INIT 1111110000110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_byte[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100111111000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000000011 .gate SB_DFF C=r_counter D=spi_if_ins.spi.r_rx_done Q=spi_if_ins.spi.r2_rx_done .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=spi_if_ins.spi.r2_rx_done Q=spi_if_ins.spi.r3_rx_done .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r3_rx_done I3=spi_if_ins.spi.r2_rx_done O=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[2] Q=spi_if_ins.spi.r_rx_bit_count[2] R=i_ss +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D Q=spi_if_ins.spi.r_rx_bit_count[2] R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[1] Q=spi_if_ins.spi.r_rx_bit_count[1] R=i_ss +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D Q=spi_if_ins.spi.r_rx_bit_count[1] R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] Q=spi_if_ins.spi.r_rx_bit_count[0] R=i_ss +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] +.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D Q=spi_if_ins.spi.r_rx_bit_count[0] R=i_ss +.attr module_not_derived 00000000000000000000000000000001 +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[2] +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=spi_if_ins.spi.r_rx_bit_count[0] CO=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1] -.attr src "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=spi_if_ins.spi.r_rx_bit_count[0] CO=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1] +.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[6] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=i_mosi E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFESR C=i_sck D=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_rx_done R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[0] I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=i_ss I1=spi_if_ins.spi.r_rx_bit_count[0] I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.gate SB_LUT4 I0=i_ss I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110101110101010 -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[6] +.param LUT_INIT 1110101010111010 +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[5] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[4] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[3] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[2] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[1] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=i_mosi E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[0] +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=i_mosi E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[0] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[0] R=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=$true I3=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=$true I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[0] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_CARRY CI=spi_if_ins.spi.r_tx_bit_count[0] CO=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] I0=spi_if_ins.spi.r_tx_bit_count[1] I1=$true -.attr src "top.v:111.10-126.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[2] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[2] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[2] S=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[1] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[1] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[1] S=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=$true I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[7] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[7] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=$true I3=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[6] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[6] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=spi_if_ins.spi.r_tx_bit_count[0] CO=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 I0=spi_if_ins.spi.r_tx_bit_count[1] I1=$true +.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[7] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[7] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[5] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[5] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[6] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[6] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[4] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[4] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[5] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[5] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[3] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[3] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[4] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[4] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[2] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[2] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[3] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[3] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[1] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[1] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[2] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[2] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[1] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[1] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000011111111 -.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I2=spi_if_ins.spi.o_rx_byte[7] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I3=i_rst_b O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] I2=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] I3=i_rst_b O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O +.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] O=spi_if_ins.r_tx_byte_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[1] +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011110011 -.gate SB_LUT4 I0=spi_if_ins.state_if[2] I1=spi_if_ins.state_if[0] I2=spi_if_ins.state_if[1] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011110000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.param LUT_INIT 0000000000110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100000000 .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] I2=i_rst_b I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1_SB_LUT4_I1_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] I3=i_rst_b O=spi_if_ins.state_if_SB_DFFESR_Q_E +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] O=spi_if_ins.state_if_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101111111111 -.gate SB_DFFE C=r_counter D=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=sys_ctrl_ins.i_cs +.param LUT_INIT 0101010111011111 +.gate SB_DFFE C=r_counter D=sys_ctrl_ins.i_cs_SB_DFFE_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=sys_ctrl_ins.i_cs .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[5] I3=spi_if_ins.spi.o_rx_byte[6] O=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=sys_ctrl_ins.i_cs_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] I2=sys_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.gate SB_DFFNSS C=lvds_clock D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105" +.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101010101010 +.gate SB_LUT4 I0=tx_fifo.empty_o I1=lvds_tx_inst.r_pulled I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.wr_addr_gray_rd_r[9] O=tx_fifo.empty_o_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010001000000010 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I2=tx_fifo.empty_o_SB_LUT4_I0_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000010010000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[8] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110110101001000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001010101010 +.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101010100010100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[7] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111100 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr[8] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011101011 +.gate SB_LUT4 I0=tx_fifo.rd_addr[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0111110100000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr[8] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001111101 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000001000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100110010000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[6] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=tx_fifo.empty_o_SB_LUT4_I0_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100001100 +.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100010001000 +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.wr_addr[1] I3=tx_fifo.rd_addr_gray_wr_r[0] O=tx_fifo.full_o_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o_SB_LUT4_I1_O[0] I2=tx_fifo.full_o_SB_LUT4_I1_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.full_o_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010101000010101 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[5] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[7] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[4] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[3] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[2] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[1] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111101000101 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[7] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010001011110011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[8] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[8] Q=tx_fifo.rd_addr_gray_wr[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[7] Q=tx_fifo.rd_addr_gray_wr[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[6] Q=tx_fifo.rd_addr_gray_wr[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[5] Q=tx_fifo.rd_addr_gray_wr[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[4] Q=tx_fifo.rd_addr_gray_wr[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[3] Q=tx_fifo.rd_addr_gray_wr[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[2] Q=tx_fifo.rd_addr_gray_wr[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[1] Q=tx_fifo.rd_addr_gray_wr[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[0] Q=tx_fifo.rd_addr_gray_wr[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[9] Q=tx_fifo.rd_addr_gray_wr_r[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[8] Q=tx_fifo.rd_addr_gray_wr_r[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[7] Q=tx_fifo.rd_addr_gray_wr_r[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[6] Q=tx_fifo.rd_addr_gray_wr_r[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[5] Q=tx_fifo.rd_addr_gray_wr_r[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[4] Q=tx_fifo.rd_addr_gray_wr_r[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[3] Q=tx_fifo.rd_addr_gray_wr_r[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[2] Q=tx_fifo.rd_addr_gray_wr_r[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[1] Q=tx_fifo.rd_addr_gray_wr_r[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[5] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[2] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[1] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_8_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111101000101 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001101001 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000100011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" +.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011111101 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I2=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000111100000011 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[0] E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] I2=i_button_SB_LUT4_I1_I0[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[0] O=sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 -.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D E=sys_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=sys_ctrl_ins.o_data_out[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D E=sys_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=sys_ctrl_ins.o_data_out[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] I3=sys_ctrl_ins.tx_sample_gap[2] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D E=sys_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=sys_ctrl_ins.o_data_out[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] I3=sys_ctrl_ins.tx_sample_gap[1] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D E=sys_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=sys_ctrl_ins.o_data_out[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.tx_sample_gap[0] I3=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[3] I3=sys_ctrl_ins.tx_sample_gap[3] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[3] I1=w_tx_data_io_SB_LUT4_I3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=io_ctrl_ins.o_data_out[3] O=r_tx_data_SB_DFFE_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[2] I1=w_tx_data_io_SB_LUT4_I3_O[1] I2=w_tx_data_io_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[3] O=r_tx_data_SB_DFFE_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100011111111 -.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[0] I1=w_tx_data_io_SB_LUT4_I3_O[1] I2=w_tx_data_io_SB_LUT4_I3_O[2] I3=w_tx_data_io_SB_LUT4_I3_O[3] O=r_tx_data_SB_DFFE_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100011111111 -.gate SB_LUT4 I0=$false I1=w_tx_data_io_SB_LUT4_I3_O[1] I2=sys_ctrl_ins.o_data_out[1] I3=smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[2] O=r_tx_data_SB_DFFE_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E Q=sys_ctrl_ins.tx_sample_gap[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E Q=sys_ctrl_ins.tx_sample_gap[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E Q=sys_ctrl_ins.tx_sample_gap[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E Q=sys_ctrl_ins.tx_sample_gap[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:132.12-146.4|sys_ctrl.v:52.5-96.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFNSS C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105" -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] I1=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] I2=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] I3=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=$false I1=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] I2=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] I3=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] I3=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr[4] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr[7] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[5] I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr[6] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] I1=tx_fifo.wr_addr_gray_rd_r[7] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=lvds_tx_inst.r_pulled I3=tx_fifo.empty_o O=tx_fifo.empty_o_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110100000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[1] I1=tx_fifo.rd_addr[1] I2=tx_fifo.rd_addr[2] I3=tx_fifo.empty_o_SB_LUT4_I3_O[3] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] I1=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] I2=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2] I3=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=tx_fifo.rd_addr[0] I1=tx_fifo.wr_addr_gray_rd_r[0] I2=tx_fifo.rd_addr[1] I3=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr[5] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] I3=tx_fifo.wr_addr_gray_rd_r[8] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011101010100011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[7] I3=tx_fifo.rd_addr[7] O=tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.full_o O=tx_fifo.full_o_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] I3=tx_fifo.wr_addr_gray_rd_r[4] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[0] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_rd_r[5] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[1] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=lvds_tx_inst.r_pulled_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I2_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000001001 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[0] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] I0=$false I1=tx_fifo.rd_addr[8] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=tx_fifo.rd_addr[7] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=tx_fifo.rd_addr[6] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=tx_fifo.rd_addr[5] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=tx_fifo.rd_addr[4] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=tx_fifo.rd_addr[3] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=tx_fifo.rd_addr[2] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=tx_fifo.rd_addr[1] -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[8] Q=tx_fifo.rd_addr_gray_wr[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[7] Q=tx_fifo.rd_addr_gray_wr[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[6] Q=tx_fifo.rd_addr_gray_wr[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[5] Q=tx_fifo.rd_addr_gray_wr[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[4] Q=tx_fifo.rd_addr_gray_wr[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[3] Q=tx_fifo.rd_addr_gray_wr[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[2] Q=tx_fifo.rd_addr_gray_wr[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[1] Q=tx_fifo.rd_addr_gray_wr[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[0] Q=tx_fifo.rd_addr_gray_wr[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[9] Q=tx_fifo.rd_addr_gray_wr_r[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[8] Q=tx_fifo.rd_addr_gray_wr_r[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[7] Q=tx_fifo.rd_addr_gray_wr_r[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[6] Q=tx_fifo.rd_addr_gray_wr_r[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[5] Q=tx_fifo.rd_addr_gray_wr_r[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[4] Q=tx_fifo.rd_addr_gray_wr_r[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[3] Q=tx_fifo.rd_addr_gray_wr_r[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[2] Q=tx_fifo.rd_addr_gray_wr_r[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[1] Q=tx_fifo.rd_addr_gray_wr_r[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] I1=tx_fifo.rd_addr_gray_wr_r[3] I2=tx_fifo.rd_addr_gray_wr_r[6] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011000010111011 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] I1=tx_fifo.rd_addr_gray_wr_r[5] I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010001000001 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] I2=tx_fifo.rd_addr_gray_wr_r[7] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000001001 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] O=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.param LUT_INIT 1100000000000000 +.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] I3=tx_fifo.rd_addr_gray_wr_r[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O[3] +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I2=$true I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I2_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.rd_addr_gray_wr_r[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1011000000001011 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[1] I1=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] I2=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] I3=tx_fifo.full_o_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[0] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] I0=$false I1=tx_fifo.wr_addr[8] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] I0=$false I1=tx_fifo.wr_addr[7] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] I0=$false I1=tx_fifo.wr_addr[6] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] I0=$false I1=tx_fifo.wr_addr[5] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] I0=$false I1=tx_fifo.wr_addr[4] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] I0=$false I1=tx_fifo.wr_addr[3] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] I0=$false I1=tx_fifo.wr_addr[2] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] I0=$false I1=tx_fifo.wr_addr[1] -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100010000010 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=tx_fifo.wr_addr[8] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=tx_fifo.wr_addr[7] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=tx_fifo.wr_addr[6] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=tx_fifo.wr_addr[5] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=tx_fifo.wr_addr[4] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=tx_fifo.wr_addr[3] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=tx_fifo.wr_addr[2] -.attr src "top.v:403.5-419.4|complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:403.5-419.4|complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I1=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.r_state_if[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011000010111111 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.param LUT_INIT 1010101000101010 +.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] I2=$true I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001000101000 +.gate SB_CARRY CI=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 CO=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I1=$true +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101100000000 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D +.param LUT_INIT 0101000111011101 +.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100111100000000 -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] I1=$false I2=$true I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001011001101001 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_phase_count[1] I2=$true I3=lvds_rx_09_inst.r_phase_count[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:312.11-323.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=lvds_rx_09_inst.r_phase_count[0] CO=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] I0=lvds_rx_09_inst.r_phase_count[1] I1=$true -.attr src "top.v:312.11-323.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101100000000 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] O=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=w_lvds_rx_09_d1 I2=w_lvds_rx_09_d0 I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d1_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111100010000 -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d1_SB_LUT4_I1_O[2] I3=i_rst_b O=w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.param LUT_INIT 0000000011111101 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] O=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] I1=lvds_rx_09_inst.r_state_if[0] I2=lvds_rx_09_inst.r_state_if[1] I3=w_lvds_rx_09_d1 O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111111100000000 -.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=w_lvds_rx_24_d0 I2=w_lvds_rx_24_d1 I3=lvds_rx_24_inst.r_state_if[0] O=w_lvds_rx_24_d0_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111100010000 -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d0_SB_LUT4_I1_O[0] I3=i_rst_b O=w_lvds_rx_24_d0_SB_LUT4_I1_O_SB_LUT4_I2_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d1 I3=w_lvds_rx_24_d0 O=w_lvds_rx_24_d1_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=w_lvds_rx_24_d1_SB_LUT4_I2_O[0] I1=rx_fifo.full_o_SB_LUT4_I0_I3[1] I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.r_state_if[1] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011000010111111 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D E=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D E=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=rx_fifo.full_o_SB_LUT4_I0_I3[1] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] I3=lvds_rx_24_inst.r_state_if[0] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101100000000 -.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D E=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O Q=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=rx_fifo.full_o_SB_LUT4_I0_I3[1] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] I3=lvds_rx_24_inst.r_state_if[0] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100111100000000 -.gate SB_LUT4 I0=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] I1=$false I2=$true I3=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001011001101001 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_phase_count[1] I2=$true I3=lvds_rx_24_inst.r_phase_count[0] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:325.11-338.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=lvds_rx_24_inst.r_phase_count[0] CO=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] I0=lvds_rx_24_inst.r_phase_count[1] I1=$true -.attr src "top.v:325.11-338.4|lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=rx_fifo.full_o_SB_LUT4_I0_I3[1] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] I3=lvds_rx_24_inst.r_state_if[0] O=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101100000000 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] O=rx_fifo.full_o_SB_LUT4_I0_I3[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_I3[1] I1=lvds_rx_24_inst.r_state_if[0] I2=lvds_rx_24_inst.r_state_if[1] I3=w_lvds_rx_24_d1 O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001111111 -.gate SB_DFFESS C=r_counter D=w_tx_data_io_SB_DFFESS_Q_D E=w_tx_data_io_SB_DFFESS_Q_E Q=w_tx_data_io S=w_tx_data_io_SB_DFFESS_Q_S -.attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:155.11-182.4|io_ctrl.v:111.5-206.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[0] I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=io_ctrl_ins.led0_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.led0_state_SB_LUT4_I0_O[3] O=w_tx_data_io_SB_DFFESS_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000111111111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] I2=i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[1] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[1] O=w_tx_data_io_SB_DFFESS_Q_S -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 -.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I1_O[0] I1=smi_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I1_O[2] I3=w_tx_data_io O=w_tx_data_io_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011101110111 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=smi_ctrl_ins.i_cs I2=sys_ctrl_ins.i_cs I3=spi_if_ins.o_cs[3] O=w_tx_data_io_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000100000000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=smi_ctrl_ins.i_cs I2=spi_if_ins.o_cs[3] I3=sys_ctrl_ins.i_cs O=w_tx_data_io_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111111101000 -.names spi_if_ins.o_ioc[0] i_button_SB_LUT4_I1_I0_SB_LUT4_O_I3[0] +.param LUT_INIT 0000000011110000 +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[12] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[2] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.SCKr_SB_LUT4_I0_O[2] +.names i_config[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[4] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] lvds_tx_inst.r_pulled_SB_LUT4_I3_O[2] +.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0] 1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[1] +.names tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] 1 1 -.names i_rst_b w_lvds_rx_24_d0_SB_LUT4_I1_O[1] +.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] +.names smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] 1 1 -.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[3] 1 1 -.names sys_ctrl_ins.i_cs sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.names rx_fifo.rd_addr[7] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.o_load_cmd sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2[2] +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] 1 1 -.names smi_ctrl_ins.i_smi_data_in[7] smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.names rx_fifo.rd_addr[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] 1 1 -.names smi_ctrl_ins.tx_reg_state[3] smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] 1 1 -.names i_rst_b smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[1] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0] 1 1 -.names spi_if_ins.o_ioc[2] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3[0] +.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] 1 1 -.names io_ctrl_ins.debug_mode[1] io_ctrl_ins.debug_mode_SB_LUT4_I0_O[0] +.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[2] +.names rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] 1 1 -.names tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[0] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.names $true w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[3] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] 1 1 -.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] 1 1 -.names i_rst_b spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[3] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[0] +.names io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] 1 1 -.names rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[1] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] 1 1 -.names rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3[2] +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +1 1 +.names io_ctrl_ins.pmod_dir_state[0] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[3] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[2] +1 1 +.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] +1 1 +.names io_ctrl_ins.mixer_en_state io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[0] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] +1 1 +.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +1 1 +.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +1 1 +.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[3] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +1 1 +.names tx_fifo.rd_addr[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[1] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] +1 1 +.names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0] +1 1 +.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_D[0] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[1] +1 1 +.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +1 1 +.names tx_fifo.rd_addr[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[1] +1 1 +.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0] +1 1 +.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[1] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[1] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[0] +1 1 +.names io_ctrl_ins.pmod_dir_state[4] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[1] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3] +1 1 +.names spi_if_ins.o_ioc[1] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.o_ioc[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[3] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] +1 1 +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0] +1 1 +.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I1_I3[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[2] +1 1 +.names spi_if_ins.o_ioc[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O[0] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_6_D[1] +1 1 +.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0] +1 1 +.names spi_if_ins.o_ioc[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[0] +1 1 +.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[0] +1 1 +.names $true rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[2] +1 1 +.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +1 1 +.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +1 1 +.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +1 1 +.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0] +1 1 +.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1] +1 1 +.names rx_fifo.wr_addr[2] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] +1 1 +.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +1 1 +.names o_led1 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] +1 1 +.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +1 1 +.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +1 1 +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +1 1 +.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D[1] +1 1 +.names tx_fifo.rd_addr_gray[9] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[1] +1 1 +.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[2] +1 1 +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +1 1 +.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0] +1 1 +.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +1 1 +.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +1 1 +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +1 1 +.names i_rst_b io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[1] +1 1 +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[0] +1 1 +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +1 1 +.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +1 1 +.names lvds_rx_24_inst.o_fifo_data[21] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +1 1 +.names tx_fifo.rd_addr[7] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[0] +1 1 +.names tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[1] 1 1 .names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] 1 1 .names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.names rx_fifo.rd_addr_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] 1 1 -.names io_ctrl_ins.pmod_state[1] io_ctrl_ins.led1_state_SB_LUT4_I0_O[0] +.names rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] 1 1 -.names spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] io_ctrl_ins.led1_state_SB_LUT4_I0_O[1] +.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3] +.names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[0] +.names io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -1 1 -.names spi_if_ins.o_ioc[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[2] -1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] -1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] -1 1 -.names io_ctrl_ins.rf_mode[1] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[1] -1 1 -.names io_ctrl_ins.rf_pin_state[5] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[2] -1 1 -.names io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[3] -1 1 -.names tx_fifo.wr_addr[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[2] -1 1 -.names rx_fifo.wr_en_i rx_fifo.full_o_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.full_o_SB_LUT4_I3_O[2] -1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[0] -1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2[1] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2[1] -1 1 -.names sys_ctrl_ins.i_cs sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[1] -1 1 -.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_cs_SB_LUT4_I2_I1[2] -1 1 -.names spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] -1 1 -.names io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] -1 1 -.names io_ctrl_ins.rf_pin_state[6] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[1] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] -1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[9] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] -1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[2] -1 1 -.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] -1 1 -.names io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1] -1 1 -.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I1_O[1] -1 1 -.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I1_O[3] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] -1 1 -.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] -1 1 -.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[3] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[0] -1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[1] -1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_I2[3] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -1 1 -.names rx_fifo.rd_addr[5] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -1 1 -.names rx_fifo.rd_addr[4] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] -1 1 -.names tx_fifo.rd_addr[0] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[1] -1 1 -.names tx_fifo.rd_addr[1] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_1_I3[2] -1 1 -.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] -1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] -1 1 -.names rx_fifo.wr_addr[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] -1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[2] spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -1 1 -.names i_rst_b spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[2] -1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[6] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] -1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[14] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] -1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[2] -1 1 -.names rx_fifo.full_o_SB_LUT4_I0_I3[1] w_lvds_rx_24_d1_SB_LUT4_I2_O[1] -1 1 -.names lvds_rx_24_inst.r_state_if[0] w_lvds_rx_24_d1_SB_LUT4_I2_O[2] -1 1 -.names lvds_rx_24_inst.r_state_if[1] w_lvds_rx_24_d1_SB_LUT4_I2_O[3] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -1 1 -.names io_ctrl_ins.rf_mode[0] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -1 1 -.names io_ctrl_ins.rf_mode[2] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] -1 1 -.names io_ctrl_ins.rf_mode[1] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -1 1 -.names smi_ctrl_ins.i_smi_data_in[7] smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[0] -1 1 -.names smi_ctrl_ins.tx_reg_state[0] smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I3[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.full_o_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] tx_fifo.full_o_SB_LUT4_I3_O[1] -1 1 -.names tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] tx_fifo.full_o_SB_LUT4_I3_O[2] -1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -1 1 -.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] -1 1 -.names lvds_rx_09_inst.r_state_if[0] w_lvds_rx_09_d1_SB_LUT4_I1_O[0] -1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I3_I0[1] w_lvds_rx_09_d1_SB_LUT4_I1_O[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[1] -1 1 -.names tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -1 1 -.names tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] 1 1 .names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] +.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] 1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[1] 1 1 -.names rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[2] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[2] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I0[3] +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[2] 1 1 -.names rx_fifo.wr_en_i rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] 1 1 -.names io_ctrl_ins.pmod_state[4] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[2] 1 1 -.names spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] +.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2] +.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] 1 1 -.names tx_fifo.rd_addr_gray[9] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[5] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1[6] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] +.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] 1 1 -.names io_ctrl_ins.pmod_dir_state[5] io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[1] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] 1 1 -.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0[3] +.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1] +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2] +.names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3] +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[0] +.names io_pmod[6] lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D[2] +.names tx_fifo.wr_addr[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] 1 1 -.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.names tx_fifo.rd_addr_gray_wr_r[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[0] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] 1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O[3] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[5] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[13] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[2] +.names rx_fifo.rd_addr[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[2] 1 1 -.names io_ctrl_ins.rf_mode[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[1] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[7] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.names rx_fifo.rd_addr[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[15] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] +.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[1] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[2] +.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I2_O[2] +.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] 1 1 -.names lvds_rx_09_inst.r_state_if[1] w_lvds_rx_09_d1_SB_LUT4_I3_I0[0] +.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] 1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] w_lvds_rx_09_d1_SB_LUT4_I3_I0[2] +.names tx_fifo.rd_addr_gray_wr_r[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] 1 1 -.names lvds_rx_09_inst.r_state_if[0] w_lvds_rx_09_d1_SB_LUT4_I3_I0[3] +.names tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] 1 1 -.names lvds_rx_09_inst.r_state_if[1] w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names lvds_rx_09_inst.r_state_if[0] w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[3] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.names spi_if_ins.o_fetch_cmd io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[11] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.names sys_ctrl_ins.i_cs io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[1] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[2] +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] 1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[1] 1 1 -.names tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2] 1 1 -.names tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] +.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] 1 1 -.names lvds_rx_24_inst.r_state_if[1] rx_fifo.full_o_SB_LUT4_I0_I3[0] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I0_O[0] 1 1 -.names w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] rx_fifo.full_o_SB_LUT4_I0_I3[2] +.names w_lvds_rx_09_d0_SB_LUT4_I2_O[3] w_lvds_rx_09_d0_SB_LUT4_I0_O[2] 1 1 -.names lvds_rx_24_inst.r_state_if[0] rx_fifo.full_o_SB_LUT4_I0_I3[3] +.names io_ctrl_ins.pmod_dir_state[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2] 1 1 -.names w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_I2_SB_LUT4_O_I2[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[2] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[10] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[2] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_D[1] 1 1 -.names w_tx_data_io_SB_LUT4_I3_O[1] smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[0] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0] 1 1 -.names sys_ctrl_ins.o_data_out[1] smi_ctrl_ins.o_data_out_SB_LUT4_I1_1_O[1] +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr[7] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.names io_ctrl_ins.rx_h_state i_button_SB_LUT4_I0_O[0] 1 1 -.names rx_fifo.rd_addr[8] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] i_button_SB_LUT4_I0_O[1] 1 1 -.names io_ctrl_ins.pmod_state[0] io_ctrl_ins.led0_state_SB_LUT4_I0_O[0] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] io_ctrl_ins.led0_state_SB_LUT4_I0_O[1] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[0] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] 1 1 -.names smi_ctrl_ins.r_fifo_pulled_data[8] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[2] +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] 1 1 -.names io_ctrl_ins.pmod_state[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] +.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.empty_o_SB_LUT4_I0_O[1] 1 1 -.names rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[0] 1 1 -.names rx_fifo.rd_addr[5] rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I2[3] +.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_1_O_SB_LUT4_I3_O[3] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.empty_o_SB_LUT4_I3_O[0] +.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] 1 1 -.names tx_fifo.rd_addr[1] tx_fifo.empty_o_SB_LUT4_I3_O[1] +.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] 1 1 -.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_LUT4_I3_O[2] +.names rx_fifo.rd_addr[5] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[0] 1 1 -.names sys_ctrl_ins.o_data_out[2] smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[0] +.names rx_fifo.rd_addr[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[1] 1 1 -.names w_tx_data_io_SB_LUT4_I3_O[1] smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[1] -1 1 -.names w_tx_data_io_SB_LUT4_I3_O[2] smi_ctrl_ins.o_data_out_SB_LUT4_I1_O[2] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[0] -1 1 -.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[1] -1 1 -.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I3_I1_SB_LUT4_O_I2[3] -1 1 -.names sys_ctrl_ins.o_data_out[0] w_tx_data_io_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[1] -1 1 -.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[2] -1 1 -.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0[3] -1 1 -.names i_config[2] i_button_SB_LUT4_I1_I0[1] -1 1 -.names spi_if_ins.o_load_cmd_SB_LUT4_I2_O[0] i_button_SB_LUT4_I1_I0[2] -1 1 -.names io_ctrl_ins.pmod_state[5] i_button_SB_LUT4_I1_I0[3] -1 1 -.names rx_fifo.empty_o rx_fifo.empty_o_SB_LUT4_I3_I1[2] -1 1 -.names $true w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[0] -1 1 -.names lvds_rx_09_inst.r_phase_count[0] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -1 1 -.names $true w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[0] -1 1 -.names lvds_rx_24_inst.r_phase_count[0] w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -1 1 -.names $false rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[0] -1 1 -.names rx_fifo.wr_addr[0] rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[1] -1 1 -.names $false rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[0] -1 1 -.names rx_fifo.wr_addr[1] rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[1] -1 1 -.names $false rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[0] -1 1 -.names rx_fifo.rd_addr[0] rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[1] -1 1 -.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D[1] -1 1 -.names smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D[0] smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D[0] -1 1 -.names $false spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -1 1 -.names spi_if_ins.spi.r_rx_bit_count[0] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[1] -1 1 -.names spi_if_ins.spi.r_rx_bit_count[1] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[1] -1 1 -.names spi_if_ins.spi.r_rx_bit_count[2] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[2] -1 1 -.names spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[0] -1 1 -.names $true spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] -1 1 -.names spi_if_ins.spi.r_tx_bit_count[0] spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] -1 1 -.names $false tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[0] -1 1 -.names tx_fifo.wr_addr[0] tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[1] -1 1 -.names $false tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[0] -1 1 -.names tx_fifo.wr_addr[1] tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[1] -1 1 -.names $false tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[0] -1 1 -.names tx_fifo.rd_addr[0] tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[1] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[0] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[1] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[2] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[4] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[5] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[7] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[8] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[10] -1 1 -.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[11] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[0] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[1] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[2] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[3] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[4] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[5] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[6] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[7] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[15] r_tx_data_SB_DFFESR_Q_D[8] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[9] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[15] r_tx_data_SB_DFFESR_Q_D[10] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[11] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[12] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[15] r_tx_data_SB_DFFESR_Q_D[13] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[14] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[19] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[20] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[21] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[22] -1 1 -.names $false r_tx_data_SB_DFFESR_Q_D[23] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[27] r_tx_data_SB_DFFESR_Q_3_D[3] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[28] r_tx_data_SB_DFFESR_Q_3_D[4] -1 1 -.names r_tx_data_SB_DFFESR_Q_D[30] r_tx_data_SB_DFFESR_Q_3_D[6] -1 1 -.names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[30] rx_fifo.mem_i.0.3_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[29] rx_fifo.mem_i.0.3_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13] -1 1 -.names rx_fifo.rd_data_o[20] rx_fifo.mem_i.0.1_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[22] rx_fifo.mem_i.0.1_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[21] rx_fifo.mem_i.0.1_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] -1 1 -.names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[25] rx_fifo.mem_i.0.2_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[27] rx_fifo.mem_i.0.2_RDATA[13] -1 1 -.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2] 1 1 .names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1] 1 1 @@ -4207,6 +4250,14 @@ 1 1 .names rx_fifo.rd_data_o[3] rx_fifo.mem_q.0.0_RDATA[13] 1 1 +.names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[10] rx_fifo.mem_q.0.2_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[9] rx_fifo.mem_q.0.2_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13] +1 1 .names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1] 1 1 .names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5] @@ -4215,13 +4266,21 @@ 1 1 .names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13] 1 1 -.names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1] +.names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1] 1 1 -.names rx_fifo.rd_data_o[10] rx_fifo.mem_q.0.2_RDATA[5] +.names rx_fifo.rd_data_o[30] rx_fifo.mem_i.0.3_RDATA[5] 1 1 -.names rx_fifo.rd_data_o[9] rx_fifo.mem_q.0.2_RDATA[9] +.names rx_fifo.rd_data_o[29] rx_fifo.mem_i.0.3_RDATA[9] 1 1 -.names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13] +.names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] 1 1 .names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1] 1 1 @@ -4231,7 +4290,25 @@ 1 1 .names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13] 1 1 -.names i_smi_a3 channel +.names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[25] rx_fifo.mem_i.0.2_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[27] rx_fifo.mem_i.0.2_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[20] rx_fifo.mem_i.0.1_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[22] rx_fifo.mem_i.0.1_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[21] rx_fifo.mem_i.0.1_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +1 1 +.names o_led1 channel 1 1 .names spi_if_ins.spi.o_spi_miso int_miso 1 1 @@ -4279,31 +4356,17 @@ 1 1 .names r_counter io_ctrl_ins.i_sys_clk 1 1 -.names w_tx_data_io io_ctrl_ins.o_data_out[0] -1 1 -.names io_ctrl_ins.led0_state io_ctrl_ins.o_led0 -1 1 -.names io_ctrl_ins.led1_state io_ctrl_ins.o_led1 -1 1 .names $true io_ctrl_ins.o_mixer_en 1 1 .names $false io_ctrl_ins.o_mixer_fm 1 1 -.names io_ctrl_ins.pmod_state[0] io_ctrl_ins.o_pmod[0] +.names io_pmod[0] io_ctrl_ins.o_pmod[0] 1 1 -.names io_ctrl_ins.pmod_state[1] io_ctrl_ins.o_pmod[1] +.names io_pmod[1] io_ctrl_ins.o_pmod[1] 1 1 -.names io_ctrl_ins.pmod_state[2] io_ctrl_ins.o_pmod[2] +.names io_pmod[2] io_ctrl_ins.o_pmod[2] 1 1 -.names io_ctrl_ins.pmod_state[3] io_ctrl_ins.o_pmod[3] -1 1 -.names io_ctrl_ins.pmod_state[4] io_ctrl_ins.o_pmod[4] -1 1 -.names io_ctrl_ins.pmod_state[5] io_ctrl_ins.o_pmod[5] -1 1 -.names io_ctrl_ins.pmod_state[6] io_ctrl_ins.o_pmod[6] -1 1 -.names io_ctrl_ins.pmod_state[7] io_ctrl_ins.o_pmod[7] +.names io_pmod[3] io_ctrl_ins.o_pmod[3] 1 1 .names io_ctrl_ins.rx_h_state io_ctrl_ins.o_rx_h_tx_l 1 1 @@ -4319,9 +4382,17 @@ 1 1 .names io_ctrl_ins.tr_vc_2_state io_ctrl_ins.o_tr_vc2 1 1 -.names lvds_rx_09_inst.i_ddr_clk lvds_clock +.names io_pmod[0] io_ctrl_ins.pmod_state[0] 1 1 -.names lvds_rx_09_inst.i_ddr_clk lvds_clock_buf +.names io_pmod[1] io_ctrl_ins.pmod_state[1] +1 1 +.names io_pmod[2] io_ctrl_ins.pmod_state[2] +1 1 +.names io_pmod[3] io_ctrl_ins.pmod_state[3] +1 1 +.names lvds_clock lvds_clock_buf +1 1 +.names lvds_clock lvds_rx_09_inst.i_ddr_clk 1 1 .names w_lvds_rx_09_d1 lvds_rx_09_inst.i_ddr_data[0] 1 1 @@ -4331,31 +4402,15 @@ 1 1 .names i_rst_b lvds_rx_09_inst.i_rst_b 1 1 -.names $false lvds_rx_09_inst.i_sync_input +.names lvds_clock lvds_rx_09_inst.o_fifo_write_clk 1 1 -.names lvds_rx_09_inst.r_state_if[0] lvds_rx_09_inst.o_debug_state[0] -1 1 -.names lvds_rx_09_inst.r_state_if[1] lvds_rx_09_inst.o_debug_state[1] -1 1 -.names lvds_rx_09_inst.i_ddr_clk lvds_rx_09_inst.o_fifo_write_clk -1 1 -.names $false lvds_rx_09_inst.r_sync_input -1 1 -.names lvds_rx_09_inst.i_ddr_clk lvds_rx_24_inst.i_ddr_clk +.names lvds_clock lvds_rx_24_inst.i_ddr_clk 1 1 .names rx_fifo.full_o lvds_rx_24_inst.i_fifo_full 1 1 .names i_rst_b lvds_rx_24_inst.i_rst_b 1 1 -.names $false lvds_rx_24_inst.i_sync_input -1 1 -.names lvds_rx_24_inst.r_state_if[0] lvds_rx_24_inst.o_debug_state[0] -1 1 -.names lvds_rx_24_inst.r_state_if[1] lvds_rx_24_inst.o_debug_state[1] -1 1 -.names lvds_rx_09_inst.i_ddr_clk lvds_rx_24_inst.o_fifo_write_clk -1 1 -.names $false lvds_rx_24_inst.r_sync_input +.names lvds_clock lvds_rx_24_inst.o_fifo_write_clk 1 1 .names $undef lvds_tx_inst.i_debug_lb 1 1 @@ -4371,8 +4426,6 @@ 1 1 .names $undef lvds_tx_inst.i_sample_gap[3] 1 1 -.names $false lvds_tx_inst.i_sync_input -1 1 .names $false lvds_tx_inst.o_ddr_data[0] 1 1 .names $false lvds_tx_inst.o_ddr_data[1] @@ -4449,11 +4502,9 @@ 1 1 .names $false lvds_tx_inst.r_state 1 1 -.names lvds_rx_09_inst.i_ddr_clk o_iq_tx_clk_p +.names lvds_clock o_iq_tx_clk_p 1 1 -.names i_smi_a2 o_led0 -1 1 -.names i_smi_a3 o_led1 +.names smi_ctrl_ins.r_dir o_led0 1 1 .names $undef o_mixer_en 1 1 @@ -4487,7 +4538,7 @@ 1 1 .names rx_fifo.wr_addr_gray[9] rx_fifo.wr_addr[9] 1 1 -.names lvds_rx_09_inst.i_ddr_clk rx_fifo.wr_clk_i +.names lvds_clock rx_fifo.wr_clk_i 1 1 .names i_rst_b rx_fifo.wr_rst_b_i 1 1 @@ -4605,7 +4656,7 @@ 1 1 .names $false smi_ctrl_ins.int_cnt_rx[2] 1 1 -.names smi_ctrl_ins.r_channel smi_ctrl_ins.o_channel +.names o_led1 smi_ctrl_ins.o_channel 1 1 .names $false smi_ctrl_ins.o_data_out[3] 1 1 @@ -4617,7 +4668,7 @@ 1 1 .names $false smi_ctrl_ins.o_data_out[7] 1 1 -.names rx_fifo.rd_en_i smi_ctrl_ins.o_rx_fifo_pull +.names smi_ctrl_ins.r_dir smi_ctrl_ins.o_dir 1 1 .names r_counter smi_ctrl_ins.o_tx_fifo_clock 1 1 @@ -4685,6 +4736,8 @@ 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[31] 1 1 +.names o_led1 smi_ctrl_ins.r_channel +1 1 .names $false smi_ctrl_ins.r_fifo_pushed_data[0] 1 1 .names $false smi_ctrl_ins.r_fifo_pushed_data[1] @@ -4863,14 +4916,6 @@ 1 1 .names r_counter sys_ctrl_ins.i_sys_clk 1 1 -.names $false sys_ctrl_ins.o_data_out[4] -1 1 -.names $false sys_ctrl_ins.o_data_out[5] -1 1 -.names $false sys_ctrl_ins.o_data_out[6] -1 1 -.names $false sys_ctrl_ins.o_data_out[7] -1 1 .names $undef sys_ctrl_ins.o_debug_loopback_tx 1 1 .names $undef sys_ctrl_ins.o_tx_sample_gap[0] @@ -5061,11 +5106,7 @@ 1 1 .names lvds_rx_09_inst.o_fifo_data[30] w_rx_09_fifo_data[30] 1 1 -.names lvds_rx_09_inst.o_fifo_data[31] w_rx_09_fifo_data[31] -1 1 -.names lvds_rx_09_inst.o_fifo_push w_rx_09_fifo_push -1 1 -.names lvds_rx_09_inst.i_ddr_clk w_rx_09_fifo_write_clk +.names lvds_clock w_rx_09_fifo_write_clk 1 1 .names lvds_rx_24_inst.o_fifo_data[0] w_rx_24_fifo_data[0] 1 1 @@ -5131,9 +5172,7 @@ 1 1 .names lvds_rx_24_inst.o_fifo_data[31] w_rx_24_fifo_data[31] 1 1 -.names lvds_rx_24_inst.o_fifo_push w_rx_24_fifo_push -1 1 -.names lvds_rx_09_inst.i_ddr_clk w_rx_24_fifo_write_clk +.names lvds_clock w_rx_24_fifo_write_clk 1 1 .names spi_if_ins.o_data_in[0] w_rx_data[0] 1 1 @@ -5151,76 +5190,10 @@ 1 1 .names spi_if_ins.o_data_in[7] w_rx_data[7] 1 1 -.names rx_fifo.wr_data_i[0] w_rx_fifo_data[0] -1 1 -.names rx_fifo.wr_data_i[1] w_rx_fifo_data[1] -1 1 -.names rx_fifo.wr_data_i[2] w_rx_fifo_data[2] -1 1 -.names rx_fifo.wr_data_i[3] w_rx_fifo_data[3] -1 1 -.names rx_fifo.wr_data_i[4] w_rx_fifo_data[4] -1 1 -.names rx_fifo.wr_data_i[5] w_rx_fifo_data[5] -1 1 -.names rx_fifo.wr_data_i[6] w_rx_fifo_data[6] -1 1 -.names rx_fifo.wr_data_i[7] w_rx_fifo_data[7] -1 1 -.names rx_fifo.wr_data_i[8] w_rx_fifo_data[8] -1 1 -.names rx_fifo.wr_data_i[9] w_rx_fifo_data[9] -1 1 -.names rx_fifo.wr_data_i[10] w_rx_fifo_data[10] -1 1 -.names rx_fifo.wr_data_i[11] w_rx_fifo_data[11] -1 1 -.names rx_fifo.wr_data_i[12] w_rx_fifo_data[12] -1 1 -.names rx_fifo.wr_data_i[13] w_rx_fifo_data[13] -1 1 -.names rx_fifo.wr_data_i[14] w_rx_fifo_data[14] -1 1 -.names rx_fifo.wr_data_i[15] w_rx_fifo_data[15] -1 1 -.names rx_fifo.wr_data_i[16] w_rx_fifo_data[16] -1 1 -.names rx_fifo.wr_data_i[17] w_rx_fifo_data[17] -1 1 -.names rx_fifo.wr_data_i[18] w_rx_fifo_data[18] -1 1 -.names rx_fifo.wr_data_i[19] w_rx_fifo_data[19] -1 1 -.names rx_fifo.wr_data_i[20] w_rx_fifo_data[20] -1 1 -.names rx_fifo.wr_data_i[21] w_rx_fifo_data[21] -1 1 -.names rx_fifo.wr_data_i[22] w_rx_fifo_data[22] -1 1 -.names rx_fifo.wr_data_i[23] w_rx_fifo_data[23] -1 1 -.names rx_fifo.wr_data_i[24] w_rx_fifo_data[24] -1 1 -.names rx_fifo.wr_data_i[25] w_rx_fifo_data[25] -1 1 -.names rx_fifo.wr_data_i[26] w_rx_fifo_data[26] -1 1 -.names rx_fifo.wr_data_i[27] w_rx_fifo_data[27] -1 1 -.names rx_fifo.wr_data_i[28] w_rx_fifo_data[28] -1 1 -.names rx_fifo.wr_data_i[29] w_rx_fifo_data[29] -1 1 -.names rx_fifo.wr_data_i[30] w_rx_fifo_data[30] -1 1 -.names rx_fifo.wr_data_i[31] w_rx_fifo_data[31] -1 1 .names rx_fifo.empty_o w_rx_fifo_empty 1 1 .names rx_fifo.full_o w_rx_fifo_full 1 1 -.names rx_fifo.rd_en_i w_rx_fifo_pull -1 1 .names rx_fifo.rd_data_o[0] w_rx_fifo_pulled_data[0] 1 1 .names rx_fifo.rd_data_o[1] w_rx_fifo_pulled_data[1] @@ -5285,11 +5258,13 @@ 1 1 .names rx_fifo.rd_data_o[31] w_rx_fifo_pulled_data[31] 1 1 -.names rx_fifo.wr_en_i w_rx_fifo_push +.names lvds_clock w_rx_fifo_write_clk 1 1 -.names lvds_rx_09_inst.i_ddr_clk w_rx_fifo_write_clk +.names lvds_rx_09_inst.i_sync_input w_rx_sync_input_09 1 1 -.names i_smi_a2 w_smi_data_direction +.names lvds_rx_24_inst.i_sync_input w_rx_sync_input_24 +1 1 +.names smi_ctrl_ins.r_dir w_smi_data_direction 1 1 .names smi_ctrl_ins.i_smi_data_in[0] w_smi_data_input[0] 1 1 @@ -5323,20 +5298,28 @@ 1 1 .names smi_ctrl_ins.o_smi_data_out[7] w_smi_data_output[7] 1 1 +.names io_ctrl_ins.o_data_out[0] w_tx_data_io[0] +1 1 +.names io_ctrl_ins.o_data_out[1] w_tx_data_io[1] +1 1 +.names io_ctrl_ins.o_data_out[2] w_tx_data_io[2] +1 1 +.names io_ctrl_ins.o_data_out[3] w_tx_data_io[3] +1 1 +.names io_ctrl_ins.o_data_out[4] w_tx_data_io[4] +1 1 +.names io_ctrl_ins.o_data_out[5] w_tx_data_io[5] +1 1 +.names io_ctrl_ins.o_data_out[6] w_tx_data_io[6] +1 1 +.names io_ctrl_ins.o_data_out[7] w_tx_data_io[7] +1 1 .names smi_ctrl_ins.o_data_out[0] w_tx_data_smi[0] 1 1 .names smi_ctrl_ins.o_data_out[1] w_tx_data_smi[1] 1 1 .names smi_ctrl_ins.o_data_out[2] w_tx_data_smi[2] 1 1 -.names sys_ctrl_ins.o_data_out[0] w_tx_data_sys[0] -1 1 -.names sys_ctrl_ins.o_data_out[1] w_tx_data_sys[1] -1 1 -.names sys_ctrl_ins.o_data_out[2] w_tx_data_sys[2] -1 1 -.names sys_ctrl_ins.o_data_out[3] w_tx_data_sys[3] -1 1 .names r_counter w_tx_fifo_clock 1 1 .names $false w_tx_fifo_data[0] diff --git a/firmware/top.json b/firmware/top.json index 6c80c72..2cc1fcb 100644 --- a/firmware/top.json +++ b/firmware/top.json @@ -1,6 +1,1593 @@ { - "creator": "Yosys 0.29+42 (git sha1 43b807fe6, gcc 10.2.1-6 -fPIC -Os)", + "creator": "Yosys 0.39+0 (git sha1 18cec2d9a, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)", "modules": { + "$__ABC9_DELAY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": 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"smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" }, "port_directions": { "C": "input", @@ -23768,11 +26994,11 @@ "R": "input" }, "connections": { - "C": [ 734 ], - "D": [ 613 ], - "E": [ 739 ], - "Q": [ 783 ], - "R": [ 59 ] + "C": [ 796 ], + "D": [ 646 ], + "E": [ 60 ], + "Q": [ 831 ], + "R": [ 61 ] } }, "smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_21": { @@ -23782,7 +27008,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:421.12-453.4|smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" + "src": "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" }, "port_directions": { "C": "input", @@ -23792,11 +27018,11 @@ "R": "input" }, "connections": { - "C": [ 734 ], - "D": [ 605 ], - "E": [ 739 ], - "Q": [ 788 ], - "R": [ 59 ] + "C": [ 796 ], + "D": [ 638 ], + "E": [ 60 ], + "Q": [ 839 ], + "R": [ 61 ] } }, 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@@ -25261,7 +28559,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:489.5-494.4" + "src": "top.v:521.5-526.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25272,10 +28570,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 881 ], - "D_OUT_0": [ 759 ], + "D_IN_0": [ 935 ], + "D_OUT_0": [ 836 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 37 ] + "PACKAGE_PIN": [ 39 ] } }, "smi_io3": { @@ -25287,7 +28585,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:498.5-503.4" + "src": "top.v:530.5-535.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25298,10 +28596,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 882 ], - "D_OUT_0": [ 757 ], + "D_IN_0": [ 936 ], + "D_OUT_0": [ 828 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 38 ] + "PACKAGE_PIN": [ 40 ] } }, "smi_io4": { @@ -25313,7 +28611,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:507.5-512.4" + "src": "top.v:539.5-544.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25324,10 +28622,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 883 ], - "D_OUT_0": [ 755 ], + "D_IN_0": [ 937 ], + "D_OUT_0": [ 820 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 39 ] + "PACKAGE_PIN": [ 41 ] } }, "smi_io5": { @@ -25339,7 +28637,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:516.5-521.4" + "src": "top.v:548.5-553.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25350,10 +28648,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 884 ], - "D_OUT_0": [ 753 ], + "D_IN_0": [ 938 ], + "D_OUT_0": [ 812 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 40 ] + "PACKAGE_PIN": [ 42 ] } }, "smi_io6": { @@ -25365,7 +28663,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:525.5-530.4" + "src": "top.v:557.5-562.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25376,10 +28674,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 885 ], - "D_OUT_0": [ 751 ], + "D_IN_0": [ 939 ], + "D_OUT_0": [ 804 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 41 ] + "PACKAGE_PIN": [ 43 ] } }, "smi_io7": { @@ -25391,7 +28689,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:534.5-539.4" + "src": "top.v:566.5-571.4" }, "port_directions": { "CLOCK_ENABLE": "input", @@ -25402,10 +28700,10 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 869 ], - "D_OUT_0": [ 749 ], + "D_IN_0": [ 923 ], + "D_OUT_0": [ 802 ], "OUTPUT_ENABLE": [ 31 ], - "PACKAGE_PIN": [ 42 ] + "PACKAGE_PIN": [ 44 ] } }, "spi_if_ins.o_cs_SB_DFFESR_Q": { @@ -25415,7 +28713,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -25425,64 +28723,14 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 886 ], - "E": [ 73 ], - "Q": [ 887 ], - "R": [ 75 ] + "C": [ 63 ], + "D": [ 940 ], + "E": [ 65 ], + "Q": [ 941 ], + "R": [ 67 ] } }, "spi_if_ins.o_cs_SB_DFFESR_Q_D_SB_LUT4_O": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000111100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ "0" ], - "I2": [ 888 ], - "I3": [ 889 ], - "O": [ 72 ] - } - }, - "spi_if_ins.o_cs_SB_DFFESR_Q_D_SB_LUT4_O_1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000111100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ "0" ], - "I2": [ 889 ], - "I3": [ 888 ], - "O": [ 732 ] - } - }, - "spi_if_ins.o_cs_SB_DFFESR_Q_D_SB_LUT4_O_2": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -25502,62 +28750,12 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 889 ], - "I3": [ 888 ], - "O": [ 886 ] + "I2": [ 68 ], + "I3": [ 69 ], + "O": [ 940 ] } }, - "spi_if_ins.o_cs_SB_LUT4_I1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000000100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 74 ], - "I1": [ 887 ], - "I2": [ 890 ], - "I3": [ 733 ], - "O": [ 745 ] - } - }, - "spi_if_ins.o_cs_SB_LUT4_I1_1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000000100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 733 ], - "I1": [ 887 ], - "I2": [ 890 ], - "I3": [ 74 ], - "O": [ 364 ] - } - }, - "spi_if_ins.o_cs_SB_LUT4_I2": { + "spi_if_ins.o_cs_SB_LUT4_I0": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -25575,18 +28773,142 @@ "O": "output" }, "connections": { - "I0": [ 74 ], - "I1": [ 733 ], - "I2": [ 887 ], - "I3": [ 890 ], - "O": [ 891 ] + "I0": [ 941 ], + "I1": [ 365 ], + "I2": [ 66 ], + "I3": [ 158 ], + "O": [ 942 ] } }, - "spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2": { + "spi_if_ins.o_cs_SB_LUT4_I0_1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000111100000000" + "LUT_INIT": "0000000000000100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 941 ], + "I1": [ 365 ], + "I2": [ 66 ], + "I3": [ 158 ], + "O": [ 402 ] + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_2": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000000000010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 941 ], + "I1": [ 365 ], + "I2": [ 66 ], + "I3": [ 158 ], + "O": [ 385 ] + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000000010111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 941 ], + "I1": [ 365 ], + "I2": [ 66 ], + "I3": [ 158 ], + "O": [ 376 ] + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q": { + "hide_name": 0, + "type": "SB_DFFER", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" + }, + "port_directions": { + "C": "input", + "D": "input", + "E": "input", + "Q": "output", + "R": "input" + }, + "connections": { + "C": [ 63 ], + "D": [ 168 ], + "E": [ 159 ], + "Q": [ 395 ], + "R": [ 61 ] + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_4": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000000010000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 941 ], + "I1": [ 365 ], + "I2": [ 66 ], + "I3": [ 158 ], + "O": [ 377 ] + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -25602,9 +28924,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 891 ], - "I3": [ 3 ], - "O": [ 355 ] + "I2": [ 3 ], + "I3": [ 942 ], + "O": [ 371 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q": { @@ -25614,7 +28936,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25623,10 +28945,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 892 ], - "E": [ 893 ], - "Q": [ 141 ] + "C": [ 63 ], + "D": [ 943 ], + "E": [ 944 ], + "Q": [ 139 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_1": { @@ -25636,7 +28958,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25645,10 +28967,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 888 ], - "E": [ 893 ], - "Q": [ 144 ] + "C": [ 63 ], + "D": [ 68 ], + "E": [ 944 ], + "Q": [ 141 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_2": { @@ -25658,7 +28980,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25667,10 +28989,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 889 ], - "E": [ 893 ], - "Q": [ 146 ] + "C": [ 63 ], + "D": [ 69 ], + "E": [ 944 ], + "Q": [ 142 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_3": { @@ -25680,7 +29002,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25689,10 +29011,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 894 ], - "E": [ 893 ], - "Q": [ 148 ] + "C": [ 63 ], + "D": [ 945 ], + "E": [ 944 ], + "Q": [ 91 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_4": { @@ -25702,7 +29024,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25711,10 +29033,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 895 ], - "E": [ 893 ], - "Q": [ 150 ] + "C": [ 63 ], + "D": [ 946 ], + "E": [ 944 ], + "Q": [ 92 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_5": { @@ -25724,7 +29046,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25733,10 +29055,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 896 ], - "E": [ 893 ], - "Q": [ 152 ] + "C": [ 63 ], + "D": [ 947 ], + "E": [ 944 ], + "Q": [ 84 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_6": { @@ -25746,7 +29068,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25755,10 +29077,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 897 ], - "E": [ 893 ], - "Q": [ 62 ] + "C": [ 63 ], + "D": [ 948 ], + "E": [ 944 ], + "Q": [ 87 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_7": { @@ -25768,7 +29090,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25777,10 +29099,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 898 ], - "E": [ 893 ], - "Q": [ 65 ] + "C": [ 63 ], + "D": [ 949 ], + "E": [ 944 ], + "Q": [ 89 ] } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q": { @@ -25790,7 +29112,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -25800,18 +29122,18 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 899 ], - "E": [ 900 ], - "Q": [ 81 ], - "R": [ 901 ] + "C": [ 63 ], + "D": [ 950 ], + "E": [ 951 ], + "Q": [ 95 ], + "R": [ 952 ] } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011111111" + "LUT_INIT": "1111111100001111" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -25827,16 +29149,41 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 902 ], - "I3": [ 903 ], - "O": [ 899 ] + "I2": [ 953 ], + "I3": [ 954 ], + "O": [ 950 ] + } + }, + "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_O_1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0011000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 953 ], + "I2": [ 955 ], + "I3": [ 956 ], + "O": [ 957 ] } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000110100000000" + "LUT_INIT": "1010100000100000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -25850,11 +29197,36 @@ "O": "output" }, "connections": { - "I0": [ 904 ], - "I1": [ 905 ], - "I2": [ 906 ], - "I3": [ 3 ], - "O": [ 900 ] + "I0": [ 3 ], + "I1": [ 958 ], + "I2": [ 959 ], + "I3": [ 960 ], + "O": [ 951 ] + } + }, + "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000011110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 943 ], + "I2": [ 953 ], + "I3": [ 954 ], + "O": [ 960 ] } }, "spi_if_ins.o_ioc_SB_DFFE_Q": { @@ -25864,7 +29236,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25873,10 +29245,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 894 ], - "E": [ 73 ], - "Q": [ 56 ] + "C": [ 63 ], + "D": [ 945 ], + "E": [ 65 ], + "Q": [ 171 ] } }, "spi_if_ins.o_ioc_SB_DFFE_Q_1": { @@ -25886,7 +29258,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25895,10 +29267,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 895 ], - "E": [ 73 ], - "Q": [ 57 ] + "C": [ 63 ], + "D": [ 946 ], + "E": [ 65 ], + "Q": [ 172 ] } }, "spi_if_ins.o_ioc_SB_DFFE_Q_2": { @@ -25908,7 +29280,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -25917,10 +29289,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": 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"port_directions": { "C": "input", @@ -25961,10 +29333,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 898 ], - "E": [ 73 ], - "Q": [ 52 ] + "C": [ 63 ], + "D": [ 949 ], + "E": [ 65 ], + "Q": [ 75 ] } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q": { @@ -25974,7 +29346,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -25984,36 +29356,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 902 ], - "E": [ 907 ], - "Q": [ 82 ], - "R": [ 901 ] - } - }, - "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0001000000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 902 ], - "I1": [ 903 ], - "I2": [ 904 ], - "I3": [ 3 ], - "O": [ 73 ] + "C": [ 63 ], + "D": [ 954 ], + "E": [ 961 ], + "Q": [ 94 ], + "R": [ 952 ] } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -26036,16 +29383,16 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 908 ], - "I3": [ 909 ], - "O": [ 902 ] + "I2": [ 955 ], + "I3": [ 956 ], + "O": [ 954 ] } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000001100000000" + "LUT_INIT": "0000000000110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26060,10 +29407,60 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 910 ], - "I2": [ 911 ], - "I3": [ 912 ], - "O": [ 907 ] + "I1": [ 962 ], + "I2": [ 963 ], + "I3": [ 964 ], + "O": [ 961 ] + } + }, + "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 3 ], + "I3": [ 959 ], + "O": [ 963 ] + } + }, + "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 958 ], + "I2": [ 954 ], + "I3": [ 957 ], + "O": [ 964 ] } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_R_SB_LUT4_O": { @@ -26087,83 +29484,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 904 ], - "O": [ 901 ] - } - }, - "spi_if_ins.o_load_cmd_SB_LUT4_I2": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0100000000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 81 ], - "I1": [ 74 ], - "I2": [ 82 ], - "I3": [ 3 ], - "O": [ 153 ] - } - }, - "spi_if_ins.o_load_cmd_SB_LUT4_I2_1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0001000000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 118 ], - "I1": [ 81 ], - "I2": [ 82 ], - "I3": [ 74 ], - "O": [ 63 ] - } - }, - "spi_if_ins.o_load_cmd_SB_LUT4_I2_2": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0100000000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 81 ], - "I1": [ 890 ], - "I2": [ 82 ], - "I3": [ 127 ], - "O": [ 913 ] + "I3": [ 958 ], + "O": [ 952 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q": { @@ -26173,7 +29495,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26182,10 +29504,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 363 ], - "E": [ 914 ], - "Q": [ 915 ] + "C": [ 63 ], + "D": [ 372 ], + "E": [ 965 ], + "Q": [ 966 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_1": { @@ -26195,7 +29517,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26204,10 +29526,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 361 ], - "E": [ 914 ], - "Q": [ 916 ] + "C": [ 63 ], + "D": [ 374 ], + "E": [ 965 ], + "Q": [ 967 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_2": { @@ -26217,7 +29539,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26226,10 +29548,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 359 ], - "E": [ 914 ], - "Q": [ 917 ] + "C": [ 63 ], + "D": [ 381 ], + "E": [ 965 ], + "Q": [ 968 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_3": { @@ -26239,7 +29561,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26248,10 +29570,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 356 ], - "E": [ 914 ], - "Q": [ 918 ] + "C": [ 63 ], + "D": [ 387 ], + "E": [ 965 ], + "Q": [ 969 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_4": { @@ -26261,7 +29583,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26270,10 +29592,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 367 ], - "E": [ 914 ], - "Q": [ 919 ] + "C": [ 63 ], + "D": [ 391 ], + "E": [ 965 ], + "Q": [ 970 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_5": { @@ -26283,7 +29605,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26292,10 +29614,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 369 ], - "E": [ 914 ], - "Q": [ 920 ] + "C": [ 63 ], + "D": [ 394 ], + "E": [ 965 ], + "Q": [ 971 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_6": { @@ -26305,7 +29627,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26314,10 +29636,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 371 ], - "E": [ 914 ], - "Q": [ 921 ] + "C": [ 63 ], + "D": [ 398 ], + "E": [ 965 ], + "Q": [ 972 ] } }, "spi_if_ins.r_tx_byte_SB_DFFE_Q_7": { @@ -26327,7 +29649,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26336,10 +29658,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 373 ], - "E": [ 914 ], - "Q": [ 922 ] + "C": [ 63 ], + "D": [ 404 ], + "E": [ 965 ], + "Q": [ 973 ] } }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q": { @@ -26349,7 +29671,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -26359,22 +29681,47 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 910 ], - "E": [ 923 ], - "Q": [ 924 ], - "R": [ 904 ] + "C": [ 63 ], + "D": [ 962 ], + "E": [ 974 ], + "Q": [ 975 ], + "R": [ 958 ] } }, - "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_O": { + "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000001100000000" + "LUT_INIT": "0101011100000000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 958 ], + "I1": [ 953 ], + "I2": [ 954 ], + "I3": [ 963 ], + "O": [ 974 ] + } + }, + "spi_if_ins.r_tx_data_valid_SB_LUT4_I3": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" }, "port_directions": { "I0": "input", @@ -26385,38 +29732,13 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 903 ], - "I2": [ 908 ], - "I3": [ 909 ], - "O": [ 910 ] + "I1": [ "0" ], + "I2": [ 48 ], + "I3": [ 975 ], + "O": [ 976 ] } }, - "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E_SB_LUT4_O": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0001111100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 902 ], - "I1": [ 903 ], - "I2": [ 904 ], - "I3": [ 912 ], - "O": [ 923 ] - } - }, - "spi_if_ins.r_tx_data_valid_SB_LUT4_I3": { + "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -26436,9 +29758,34 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 46 ], - "I3": [ 924 ], - "O": [ 925 ] + "I2": [ 48 ], + "I3": [ 975 ], + "O": [ 977 ] + } + }, + "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_I1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111110000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 976 ], + "I2": [ 978 ], + "I3": [ 979 ], + "O": [ 980 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q": { @@ -26448,7 +29795,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26456,9 +29803,9 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 926 ], - "Q": [ 927 ] + "C": [ 63 ], + "D": [ 981 ], + "Q": [ 982 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q_1": { @@ -26468,7 +29815,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26476,9 +29823,9 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 928 ], - "Q": [ 926 ] + "C": [ 63 ], + "D": [ 983 ], + "Q": [ 981 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q_2": { @@ -26488,7 +29835,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26496,20 +29843,20 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 45 ], - "Q": [ 928 ] + "C": [ 63 ], + "D": [ 47 ], + "Q": [ 983 ] } }, - "spi_if_ins.spi.SCKr_SB_LUT4_I0": { + "spi_if_ins.spi.SCKr_SB_LUT4_I1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000000100000000" + "LUT_INIT": "1111111100110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" }, "port_directions": { "I0": "input", @@ -26519,11 +29866,11 @@ "O": "output" }, "connections": { - "I0": [ 927 ], - "I1": [ 929 ], - "I2": [ 930 ], - "I3": [ 926 ], - "O": [ 931 ] + "I0": [ "0" ], + "I1": [ 982 ], + "I2": [ 981 ], + "I3": [ 976 ], + "O": [ 979 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q": { @@ -26533,7 +29880,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26542,10 +29889,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 932 ], - "E": [ 933 ], - "Q": [ 892 ] + "C": [ 63 ], + "D": [ 984 ], + "E": [ 985 ], + "Q": [ 943 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_1": { @@ -26555,7 +29902,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26564,10 +29911,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 934 ], - "E": [ 933 ], - "Q": [ 888 ] + "C": [ 63 ], + "D": [ 986 ], + "E": [ 985 ], + "Q": [ 68 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_2": { @@ -26577,7 +29924,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26586,10 +29933,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 935 ], - "E": [ 933 ], - "Q": [ 889 ] + "C": [ 63 ], + "D": [ 987 ], + "E": [ 985 ], + "Q": [ 69 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_3": { @@ -26599,7 +29946,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26608,10 +29955,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 936 ], - "E": [ 933 ], - "Q": [ 894 ] + "C": [ 63 ], + "D": [ 988 ], + "E": [ 985 ], + "Q": [ 945 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4": { @@ -26621,7 +29968,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26630,10 +29977,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 937 ], - "E": [ 933 ], - "Q": [ 895 ] + "C": [ 63 ], + "D": [ 989 ], + "E": [ 985 ], + "Q": [ 946 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_5": { @@ -26643,7 +29990,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26652,10 +29999,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 938 ], - "E": [ 933 ], - "Q": [ 896 ] + "C": [ 63 ], + "D": [ 990 ], + "E": [ 985 ], + "Q": [ 947 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_6": { @@ -26665,7 +30012,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26674,10 +30021,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 939 ], - "E": [ 933 ], - "Q": [ 897 ] + "C": [ 63 ], + "D": [ 991 ], + "E": [ 985 ], + "Q": [ 948 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_7": { @@ -26687,7 +30034,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26696,10 +30043,10 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 940 ], - "E": [ 933 ], - "Q": [ 898 ] + "C": [ 63 ], + "D": [ 992 ], + "E": [ 985 ], + "Q": [ 949 ] } }, "spi_if_ins.spi.o_rx_data_valid_SB_DFF_Q": { @@ -26709,7 +30056,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26717,9 +30064,59 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 933 ], - "Q": [ 904 ] + "C": [ 63 ], + "D": [ 985 ], + "Q": [ 958 ] + } + }, + "spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000000000001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 3 ], + "I1": [ 958 ], + "I2": [ 953 ], + "I3": [ 954 ], + "O": [ 65 ] + } + }, + "spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I2": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 3 ], + "I2": [ 958 ], + "I3": [ 957 ], + "O": [ 944 ] } }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q": { @@ -26729,7 +30126,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -26738,17 +30135,17 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 941 ], - "E": [ 942 ], - "Q": [ 350 ] + "C": [ 63 ], + "D": [ 993 ], + "E": [ 979 ], + "Q": [ 366 ] } }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100000011001111" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26763,17 +30160,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 915 ], - "I2": [ 943 ], - "I3": [ 925 ], - "O": [ 941 ] + "I1": [ 966 ], + "I2": [ 976 ], + "I3": [ 994 ], + "O": [ 993 ] } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000000011111110" + "LUT_INIT": "1010100011111101" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26787,18 +30184,18 @@ "O": "output" }, "connections": { - "I0": [ 944 ], - "I1": [ 945 ], - "I2": [ 946 ], - "I3": [ 947 ], - "O": [ 943 ] + "I0": [ 995 ], + "I1": [ 996 ], + "I2": [ 997 ], + "I3": [ 998 ], + "O": [ 994 ] } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100101000000000" + "LUT_INIT": "0101001100000000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26812,18 +30209,18 @@ "O": "output" }, "connections": { - "I0": [ 948 ], - "I1": [ 949 ], - "I2": [ 930 ], - "I3": [ 929 ], - "O": [ 946 ] + "I0": [ 999 ], + "I1": [ 1000 ], + "I2": [ 1001 ], + "I3": [ 1002 ], + "O": [ 996 ] } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000110000001010" + "LUT_INIT": "0000000001010011" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26837,43 +30234,18 @@ "O": "output" }, "connections": { - "I0": [ 950 ], - "I1": [ 951 ], - "I2": [ 929 ], - "I3": [ 930 ], - "O": [ 945 ] + "I0": [ 1003 ], + "I1": [ 1004 ], + "I2": [ 1001 ], + "I3": [ 1002 ], + "O": [ 997 ] } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100101000000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ 952 ], - "I1": [ 953 ], - "I2": [ 929 ], - "I3": [ 944 ], - "O": [ 947 ] - } - }, - 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"O": [ 953 ] + "I1": [ 1007 ], + "I2": [ 1002 ], + "I3": [ 1008 ], + "O": [ 1005 ] + } + }, + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2_SB_LUT4_O_1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1100110011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 1009 ], + "I2": [ 1010 ], + "I3": [ 1002 ], + "O": [ 1006 ] } }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0011000011111111" + "LUT_INIT": "0000000000000011" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -26938,10 +30335,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 927 ], - "I2": [ 926 ], - "I3": [ 925 ], - "O": [ 942 ] + "I1": [ 995 ], + "I2": [ 1001 ], + "I3": [ 1002 ], + "O": [ 978 ] } }, "spi_if_ins.spi.r2_rx_done_SB_DFF_Q": { @@ -26951,7 +30348,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26959,9 +30356,9 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 958 ], - "Q": [ 959 ] + "C": [ 63 ], + "D": [ 1011 ], + "Q": [ 1012 ] } }, "spi_if_ins.spi.r3_rx_done_SB_DFF_Q": { @@ -26971,7 +30368,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" + "src": "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" }, "port_directions": { "C": "input", @@ -26979,9 +30376,9 @@ "Q": "output" }, "connections": { - "C": [ 61 ], - "D": [ 959 ], - "Q": [ 960 ] + "C": [ 63 ], + "D": [ 1012 ], + "Q": [ 1013 ] } }, "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2": { @@ -27004,9 +30401,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 960 ], - "I3": [ 959 ], - "O": [ 933 ] + "I2": [ 1013 ], + "I3": [ 1012 ], + "O": [ 985 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q": { @@ -27016,7 +30413,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" }, "port_directions": { "C": "input", @@ -27025,10 +30422,10 @@ "R": "input" }, "connections": { - "C": [ 45 ], - "D": [ 961 ], - "Q": [ 962 ], - "R": [ 46 ] + "C": [ 47 ], + "D": [ 1014 ], + "Q": [ 1015 ], + "R": [ 48 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1": { @@ -27038,7 +30435,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" }, "port_directions": { "C": "input", @@ -27047,10 +30444,35 @@ "R": "input" }, "connections": { - "C": [ 45 ], - "D": [ 963 ], - "Q": [ 964 ], - "R": [ 46 ] + "C": [ 47 ], + "D": [ 1016 ], + "Q": [ 1017 ], + "R": [ 48 ] + } + }, + "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0110100110010110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 1017 ], + "I3": [ 1018 ], + "O": [ 1016 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2": { @@ -27060,7 +30482,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" }, "port_directions": { "C": "input", @@ -27069,10 +30491,10 @@ "R": "input" }, "connections": { - "C": [ 45 ], - "D": [ 965 ], - "Q": [ 966 ], - "R": [ 46 ] + "C": [ 47 ], + "D": [ 1019 ], + "Q": [ 1018 ], + "R": [ 48 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D_SB_LUT4_O": { @@ -27096,8 +30518,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 966 ], - "O": [ 965 ] + "I3": [ 1018 ], + "O": [ 1019 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O": { @@ -27108,7 +30530,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" }, "port_directions": { "I0": "input", @@ -27120,34 +30542,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 962 ], - "I3": [ 967 ], - "O": [ 961 ] - } - }, - "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0110100110010110" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ "0" ], - "I2": [ 964 ], - "I3": [ 966 ], - "O": [ 963 ] + "I2": [ 1015 ], + "I3": [ 1020 ], + "O": [ 1014 ] } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": { @@ -27156,7 +30553,7 @@ "parameters": { }, "attributes": { - "src": "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" + "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" }, "port_directions": { "CI": "input", @@ -27165,10 +30562,10 @@ "I1": "input" }, "connections": { - "CI": [ 966 ], - "CO": [ 967 ], + "CI": [ 1018 ], + "CO": [ 1020 ], "I0": [ "0" ], - "I1": [ 964 ] + "I1": [ 1017 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q": { @@ -27178,7 +30575,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27187,10 +30584,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 968 ], - "E": [ 969 ], - "Q": [ 932 ] + "C": [ 47 ], + "D": [ 1021 ], + "E": [ 1022 ], + "Q": [ 984 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_1": { @@ -27200,7 +30597,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27209,10 +30606,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 970 ], - "E": [ 969 ], - "Q": [ 934 ] + "C": [ 47 ], + "D": [ 1023 ], + "E": [ 1022 ], + "Q": [ 986 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_2": { @@ -27222,7 +30619,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27231,10 +30628,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 971 ], - "E": [ 969 ], - "Q": [ 935 ] + "C": [ 47 ], + "D": [ 1024 ], + "E": [ 1022 ], + "Q": [ 987 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_3": { @@ -27244,7 +30641,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27253,10 +30650,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 972 ], - "E": [ 969 ], - "Q": [ 936 ] + "C": [ 47 ], + "D": [ 1025 ], + "E": [ 1022 ], + "Q": [ 988 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_4": { @@ -27266,7 +30663,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27275,10 +30672,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 973 ], - "E": [ 969 ], - "Q": [ 937 ] + "C": [ 47 ], + "D": [ 1026 ], + "E": [ 1022 ], + "Q": [ 989 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_5": { @@ -27288,7 +30685,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27297,10 +30694,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 974 ], - "E": [ 969 ], - "Q": [ 938 ] + "C": [ 47 ], + "D": [ 1027 ], + "E": [ 1022 ], + "Q": [ 990 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_6": { @@ -27310,7 +30707,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27319,10 +30716,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 975 ], - "E": [ 969 ], - "Q": [ 939 ] + "C": [ 47 ], + "D": [ 1028 ], + "E": [ 1022 ], + "Q": [ 991 ] } }, "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_7": { @@ -27332,7 +30729,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27341,10 +30738,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 44 ], - "E": [ 969 ], - "Q": [ 940 ] + "C": [ 47 ], + "D": [ 46 ], + "E": [ 1022 ], + "Q": [ 992 ] } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q": { @@ -27354,7 +30751,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27364,11 +30761,11 @@ "R": "input" }, "connections": { - "C": [ 45 ], - "D": [ 976 ], - "E": [ 977 ], - "Q": [ 958 ], - "R": [ 46 ] + "C": [ 47 ], + "D": [ 1029 ], + "E": [ 1030 ], + "Q": [ 1011 ], + "R": [ 48 ] } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3": { @@ -27391,9 +30788,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 46 ], - "I3": [ 976 ], - "O": [ 969 ] + "I2": [ 48 ], + "I3": [ 1029 ], + "O": [ 1022 ] } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -27415,17 +30812,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 966 ], - "I2": [ 962 ], - "I3": [ 964 ], - "O": [ 976 ] + "I1": [ 1015 ], + "I2": [ 1017 ], + "I3": [ 1018 ], + "O": [ 1029 ] } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1110101110101010" + "LUT_INIT": "1110101010111010" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -27439,11 +30836,11 @@ "O": "output" }, "connections": { - "I0": [ 46 ], - "I1": [ 966 ], - "I2": [ 962 ], - "I3": [ 964 ], - "O": [ 977 ] + "I0": [ 48 ], + "I1": [ 1015 ], + "I2": [ 1017 ], + "I3": [ 1018 ], + "O": [ 1030 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q": { @@ -27453,7 +30850,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27462,10 +30859,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 970 ], - "E": [ 60 ], - "Q": [ 968 ] + "C": [ 47 ], + "D": [ 1023 ], + "E": [ 62 ], + "Q": [ 1021 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_1": { @@ -27475,7 +30872,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27484,10 +30881,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 971 ], - "E": [ 60 ], - "Q": [ 970 ] + "C": [ 47 ], + "D": [ 1024 ], + "E": [ 62 ], + "Q": [ 1023 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_2": { @@ -27497,7 +30894,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27506,10 +30903,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 972 ], - "E": [ 60 ], - "Q": [ 971 ] + "C": [ 47 ], + "D": [ 1025 ], + "E": [ 62 ], + "Q": [ 1024 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_3": { @@ -27519,7 +30916,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27528,10 +30925,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 973 ], - "E": [ 60 ], - "Q": [ 972 ] + "C": [ 47 ], + "D": [ 1026 ], + "E": [ 62 ], + "Q": [ 1025 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_4": { @@ -27541,7 +30938,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27550,10 +30947,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 974 ], - "E": [ 60 ], - "Q": [ 973 ] + "C": [ 47 ], + "D": [ 1027 ], + "E": [ 62 ], + "Q": [ 1026 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_5": { @@ -27563,7 +30960,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27572,10 +30969,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 975 ], - "E": [ 60 ], - "Q": [ 974 ] + "C": [ 47 ], + "D": [ 1028 ], + "E": [ 62 ], + "Q": [ 1027 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_6": { @@ -27585,7 +30982,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -27594,10 +30991,10 @@ "Q": "output" }, "connections": { - "C": [ 45 ], - "D": [ 44 ], - "E": [ 60 ], - "Q": [ 975 ] + "C": [ 47 ], + "D": [ 46 ], + "E": [ 62 ], + "Q": [ 1028 ] } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q": { @@ -27607,7 +31004,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": 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], + "CO": [ 1034 ], + "I0": [ 1001 ], + "I1": [ "1" ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q": { @@ -27800,7 +31172,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27810,11 +31182,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 915 ], - "E": [ 983 ], - "Q": [ 957 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 966 ], + "E": [ 980 ], + "Q": [ 999 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_1": { @@ -27824,7 +31196,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27834,11 +31206,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 916 ], - "E": [ 983 ], - "Q": [ 955 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 967 ], + "E": [ 980 ], + "Q": [ 1003 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_2": { @@ -27848,7 +31220,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27858,11 +31230,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 917 ], - "E": [ 983 ], - "Q": [ 949 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 968 ], + "E": [ 980 ], + "Q": [ 1000 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_3": { @@ -27872,7 +31244,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27882,11 +31254,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 918 ], - "E": [ 983 ], - "Q": [ 951 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 969 ], + "E": [ 980 ], + "Q": [ 1004 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_4": { @@ -27896,7 +31268,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27906,11 +31278,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 919 ], - "E": [ 983 ], - "Q": [ 956 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 970 ], + "E": [ 980 ], + "Q": [ 1009 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_5": { @@ -27920,7 +31292,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -27930,11 +31302,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 920 ], - "E": [ 983 ], - "Q": [ 954 ], - "R": [ 925 ] + "C": [ 63 ], + "D": [ 971 ], + "E": [ 980 ], + "Q": [ 1010 ], + "R": [ 977 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_6": { @@ -27944,7 +31316,7 @@ }, "attributes": { "module_not_derived": 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"spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -28027,11 +31374,11 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 906 ], - "E": [ 984 ], - "Q": [ 903 ], - "R": [ 59 ] + "C": [ 63 ], + "D": [ 1035 ], + "E": [ 1036 ], + "Q": [ 953 ], + "R": [ 61 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q_1": { @@ -28041,7 +31388,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" + "src": "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" }, "port_directions": { "C": "input", @@ -28051,18 +31398,18 @@ "R": "input" }, "connections": { - "C": [ 61 ], - "D": [ 985 ], - "E": [ 984 ], - "Q": [ 909 ], - "R": [ 59 ] + "C": [ 63 ], + "D": [ 1037 ], + "E": [ 1036 ], + "Q": [ 955 ], + "R": [ 61 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -28077,38 +31424,13 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 986 ], - "I2": [ 892 ], - "I3": [ 987 ], - "O": [ 985 ] + "I1": [ 943 ], + "I2": [ 959 ], + "I3": [ 1038 ], + "O": [ 1037 ] } }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0000111100000000" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ "0" ], - "I2": [ 986 ], - "I3": [ 3 ], - "O": [ 912 ] - } - }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1": { + 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"io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 19, 108, 137 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "io_ctrl_ins.o_mixer_en": { @@ -34206,7 +36639,7 @@ "bits": [ "1" ], "attributes": { "hdlname": "io_ctrl_ins o_mixer_en", - "src": "top.v:155.11-182.4|io_ctrl.v:29.22-29.32" + "src": "io_ctrl.v:29.22-29.32" } }, "io_ctrl_ins.o_mixer_fm": { @@ -34214,15 +36647,15 @@ "bits": [ "0" ], "attributes": { "hdlname": "io_ctrl_ins o_mixer_fm", - "src": "top.v:155.11-182.4|io_ctrl.v:21.22-21.32" + "src": "io_ctrl.v:21.22-21.32" } }, "io_ctrl_ins.o_pmod": { "hide_name": 0, - "bits": [ 157, 140, 92, 104, 109, 156, 155, 50 ], + "bits": [ 23, 24, 25, 26 ], "attributes": { "hdlname": "io_ctrl_ins o_pmod", - "src": "top.v:155.11-182.4|io_ctrl.v:18.22-18.28" + "src": "io_ctrl.v:18.22-18.28" } }, "io_ctrl_ins.o_rx_h_tx_l": { @@ -34230,7 +36663,7 @@ "bits": [ 4 ], "attributes": { "hdlname": "io_ctrl_ins o_rx_h_tx_l", - "src": "top.v:155.11-182.4|io_ctrl.v:22.22-22.33" + "src": "io_ctrl.v:22.22-22.33" } }, "io_ctrl_ins.o_rx_h_tx_l_b": { @@ -34238,7 +36671,7 @@ "bits": [ 5 ], "attributes": { "hdlname": "io_ctrl_ins o_rx_h_tx_l_b", - "src": "top.v:155.11-182.4|io_ctrl.v:23.22-23.35" + "src": "io_ctrl.v:23.22-23.35" } }, "io_ctrl_ins.o_shdn_rx_lna": { @@ -34246,7 +36679,7 @@ "bits": [ 9 ], "attributes": { "hdlname": "io_ctrl_ins o_shdn_rx_lna", - "src": "top.v:155.11-182.4|io_ctrl.v:28.22-28.35" + "src": "io_ctrl.v:28.22-28.35" } }, "io_ctrl_ins.o_shdn_tx_lna": { @@ -34254,7 +36687,7 @@ "bits": [ 10 ], "attributes": { "hdlname": "io_ctrl_ins o_shdn_tx_lna", - "src": "top.v:155.11-182.4|io_ctrl.v:27.22-27.35" + "src": "io_ctrl.v:27.22-27.35" } }, "io_ctrl_ins.o_tr_vc1": { @@ -34262,7 +36695,7 @@ "bits": [ 6 ], "attributes": { "hdlname": "io_ctrl_ins o_tr_vc1", - "src": "top.v:155.11-182.4|io_ctrl.v:24.22-24.30" + "src": "io_ctrl.v:24.22-24.30" } }, "io_ctrl_ins.o_tr_vc1_b": { @@ -34270,7 +36703,7 @@ "bits": [ 7 ], "attributes": { "hdlname": "io_ctrl_ins o_tr_vc1_b", - "src": "top.v:155.11-182.4|io_ctrl.v:25.22-25.32" + "src": "io_ctrl.v:25.22-25.32" } }, "io_ctrl_ins.o_tr_vc2": { @@ -34278,63 +36711,31 @@ "bits": [ 8 ], "attributes": { "hdlname": "io_ctrl_ins o_tr_vc2", - "src": "top.v:155.11-182.4|io_ctrl.v:26.22-26.30" + "src": "io_ctrl.v:26.22-26.30" } }, "io_ctrl_ins.pmod_dir_state": { "hide_name": 0, - "bits": [ 78, 83, 116, 151, 149, 147, 145, 143 ], + "bits": [ 106, 124, 82, 144, 143, 56, 54, 50 ], "attributes": { "hdlname": "io_ctrl_ins pmod_dir_state", - "src": "top.v:155.11-182.4|io_ctrl.v:75.17-75.31" - } - }, - "io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 142 ], - "attributes": { + "src": "io_ctrl.v:75.17-75.31" } }, "io_ctrl_ins.pmod_state": { "hide_name": 0, - "bits": [ 157, 140, 92, 104, 109, 156, 155, 50 ], + "bits": [ 23, 24, 25, 26 ], "attributes": { "hdlname": "io_ctrl_ins pmod_state", - "src": "top.v:155.11-182.4|io_ctrl.v:76.17-76.27" - } - }, - "io_ctrl_ins.pmod_state_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 154 ], - "attributes": { - } - }, - "io_ctrl_ins.rf_mode": { - "hide_name": 0, - "bits": [ 119, 67, 68 ], - "attributes": { - "hdlname": "io_ctrl_ins rf_mode", - "src": "top.v:155.11-182.4|io_ctrl.v:70.17-70.24" - } - }, - "io_ctrl_ins.rf_mode_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 63 ], - "attributes": { + "src": "io_ctrl.v:76.17-76.27" } }, "io_ctrl_ins.rf_pin_state": { "hide_name": 0, - "bits": [ 96, 88, 90, 163, 162, 161, 160, 159 ], + "bits": [ 101, 72, 79, 150, 149, 148, 147, 146 ], "attributes": { "hdlname": "io_ctrl_ins rf_pin_state", - "src": "top.v:155.11-182.4|io_ctrl.v:77.17-77.29" - } - }, - "io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 158 ], - "attributes": { + "src": "io_ctrl.v:77.17-77.29" } }, "io_ctrl_ins.rx_h_b_state": { @@ -34342,19 +36743,18 @@ "bits": [ 5 ], "attributes": { "hdlname": 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"hide_name": 0, + "bits": [ 150, 80, 73, 74 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 70, 160, 165 ], + "bits": [ 146, 74, 152 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.rx_h_state_SB_LUT4_I3_I0": { + "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 54, 147, 91, 6 ], + "bits": [ 71 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "io_ctrl_ins.tr_vc_1_b_state": { @@ -34396,19 +36801,98 @@ "bits": [ 7 ], "attributes": { "hdlname": "io_ctrl_ins tr_vc_1_b_state", - "src": "top.v:155.11-182.4|io_ctrl.v:86.17-86.32" + "src": "io_ctrl.v:86.17-86.32" } }, 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}, + "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2": { + "hide_name": 0, + "bits": [ 163, 160 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -34419,27 +36903,26 @@ "bits": [ 6 ], "attributes": { "hdlname": "io_ctrl_ins tr_vc_1_state", - "src": "top.v:155.11-182.4|io_ctrl.v:85.17-85.30" + "src": "io_ctrl.v:85.17-85.30" } }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 169 ], + "bits": [ 174 ], "attributes": { - "src": "top.v:155.11-182.4|io_ctrl.v:209.5-307.8" } }, - "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0": { + "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 168, 67, 161, 70 ], + "bits": [ 149, 73, 155, 74 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O": { + "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3": { "hide_name": 0, - "bits": [ 131, 132 ], + "bits": [ 6, 102, 57 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -34450,27 +36933,18 @@ "bits": [ 8 ], "attributes": { "hdlname": "io_ctrl_ins tr_vc_2_state", - "src": "top.v:155.11-182.4|io_ctrl.v:87.17-87.30" + "src": "io_ctrl.v:87.17-87.30" } }, "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 170 ], + "bits": [ 175 ], "attributes": { - "src": "top.v:155.11-182.4|io_ctrl.v:209.5-307.8" - } - }, - "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_I3": { - "hide_name": 0, - "bits": [ 55, 85 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 104, 49, 105, 106 ], + "bits": [ 73, 96, 117, 118 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -34483,25 +36957,51 @@ "src": "top.v:43.17-43.24" } }, + "io_pmod_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + } + }, + "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 75, 177, 76 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + } + }, + "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + } + }, "io_smi_data": { "hide_name": 0, - "bits": [ 35, 36, 37, 38, 39, 40, 41, 42 ], + "bits": [ 37, 38, 39, 40, 41, 42, 43, 44 ], "attributes": { - "src": "top.v:79.17-79.28" + "src": "top.v:80.17-80.28" } }, "lvds_clock": { "hide_name": 0, "bits": [ 13 ], "attributes": { - "src": "top.v:216.8-216.18" + "src": "top.v:248.8-248.18" } }, "lvds_clock_buf": { "hide_name": 0, "bits": [ 13 ], "attributes": { - "src": "top.v:217.8-217.22" + "src": "top.v:249.8-249.22" } }, "lvds_rx_09_inst.i_ddr_clk": { @@ -34509,23 +37009,23 @@ "bits": [ 13 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_clk", - "src": "top.v:312.11-323.4|lvds_rx.v:3.17-3.26" + "src": "lvds_rx.v:3.17-3.26" } }, "lvds_rx_09_inst.i_ddr_data": { "hide_name": 0, - "bits": [ 172, 171 ], + "bits": [ 179, 178 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_data", - "src": "top.v:312.11-323.4|lvds_rx.v:4.17-4.27" + "src": "lvds_rx.v:4.17-4.27" } }, "lvds_rx_09_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 424 ], + "bits": [ 418 ], "attributes": { "hdlname": "lvds_rx_09_inst i_fifo_full", - "src": "top.v:312.11-323.4|lvds_rx.v:6.23-6.34" + "src": "lvds_rx.v:6.23-6.34" } }, "lvds_rx_09_inst.i_rst_b": { @@ -34533,75 +37033,246 @@ "bits": [ 3 ], "attributes": { "hdlname": "lvds_rx_09_inst i_rst_b", - "src": "top.v:312.11-323.4|lvds_rx.v:2.17-2.24" + "src": "lvds_rx.v:2.17-2.24" } }, "lvds_rx_09_inst.i_sync_input": { "hide_name": 0, - "bits": [ "0" ], + "bits": [ 182 ], "attributes": { "hdlname": "lvds_rx_09_inst i_sync_input", - "src": "top.v:312.11-323.4|lvds_rx.v:10.23-10.35" + "src": "lvds_rx.v:10.23-10.35" } }, - "lvds_rx_09_inst.o_debug_state": { + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 237, 244 ], + "bits": [ 183 ], "attributes": { - "hdlname": "lvds_rx_09_inst o_debug_state", - "src": "top.v:312.11-323.4|lvds_rx.v:11.23-11.36" + "defaultvalue": "1", + "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q": { + "hide_name": 0, + "bits": [ 179, 184, 187 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": 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242 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_data", - "src": "top.v:312.11-323.4|lvds_rx.v:9.23-9.34" + "src": "lvds_rx.v:9.23-9.34" + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + } + }, + "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D": { + "hide_name": 0, + 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"top.v:312.11-323.4|lvds_rx.v:8.23-8.34" - } - }, - "lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_D": { - "hide_name": 0, - "bits": [ 241 ], - "attributes": { - "src": "top.v:312.11-323.4|lvds_rx.v:36.3-84.6" - } - }, - "lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 242 ], + "bits": [ 188 ], "attributes": { } }, @@ -34610,46 +37281,7 @@ "bits": [ 13 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_write_clk", - "src": "top.v:312.11-323.4|lvds_rx.v:7.23-7.39" - } - }, - "lvds_rx_09_inst.r_phase_count": { - "hide_name": 0, - "bits": [ 246, 248, 1185 ], - "attributes": { - "hdlname": "lvds_rx_09_inst r_phase_count", - "src": "top.v:312.11-323.4|lvds_rx.v:22.13-22.26", - "unused_bits": "2" - } - }, - "lvds_rx_09_inst.r_state_if": { - "hide_name": 0, - "bits": [ 237, 244 ], - "attributes": { - "hdlname": "lvds_rx_09_inst r_state_if", - "src": "top.v:312.11-323.4|lvds_rx.v:21.13-21.23" - } - }, - "lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D": { - "hide_name": 0, - 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"lvds_rx_24_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 424 ], + "bits": [ 418 ], "attributes": { "hdlname": "lvds_rx_24_inst i_fifo_full", - "src": "top.v:325.11-338.4|lvds_rx.v:6.23-6.34" + "src": "lvds_rx.v:6.23-6.34" } }, "lvds_rx_24_inst.i_rst_b": { @@ -34682,75 +37305,284 @@ "bits": [ 3 ], "attributes": { "hdlname": "lvds_rx_24_inst i_rst_b", - "src": "top.v:325.11-338.4|lvds_rx.v:2.17-2.24" + "src": "lvds_rx.v:2.17-2.24" } }, "lvds_rx_24_inst.i_sync_input": { "hide_name": 0, - "bits": [ "0" ], + "bits": [ 256 ], "attributes": { "hdlname": "lvds_rx_24_inst i_sync_input", - "src": "top.v:325.11-338.4|lvds_rx.v:10.23-10.35" + "src": "lvds_rx.v:10.23-10.35" } }, - "lvds_rx_24_inst.o_debug_state": { + "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 318, 325 ], + "bits": [ 257, 259 ], "attributes": { - "hdlname": "lvds_rx_24_inst o_debug_state", - "src": "top.v:325.11-338.4|lvds_rx.v:11.23-11.36" + "force_downto": "00000000000000000000000000000001", + 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"hide_name": 0, - "bits": [ 731, 730, 729, 728, 727, 726, 725, 724, 723, 722 ], + "bits": [ 794, 793, 792, 791, 790, 789, 788, 787, 786, 785 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd", - "src": "top.v:354.5-367.4|complex_fifo.v:25.23-25.38" + "src": "complex_fifo.v:25.23-25.38" } }, "rx_fifo.wr_addr_gray_rd_r": { "hide_name": 0, - "bits": [ 422, 417, 391, 400, 387, 411, 413, 402, 395, 396 ], + "bits": [ 708, 719, 690, 710, 715, 721, 713, 700, 703, 717 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd_r", - "src": "top.v:354.5-367.4|complex_fifo.v:26.23-26.40" + "src": "complex_fifo.v:26.23-26.40" } }, "rx_fifo.wr_clk_i": { @@ -35635,29 +39141,7 @@ "bits": [ 13 ], "attributes": { "hdlname": "rx_fifo wr_clk_i", - "src": "top.v:354.5-367.4|complex_fifo.v:7.28-7.36" - } - }, - "rx_fifo.wr_data_i": { - "hide_name": 0, - "bits": [ 576, 578, 577, 579, 596, 598, 597, 599, 616, 618, 617, 619, 636, 638, 637, 639, 496, 498, 497, 499, 516, 518, 517, 519, 536, 538, 537, 539, 556, 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"smi_ctrl_ins.w_fifo_pull_trigger": { "hide_name": 0, - "bits": [ 805 ], + "bits": [ 868 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_pull_trigger", - "src": "top.v:421.12-453.4|smi_ctrl.v:114.10-114.29" + "src": "smi_ctrl.v:114.10-114.29" } }, "smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 876 ], + "bits": [ 930 ], "attributes": { - "src": "top.v:421.12-453.4|smi_ctrl.v:132.37-132.55" } }, "smi_ctrl_ins.w_fifo_push_trigger": { "hide_name": 0, - "bits": [ 863 ], + "bits": [ 917 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_push_trigger", - "src": "top.v:421.12-453.4|smi_ctrl.v:181.10-181.29" + "src": "smi_ctrl.v:181.10-181.29" } }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D": { "hide_name": 0, - "bits": [ 877 ], + "bits": [ 931 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R": { "hide_name": 0, - "bits": [ 878 ], + "bits": [ 932 ], "attributes": { } }, "spi_if_ins.i_data_out": { "hide_name": 0, - "bits": [ 373, 371, 369, 367, 356, 359, 361, 363 ], + "bits": [ 404, 398, 394, 391, 387, 381, 374, 372 ], "attributes": { "hdlname": "spi_if_ins i_data_out", - "src": "top.v:111.10-126.4|spi_if.v:9.22-9.32" + "src": "spi_if.v:9.22-9.32" } }, "spi_if_ins.i_rst_b": { @@ -36213,98 +39801,116 @@ "bits": [ 3 ], "attributes": { "hdlname": "spi_if_ins i_rst_b", - "src": "top.v:111.10-126.4|spi_if.v:4.11-4.18" + "src": "spi_if.v:4.11-4.18" } }, "spi_if_ins.i_spi_cs_b": { "hide_name": 0, - "bits": [ 46 ], + "bits": [ 48 ], "attributes": { "hdlname": "spi_if_ins i_spi_cs_b", - "src": "top.v:111.10-126.4|spi_if.v:18.12-18.22" + "src": "spi_if.v:18.12-18.22" } }, "spi_if_ins.i_spi_mosi": { "hide_name": 0, - "bits": [ 44 ], + "bits": [ 46 ], "attributes": { "hdlname": "spi_if_ins i_spi_mosi", - "src": "top.v:111.10-126.4|spi_if.v:17.12-17.22" + "src": "spi_if.v:17.12-17.22" } }, "spi_if_ins.i_spi_sck": { "hide_name": 0, - "bits": [ 45 ], + "bits": [ 47 ], "attributes": { "hdlname": "spi_if_ins i_spi_sck", - "src": "top.v:111.10-126.4|spi_if.v:15.12-15.21" + "src": "spi_if.v:15.12-15.21" } }, "spi_if_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 61 ], + "bits": [ 63 ], "attributes": { "hdlname": "spi_if_ins i_sys_clk", - "src": "top.v:111.10-126.4|spi_if.v:5.11-5.20" + "src": "spi_if.v:5.11-5.20" } }, "spi_if_ins.o_cs": { "hide_name": 0, - "bits": [ 890, 74, 733, 887 ], + "bits": [ 158, 66, 365, 941 ], "attributes": { "hdlname": "spi_if_ins o_cs", - "src": "top.v:111.10-126.4|spi_if.v:10.22-10.26" + "src": "spi_if.v:10.22-10.26" } }, "spi_if_ins.o_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ "0", "0", "0", 886, "0", "0", 732, "0", "0", 72, "0", "0" ], + "bits": [ 940 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:65.11-70.18|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:583.28-583.35" } }, - "spi_if_ins.o_cs_SB_LUT4_I1_O": { + "spi_if_ins.o_cs_SB_LUT4_I0_3_O": { "hide_name": 0, - "bits": [ 745, 742, 364, 114 ], + "bits": [ 395, 385, 376, 396 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.o_cs_SB_LUT4_I2_O": { + "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 891, 3 ], + "bits": [ 164, 170, 168, 166 ], + "attributes": { + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_4_O": { + "hide_name": 0, + "bits": [ 121, 800, 402, 377 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.o_cs_SB_LUT4_I2_O_SB_LUT4_I2_O": { + "spi_if_ins.o_cs_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 355 ], + "bits": [ 3, 942 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 371 ], "attributes": { } }, "spi_if_ins.o_data_in": { "hide_name": 0, - "bits": [ 65, 62, 152, 150, 148, 146, 144, 141 ], + "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], "attributes": { "hdlname": "spi_if_ins o_data_in", - "src": "top.v:111.10-126.4|spi_if.v:8.22-8.31" + "src": "spi_if.v:8.22-8.31" + } + }, + "spi_if_ins.o_data_in_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 944 ], + "attributes": { } }, "spi_if_ins.o_fetch_cmd": { "hide_name": 0, - "bits": [ 81 ], + "bits": [ 95 ], "attributes": { "hdlname": "spi_if_ins o_fetch_cmd", - "src": "top.v:111.10-126.4|spi_if.v:11.22-11.33" + "src": "spi_if.v:11.22-11.33" } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 988, 899, 904 ], + "bits": [ 958, 957, 950 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36312,35 +39918,43 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 900 ], + "bits": [ 951 ], "attributes": { } }, + "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 3, 958, 959, 960 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "spi_if_ins.o_ioc": { "hide_name": 0, - "bits": [ 52, 58, 55, 57, 56 ], + "bits": [ 75, 97, 173, 172, 171 ], "attributes": { "hdlname": "spi_if_ins o_ioc", - "src": "top.v:111.10-126.4|spi_if.v:7.22-7.27" + "src": "spi_if.v:7.22-7.27" } }, "spi_if_ins.o_ioc_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 73 ], + "bits": [ 65 ], "attributes": { } }, "spi_if_ins.o_load_cmd": { "hide_name": 0, - "bits": [ 82 ], + "bits": [ 94 ], "attributes": { "hdlname": "spi_if_ins o_load_cmd", - "src": "top.v:111.10-126.4|spi_if.v:12.22-12.32" + "src": "spi_if.v:12.22-12.32" } }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 902, 903, 904, 3 ], + "bits": [ 953, 954 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36348,65 +39962,77 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 907 ], + "bits": [ 961 ], "attributes": { } }, + "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 958, 953, 954, 963 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 962, 963, 964 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 901 ], + "bits": [ 952 ], "attributes": { } }, - "spi_if_ins.o_load_cmd_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 49, 153 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "spi_if_ins.o_spi_miso": { "hide_name": 0, - "bits": [ 350 ], + "bits": [ 366 ], "attributes": { "hdlname": "spi_if_ins o_spi_miso", - "src": "top.v:111.10-126.4|spi_if.v:16.12-16.22" + "src": "spi_if.v:16.12-16.22" } }, "spi_if_ins.r_tx_byte": { "hide_name": 0, - "bits": [ 922, 921, 920, 919, 918, 917, 916, 915 ], + "bits": [ 973, 972, 971, 970, 969, 968, 967, 966 ], "attributes": { "hdlname": "spi_if_ins r_tx_byte", - "src": "top.v:111.10-126.4|spi_if.v:33.14-33.23" + "src": "spi_if.v:33.14-33.23" + } + }, + "spi_if_ins.r_tx_byte_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 965 ], + "attributes": { } }, "spi_if_ins.r_tx_data_valid": { "hide_name": 0, - "bits": [ 924 ], + "bits": [ 975 ], "attributes": { "hdlname": "spi_if_ins r_tx_data_valid", - "src": "top.v:111.10-126.4|spi_if.v:32.14-32.29" - } - }, - "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D": { - "hide_name": 0, - "bits": [ 906, 910, 3 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + "src": "spi_if.v:32.14-32.29" } }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 923 ], + "bits": [ 974 ], + "attributes": { + } + }, + "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O": { + "hide_name": 0, + "bits": [ 977 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 927, 926, 925 ], + "bits": [ 982, 981, 976 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36414,118 +40040,109 @@ }, "spi_if_ins.spi.SCKr": { "hide_name": 0, - "bits": [ 928, 926, 927 ], + "bits": [ 983, 981, 982 ], "attributes": { "hdlname": "spi_if_ins spi SCKr", - "src": "top.v:111.10-126.4|spi_slave.v:61.13-61.17|spi_if.v:43.13-54.4" - } - }, - "spi_if_ins.spi.SCKr_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 944, 931, 925 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + "src": "spi_slave.v:61.13-61.17" } }, "spi_if_ins.spi.i_spi_cs_b": { "hide_name": 0, - "bits": [ 46 ], + "bits": [ 48 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_cs_b", - "src": "top.v:111.10-126.4|spi_slave.v:13.16-13.26|spi_if.v:43.13-54.4" + "src": "spi_slave.v:13.16-13.26" } }, "spi_if_ins.spi.i_spi_mosi": { "hide_name": 0, - "bits": [ 44 ], + "bits": [ 46 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_mosi", - "src": "top.v:111.10-126.4|spi_slave.v:12.16-12.26|spi_if.v:43.13-54.4" + "src": "spi_slave.v:12.16-12.26" } }, "spi_if_ins.spi.i_spi_sck": { "hide_name": 0, - "bits": [ 45 ], + "bits": [ 47 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_sck", - "src": "top.v:111.10-126.4|spi_slave.v:10.16-10.25|spi_if.v:43.13-54.4" + "src": "spi_slave.v:10.16-10.25" } }, "spi_if_ins.spi.i_sys_clk": { "hide_name": 0, - "bits": [ 61 ], + "bits": [ 63 ], "attributes": { "hdlname": "spi_if_ins spi i_sys_clk", - "src": "top.v:111.10-126.4|spi_slave.v:3.22-3.31|spi_if.v:43.13-54.4" + "src": "spi_slave.v:3.22-3.31" } }, "spi_if_ins.spi.i_tx_byte": { "hide_name": 0, - "bits": [ 922, 921, 920, 919, 918, 917, 916, 915 ], + "bits": [ 973, 972, 971, 970, 969, 968, 967, 966 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_byte", - "src": "top.v:111.10-126.4|spi_slave.v:7.22-7.31|spi_if.v:43.13-54.4" + "src": "spi_slave.v:7.22-7.31" } }, "spi_if_ins.spi.i_tx_data_valid": { "hide_name": 0, - "bits": [ 924 ], + "bits": [ 975 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_data_valid", - "src": "top.v:111.10-126.4|spi_slave.v:6.22-6.37|spi_if.v:43.13-54.4" + "src": "spi_slave.v:6.22-6.37" } }, "spi_if_ins.spi.o_rx_byte": { "hide_name": 0, - "bits": [ 898, 897, 896, 895, 894, 889, 888, 892 ], + "bits": [ 949, 948, 947, 946, 945, 69, 68, 943 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_byte", - "src": "top.v:111.10-126.4|spi_slave.v:5.22-5.31|spi_if.v:43.13-54.4" + "src": "spi_slave.v:5.22-5.31" } }, "spi_if_ins.spi.o_rx_data_valid": { "hide_name": 0, - "bits": [ 904 ], + "bits": [ 958 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_data_valid", - "src": "top.v:111.10-126.4|spi_slave.v:4.22-4.37|spi_if.v:43.13-54.4" + "src": "spi_slave.v:4.22-4.37" } }, "spi_if_ins.spi.o_spi_miso": { "hide_name": 0, - "bits": [ 350 ], + "bits": [ 366 ], "attributes": { "hdlname": "spi_if_ins spi o_spi_miso", - "src": "top.v:111.10-126.4|spi_slave.v:11.16-11.26|spi_if.v:43.13-54.4" + "src": "spi_slave.v:11.16-11.26" } }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 941 ], + "bits": [ 993 ], "attributes": { - "src": "top.v:111.10-126.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 915, 943, 925 ], + "bits": [ 966, 976, 994 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 944, 945, 946, 947 ], + "bits": [ 995, 996, 997, 998 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2": { "hide_name": 0, - "bits": [ 952, 953, 929, 944 ], + "bits": [ 1001, 1005, 1006 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36533,84 +40150,87 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 942 ], + "bits": [ 976, 978, 979 ], "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "spi_if_ins.spi.r2_rx_done": { "hide_name": 0, - "bits": [ 959 ], + "bits": [ 1012 ], "attributes": { "hdlname": "spi_if_ins spi r2_rx_done", - "src": "top.v:111.10-126.4|spi_slave.v:21.7-21.17|spi_if.v:43.13-54.4" + "src": "spi_slave.v:21.7-21.17" } }, "spi_if_ins.spi.r3_rx_done": { "hide_name": 0, - "bits": [ 960 ], + "bits": [ 1013 ], "attributes": { "hdlname": "spi_if_ins spi r3_rx_done", - "src": "top.v:111.10-126.4|spi_slave.v:22.7-22.17|spi_if.v:43.13-54.4" + "src": "spi_slave.v:22.7-22.17" } }, "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 933 ], + "bits": [ 985 ], "attributes": { - "src": "top.v:111.10-126.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4" } }, "spi_if_ins.spi.r_rx_bit_count": { "hide_name": 0, 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"spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "0", 966, 967 ], + "bits": [ 1020 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" + "abc9_carry": "00000000000000000000000000000001", + "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, "spi_if_ins.spi.r_rx_byte": { "hide_name": 0, - "bits": [ 940, 939, 938, 937, 936, 935, 934, 932 ], + "bits": [ 992, 991, 990, 989, 988, 987, 986, 984 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_byte", - "src": "top.v:111.10-126.4|spi_slave.v:19.13-19.22|spi_if.v:43.13-54.4" + "src": "spi_slave.v:19.13-19.22" } }, "spi_if_ins.spi.r_rx_done": { "hide_name": 0, - "bits": [ 958 ], + "bits": [ 1011 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_done", - "src": "top.v:111.10-126.4|spi_slave.v:20.7-20.16|spi_if.v:43.13-54.4" + "src": "spi_slave.v:20.7-20.16" } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 46, 976 ], + "bits": [ 48, 1029 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36618,107 +40238,97 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 969 ], + "bits": [ 1022 ], "attributes": { } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 977 ], + "bits": [ 1030 ], "attributes": { } }, "spi_if_ins.spi.r_temp_rx_byte": { "hide_name": 0, - "bits": [ 975, 974, 973, 972, 971, 970, 968, "x" ], + "bits": [ 1028, 1027, 1026, 1025, 1024, 1023, 1021, "x" ], "attributes": { "hdlname": "spi_if_ins spi r_temp_rx_byte", - "src": "top.v:111.10-126.4|spi_slave.v:18.13-18.27|spi_if.v:43.13-54.4" + "src": "spi_slave.v:18.13-18.27" } }, "spi_if_ins.spi.r_tx_bit_count": { "hide_name": 0, - "bits": [ 929, 944, 930 ], + "bits": [ 1002, 1001, 995 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_bit_count", - "src": "top.v:111.10-126.4|spi_slave.v:17.13-17.27|spi_if.v:43.13-54.4" + "src": "spi_slave.v:17.13-17.27" } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 978, 982, 981 ], + "bits": [ 1031 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" } }, - "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": { + "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D": { "hide_name": 0, - "bits": [ "1", 929, 980 ], + "bits": [ 1033 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" } }, - "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R": { + "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 979 ], + "bits": [ 1032 ], "attributes": { } }, + "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1034 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, "spi_if_ins.spi.r_tx_byte": { "hide_name": 0, - "bits": [ 950, 948, 954, 956, 951, 949, 955, 957 ], + "bits": [ 1008, 1007, 1010, 1009, 1004, 1000, 1003, 999 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_byte", - "src": "top.v:111.10-126.4|spi_slave.v:23.13-23.22|spi_if.v:43.13-54.4" + "src": "spi_slave.v:23.13-23.22" } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 983 ], + "bits": [ 980 ], "attributes": { } }, "spi_if_ins.state_if": { "hide_name": 0, - "bits": [ 908, 909, 903 ], + "bits": [ 956, 955, 953 ], "attributes": { "hdlname": "spi_if_ins state_if", - "src": "top.v:111.10-126.4|spi_if.v:29.14-29.22" + "src": "spi_if.v:29.14-29.22" } }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 985 ], + "bits": [ 1037 ], "attributes": { } }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1": { + "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 986, 3 ], + "bits": [ 958, 959 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O": { + "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 904, 905, 906, 3 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_1_O_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 914 ], - "attributes": { - } - }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 910, 911, 912 ], + "bits": [ 3, 962, 1035 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36726,103 +40336,78 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 986, 892, 987 ], + "bits": [ 943, 959, 1038 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.state_if_SB_DFFESR_Q_2_D_SB_LUT4_O_I1": { - "hide_name": 0, - "bits": [ 988, 3, 904 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - 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"sys_ctrl_ins.i_cs_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 75, 1238, 1239, 1240 ], + "bits": [ 67 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:111.10-126.4|spi_if.v:65.11-70.18|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22", - "unused_bits": "1 2 3" - } - }, - "sys_ctrl_ins.i_cs_SB_LUT4_I2_I1": { - "hide_name": 0, - "bits": [ 989, 890, 81 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "sys_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 65, 62, 152, 150, 148, 146, 144, 141 ], + "bits": [ 89, 87, 84, 92, 91, 142, 141, 139 ], "attributes": { "hdlname": "sys_ctrl_ins i_data_in", - "src": "top.v:132.12-146.4|sys_ctrl.v:7.29-7.38" + "src": "sys_ctrl.v:7.29-7.38" } }, "sys_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 81 ], + "bits": [ 95 ], "attributes": { "hdlname": "sys_ctrl_ins i_fetch_cmd", - "src": "top.v:132.12-146.4|sys_ctrl.v:10.29-10.40" + "src": "sys_ctrl.v:10.29-10.40" } }, "sys_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 52, 58, 55, 57, 56 ], + "bits": [ 75, 97, 173, 172, 171 ], "attributes": { "hdlname": "sys_ctrl_ins i_ioc", - "src": "top.v:132.12-146.4|sys_ctrl.v:6.29-6.34" + "src": "sys_ctrl.v:6.29-6.34" } }, "sys_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 82 ], + "bits": [ 94 ], "attributes": { "hdlname": "sys_ctrl_ins i_load_cmd", - "src": "top.v:132.12-146.4|sys_ctrl.v:11.29-11.39" + "src": "sys_ctrl.v:11.29-11.39" } }, "sys_ctrl_ins.i_rst_b": { @@ -36830,61 +40415,15 @@ "bits": [ 3 ], "attributes": { "hdlname": "sys_ctrl_ins i_rst_b", - "src": "top.v:132.12-146.4|sys_ctrl.v:3.29-3.36" + "src": "sys_ctrl.v:3.29-3.36" } }, "sys_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 61 ], + "bits": [ 63 ], "attributes": { "hdlname": "sys_ctrl_ins i_sys_clk", - "src": "top.v:132.12-146.4|sys_ctrl.v:4.29-4.38" - } - }, - "sys_ctrl_ins.o_data_out": { - "hide_name": 0, - "bits": [ 1000, 997, 994, 992, "0", "0", "0", "0" ], - "attributes": { - "hdlname": "sys_ctrl_ins o_data_out", - "src": "top.v:132.12-146.4|sys_ctrl.v:8.29-8.39" - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D": { - "hide_name": 0, - "bits": [ 993 ], - "attributes": { - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D": { - "hide_name": 0, - "bits": [ 996 ], - "attributes": { - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D": { - "hide_name": 0, - "bits": [ 999 ], - "attributes": { - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_D": { - "hide_name": 0, - "bits": [ 991 ], - "attributes": { - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 81, 890, 82, 127 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 990 ], - "attributes": { + "src": "sys_ctrl.v:4.29-4.38" } }, "sys_ctrl_ins.o_debug_loopback_tx": { @@ -36892,7 +40431,7 @@ "bits": [ "x" ], "attributes": { "hdlname": "sys_ctrl_ins o_debug_loopback_tx", - "src": "top.v:132.12-146.4|sys_ctrl.v:17.29-17.48" + "src": "sys_ctrl.v:17.29-17.48" } }, "sys_ctrl_ins.o_tx_sample_gap": { @@ -36900,21 +40439,7 @@ "bits": [ "x", "x", "x", "x" ], "attributes": { "hdlname": "sys_ctrl_ins o_tx_sample_gap", - "src": "top.v:132.12-146.4|sys_ctrl.v:18.29-18.44" - } - }, - "sys_ctrl_ins.tx_sample_gap": { - "hide_name": 0, - "bits": [ 1001, 998, 995, 1002 ], - "attributes": { - "hdlname": "sys_ctrl_ins tx_sample_gap", - "src": "top.v:132.12-146.4|sys_ctrl.v:44.16-44.29" - } - }, - "sys_ctrl_ins.tx_sample_gap_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 913 ], - "attributes": { + "src": "sys_ctrl.v:18.29-18.44" } }, "tx_fifo.debug_pull": { @@ -36922,7 +40447,7 @@ "bits": [ "0" ], "attributes": { "hdlname": "tx_fifo debug_pull", - "src": "top.v:403.5-419.4|complex_fifo.v:19.18-19.28" + "src": "complex_fifo.v:19.18-19.28" } }, "tx_fifo.debug_push": { @@ -36930,98 +40455,90 @@ "bits": [ "0" ], "attributes": { "hdlname": "tx_fifo debug_push", - "src": "top.v:403.5-419.4|complex_fifo.v:20.18-20.28" + "src": "complex_fifo.v:20.18-20.28" } }, "tx_fifo.empty_o": { "hide_name": 0, - "bits": [ 339 ], + "bits": [ 336 ], "attributes": { "hdlname": "tx_fifo empty_o", - "src": "top.v:403.5-419.4|complex_fifo.v:17.19-17.26" + "src": "complex_fifo.v:17.19-17.26" } }, "tx_fifo.empty_o_SB_DFFNSS_Q_D": { "hide_name": 0, - "bits": [ 1004 ], + "bits": [ 1039 ], "attributes": { } }, - "tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0": { + "tx_fifo.empty_o_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 1005, 1006, 1007, 1008 ], + "bits": [ 358, 1042, 1041, 1043 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 1012, 1013 ], + "bits": [ 1049, 1054, 1055, 1044 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3": { "hide_name": 0, - "bits": [ 1018, 346, 1017, 1019 ], + "bits": [ 1050, 1051, 1052, 1053 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_DFFNSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0": { + "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1014, 1015, 1016, 1017 ], + "bits": [ 1045, 1046, 1047, 1048 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": 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"bits": [ 352 ], + "bits": [ 368 ], "attributes": { - "src": "top.v:391.8-391.22" + "src": "top.v:420.8-420.22" } }, "w_tx_fifo_pull": { "hide_name": 0, - "bits": [ 338 ], + "bits": [ 335 ], "attributes": { - "src": "top.v:397.8-397.22" + "src": "top.v:426.8-426.22" } } } diff --git a/firmware/top.v b/firmware/top.v index 3d07318..dd6d4c6 100644 --- a/firmware/top.v +++ b/firmware/top.v @@ -50,27 +50,28 @@ module top ( // // RPI PIN | FPGA TOP-LEVEL SIGNAL // ------------------------------------------------------------------------ - // GPIO2_SA3 | i_smi_a[2] - RX09 / RX24 channel select - // GPIO3_SA2 | i_smi_a[1] - Tx SMI (0) / Rx SMI (1) select - // GPIO4_SA1 | i_smi_a[0] - used as a sys async reset (GBIN1) + // GPIO2_SA3 | i_smi_a3 - RX09 / RX24 channel select + // GPIO3_SA2 | i_smi_a2 - Tx SMI (0) / Rx SMI (1) select + // GPIO4_SA1 | i_rst_b - used as a sys async reset (GBIN1) // GPIO5_SA0 | Not connected to FPGA (MixerRst) // // In order to perform SMI data bus direction selection (highZ / PushPull) // signal a[0] was chosen, while the '0' level (default) denotes RPI => FPGA // direction, and the DATA bus is highZ (recessive mode). - // The signal a[2] selects the RX source (900 MHZ or 2.4GHz) - // The signal a[1] can be used in the future for other purposes + // The signal i_smi_a2 selects Tx(0) or Rx(1) direction + // The signal i_smi_a3 selects the RX source (900 MHZ or 2.4GHz) + // - // Description | a[2] (SA3)| a[1] (SA2) | - // -------------|------------|---------------| - // | 0 | 0 | - // TX |------------| RPI => FPGA | - // | 1 | Data HighZ | - // -------------|------------|---------------| - // RX09 | 0 | 1 | - // -------------|------------| FPGA => RPI | - // RX24 | 1 | Data PushPull | - // -------------|------------|---------------| + // Description | a2 (SA2) | a3 (SA3) | + // -------------|---------------|------------| + // | 0 | 0 | + // TX | RPI => FPGA |------------| + // | Data HighZ | 1 | + // -------------|---------------|------------| + // RX09 | 1 | 0 | + // -------------| FPGA => RPI |------------| + // RX24 | Data PushPull | 1 | + // -------------|---------------|------------| input i_smi_a2, input i_smi_a3, @@ -105,6 +106,26 @@ module top ( wire [7:0] w_tx_data_io; wire [7:0] w_tx_data_smi; + wire w_rx_sync_type_09; + wire w_rx_sync_type_24; + wire w_tx_sync_type_09; + wire w_tx_sync_type_24; + + wire w_rx_sync_09; + wire w_rx_sync_24; + wire w_tx_sync_09; + wire w_tx_sync_24; + + wire w_rx_sync_input_09; + wire w_rx_sync_input_24; + wire w_tx_sync_input_09; + wire w_tx_sync_input_24; + + assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod[7] : w_rx_sync_09; + assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod[6] : w_rx_sync_24; + assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod[5] : w_tx_sync_09; + assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod[4] : w_tx_sync_24; + //========================================================================= // INSTANCES //========================================================================= @@ -138,11 +159,22 @@ module top ( .i_cs(w_cs[0]), .i_fetch_cmd(w_fetch), .i_load_cmd(w_load), + .o_debug_fifo_push(), .o_debug_fifo_pull(), .o_debug_smi_test(), .o_debug_loopback_tx(w_debug_lb_tx), .o_tx_sample_gap(tx_sample_gap), + + .o_rx_sync_type09(w_rx_sync_type_09), + .o_rx_sync_type24(w_rx_sync_type_24), + .o_tx_sync_type09(w_tx_sync_type_09), + .o_tx_sync_type24(w_tx_sync_type_24), + + .o_rx_sync_09(w_rx_sync_09), + .o_rx_sync_24(w_rx_sync_24), + .o_tx_sync_09(w_tx_sync_09), + .o_tx_sync_24(w_tx_sync_24) ); wire w_debug_fifo_push; @@ -167,7 +199,7 @@ module top ( .i_config(i_config), .o_led0 (/*o_led0*/), .o_led1 (/*o_led1*/), - .o_pmod (), + .o_pmod (io_pmod[3:0]), // Analog interfaces .o_mixer_fm(/*o_mixer_fm*/), @@ -266,7 +298,7 @@ module top ( // Non-inverting, P-side of pair SB_IO #( - .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_INPUT_REGISTER } + .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_OUTPUT_REGISTER } .IO_STANDARD("SB_LVCMOS"), ) iq_tx_p ( .PACKAGE_PIN(o_iq_tx_p), @@ -277,7 +309,7 @@ module top ( // Inverting, N-side of pair SB_IO #( - .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_INPUT_REGISTER } + .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_OUTPUT_REGISTER } .IO_STANDARD("SB_LVCMOS"), ) iq_tx_n ( .PACKAGE_PIN(o_iq_tx_n), @@ -318,7 +350,7 @@ module top ( .o_fifo_push(w_rx_09_fifo_push), .o_fifo_data (w_rx_09_fifo_data), - .i_sync_input (1'b0), + .i_sync_input (w_rx_sync_input_09), .o_debug_state() ); @@ -333,7 +365,7 @@ module top ( .o_fifo_push(w_rx_24_fifo_push), .o_fifo_data (w_rx_24_fifo_data), - .i_sync_input (1'b0), + .i_sync_input (w_rx_sync_input_24), .o_debug_state() ); @@ -344,9 +376,6 @@ module top ( wire [31:0] w_rx_fifo_pulled_data; wire w_rx_fifo_full; wire w_rx_fifo_empty; - wire channel; - - //assign channel = i_smi_a3; complex_fifo #( .ADDR_WIDTH(10), // 1024 samples @@ -382,12 +411,12 @@ module top ( .i_fifo_data(w_tx_fifo_pulled_data), .i_sample_gap(tx_sample_gap), .i_tx_state(~w_smi_data_direction), - .i_sync_input(1'b0), + .i_sync_input(w_tx_sync_input_09), .i_debug_lb(w_debug_lb_tx), .o_tx_state_bit(), .o_sync_state_bit(), ); - + wire w_tx_fifo_full; wire w_tx_fifo_empty; wire w_tx_fifo_read_clk; @@ -418,6 +447,11 @@ module top ( .debug_push(1'b0) ); + wire channel; + wire w_smi_data_direction; + //assign channel = i_smi_a3; + //assign w_smi_data_direction = i_smi_a2; + smi_ctrl smi_ctrl_ins ( .i_rst_b(i_rst_b), .i_sys_clk(w_clock_sys), @@ -446,7 +480,7 @@ module top ( .o_smi_read_req(w_smi_read_req), .o_smi_write_req(w_smi_write_req), .o_channel(channel), - .o_dir (/*w_smi_data_direction*/), + .o_dir (w_smi_data_direction), .i_smi_test(1'b0/*w_debug_smi_test*/), .o_cond_tx(), .o_address_error() @@ -456,7 +490,6 @@ module top ( wire [7:0] w_smi_data_input; wire w_smi_read_req; wire w_smi_write_req; - wire w_smi_data_direction; // the "Writing" flag indicates that the data[7:0] direction (inout) // from the FPGA's SMI module should be "output". This happens when the @@ -464,7 +497,6 @@ module top ( // The address has the MSB '1' when in RX mode. otherwise (when IDLE or TX) // the data is high-z, which is the more "recessive" mode - assign w_smi_data_direction = i_smi_a2; SB_IO #( .PIN_TYPE(6'b1010_01), .PULLUP (1'b0) @@ -538,8 +570,6 @@ module top ( .D_IN_0(w_smi_data_input[7]) ); - // We need the 'o_smi_write_req' to be 1 only when the direction is TX - // (w_smi_data_direction == 0) and the write fifo is not full assign o_smi_read_req = (w_smi_data_direction) ? w_smi_read_req : w_smi_write_req; assign o_smi_write_req = 1'bZ; diff --git a/software/libcariboulite/src/CaribouLite.hpp b/software/libcariboulite/src/CaribouLite.hpp index 3cabbda..462623a 100644 --- a/software/libcariboulite/src/CaribouLite.hpp +++ b/software/libcariboulite/src/CaribouLite.hpp @@ -175,7 +175,7 @@ public: void StartReceiving(); void StartReceivingInternal(size_t samples_per_chunk); void StopReceiving(void); - void StartTransmitting(std::function*, const bool*, size_t*)> on_data_request, size_t samples_per_chunk); + void StartTransmitting(void); void StartTransmittingLo(void); void StartTransmittingCw(void); void StopTransmitting(void); @@ -198,6 +198,7 @@ private: const CaribouLite* _device; const RadioType _type; + // Rx information bool _rx_thread_running; bool _rx_is_active; std::thread *_rx_thread; @@ -209,14 +210,12 @@ private: RxCbType _rxCallbackType; ApiType _api_type; - bool _tx_thread_running; + // Tx information bool _tx_is_active; - std::thread *_tx_thread; - std::function*, const bool*, size_t*)> _on_data_request; - size_t _tx_samples_per_chunk; // buffers cariboulite_sample_complex_int16 *_read_samples; + std::complex *_write_samples; cariboulite_sample_meta* _read_metadata; private: diff --git a/software/libcariboulite/src/CaribouLiteRadioCpp.cpp b/software/libcariboulite/src/CaribouLiteRadioCpp.cpp index 3f5209d..ace43ba 100644 --- a/software/libcariboulite/src/CaribouLiteRadioCpp.cpp +++ b/software/libcariboulite/src/CaribouLiteRadioCpp.cpp @@ -132,7 +132,32 @@ int CaribouLiteRadio::ReadSamples(std::complex* samples, size_t num_to_re //================================================================== int CaribouLiteRadio::WriteSamples(std::complex* samples, size_t num_to_write) { - return 0; + // fill in the _write_samples internal buffer + size_t written_so_far = 0; + size_t left_to_write = num_to_write; + size_t mtu_size = GetNativeMtuSample(); + + while (written_so_far < num_to_write) + { + size_t current_write = left_to_write; + size_t k = written_so_far; + if (current_write > mtu_size) current_write = mtu_size; + + for (size_t i = 0; i < current_write; i++, k++) + { + _write_samples[i].real((uint16_t)(samples[k].real() * 4096)); + _write_samples[i].imag((uint16_t)(samples[k].imag() * 4096)); + } + int ret = WriteSamples(_write_samples, current_write); + if (ret <= 0) + { + break; + } + written_so_far += ret; + left_to_write -= ret; + } + + return written_so_far; } //================================================================== @@ -143,20 +168,6 @@ int CaribouLiteRadio::WriteSamples(std::complex* samples, size_t num_to_w num_to_write); } -//================================================================== -void CaribouLiteRadio::CaribouLiteTxThread(CaribouLiteRadio* radio) -{ - while (radio->_tx_thread_running) - { - if (!radio->_tx_is_active) - { - std::this_thread::sleep_for(std::chrono::milliseconds(4)); - continue; - } - // TBD - } -} - //================================================================== CaribouLiteRadio::CaribouLiteRadio( const cariboulite_radio_state_st* radio, RadioType type, @@ -164,25 +175,26 @@ CaribouLiteRadio::CaribouLiteRadio( const cariboulite_radio_state_st* radio, const CaribouLite* parent) : _radio(radio), _device(parent), _type(type), _rxCallbackType(RxCbType::None), _api_type(api_type) { + size_t mtu_size = GetNativeMtuSample(); if (_api_type == Async) { //printf("Creating Radio Type %d ASYNC\n", type); _rx_thread_running = true; _rx_thread = new std::thread(CaribouLiteRadio::CaribouLiteRxThread, this); - - _tx_thread_running = true; - _tx_thread = new std::thread(CaribouLiteRadio::CaribouLiteTxThread, this); } else { //printf("Creating Radio Type %d SYNC\n", type); _read_samples = NULL; _read_metadata = NULL; - size_t mtu_size = GetNativeMtuSample(); + // allocate internal buffers - _read_samples = new cariboulite_sample_complex_int16[mtu_size]; + _read_samples = new cariboulite_sample_complex_int16[mtu_size]; _read_metadata = new cariboulite_sample_meta[mtu_size]; } + + _write_samples = NULL; + _write_samples = new std::complex[mtu_size]; } //================================================================== @@ -197,18 +209,18 @@ CaribouLiteRadio::~CaribouLiteRadio() _rx_thread_running = false; _rx_thread->join(); if (_rx_thread) delete _rx_thread; - - _tx_thread_running = false; - _tx_thread->join(); - if (_tx_thread) delete _tx_thread; } else { if (_read_samples) delete [] _read_samples; _read_samples = NULL; + if (_read_metadata) delete [] _read_metadata; _read_metadata = NULL; - } + } + + if (_write_samples) delete [] _write_samples; + _write_samples = NULL; } // Gain @@ -596,11 +608,9 @@ void CaribouLiteRadio::StopReceiving() } //================================================================== -void CaribouLiteRadio::StartTransmitting(std::function*, const bool*, size_t*)> on_data_request, size_t samples_per_chunk) +void CaribouLiteRadio::StartTransmitting() { _rx_is_active = false; - _on_data_request = on_data_request; - _tx_samples_per_chunk = samples_per_chunk; cariboulite_radio_activate_channel((cariboulite_radio_state_st*)_radio, cariboulite_channel_dir_rx, false); cariboulite_radio_set_cw_outputs((cariboulite_radio_state_st*)_radio, false, false); cariboulite_radio_activate_channel((cariboulite_radio_state_st*)_radio, cariboulite_channel_dir_tx, true); diff --git a/software/libcariboulite/src/at86rf215/at86rf215_radio.h b/software/libcariboulite/src/at86rf215/at86rf215_radio.h index 133d496..f0a37d3 100644 --- a/software/libcariboulite/src/at86rf215/at86rf215_radio.h +++ b/software/libcariboulite/src/at86rf215/at86rf215_radio.h @@ -90,10 +90,6 @@ typedef enum at86rf215_radio_rx_bw_BW1250KHZ_IF2000KHZ = 0x9, // at86rf215_radio_rx_f_cut_0_75_half_fs at86rf215_radio_rx_bw_BW1600KHZ_IF2000KHZ = 0xA, // at86rf215_radio_rx_f_cut_half_fs at86rf215_radio_rx_bw_BW2000KHZ_IF2000KHZ = 0xB, // at86rf215_radio_rx_f_cut_half_fs - at86rf215_radio_rx_bw_BW2000KHZ_IFCCKHZ = 0xC, // ** - at86rf215_radio_rx_bw_BW2000KHZ_IFDDHZ = 0xD, // ** - at86rf215_radio_rx_bw_BW2000KHZ_IFEEKHZ = 0xE, // ** - at86rf215_radio_rx_bw_BW2000KHZ_IFFFKHZ = 0xF, // ** } at86rf215_radio_rx_bw_en; typedef enum diff --git a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c index a5f492a..45a52f6 100644 --- a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c +++ b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c @@ -13,13 +13,14 @@ //-------------------------------------------------------------- // Static Definitions //-------------------------------------------------------------- -#define IOC_MOD_VER 0 -#define IOC_SYS_CTRL_SYS_VERSION 1 -#define IOC_SYS_CTRL_MANU_ID 2 -#define IOC_SYS_CTRL_SYS_ERR_STAT 3 -#define IOC_SYS_CTRL_SYS_SOFT_RST 4 -#define IOC_SYS_CTRL_DEBUG_MODES 5 -#define IOC_SYS_CTRL_SYS_TX_SAMPLE_GAP 6 +#define IOC_MOD_VER 0 +#define IOC_SYS_CTRL_SYS_VERSION 1 +#define IOC_SYS_CTRL_MANU_ID 2 +#define IOC_SYS_CTRL_SYS_ERR_STAT 3 +#define IOC_SYS_CTRL_SYS_SOFT_RST 4 +#define IOC_SYS_CTRL_DEBUG_MODES 5 +#define IOC_SYS_CTRL_TX_SAMPLE_GAP 6 +#define IOC_SYS_CTRL_SOFT_SYNC 7 #define IOC_IO_CTRL_MODE 1 #define IOC_IO_CTRL_DIG_PIN 2 @@ -31,7 +32,7 @@ #define IOC_SMI_CTRL_FIFO_STATUS 1 #define IOC_SMI_CHANNEL_SELECT 2 -#define IOC_SMI_CTRL_DIR_SELECT 3 +#define IOC_SMI_CTRL_DIR_SELECT 3 //-------------------------------------------------------------- // Internal Data-Types @@ -380,21 +381,42 @@ int caribou_fpga_get_errors (caribou_fpga_st* dev, uint8_t *err_map) .ioc = IOC_SYS_CTRL_SYS_ERR_STAT }; - *err_map = 0; - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), err_map); + if (err_map) + { + *err_map = 0; + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), err_map); + } + return -1; } //-------------------------------------------------------------- int caribou_fpga_set_sys_ctrl_tx_sample_gap (caribou_fpga_st* dev, uint8_t gap) { + uint8_t actual_val = 0; + uint8_t actual_gap = 0; CARIBOU_FPGA_CHECK_DEV(dev,"caribou_fpga_set_sys_ctrl_tx_sample_gap"); + + // read before write caribou_fpga_opcode_st oc = { - .rw = caribou_fpga_rw_write, + .rw = caribou_fpga_rw_read, .mid = caribou_fpga_mid_sys_ctrl, - .ioc = IOC_SYS_CTRL_SYS_TX_SAMPLE_GAP, + .ioc = IOC_SYS_CTRL_TX_SAMPLE_GAP, }; - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &gap); + int ret = caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &actual_val); + if (ret != 0) return -1; + + actual_gap = actual_val & 0xF; + actual_val &= 0xF0; + + if (gap != actual_gap) + { + // only if change is needed + oc.rw = caribou_fpga_rw_write; + actual_val |= (gap & 0xF); + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &actual_val); + } + return 0; } //-------------------------------------------------------------- @@ -406,14 +428,104 @@ int caribou_fpga_get_sys_ctrl_tx_sample_gap (caribou_fpga_st* dev, uint8_t *gap) { .rw = caribou_fpga_rw_read, .mid = caribou_fpga_mid_sys_ctrl, - .ioc = IOC_SYS_CTRL_SYS_TX_SAMPLE_GAP + .ioc = IOC_SYS_CTRL_TX_SAMPLE_GAP }; - *gap = 0; - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), gap); + uint8_t actual_gap = 0; + + int ret = caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &actual_gap); + + if (gap) *gap = actual_gap & 0xF; + return ret; } +//-------------------------------------------------------------- +int caribou_fpga_set_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sync_source_en rx_09, + caribou_fpga_sync_source_en rx_24, + caribou_fpga_sync_source_en tx_09, + caribou_fpga_sync_source_en tx_24) +{ + uint8_t actual_val = 0; + uint8_t temp = 0; + CARIBOU_FPGA_CHECK_DEV(dev,"caribou_fpga_set_sys_ctrl_sync_source"); + + // read before write + caribou_fpga_opcode_st oc = + { + .rw = caribou_fpga_rw_read, + .mid = caribou_fpga_mid_sys_ctrl, + .ioc = IOC_SYS_CTRL_TX_SAMPLE_GAP, + }; + int ret = caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &actual_val); + if (ret != 0) return -1; + + temp = actual_val & 0xF; + uint8_t cur_rx_09 = (actual_val >> 4) & 0x1; + uint8_t cur_rx_24 = (actual_val >> 5) & 0x1; + uint8_t cur_tx_09 = (actual_val >> 6) & 0x1; + uint8_t cur_tx_24 = (actual_val >> 7) & 0x1; + + if (rx_09 != caribou_fpga_sync_src_no_change) cur_rx_09 = rx_09 & 0x1; + if (rx_24 != caribou_fpga_sync_src_no_change) cur_rx_24 = rx_24 & 0x1; + if (tx_09 != caribou_fpga_sync_src_no_change) cur_tx_09 = tx_09 & 0x1; + if (tx_24 != caribou_fpga_sync_src_no_change) cur_tx_24 = tx_24 & 0x1; + + temp |= cur_rx_09 << 4; + temp |= cur_rx_24 << 5; + temp |= cur_tx_09 << 6; + temp |= cur_tx_24 << 7; + + oc.rw = caribou_fpga_rw_write; + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &temp); +} +//-------------------------------------------------------------- +int caribou_fpga_get_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sync_source_en *rx_09, + caribou_fpga_sync_source_en *rx_24, + caribou_fpga_sync_source_en *tx_09, + caribou_fpga_sync_source_en *tx_24) +{ + uint8_t temp = 0; + CARIBOU_FPGA_CHECK_DEV(dev,"caribou_fpga_get_sys_ctrl_sync_source"); + + // read before write + caribou_fpga_opcode_st oc = + { + .rw = caribou_fpga_rw_read, + .mid = caribou_fpga_mid_sys_ctrl, + .ioc = IOC_SYS_CTRL_TX_SAMPLE_GAP, + }; + int ret = caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &temp); + if (ret != 0) return -1; + + if (rx_09) *rx_09 = (temp >> 4) & 0x1; + if (rx_24) *rx_24 = (temp >> 5) & 0x1; + if (tx_09) *tx_09 = (temp >> 6) & 0x1; + if (tx_24) *tx_24 = (temp >> 7) & 0x1; + + return 0; +} + +//-------------------------------------------------------------- +int caribou_fpga_set_sys_ctrl_soft_sync_value (caribou_fpga_st* dev, uint8_t rx_09, + uint8_t rx_24, + uint8_t tx_09, + uint8_t tx_24) +{ + uint8_t temp = (rx_09 & 0xf) | ((tx_09 & 0xf) << 1) | ((rx_24 & 0xf) << 2) | ((tx_24 & 0xf) << 3); + CARIBOU_FPGA_CHECK_DEV(dev,"caribou_fpga_set_sys_ctrl_soft_sync_value"); + + // read before write + caribou_fpga_opcode_st oc = + { + .rw = caribou_fpga_rw_write, + .mid = caribou_fpga_mid_sys_ctrl, + .ioc = IOC_SYS_CTRL_SOFT_SYNC, + }; + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &temp); +} + +//-------------------------------------------------------------- // I/O Controller int caribou_fpga_set_io_ctrl_mode (caribou_fpga_st* dev, uint8_t debug_mode, caribou_fpga_io_ctrl_rfm_en rfm) { @@ -445,8 +557,8 @@ int caribou_fpga_get_io_ctrl_mode (caribou_fpga_st* dev, uint8_t* debug_mode, ca uint8_t mode = 0; caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &mode); - *debug_mode = mode & 0x3; - *rfm = (mode >> 2) & 0x7; + if (debug_mode) *debug_mode = mode & 0x3; + if (rfm) *rfm = (mode >> 2) & 0x7; return 0; } @@ -512,8 +624,12 @@ int caribou_fpga_get_io_ctrl_pmod_dir (caribou_fpga_st* dev, uint8_t *dir) .mid = caribou_fpga_mid_io_ctrl, .ioc = IOC_IO_CTRL_PMOD_DIR }; - *dir = 0; - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), dir); + if (dir) + { + *dir = 0; + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), dir); + } + return -1; } //-------------------------------------------------------------- @@ -540,8 +656,12 @@ int caribou_fpga_get_io_ctrl_pmod_val (caribou_fpga_st* dev, uint8_t *val) .mid = caribou_fpga_mid_io_ctrl, .ioc = IOC_IO_CTRL_PMOD_VAL }; - *val = 0; - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), val); + if (val) + { + *val = 0; + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), val); + } + return -1; } //-------------------------------------------------------------- @@ -568,8 +688,12 @@ int caribou_fpga_get_io_ctrl_rf_state (caribou_fpga_st* dev, caribou_fpga_rf_pin .mid = caribou_fpga_mid_io_ctrl, .ioc = IOC_IO_CTRL_RF_PIN }; - memset(pins, 0, sizeof(caribou_fpga_rf_pin_st)); - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), (uint8_t*)pins); + if (pins) + { + memset(pins, 0, sizeof(caribou_fpga_rf_pin_st)); + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), (uint8_t*)pins); + } + return -1; } //-------------------------------------------------------------- @@ -583,8 +707,12 @@ int caribou_fpga_get_smi_ctrl_fifo_status (caribou_fpga_st* dev, caribou_fpga_sm .mid = caribou_fpga_mid_smi_ctrl, .ioc = IOC_SMI_CTRL_FIFO_STATUS }; - memset(status, 0, sizeof(caribou_fpga_smi_fifo_status_st)); - return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), (uint8_t*)status); + if (status) + { + memset(status, 0, sizeof(caribou_fpga_smi_fifo_status_st)); + return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), (uint8_t*)status); + } + return -1; } //-------------------------------------------------------------- diff --git a/software/libcariboulite/src/caribou_fpga/caribou_fpga.h b/software/libcariboulite/src/caribou_fpga/caribou_fpga.h index 25c31c3..94d4638 100644 --- a/software/libcariboulite/src/caribou_fpga/caribou_fpga.h +++ b/software/libcariboulite/src/caribou_fpga/caribou_fpga.h @@ -98,6 +98,20 @@ typedef enum caribou_fpga_smi_channel_1 = 1, } caribou_fpga_smi_channel_en; +/** + * @brief Syncronization bit (metadata) source. Either software + * setting using "caribou_fpga_set_sys_ctrl_soft_sync_value" + * or by using an external pulse on the PMOD 6/7 pins. + * If no change is needed on a specific sync source, + * "caribou_fpga_sync_src_no_change" should be used + */ +typedef enum +{ + caribou_fpga_sync_src_soft = 0, + caribou_fpga_sync_src_pmod = 1, + caribou_fpga_sync_src_no_change = 2, +} caribou_fpga_sync_source_en; + #pragma pack() /** @@ -154,6 +168,19 @@ int caribou_fpga_set_debug_modes (caribou_fpga_st* dev, bool dbg_fifo_push, bool int caribou_fpga_set_sys_ctrl_tx_sample_gap (caribou_fpga_st* dev, uint8_t gap); int caribou_fpga_get_sys_ctrl_tx_sample_gap (caribou_fpga_st* dev, uint8_t *gap); +int caribou_fpga_set_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sync_source_en rx_09, + caribou_fpga_sync_source_en rx_24, + caribou_fpga_sync_source_en tx_09, + caribou_fpga_sync_source_en tx_24); +int caribou_fpga_get_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sync_source_en *rx_09, + caribou_fpga_sync_source_en *rx_24, + caribou_fpga_sync_source_en *tx_09, + caribou_fpga_sync_source_en *tx_24); + +int caribou_fpga_set_sys_ctrl_soft_sync_value (caribou_fpga_st* dev, uint8_t rx_09, + uint8_t rx_24, + uint8_t tx_09, + uint8_t tx_24); // I/O Controller int caribou_fpga_set_io_ctrl_mode (caribou_fpga_st* dev, uint8_t debug_mode, caribou_fpga_io_ctrl_rfm_en rfm); int caribou_fpga_get_io_ctrl_mode (caribou_fpga_st* dev, uint8_t *debug_mode, caribou_fpga_io_ctrl_rfm_en *rfm); diff --git a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h index 0e49cb7..a45c7fd 100644 --- a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h +++ b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h @@ -17,161 +17,249 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-02-28 - * Time: 01:39:42 + * Date: 2024-03-14 + * Time: 22:57:13 */ struct tm smi_stream_dev_date_time = { - .tm_sec = 42, - .tm_min = 39, - .tm_hour = 1, - .tm_mday = 28, - .tm_mon = 1, /* +1 */ + .tm_sec = 13, + .tm_min = 57, + .tm_hour = 22, + .tm_mday = 14, + .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ }; /* * Data blob of variable smi_stream_dev: - * Size: 35328 bytes + * Size: 35224 bytes * Original filename: /home/pi/cariboulite/driver/build/smi_stream_dev.ko */ uint8_t smi_stream_dev[] = { 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xB7, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x28, 0x00, 0x27, 0x00, 0x3F, 0x23, 0x03, 0xD5, 0x00, 0x00, 0x40, 0xB9, 0xBF, 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0x71, 0xE0, 0x14, 0x00, 0x54, - 0x3F, 0x10, 0x04, 0x71, 0x00, 0x01, 0x00, 0x54, 0x3F, 0x08, 0x04, 0x71, 0x60, 0x13, 0x00, 0x54, - 0xA8, 0x00, 0x00, 0x54, 0x3F, 0x00, 0x04, 0x71, 0x80, 0x0F, 0x00, 0x54, 0x3F, 0x04, 0x04, 0x71, - 0x80, 0x0A, 0x00, 0x54, 0x00, 0x00, 0x00, 0x90, 0xE2, 0x03, 0x01, 0x2A, 0x14, 0x03, 0x80, 0x92, + 0x69, 0x18, 0x00, 0x54, 0x01, 0x00, 0x00, 0x90, 0xB4, 0x02, 0x80, 0x92, 0x21, 0x00, 0x00, 0x91, + 0x00, 0x00, 0x00, 0x94, 0xCA, 0xFF, 0xFF, 0x17, 0x3F, 0x0C, 0x04, 0x71, 0x00, 0x15, 0x00, 0x54, + 0x3F, 0x10, 0x04, 0x71, 0x00, 0x01, 0x00, 0x54, 0x3F, 0x08, 0x04, 0x71, 0x80, 0x13, 0x00, 0x54, + 0xA8, 0x00, 0x00, 0x54, 0x3F, 0x00, 0x04, 0x71, 0xA0, 0x0F, 0x00, 0x54, 0x3F, 0x04, 0x04, 0x71, + 0xA0, 0x0A, 0x00, 0x54, 0x00, 0x00, 0x00, 0x90, 0xE2, 0x03, 0x01, 0x2A, 0x14, 0x03, 0x80, 0x92, 0x01, 0x00, 0x00, 0x90, 0x00, 0x00, 0x40, 0xF9, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xB6, 0xFF, 0xFF, 0x17, 0xE0, 0x03, 0x02, 0xAA, 0x01, 0x41, 0x38, 0xD5, 0x22, 0x2C, 0x40, 0xB9, 0xE2, 0x03, 0xA8, 0x36, 0x61, 0xDE, 0x40, 0x93, 0x73, 0x02, 0x01, 0x8A, - 0xE1, 0x93, 0x7E, 0xB2, 0x7F, 0x02, 0x01, 0xEB, 0xE9, 0x06, 0x00, 0x54, 0x00, 0x00, 0x00, 0x90, + 0xE1, 0x93, 0x7E, 0xB2, 0x7F, 0x02, 0x01, 0xEB, 0x09, 0x07, 0x00, 0x54, 0x00, 0x00, 0x00, 0x90, 0x01, 0x00, 0x00, 0x90, 0x14, 0x00, 0x80, 0xD2, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xA5, 0xFF, 0xFF, 0x17, 0xE0, 0x03, 0x02, 0xAA, 0x01, 0x41, 0x38, 0xD5, 0x22, 0x2C, 0x40, 0xB9, 0xC2, 0x02, 0xA8, 0x36, 0x61, 0xDE, 0x40, 0x93, @@ -183,308 +271,193 @@ uint8_t smi_stream_dev[] = { 0x21, 0x00, 0x40, 0xF9, 0x3F, 0x00, 0x06, 0x72, 0x21, 0xFD, 0xFF, 0x54, 0xEA, 0xFF, 0xFF, 0x17, 0x00, 0xF8, 0x48, 0x92, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x21, 0x40, 0x03, 0x91, 0x82, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 0xC0, 0xFC, 0xFF, 0xB5, 0x14, 0x00, 0x80, 0xD2, - 0x7F, 0xFF, 0xFF, 0x17, 0x00, 0xF8, 0x48, 0x92, 0x01, 0x00, 0x00, 0x90, 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36, - .tm_hour = 20, - .tm_mday = 13, + .tm_sec = 51, + .tm_min = 58, + .tm_hour = 22, + .tm_mday = 14, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ }; @@ -38,379 +38,379 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x50, 0x07, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x20, 0x00, 0x01, 0x0B, 0xAE, 0x00, 0x00, 0x40, 0x04, 0x02, + 0x36, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -421,751 +421,752 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x1E, 0x52, 0x80, 0xC0, 0x08, 0xA0, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0A, 0x50, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x80, 0x04, 0x21, 0x54, 0x01, 0xA5, 0x01, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x08, 0x00, 0x0F, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x10, 0xB0, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x08, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x1E, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x58, 0x0D, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xCA, 0x13, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/software/libcariboulite/src/cariboulite_radio.c b/software/libcariboulite/src/cariboulite_radio.c index 962035a..6992478 100644 --- a/software/libcariboulite/src/cariboulite_radio.c +++ b/software/libcariboulite/src/cariboulite_radio.c @@ -18,12 +18,13 @@ #include "cariboulite_events.h" #include "cariboulite_setup.h" + #define GET_MODEM_CH(rad_ch) ((rad_ch)==cariboulite_channel_s1g ? at86rf215_rf_channel_900mhz : at86rf215_rf_channel_2400mhz) #define GET_SMI_CH(rad_ch) ((rad_ch)==cariboulite_channel_s1g ? caribou_smi_channel_900 : caribou_smi_channel_2400) -static float sample_rate_middles[] = {3000, 1666, 1166, 900, 733, 583, 450}; -static float rx_bandwidth_middles[] = {225, 281, 356, 450, 562, 706, 893, 1125, 1406, 1781, 2250}; -static float tx_bandwidth_middles[] = {90, 112, 142, 180, 225, 282, 357, 450, 562, 712, 900}; +static float sample_rate_middles[] = {3000e3, 1666e3, 1166e3, 900e3, 733e3, 583e3, 450e3}; +static float rx_bandwidth_middles[] = {225e3, 281e3, 356e3, 450e3, 562e3, 706e3, 893e3, 1125e3, 1406e3, 1781e3, 2250e3}; +static float tx_bandwidth_middles[] = {90e3, 112e3, 142e3, 180e3, 225e3, 282e3, 357e3, 450e3, 562e3, 712e3, 900e3}; //========================================================================= @@ -187,8 +188,30 @@ int cariboulite_radio_set_rx_bandwidth(cariboulite_radio_state_st* radio, cariboulite_radio_rx_bw_en rx_bw) { cariboulite_radio_f_cut_en fcut = cariboulite_radio_rx_f_cut_half_fs; + + /*if (rx_bw == cariboulite_radio_rx_bw_2500KHz || rx_bw == cariboulite_radio_rx_bw_2000KHz) + { + fcut = cariboulite_radio_rx_f_cut_half_fs; // 2MHz cuttof + } + else if (rx_bw == cariboulite_radio_rx_bw_1562KHz || + rx_bw == cariboulite_radio_rx_bw_1250KHz || + rx_bw == cariboulite_radio_rx_bw_1000KHz) + { + fcut = cariboulite_radio_rx_f_cut_0_75_half_fs; // 1.5MHz cuttof + } + else if (rx_bw == cariboulite_radio_rx_bw_787KHz || + rx_bw == cariboulite_radio_rx_bw_625KHz) + { + fcut = cariboulite_radio_rx_f_cut_0_5_half_fs; // 1MHz cuttof + } + else + { + fcut = cariboulite_radio_rx_f_cut_0_25_half_fs; // 500kHz cuttof + }*/ + + radio->rx_fcut = fcut; - + at86rf215_radio_set_rx_bw_samp_st cfg = { .inverter_sign_if = 0, @@ -197,8 +220,8 @@ int cariboulite_radio_set_rx_bandwidth(cariboulite_radio_state_st* radio, // to channel scheme. This increases the IF frequency to max 2.5MHz // thus places the internal LO fasr away from the signal => lower noise .bw = (at86rf215_radio_rx_bw_en)rx_bw, - .fcut = (at86rf215_radio_f_cut_en)radio->rx_fcut, // keep the same - .fs = (at86rf215_radio_sample_rate_en)radio->rx_fs, // keep the same + .fcut = (at86rf215_radio_f_cut_en)radio->rx_fcut, + .fs = (at86rf215_radio_sample_rate_en)radio->rx_fs, }; at86rf215_radio_set_rx_bandwidth_sampling(&radio->sys->modem, GET_MODEM_CH(radio->type), &cfg); radio->rx_bw = rx_bw; @@ -1053,12 +1076,11 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, // then deactivate the modem's stream cariboulite_radio_set_modem_state(radio, cariboulite_radio_state_cmd_trx_off); + ret = caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_idle); // DEACTIVATION if (!activate) { - // if we deactivate, first shut off the smi stream - ret = caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_idle); return ret; } @@ -1088,14 +1110,7 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, // Activate the channel according to the configurations // RX on both channels looks the same if (radio->channel_direction == cariboulite_channel_dir_rx) - { - // Setup the IQ stream properties - smi_stream_state_en smi_state = smi_stream_idle; - if (radio->smi_channel_id == caribou_smi_channel_900) - smi_state = smi_stream_rx_channel_0; - else if (radio->smi_channel_id == caribou_smi_channel_2400) - smi_state = smi_stream_rx_channel_1; - + { at86rf215_iq_interface_config_st modem_iq_config = { .loopback_enable = radio->tx_loopback_anabled, .drv_strength = at86rf215_iq_drive_current_4ma, @@ -1105,11 +1120,29 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, .radio24_mode = at86rf215_iq_if_mode, .clock_skew = at86rf215_iq_clock_data_skew_4_906ns, }; - at86rf215_setup_iq_if(&radio->sys->modem, &modem_iq_config); - + + // Setup the IQ stream properties + smi_stream_state_en smi_state = smi_stream_idle; + if (radio->smi_channel_id == caribou_smi_channel_900) + { + modem_iq_config.radio09_mode = at86rf215_iq_if_mode; + modem_iq_config.radio24_mode = at86rf215_baseband_mode; + modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_4_906ns; + smi_state = smi_stream_rx_channel_0; + } + else if (radio->smi_channel_id == caribou_smi_channel_2400) + { + modem_iq_config.radio09_mode = at86rf215_baseband_mode; + modem_iq_config.radio24_mode = at86rf215_iq_if_mode; + modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_2_906ns; + smi_state = smi_stream_rx_channel_1; + } + + at86rf215_setup_iq_if(&radio->sys->modem, &modem_iq_config); + // configure FPGA with the correct rx channel caribou_fpga_set_smi_channel (&radio->sys->fpga, radio->type == cariboulite_channel_s1g? caribou_fpga_smi_channel_0 : caribou_fpga_smi_channel_1); - //caribou_fpga_set_io_ctrl_dig (&radio->sys->fpga, radio->type == cariboulite_channel_s1g? 0 : 1, 0); + caribou_fpga_set_smi_ctrl_data_direction(&radio->sys->fpga, 1); // turn on the modem RX cariboulite_radio_set_modem_state(radio, cariboulite_radio_state_cmd_rx); @@ -1135,7 +1168,7 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, .tx_control_with_iq_if = !radio->cw_output, .radio09_mode = at86rf215_iq_if_mode, .radio24_mode = at86rf215_iq_if_mode, - .clock_skew = at86rf215_iq_clock_data_skew_4_906ns, + .clock_skew = at86rf215_iq_clock_data_skew_2_906ns, }; at86rf215_setup_iq_if(&radio->sys->modem, &modem_iq_config); diff --git a/software/libcariboulite/src/rffc507x/rffc507x.c b/software/libcariboulite/src/rffc507x/rffc507x.c index a3355e3..cd152d1 100644 --- a/software/libcariboulite/src/rffc507x/rffc507x.c +++ b/software/libcariboulite/src/rffc507x/rffc507x.c @@ -157,7 +157,7 @@ int rffc507x_init( rffc507x_st* dev, set_RFFC507X_CTMAX(dev, 127); set_RFFC507X_P2CTV(dev, 12); set_RFFC507X_FULLD(dev, 0);*/ - set_RFFC507X_P2MIXIDD(dev, 4); + set_RFFC507X_P2MIXIDD(dev, 5); // Others set_RFFC507X_LDEN(dev, 1);