kopia lustrzana https://github.com/cariboulabs/cariboulite
Kernel module SMI
integration of TX stream dma reader and writer corrections using mb() for memory boundarybug_fixes_integration_tx
David Michaeli
rodzic
0595990c8d
commit
35d4a04295
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@ -1,166 +0,0 @@
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <sys/ioctl.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <sched.h>
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#include <errno.h>
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#include <pthread.h>
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#include "../caribou_smi.h"
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#include "old/bcm2835_smi.h"
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#define SMI_STREAM_IOC_GET_NATIVE_BUF_SIZE _IO(BCM2835_SMI_IOC_MAGIC, 3)
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#define SMI_STREAM_IOC_SET_NON_BLOCK_READ _IO(BCM2835_SMI_IOC_MAGIC, 4)
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#define SMI_STREAM_IOC_SET_NON_BLOCK_WRITE _IO(BCM2835_SMI_IOC_MAGIC, 5)
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#define SMI_STREAM_IOC_SET_STREAM_STATUS _IO(BCM2835_SMI_IOC_MAGIC, 6)
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static void setup_settings (struct smi_settings *settings)
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{
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settings->read_setup_time = 0;
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settings->read_strobe_time = 5;
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settings->read_hold_time = 0;
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settings->read_pace_time = 0;
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settings->write_setup_time = 0;
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settings->write_hold_time = 0;
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settings->write_pace_time = 0;
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settings->write_strobe_time = 4;
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settings->data_width = SMI_WIDTH_8BIT;
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settings->dma_enable = 1;
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settings->pack_data = 1;
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settings->dma_passthrough_enable = 1;
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}
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pthread_t tid;
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int fd = -1;
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size_t native_batch_length_bytes = 0;
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int thread_running = 0;
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void* read_thread(void *arg)
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{
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fd_set set;
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int rv;
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int timeout_num_millisec = 500;
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uint8_t *buffer = malloc(native_batch_length_bytes);
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int size_of_buf = native_batch_length_bytes;
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while (thread_running)
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{
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while (1)
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{
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struct timeval timeout = {0};
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FD_ZERO(&set); // clear the set mask
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FD_SET(fd, &set); // add our file descriptor to the set - and only it
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int num_sec = timeout_num_millisec / 1000;
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timeout.tv_sec = num_sec;
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timeout.tv_usec = (timeout_num_millisec - num_sec*1000) * 1000;
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rv = select(fd + 1, &set, NULL, NULL, &timeout);
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if(rv == -1)
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{
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int error = errno;
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switch(error)
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{
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case EINTR: // A signal was caught.
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continue;
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case EBADF: // An invalid file descriptor was given in one of the sets.
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// (Perhaps a file descriptor that was already closed, or one on which an error has occurred.)
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case EINVAL: // nfds is negative or the value contained within timeout is invalid.
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case ENOMEM: // unable to allocate memory for internal tables.
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default: goto exit;
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};
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}
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else if (rv == 0)
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{
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printf("Read poll timeout\n");
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break;
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}
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else if (FD_ISSET(fd, &set))
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{
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int num_read = read(fd, buffer, size_of_buf);
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printf("Read %d bytes\n", num_read);
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break;
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}
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}
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}
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exit:
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free(buffer);
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return NULL;
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}
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int main()
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{
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char smi_file[] = "/dev/smi";
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struct smi_settings settings = {0};
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fd = open(smi_file, O_RDWR);
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if (fd < 0)
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{
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printf("can't open smi driver file '%s'\n", smi_file);
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return -1;
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}
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// Get the current settings
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int ret = ioctl(fd, BCM2835_SMI_IOC_GET_SETTINGS, &settings);
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if (ret != 0)
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{
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printf("failed reading ioctl from smi fd (settings)\n");
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close (fd);
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return -1;
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}
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// apply the new settings
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setup_settings(&settings);
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ret = ioctl(fd, BCM2835_SMI_IOC_WRITE_SETTINGS, &settings);
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if (ret != 0)
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{
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printf("failed writing ioctl to the smi fd (settings)\n");
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close (fd);
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return -1;
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}
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// set the address to idle
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ret = ioctl(fd, BCM2835_SMI_IOC_ADDRESS, caribou_smi_address_idle);
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if (ret != 0)
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{
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printf("failed setting smi address (idle / %d) to device\n", caribou_smi_address_idle);
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close (fd);
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return -1;
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}
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// get the native batch length in bytes
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ret = ioctl(fd, SMI_STREAM_IOC_GET_NATIVE_BUF_SIZE, &native_batch_length_bytes);
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if (ret != 0)
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{
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printf("failed reading native batch length, setting default\n");
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native_batch_length_bytes = (1024)*(1024)/2;
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}
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printf("Native batch size: %u\n", native_batch_length_bytes);
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// start streaming data
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ret = ioctl(fd, SMI_STREAM_IOC_SET_STREAM_STATUS, 1);
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// start the reader thread
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thread_running = 1;
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int err = pthread_create(&tid, NULL, &read_thread, NULL);
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if (err != 0)
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{
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printf("\ncan't create thread :[%s]", strerror(err));
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}
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getchar();
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thread_running = 0;
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pthread_join(tid, NULL);
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ret = ioctl(fd, SMI_STREAM_IOC_SET_STREAM_STATUS, 0);
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close (fd);
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return 0;
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}
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@ -176,7 +176,7 @@ static void set_state(smi_stream_state_en state)
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{
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inst->cur_address = (smi_stream_dir_device_to_smi<<ADDR_DIR_OFFSET) | (smi_stream_channel_1<<ADDR_CH_OFFSET);
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}
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else if (state == smi_stream_tx)
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else if (state == smi_stream_tx_channel)
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{
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inst->cur_address = smi_stream_dir_smi_to_device<<ADDR_DIR_OFFSET;
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}
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@ -250,17 +250,21 @@ static inline int smi_enabled(struct bcm2835_smi_instance *inst)
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}*/
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/***************************************************************************/
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static void smi_init_programmed_read(struct bcm2835_smi_instance *smi_inst, int num_transfers)
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static int smi_init_programmed_read(struct bcm2835_smi_instance *smi_inst, int num_transfers)
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{
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int smics_temp;
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int success = 0;
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/* Disable the peripheral: */
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smics_temp = read_smi_reg(smi_inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
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write_smi_reg(smi_inst, smics_temp, SMICS);
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// wait for the ENABLE to go low
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while (read_smi_reg(smi_inst, SMICS) & SMICS_ENABLE)
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;
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BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 100000U, success);
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if (!success)
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{
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return -1;
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}
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/* Program the transfer count: */
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write_smi_reg(smi_inst, num_transfers, SMIL);
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@ -274,31 +278,38 @@ static void smi_init_programmed_read(struct bcm2835_smi_instance *smi_inst, int
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/* IO barrier - to be sure that the last request have
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been dispatched in the correct order
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*/
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smp_mb();
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mb();
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// busy wait as long as the transaction is active (taking place)
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while (read_smi_reg(smi_inst, SMICS) & SMICS_ACTIVE)
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;
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BUSY_WAIT_WHILE_TIMEOUT(smi_is_active(smi_inst), 100000U, success);
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if (!success)
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{
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return -2;
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}
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// Clear the FIFO (reset it to zero contents)
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write_smi_reg(smi_inst, smics_temp, SMICS);
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// Start the transaction
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smics_temp |= SMICS_START;
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write_smi_reg(smi_inst, smics_temp, SMICS);
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return 0;
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}
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/***************************************************************************/
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static void smi_init_programmed_write(struct bcm2835_smi_instance *smi_inst, int num_transfers)
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static int smi_init_programmed_write(struct bcm2835_smi_instance *smi_inst, int num_transfers)
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{
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int smics_temp;
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int success = 0;
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/* Disable the peripheral: */
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smics_temp = read_smi_reg(smi_inst, SMICS) & ~SMICS_ENABLE;
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write_smi_reg(smi_inst, smics_temp, SMICS);
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// Wait as long as the SMI is still enabled
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while (read_smi_reg(smi_inst, SMICS) & SMICS_ENABLE)
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;
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BUSY_WAIT_WHILE_TIMEOUT(smi_enabled(smi_inst), 100000U, success);
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if (!success)
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{
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return -1;
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}
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/* Program the transfer count: */
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write_smi_reg(smi_inst, num_transfers, SMIL);
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@ -309,6 +320,7 @@ static void smi_init_programmed_write(struct bcm2835_smi_instance *smi_inst, int
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smics_temp |= SMICS_START;
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write_smi_reg(smi_inst, smics_temp, SMICS);
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return 0;
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}
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@ -488,11 +500,23 @@ ssize_t stream_smi_user_dma( struct bcm2835_smi_instance *inst,
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// we have only 8 bit width
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if (dma_dir == DMA_DEV_TO_MEM)
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{
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smi_init_programmed_read(inst, DMA_BOUNCE_BUFFER_SIZE);
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int ret = smi_init_programmed_read(inst, DMA_BOUNCE_BUFFER_SIZE);
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if (ret != 0)
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{
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spin_unlock(&inst->transaction_lock);
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dev_err(inst->dev, "smi_init_programmed_read returned %d", ret);
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return 0;
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}
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}
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else
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{
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smi_init_programmed_write(inst, DMA_BOUNCE_BUFFER_SIZE);
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int ret = smi_init_programmed_write(inst, DMA_BOUNCE_BUFFER_SIZE);
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if (ret != 0)
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{
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spin_unlock(&inst->transaction_lock);
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dev_err(inst->dev, "smi_init_programmed_write returned %d", ret);
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return 0;
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}
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}
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//printk(KERN_ERR DRIVER_NAME": SPIN-UNLOCK\n");
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@ -517,6 +541,10 @@ int reader_thread_stream_function(void *pv)
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// check if the streaming state is on, if not, sleep and check again
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if (inst->state != smi_stream_rx_channel_0 && inst->state != smi_stream_rx_channel_1)
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{
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//mutex_lock(&inst->read_lock);
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//kfifo_reset(&inst->rx_fifo);
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//mutex_unlock(&inst->read_lock);
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msleep(5);
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continue;
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}
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@ -531,8 +559,10 @@ int reader_thread_stream_function(void *pv)
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count = stream_smi_user_dma(inst->smi_inst, DMA_DEV_TO_MEM, &bounce, current_dma_buffer);
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if (count != DMA_BOUNCE_BUFFER_SIZE || bounce == NULL)
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{
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dev_err(inst->dev, "reader_thread return illegal count = %d", count);
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//current_dma_buffer = 1-current_dma_buffer;
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dev_err(inst->dev, "stream_smi_user_dma returned illegal count = %d", count);
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spin_lock(&inst->smi_inst->transaction_lock);
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dmaengine_terminate_sync(inst->smi_inst->dma_chan);
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spin_unlock(&inst->smi_inst->transaction_lock);
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continue;
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}
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@ -570,7 +600,10 @@ int reader_thread_stream_function(void *pv)
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// try to wait more, unless someone tells us to stop
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if (down_timeout(&bounce->callback_sem, msecs_to_jiffies(1000)))
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{
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dev_info(inst->dev, "DMA bounce timed out");
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dev_info(inst->dev, "Reader DMA bounce timed out");
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spin_lock(&inst->smi_inst->transaction_lock);
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dmaengine_terminate_sync(inst->smi_inst->dma_chan);
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spin_unlock(&inst->smi_inst->transaction_lock);
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}
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else
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{
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@ -612,7 +645,7 @@ int writer_thread_stream_function(void *pv)
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while(!kthread_should_stop())
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{
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// check if the streaming state is on, if not, sleep and check again
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if (inst->state != smi_stream_tx)
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if (inst->state != smi_stream_tx_channel)
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{
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msleep(5);
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continue;
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@ -654,15 +687,25 @@ int writer_thread_stream_function(void *pv)
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if (count != DMA_BOUNCE_BUFFER_SIZE)
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{
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// error
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dev_err(inst->dev, "stream_smi_user_dma error");
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continue;
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}
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// Wait for current chunk to complete
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if (down_timeout(&bounce->callback_sem, msecs_to_jiffies(1000)))
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{
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dev_err(inst->dev, "DMA bounce timed out");
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dev_err(inst->dev, "Writer DMA bounce timed out");
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spin_lock(&inst->smi_inst->transaction_lock);
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dmaengine_terminate_sync(inst->smi_inst->dma_chan);
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spin_unlock(&inst->smi_inst->transaction_lock);
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}
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}
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else
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{
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// if doen't have enough data, invoke poll
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inst->writeable = true;
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wake_up_interruptible(&inst->poll_event);
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}
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}
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dev_info(inst->dev, "Left writer thread");
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@ -69,7 +69,7 @@ typedef enum
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smi_stream_idle = 0,
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smi_stream_rx_channel_0 = 1,
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smi_stream_rx_channel_1 = 2,
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smi_stream_tx = 3,
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smi_stream_tx_channel = 3,
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} smi_stream_state_en;
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#ifdef __KERNEL__
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