diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c
index 0c27b5c..e0d6618 100644
--- a/driver/smi_stream_dev.c
+++ b/driver/smi_stream_dev.c
@@ -254,7 +254,6 @@ static int set_state(smi_stream_state_en new_state)
         return 0;
     }
     
-
     // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer
     if(new_state != smi_stream_idle)
     {
@@ -262,7 +261,23 @@ static int set_state(smi_stream_state_en new_state)
 
         if (new_state == smi_stream_tx_channel)
         {
-            ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            // remove all data inside the tx_fifo
+            if (mutex_lock_interruptible(&inst->write_lock))
+            {
+                return -EINTR;
+            }
+            kfifo_reset(&inst->tx_fifo);
+            mutex_unlock(&inst->write_lock);
+            
+            inst->writeable = true;
+            wake_up_interruptible(&inst->poll_event);
+            
+            //ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            mb();
+            spin_unlock(&inst->state_lock);
+            
+            // return the success
+            return ret;
         }
         else
         {
@@ -734,7 +749,7 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe
         struct dma_async_tx_descriptor *desc = NULL;
         struct bcm2835_smi_instance *smi_inst = inst->smi_inst;
         spin_lock(&smi_inst->transaction_lock);
-        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst);
+        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst);
     
         if(desc)
         {
@@ -886,15 +901,6 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr
         return -EAGAIN;
     }
     
-    if (kfifo_is_full(&inst->tx_fifo))
-    {
-        if(wait_event_interruptible(inst->poll_event,  !kfifo_is_full(&inst->tx_fifo)))
-        {
-            mutex_unlock(&inst->write_lock);
-            return -EAGAIN;
-        }	
-    }
-    
     // check how many bytes are available in the tx fifo
     num_bytes_available = kfifo_avail(&inst->tx_fifo);
     num_to_push = num_bytes_available > count ? count : num_bytes_available;
diff --git a/examples/cpp_api/async_sample_process/main.cpp b/examples/cpp_api/async_sample_process/main.cpp
index c28ef78..5f81380 100644
--- a/examples/cpp_api/async_sample_process/main.cpp
+++ b/examples/cpp_api/async_sample_process/main.cpp
@@ -152,12 +152,12 @@ void dataConsumerThread(appContext_st* app)
 // Rx Callback (async)
 void receivedSamples(CaribouLiteRadio* radio, const std::complex<float>* samples, CaribouLiteMeta* sync, size_t num_samples)
 {
-    for (int i = 0; i < 6; i ++)
+    /*for (int i = 0; i < 6; i ++)
     {
         std::cout << "[" << samples[i].real() << ", " << samples[i].imag() << "]";
     }
     std::cout << std::endl;
-
+    */
     // push the received samples in the fifo
     app.rx_fifo->put(samples, num_samples);
 }
diff --git a/firmware/.gitignore.bak b/firmware/.gitignore.bak
index 5c28f56..e69de29 100644
--- a/firmware/.gitignore.bak
+++ b/firmware/.gitignore.bak
@@ -1,56 +0,0 @@
-# Prerequisites
-*.d
-
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Linker output
-*.ilk
-*.map
-*.exp
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-*.su
-*.idb
-*.pdb
-
-# Kernel Module Compile Results
-*.mod*
-*.cmd
-.tmp_versions/
-modules.order
-Module.symvers
-Mkfile.old
-dkms.conf
-
-# build directories
-installations
-build
diff --git a/firmware/Makefile b/firmware/Makefile
index e9dbb96..0386c53 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -4,9 +4,9 @@ pcf_file = ./io.pcf
 
 top.bin:
 	yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v
+
 	#nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc
-	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 5 --timing-allow-fail
-	#nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui
+	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail
 	icepack $(filename).asc $(filename).bin
 
 build: top.bin
diff --git a/firmware/complex_fifo.v b/firmware/complex_fifo.v
index d978d53..d4abb29 100644
--- a/firmware/complex_fifo.v
+++ b/firmware/complex_fifo.v
@@ -15,9 +15,6 @@ module complex_fifo #(
 
 	output reg 						full_o,
 	output reg 						empty_o,
-
-	input wire						debug_pull,
-	input wire						debug_push,
 );
 
 	reg [ADDR_WIDTH-1:0]	wr_addr;
@@ -29,7 +26,15 @@ module complex_fifo #(
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr;
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr_r;
 
-	reg [2*DATA_WIDTH-1:0] 	debug_buffer;
+	// Initial conditions
+	initial begin
+		wr_addr <= 0;
+		wr_addr_gray <= 0;
+		full_o <= 0;
+		rd_addr <= 0;
+		rd_addr_gray <= 0;
+		empty_o <= 1'b1;
+	end
 
 	function [ADDR_WIDTH-1:0] gray_conv;
 		input [ADDR_WIDTH-1:0] in;
@@ -38,7 +43,7 @@ module complex_fifo #(
 		end
 	endfunction
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			wr_addr <= 0;
 			wr_addr_gray <= 0;
@@ -54,7 +59,7 @@ module complex_fifo #(
 		rd_addr_gray_wr_r <= rd_addr_gray_wr;
 	end
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			full_o <= 0;
 		end else if (wr_en_i) begin
@@ -64,11 +69,10 @@ module complex_fifo #(
 		end
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			rd_addr <= 0;
 			rd_addr_gray <= 0;
-			debug_buffer <= 32'hABCDEF01;
 		end else if (rd_en_i) begin
 			rd_addr <= rd_addr + 1'b1;
 			rd_addr_gray <= gray_conv(rd_addr + 1'b1);
@@ -81,7 +85,7 @@ module complex_fifo #(
 		wr_addr_gray_rd_r <= wr_addr_gray_rd;
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			empty_o <= 1'b1;
 		end else if (rd_en_i) begin
@@ -93,24 +97,15 @@ module complex_fifo #(
 
 	always @(posedge rd_clk_i) begin
 		if (rd_en_i) begin
-			if (debug_pull) begin
-				rd_data_o <= debug_buffer;
-			end else begin
-				rd_data_o[15:0] <= mem_q[rd_addr][15:0];
-				rd_data_o[31:16] <= mem_i[rd_addr][15:0];
-			end
+			rd_data_o[15:0] <= mem_q[rd_addr][15:0];
+			rd_data_o[31:16] <= mem_i[rd_addr][15:0];
 		end
 	end
 
 	always @(posedge wr_clk_i) begin
 		if (wr_en_i) begin
-			if (debug_push) begin
-				mem_q[wr_addr] <= debug_buffer[15:0];
-				mem_i[wr_addr] <= debug_buffer[31:16];
-			end else begin
-				mem_q[wr_addr] <= wr_data_i[15:0];
-				mem_i[wr_addr] <= wr_data_i[31:16];
-			end
+			mem_q[wr_addr] <= wr_data_i[15:0];
+			mem_i[wr_addr] <= wr_data_i[31:16];
 		end
 	end
 
diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h
index d76d608..e610570 100644
--- a/firmware/h-files/cariboulite_fpga_firmware.h
+++ b/firmware/h-files/cariboulite_fpga_firmware.h
@@ -17,15 +17,15 @@ extern "C" {
 
 /*
  * Time tagging of the module through the 'struct tm' structure 
- *     Date: 2024-03-15
- *     Time: 03:49:31
+ *     Date: 2024-04-09
+ *     Time: 13:13:50
  */
 struct tm cariboulite_firmware_date_time = {
-   .tm_sec = 31,
-   .tm_min = 49,
-   .tm_hour = 3,
-   .tm_mday = 15,
-   .tm_mon = 2,   /* +1    */
+   .tm_sec = 50,
+   .tm_min = 13,
+   .tm_hour = 13,
+   .tm_mday = 9,
+   .tm_mon = 3,   /* +1    */
    .tm_year = 124,  /* +1900 */
 };
 
@@ -38,382 +38,382 @@ uint8_t cariboulite_firmware[] = {
 	0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 
 	0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 
+	0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x03, 0x40, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x40, 
 	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 
+	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x20, 0x01, 
+	0xE0, 0x01, 0x50, 0x00, 0x00, 0x80, 0x08, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x04, 0x00, 0x00, 0x20, 0x00, 
-	0x00, 0x02, 0x50, 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x0B, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 
-	0x50, 0x40, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xD0, 0x10, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x0F, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 
+	0xF0, 0x40, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 
-	0x30, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x03, 0x83, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
+	0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x05, 0x03, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x03, 0x40, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x07, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0xF0, 0x00, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x0F, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x08, 0x00, 0x05, 0x00, 0x00, 
+	0x01, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x04, 0x00, 0x78, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x01, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x50, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x36, 0x00, 0x18, 0x00, 0x00, 0x04, 0x00, 0xF0, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x70, 
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+	0x00, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x07, 0xEA, 0x81, 0x20, 0x82, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x51, 0x01, 0x00, 0x00, 0x00, 0x04, 0x07, 0xA0, 0x99, 0x00, 0x80, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x08, 
+	0xCF, 0x38, 0x00, 0x0A, 0x80, 0x02, 0x5B, 0x60, 0x00, 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x08, 
+	0x00, 0x00, 0x00, 0x00, 0xB0, 0x03, 0x94, 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x02, 0x05, 0x00, 
+	0xE0, 0x00, 0x00, 0x0C, 0xAA, 0x52, 0x80, 0x80, 0x50, 0x01, 0xD8, 0x40, 0x28, 0x15, 0x46, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3B, 0x0C, 0xE0, 0x0A, 0x00, 0x20, 0x00, 0x1A, 0x10, 0x60, 
+	0x40, 0x00, 0x02, 0x00, 0x07, 0x00, 0xF3, 0x90, 0x80, 0x08, 0x00, 0x00, 0x01, 0xE0, 0xA0, 0x29, 
+	0xA0, 0x02, 0x00, 0xC7, 0xB4, 0x18, 0x00, 0x94, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 
+	0x83, 0x30, 0x04, 0x00, 0x01, 0x40, 0x01, 0x00, 0x02, 0x18, 0x00, 0x00, 0x30, 0x00, 0x18, 0x00, 
+	0x00, 0x00, 0x00, 0xC0, 0x01, 0xE3, 0xA0, 0x00, 0x04, 0x01, 0x00, 0x00, 0x1E, 0x00, 0x00, 0xC0, 
+	0x00, 0x02, 0x95, 0x90, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0C, 0xE0, 0x0C, 0x00, 0x16, 0x6C, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 
+	0xC0, 0x08, 0x00, 0x90, 0x20, 0xF0, 0x0D, 0x00, 0x0C, 0x08, 0x00, 0x78, 0x28, 0x06, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x3F, 0x30, 0x00, 0x40, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
+	0x00, 0x80, 0x10, 0x60, 0x3C, 0x00, 0x04, 0x00, 0xE0, 0x17, 0xFE, 0x40, 0x00, 0x02, 0x00, 0x1C, 
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x10, 0x26, 0x80, 0x00, 0x00, 0x00, 0x02, 0x0C, 0xE0, 0x01, 
+	0x00, 0x00, 0x68, 0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x10, 0x01, 0x08, 0x00, 0x03, 0xC8, 0x10, 
+	0xA0, 0x04, 0x00, 0x1A, 0xE4, 0x20, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x34, 0x40, 0x0A, 
+	0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3B, 0x30, 0x00, 0x1A, 0x00, 0x00, 0x34, 0x00, 0x82, 0x9C, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xEA, 0x81, 0x00, 0x00, 0x01, 0x40, 0x0E, 0x00, 0x04, 0x04, 
+	0x10, 0x07, 0x00, 0x80, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x25, 0x14, 0x00, 0x0D, 0x80, 0x02, 
+	0x4C, 0xE0, 0x00, 0x00, 0x00, 0x04, 0x01, 0x02, 0x60, 0x40, 0x00, 0x00, 0x02, 0x00, 0x09, 0x0C, 
+	0x28, 0x00, 0x00, 0x02, 0x00, 0x24, 0x00, 0x04, 0x00, 0x00, 0x22, 0x00, 0x0F, 0x00, 0x00, 0x02, 
+	0x0C, 0x00, 0x0B, 0x00, 0x08, 0x80, 0x00, 0x90, 0x00, 0x33, 0x30, 0x00, 0x00, 0x00, 0x02, 0x40, 
+	0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x83, 0x9C, 0x00, 0x00, 0x01, 0x60, 0x14, 
+	0x00, 0x06, 0x00, 0x00, 0x00, 0x1B, 0x18, 0x00, 0x0A, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x08, 0x01, 0x7A, 0x0C, 0xE0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x08, 
+	0x0F, 0x00, 0x52, 0x90, 0x80, 0x10, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0xA3, 
+	0x80, 0x00, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0xA0, 0x03, 0x30, 0x00, 0x00, 
+	0x00, 0x00, 0x1C, 0x00, 0x83, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x86, 0x05, 0x00, 0x04, 
+	0x0B, 0x40, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x53, 0x9C, 0x80, 0x00, 0x0A, 0x4C, 0x07, 0x80, 0x00, 
+	0x25, 0x00, 0x00, 0x28, 0x1A, 0x7A, 0x0C, 0xE0, 0x40, 0x40, 0x00, 0x00, 0x00, 0x02, 0x61, 0x00, 
+	0x80, 0x00, 0x00, 0x09, 0x00, 0x0B, 0xE0, 0x40, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x04, 0x20, 0x01, 
+	0x08, 0x09, 0x0B, 0x00, 0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x29, 0x00, 0x04, 0x50, 0x00, 0x03, 
+	0x30, 0x00, 0x08, 0x03, 0x40, 0x00, 0xA0, 0x01, 0x8C, 0x00, 0x00, 0x30, 0x00, 0x01, 0xD5, 0x06, 
+	0x05, 0x00, 0x40, 0x01, 0x42, 0x20, 0xED, 0x11, 0x03, 0x20, 0x59, 0x1C, 0x00, 0x00, 0x42, 0x08, 
+	0x00, 0x20, 0x05, 0xA4, 0x04, 0x00, 0x09, 0x80, 0x02, 0x0C, 0xE0, 0x04, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x1E, 0x03, 0xE0, 0x40, 0x00, 0x00, 0x00, 0x01, 0x4B, 
+	0xE2, 0x00, 0x31, 0x02, 0x50, 0x01, 0x00, 0x00, 0x40, 0x40, 0x02, 0x40, 0xA5, 0x29, 0x00, 0x00, 
+	0x98, 0x00, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x05, 0x82, 0x05, 0x20, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x24, 0x00, 0x04, 0x00, 0x1E, 0x00, 
+	0x00, 0x00, 0x01, 0xE2, 0x86, 0x00, 0x08, 0x00, 0x00, 0x03, 0x9B, 0x02, 0x4C, 0xE2, 0x00, 0x20, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0xA0, 0x40, 0x00, 0x00, 
+	0x00, 0x20, 0x0E, 0x00, 0x00, 0x40, 0x00, 0x00, 0x05, 0x2C, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 
+	0x02, 0x00, 0x18, 0x00, 0xF0, 0x2B, 0x30, 0x14, 0x00, 0x00, 0x02, 0xC0, 0x00, 0x00, 0x00, 0x04, 
+	0x00, 0x08, 0x00, 0x00, 0x07, 0x02, 0x95, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x84, 
+	0x08, 0x01, 0x18, 0x00, 0x00, 0x00, 0x02, 0x80, 0x00, 0x08, 0x02, 0xA1, 0x95, 0x0A, 0x02, 0x4C, 
+	0xC0, 0x0A, 0x00, 0x00, 0x00, 0x0E, 0x33, 0x20, 0x00, 0x00, 0x02, 0x00, 0x00, 0x0A, 0xD0, 0x00, 
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xF5, 0xB4, 0x00, 0x00, 0x00, 
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x3A, 0xF0, 0xA0, 0x33, 0x30, 0x84, 0x00, 0x00, 0x00, 0x00, 0xF3, 
+	0x30, 0x80, 0x30, 0x00, 0x10, 0x00, 0x50, 0x00, 0x6A, 0x81, 0x20, 0xC0, 0x14, 0x00, 0x00, 0x00, 
+	0x24, 0x83, 0x01, 0x0F, 0x9E, 0x80, 0x00, 0x00, 0x00, 0x07, 0x80, 0x83, 0x3A, 0x0D, 0x00, 0x08, 
+	0x0B, 0x06, 0x15, 0x40, 0x04, 0x00, 0x00, 0x2E, 0x00, 0xE7, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 
+	0x08, 0x70, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x8B, 0x00, 
+	0x00, 0x02, 0x00, 0x40, 0x0B, 0xCC, 0x00, 0x10, 0x00, 0x91, 0xA3, 0x42, 0xA8, 0x01, 0xC0, 0xE0, 
+	0x06, 0x14, 0xCD, 0xB2, 0x08, 0x00, 0x62, 0x00, 0x00, 0x80, 0xF9, 0xEA, 0x94, 0x80, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x93, 0x38, 
+	0x00, 0x10, 0x09, 0x80, 0x06, 0x04, 0x1A, 0x00, 0x02, 0x86, 0x02, 0x01, 0x66, 0x00, 0x00, 0x04, 
+	0x00, 0x00, 0x01, 0x08, 0xDC, 0x2A, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 
+	0x08, 0x0D, 0x00, 0x00, 0x00, 0x14, 0x00, 0x0A, 0xCC, 0x09, 0x40, 0x00, 0x98, 0x00, 0x00, 0x01, 
+	0x82, 0x00, 0x00, 0x00, 0x1C, 0xC9, 0x90, 0x90, 0x00, 0x00, 0x00, 0x00, 0x01, 0xE3, 0x02, 0x05, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x03, 0x9C, 0x00, 0x00, 0x04, 0x18, 0x00, 
+	0x04, 0x83, 0x38, 0x00, 0x00, 0x08, 0x01, 0x52, 0x45, 0x00, 0x40, 0x00, 0x80, 0x01, 0xC0, 0x00, 
+	0x01, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x0B, 0xA0, 0x40, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x91, 0x03, 0x00, 0x00, 0xAB, 0x40, 0x00, 0x20, 0xCC, 0x01, 0x00, 0x00, 0x10, 
+	0x90, 0xF8, 0x50, 0x00, 0x00, 0x14, 0x40, 0x3E, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
+	0x05, 0xAF, 0x88, 0x80, 0x04, 0x95, 0x40, 0x00, 0x81, 0x04, 0x00, 0x00, 0x50, 0x00, 0x18, 0x00, 
+	0x00, 0x00, 0x00, 0x0E, 0x83, 0x3A, 0x00, 0x08, 0x03, 0x80, 0x18, 0x59, 0x80, 0x40, 0x08, 0x06, 
+	0x28, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x80, 0x80, 0x0A, 0xB8, 0x80, 0x00, 0x20, 0x80, 
+	0x00, 0x10, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xE9, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0xCC, 0x00, 
+	0x01, 0x00, 0x08, 0x00, 0xA5, 0x98, 0x01, 0x08, 0x03, 0x64, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x30, 0x03, 0x82, 0x05, 0x00, 0x00, 0x09, 0x40, 0x01, 0xC1, 0x04, 0x00, 0x00, 0x00, 
+	0x0E, 0x80, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x83, 0x38, 0x00, 0x10, 0x00, 0x00, 0x5A, 0x83, 0x00, 
+	0x10, 0x00, 0x06, 0x66, 0xEA, 0xF0, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0xA0, 0x40, 
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 
+	0x20, 0xCC, 0x00, 0x80, 0x80, 0x00, 0x0D, 0x34, 0xF0, 0x00, 0x00, 0x00, 0x26, 0x5F, 0x0F, 0xA2, 
+	0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x04, 0xF0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x01, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x38, 0x01, 0x00, 0x01, 0x00, 
+	0x98, 0x30, 0xC0, 0x0C, 0xA0, 0x34, 0x00, 0x0F, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 
+	0x03, 0x8F, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x00, 0x08, 0x03, 0x00, 0x00, 
+	0x00, 0x80, 0x20, 0x0E, 0xCC, 0x00, 0x80, 0x00, 0x08, 0x01, 0xA0, 0xF0, 0x00, 0x40, 0x02, 0x60, 
+	0x01, 0xE3, 0x30, 0x10, 0x00, 0x00, 0x11, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -421,26 +421,26 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xF0, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -448,19 +448,10 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -468,696 +459,705 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAD, 0xB0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x41, 0xDB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x14, 0x03, 0xC4, 0x00, 0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x16, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0x02, 0x1A, 0x05, 0x48, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 
-	0x81, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
-	0x2D, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x10, 0x00, 0x40, 0x80, 0x00, 0x01, 0x00, 0x01, 0x81, 0x78, 0x50, 0x90, 0x04, 0x00, 0x04, 0x64, 
-	0x0A, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0xA1, 0x04, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x80, 0x2C, 0xF0, 0x00, 0x00, 0x00, 0x04, 0x1E, 0xAD, 0x14, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x04, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x8F, 0x00, 0x4F, 0x00, 0x00, 
-	0x00, 0x00, 0x63, 0xEB, 0x52, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x04, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x7D, 0xC0, 0x00, 0x00, 0x02, 0x40, 0x15, 0xF0, 0x00, 0x80, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF6, 
-	0xBC, 0x00, 0x00, 0x00, 0x20, 0x01, 0x4D, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x0E, 0x10, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0xEC, 0x00, 0x00, 0x00, 0x20, 0x02, 0x0C, 
-	0x84, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x40, 0x08, 0x60, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x01, 0x5B, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x06, 0x01, 0x81, 0x20, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0xA0, 0x01, 0x68, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0xF3, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x40, 0x08, 0x60, 0x40, 
-	0x00, 0x00, 0x00, 0x00, 0x18, 0x70, 0x16, 0x80, 0x00, 0x00, 0x06, 0x00, 0x01, 0x3C, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x85, 0xB4, 
-	0x85, 0x00, 0xC0, 0x02, 0xC3, 0x2C, 0x92, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x3C, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x18, 0x5A, 0x21, 0x10, 0x0C, 0x00, 0x26, 0x65, 0x48, 
-	0x84, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x8D, 0xED, 0x21, 0x00, 0x00, 0x01, 0x40, 0x17, 0xB4, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 
-	0x00, 0x3C, 0xC0, 0x08, 0x40, 0x00, 0x00, 0x02, 0x80, 0x00, 0x01, 0xD6, 0x08, 0x70, 0x0A, 0x00, 
-	0x20, 0x01, 0xEA, 0x21, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x20, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x60, 0x00, 0x04, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x08, 0x00, 0x00, 0x03, 0x00, 0xB0, 0x00, 0x20, 0x04, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 
-	0x20, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x80, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x38, 0x20, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x05, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
-	0x00, 0x06, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x26, 0xF5, 0x22, 0x00, 0x00, 
-	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x48, 0x10, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x90, 0x4F, 0x10, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x27, 0xEA, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x69, 0xE8, 
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-	0x02, 0x2C, 0xEE, 0xB0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 0x03, 0x00, 0x80, 0x00, 0x04, 
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-	0x40, 0x00, 0x00, 0x80, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x18, 0x00, 0x00, 0x00, 0x05, 0xE7, 0x80, 0x00, 0x00, 
-	0x1F, 0xB5, 0x95, 0x00, 0x04, 0x01, 0x08, 0x01, 0xD6, 0xA0, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x30, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x10, 0x00, 0x00, 0x00, 0x03, 0x82, 0x00, 0x30, 0x00, 0x22, 0xD5, 0x58, 0x08, 0x00, 0x00, 0x00, 
-	0x00, 0x1B, 0x41, 0x40, 0x00, 0x50, 0x00, 0x04, 0x00, 0xF0, 0x80, 0x0C, 0x00, 0x00, 0x00, 0x00, 
-	0x20, 0x00, 0x68, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00, 0x08, 0x00, 0x01, 0xC2, 
-	0x40, 0x03, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x20, 0xF0, 0x06, 0x00, 0x00, 0x00, 
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-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0xA4, 0x34, 0x00, 0x20, 0x00, 0x40, 0x0A, 0x00, 
-	0x81, 0x00, 0x00, 0x41, 0x0B, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x08, 0x07, 0x5E, 0x34, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x80, 0x10, 0x0C, 0x37, 0x20, 
+	0x03, 0xC0, 0x00, 0x00, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0xAF, 0x60, 0x80, 0x00, 0x00, 0x00, 0x00, 0x05, 0xE7, 0x90, 0x00, 0x80, 
+	0x80, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x29, 0x02, 0x00, 0x00, 0x00, 0x00, 
+	0x98, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x61, 0xCB, 
+	0x00, 0x0A, 0x00, 0x00, 0x03, 0xC2, 0x3A, 0x00, 0x00, 0x00, 0x40, 0x09, 0x00, 0x00, 0x10, 0x00, 
+	0x00, 0x00, 0x00, 0x44, 0x27, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x01, 0xC7, 
+	0x80, 0x03, 0x80, 0x82, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x12, 0xC0, 0x3C, 0x00, 0x30, 
+	0x01, 0x68, 0x0D, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 
+	0x01, 0x80, 0x00, 0x00, 0x50, 0xE8, 0x07, 0x80, 0x03, 0x44, 0x00, 0x00, 0x80, 0x00, 0x80, 0x0C, 
 	0x00, 0x00, 0x11, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -1165,373 +1165,373 @@ uint8_t cariboulite_firmware[] = {
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@@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8D, 0x0D, 0x01, 0x06, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8B, 0x30, 0x01, 0x06, 0x00, 
 };
 
 #ifdef __cplusplus
diff --git a/firmware/io.pcf b/firmware/io.pcf
index 93059c1..f7107e8 100644
--- a/firmware/io.pcf
+++ b/firmware/io.pcf
@@ -37,14 +37,14 @@ set_io i_glob_clock             A29
 set_io i_rst_b                  A43
 
 # PMOD
-set_io io_pmod[0]               B24
-set_io io_pmod[1]               A31
-set_io io_pmod[2]               B23
-set_io io_pmod[3]               B21
-set_io io_pmod[4]               A25
-set_io io_pmod[5]               A26
-set_io io_pmod[6]               A27
-set_io io_pmod[7]               B20
+set_io io_pmod_out[0]           B24
+set_io io_pmod_out[1]           A31
+set_io io_pmod_out[2]           B23
+set_io io_pmod_out[3]           B21
+set_io io_pmod_in[0]            A25
+set_io io_pmod_in[1]            A26
+set_io io_pmod_in[2]            A27
+set_io io_pmod_in[3]            B20
 
 # MIXER
 set_io o_mixer_fm               A32
diff --git a/firmware/output.txt b/firmware/output.txt
new file mode 100644
index 0000000..e69de29
diff --git a/firmware/p1k b/firmware/p1k
new file mode 100644
index 0000000..e69de29
diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v
index 8428534..b7d0052 100644
--- a/firmware/smi_ctrl.v
+++ b/firmware/smi_ctrl.v
@@ -27,14 +27,13 @@ module smi_ctrl
     input [7:0]         i_smi_data_in,
     output              o_smi_read_req,
     output              o_smi_write_req,
-    input               i_smi_test,
     output              o_channel,
     output              o_dir,
 
     // TX CONDITIONAL
     output reg          o_cond_tx,
-    // Errors
-    output reg          o_address_error);
+    
+    output wire [1:0]   o_state);
 
     // ---------------------------------
 
@@ -60,7 +59,6 @@ module smi_ctrl
     always @(posedge i_sys_clk or negedge i_rst_b)
     begin
         if (i_rst_b == 1'b0) begin
-            o_address_error <= 1'b0;
             r_dir <= 1'b0;
             r_channel <= 1'b0;
         end else begin
@@ -78,7 +76,7 @@ module smi_ctrl
                             o_data_out[0] <= i_rx_fifo_empty;
                             o_data_out[1] <= i_tx_fifo_full;
                             o_data_out[2] <= r_channel;
-                            o_data_out[3] <= i_smi_test;
+                            o_data_out[3] <= 1'b0;
                             o_data_out[4] <= r_dir;
                             o_data_out[7:4] <= 3'b000;
                         end
@@ -118,7 +116,7 @@ module smi_ctrl
 
     wire soe_and_reset;
     assign soe_and_reset = i_rst_b & i_smi_soe_se;
-    assign o_smi_read_req = (!i_rx_fifo_empty) || i_smi_test;
+    assign o_smi_read_req = (!i_rx_fifo_empty);
     assign o_rx_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_rx_fifo_empty;
 
     always @(negedge soe_and_reset)
@@ -129,25 +127,15 @@ module smi_ctrl
             r_fifo_pulled_data <= 32'h00000000;
         end else begin
             // trigger the fifo pulling on the second byte
-            w_fifo_pull_trigger <= (int_cnt_rx == 5'd8) && !i_smi_test;
+            w_fifo_pull_trigger <= (int_cnt_rx == 5'd8);
 
-            if ( i_smi_test ) begin
-                if (r_smi_test_count == 0) begin
-                    r_smi_test_count <= 8'h56;
-                end else begin
-                    o_smi_data_out <= r_smi_test_count;
-                    r_smi_test_count <= {((r_smi_test_count[2] ^ r_smi_test_count[3]) & 1'b1), r_smi_test_count[7:1]};
-                end
-            end else begin
-                int_cnt_rx <= int_cnt_rx + 8;
-                o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
-                
-                // update the internal register as soon as we reach the fourth byte
-                if (int_cnt_rx == 5'd24) begin
-                    r_fifo_pulled_data <= i_rx_fifo_pulled_data;
-                end
+            int_cnt_rx <= int_cnt_rx + 8;
+            o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
+            
+            // update the internal register as soon as we reach the fourth byte
+            if (int_cnt_rx == 5'd24) begin
+                r_fifo_pulled_data <= i_rx_fifo_pulled_data;
             end
-
         end
     end
 
@@ -185,6 +173,7 @@ module smi_ctrl
     assign o_tx_fifo_push = !r_fifo_push_1 && r_fifo_push && !i_tx_fifo_full;
     assign swe_and_reset = i_rst_b & i_smi_swe_srw;
     assign o_tx_fifo_clock = i_sys_clk;
+    assign o_state = tx_reg_state;
 
     always @(negedge swe_and_reset)
     begin
diff --git a/firmware/top.asc b/firmware/top.asc
index e5d1897..f5d712b 100644
--- a/firmware/top.asc
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+.sym 787 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 790 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 798 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 816 iq_tx_n_OUTPUT_CLK
+.sym 826 lvds_clock
+.sym 829 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 830 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.sym 851 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.sym 861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
+.sym 862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 863 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 864 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 865 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 866 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 867 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 895 rx_fifo.mem_q.0.0_WDATA
+.sym 899 rx_fifo.mem_q.0.0_WDATA_2
+.sym 916 w_rx_09_fifo_data[0]
+.sym 917 $PACKER_VCC_NET
 .sym 940 lvds_clock
-.sym 944 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 959 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 974 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 975 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
-.sym 976 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
-.sym 978 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
-.sym 979 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
-.sym 980 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 981 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
-.sym 1007 $PACKER_VCC_NET
-.sym 1042 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 1051 $PACKER_VCC_NET
-.sym 1054 w_lvds_rx_09_d0
-.sym 1055 $PACKER_VCC_NET
+.sym 941 $PACKER_VCC_NET
+.sym 944 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 961 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 975 w_rx_24_fifo_data[1]
+.sym 976 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
+.sym 977 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
+.sym 978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
+.sym 979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
+.sym 980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
+.sym 981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
+.sym 982 i_sck$SB_IO_IN
+.sym 994 rx_fifo.wr_addr[5]
+.sym 1000 rx_fifo.wr_addr[7]
+.sym 1053 rx_fifo.wr_addr[8]
+.sym 1054 lvds_clock
 .sym 1061 $PACKER_GND_NET
 .sym 1062 $PACKER_GND_NET
 .sym 1066 $PACKER_VCC_NET
 .sym 1067 $PACKER_VCC_NET
 .sym 1069 $PACKER_VCC_NET
-.sym 1071 io_pmod[0]$SB_IO_IN
+.sym 1071 iq_tx_n_OUTPUT_CLK
+.sym 1073 iq_tx_n_OUTPUT_CLK
+.sym 1074 $PACKER_VCC_NET
 .sym 1076 $PACKER_GND_NET
-.sym 1077 $PACKER_GND_NET
-.sym 1078 $PACKER_VCC_NET
-.sym 1084 io_pmod[0]$SB_IO_IN
-.sym 1085 $PACKER_VCC_NET
-.sym 1086 $PACKER_VCC_NET
-.sym 1088 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 1090 rx_fifo.rd_addr_gray_wr[4]
-.sym 1091 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
-.sym 1092 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 1093 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
-.sym 1094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
-.sym 1095 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 1116 $PACKER_VCC_NET
-.sym 1121 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 1141 io_pmod[0]$SB_IO_IN
-.sym 1142 $PACKER_VCC_NET
+.sym 1080 $PACKER_VCC_NET
+.sym 1084 $PACKER_GND_NET
+.sym 1088 w_rx_09_fifo_data[1]
+.sym 1090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
+.sym 1091 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 1092 $PACKER_GND_NET
+.sym 1096 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 1120 $PACKER_VCC_NET
+.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 1132 $PACKER_VCC_NET
+.sym 1138 w_lvds_rx_24_d0
+.sym 1145 iq_tx_n_OUTPUT_CLK
+.sym 1165 $PACKER_VCC_NET
+.sym 1168 w_lvds_rx_24_d0
+.sym 1169 $PACKER_VCC_NET
 .sym 1173 w_lvds_rx_09_d0
 .sym 1174 w_lvds_rx_09_d1
 .sym 1183 $PACKER_VCC_NET
 .sym 1184 lvds_clock_$glb_clk
-.sym 1199 $PACKER_VCC_NET
-.sym 1202 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 1203 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 1204 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
-.sym 1206 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
-.sym 1208 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 1209 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
-.sym 1222 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 1235 $PACKER_GND_NET
-.sym 1241 i_rst_b$SB_IO_IN
-.sym 1242 w_lvds_rx_09_d0
-.sym 1244 w_lvds_rx_09_d1
-.sym 1256 $PACKER_VCC_NET
-.sym 1271 w_lvds_rx_09_d1
-.sym 1279 $PACKER_GND_NET
+.sym 1191 $PACKER_VCC_NET
+.sym 1203 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 1204 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 1205 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
+.sym 1208 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
+.sym 1209 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
+.sym 1228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 1230 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 1247 i_rst_b$SB_IO_IN
+.sym 1262 w_lvds_rx_09_d1
+.sym 1269 w_lvds_rx_09_d0
+.sym 1272 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 1282 lvds_clock
 .sym 1287 lvds_clock
 .sym 1297 $PACKER_VCC_NET
 .sym 1305 $PACKER_VCC_NET
-.sym 1316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
-.sym 1317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.sym 1318 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.sym 1319 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
-.sym 1320 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 1321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 1322 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
-.sym 1323 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
-.sym 1324 lvds_clock
-.sym 1336 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 1348 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 1360 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 1362 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
+.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 1317 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 1318 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 1320 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
+.sym 1321 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 1322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
+.sym 1323 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 1379 $PACKER_VCC_NET
 .sym 1401 w_lvds_rx_24_d0
 .sym 1402 w_lvds_rx_24_d1
 .sym 1411 $PACKER_VCC_NET
 .sym 1412 lvds_clock_$glb_clk
-.sym 1416 $PACKER_VCC_NET
-.sym 1430 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
-.sym 1433 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
-.sym 1434 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 1435 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 1436 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 1462 w_lvds_rx_24_d0
-.sym 1463 w_lvds_rx_09_d0
-.sym 1464 $PACKER_VCC_NET
+.sym 1427 $PACKER_VCC_NET
+.sym 1431 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
+.sym 1432 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
+.sym 1433 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
+.sym 1434 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
+.sym 1435 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
+.sym 1436 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 1437 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
 .sym 1474 w_lvds_rx_24_d1
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-.sym 1546 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2]
-.sym 1547 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
-.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 1549 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
-.sym 1550 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
-.sym 1551 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
-.sym 1690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 1894 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 1945 w_rx_09_fifo_data[5]
-.sym 1951 w_rx_24_fifo_data[15]
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-.sym 2064 rx_fifo.mem_q.0.3_WDATA_2
-.sym 2065 w_rx_09_fifo_data[10]
-.sym 2066 rx_fifo.mem_q.0.3_WDATA_3
-.sym 2067 w_rx_09_fifo_data[12]
-.sym 2068 w_rx_09_fifo_data[18]
-.sym 2069 w_rx_09_fifo_data[14]
-.sym 2070 w_rx_09_fifo_data[16]
-.sym 2081 $PACKER_VCC_NET
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-.sym 2123 rx_fifo.mem_q.0.2_WDATA_1
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-.sym 2125 rx_fifo.mem_i.0.0_WDATA_1
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-.sym 2156 w_rx_09_fifo_data[13]
-.sym 2159 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 2169 w_rx_09_fifo_data[15]
-.sym 2172 w_rx_24_fifo_data[15]
-.sym 2180 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 2186 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 2187 w_rx_24_fifo_data[15]
-.sym 2188 w_rx_09_fifo_data[15]
-.sym 2193 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 2194 w_rx_09_fifo_data[13]
-.sym 2210 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 2212 w_rx_09_fifo_data[11]
-.sym 2227 w_rx_09_fifo_data[15]
-.sym 2229 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 1510 lvds_clock
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+.sym 1545 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 1547 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
+.sym 1549 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 1551 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 1569 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 1579 $PACKER_VCC_NET
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+.sym 1706 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 1879 rx_fifo.mem_i.0.1_WDATA_3
+.sym 1880 w_rx_09_fifo_data[20]
+.sym 1881 w_rx_09_fifo_data[24]
+.sym 1883 rx_fifo.mem_i.0.1_WDATA_2
+.sym 1885 w_rx_09_fifo_data[22]
+.sym 1886 w_rx_09_fifo_data[26]
+.sym 1907 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 2063 w_rx_24_fifo_data[22]
+.sym 2064 rx_fifo.mem_i.0.2_WDATA_3
+.sym 2065 rx_fifo.mem_q.0.3_WDATA_2
+.sym 2066 w_rx_24_fifo_data[24]
+.sym 2067 w_rx_24_fifo_data[14]
+.sym 2068 w_rx_24_fifo_data[16]
+.sym 2069 w_rx_24_fifo_data[20]
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-.sym 3129 $nextpnr_ICESTORM_LC_6$O
+.sym 3043 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
+.sym 3044 rx_fifo.wr_addr[7]
+.sym 3045 rx_fifo.mem_q.0.0_WDATA_3
+.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 3047 rx_fifo.wr_addr[6]
+.sym 3048 rx_fifo.wr_addr[1]
+.sym 3049 rx_fifo.wr_addr[2]
+.sym 3050 rx_fifo.mem_q.0.0_WDATA_1
+.sym 3051 rx_fifo.wr_addr[5]
+.sym 3057 $PACKER_VCC_NET
+.sym 3061 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 3068 w_rx_09_fifo_data[1]
+.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 3074 rx_fifo.wr_addr[9]
+.sym 3076 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3078 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 3086 $PACKER_VCC_NET
+.sym 3101 rx_fifo.wr_addr[8]
+.sym 3106 rx_fifo.wr_addr[3]
+.sym 3113 rx_fifo.wr_addr[7]
+.sym 3116 rx_fifo.wr_addr[6]
+.sym 3117 rx_fifo.wr_addr[1]
+.sym 3124 rx_fifo.wr_addr[4]
+.sym 3126 rx_fifo.wr_addr[2]
+.sym 3128 rx_fifo.wr_addr[5]
+.sym 3129 $nextpnr_ICESTORM_LC_0$O
 .sym 3132 rx_fifo.wr_addr[1]
-.sym 3135 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
+.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
 .sym 3137 rx_fifo.wr_addr[2]
 .sym 3139 rx_fifo.wr_addr[1]
-.sym 3141 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
-.sym 3143 rx_fifo.wr_addr[3]
-.sym 3145 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
-.sym 3147 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 3144 rx_fifo.wr_addr[3]
+.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
+.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
 .sym 3149 rx_fifo.wr_addr[4]
-.sym 3151 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
-.sym 3153 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
-.sym 3155 rx_fifo.wr_addr[5]
-.sym 3157 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
-.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 3161 rx_fifo.wr_addr[6]
-.sym 3163 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
-.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 3167 rx_fifo.wr_addr[7]
-.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 3156 rx_fifo.wr_addr[5]
+.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 3159 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 3162 rx_fifo.wr_addr[6]
+.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 3165 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 3168 rx_fifo.wr_addr[7]
+.sym 3169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 3171 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
 .sym 3173 rx_fifo.wr_addr[8]
-.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 3179 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 3184 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 3186 rx_fifo.wr_addr_gray_rd[9]
-.sym 3194 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 3202 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 3203 rx_fifo.wr_addr[8]
-.sym 3207 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 3209 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 3212 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 3213 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3215 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3221 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
-.sym 3226 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 3232 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 3233 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
-.sym 3234 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 3236 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 3237 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 3238 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 3239 rx_fifo.rd_addr_gray_wr[6]
-.sym 3240 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 3241 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
-.sym 3242 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.sym 3243 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
-.sym 3244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.sym 3245 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 3246 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 3247 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 3250 rx_fifo.wr_addr[9]
-.sym 3260 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 3263 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
-.sym 3267 rx_fifo.wr_addr[9]
-.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 3271 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.sym 3272 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
-.sym 3278 rx_fifo.rd_addr_gray_wr[6]
-.sym 3283 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
-.sym 3285 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 3286 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
-.sym 3289 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 3290 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
-.sym 3292 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 3297 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 3298 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 3301 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 3307 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.sym 3308 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 3310 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
+.sym 3175 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 3179 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
+.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 3181 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 3182 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 3183 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
+.sym 3184 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
+.sym 3185 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
+.sym 3191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 3192 rx_fifo.wr_addr[3]
+.sym 3193 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 3194 rx_fifo.wr_addr[6]
+.sym 3195 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 3196 rx_fifo.wr_addr[5]
+.sym 3198 rx_fifo.wr_addr[7]
+.sym 3200 rx_fifo.wr_addr[0]
+.sym 3201 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 3208 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 3210 w_rx_09_fifo_data[0]
+.sym 3211 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 3212 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 3214 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 3224 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
+.sym 3227 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
+.sym 3232 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 3233 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
+.sym 3234 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 3235 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 3242 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
+.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 3247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 3248 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
+.sym 3250 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 3254 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
+.sym 3255 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
+.sym 3257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 3258 rx_fifo.wr_addr[9]
+.sym 3260 w_lvds_rx_24_d0
+.sym 3261 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
+.sym 3266 rx_fifo.wr_addr[9]
+.sym 3268 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
+.sym 3273 w_lvds_rx_24_d0
+.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
+.sym 3284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
+.sym 3285 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
+.sym 3286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
+.sym 3289 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 3291 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 3292 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 3295 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
+.sym 3296 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 3298 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 3301 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 3302 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 3303 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 3310 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
+.sym 3311 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
 .sym 3312 lvds_clock_$glb_clk
-.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
-.sym 3315 rx_fifo.full_o_SB_LUT4_I0_O[0]
-.sym 3316 rx_fifo.wr_addr[9]
-.sym 3317 rx_fifo.wr_addr_gray[7]
-.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
-.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O[2]
-.sym 3320 rx_fifo.wr_addr[8]
-.sym 3321 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
-.sym 3331 rx_fifo.wr_addr_gray_rd[9]
-.sym 3332 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 3333 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 3335 rx_fifo.rd_addr_gray_wr[6]
-.sym 3339 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3340 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 3343 rx_fifo.wr_addr[8]
-.sym 3346 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 3348 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 3350 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
-.sym 3359 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3361 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 3367 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3368 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 3369 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 3370 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
-.sym 3372 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3375 rx_fifo.rd_addr_gray[4]
-.sym 3377 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
-.sym 3378 rx_fifo.rd_addr_gray_wr[2]
-.sym 3379 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
-.sym 3380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 3381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 3383 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 3385 rx_fifo.rd_addr_gray_wr[4]
-.sym 3393 i_rst_b$SB_IO_IN
-.sym 3397 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 3402 rx_fifo.rd_addr_gray_wr[4]
-.sym 3406 i_rst_b$SB_IO_IN
-.sym 3408 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
-.sym 3413 rx_fifo.rd_addr_gray[4]
-.sym 3420 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 3421 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 3424 rx_fifo.rd_addr_gray_wr[2]
-.sym 3430 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
-.sym 3432 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
-.sym 3436 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 3437 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 3438 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 3439 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 3442 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 3443 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3445 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 3314 rx_fifo.full_o_SB_LUT4_I0_O[1]
+.sym 3315 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 3317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 3318 rx_fifo.rd_addr_gray_wr[0]
+.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 3320 rx_fifo.full_o_SB_LUT4_I0_O[2]
+.sym 3321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
+.sym 3326 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 3327 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 3330 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 3332 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 3337 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 3339 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3341 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 3342 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 3343 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 3345 rx_fifo.rd_addr_gray[5]
+.sym 3349 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 3375 w_lvds_rx_09_d0
+.sym 3382 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
+.sym 3384 i_rst_b$SB_IO_IN
+.sym 3392 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 3396 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 3401 w_lvds_rx_09_d0
+.sym 3412 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 3414 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 3419 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
+.sym 3420 i_rst_b$SB_IO_IN
+.sym 3446 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
 .sym 3447 lvds_clock_$glb_clk
-.sym 3449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
-.sym 3450 rx_fifo.full_o_SB_LUT4_I0_O[1]
-.sym 3451 rx_fifo.mem_q.0.0_WDATA_3
-.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
-.sym 3453 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 3454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
-.sym 3455 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 3456 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 3457 rx_fifo.rd_addr_gray[4]
-.sym 3462 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 3466 rx_fifo.rd_addr_gray_wr[2]
-.sym 3468 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 3471 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 3472 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 3476 w_rx_09_fifo_data[0]
-.sym 3477 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3480 w_rx_09_fifo_data[1]
-.sym 3481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3485 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 3486 w_lvds_rx_09_d1
-.sym 3493 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3502 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
-.sym 3503 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 3504 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
-.sym 3505 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 3506 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3507 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
-.sym 3509 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 3510 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 3512 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
-.sym 3513 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3514 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 3517 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 3519 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3522 w_lvds_rx_09_d0
-.sym 3523 w_lvds_rx_09_d1
-.sym 3524 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3526 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3533 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
-.sym 3536 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 3541 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 3542 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3547 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3548 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3549 w_lvds_rx_09_d0
-.sym 3550 w_lvds_rx_09_d1
-.sym 3559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3560 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 3562 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 3565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
-.sym 3566 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
-.sym 3567 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
-.sym 3568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
-.sym 3571 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3574 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 3577 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 3578 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 3579 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 3580 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 3581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
+.sym 3449 rx_fifo.rd_addr_gray_wr[9]
+.sym 3451 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 3453 rx_fifo.rd_addr_gray_wr[5]
+.sym 3454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 3464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 3465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 3466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 3468 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.sym 3469 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 3472 rx_fifo.rd_addr_gray[0]
+.sym 3475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 3477 w_rx_fifo_full
+.sym 3481 w_rx_24_fifo_data[0]
+.sym 3484 rx_fifo.rd_addr[9]
+.sym 3488 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 3496 w_lvds_rx_09_d0
+.sym 3505 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 3509 $PACKER_VCC_NET
+.sym 3511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 3516 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
+.sym 3517 $PACKER_VCC_NET
+.sym 3519 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 3520 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 3522 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3523 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3526 w_lvds_rx_09_d0
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+.sym 3531 w_lvds_rx_09_d1
+.sym 3533 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 3534 $nextpnr_ICESTORM_LC_1$O
+.sym 3537 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 3540 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3541 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3542 $PACKER_VCC_NET
+.sym 3543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
+.sym 3544 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 3547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3548 $PACKER_VCC_NET
+.sym 3549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 3550 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3553 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 3556 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 3577 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 3578 w_lvds_rx_09_d1
+.sym 3579 w_lvds_rx_09_d0
+.sym 3580 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 3581 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
 .sym 3582 lvds_clock_$glb_clk
 .sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 3584 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 3585 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
-.sym 3587 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
-.sym 3588 w_rx_fifo_full
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-.sym 3592 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 3597 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
-.sym 3599 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 3600 w_rx_data[0]
-.sym 3601 w_rx_24_fifo_data[0]
-.sym 3608 $PACKER_VCC_NET
-.sym 3609 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 3611 $PACKER_VCC_NET
-.sym 3614 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 3617 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3619 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 3637 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3638 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 3639 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
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-.sym 3673 rx_fifo.rd_addr_gray_wr_r[4]
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-.sym 3677 w_lvds_rx_24_d1
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-.sym 3690 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 3694 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.sym 3696 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3697 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
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-.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
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-.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
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+.sym 3586 w_rx_24_fifo_data[0]
+.sym 3590 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 3601 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
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+.sym 3638 w_lvds_rx_24_d1
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+.sym 3652 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 3658 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 3659 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3667 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 3668 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 3670 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 3671 w_lvds_rx_24_d1
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+.sym 3682 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 3683 w_lvds_rx_24_d1
+.sym 3684 w_lvds_rx_24_d0
+.sym 3695 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 3697 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
+.sym 3700 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
+.sym 3701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3702 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 3706 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
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+.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
 .sym 3709 w_lvds_rx_24_d0
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-.sym 3713 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3716 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 3713 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 3714 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 3715 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
+.sym 3716 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
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 .sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 3720 w_rx_09_fifo_data[0]
-.sym 3721 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
-.sym 3722 w_rx_09_fifo_data[1]
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-.sym 3782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.sym 3784 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
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-.sym 3792 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3801 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 3807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 3808 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 3823 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 3824 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 3825 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
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-.sym 3830 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
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+.sym 3735 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
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 .sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr
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 .sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr
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+.sym 4804 rx_fifo.wr_addr[2]
+.sym 4805 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 4811 w_rx_24_fifo_data[8]
+.sym 4816 w_rx_09_fifo_data[8]
+.sym 4818 w_rx_24_fifo_data[17]
+.sym 4819 w_rx_09_fifo_data[6]
+.sym 4821 w_rx_24_fifo_data[29]
+.sym 4822 w_rx_24_fifo_data[19]
+.sym 4823 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4825 w_rx_09_fifo_data[19]
+.sym 4828 w_rx_fifo_pulled_data[5]
+.sym 4832 w_rx_09_fifo_data[29]
+.sym 4833 w_rx_09_fifo_data[17]
+.sym 4836 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4840 w_rx_24_fifo_data[6]
+.sym 4845 w_rx_fifo_pulled_data[5]
+.sym 4862 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4863 w_rx_24_fifo_data[8]
+.sym 4864 w_rx_09_fifo_data[8]
+.sym 4869 w_rx_24_fifo_data[29]
+.sym 4870 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4871 w_rx_09_fifo_data[29]
+.sym 4874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4876 w_rx_24_fifo_data[17]
+.sym 4877 w_rx_09_fifo_data[17]
+.sym 4881 w_rx_09_fifo_data[6]
+.sym 4882 w_rx_24_fifo_data[6]
+.sym 4883 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4886 w_rx_09_fifo_data[19]
+.sym 4887 w_rx_24_fifo_data[19]
+.sym 4888 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4890 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
+.sym 4891 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 4892 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 4894 w_rx_fifo_pulled_data[5]
+.sym 4898 w_rx_fifo_pulled_data[7]
+.sym 4906 smi_ctrl_ins.r_fifo_pulled_data[2]
+.sym 4907 rx_fifo.mem_i.0.0_WDATA_1
+.sym 4908 rx_fifo.wr_addr[6]
+.sym 4910 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 4912 rx_fifo.wr_addr[7]
+.sym 4915 rx_fifo.mem_i.0.3_WDATA_1
+.sym 4920 rx_fifo.mem_q.0.2_WDATA_3
+.sym 4924 rx_fifo.wr_addr[5]
+.sym 4928 w_rx_24_fifo_data[28]
+.sym 4936 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 4937 w_rx_24_fifo_data[19]
+.sym 4939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4941 w_rx_24_fifo_data[17]
+.sym 4943 w_rx_24_fifo_data[21]
+.sym 4944 w_rx_24_fifo_data[15]
+.sym 4947 w_rx_24_fifo_data[6]
+.sym 4948 w_rx_24_fifo_data[31]
+.sym 4949 w_rx_24_fifo_data[29]
+.sym 4952 w_rx_24_fifo_data[28]
+.sym 4961 w_rx_09_fifo_data[31]
+.sym 4964 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4969 w_rx_24_fifo_data[6]
+.sym 4970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4973 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4975 w_rx_24_fifo_data[19]
+.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4981 w_rx_24_fifo_data[28]
+.sym 4985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4987 w_rx_24_fifo_data[17]
+.sym 4991 w_rx_24_fifo_data[21]
+.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 4997 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 4999 w_rx_24_fifo_data[31]
+.sym 5000 w_rx_09_fifo_data[31]
+.sym 5003 w_rx_24_fifo_data[29]
+.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5011 w_rx_24_fifo_data[15]
+.sym 5013 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
 .sym 5014 lvds_clock_$glb_clk
 .sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
-.sym 5017 w_rx_fifo_pulled_data[20]
-.sym 5021 w_rx_fifo_pulled_data[22]
-.sym 5028 rx_fifo.mem_q.0.1_WDATA_1
-.sym 5031 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 5032 w_rx_24_fifo_data[26]
-.sym 5033 rx_fifo.wr_addr[7]
-.sym 5034 w_rx_24_fifo_data[22]
-.sym 5036 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5038 rx_fifo.mem_q.0.1_WDATA
-.sym 5040 rx_fifo.wr_addr[8]
-.sym 5041 rx_fifo.wr_addr_gray[3]
-.sym 5043 i_rst_b$SB_IO_IN
-.sym 5047 rx_fifo.wr_addr[3]
-.sym 5051 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5057 w_rx_24_fifo_data[29]
-.sym 5058 w_rx_09_fifo_data[29]
-.sym 5060 w_rx_09_fifo_data[3]
-.sym 5061 w_rx_24_fifo_data[3]
-.sym 5062 w_rx_24_fifo_data[31]
-.sym 5063 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5064 w_rx_24_fifo_data[30]
-.sym 5065 w_rx_09_fifo_data[31]
-.sym 5067 w_rx_09_fifo_data[2]
-.sym 5069 w_rx_09_fifo_data[30]
-.sym 5071 w_rx_24_fifo_data[2]
-.sym 5082 w_rx_fifo_pulled_data[20]
-.sym 5084 rx_fifo.mem_i.0.1_WDATA
-.sym 5090 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5092 w_rx_24_fifo_data[3]
-.sym 5093 w_rx_09_fifo_data[3]
-.sym 5102 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5103 w_rx_09_fifo_data[30]
-.sym 5105 w_rx_24_fifo_data[30]
-.sym 5109 w_rx_fifo_pulled_data[20]
-.sym 5116 rx_fifo.mem_i.0.1_WDATA
-.sym 5120 w_rx_09_fifo_data[31]
-.sym 5122 w_rx_24_fifo_data[31]
-.sym 5123 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5126 w_rx_24_fifo_data[29]
-.sym 5127 w_rx_09_fifo_data[29]
-.sym 5128 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5132 w_rx_24_fifo_data[2]
-.sym 5134 w_rx_09_fifo_data[2]
-.sym 5135 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 5017 w_rx_fifo_pulled_data[8]
+.sym 5021 w_rx_fifo_pulled_data[10]
+.sym 5030 rx_fifo.mem_i.0.3_WDATA
+.sym 5036 rx_fifo.mem_q.0.1_WDATA_1
+.sym 5040 smi_ctrl_ins.r_fifo_pulled_data[10]
+.sym 5041 $PACKER_VCC_NET
+.sym 5046 rx_fifo.wr_addr[6]
+.sym 5048 rx_fifo.wr_addr[1]
+.sym 5050 rx_fifo.wr_addr[2]
+.sym 5051 i_rst_b$SB_IO_IN
+.sym 5066 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5067 w_rx_24_fifo_data[30]
+.sym 5068 w_rx_fifo_pulled_data[18]
+.sym 5069 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5070 w_rx_09_fifo_data[28]
+.sym 5074 w_rx_fifo_pulled_data[9]
+.sym 5075 i_rst_b$SB_IO_IN
+.sym 5078 w_rx_fifo_pulled_data[10]
+.sym 5081 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 5082 w_rx_09_fifo_data[30]
+.sym 5086 w_rx_fifo_pulled_data[11]
+.sym 5088 w_rx_24_fifo_data[28]
+.sym 5096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 5097 i_rst_b$SB_IO_IN
+.sym 5099 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5102 w_rx_fifo_pulled_data[11]
+.sym 5109 w_rx_09_fifo_data[28]
+.sym 5110 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5111 w_rx_24_fifo_data[28]
+.sym 5115 w_rx_fifo_pulled_data[10]
+.sym 5121 w_rx_fifo_pulled_data[18]
+.sym 5127 w_rx_fifo_pulled_data[9]
+.sym 5132 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5134 w_rx_24_fifo_data[30]
+.sym 5135 w_rx_09_fifo_data[30]
 .sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
 .sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk
 .sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 5140 w_rx_fifo_pulled_data[21]
-.sym 5144 w_rx_fifo_pulled_data[23]
-.sym 5149 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
-.sym 5151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 5152 $PACKER_VCC_NET
-.sym 5153 rx_fifo.mem_i.0.3_WDATA
-.sym 5157 rx_fifo.mem_i.0.3_WDATA_2
-.sym 5158 rx_fifo.wr_addr[6]
-.sym 5159 rx_fifo.wr_addr[7]
-.sym 5161 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 5162 rx_fifo.wr_addr[9]
-.sym 5163 rx_fifo.wr_addr[2]
-.sym 5174 rx_fifo.mem_q.0.0_WDATA_2
-.sym 5182 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 5183 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5184 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5189 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5190 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 5191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5192 w_rx_24_fifo_data[1]
-.sym 5194 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5199 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
-.sym 5202 w_rx_09_fifo_data[1]
-.sym 5203 i_rst_b$SB_IO_IN
-.sym 5214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5222 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5226 w_rx_24_fifo_data[1]
-.sym 5227 w_rx_09_fifo_data[1]
-.sym 5228 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5232 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5234 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5240 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 5244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5250 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
-.sym 5255 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5257 i_rst_b$SB_IO_IN
-.sym 5259 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 5260 lvds_clock_$glb_clk
+.sym 5140 w_rx_fifo_pulled_data[9]
+.sym 5144 w_rx_fifo_pulled_data[11]
+.sym 5147 rx_fifo.wr_addr[8]
+.sym 5154 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 5156 w_rx_fifo_pulled_data[18]
+.sym 5159 rx_fifo.mem_i.0.3_WDATA_3
+.sym 5162 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5163 rx_fifo.rd_addr[9]
+.sym 5165 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5166 w_rx_fifo_pulled_data[1]
+.sym 5168 rx_fifo.wr_addr[7]
+.sym 5169 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5171 smi_ctrl_ins.r_fifo_pulled_data[0]
+.sym 5173 rx_fifo.rd_addr[0]
+.sym 5174 w_rx_fifo_pulled_data[3]
+.sym 5182 w_rx_fifo_pulled_data[1]
+.sym 5198 w_rx_fifo_pulled_data[3]
+.sym 5201 w_rx_fifo_pulled_data[2]
+.sym 5205 w_rx_fifo_pulled_data[0]
+.sym 5215 w_rx_fifo_pulled_data[0]
+.sym 5227 w_rx_fifo_pulled_data[3]
+.sym 5246 w_rx_fifo_pulled_data[1]
+.sym 5252 w_rx_fifo_pulled_data[2]
+.sym 5259 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
+.sym 5260 smi_ctrl_ins.soe_and_reset_$glb_clk
 .sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 5263 w_rx_fifo_pulled_data[0]
 .sym 5267 w_rx_fifo_pulled_data[2]
-.sym 5274 rx_fifo.wr_addr[5]
-.sym 5275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 5276 rx_fifo.wr_addr[1]
-.sym 5278 rx_fifo.wr_addr[3]
-.sym 5279 rx_fifo.rd_addr[3]
-.sym 5282 rx_fifo.wr_addr[8]
-.sym 5284 rx_fifo.wr_addr[2]
-.sym 5285 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 5286 rx_fifo.mem_q.0.0_WDATA
-.sym 5287 rx_fifo.mem_q.0.0_WDATA_1
-.sym 5288 rx_fifo.rd_addr[0]
-.sym 5292 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5293 rx_fifo.wr_addr[1]
-.sym 5296 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 5303 rx_fifo.wr_addr[5]
-.sym 5307 rx_fifo.wr_addr[2]
-.sym 5312 rx_fifo.wr_addr[3]
-.sym 5316 rx_fifo.wr_addr[1]
-.sym 5319 rx_fifo.wr_addr[0]
-.sym 5320 rx_fifo.wr_addr[4]
-.sym 5321 rx_fifo.wr_addr[6]
-.sym 5327 rx_fifo.wr_addr[0]
-.sym 5332 rx_fifo.wr_addr[7]
-.sym 5335 $nextpnr_ICESTORM_LC_4$O
-.sym 5337 rx_fifo.wr_addr[0]
-.sym 5341 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5343 rx_fifo.wr_addr[1]
-.sym 5345 rx_fifo.wr_addr[0]
-.sym 5347 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5350 rx_fifo.wr_addr[2]
-.sym 5351 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5355 rx_fifo.wr_addr[3]
-.sym 5357 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5359 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5361 rx_fifo.wr_addr[4]
-.sym 5363 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5365 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5367 rx_fifo.wr_addr[5]
-.sym 5369 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5371 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 5374 rx_fifo.wr_addr[6]
-.sym 5375 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 5377 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 5379 rx_fifo.wr_addr[7]
-.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 5275 rx_fifo.mem_q.0.2_WDATA
+.sym 5276 smi_ctrl_ins.r_fifo_pulled_data[1]
+.sym 5277 rx_fifo.mem_q.0.2_WDATA_1
+.sym 5278 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5280 rx_fifo.rd_addr[2]
+.sym 5281 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 5282 rx_fifo.rd_addr[1]
+.sym 5283 $PACKER_VCC_NET
+.sym 5286 rx_fifo.wr_addr[1]
+.sym 5287 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5288 rx_fifo.wr_addr[2]
+.sym 5289 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 5292 rx_fifo.wr_addr[5]
+.sym 5293 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5294 rx_fifo.rd_addr[1]
+.sym 5295 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 5296 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 5303 w_rx_24_fifo_data[0]
+.sym 5308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5310 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 5312 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5313 rx_fifo.wr_addr[0]
+.sym 5314 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5316 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 5320 w_rx_24_fifo_data[1]
+.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 5323 rx_fifo.wr_addr[1]
+.sym 5328 w_rx_09_fifo_data[1]
+.sym 5329 w_rx_09_fifo_data[0]
+.sym 5332 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5337 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 5342 w_rx_09_fifo_data[0]
+.sym 5343 w_rx_24_fifo_data[0]
+.sym 5345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5349 rx_fifo.wr_addr[0]
+.sym 5350 rx_fifo.wr_addr[1]
+.sym 5355 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 5366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5372 w_rx_09_fifo_data[1]
+.sym 5373 w_rx_24_fifo_data[1]
+.sym 5374 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5382 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5383 lvds_clock_$glb_clk
+.sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 5386 w_rx_fifo_pulled_data[1]
 .sym 5390 w_rx_fifo_pulled_data[3]
-.sym 5399 rx_fifo.wr_addr[0]
-.sym 5401 rx_fifo.rd_addr[9]
-.sym 5402 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5403 rx_fifo.wr_addr[8]
-.sym 5405 rx_fifo.wr_addr[4]
-.sym 5407 rx_fifo.wr_addr[6]
-.sym 5410 rx_fifo.wr_addr[8]
-.sym 5411 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 5412 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 5413 rx_fifo.mem_q.0.0_WDATA_3
-.sym 5414 w_rx_24_fifo_data[0]
-.sym 5415 rx_fifo.wr_addr[7]
-.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5418 rx_fifo.wr_addr[9]
-.sym 5419 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5421 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 5427 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 5428 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 5430 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5431 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5432 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5433 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 5435 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5436 rx_fifo.wr_addr[9]
-.sym 5437 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5440 rx_fifo.wr_addr[8]
-.sym 5441 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 5454 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 5458 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 5460 rx_fifo.wr_addr[8]
-.sym 5462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 5467 rx_fifo.wr_addr[9]
-.sym 5468 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 5471 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5473 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5474 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 5478 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 5479 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5483 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5485 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 5491 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5496 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 5497 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 5501 rx_fifo.wr_addr[9]
-.sym 5506 r_counter_$glb_clk
-.sym 5522 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 5524 $PACKER_VCC_NET
-.sym 5526 io_pmod[0]$SB_IO_IN
-.sym 5533 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5536 rx_fifo.wr_addr[8]
-.sym 5537 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 5539 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 5540 w_rx_fifo_full
+.sym 5394 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5397 rx_fifo.rd_addr_gray[5]
+.sym 5399 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 5405 rx_fifo.wr_addr[6]
+.sym 5407 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 5411 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5413 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5414 rx_fifo.wr_addr[1]
+.sym 5415 rx_fifo.mem_q.0.0_WDATA_2
+.sym 5416 rx_fifo.wr_addr[2]
+.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5418 $PACKER_VCC_NET
+.sym 5420 rx_fifo.wr_addr[5]
+.sym 5428 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
+.sym 5429 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
+.sym 5430 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 5433 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
+.sym 5434 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 5435 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 5436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 5437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 5438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
+.sym 5439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5441 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 5443 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
+.sym 5447 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5449 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
+.sym 5451 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5452 i_rst_b$SB_IO_IN
+.sym 5453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 5454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 5455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
+.sym 5457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 5459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 5461 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 5462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 5465 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
+.sym 5467 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 5468 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 5472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5479 i_rst_b$SB_IO_IN
+.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5483 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
+.sym 5484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
+.sym 5485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5486 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 5490 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 5492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 5495 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
+.sym 5496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
+.sym 5497 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
+.sym 5498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
+.sym 5501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 5502 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5503 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 5504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 5518 w_rx_09_fifo_data[0]
+.sym 5524 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5526 rx_fifo.rd_addr[9]
+.sym 5527 w_rx_fifo_full
+.sym 5528 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 5530 rx_fifo.rd_addr[2]
+.sym 5536 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 5538 i_rst_b$SB_IO_IN
+.sym 5542 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 5549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
 .sym 5550 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5551 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 5554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
-.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
-.sym 5557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 5560 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 5561 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5562 rx_fifo.wr_addr[2]
-.sym 5563 rx_fifo.wr_addr[1]
-.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5567 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 5568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5571 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 5572 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 5582 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5583 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
-.sym 5584 rx_fifo.wr_addr[2]
-.sym 5585 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 5588 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 5590 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 5551 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5553 rx_fifo.rd_addr_gray[0]
+.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
+.sym 5557 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5559 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 5561 rx_fifo.rd_addr_gray_wr[0]
+.sym 5562 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 5563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 5565 rx_fifo.full_o_SB_LUT4_I0_O[1]
+.sym 5568 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 5569 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 5571 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5573 w_rx_fifo_full
+.sym 5574 rx_fifo.wr_addr[1]
+.sym 5575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 5576 rx_fifo.wr_addr[2]
+.sym 5577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 5579 rx_fifo.full_o_SB_LUT4_I0_O[2]
+.sym 5582 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5583 w_rx_fifo_full
+.sym 5584 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 5588 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 5594 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.sym 5595 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
 .sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5602 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
-.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 5607 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5608 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 5609 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5612 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5613 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 5614 rx_fifo.wr_addr[1]
-.sym 5615 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5624 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 5627 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 5628 rx_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 5597 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 5600 rx_fifo.rd_addr_gray_wr[0]
+.sym 5606 rx_fifo.rd_addr_gray[0]
+.sym 5613 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 5614 rx_fifo.full_o_SB_LUT4_I0_O[2]
+.sym 5615 rx_fifo.full_o_SB_LUT4_I0_O[1]
+.sym 5618 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 5620 rx_fifo.wr_addr[1]
+.sym 5621 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 5624 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
+.sym 5627 rx_fifo.wr_addr[2]
 .sym 5629 lvds_clock_$glb_clk
-.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 5645 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 5647 $PACKER_VCC_NET
-.sym 5649 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 5652 $PACKER_VCC_NET
-.sym 5653 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 5658 rx_fifo.wr_addr_gray[7]
-.sym 5673 rx_fifo.full_o_SB_LUT4_I0_O[0]
-.sym 5675 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 5676 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
-.sym 5677 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5679 w_rx_data[0]
-.sym 5680 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
-.sym 5681 rx_fifo.full_o_SB_LUT4_I0_O[1]
-.sym 5682 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5683 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
-.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
-.sym 5685 rx_fifo.full_o_SB_LUT4_I0_O[2]
-.sym 5686 w_rx_24_fifo_data[0]
-.sym 5687 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5689 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5690 w_rx_09_fifo_data[0]
-.sym 5691 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
-.sym 5692 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5694 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5699 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
-.sym 5700 w_rx_fifo_full
-.sym 5702 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
-.sym 5703 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5705 rx_fifo.full_o_SB_LUT4_I0_O[1]
-.sym 5706 rx_fifo.full_o_SB_LUT4_I0_O[0]
-.sym 5707 rx_fifo.full_o_SB_LUT4_I0_O[2]
-.sym 5711 w_rx_fifo_full
-.sym 5712 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 5714 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 5717 w_rx_09_fifo_data[0]
-.sym 5719 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5720 w_rx_24_fifo_data[0]
-.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
-.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
-.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
-.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
-.sym 5732 w_rx_data[0]
-.sym 5735 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 5737 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 5743 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 5744 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 5747 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
-.sym 5748 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
-.sym 5751 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
-.sym 5752 r_counter_$glb_clk
-.sym 5753 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 5766 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
-.sym 5769 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
-.sym 5776 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5780 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 5783 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 5784 w_lvds_rx_09_d1
-.sym 5789 w_lvds_rx_09_d0
-.sym 5795 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
-.sym 5798 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
-.sym 5800 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
-.sym 5802 w_lvds_rx_09_d1
-.sym 5803 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
-.sym 5806 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
-.sym 5810 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 5811 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 5812 w_lvds_rx_09_d0
-.sym 5816 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
-.sym 5817 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 5818 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
-.sym 5819 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 5821 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 5824 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
-.sym 5826 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 5828 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 5829 w_lvds_rx_09_d0
-.sym 5830 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 5831 w_lvds_rx_09_d1
-.sym 5834 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 5836 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 5846 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
-.sym 5847 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
-.sym 5848 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
-.sym 5849 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 5852 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
-.sym 5853 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
-.sym 5854 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
-.sym 5855 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
-.sym 5871 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 5872 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 5645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 5646 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5647 rx_fifo.wr_addr[9]
+.sym 5649 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 5651 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 5657 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 5661 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 5680 rx_fifo.rd_addr_gray_wr[9]
+.sym 5683 rx_fifo.rd_addr_gray[5]
+.sym 5684 rx_fifo.rd_addr_gray_wr[5]
+.sym 5690 rx_fifo.rd_addr[9]
+.sym 5707 rx_fifo.rd_addr[9]
+.sym 5720 rx_fifo.rd_addr_gray_wr[9]
+.sym 5731 rx_fifo.rd_addr_gray[5]
+.sym 5735 rx_fifo.rd_addr_gray_wr[5]
+.sym 5752 lvds_clock_$glb_clk
+.sym 5782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 5797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 5801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 5802 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 5809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5810 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 5812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 5813 w_lvds_rx_24_d1
+.sym 5834 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 5837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 5840 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 5841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 5842 w_lvds_rx_24_d1
+.sym 5865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 5867 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5874 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
 .sym 5875 lvds_clock_$glb_clk
-.sym 5876 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 5886 rx_fifo.wr_addr[1]
-.sym 5889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 5892 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 5906 w_rx_fifo_full
-.sym 5910 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 5923 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 5927 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 5929 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 5941 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
-.sym 5944 w_lvds_rx_09_d1
-.sym 5949 w_lvds_rx_09_d0
-.sym 5957 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 5958 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 5959 w_lvds_rx_09_d1
-.sym 5960 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 5966 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
-.sym 5970 w_lvds_rx_09_d0
-.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 5885 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
+.sym 5893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 5920 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
+.sym 5924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 5941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 5942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 5944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 5964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 5966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 5969 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 5972 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5988 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 5989 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 5995 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 5997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
 .sym 5998 lvds_clock_$glb_clk
-.sym 6017 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 6043 $PACKER_VCC_NET
-.sym 6045 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 6050 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
-.sym 6051 $PACKER_VCC_NET
-.sym 6052 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
-.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 6059 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
-.sym 6061 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6068 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
-.sym 6070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6071 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
-.sym 6072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
-.sym 6073 $nextpnr_ICESTORM_LC_7$O
-.sym 6076 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
-.sym 6079 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3
-.sym 6080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 6081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
-.sym 6082 $PACKER_VCC_NET
-.sym 6083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
-.sym 6086 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
-.sym 6087 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 6088 $PACKER_VCC_NET
-.sym 6089 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3
-.sym 6094 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
-.sym 6098 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 6104 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 6105 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
-.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
-.sym 6107 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2]
-.sym 6110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
-.sym 6112 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 6113 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
-.sym 6120 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
+.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 6013 o_shdn_tx_lna$SB_IO_OUT
+.sym 6014 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 6017 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 6044 w_lvds_rx_09_d1
+.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 6056 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 6071 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 6104 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 6116 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 6117 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 6118 w_lvds_rx_09_d1
+.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 6120 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
 .sym 6121 lvds_clock_$glb_clk
-.sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 6139 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 6165 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6166 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
-.sym 6168 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 6176 w_rx_fifo_full
-.sym 6177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 6197 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 6200 w_rx_fifo_full
-.sym 6222 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 6223 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 6243 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
-.sym 6244 lvds_clock_$glb_clk
-.sym 6245 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 6257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 6258 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
+.sym 6262 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
 .sym 6294 o_shdn_tx_lna$SB_IO_OUT
-.sym 6314 o_shdn_tx_lna$SB_IO_OUT
-.sym 6381 w_smi_data_output[6]
-.sym 6389 rx_fifo.wr_addr[9]
-.sym 6391 rx_fifo.wr_addr[0]
+.sym 6310 o_shdn_tx_lna$SB_IO_OUT
+.sym 6346 tx_fifo.rd_addr_gray_wr[3]
+.sym 6347 tx_fifo.rd_addr_gray_wr[2]
+.sym 6348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 6349 tx_fifo.rd_addr_gray_wr[5]
+.sym 6350 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 6351 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 6352 tx_fifo.rd_addr_gray_wr[6]
+.sym 6386 rx_fifo.mem_i.0.1_WDATA_3
+.sym 6390 rx_fifo.mem_i.0.1_WDATA_2
 .sym 6392 rx_fifo.wr_addr[4]
-.sym 6395 rx_fifo.wr_addr[6]
-.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6400 rx_fifo.wr_addr[3]
-.sym 6404 rx_fifo.wr_addr[1]
-.sym 6406 $PACKER_VCC_NET
-.sym 6408 rx_fifo.wr_addr[8]
-.sym 6409 rx_fifo.wr_addr[7]
-.sym 6411 rx_fifo.mem_q.0.3_WDATA_2
-.sym 6413 rx_fifo.mem_q.0.3_WDATA_3
+.sym 6395 rx_fifo.wr_addr[1]
+.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6398 rx_fifo.wr_addr[3]
+.sym 6399 rx_fifo.wr_addr[2]
+.sym 6400 rx_fifo.wr_addr[7]
+.sym 6401 rx_fifo.wr_addr[6]
+.sym 6403 rx_fifo.wr_addr[9]
+.sym 6406 rx_fifo.wr_addr[8]
 .sym 6414 rx_fifo.wr_addr[5]
-.sym 6415 rx_fifo.wr_addr[2]
-.sym 6422 smi_ctrl_ins.r_fifo_pulled_data[14]
-.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 6424 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
-.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[9]
-.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[8]
-.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[11]
-.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[15]
+.sym 6415 $PACKER_VCC_NET
+.sym 6416 rx_fifo.wr_addr[0]
+.sym 6422 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
+.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[13]
+.sym 6424 smi_ctrl_ins.r_fifo_pulled_data[26]
+.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[15]
+.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[23]
+.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[21]
+.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[22]
 .sym 6438 rx_fifo.wr_addr[2]
 .sym 6439 rx_fifo.wr_addr[3]
 .sym 6441 rx_fifo.wr_addr[4]
@@ -6151,89 +6023,90 @@
 .sym 6447 rx_fifo.wr_addr[1]
 .sym 6448 rx_fifo.wr_addr[0]
 .sym 6449 lvds_clock_$glb_clk
-.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6452 rx_fifo.mem_q.0.3_WDATA_3
-.sym 6456 rx_fifo.mem_q.0.3_WDATA_2
+.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6452 rx_fifo.mem_i.0.1_WDATA_3
+.sym 6456 rx_fifo.mem_i.0.1_WDATA_2
 .sym 6459 $PACKER_VCC_NET
-.sym 6469 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6472 rx_fifo.wr_addr[3]
-.sym 6478 $PACKER_VCC_NET
-.sym 6493 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6497 rx_fifo.rd_addr[6]
-.sym 6500 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6505 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6506 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6508 w_rx_fifo_pulled_data[9]
-.sym 6511 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6512 rx_fifo.rd_addr[3]
-.sym 6514 w_smi_data_output[1]
-.sym 6515 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 6517 w_rx_fifo_pulled_data[11]
-.sym 6528 rx_fifo.mem_q.0.3_WDATA_1
-.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 6531 rx_fifo.rd_addr[0]
+.sym 6473 rx_fifo.wr_addr[6]
+.sym 6481 rx_fifo.rd_addr[0]
+.sym 6487 rx_fifo.rd_addr[5]
+.sym 6490 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6493 rx_fifo.rd_addr[9]
+.sym 6494 rx_fifo.mem_i.0.1_WDATA
+.sym 6495 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 6497 rx_fifo.wr_addr[3]
+.sym 6498 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 6500 rx_fifo.wr_addr[4]
+.sym 6502 tx_fifo.rd_addr_gray[5]
+.sym 6503 rx_fifo.wr_addr[9]
+.sym 6504 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 6506 rx_fifo.wr_addr[8]
+.sym 6513 w_smi_data_direction
+.sym 6515 w_smi_data_output[6]
+.sym 6516 $PACKER_VCC_NET
+.sym 6517 rx_fifo.wr_addr[0]
+.sym 6518 smi_ctrl_ins.r_fifo_pulled_data[13]
+.sym 6528 rx_fifo.rd_addr[1]
 .sym 6532 $PACKER_VCC_NET
-.sym 6537 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6540 rx_fifo.rd_addr[3]
-.sym 6541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6542 rx_fifo.rd_addr[9]
-.sym 6544 rx_fifo.mem_q.0.3_WDATA
-.sym 6549 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6553 rx_fifo.rd_addr[6]
-.sym 6555 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6557 rx_fifo.rd_addr[8]
-.sym 6558 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6560 tx_fifo.rd_addr_gray[1]
-.sym 6561 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 6562 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
-.sym 6564 tx_fifo.rd_addr_gray[4]
-.sym 6565 tx_fifo.rd_addr_gray[2]
-.sym 6566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 6576 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6577 rx_fifo.rd_addr[3]
-.sym 6579 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6581 rx_fifo.rd_addr[6]
-.sym 6582 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6583 rx_fifo.rd_addr[8]
+.sym 6536 rx_fifo.rd_addr[0]
+.sym 6539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 6540 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6541 rx_fifo.rd_addr[2]
+.sym 6542 rx_fifo.rd_addr[5]
+.sym 6543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6548 rx_fifo.mem_i.0.1_WDATA
+.sym 6549 rx_fifo.rd_addr[9]
+.sym 6557 rx_fifo.mem_i.0.1_WDATA_1
+.sym 6558 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6559 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 6563 tx_fifo.rd_addr_gray[6]
+.sym 6564 tx_fifo.rd_addr_gray[5]
+.sym 6565 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
+.sym 6566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
+.sym 6567 rx_fifo.mem_i.0.2_WDATA_2
+.sym 6576 rx_fifo.rd_addr[2]
+.sym 6577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6580 rx_fifo.rd_addr[5]
+.sym 6581 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6582 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6583 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 6584 rx_fifo.rd_addr[9]
-.sym 6585 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 6585 rx_fifo.rd_addr[1]
 .sym 6586 rx_fifo.rd_addr[0]
 .sym 6587 r_counter_$glb_clk
-.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 6588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 6589 $PACKER_VCC_NET
-.sym 6593 rx_fifo.mem_q.0.3_WDATA
-.sym 6597 rx_fifo.mem_q.0.3_WDATA_1
-.sym 6605 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 6607 smi_ctrl_ins.r_fifo_pulled_data[15]
-.sym 6614 $PACKER_VCC_NET
-.sym 6616 w_rx_fifo_pulled_data[10]
-.sym 6618 smi_ctrl_ins.r_fifo_pulled_data[9]
-.sym 6623 rx_fifo.rd_addr[8]
-.sym 6624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 6625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 6630 rx_fifo.mem_q.0.2_WDATA_2
-.sym 6631 rx_fifo.wr_addr[9]
-.sym 6632 rx_fifo.wr_addr[1]
-.sym 6634 $PACKER_VCC_NET
-.sym 6635 rx_fifo.wr_addr[0]
-.sym 6636 rx_fifo.wr_addr[6]
-.sym 6637 rx_fifo.wr_addr[7]
-.sym 6641 rx_fifo.mem_q.0.2_WDATA_3
+.sym 6593 rx_fifo.mem_i.0.1_WDATA
+.sym 6597 rx_fifo.mem_i.0.1_WDATA_1
+.sym 6603 w_rx_fifo_pulled_data[13]
+.sym 6607 smi_ctrl_ins.int_cnt_rx[3]
+.sym 6608 $PACKER_VCC_NET
+.sym 6610 w_rx_fifo_pulled_data[15]
+.sym 6621 smi_ctrl_ins.r_fifo_pulled_data[7]
+.sym 6636 rx_fifo.wr_addr[1]
+.sym 6641 rx_fifo.wr_addr[2]
 .sym 6642 rx_fifo.wr_addr[5]
-.sym 6643 rx_fifo.wr_addr[2]
-.sym 6645 rx_fifo.wr_addr[4]
-.sym 6648 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6655 rx_fifo.wr_addr[8]
-.sym 6660 rx_fifo.wr_addr[3]
-.sym 6662 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 6663 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 6664 tx_fifo.rd_addr_gray_wr[9]
-.sym 6665 tx_fifo.rd_addr_gray_wr[0]
-.sym 6666 tx_fifo.rd_addr_gray_wr[8]
-.sym 6667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 6668 tx_fifo.rd_addr_gray_wr[1]
-.sym 6669 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 6643 $PACKER_VCC_NET
+.sym 6647 rx_fifo.wr_addr[9]
+.sym 6648 rx_fifo.wr_addr[6]
+.sym 6649 rx_fifo.wr_addr[3]
+.sym 6650 rx_fifo.wr_addr[8]
+.sym 6651 rx_fifo.wr_addr[7]
+.sym 6655 rx_fifo.mem_i.0.2_WDATA_3
+.sym 6657 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6659 rx_fifo.wr_addr[4]
+.sym 6660 rx_fifo.wr_addr[0]
+.sym 6661 rx_fifo.mem_i.0.2_WDATA_2
+.sym 6662 smi_ctrl_ins.r_fifo_pulled_data[24]
+.sym 6663 smi_ctrl_ins.r_fifo_pulled_data[25]
+.sym 6664 smi_ctrl_ins.r_fifo_pulled_data[27]
+.sym 6665 smi_ctrl_ins.r_fifo_pulled_data[12]
+.sym 6666 smi_ctrl_ins.r_fifo_pulled_data[6]
+.sym 6667 smi_ctrl_ins.r_fifo_pulled_data[14]
+.sym 6668 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
+.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
 .sym 6678 rx_fifo.wr_addr[2]
 .sym 6679 rx_fifo.wr_addr[3]
 .sym 6681 rx_fifo.wr_addr[4]
@@ -6245,79 +6118,96 @@
 .sym 6687 rx_fifo.wr_addr[1]
 .sym 6688 rx_fifo.wr_addr[0]
 .sym 6689 lvds_clock_$glb_clk
-.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6692 rx_fifo.mem_q.0.2_WDATA_3
-.sym 6696 rx_fifo.mem_q.0.2_WDATA_2
+.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6692 rx_fifo.mem_i.0.2_WDATA_3
+.sym 6696 rx_fifo.mem_i.0.2_WDATA_2
 .sym 6699 $PACKER_VCC_NET
-.sym 6705 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 6709 w_tx_fifo_pull
-.sym 6710 i_rst_b$SB_IO_IN
-.sym 6719 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 6720 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6727 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 6732 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6734 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6737 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6741 rx_fifo.mem_q.0.2_WDATA_1
-.sym 6744 rx_fifo.rd_addr[3]
-.sym 6747 rx_fifo.mem_q.0.2_WDATA
-.sym 6750 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 6752 $PACKER_VCC_NET
-.sym 6753 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6755 rx_fifo.rd_addr[9]
+.sym 6704 smi_ctrl_ins.int_cnt_rx[4]
+.sym 6705 w_rx_09_fifo_data[26]
+.sym 6706 smi_ctrl_ins.r_fifo_pulled_data[11]
+.sym 6707 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 6708 rx_fifo.mem_q.0.3_WDATA_3
+.sym 6709 smi_ctrl_ins.int_cnt_rx[3]
+.sym 6710 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 6712 rx_fifo.wr_addr[1]
+.sym 6713 rx_fifo.rd_addr[2]
+.sym 6715 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6717 rx_fifo.rd_addr[0]
+.sym 6721 smi_ctrl_ins.int_cnt_rx[4]
+.sym 6725 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6727 rx_fifo.rd_addr[5]
+.sym 6732 rx_fifo.rd_addr[2]
+.sym 6733 rx_fifo.rd_addr[5]
+.sym 6740 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6745 $PACKER_VCC_NET
+.sym 6746 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6747 rx_fifo.mem_i.0.2_WDATA_1
+.sym 6748 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6750 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 6752 rx_fifo.rd_addr[1]
 .sym 6756 rx_fifo.rd_addr[0]
-.sym 6757 rx_fifo.rd_addr[6]
-.sym 6759 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6761 rx_fifo.rd_addr[8]
-.sym 6764 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
-.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[27]
-.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[25]
-.sym 6767 rx_fifo.mem_i.0.2_WDATA_3
-.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[10]
-.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24]
-.sym 6770 smi_ctrl_ins.r_fifo_pulled_data[26]
-.sym 6771 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
-.sym 6780 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6781 rx_fifo.rd_addr[3]
-.sym 6783 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6784 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6785 rx_fifo.rd_addr[6]
-.sym 6786 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6787 rx_fifo.rd_addr[8]
+.sym 6759 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 6760 rx_fifo.rd_addr[9]
+.sym 6761 rx_fifo.mem_i.0.2_WDATA
+.sym 6763 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[8]
+.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[16]
+.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[7]
+.sym 6768 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
+.sym 6769 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
+.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[4]
+.sym 6780 rx_fifo.rd_addr[2]
+.sym 6781 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6783 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6784 rx_fifo.rd_addr[5]
+.sym 6785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6786 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6787 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 6788 rx_fifo.rd_addr[9]
-.sym 6789 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 6789 rx_fifo.rd_addr[1]
 .sym 6790 rx_fifo.rd_addr[0]
 .sym 6791 r_counter_$glb_clk
-.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 6792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 6793 $PACKER_VCC_NET
-.sym 6797 rx_fifo.mem_q.0.2_WDATA
-.sym 6801 rx_fifo.mem_q.0.2_WDATA_1
-.sym 6814 rx_fifo.wr_addr[5]
-.sym 6816 rx_fifo.wr_addr[8]
-.sym 6817 rx_fifo.wr_addr[2]
-.sym 6819 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6821 rx_fifo.rd_addr[9]
-.sym 6823 rx_fifo.rd_addr[6]
-.sym 6824 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 6825 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6827 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6835 rx_fifo.wr_addr[0]
-.sym 6836 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6838 rx_fifo.wr_addr[6]
-.sym 6840 rx_fifo.wr_addr[8]
-.sym 6843 rx_fifo.mem_i.0.2_WDATA_2
-.sym 6845 rx_fifo.wr_addr[4]
-.sym 6848 rx_fifo.wr_addr[3]
-.sym 6851 rx_fifo.wr_addr[9]
-.sym 6854 rx_fifo.wr_addr[2]
-.sym 6856 rx_fifo.wr_addr[1]
-.sym 6857 rx_fifo.wr_addr[7]
-.sym 6861 rx_fifo.mem_i.0.2_WDATA_3
-.sym 6862 rx_fifo.wr_addr[5]
-.sym 6863 $PACKER_VCC_NET
-.sym 6867 w_rx_24_fifo_data[24]
-.sym 6871 w_rx_24_fifo_data[26]
-.sym 6872 w_rx_24_fifo_data[28]
+.sym 6797 rx_fifo.mem_i.0.2_WDATA
+.sym 6801 rx_fifo.mem_i.0.2_WDATA_1
+.sym 6806 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6808 smi_ctrl_ins.int_cnt_rx[4]
+.sym 6810 w_rx_fifo_pulled_data[12]
+.sym 6813 $PACKER_VCC_NET
+.sym 6816 $PACKER_VCC_NET
+.sym 6818 rx_fifo.wr_addr[9]
+.sym 6819 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 6820 w_rx_fifo_pulled_data[8]
+.sym 6821 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 6822 rx_fifo.rd_addr[0]
+.sym 6823 rx_fifo.rd_addr[1]
+.sym 6824 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 6825 rx_fifo.wr_addr[4]
+.sym 6826 rx_fifo.rd_addr[9]
+.sym 6827 rx_fifo.wr_addr[3]
+.sym 6828 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6829 w_rx_fifo_pulled_data[14]
+.sym 6835 rx_fifo.wr_addr[9]
+.sym 6836 rx_fifo.wr_addr[1]
+.sym 6837 rx_fifo.wr_addr[3]
+.sym 6838 $PACKER_VCC_NET
+.sym 6840 rx_fifo.mem_q.0.1_WDATA_2
+.sym 6842 rx_fifo.wr_addr[7]
+.sym 6845 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6847 rx_fifo.mem_q.0.1_WDATA_3
+.sym 6849 rx_fifo.wr_addr[6]
+.sym 6851 rx_fifo.wr_addr[0]
+.sym 6853 rx_fifo.wr_addr[5]
+.sym 6854 rx_fifo.wr_addr[8]
+.sym 6861 rx_fifo.wr_addr[2]
+.sym 6865 rx_fifo.wr_addr[4]
+.sym 6866 rx_fifo.rd_addr[0]
+.sym 6868 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 6869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
+.sym 6870 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6871 rx_fifo.rd_addr[5]
+.sym 6873 rx_fifo.wr_addr[4]
 .sym 6882 rx_fifo.wr_addr[2]
 .sym 6883 rx_fifo.wr_addr[3]
 .sym 6885 rx_fifo.wr_addr[4]
@@ -6329,84 +6219,93 @@
 .sym 6891 rx_fifo.wr_addr[1]
 .sym 6892 rx_fifo.wr_addr[0]
 .sym 6893 lvds_clock_$glb_clk
-.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6896 rx_fifo.mem_i.0.2_WDATA_3
-.sym 6900 rx_fifo.mem_i.0.2_WDATA_2
+.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 6896 rx_fifo.mem_q.0.1_WDATA_3
+.sym 6900 rx_fifo.mem_q.0.1_WDATA_2
 .sym 6903 $PACKER_VCC_NET
-.sym 6910 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 6911 w_rx_09_fifo_data[24]
-.sym 6913 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
-.sym 6915 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
-.sym 6916 rx_fifo.wr_addr[8]
-.sym 6920 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6922 rx_fifo.rd_addr[9]
-.sym 6923 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 6925 rx_fifo.rd_addr[3]
-.sym 6927 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 6928 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6930 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6931 smi_ctrl_ins.r_fifo_pulled_data[2]
-.sym 6936 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6938 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6939 rx_fifo.rd_addr[9]
-.sym 6942 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6947 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 6954 rx_fifo.mem_i.0.2_WDATA
-.sym 6956 rx_fifo.rd_addr[8]
-.sym 6959 rx_fifo.rd_addr[0]
-.sym 6960 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6961 rx_fifo.rd_addr[6]
-.sym 6963 rx_fifo.mem_i.0.2_WDATA_1
-.sym 6964 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6965 $PACKER_VCC_NET
-.sym 6966 rx_fifo.rd_addr[3]
-.sym 6968 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6969 rx_fifo.mem_i.0.3_WDATA_3
-.sym 6970 rx_fifo.rd_addr[6]
-.sym 6971 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 6972 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6973 rx_fifo.rd_addr_gray[3]
-.sym 6974 rx_fifo.rd_addr[3]
-.sym 6975 rx_fifo.rd_addr[0]
-.sym 6984 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 6985 rx_fifo.rd_addr[3]
-.sym 6987 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 6988 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 6989 rx_fifo.rd_addr[6]
-.sym 6990 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 6991 rx_fifo.rd_addr[8]
+.sym 6908 rx_fifo.mem_i.0.0_WDATA_3
+.sym 6909 smi_ctrl_ins.r_fifo_pulled_data[10]
+.sym 6910 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 6911 rx_fifo.wr_addr[2]
+.sym 6912 rx_fifo.wr_addr[1]
+.sym 6913 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6914 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 6916 rx_fifo.mem_i.0.0_WDATA_2
+.sym 6917 $PACKER_VCC_NET
+.sym 6920 rx_fifo.wr_addr[8]
+.sym 6921 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6922 rx_fifo.wr_addr[0]
+.sym 6923 rx_fifo.rd_addr[5]
+.sym 6925 w_smi_data_direction
+.sym 6926 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 6929 $PACKER_VCC_NET
+.sym 6938 rx_fifo.rd_addr[2]
+.sym 6940 $PACKER_VCC_NET
+.sym 6941 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6942 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 6947 rx_fifo.mem_q.0.1_WDATA_1
+.sym 6951 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6954 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 6956 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6957 rx_fifo.rd_addr[5]
+.sym 6960 rx_fifo.rd_addr[0]
+.sym 6961 rx_fifo.rd_addr[1]
+.sym 6963 rx_fifo.mem_q.0.1_WDATA
+.sym 6964 rx_fifo.rd_addr[9]
+.sym 6966 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6968 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 6970 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
+.sym 6971 rx_fifo.wr_addr[4]
+.sym 6972 rx_fifo.wr_addr[3]
+.sym 6974 rx_fifo.wr_addr[8]
+.sym 6975 rx_fifo.wr_addr[0]
+.sym 6984 rx_fifo.rd_addr[2]
+.sym 6985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 6987 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 6988 rx_fifo.rd_addr[5]
+.sym 6989 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 6990 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 6991 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 6992 rx_fifo.rd_addr[9]
-.sym 6993 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 6993 rx_fifo.rd_addr[1]
 .sym 6994 rx_fifo.rd_addr[0]
 .sym 6995 r_counter_$glb_clk
-.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 6996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 6997 $PACKER_VCC_NET
-.sym 7001 rx_fifo.mem_i.0.2_WDATA
-.sym 7005 rx_fifo.mem_i.0.2_WDATA_1
-.sym 7023 rx_fifo.rd_addr[8]
-.sym 7029 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 7031 $PACKER_VCC_NET
-.sym 7038 rx_fifo.wr_addr[6]
-.sym 7042 $PACKER_VCC_NET
-.sym 7043 rx_fifo.wr_addr[0]
-.sym 7044 rx_fifo.wr_addr[8]
-.sym 7045 rx_fifo.wr_addr[7]
-.sym 7050 rx_fifo.wr_addr[9]
-.sym 7053 rx_fifo.wr_addr[4]
-.sym 7055 rx_fifo.wr_addr[3]
-.sym 7056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 7058 rx_fifo.wr_addr[2]
-.sym 7062 rx_fifo.wr_addr[5]
-.sym 7063 rx_fifo.mem_i.0.1_WDATA_2
-.sym 7065 rx_fifo.mem_i.0.1_WDATA_3
-.sym 7067 rx_fifo.wr_addr[1]
-.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[3]
-.sym 7071 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 7072 smi_ctrl_ins.r_fifo_pulled_data[1]
-.sym 7074 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[2]
-.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 7077 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 7001 rx_fifo.mem_q.0.1_WDATA
+.sym 7005 rx_fifo.mem_q.0.1_WDATA_1
+.sym 7013 i_rst_b$SB_IO_IN
+.sym 7014 rx_fifo.rd_addr[2]
+.sym 7016 $PACKER_VCC_NET
+.sym 7017 rx_fifo.rd_addr[0]
+.sym 7018 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7020 rx_fifo.mem_i.0.0_WDATA
+.sym 7021 smi_ctrl_ins.r_fifo_pulled_data[0]
+.sym 7023 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 7027 rx_fifo.wr_addr[8]
+.sym 7029 rx_fifo.wr_addr[0]
+.sym 7032 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7033 rx_fifo.wr_addr[9]
+.sym 7039 rx_fifo.wr_addr[9]
+.sym 7040 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 7044 rx_fifo.mem_q.0.2_WDATA_2
+.sym 7046 rx_fifo.wr_addr[5]
+.sym 7049 rx_fifo.wr_addr[4]
+.sym 7053 rx_fifo.mem_q.0.2_WDATA_3
+.sym 7055 rx_fifo.wr_addr[7]
+.sym 7060 rx_fifo.wr_addr[8]
+.sym 7061 rx_fifo.wr_addr[0]
+.sym 7063 rx_fifo.wr_addr[1]
+.sym 7065 rx_fifo.wr_addr[2]
+.sym 7066 rx_fifo.wr_addr[3]
+.sym 7067 $PACKER_VCC_NET
+.sym 7069 rx_fifo.wr_addr[6]
+.sym 7072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7073 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7074 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7075 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7076 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7077 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
 .sym 7086 rx_fifo.wr_addr[2]
 .sym 7087 rx_fifo.wr_addr[3]
 .sym 7089 rx_fifo.wr_addr[4]
@@ -6418,92 +6317,100 @@
 .sym 7095 rx_fifo.wr_addr[1]
 .sym 7096 rx_fifo.wr_addr[0]
 .sym 7097 lvds_clock_$glb_clk
-.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 7100 rx_fifo.mem_i.0.1_WDATA_3
-.sym 7104 rx_fifo.mem_i.0.1_WDATA_2
+.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 7100 rx_fifo.mem_q.0.2_WDATA_3
+.sym 7104 rx_fifo.mem_q.0.2_WDATA_2
 .sym 7107 $PACKER_VCC_NET
-.sym 7112 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 7114 w_rx_fifo_pulled_data[22]
-.sym 7115 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 7117 rx_fifo.rd_addr[0]
-.sym 7119 w_rx_09_fifo_data[28]
-.sym 7123 rx_fifo.rd_addr[6]
-.sym 7124 rx_fifo.rd_addr[6]
-.sym 7127 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 7128 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7130 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 7134 w_rx_fifo_pulled_data[3]
-.sym 7135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 7140 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 7142 rx_fifo.rd_addr[6]
-.sym 7144 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 7147 rx_fifo.rd_addr[0]
-.sym 7148 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 7151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 7152 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7154 rx_fifo.rd_addr[3]
-.sym 7156 rx_fifo.rd_addr[8]
-.sym 7158 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 7160 rx_fifo.mem_i.0.1_WDATA
-.sym 7161 rx_fifo.rd_addr[9]
-.sym 7162 rx_fifo.mem_i.0.1_WDATA_1
-.sym 7169 $PACKER_VCC_NET
-.sym 7172 rx_fifo.rd_addr[8]
-.sym 7173 rx_fifo.rd_addr_gray[6]
-.sym 7174 rx_fifo.rd_addr_gray[8]
-.sym 7175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
-.sym 7176 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
-.sym 7177 rx_fifo.rd_addr[9]
-.sym 7178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
-.sym 7179 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
-.sym 7188 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 7189 rx_fifo.rd_addr[3]
-.sym 7191 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 7192 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7193 rx_fifo.rd_addr[6]
-.sym 7194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 7195 rx_fifo.rd_addr[8]
+.sym 7112 rx_fifo.wr_addr[5]
+.sym 7113 rx_fifo.wr_addr[8]
+.sym 7115 rx_fifo.wr_addr[4]
+.sym 7117 rx_fifo.wr_addr[0]
+.sym 7118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 7119 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7120 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 7121 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7122 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7123 rx_fifo.rd_addr[1]
+.sym 7125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7126 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 7128 rx_fifo.wr_addr[3]
+.sym 7129 rx_fifo.rd_addr[5]
+.sym 7131 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 7133 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 7143 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7144 rx_fifo.mem_q.0.2_WDATA
+.sym 7146 rx_fifo.mem_q.0.2_WDATA_1
+.sym 7148 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 7149 rx_fifo.rd_addr[2]
+.sym 7150 rx_fifo.rd_addr[5]
+.sym 7151 rx_fifo.rd_addr[1]
+.sym 7153 $PACKER_VCC_NET
+.sym 7156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 7157 rx_fifo.rd_addr[9]
+.sym 7159 rx_fifo.rd_addr[0]
+.sym 7162 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 7169 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7172 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 7173 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 7174 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 7175 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 7176 rx_fifo.rd_addr_gray[5]
+.sym 7177 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
+.sym 7178 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 7179 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 7188 rx_fifo.rd_addr[2]
+.sym 7189 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 7191 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7192 rx_fifo.rd_addr[5]
+.sym 7193 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 7194 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7195 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 7196 rx_fifo.rd_addr[9]
-.sym 7197 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 7197 rx_fifo.rd_addr[1]
 .sym 7198 rx_fifo.rd_addr[0]
 .sym 7199 r_counter_$glb_clk
-.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 7200 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 7201 $PACKER_VCC_NET
-.sym 7205 rx_fifo.mem_i.0.1_WDATA
-.sym 7209 rx_fifo.mem_i.0.1_WDATA_1
-.sym 7210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 7215 rx_fifo.wr_addr[4]
-.sym 7216 w_rx_fifo_pulled_data[23]
-.sym 7220 rx_fifo.wr_addr[0]
-.sym 7222 rx_fifo.mem_i.0.3_WDATA_1
-.sym 7227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 7228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 7229 rx_fifo.rd_addr[9]
-.sym 7231 rx_fifo.rd_addr_gray[3]
-.sym 7233 w_rx_fifo_pulled_data[1]
-.sym 7236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 7246 rx_fifo.wr_addr[2]
-.sym 7249 rx_fifo.wr_addr[0]
-.sym 7251 rx_fifo.wr_addr[8]
-.sym 7253 rx_fifo.wr_addr[4]
-.sym 7255 rx_fifo.wr_addr[6]
-.sym 7257 rx_fifo.mem_q.0.0_WDATA_2
-.sym 7258 rx_fifo.mem_q.0.0_WDATA_3
-.sym 7259 rx_fifo.wr_addr[3]
-.sym 7262 $PACKER_VCC_NET
-.sym 7263 rx_fifo.wr_addr[9]
-.sym 7266 rx_fifo.wr_addr[5]
-.sym 7268 rx_fifo.wr_addr[7]
-.sym 7271 rx_fifo.wr_addr[1]
-.sym 7274 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 7275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
-.sym 7276 rx_fifo.empty_o_SB_LUT4_I0_O[3]
-.sym 7277 rx_fifo.empty_o_SB_LUT4_I0_O[2]
-.sym 7278 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
-.sym 7279 rx_fifo.rd_addr_gray_wr[6]
-.sym 7280 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
-.sym 7281 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
+.sym 7205 rx_fifo.mem_q.0.2_WDATA
+.sym 7209 rx_fifo.mem_q.0.2_WDATA_1
+.sym 7217 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7218 $PACKER_VCC_NET
+.sym 7220 rx_fifo.wr_addr[1]
+.sym 7222 rx_fifo.wr_addr[2]
+.sym 7225 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7226 rx_fifo.rd_addr[9]
+.sym 7227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 7228 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7229 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 7231 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 7232 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 7233 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7234 rx_fifo.wr_addr[4]
+.sym 7235 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7236 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 7237 rx_fifo.wr_addr[9]
+.sym 7243 rx_fifo.wr_addr[9]
+.sym 7244 rx_fifo.wr_addr[4]
+.sym 7246 rx_fifo.wr_addr[1]
+.sym 7249 rx_fifo.wr_addr[5]
+.sym 7250 rx_fifo.wr_addr[7]
+.sym 7251 rx_fifo.mem_q.0.0_WDATA_3
+.sym 7253 rx_fifo.wr_addr[6]
+.sym 7255 rx_fifo.wr_addr[2]
+.sym 7256 rx_fifo.wr_addr[0]
+.sym 7260 rx_fifo.mem_q.0.0_WDATA_2
+.sym 7262 rx_fifo.wr_addr[8]
+.sym 7266 rx_fifo.wr_addr[3]
+.sym 7269 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 7271 $PACKER_VCC_NET
+.sym 7274 rx_fifo.rd_addr_gray[0]
+.sym 7275 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
+.sym 7276 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
+.sym 7277 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
+.sym 7279 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 7280 rx_fifo.rd_addr[9]
+.sym 7281 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
 .sym 7290 rx_fifo.wr_addr[2]
 .sym 7291 rx_fifo.wr_addr[3]
 .sym 7293 rx_fifo.wr_addr[4]
@@ -6515,3805 +6422,4081 @@
 .sym 7299 rx_fifo.wr_addr[1]
 .sym 7300 rx_fifo.wr_addr[0]
 .sym 7301 lvds_clock_$glb_clk
-.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
+.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
 .sym 7304 rx_fifo.mem_q.0.0_WDATA_3
 .sym 7308 rx_fifo.mem_q.0.0_WDATA_2
 .sym 7311 $PACKER_VCC_NET
-.sym 7316 rx_fifo.wr_addr_gray[3]
-.sym 7320 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 7323 rx_fifo.rd_addr[8]
-.sym 7327 i_rst_b$SB_IO_IN
-.sym 7330 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 7331 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 7334 rx_fifo.rd_addr[9]
-.sym 7335 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 7336 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 7338 rx_fifo.rd_addr[3]
-.sym 7344 rx_fifo.rd_addr[8]
-.sym 7346 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 7348 rx_fifo.mem_q.0.0_WDATA
-.sym 7349 rx_fifo.rd_addr[9]
-.sym 7353 rx_fifo.rd_addr[6]
-.sym 7355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 7357 rx_fifo.mem_q.0.0_WDATA_1
-.sym 7358 rx_fifo.rd_addr[0]
-.sym 7359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 7362 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 7363 rx_fifo.rd_addr[3]
-.sym 7364 $PACKER_VCC_NET
-.sym 7365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 7374 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7376 rx_fifo.rd_addr_gray_wr[8]
-.sym 7377 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 7378 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 7379 rx_fifo.rd_addr_gray_wr[2]
-.sym 7380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 7381 rx_fifo.rd_addr_gray_wr[9]
-.sym 7382 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 7383 rx_fifo.rd_addr_gray_wr[5]
-.sym 7392 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 7393 rx_fifo.rd_addr[3]
-.sym 7395 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 7396 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 7397 rx_fifo.rd_addr[6]
-.sym 7398 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 7399 rx_fifo.rd_addr[8]
+.sym 7316 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 7319 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 7322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 7323 i_rst_b$SB_IO_IN
+.sym 7324 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7325 $PACKER_VCC_NET
+.sym 7333 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 7338 rx_fifo.mem_q.0.0_WDATA
+.sym 7344 rx_fifo.mem_q.0.0_WDATA
+.sym 7347 rx_fifo.rd_addr[0]
+.sym 7348 rx_fifo.rd_addr[1]
+.sym 7350 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7351 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7355 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 7356 rx_fifo.rd_addr[5]
+.sym 7357 rx_fifo.rd_addr[2]
+.sym 7360 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 7366 rx_fifo.mem_q.0.0_WDATA_1
+.sym 7367 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 7371 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7373 $PACKER_VCC_NET
+.sym 7374 rx_fifo.rd_addr[9]
+.sym 7376 rx_fifo.wr_addr_gray[1]
+.sym 7377 w_smi_read_req_SB_LUT4_I1_I3[3]
+.sym 7378 rx_fifo.wr_addr_gray[8]
+.sym 7379 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 7380 rx_fifo.wr_addr_gray[5]
+.sym 7381 rx_fifo.wr_addr[9]
+.sym 7383 rx_fifo.wr_addr_gray[0]
+.sym 7392 rx_fifo.rd_addr[2]
+.sym 7393 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 7395 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 7396 rx_fifo.rd_addr[5]
+.sym 7397 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 7398 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 7399 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 7400 rx_fifo.rd_addr[9]
-.sym 7401 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 7401 rx_fifo.rd_addr[1]
 .sym 7402 rx_fifo.rd_addr[0]
 .sym 7403 r_counter_$glb_clk
-.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 7404 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 7405 $PACKER_VCC_NET
 .sym 7409 rx_fifo.mem_q.0.0_WDATA
 .sym 7413 rx_fifo.mem_q.0.0_WDATA_1
-.sym 7415 w_ioc[1]
-.sym 7422 i_rst_b$SB_IO_IN
-.sym 7430 $PACKER_VCC_NET
-.sym 7431 w_lvds_rx_24_d0
-.sym 7433 w_lvds_rx_24_d1
-.sym 7437 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 7441 $PACKER_VCC_NET
-.sym 7479 w_rx_24_fifo_data[1]
-.sym 7480 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
-.sym 7481 w_rx_24_fifo_data[0]
-.sym 7528 i_rst_b$SB_IO_IN
-.sym 7531 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 7532 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 7535 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 7541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 7542 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 7543 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 7580 rx_fifo.wr_addr_gray[5]
-.sym 7581 rx_fifo.wr_addr_gray[4]
-.sym 7582 rx_fifo.wr_addr_gray[6]
-.sym 7583 rx_fifo.wr_addr_gray[2]
-.sym 7584 rx_fifo.wr_addr_gray[1]
-.sym 7585 rx_fifo.wr_addr_gray[8]
-.sym 7587 rx_fifo.wr_addr_gray[0]
-.sym 7624 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 7625 w_rx_24_fifo_data[0]
-.sym 7626 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 7627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 7629 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 7633 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 7636 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 7639 rx_fifo.rd_addr_gray[3]
-.sym 7641 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 7682 rx_fifo.wr_addr_gray_rd[7]
-.sym 7683 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 7684 rx_fifo.wr_addr_gray_rd[4]
-.sym 7686 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 7688 rx_fifo.wr_addr_gray_rd[6]
-.sym 7689 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 7724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 7730 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 7732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 7787 rx_fifo.rd_addr_gray_wr[3]
-.sym 7789 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 7830 rx_fifo.wr_addr_gray[7]
-.sym 8043 o_shdn_rx_lna$SB_IO_OUT
+.sym 7418 w_rx_fifo_full
+.sym 7419 rx_fifo.rd_addr[9]
+.sym 7423 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 7425 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 7426 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 7428 rx_fifo.rd_addr[1]
+.sym 7433 rx_fifo.wr_addr[9]
+.sym 7436 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7479 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 7480 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 7481 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 7482 rx_fifo.wr_addr_gray_rd[5]
+.sym 7484 rx_fifo.wr_addr_gray_rd[8]
+.sym 7485 rx_fifo.wr_addr_gray_rd[1]
+.sym 7521 rx_fifo.wr_addr[1]
+.sym 7529 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 7530 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 7531 i_rst_b$SB_IO_IN
+.sym 7533 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 7542 $PACKER_VCC_NET
+.sym 7580 rx_fifo.wr_addr_gray_rd[4]
+.sym 7582 rx_fifo.wr_addr_gray_rd[2]
+.sym 7583 rx_fifo.wr_addr_gray_rd[6]
+.sym 7584 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 7585 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 7587 rx_fifo.wr_addr_gray_rd[3]
+.sym 7636 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 7682 rx_fifo.wr_addr_gray[2]
+.sym 7683 rx_fifo.wr_addr_gray[3]
+.sym 7684 rx_fifo.wr_addr_gray[7]
+.sym 7685 rx_fifo.wr_addr_gray[6]
+.sym 7689 rx_fifo.wr_addr_gray[4]
+.sym 7728 i_rst_b$SB_IO_IN
+.sym 7835 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 7929 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 7935 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
 .sym 8093 w_smi_data_output[6]
 .sym 8095 w_smi_data_direction
 .sym 8099 $PACKER_VCC_NET
-.sym 8110 w_smi_data_direction
-.sym 8112 $PACKER_VCC_NET
-.sym 8117 w_smi_data_output[6]
-.sym 8118 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 8119 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 8120 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 8121 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
-.sym 8122 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 8123 tx_fifo.rd_addr[0]
-.sym 8124 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 8125 tx_fifo.rd_addr[2]
-.sym 8150 w_smi_data_direction
-.sym 8153 w_smi_data_output[1]
-.sym 8247 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 8248 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 8249 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 8250 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 8251 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 8252 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 8253 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 8260 $PACKER_VCC_NET
-.sym 8263 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 8265 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 8272 $PACKER_VCC_NET
-.sym 8276 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 8290 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 8296 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 8298 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 8302 smi_ctrl_ins.r_fifo_pulled_data[8]
-.sym 8309 smi_ctrl_ins.r_fifo_pulled_data[14]
-.sym 8312 tx_fifo.rd_addr[9]
-.sym 8325 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 8326 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
-.sym 8329 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 8332 w_rx_fifo_pulled_data[13]
-.sym 8336 w_rx_fifo_pulled_data[15]
-.sym 8340 w_rx_fifo_pulled_data[12]
-.sym 8342 w_rx_fifo_pulled_data[11]
-.sym 8344 w_rx_fifo_pulled_data[14]
-.sym 8348 w_rx_fifo_pulled_data[8]
-.sym 8350 w_rx_fifo_pulled_data[9]
-.sym 8353 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 8359 w_rx_fifo_pulled_data[14]
-.sym 8362 w_rx_fifo_pulled_data[12]
-.sym 8368 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 8369 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
-.sym 8370 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 8371 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 8375 w_rx_fifo_pulled_data[13]
-.sym 8380 w_rx_fifo_pulled_data[9]
-.sym 8387 w_rx_fifo_pulled_data[8]
-.sym 8393 w_rx_fifo_pulled_data[11]
-.sym 8401 w_rx_fifo_pulled_data[15]
+.sym 8106 w_smi_data_output[6]
+.sym 8112 w_smi_data_direction
+.sym 8115 $PACKER_VCC_NET
+.sym 8118 tx_fifo.rd_addr[0]
+.sym 8119 tx_fifo.rd_addr[2]
+.sym 8120 tx_fifo.rd_addr[1]
+.sym 8121 tx_fifo.rd_addr[4]
+.sym 8122 tx_fifo.rd_addr_gray[2]
+.sym 8123 tx_fifo.rd_addr[3]
+.sym 8124 tx_fifo.rd_addr_gray[3]
+.sym 8125 tx_fifo.rd_addr[7]
+.sym 8137 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8140 rx_fifo.rd_addr[5]
+.sym 8168 tx_fifo.rd_addr_gray_wr[3]
+.sym 8171 tx_fifo.rd_addr_gray_wr[5]
+.sym 8176 tx_fifo.rd_addr_gray[5]
+.sym 8180 tx_fifo.rd_addr_gray[2]
+.sym 8182 tx_fifo.rd_addr_gray[3]
+.sym 8190 tx_fifo.rd_addr_gray_wr[6]
+.sym 8191 tx_fifo.rd_addr_gray[6]
+.sym 8193 tx_fifo.rd_addr_gray[3]
+.sym 8202 tx_fifo.rd_addr_gray[2]
+.sym 8205 tx_fifo.rd_addr_gray_wr[5]
+.sym 8212 tx_fifo.rd_addr_gray[5]
+.sym 8218 tx_fifo.rd_addr_gray_wr[6]
+.sym 8225 tx_fifo.rd_addr_gray_wr[3]
+.sym 8231 tx_fifo.rd_addr_gray[6]
+.sym 8240 r_counter_$glb_clk
+.sym 8246 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
+.sym 8247 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
+.sym 8248 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 8249 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 8250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 8251 w_tx_fifo_pull
+.sym 8252 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.sym 8253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
+.sym 8260 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8262 tx_fifo.rd_addr_gray_wr[2]
+.sym 8264 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 8269 tx_fifo.rd_addr[1]
+.sym 8287 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 8288 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 8294 tx_fifo.rd_addr[7]
+.sym 8295 i_rst_b_SB_LUT4_I3_O
+.sym 8298 tx_fifo.rd_addr[2]
+.sym 8299 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 8300 tx_fifo.rd_addr[1]
+.sym 8301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8307 tx_fifo.rd_addr[3]
+.sym 8308 w_smi_data_direction
+.sym 8309 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
+.sym 8312 tx_fifo.rd_addr_gray[6]
+.sym 8315 i_rst_b_SB_LUT4_I3_O
+.sym 8323 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 8324 w_rx_fifo_pulled_data[21]
+.sym 8326 w_rx_fifo_pulled_data[15]
+.sym 8327 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8333 smi_ctrl_ins.r_fifo_pulled_data[26]
+.sym 8335 w_rx_fifo_pulled_data[13]
+.sym 8336 w_rx_fifo_pulled_data[23]
+.sym 8337 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8344 w_rx_fifo_pulled_data[22]
+.sym 8348 w_rx_fifo_pulled_data[20]
+.sym 8352 w_rx_fifo_pulled_data[26]
+.sym 8356 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8357 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8358 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 8359 smi_ctrl_ins.r_fifo_pulled_data[26]
+.sym 8362 w_rx_fifo_pulled_data[13]
+.sym 8368 w_rx_fifo_pulled_data[26]
+.sym 8376 w_rx_fifo_pulled_data[15]
+.sym 8380 w_rx_fifo_pulled_data[23]
+.sym 8388 w_rx_fifo_pulled_data[21]
+.sym 8394 w_rx_fifo_pulled_data[20]
+.sym 8398 w_rx_fifo_pulled_data[22]
 .sym 8402 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
 .sym 8403 smi_ctrl_ins.soe_and_reset_$glb_clk
 .sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 8407 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
-.sym 8408 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
-.sym 8409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 8410 tx_fifo.rd_addr_gray_wr[2]
-.sym 8411 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 8412 tx_fifo.rd_addr_gray_wr[4]
-.sym 8415 rx_fifo.rd_addr[9]
-.sym 8432 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 8438 smi_ctrl_ins.r_fifo_pulled_data[11]
-.sym 8439 tx_fifo.rd_addr[1]
-.sym 8448 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
-.sym 8452 w_tx_fifo_pull
-.sym 8453 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 8455 i_rst_b$SB_IO_IN
+.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
+.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.sym 8407 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.sym 8408 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
+.sym 8409 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
+.sym 8410 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
+.sym 8411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 8412 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 8423 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8435 i_rst_b$SB_IO_IN
+.sym 8436 smi_ctrl_ins.r_fifo_pulled_data[21]
+.sym 8439 smi_ctrl_ins.r_fifo_pulled_data[5]
+.sym 8440 smi_ctrl_ins.r_fifo_pulled_data[22]
+.sym 8448 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 8449 smi_ctrl_ins.r_fifo_pulled_data[15]
+.sym 8452 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8455 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
 .sym 8457 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 8462 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 8464 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 8468 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
-.sym 8472 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
-.sym 8479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 8486 i_rst_b$SB_IO_IN
-.sym 8488 w_tx_fifo_pull
-.sym 8491 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
-.sym 8493 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
-.sym 8506 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
-.sym 8510 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 8518 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
+.sym 8458 w_rx_09_fifo_data[26]
+.sym 8459 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8460 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 8464 tx_fifo.rd_addr[2]
+.sym 8466 tx_fifo.rd_addr[1]
+.sym 8468 w_rx_24_fifo_data[26]
+.sym 8469 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 8476 smi_ctrl_ins.r_fifo_pulled_data[7]
+.sym 8498 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 8505 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 8510 tx_fifo.rd_addr[1]
+.sym 8511 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 8512 tx_fifo.rd_addr[2]
+.sym 8515 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8516 smi_ctrl_ins.r_fifo_pulled_data[15]
+.sym 8517 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8518 smi_ctrl_ins.r_fifo_pulled_data[7]
+.sym 8521 w_rx_09_fifo_data[26]
+.sym 8522 w_rx_24_fifo_data[26]
+.sym 8523 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
 .sym 8525 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
 .sym 8526 lvds_clock_$glb_clk
 .sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 8528 tx_fifo.rd_addr_gray[8]
-.sym 8529 tx_fifo.rd_addr_gray[0]
-.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
-.sym 8531 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
-.sym 8533 tx_fifo.rd_addr[9]
-.sym 8534 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
-.sym 8535 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 8540 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 8544 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 8545 tx_fifo.rd_addr_gray_wr[4]
-.sym 8557 smi_ctrl_ins.int_cnt_rx[4]
-.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 8563 smi_ctrl_ins.int_cnt_rx[3]
-.sym 8569 tx_fifo.rd_addr_gray[1]
-.sym 8573 tx_fifo.rd_addr_gray_wr[8]
-.sym 8586 tx_fifo.rd_addr_gray[0]
-.sym 8587 tx_fifo.rd_addr_gray_wr[9]
-.sym 8591 tx_fifo.rd_addr_gray_wr[1]
-.sym 8593 tx_fifo.rd_addr_gray[8]
-.sym 8596 tx_fifo.rd_addr_gray_wr[0]
-.sym 8598 tx_fifo.rd_addr[9]
-.sym 8604 tx_fifo.rd_addr_gray_wr[8]
-.sym 8609 tx_fifo.rd_addr_gray_wr[0]
-.sym 8616 tx_fifo.rd_addr[9]
-.sym 8620 tx_fifo.rd_addr_gray[0]
-.sym 8627 tx_fifo.rd_addr_gray[8]
-.sym 8635 tx_fifo.rd_addr_gray_wr[9]
-.sym 8640 tx_fifo.rd_addr_gray[1]
-.sym 8647 tx_fifo.rd_addr_gray_wr[1]
-.sym 8649 r_counter_$glb_clk
-.sym 8651 smi_ctrl_ins.r_fifo_pulled_data[6]
-.sym 8652 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 8653 smi_ctrl_ins.r_fifo_pulled_data[19]
-.sym 8654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
-.sym 8655 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
-.sym 8656 smi_ctrl_ins.r_fifo_pulled_data[18]
-.sym 8657 smi_ctrl_ins.r_fifo_pulled_data[4]
-.sym 8658 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
-.sym 8663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 8665 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 8667 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 8668 rx_fifo.rd_addr[9]
-.sym 8669 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 8671 w_smi_data_output[1]
-.sym 8672 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 8677 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 8682 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 8686 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 8693 w_rx_24_fifo_data[24]
+.sym 8528 w_smi_data_output[2]
+.sym 8529 w_smi_data_output[7]
+.sym 8530 w_smi_data_output[6]
+.sym 8531 smi_ctrl_ins.w_fifo_pull_trigger
+.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
+.sym 8533 w_smi_data_output[5]
+.sym 8534 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 8542 w_rx_fifo_pulled_data[14]
+.sym 8545 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 8548 rx_fifo.wr_addr[9]
+.sym 8550 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8556 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8558 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8560 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8561 tx_fifo.rd_addr[6]
+.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[25]
+.sym 8570 w_rx_fifo_pulled_data[25]
+.sym 8571 smi_ctrl_ins.r_fifo_pulled_data[13]
+.sym 8574 w_rx_fifo_pulled_data[27]
+.sym 8576 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8582 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8584 w_rx_fifo_pulled_data[12]
+.sym 8586 w_rx_fifo_pulled_data[24]
+.sym 8589 smi_ctrl_ins.r_fifo_pulled_data[6]
+.sym 8590 smi_ctrl_ins.r_fifo_pulled_data[14]
+.sym 8592 w_rx_fifo_pulled_data[14]
+.sym 8598 w_rx_fifo_pulled_data[6]
+.sym 8599 smi_ctrl_ins.r_fifo_pulled_data[5]
+.sym 8605 w_rx_fifo_pulled_data[24]
+.sym 8610 w_rx_fifo_pulled_data[25]
+.sym 8617 w_rx_fifo_pulled_data[27]
+.sym 8621 w_rx_fifo_pulled_data[12]
+.sym 8628 w_rx_fifo_pulled_data[6]
+.sym 8634 w_rx_fifo_pulled_data[14]
+.sym 8638 smi_ctrl_ins.r_fifo_pulled_data[13]
+.sym 8639 smi_ctrl_ins.r_fifo_pulled_data[5]
+.sym 8640 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8641 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8644 smi_ctrl_ins.r_fifo_pulled_data[14]
+.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[6]
+.sym 8646 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8647 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8648 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
+.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 8651 smi_ctrl_ins.r_fifo_pull
+.sym 8654 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 8657 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
+.sym 8658 smi_ctrl_ins.r_fifo_pull_1
+.sym 8659 rx_fifo.rd_addr[9]
+.sym 8661 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 8662 rx_fifo.rd_addr[9]
+.sym 8663 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 8668 $PACKER_VCC_NET
+.sym 8669 smi_ctrl_ins.r_fifo_pulled_data[27]
+.sym 8672 rx_fifo.rd_addr[5]
+.sym 8674 w_smi_data_output[6]
+.sym 8675 smi_ctrl_ins.r_fifo_pulled_data[9]
+.sym 8683 rx_fifo.wr_addr[3]
+.sym 8685 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 8692 smi_ctrl_ins.r_fifo_pulled_data[24]
+.sym 8693 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8694 w_rx_fifo_pulled_data[16]
 .sym 8696 smi_ctrl_ins.r_fifo_pulled_data[10]
-.sym 8697 w_rx_fifo_pulled_data[26]
-.sym 8698 w_rx_09_fifo_data[24]
-.sym 8701 w_rx_fifo_pulled_data[24]
-.sym 8703 w_rx_fifo_pulled_data[10]
-.sym 8705 smi_ctrl_ins.r_fifo_pulled_data[9]
-.sym 8709 w_rx_fifo_pulled_data[25]
-.sym 8710 smi_ctrl_ins.int_cnt_rx[4]
-.sym 8713 smi_ctrl_ins.int_cnt_rx[3]
-.sym 8715 smi_ctrl_ins.r_fifo_pulled_data[2]
-.sym 8716 smi_ctrl_ins.r_fifo_pulled_data[1]
-.sym 8721 w_rx_fifo_pulled_data[27]
-.sym 8723 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 8725 smi_ctrl_ins.r_fifo_pulled_data[9]
-.sym 8726 smi_ctrl_ins.int_cnt_rx[3]
-.sym 8727 smi_ctrl_ins.int_cnt_rx[4]
-.sym 8728 smi_ctrl_ins.r_fifo_pulled_data[1]
-.sym 8732 w_rx_fifo_pulled_data[27]
-.sym 8740 w_rx_fifo_pulled_data[25]
-.sym 8743 w_rx_24_fifo_data[24]
-.sym 8744 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 8746 w_rx_09_fifo_data[24]
-.sym 8749 w_rx_fifo_pulled_data[10]
-.sym 8758 w_rx_fifo_pulled_data[24]
-.sym 8764 w_rx_fifo_pulled_data[26]
-.sym 8767 smi_ctrl_ins.r_fifo_pulled_data[2]
-.sym 8768 smi_ctrl_ins.r_fifo_pulled_data[10]
-.sym 8769 smi_ctrl_ins.int_cnt_rx[3]
-.sym 8770 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8701 w_rx_fifo_pulled_data[4]
+.sym 8710 smi_ctrl_ins.r_fifo_pulled_data[16]
+.sym 8711 w_rx_fifo_pulled_data[8]
+.sym 8713 w_rx_fifo_pulled_data[7]
+.sym 8716 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8717 smi_ctrl_ins.r_fifo_pulled_data[2]
+.sym 8728 w_rx_fifo_pulled_data[8]
+.sym 8739 w_rx_fifo_pulled_data[16]
+.sym 8743 w_rx_fifo_pulled_data[7]
+.sym 8749 smi_ctrl_ins.r_fifo_pulled_data[24]
+.sym 8750 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8751 smi_ctrl_ins.r_fifo_pulled_data[16]
+.sym 8752 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8755 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8756 smi_ctrl_ins.r_fifo_pulled_data[2]
+.sym 8757 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8758 smi_ctrl_ins.r_fifo_pulled_data[10]
+.sym 8768 w_rx_fifo_pulled_data[4]
 .sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
 .sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk
 .sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 8776 smi_ctrl_ins.int_cnt_rx[4]
-.sym 8779 smi_ctrl_ins.int_cnt_rx[3]
-.sym 8786 io_pmod[0]$SB_IO_IN
-.sym 8787 $PACKER_VCC_NET
-.sym 8790 w_rx_fifo_pulled_data[6]
-.sym 8792 smi_ctrl_ins.r_fifo_pulled_data[25]
-.sym 8798 smi_ctrl_ins.r_fifo_pulled_data[3]
-.sym 8801 rx_fifo.rd_addr[0]
-.sym 8802 smi_ctrl_ins.r_fifo_pulled_data[1]
-.sym 8803 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 8806 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 8807 rx_fifo.rd_addr[6]
-.sym 8808 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 8809 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 8828 w_rx_24_fifo_data[26]
-.sym 8832 w_rx_24_fifo_data[24]
-.sym 8837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 8842 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 8843 w_rx_24_fifo_data[22]
-.sym 8854 w_rx_24_fifo_data[22]
-.sym 8855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 8878 w_rx_24_fifo_data[24]
-.sym 8879 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 8884 w_rx_24_fifo_data[26]
-.sym 8886 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 8894 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 8895 lvds_clock_$glb_clk
-.sym 8896 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
-.sym 8898 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
+.sym 8774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
+.sym 8775 w_smi_data_output[1]
+.sym 8776 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 8777 w_smi_data_output[0]
+.sym 8780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
+.sym 8788 w_rx_fifo_pulled_data[16]
+.sym 8797 rx_fifo.wr_addr[8]
+.sym 8798 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 8799 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 8800 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 8805 w_smi_data_direction
+.sym 8806 rx_fifo.rd_addr[0]
+.sym 8815 rx_fifo.rd_addr[0]
+.sym 8818 rx_fifo.wr_addr[4]
+.sym 8819 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8823 smi_ctrl_ins.r_fifo_pulled_data[8]
+.sym 8826 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 8827 smi_ctrl_ins.r_fifo_pulled_data[0]
+.sym 8828 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8833 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 8844 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 8845 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 8850 rx_fifo.rd_addr[0]
+.sym 8862 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 8866 smi_ctrl_ins.r_fifo_pulled_data[8]
+.sym 8867 smi_ctrl_ins.int_cnt_rx[4]
+.sym 8868 smi_ctrl_ins.r_fifo_pulled_data[0]
+.sym 8869 smi_ctrl_ins.int_cnt_rx[3]
+.sym 8873 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 8879 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 8892 rx_fifo.wr_addr[4]
+.sym 8894 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 8895 r_counter_$glb_clk
+.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 8898 w_smi_read_req_SB_LUT4_I1_I3[2]
 .sym 8899 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 8911 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 8913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 8920 smi_ctrl_ins.int_cnt_rx[4]
-.sym 8943 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 8944 w_rx_24_fifo_data[28]
-.sym 8946 w_rx_09_fifo_data[28]
-.sym 8949 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 8955 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 8956 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 8959 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 8961 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 8965 rx_fifo.rd_addr[3]
-.sym 8968 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 8969 rx_fifo.rd_addr[0]
-.sym 8972 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 8977 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 8978 w_rx_24_fifo_data[28]
-.sym 8979 w_rx_09_fifo_data[28]
-.sym 8984 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 8989 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 8996 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 9002 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 9009 rx_fifo.rd_addr[3]
-.sym 9014 rx_fifo.rd_addr[0]
-.sym 9017 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9018 r_counter_$glb_clk
+.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 8906 smi_ctrl_ins.r_fifo_pulled_data[17]
+.sym 8908 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 8909 rx_fifo.rd_addr[0]
+.sym 8911 rx_fifo.rd_addr[5]
+.sym 8916 $PACKER_VCC_NET
+.sym 8919 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8920 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 8921 rx_fifo.wr_addr[3]
+.sym 8922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8923 rx_fifo.wr_addr[5]
+.sym 8924 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 8925 rx_fifo.wr_addr[7]
+.sym 8926 i_rst_b$SB_IO_IN
+.sym 8927 rx_fifo.wr_addr[0]
+.sym 8928 rx_fifo.wr_addr[9]
+.sym 8930 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 8931 rx_fifo.wr_addr[6]
+.sym 8932 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 8941 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 8942 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8943 rx_fifo.rd_addr[5]
+.sym 8944 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8945 rx_fifo.wr_addr[0]
+.sym 8948 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 8949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8950 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 8953 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 8954 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 8965 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 8971 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 8973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 8974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 8984 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 8985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 8986 rx_fifo.rd_addr[5]
+.sym 8991 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 8997 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9009 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9013 rx_fifo.wr_addr[0]
+.sym 9017 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 9018 lvds_clock_$glb_clk
 .sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 9022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9023 rx_fifo.rd_addr[3]
-.sym 9024 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 9026 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 9032 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 9034 rx_fifo.rd_addr_gray[3]
-.sym 9036 rx_fifo.mem_i.0.3_WDATA_3
-.sym 9045 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9047 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9048 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 9049 rx_fifo.rd_addr[8]
-.sym 9052 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 9054 w_rx_24_fifo_data[1]
-.sym 9065 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 9068 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 9070 w_rx_fifo_pulled_data[21]
-.sym 9074 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 9075 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 9080 w_rx_fifo_pulled_data[3]
-.sym 9082 w_rx_fifo_pulled_data[2]
-.sym 9086 w_rx_fifo_pulled_data[0]
-.sym 9088 w_rx_fifo_pulled_data[1]
-.sym 9095 w_rx_fifo_pulled_data[3]
-.sym 9100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 9102 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 9108 w_rx_fifo_pulled_data[1]
-.sym 9120 w_rx_fifo_pulled_data[0]
-.sym 9126 w_rx_fifo_pulled_data[2]
-.sym 9130 w_rx_fifo_pulled_data[21]
-.sym 9137 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 9139 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 9143 rx_fifo.wr_addr_gray_rd[3]
-.sym 9144 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
-.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
-.sym 9147 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 9149 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
-.sym 9150 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
-.sym 9156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9158 rx_fifo.rd_addr[3]
-.sym 9163 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 9165 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 9166 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9167 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9169 rx_fifo.rd_addr[9]
-.sym 9171 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 9175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9176 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 9178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 9185 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 9186 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9187 rx_fifo.rd_addr[3]
-.sym 9189 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 9190 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9192 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 9194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 9202 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 9206 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 9207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 9213 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 9215 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
-.sym 9218 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 9225 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 9229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 9235 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
-.sym 9237 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9238 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 9242 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9243 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 9248 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 9253 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 9254 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 9255 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 9256 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 9259 rx_fifo.rd_addr[3]
-.sym 9260 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 9262 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
+.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 9023 w_smi_data_direction
+.sym 9024 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 9026 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 9027 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
+.sym 9028 rx_fifo.wr_addr[3]
+.sym 9031 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 9032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 9034 rx_fifo.wr_addr[9]
+.sym 9035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 9036 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 9038 rx_fifo.rd_addr[1]
+.sym 9040 rx_fifo.wr_addr[4]
+.sym 9042 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 9044 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 9045 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 9046 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9047 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9049 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 9050 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 9051 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 9052 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 9062 rx_fifo.wr_addr[1]
+.sym 9064 rx_fifo.wr_addr[4]
+.sym 9068 rx_fifo.wr_addr[0]
+.sym 9072 rx_fifo.wr_addr[2]
+.sym 9073 rx_fifo.wr_addr[3]
+.sym 9083 rx_fifo.wr_addr[5]
+.sym 9085 rx_fifo.wr_addr[7]
+.sym 9091 rx_fifo.wr_addr[6]
+.sym 9093 $nextpnr_ICESTORM_LC_8$O
+.sym 9095 rx_fifo.wr_addr[0]
+.sym 9099 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9102 rx_fifo.wr_addr[1]
+.sym 9105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9108 rx_fifo.wr_addr[2]
+.sym 9109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9111 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9114 rx_fifo.wr_addr[3]
+.sym 9115 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9117 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9119 rx_fifo.wr_addr[4]
+.sym 9121 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9123 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9125 rx_fifo.wr_addr[5]
+.sym 9127 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9129 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 9131 rx_fifo.wr_addr[6]
+.sym 9133 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 9135 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 9138 rx_fifo.wr_addr[7]
+.sym 9139 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 9143 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9144 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 9145 spi_if_ins.spi.SCKr[0]
+.sym 9146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 9147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 9148 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 9150 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 9158 w_smi_data_direction
+.sym 9160 $PACKER_VCC_NET
+.sym 9161 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 9163 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 9164 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
+.sym 9165 rx_fifo.rd_addr[5]
+.sym 9167 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 9168 rx_fifo.rd_addr[9]
+.sym 9169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 9170 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9171 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.sym 9172 rx_fifo.rd_addr_gray[0]
+.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 9174 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 9175 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9176 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9177 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 9188 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9189 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9190 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9193 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 9195 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9196 rx_fifo.wr_addr[8]
+.sym 9198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 9199 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 9202 rx_fifo.wr_addr[9]
+.sym 9205 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
+.sym 9206 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9207 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 9210 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9216 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 9218 rx_fifo.wr_addr[8]
+.sym 9220 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 9224 rx_fifo.wr_addr[9]
+.sym 9226 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 9229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9231 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 9235 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 9236 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9237 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
+.sym 9238 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 9242 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 9247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 9248 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9250 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9255 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9256 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9261 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9262 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
 .sym 9264 r_counter_$glb_clk
 .sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 9266 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 9268 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
-.sym 9271 rx_fifo.empty_o_SB_LUT4_I0_O[1]
-.sym 9272 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 9273 rx_fifo.empty_o_SB_LUT4_I0_O[0]
-.sym 9280 $PACKER_VCC_NET
-.sym 9283 $PACKER_VCC_NET
-.sym 9287 $PACKER_VCC_NET
-.sym 9291 rx_fifo.rd_addr_gray[8]
-.sym 9292 w_rx_24_fifo_data[1]
-.sym 9293 w_rx_data[0]
-.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 9297 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 9299 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9307 rx_fifo.rd_addr[8]
-.sym 9308 rx_fifo.rd_addr[6]
-.sym 9311 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
-.sym 9312 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 9313 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 9314 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
-.sym 9315 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 9316 rx_fifo.rd_addr_gray[6]
-.sym 9317 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9318 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
-.sym 9319 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
-.sym 9320 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 9322 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 9323 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 9325 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 9327 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9329 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 9332 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
-.sym 9335 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9337 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
-.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 9342 rx_fifo.rd_addr[8]
-.sym 9346 rx_fifo.rd_addr[6]
-.sym 9347 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 9348 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 9349 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 9352 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
-.sym 9354 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
-.sym 9355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
-.sym 9358 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 9359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
-.sym 9360 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 9361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 9364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 9365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 9366 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 9367 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
-.sym 9373 rx_fifo.rd_addr_gray[6]
-.sym 9377 rx_fifo.rd_addr[6]
-.sym 9378 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 9382 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
-.sym 9383 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 9384 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9385 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 9387 lvds_clock_$glb_clk
-.sym 9389 rx_fifo.rd_addr_gray[4]
-.sym 9393 rx_fifo.rd_addr_gray[1]
+.sym 9266 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 9267 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
+.sym 9268 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
+.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
+.sym 9270 w_rx_fifo_full
+.sym 9271 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 9272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
+.sym 9273 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
+.sym 9290 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9291 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9293 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 9294 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 9295 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 9296 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 9297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 9301 rx_fifo.wr_addr_gray_rd[3]
+.sym 9307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 9308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9309 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 9310 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 9312 rx_fifo.rd_addr[1]
+.sym 9313 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9314 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9315 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
+.sym 9318 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 9319 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 9320 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 9321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 9322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
+.sym 9325 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 9326 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
+.sym 9327 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 9329 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 9331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 9334 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 9343 rx_fifo.rd_addr[1]
+.sym 9346 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
+.sym 9347 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 9348 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
+.sym 9349 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
+.sym 9352 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 9353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9354 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 9355 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9358 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9359 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 9360 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 9361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 9370 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 9371 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9372 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 9373 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 9376 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 9382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 9385 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9386 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 9387 r_counter_$glb_clk
+.sym 9388 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 9389 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.sym 9390 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
+.sym 9391 rx_fifo.rd_addr_gray[1]
+.sym 9392 rx_fifo.rd_addr_gray[6]
+.sym 9393 rx_fifo.rd_addr_gray[2]
 .sym 9394 rx_fifo.rd_addr_gray[7]
-.sym 9395 rx_fifo.rd_addr_gray[5]
-.sym 9396 rx_fifo.rd_addr_gray[2]
-.sym 9405 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 9407 w_load
-.sym 9408 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9410 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 9411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 9417 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 9418 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 9420 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 9421 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 9422 rx_fifo.wr_addr_gray_rd[2]
-.sym 9423 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 9424 rx_fifo.wr_addr_gray_rd[5]
-.sym 9441 rx_fifo.rd_addr[9]
-.sym 9443 rx_fifo.rd_addr_gray_wr[9]
-.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 9451 rx_fifo.rd_addr_gray[8]
-.sym 9453 rx_fifo.rd_addr_gray_wr[5]
-.sym 9454 rx_fifo.rd_addr_gray_wr[8]
-.sym 9459 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 9460 rx_fifo.rd_addr_gray[5]
-.sym 9461 rx_fifo.rd_addr_gray[2]
-.sym 9466 rx_fifo.rd_addr_gray[8]
-.sym 9469 rx_fifo.rd_addr_gray_wr[8]
-.sym 9477 rx_fifo.rd_addr_gray_wr[9]
-.sym 9484 rx_fifo.rd_addr_gray[2]
-.sym 9487 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 9488 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 9490 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 9494 rx_fifo.rd_addr[9]
-.sym 9500 rx_fifo.rd_addr_gray_wr[5]
-.sym 9505 rx_fifo.rd_addr_gray[5]
+.sym 9395 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
+.sym 9396 rx_fifo.rd_addr_gray[8]
+.sym 9404 $PACKER_VCC_NET
+.sym 9407 $PACKER_VCC_NET
+.sym 9409 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 9413 i_rst_b$SB_IO_IN
+.sym 9414 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9415 rx_fifo.wr_addr[9]
+.sym 9418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
+.sym 9420 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9423 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 9424 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 9430 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 9431 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9433 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 9434 rx_fifo.wr_addr[1]
+.sym 9436 rx_fifo.rd_addr[9]
+.sym 9442 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9443 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9454 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 9455 rx_fifo.rd_addr[5]
+.sym 9457 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 9463 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 9469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 9471 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 9472 rx_fifo.rd_addr[5]
+.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 9478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9481 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 9482 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 9483 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 9484 rx_fifo.rd_addr[9]
+.sym 9490 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 9506 rx_fifo.wr_addr[1]
+.sym 9509 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
 .sym 9510 lvds_clock_$glb_clk
-.sym 9512 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 9513 rx_fifo.rd_addr_gray_wr_r[0]
-.sym 9515 rx_fifo.rd_addr_gray_wr[0]
-.sym 9516 rx_fifo.rd_addr_gray_wr[1]
-.sym 9517 rx_fifo.rd_addr_gray_wr_r[1]
-.sym 9519 rx_fifo.rd_addr_gray_wr[7]
-.sym 9525 $PACKER_GND_NET
-.sym 9530 $PACKER_GND_NET
-.sym 9538 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9540 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 9541 rx_fifo.rd_addr_gray[0]
-.sym 9543 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 9544 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 9546 w_rx_24_fifo_data[1]
-.sym 9547 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 9557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 9558 w_lvds_rx_24_d0
-.sym 9561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 9562 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 9564 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 9565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 9567 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 9568 w_lvds_rx_24_d1
-.sym 9572 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 9592 w_lvds_rx_24_d0
-.sym 9598 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 9599 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 9604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 9606 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 9607 w_lvds_rx_24_d1
-.sym 9632 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 9633 lvds_clock_$glb_clk
-.sym 9635 rx_fifo.wr_addr_gray_rd[8]
-.sym 9636 rx_fifo.wr_addr_gray_rd[0]
-.sym 9637 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 9638 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 9639 rx_fifo.wr_addr_gray_rd[2]
-.sym 9640 rx_fifo.wr_addr_gray_rd[5]
-.sym 9642 rx_fifo.wr_addr_gray_rd[1]
-.sym 9669 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 9679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 9681 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 9683 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 9685 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 9688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 9689 rx_fifo.wr_addr[1]
-.sym 9693 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 9695 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 9703 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 9707 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 9712 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 9715 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 9722 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 9727 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 9729 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 9740 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 9741 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 9752 rx_fifo.wr_addr[1]
-.sym 9755 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 9756 lvds_clock_$glb_clk
-.sym 9757 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 9760 rx_fifo.rd_addr_gray[0]
-.sym 9801 rx_fifo.wr_addr_gray[6]
-.sym 9805 rx_fifo.wr_addr_gray_rd[6]
-.sym 9807 rx_fifo.wr_addr_gray_rd[7]
-.sym 9808 rx_fifo.wr_addr_gray[4]
-.sym 9809 rx_fifo.wr_addr_gray_rd[4]
-.sym 9814 rx_fifo.wr_addr_gray[7]
-.sym 9834 rx_fifo.wr_addr_gray[7]
-.sym 9839 rx_fifo.wr_addr_gray_rd[6]
-.sym 9846 rx_fifo.wr_addr_gray[4]
-.sym 9859 rx_fifo.wr_addr_gray_rd[4]
-.sym 9870 rx_fifo.wr_addr_gray[6]
-.sym 9876 rx_fifo.wr_addr_gray_rd[7]
-.sym 9879 r_counter_$glb_clk
-.sym 9926 rx_fifo.rd_addr_gray[3]
-.sym 9949 rx_fifo.rd_addr_gray_wr[3]
-.sym 9976 rx_fifo.rd_addr_gray[3]
-.sym 9988 rx_fifo.rd_addr_gray_wr[3]
-.sym 10002 lvds_clock_$glb_clk
-.sym 10004 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
-.sym 10018 o_shdn_rx_lna$SB_IO_OUT
+.sym 9511 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 9512 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 9513 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 9514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 9515 rx_fifo.wr_addr_gray_rd[9]
+.sym 9516 w_smi_read_req_SB_LUT4_I1_O[3]
+.sym 9517 rx_fifo.wr_addr_gray_rd[0]
+.sym 9518 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 9519 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 9528 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 9532 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 9539 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 9541 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 9542 rx_fifo.rd_addr_gray[7]
+.sym 9543 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 9546 rx_fifo.rd_addr_gray[8]
+.sym 9547 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9553 rx_fifo.wr_addr_gray[1]
+.sym 9557 rx_fifo.wr_addr_gray[5]
+.sym 9561 rx_fifo.wr_addr_gray_rd[4]
+.sym 9563 rx_fifo.wr_addr_gray[8]
+.sym 9565 rx_fifo.wr_addr_gray_rd[5]
+.sym 9567 rx_fifo.wr_addr_gray_rd[8]
+.sym 9592 rx_fifo.wr_addr_gray_rd[4]
+.sym 9601 rx_fifo.wr_addr_gray_rd[5]
+.sym 9604 rx_fifo.wr_addr_gray_rd[8]
+.sym 9612 rx_fifo.wr_addr_gray[5]
+.sym 9625 rx_fifo.wr_addr_gray[8]
+.sym 9629 rx_fifo.wr_addr_gray[1]
+.sym 9633 r_counter_$glb_clk
+.sym 9636 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
+.sym 9637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
+.sym 9639 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
+.sym 9640 rx_fifo.rd_addr_gray[4]
+.sym 9641 rx_fifo.rd_addr_gray[3]
+.sym 9660 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 9661 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 9669 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9676 rx_fifo.wr_addr_gray[2]
+.sym 9683 rx_fifo.wr_addr_gray[4]
+.sym 9685 rx_fifo.wr_addr_gray[3]
+.sym 9686 rx_fifo.wr_addr_gray_rd[2]
+.sym 9687 rx_fifo.wr_addr_gray[6]
+.sym 9689 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9691 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9710 rx_fifo.wr_addr_gray[4]
+.sym 9723 rx_fifo.wr_addr_gray[2]
+.sym 9730 rx_fifo.wr_addr_gray[6]
+.sym 9733 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9739 rx_fifo.wr_addr_gray_rd[2]
+.sym 9752 rx_fifo.wr_addr_gray[3]
+.sym 9756 r_counter_$glb_clk
+.sym 9758 rx_fifo.rd_addr_gray_wr[7]
+.sym 9759 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 9760 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 9761 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 9762 rx_fifo.rd_addr_gray_wr[8]
+.sym 9763 rx_fifo.rd_addr_gray_wr[4]
+.sym 9764 rx_fifo.rd_addr_gray_wr[3]
+.sym 9765 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 9778 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 9793 rx_fifo.wr_addr_gray_rd[3]
+.sym 9801 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 9805 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9811 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9815 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 9828 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9832 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 9834 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 9840 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9845 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 9853 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 9875 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 9878 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
+.sym 9879 lvds_clock_$glb_clk
+.sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 9881 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 9884 rx_fifo.wr_addr_gray_rd[7]
+.sym 9905 i_rst_b$SB_IO_IN
 .sym 10172 o_shdn_rx_lna$SB_IO_OUT
-.sym 10185 o_shdn_rx_lna$SB_IO_OUT
+.sym 10190 o_shdn_rx_lna$SB_IO_OUT
+.sym 10197 lvds_clock
+.sym 10198 o_shdn_rx_lna$SB_IO_OUT
 .sym 10201 w_smi_data_output[2]
 .sym 10203 w_smi_data_direction
 .sym 10204 w_smi_data_output[1]
 .sym 10206 w_smi_data_direction
 .sym 10207 $PACKER_VCC_NET
 .sym 10212 $PACKER_VCC_NET
-.sym 10214 w_smi_data_direction
-.sym 10217 w_smi_data_output[1]
-.sym 10222 w_smi_data_direction
+.sym 10213 w_smi_data_direction
+.sym 10215 w_smi_data_output[1]
+.sym 10221 w_smi_data_direction
 .sym 10225 w_smi_data_output[2]
-.sym 10226 tx_fifo.rd_addr[1]
-.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 10231 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 10233 w_smi_data_output[2]
-.sym 10270 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10271 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10272 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10277 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 10278 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 10283 tx_fifo.rd_addr[2]
-.sym 10295 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 10297 tx_fifo.rd_addr[0]
-.sym 10301 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10304 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10308 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 10310 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10313 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 10320 tx_fifo.rd_addr[2]
-.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10334 tx_fifo.rd_addr[0]
-.sym 10338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10346 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 10228 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10229 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10231 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 10233 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 10239 w_smi_data_output[1]
+.sym 10254 tx_fifo.rd_addr[4]
+.sym 10255 w_smi_data_output[2]
+.sym 10260 $PACKER_VCC_NET
+.sym 10261 w_smi_data_direction
+.sym 10279 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 10280 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 10284 tx_fifo.rd_addr[0]
+.sym 10291 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 10293 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 10294 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10295 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10301 tx_fifo.rd_addr[0]
+.sym 10307 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10313 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 10319 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10332 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10338 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 10343 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
 .sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
 .sym 10348 lvds_clock_$glb_clk
 .sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 10352 w_smi_data_input[7]
-.sym 10354 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
-.sym 10355 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
-.sym 10356 tx_fifo.empty_o_SB_LUT4_I1_O[3]
-.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 10358 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
-.sym 10359 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
-.sym 10360 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10361 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 10368 $PACKER_VCC_NET
-.sym 10370 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 10372 $PACKER_VCC_NET
-.sym 10373 tx_fifo.rd_addr[1]
-.sym 10379 w_smi_data_output[0]
-.sym 10392 $PACKER_VCC_NET
-.sym 10396 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
-.sym 10405 tx_fifo.empty_o_SB_LUT4_I1_O[3]
-.sym 10409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 10411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
-.sym 10412 w_smi_data_input[7]
-.sym 10414 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 10423 w_smi_data_output[7]
-.sym 10436 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 10439 tx_fifo.rd_addr[1]
-.sym 10440 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 10441 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 10444 tx_fifo.rd_addr[0]
-.sym 10445 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 10446 tx_fifo.rd_addr[2]
-.sym 10453 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 10463 $nextpnr_ICESTORM_LC_5$O
-.sym 10466 tx_fifo.rd_addr[0]
-.sym 10469 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10472 tx_fifo.rd_addr[1]
-.sym 10473 tx_fifo.rd_addr[0]
-.sym 10475 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10478 tx_fifo.rd_addr[2]
-.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10481 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10484 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 10485 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10487 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 10489 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 10491 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 10493 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
-.sym 10496 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 10497 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 10499 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 10502 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 10503 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
-.sym 10505 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 10507 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 10513 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 10514 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
-.sym 10515 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 10516 tx_fifo.empty_o_SB_LUT4_I1_O[2]
-.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 10518 w_tx_fifo_empty
-.sym 10519 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
-.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
-.sym 10537 w_smi_data_output[0]
-.sym 10538 tx_fifo.rd_addr[1]
-.sym 10540 smi_ctrl_ins.r_fifo_pulled_data[24]
-.sym 10543 w_smi_data_output[7]
-.sym 10546 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 10548 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 10549 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 10554 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
-.sym 10557 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 10558 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10560 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10561 tx_fifo.rd_addr[9]
-.sym 10564 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
-.sym 10565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 10566 tx_fifo.rd_addr_gray[4]
-.sym 10567 tx_fifo.rd_addr_gray[2]
-.sym 10568 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 10569 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 10571 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
-.sym 10577 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
-.sym 10581 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
-.sym 10584 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10586 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 10589 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 10590 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 10593 tx_fifo.rd_addr[9]
-.sym 10596 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 10600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 10601 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 10605 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 10606 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 10607 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 10608 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10611 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 10612 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10614 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
-.sym 10618 tx_fifo.rd_addr_gray[2]
-.sym 10623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
-.sym 10624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
-.sym 10625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
-.sym 10626 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
-.sym 10629 tx_fifo.rd_addr_gray[4]
-.sym 10634 r_counter_$glb_clk
-.sym 10636 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
-.sym 10637 w_smi_data_output[7]
-.sym 10638 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
-.sym 10639 w_smi_data_output[3]
-.sym 10640 w_smi_data_output[2]
-.sym 10641 w_smi_data_output[6]
-.sym 10642 w_smi_data_output[0]
-.sym 10643 w_smi_data_output[1]
-.sym 10650 tx_fifo.rd_addr_gray_wr[2]
-.sym 10656 rx_fifo.mem_i.0.0_WDATA_2
-.sym 10661 w_rx_fifo_pulled_data[18]
-.sym 10664 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10666 w_rx_fifo_pulled_data[19]
-.sym 10667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 10669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
-.sym 10670 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10677 smi_ctrl_ins.r_fifo_pulled_data[6]
-.sym 10678 smi_ctrl_ins.r_fifo_pulled_data[14]
-.sym 10679 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 10680 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 10685 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 10686 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 10687 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[8]
-.sym 10690 tx_fifo.rd_addr[9]
-.sym 10691 tx_fifo.rd_addr[1]
-.sym 10695 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10696 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10703 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10704 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 10355 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 10356 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
+.sym 10357 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10358 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 10359 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
+.sym 10360 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10361 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
+.sym 10366 tx_fifo.rd_addr[0]
+.sym 10370 i_rst_b_SB_LUT4_I3_O
+.sym 10394 w_smi_data_output[0]
+.sym 10403 tx_fifo.rd_addr[7]
+.sym 10405 tx_fifo.wr_addr_gray_rd[1]
+.sym 10406 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 10407 tx_fifo.rd_addr[2]
+.sym 10409 $PACKER_VCC_NET
+.sym 10410 w_smi_data_output[7]
+.sym 10415 w_smi_data_direction
+.sym 10418 tx_fifo.rd_addr[8]
+.sym 10420 smi_ctrl_ins.r_fifo_pulled_data[3]
+.sym 10432 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
+.sym 10433 i_rst_b_SB_LUT4_I3_O
+.sym 10434 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10435 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 10438 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 10441 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10442 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10450 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 10454 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
+.sym 10456 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 10457 i_rst_b$SB_IO_IN
+.sym 10458 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 10460 w_tx_fifo_pull
+.sym 10464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 10465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
+.sym 10466 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10471 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10472 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10473 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10478 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 10483 w_tx_fifo_pull
+.sym 10484 i_rst_b$SB_IO_IN
+.sym 10488 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10490 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 10496 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 10501 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 10502 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 10503 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
+.sym 10507 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10508 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10510 i_rst_b_SB_LUT4_I3_O
+.sym 10511 lvds_clock_$glb_clk
+.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 10513 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 10514 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 10515 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
+.sym 10516 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 10518 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 10519 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
+.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 10526 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10528 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10529 tx_fifo.rd_addr[6]
+.sym 10539 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10542 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 10544 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10545 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10548 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 10554 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
+.sym 10555 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 10556 tx_fifo.rd_addr[3]
+.sym 10557 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
+.sym 10560 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10561 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
+.sym 10562 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
+.sym 10564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 10565 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10567 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
+.sym 10568 tx_fifo.rd_addr[7]
+.sym 10569 tx_fifo.rd_addr[7]
+.sym 10571 tx_fifo.wr_addr_gray_rd[1]
+.sym 10572 tx_fifo.rd_addr[4]
+.sym 10573 tx_fifo.rd_addr[2]
+.sym 10575 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
+.sym 10577 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
+.sym 10578 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
+.sym 10579 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 10580 smi_ctrl_ins.r_fifo_pulled_data[11]
+.sym 10582 smi_ctrl_ins.r_fifo_pulled_data[23]
+.sym 10583 tx_fifo.rd_addr[6]
+.sym 10584 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10585 smi_ctrl_ins.r_fifo_pulled_data[3]
+.sym 10587 tx_fifo.rd_addr[3]
+.sym 10588 tx_fifo.rd_addr[2]
+.sym 10590 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10593 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
+.sym 10594 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
+.sym 10595 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
+.sym 10596 tx_fifo.rd_addr[4]
+.sym 10599 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10600 smi_ctrl_ins.r_fifo_pulled_data[11]
+.sym 10601 smi_ctrl_ins.r_fifo_pulled_data[3]
+.sym 10602 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10605 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
+.sym 10606 tx_fifo.rd_addr[7]
+.sym 10607 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
+.sym 10608 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
+.sym 10611 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10612 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 10613 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10614 smi_ctrl_ins.r_fifo_pulled_data[23]
+.sym 10617 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
+.sym 10618 tx_fifo.rd_addr[6]
+.sym 10619 tx_fifo.rd_addr[7]
+.sym 10620 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 10623 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 10624 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
+.sym 10626 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 10629 tx_fifo.wr_addr_gray_rd[1]
+.sym 10634 lvds_clock_$glb_clk
+.sym 10636 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
+.sym 10638 tx_fifo.rd_addr_gray[8]
+.sym 10640 tx_fifo.rd_addr[8]
+.sym 10641 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
+.sym 10642 tx_fifo.rd_addr_gray[4]
+.sym 10643 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
+.sym 10647 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 10648 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 10649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 10651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 10652 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.sym 10653 rx_fifo.wr_addr[3]
+.sym 10654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.sym 10659 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 10661 w_smi_read_req
+.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 10665 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 10666 w_smi_data_output[0]
+.sym 10669 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 10670 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10671 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 10679 i_rst_b$SB_IO_IN
+.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
+.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
+.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
+.sym 10685 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 10686 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
+.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[12]
+.sym 10689 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
+.sym 10691 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
+.sym 10692 smi_ctrl_ins.r_fifo_pulled_data[22]
+.sym 10699 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10700 smi_ctrl_ins.r_fifo_pulled_data[4]
 .sym 10705 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 10713 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 10716 tx_fifo.rd_addr[1]
-.sym 10722 smi_ctrl_ins.r_fifo_pulled_data[8]
-.sym 10723 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 10725 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10729 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 10730 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[6]
-.sym 10735 smi_ctrl_ins.r_fifo_pulled_data[14]
+.sym 10706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
+.sym 10707 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
+.sym 10710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
+.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
+.sym 10716 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
+.sym 10718 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
+.sym 10724 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
+.sym 10725 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
+.sym 10729 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10730 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[22]
+.sym 10735 smi_ctrl_ins.int_cnt_rx[4]
 .sym 10736 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10737 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10743 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 10746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 10747 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 10748 tx_fifo.rd_addr[9]
-.sym 10749 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10754 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 10756 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 10757 lvds_clock_$glb_clk
-.sym 10758 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 10759 tx_fifo.wr_addr_gray_rd[7]
-.sym 10760 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
-.sym 10761 tx_fifo.wr_addr_gray_rd[8]
-.sym 10762 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 10763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 10764 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 10765 tx_fifo.wr_addr_gray_rd[1]
-.sym 10766 tx_fifo.wr_addr_gray_rd[5]
-.sym 10772 rx_fifo.rd_addr[6]
-.sym 10775 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 10776 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 10780 rx_fifo.rd_addr[0]
-.sym 10782 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 10783 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
-.sym 10793 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 10801 w_rx_fifo_pulled_data[4]
-.sym 10802 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10805 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10806 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 10807 w_rx_fifo_pulled_data[6]
-.sym 10808 smi_ctrl_ins.r_fifo_pulled_data[11]
-.sym 10809 smi_ctrl_ins.r_fifo_pulled_data[27]
-.sym 10810 smi_ctrl_ins.r_fifo_pulled_data[19]
-.sym 10813 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[26]
-.sym 10821 w_rx_fifo_pulled_data[18]
-.sym 10826 w_rx_fifo_pulled_data[19]
-.sym 10828 smi_ctrl_ins.r_fifo_pulled_data[3]
-.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[18]
-.sym 10830 smi_ctrl_ins.r_fifo_pulled_data[4]
-.sym 10836 w_rx_fifo_pulled_data[6]
-.sym 10839 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10840 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10841 smi_ctrl_ins.r_fifo_pulled_data[4]
-.sym 10842 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 10848 w_rx_fifo_pulled_data[19]
-.sym 10851 smi_ctrl_ins.r_fifo_pulled_data[19]
-.sym 10852 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10853 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10854 smi_ctrl_ins.r_fifo_pulled_data[27]
-.sym 10857 smi_ctrl_ins.r_fifo_pulled_data[18]
-.sym 10858 smi_ctrl_ins.r_fifo_pulled_data[26]
-.sym 10859 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10860 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10865 w_rx_fifo_pulled_data[18]
-.sym 10870 w_rx_fifo_pulled_data[4]
-.sym 10875 smi_ctrl_ins.r_fifo_pulled_data[11]
-.sym 10876 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10877 smi_ctrl_ins.r_fifo_pulled_data[3]
-.sym 10878 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 10880 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 10737 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 10740 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
+.sym 10741 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
+.sym 10746 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10747 smi_ctrl_ins.r_fifo_pulled_data[4]
+.sym 10748 smi_ctrl_ins.r_fifo_pulled_data[12]
+.sym 10749 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10756 i_rst_b$SB_IO_IN
+.sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 10759 tx_fifo.wr_addr_gray_rd[6]
+.sym 10760 tx_fifo.wr_addr_gray_rd[8]
+.sym 10761 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 10762 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 10763 tx_fifo.wr_addr_gray_rd[4]
+.sym 10764 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 10765 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 10766 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 10770 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 10771 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 10772 tx_fifo.rd_addr_gray[4]
+.sym 10775 rx_fifo.rd_addr[0]
+.sym 10779 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 10780 rx_fifo.mem_q.0.3_WDATA_1
+.sym 10783 tx_fifo.wr_addr_gray_rd[1]
+.sym 10790 w_smi_data_output[5]
+.sym 10803 smi_ctrl_ins.w_fifo_pull_trigger
+.sym 10811 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[21]
+.sym 10815 smi_ctrl_ins.r_fifo_pull_1
+.sym 10816 smi_ctrl_ins.r_fifo_pull
+.sym 10817 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10821 w_smi_read_req
+.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 10834 smi_ctrl_ins.w_fifo_pull_trigger
+.sym 10851 w_smi_read_req
+.sym 10852 smi_ctrl_ins.r_fifo_pull_1
+.sym 10854 smi_ctrl_ins.r_fifo_pull
+.sym 10869 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 10870 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10871 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10872 smi_ctrl_ins.r_fifo_pulled_data[21]
+.sym 10878 smi_ctrl_ins.r_fifo_pull
+.sym 10880 r_counter_$glb_clk
 .sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 10883 tx_fifo.wr_addr_gray_rd[0]
-.sym 10885 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 10886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
-.sym 10888 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
-.sym 10889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
-.sym 10891 w_rx_fifo_pulled_data[4]
-.sym 10898 $PACKER_VCC_NET
-.sym 10899 o_smi_read_req$SB_IO_OUT
-.sym 10904 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 10908 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10910 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 10912 rx_fifo.rd_addr[3]
-.sym 10916 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
-.sym 10941 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10952 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10968 smi_ctrl_ins.int_cnt_rx[3]
-.sym 10970 smi_ctrl_ins.int_cnt_rx[4]
-.sym 10989 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10884 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 10888 tx_fifo.wr_addr_gray_rd[1]
+.sym 10894 rx_fifo.wr_addr[0]
+.sym 10895 rx_fifo.wr_addr[3]
+.sym 10897 rx_fifo.wr_addr[9]
+.sym 10904 rx_fifo.wr_addr[5]
+.sym 10906 rx_fifo.rd_addr[1]
+.sym 10907 $PACKER_VCC_NET
+.sym 10909 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 10910 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 10911 smi_ctrl_ins.r_fifo_pulled_data[1]
+.sym 10912 w_smi_data_direction
+.sym 10916 rx_fifo.rd_addr[2]
+.sym 10926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
+.sym 10927 smi_ctrl_ins.r_fifo_pulled_data[9]
+.sym 10928 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10933 smi_ctrl_ins.r_fifo_pulled_data[17]
+.sym 10934 smi_ctrl_ins.r_fifo_pulled_data[25]
+.sym 10935 smi_ctrl_ins.r_fifo_pulled_data[1]
+.sym 10938 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10941 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 10942 i_rst_b$SB_IO_IN
+.sym 10945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
+.sym 10947 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
+.sym 10950 i_rst_b$SB_IO_IN
+.sym 10951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
+.sym 10956 smi_ctrl_ins.r_fifo_pulled_data[9]
+.sym 10957 smi_ctrl_ins.int_cnt_rx[3]
+.sym 10958 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10959 smi_ctrl_ins.r_fifo_pulled_data[1]
+.sym 10962 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
+.sym 10965 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
+.sym 10968 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 10969 i_rst_b$SB_IO_IN
+.sym 10974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
+.sym 10976 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
+.sym 10992 smi_ctrl_ins.int_cnt_rx[4]
+.sym 10993 smi_ctrl_ins.r_fifo_pulled_data[17]
+.sym 10994 smi_ctrl_ins.r_fifo_pulled_data[25]
+.sym 10995 smi_ctrl_ins.int_cnt_rx[3]
+.sym 11002 i_rst_b$SB_IO_IN
 .sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 11004 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 11010 smi_ctrl_ins.r_fifo_pulled_data[22]
-.sym 11011 smi_ctrl_ins.r_fifo_pulled_data[23]
-.sym 11019 smi_ctrl_ins.int_cnt_rx[3]
-.sym 11023 smi_ctrl_ins.int_cnt_rx[4]
-.sym 11024 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 11028 rx_fifo.rd_addr[8]
-.sym 11030 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 11038 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 11048 rx_fifo.rd_addr[6]
-.sym 11049 rx_fifo.rd_addr[3]
-.sym 11054 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 11056 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 11057 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11058 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 11060 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 11061 rx_fifo.rd_addr[0]
-.sym 11078 $nextpnr_ICESTORM_LC_8$O
+.sym 11005 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11006 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11008 rx_fifo.rd_addr[2]
+.sym 11009 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11010 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11011 rx_fifo.rd_addr[1]
+.sym 11018 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 11030 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 11032 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11035 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11039 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11040 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11062 rx_fifo.rd_addr[0]
+.sym 11063 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11066 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11068 rx_fifo.rd_addr[1]
+.sym 11070 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11073 rx_fifo.rd_addr[2]
+.sym 11074 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 11075 rx_fifo.rd_addr[5]
+.sym 11078 $nextpnr_ICESTORM_LC_3$O
 .sym 11081 rx_fifo.rd_addr[0]
 .sym 11084 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 11086 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 11086 rx_fifo.rd_addr[1]
 .sym 11088 rx_fifo.rd_addr[0]
 .sym 11090 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
-.sym 11092 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
+.sym 11093 rx_fifo.rd_addr[2]
 .sym 11094 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
 .sym 11096 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
-.sym 11099 rx_fifo.rd_addr[3]
+.sym 11099 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
 .sym 11100 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
-.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
-.sym 11104 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
+.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 11105 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
 .sym 11106 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
-.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
-.sym 11111 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
-.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 11117 rx_fifo.rd_addr[6]
-.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
-.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 11123 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 11128 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11132 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
-.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 11144 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 11146 rx_fifo.wr_addr[6]
-.sym 11147 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11154 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 11157 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 11163 rx_fifo.wr_addr_gray_rd[1]
-.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 11170 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 11172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11179 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11181 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
+.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11110 rx_fifo.rd_addr[5]
+.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11116 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11123 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11129 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11130 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 11131 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11132 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11133 spi_if_ins.r_tx_data_valid
+.sym 11134 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 11135 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11143 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 11149 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11152 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 11153 w_smi_read_req
+.sym 11154 rx_fifo.rd_addr[2]
+.sym 11156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 11158 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 11159 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11160 rx_fifo.rd_addr[1]
+.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11170 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 11171 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
+.sym 11172 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 11173 w_rx_data[0]
+.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11176 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 11180 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 11181 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11182 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11185 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11187 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
 .sym 11190 rx_fifo.rd_addr[9]
-.sym 11193 rx_fifo.rd_addr[8]
-.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 11203 rx_fifo.rd_addr[8]
-.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 11208 rx_fifo.rd_addr[9]
-.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 11222 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 11227 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 11228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 11239 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 11244 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 11246 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
+.sym 11198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11204 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11210 rx_fifo.rd_addr[9]
+.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 11214 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11223 w_rx_data[0]
+.sym 11227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 11228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 11229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11238 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 11239 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11240 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
+.sym 11241 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 11245 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11246 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 11248 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
 .sym 11249 r_counter_$glb_clk
 .sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 11251 w_rx_fifo_empty
-.sym 11256 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
-.sym 11258 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
-.sym 11265 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 11266 rx_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 11267 rx_fifo.rd_addr[6]
-.sym 11269 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11270 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 11271 rx_fifo.rd_addr[3]
-.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11273 w_rx_data[0]
-.sym 11278 rx_fifo.rd_addr[3]
-.sym 11280 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 11292 rx_fifo.wr_addr_gray_rd[2]
-.sym 11293 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 11295 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 11296 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 11298 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
-.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11304 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 11306 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 11308 rx_fifo.wr_addr_gray[3]
-.sym 11312 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11315 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 11316 rx_fifo.wr_addr_gray_rd[3]
-.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 11318 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 11319 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
-.sym 11322 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
-.sym 11325 rx_fifo.wr_addr_gray[3]
-.sym 11331 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 11332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 11333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
-.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 11340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11343 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 11344 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 11349 rx_fifo.wr_addr_gray_rd[2]
-.sym 11357 rx_fifo.wr_addr_gray_rd[3]
-.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
-.sym 11369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11251 spi_if_ins.state_if[0]
+.sym 11252 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 11253 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 11254 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 11255 spi_if_ins.state_if[1]
+.sym 11256 spi_if_ins.state_if_SB_DFFESR_Q_E
+.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 11258 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 11263 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 11264 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 11265 $PACKER_VCC_NET
+.sym 11267 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11269 w_rx_data[0]
+.sym 11271 w_smi_data_direction
+.sym 11272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11274 rx_fifo.rd_addr[0]
+.sym 11276 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 11277 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11279 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11282 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 11286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 11292 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 11293 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
+.sym 11294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 11295 i_sck$SB_IO_IN
+.sym 11296 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 11299 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
+.sym 11303 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 11305 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 11308 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11315 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 11318 spi_if_ins.spi.SCKr[0]
+.sym 11320 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 11322 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11323 rx_fifo.wr_addr_gray_rd[3]
+.sym 11325 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 11326 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 11331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
+.sym 11332 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 11333 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 11334 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 11340 i_sck$SB_IO_IN
+.sym 11346 rx_fifo.wr_addr_gray_rd[3]
+.sym 11351 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 11357 spi_if_ins.spi.SCKr[0]
+.sym 11361 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 11362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
+.sym 11364 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 11370 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
 .sym 11372 r_counter_$glb_clk
-.sym 11374 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
-.sym 11375 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
-.sym 11376 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
-.sym 11377 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
-.sym 11378 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
-.sym 11379 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 11380 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 11392 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 11396 rx_fifo.wr_addr_gray_rd[2]
-.sym 11407 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
-.sym 11415 w_rx_fifo_empty
-.sym 11417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11418 rx_fifo.wr_addr_gray_rd[9]
-.sym 11420 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 11422 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
-.sym 11425 rx_fifo.empty_o_SB_LUT4_I0_O[3]
-.sym 11426 rx_fifo.empty_o_SB_LUT4_I0_O[2]
-.sym 11427 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 11428 rx_fifo.empty_o_SB_LUT4_I0_O[1]
-.sym 11431 rx_fifo.rd_addr[8]
-.sym 11432 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 11433 rx_fifo.wr_addr_gray_rd[1]
-.sym 11434 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 11438 rx_fifo.empty_o_SB_LUT4_I0_O[0]
-.sym 11441 i_rst_b$SB_IO_IN
-.sym 11442 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 11444 rx_fifo.rd_addr[9]
-.sym 11446 rx_fifo.wr_addr_gray_rd[5]
-.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 11451 i_rst_b$SB_IO_IN
-.sym 11455 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11457 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 11460 rx_fifo.wr_addr_gray_rd[5]
-.sym 11468 rx_fifo.wr_addr_gray_rd[9]
-.sym 11472 rx_fifo.empty_o_SB_LUT4_I0_O[2]
-.sym 11473 rx_fifo.empty_o_SB_LUT4_I0_O[3]
-.sym 11474 rx_fifo.empty_o_SB_LUT4_I0_O[1]
-.sym 11475 rx_fifo.empty_o_SB_LUT4_I0_O[0]
-.sym 11478 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
-.sym 11479 w_rx_fifo_empty
-.sym 11480 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 11481 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 11484 rx_fifo.wr_addr_gray_rd[1]
-.sym 11490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 11491 rx_fifo.rd_addr[9]
-.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 11493 rx_fifo.rd_addr[8]
-.sym 11495 r_counter_$glb_clk
-.sym 11497 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
-.sym 11498 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
-.sym 11499 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
-.sym 11500 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11501 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
-.sym 11502 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11503 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
-.sym 11504 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 11509 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11510 w_cs[0]
-.sym 11514 rx_fifo.wr_addr_gray_rd[9]
-.sym 11516 w_rx_data[1]
-.sym 11517 w_rx_data[4]
-.sym 11522 w_rx_fifo_empty
-.sym 11530 w_rx_data[3]
-.sym 11540 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11541 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 11548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 11550 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11574 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 11598 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 11604 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 11610 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 11614 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
+.sym 11374 w_smi_read_req
+.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 11379 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 11380 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 11386 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 11390 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 11396 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 11398 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 11406 rx_fifo.rd_addr[1]
+.sym 11407 w_smi_read_req
+.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
+.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11419 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11420 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 11423 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 11424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11426 rx_fifo.rd_addr[2]
+.sym 11427 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 11428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 11430 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 11432 rx_fifo.rd_addr[1]
+.sym 11434 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 11436 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11438 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 11439 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11440 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
+.sym 11442 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 11443 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 11444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 11446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 11448 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11449 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 11450 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 11451 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 11454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 11457 rx_fifo.rd_addr[2]
+.sym 11460 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 11461 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 11462 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 11463 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 11466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 11468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 11469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
+.sym 11473 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
+.sym 11474 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 11475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 11478 rx_fifo.rd_addr[1]
+.sym 11479 rx_fifo.rd_addr[2]
+.sym 11480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 11484 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11487 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11491 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 11495 lvds_clock_$glb_clk
+.sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 11497 rx_fifo.rd_addr_gray_wr[2]
+.sym 11498 rx_fifo.rd_addr_gray_wr[6]
+.sym 11501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 11502 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 11504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 11514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 11515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 11522 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 11523 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 11524 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11526 w_rx_fifo_full
+.sym 11528 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11532 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11538 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 11539 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 11541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 11543 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
+.sym 11545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 11548 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
+.sym 11550 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11551 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11558 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 11560 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
+.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 11566 rx_fifo.rd_addr[1]
+.sym 11568 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
+.sym 11571 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
+.sym 11572 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
+.sym 11573 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
+.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 11577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 11578 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 11579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
+.sym 11584 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 11589 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 11595 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 11601 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 11607 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 11608 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 11609 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11610 rx_fifo.rd_addr[1]
+.sym 11613 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 11616 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
 .sym 11618 r_counter_$glb_clk
 .sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 11620 w_tx_data_smi[1]
-.sym 11622 w_tx_data_smi[2]
-.sym 11624 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.sym 11625 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
-.sym 11635 w_ioc[1]
-.sym 11636 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 11642 w_cs[0]
-.sym 11643 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 11645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 11646 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 11647 rx_fifo.wr_addr_gray_rd[1]
-.sym 11653 w_ioc[0]
-.sym 11672 rx_fifo.rd_addr_gray_wr[0]
-.sym 11673 rx_fifo.rd_addr_gray[1]
-.sym 11674 rx_fifo.rd_addr_gray[7]
-.sym 11681 rx_fifo.rd_addr_gray_wr[1]
-.sym 11684 rx_fifo.rd_addr_gray_wr[7]
-.sym 11689 rx_fifo.rd_addr_gray[0]
-.sym 11695 rx_fifo.rd_addr_gray_wr[7]
-.sym 11703 rx_fifo.rd_addr_gray_wr[0]
-.sym 11714 rx_fifo.rd_addr_gray[0]
-.sym 11721 rx_fifo.rd_addr_gray[1]
-.sym 11725 rx_fifo.rd_addr_gray_wr[1]
-.sym 11739 rx_fifo.rd_addr_gray[7]
-.sym 11741 lvds_clock_$glb_clk
-.sym 11746 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 11747 o_led0_SB_LUT4_I1_O[1]
-.sym 11748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
-.sym 11750 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 11751 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 11773 o_shdn_rx_lna$SB_IO_OUT
-.sym 11784 rx_fifo.wr_addr_gray_rd[8]
-.sym 11792 rx_fifo.wr_addr_gray[5]
-.sym 11795 rx_fifo.wr_addr_gray[2]
-.sym 11796 rx_fifo.wr_addr_gray[1]
-.sym 11797 rx_fifo.wr_addr_gray[8]
-.sym 11799 rx_fifo.wr_addr_gray[0]
-.sym 11801 rx_fifo.wr_addr_gray_rd[0]
-.sym 11817 rx_fifo.wr_addr_gray[8]
-.sym 11826 rx_fifo.wr_addr_gray[0]
-.sym 11831 rx_fifo.wr_addr_gray_rd[8]
-.sym 11835 rx_fifo.wr_addr_gray_rd[0]
-.sym 11843 rx_fifo.wr_addr_gray[2]
-.sym 11849 rx_fifo.wr_addr_gray[5]
-.sym 11861 rx_fifo.wr_addr_gray[1]
+.sym 11620 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 11622 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 11624 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 11626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
+.sym 11628 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 11637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 11645 rx_fifo.rd_addr_gray[1]
+.sym 11651 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11653 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 11654 rx_fifo.rd_addr_gray_wr[1]
+.sym 11655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 11664 rx_fifo.wr_addr_gray_rd[9]
+.sym 11666 rx_fifo.wr_addr_gray_rd[0]
+.sym 11668 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 11670 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 11673 w_smi_read_req_SB_LUT4_I1_O[3]
+.sym 11676 rx_fifo.wr_addr_gray_rd[1]
+.sym 11677 w_smi_read_req
+.sym 11678 w_smi_read_req_SB_LUT4_I1_I3[3]
+.sym 11680 rx_fifo.wr_addr_gray_rd[6]
+.sym 11682 rx_fifo.wr_addr[9]
+.sym 11684 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11688 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11690 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 11692 rx_fifo.wr_addr_gray[0]
+.sym 11697 rx_fifo.wr_addr_gray_rd[9]
+.sym 11702 rx_fifo.wr_addr_gray_rd[0]
+.sym 11707 rx_fifo.wr_addr_gray_rd[6]
+.sym 11712 rx_fifo.wr_addr[9]
+.sym 11718 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 11719 w_smi_read_req_SB_LUT4_I1_I3[3]
+.sym 11720 w_smi_read_req
+.sym 11721 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 11727 rx_fifo.wr_addr_gray[0]
+.sym 11732 rx_fifo.wr_addr_gray_rd[1]
+.sym 11736 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 11737 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 11738 w_smi_read_req_SB_LUT4_I1_O[3]
+.sym 11739 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 11741 r_counter_$glb_clk
+.sym 11746 rx_fifo.rd_addr_gray_wr[1]
+.sym 11756 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 11761 w_rx_data[0]
+.sym 11774 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 11786 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 11787 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 11788 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11791 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 11792 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 11795 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 11799 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 11803 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11804 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
+.sym 11809 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
+.sym 11811 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11823 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 11826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
+.sym 11830 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 11831 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
+.sym 11832 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 11841 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 11843 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 11849 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 11855 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 11863 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
 .sym 11864 r_counter_$glb_clk
-.sym 11866 io_ctrl_ins.o_pmod[0]
-.sym 11868 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
-.sym 11869 io_ctrl_ins.o_pmod[3]
-.sym 11870 io_ctrl_ins.o_pmod[2]
-.sym 11871 o_led1_SB_LUT4_I1_O[2]
-.sym 11872 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
-.sym 11873 io_ctrl_ins.o_pmod[1]
-.sym 11881 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 11883 w_load
-.sym 11885 w_fetch
-.sym 11896 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
-.sym 11912 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11918 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11955 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 11986 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 11987 r_counter_$glb_clk
-.sym 11988 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 11990 o_led0_SB_LUT4_I1_O[0]
-.sym 11992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 11993 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 11995 o_led1_SB_LUT4_I1_O[0]
-.sym 11996 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 12001 o_shdn_tx_lna$SB_IO_OUT
-.sym 12006 w_rx_data[1]
-.sym 12023 w_rx_data[3]
-.sym 12125 w_rx_data[1]
-.sym 12127 w_rx_data[3]
-.sym 12133 w_rx_data[4]
-.sym 12183 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 12187 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
+.sym 11865 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 11867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 11871 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 11884 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 11912 rx_fifo.rd_addr_gray_wr[4]
+.sym 11915 rx_fifo.rd_addr_gray_wr[7]
+.sym 11918 rx_fifo.rd_addr_gray[8]
+.sym 11920 rx_fifo.rd_addr_gray[4]
+.sym 11921 rx_fifo.rd_addr_gray[3]
+.sym 11922 rx_fifo.rd_addr_gray[7]
+.sym 11929 rx_fifo.rd_addr_gray_wr[3]
+.sym 11935 rx_fifo.rd_addr_gray_wr[8]
+.sym 11940 rx_fifo.rd_addr_gray[7]
+.sym 11946 rx_fifo.rd_addr_gray_wr[8]
+.sym 11955 rx_fifo.rd_addr_gray_wr[4]
+.sym 11960 rx_fifo.rd_addr_gray_wr[7]
+.sym 11966 rx_fifo.rd_addr_gray[8]
+.sym 11971 rx_fifo.rd_addr_gray[4]
+.sym 11977 rx_fifo.rd_addr_gray[3]
+.sym 11983 rx_fifo.rd_addr_gray_wr[3]
+.sym 11987 lvds_clock_$glb_clk
+.sym 11993 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 12010 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 12048 rx_fifo.wr_addr_gray[7]
+.sym 12049 rx_fifo.wr_addr_gray_rd[7]
+.sym 12066 rx_fifo.wr_addr_gray_rd[7]
+.sym 12084 rx_fifo.wr_addr_gray[7]
+.sym 12110 r_counter_$glb_clk
+.sym 12113 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .sym 12305 i_rst_b$SB_IO_IN
-.sym 12307 o_shdn_tx_lna$SB_IO_OUT
 .sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
 .sym 12310 w_smi_data_output[0]
 .sym 12312 w_smi_data_direction
 .sym 12313 w_smi_data_output[7]
 .sym 12315 w_smi_data_direction
 .sym 12316 $PACKER_VCC_NET
-.sym 12320 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
 .sym 12321 w_smi_data_direction
-.sym 12326 w_smi_data_output[7]
-.sym 12328 w_smi_data_output[0]
+.sym 12324 $PACKER_VCC_NET
+.sym 12326 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
 .sym 12329 w_smi_data_direction
-.sym 12332 $PACKER_VCC_NET
-.sym 12335 tx_fifo.wr_addr_gray_rd[2]
-.sym 12336 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 12337 w_smi_data_direction
-.sym 12338 tx_fifo.wr_addr_gray_rd[3]
-.sym 12339 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12340 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 12341 tx_fifo.wr_addr_gray_rd[6]
-.sym 12342 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
-.sym 12368 $PACKER_VCC_NET
+.sym 12333 w_smi_data_output[7]
+.sym 12334 w_smi_data_output[0]
+.sym 12335 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 12336 tx_fifo.wr_addr_gray_rd[9]
+.sym 12337 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12338 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12339 tx_fifo.wr_addr_gray_rd[3]
+.sym 12340 i_rst_b_SB_LUT4_I3_O
+.sym 12341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 12342 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
 .sym 12369 w_smi_data_input[7]
-.sym 12385 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 12389 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 12394 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 12397 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12398 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 12404 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 12405 w_smi_data_output[2]
-.sym 12406 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 12407 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 12411 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 12418 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 12434 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12435 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 12436 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 12437 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 12440 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 12447 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 12454 w_smi_data_output[2]
-.sym 12456 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 12457 lvds_clock_$glb_clk
-.sym 12458 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 12464 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 12465 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
-.sym 12466 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 12467 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 12468 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
-.sym 12469 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 12470 w_tx_fifo_pull
-.sym 12475 tx_fifo.rd_addr[1]
-.sym 12481 w_smi_data_input[7]
-.sym 12492 w_smi_data_output[4]
-.sym 12498 w_smi_data_output[6]
-.sym 12507 w_tx_fifo_pull
-.sym 12509 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 12512 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 12513 i_rst_b_SB_LUT4_I3_O
-.sym 12516 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 12524 w_smi_data_output[3]
-.sym 12525 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12526 w_smi_data_output[2]
-.sym 12527 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 12540 tx_fifo.rd_addr[1]
-.sym 12541 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
-.sym 12544 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12545 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12546 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 12547 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 12549 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 12553 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 12554 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 12555 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
-.sym 12557 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-.sym 12558 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 12563 tx_fifo.rd_addr[2]
-.sym 12564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 12565 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 12566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 12567 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 12568 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 12570 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 12571 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 12573 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 12574 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
-.sym 12575 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
-.sym 12576 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 12579 tx_fifo.rd_addr[2]
-.sym 12580 tx_fifo.rd_addr[1]
-.sym 12581 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-.sym 12585 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12586 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 12587 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 12594 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 12598 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 12603 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 12604 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 12605 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 12609 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 12611 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 12612 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12615 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 12616 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
-.sym 12617 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 12618 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 12623 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-.sym 12624 tx_fifo.wr_addr_gray_rd[9]
-.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 12626 i_rst_b_SB_LUT4_I3_O
-.sym 12627 tx_fifo.wr_addr_gray_rd[4]
-.sym 12628 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12639 $PACKER_VCC_NET
-.sym 12645 $PACKER_VCC_NET
-.sym 12648 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
-.sym 12649 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 12650 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
-.sym 12652 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 12654 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
-.sym 12666 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12667 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 12669 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
-.sym 12670 w_tx_fifo_pull
-.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12672 tx_fifo.empty_o_SB_LUT4_I1_O[3]
-.sym 12673 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
-.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12675 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
-.sym 12676 w_tx_fifo_empty
-.sym 12677 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12678 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 12682 tx_fifo.empty_o_SB_LUT4_I1_O[2]
-.sym 12685 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12686 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
-.sym 12687 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 12688 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 12689 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 12690 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 12692 tx_fifo.rd_addr[9]
-.sym 12694 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 12696 tx_fifo.empty_o_SB_LUT4_I1_O[3]
-.sym 12697 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 12698 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 12699 tx_fifo.empty_o_SB_LUT4_I1_O[2]
-.sym 12702 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 12703 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12704 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 12705 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 12709 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 12710 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12711 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
-.sym 12714 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12715 tx_fifo.rd_addr[9]
-.sym 12716 w_tx_fifo_pull
-.sym 12717 w_tx_fifo_empty
-.sym 12722 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12726 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 12727 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-.sym 12728 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
-.sym 12729 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.sym 12732 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12733 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 12735 w_tx_fifo_pull
-.sym 12738 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
-.sym 12739 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
-.sym 12741 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.sym 12379 tx_fifo.rd_addr[1]
+.sym 12382 tx_fifo.rd_addr[3]
+.sym 12385 tx_fifo.rd_addr[0]
+.sym 12386 tx_fifo.rd_addr[2]
+.sym 12388 tx_fifo.rd_addr[4]
+.sym 12390 tx_fifo.rd_addr[0]
+.sym 12392 tx_fifo.rd_addr[7]
+.sym 12399 tx_fifo.rd_addr[5]
+.sym 12406 tx_fifo.rd_addr[6]
+.sym 12409 $nextpnr_ICESTORM_LC_7$O
+.sym 12411 tx_fifo.rd_addr[0]
+.sym 12415 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
+.sym 12417 tx_fifo.rd_addr[1]
+.sym 12419 tx_fifo.rd_addr[0]
+.sym 12421 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 12424 tx_fifo.rd_addr[2]
+.sym 12425 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
+.sym 12427 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 12430 tx_fifo.rd_addr[3]
+.sym 12431 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 12433 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
+.sym 12436 tx_fifo.rd_addr[4]
+.sym 12437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 12439 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 12441 tx_fifo.rd_addr[5]
+.sym 12443 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
+.sym 12445 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12448 tx_fifo.rd_addr[6]
+.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 12451 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12453 tx_fifo.rd_addr[7]
+.sym 12455 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
+.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12465 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 12466 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12467 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 12468 tx_fifo.rd_addr[6]
+.sym 12469 tx_fifo.rd_addr[5]
+.sym 12470 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
+.sym 12477 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 12489 $PACKER_VCC_NET
+.sym 12502 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12504 smi_ctrl_ins.int_cnt_rx[4]
+.sym 12511 w_smi_data_output[3]
+.sym 12513 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 12515 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12516 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12517 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12518 i_ss$SB_IO_IN
+.sym 12519 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12522 smi_ctrl_ins.int_cnt_rx[4]
+.sym 12526 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12529 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12535 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12540 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12543 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 12550 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12551 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12553 w_tx_fifo_pull
+.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12557 tx_fifo.rd_addr[2]
+.sym 12559 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 12561 tx_fifo.rd_addr[3]
+.sym 12562 smi_ctrl_ins.int_cnt_rx[4]
+.sym 12564 tx_fifo.rd_addr[8]
+.sym 12565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 12567 tx_fifo.rd_addr[4]
+.sym 12569 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12572 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12574 tx_fifo.rd_addr[8]
+.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12580 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12582 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 12585 w_tx_fifo_pull
+.sym 12586 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 12587 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12588 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12592 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12603 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 12604 tx_fifo.rd_addr[4]
+.sym 12605 tx_fifo.rd_addr[2]
+.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 12609 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12611 smi_ctrl_ins.int_cnt_rx[4]
+.sym 12615 tx_fifo.rd_addr[3]
+.sym 12616 tx_fifo.rd_addr[4]
+.sym 12618 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 12620 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 12622 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
+.sym 12623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.sym 12624 tx_fifo.rd_addr_gray[1]
+.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 12626 tx_fifo.rd_addr_gray[7]
+.sym 12627 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 12629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
+.sym 12639 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 12643 rx_fifo.mem_q.0.3_WDATA_2
+.sym 12647 tx_fifo.wr_addr[1]
+.sym 12648 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 12649 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12650 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 12654 tx_fifo.rd_addr[5]
+.sym 12655 tx_fifo.wr_addr_gray_rd[3]
+.sym 12657 $PACKER_VCC_NET
+.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
+.sym 12667 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 12669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 12670 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12672 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12673 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
+.sym 12675 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 12676 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
+.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
+.sym 12678 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 12682 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
+.sym 12683 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12684 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 12688 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 12689 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 12690 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 12691 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 12692 w_tx_fifo_pull
+.sym 12693 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.sym 12697 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
+.sym 12698 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
+.sym 12699 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
+.sym 12702 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 12705 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12708 w_tx_fifo_pull
+.sym 12709 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12710 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12714 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 12715 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 12716 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 12717 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 12721 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12726 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 12727 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 12728 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 12729 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 12732 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
+.sym 12733 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 12734 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
+.sym 12735 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 12738 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.sym 12739 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 12740 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
 .sym 12743 lvds_clock_$glb_clk
 .sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 12745 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
-.sym 12747 tx_fifo.rd_addr_gray[3]
-.sym 12748 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
-.sym 12749 tx_fifo.rd_addr_gray[6]
-.sym 12750 tx_fifo.rd_addr_gray[5]
-.sym 12751 tx_fifo.rd_addr_gray[7]
-.sym 12752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.sym 12758 $PACKER_VCC_NET
-.sym 12762 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12763 w_smi_data_output[5]
-.sym 12764 rx_fifo.mem_i.0.0_WDATA_3
-.sym 12769 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 12770 tx_fifo.wr_addr_gray_rd[1]
-.sym 12771 w_smi_data_output[6]
-.sym 12772 i_rst_b$SB_IO_IN
-.sym 12773 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12774 w_smi_data_output[4]
-.sym 12775 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 12777 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 12778 smi_ctrl_ins.r_fifo_pulled_data[15]
-.sym 12779 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 12788 i_rst_b$SB_IO_IN
-.sym 12793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12794 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
-.sym 12795 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
-.sym 12796 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
-.sym 12797 smi_ctrl_ins.int_cnt_rx[3]
-.sym 12798 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
-.sym 12799 tx_fifo.rd_addr[1]
-.sym 12801 smi_ctrl_ins.r_fifo_pulled_data[24]
-.sym 12802 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
-.sym 12805 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
-.sym 12806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
-.sym 12807 smi_ctrl_ins.int_cnt_rx[4]
-.sym 12808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
-.sym 12809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
-.sym 12810 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
-.sym 12811 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 12812 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 12813 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
-.sym 12816 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 12817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
-.sym 12819 smi_ctrl_ins.int_cnt_rx[3]
-.sym 12820 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 12821 smi_ctrl_ins.r_fifo_pulled_data[24]
-.sym 12822 smi_ctrl_ins.int_cnt_rx[4]
-.sym 12826 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
-.sym 12828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
-.sym 12831 tx_fifo.rd_addr[1]
-.sym 12832 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 12833 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 12834 tx_fifo.empty_o_SB_LUT4_I1_O[0]
-.sym 12837 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
-.sym 12838 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
-.sym 12843 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
-.sym 12845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
-.sym 12849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
-.sym 12851 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
-.sym 12856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
-.sym 12858 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
-.sym 12861 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
-.sym 12862 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
-.sym 12865 i_rst_b$SB_IO_IN
-.sym 12866 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 12868 tx_fifo.wr_addr_gray[8]
-.sym 12869 tx_fifo.wr_addr_gray[5]
-.sym 12870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
-.sym 12871 tx_fifo.wr_addr_gray[1]
-.sym 12872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
-.sym 12873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
-.sym 12874 tx_fifo.wr_addr_gray[7]
-.sym 12875 tx_fifo.wr_addr_gray[0]
-.sym 12880 rx_fifo.mem_i.0.0_WDATA_1
-.sym 12881 rx_fifo.wr_addr[6]
-.sym 12883 rx_fifo.wr_addr[4]
-.sym 12885 smi_ctrl_ins.int_cnt_rx[3]
-.sym 12886 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 12889 rx_fifo.rd_addr[3]
-.sym 12890 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 12895 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
-.sym 12903 i_rst_b$SB_IO_IN
-.sym 12909 tx_fifo.wr_addr_gray_rd[7]
-.sym 12916 tx_fifo.wr_addr_gray_rd[5]
-.sym 12925 tx_fifo.wr_addr_gray[8]
-.sym 12927 smi_ctrl_ins.int_cnt_rx[4]
-.sym 12929 smi_ctrl_ins.r_fifo_pulled_data[25]
-.sym 12930 smi_ctrl_ins.int_cnt_rx[3]
-.sym 12934 tx_fifo.wr_addr_gray[5]
-.sym 12935 tx_fifo.wr_addr_gray_rd[8]
-.sym 12936 tx_fifo.wr_addr_gray[1]
-.sym 12937 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 12939 tx_fifo.wr_addr_gray[7]
-.sym 12945 tx_fifo.wr_addr_gray[7]
-.sym 12948 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 12949 smi_ctrl_ins.int_cnt_rx[4]
-.sym 12950 smi_ctrl_ins.int_cnt_rx[3]
-.sym 12951 smi_ctrl_ins.r_fifo_pulled_data[25]
-.sym 12954 tx_fifo.wr_addr_gray[8]
-.sym 12960 tx_fifo.wr_addr_gray_rd[8]
-.sym 12966 tx_fifo.wr_addr_gray_rd[7]
-.sym 12972 tx_fifo.wr_addr_gray_rd[5]
-.sym 12978 tx_fifo.wr_addr_gray[1]
-.sym 12987 tx_fifo.wr_addr_gray[5]
+.sym 12745 tx_fifo.full_o_SB_LUT4_I1_O[2]
+.sym 12746 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
+.sym 12747 tx_fifo.wr_addr_gray[6]
+.sym 12748 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
+.sym 12750 tx_fifo.wr_addr_gray[4]
+.sym 12759 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 12760 w_smi_data_output[5]
+.sym 12769 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 12770 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 12772 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 12777 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 12779 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 12780 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 12790 tx_fifo.rd_addr[8]
+.sym 12791 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12793 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 12795 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12798 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 12799 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 12800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 12803 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12804 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12813 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 12814 tx_fifo.rd_addr[5]
+.sym 12820 tx_fifo.rd_addr[5]
+.sym 12822 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 12834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 12844 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 12849 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 12850 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 12851 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 12852 tx_fifo.rd_addr[8]
+.sym 12857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 12862 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 12864 tx_fifo.rd_addr[8]
+.sym 12865 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 12866 lvds_clock_$glb_clk
+.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 12868 tx_fifo.wr_addr_gray[1]
+.sym 12869 tx_fifo.wr_addr_gray[0]
+.sym 12870 tx_fifo.wr_addr_gray[8]
+.sym 12871 tx_fifo.wr_addr_gray[2]
+.sym 12872 tx_fifo.wr_addr_gray[5]
+.sym 12875 tx_fifo.wr_addr_gray[7]
+.sym 12884 rx_fifo.mem_q.0.3_WDATA
+.sym 12886 tx_fifo.rd_addr_gray[8]
+.sym 12889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 12892 rx_fifo.wr_addr[8]
+.sym 12894 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 12895 i_rst_b$SB_IO_IN
+.sym 12898 rx_fifo.rd_addr[2]
+.sym 12900 rx_fifo.wr_addr[0]
+.sym 12911 tx_fifo.wr_addr_gray[6]
+.sym 12913 tx_fifo.wr_addr_gray_rd[4]
+.sym 12922 tx_fifo.wr_addr_gray[4]
+.sym 12925 tx_fifo.wr_addr_gray_rd[3]
+.sym 12926 tx_fifo.wr_addr_gray_rd[8]
+.sym 12927 tx_fifo.wr_addr_gray[8]
+.sym 12939 tx_fifo.wr_addr_gray_rd[7]
+.sym 12940 tx_fifo.wr_addr_gray_rd[2]
+.sym 12944 tx_fifo.wr_addr_gray[6]
+.sym 12949 tx_fifo.wr_addr_gray[8]
+.sym 12956 tx_fifo.wr_addr_gray_rd[3]
+.sym 12963 tx_fifo.wr_addr_gray_rd[2]
+.sym 12966 tx_fifo.wr_addr_gray[4]
+.sym 12972 tx_fifo.wr_addr_gray_rd[7]
+.sym 12981 tx_fifo.wr_addr_gray_rd[8]
+.sym 12987 tx_fifo.wr_addr_gray_rd[4]
 .sym 12989 lvds_clock_$glb_clk
-.sym 12991 smi_ctrl_ins.w_fifo_pull_trigger
-.sym 12993 w_smi_data_output[4]
-.sym 12996 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
-.sym 12998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 13003 rx_fifo.wr_addr[0]
-.sym 13004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 13008 rx_fifo.mem_q.0.1_WDATA_3
-.sym 13009 rx_fifo.mem_q.0.1_WDATA_2
-.sym 13010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 13011 rx_fifo.wr_addr[4]
-.sym 13014 rx_fifo.wr_addr[6]
-.sym 13021 w_rx_fifo_pulled_data[31]
-.sym 13026 w_rx_fifo_pulled_data[23]
-.sym 13034 smi_ctrl_ins.int_cnt_rx[4]
-.sym 13037 smi_ctrl_ins.r_fifo_pulled_data[22]
-.sym 13039 tx_fifo.wr_addr_gray[0]
-.sym 13042 smi_ctrl_ins.int_cnt_rx[4]
-.sym 13045 smi_ctrl_ins.int_cnt_rx[3]
-.sym 13046 smi_ctrl_ins.r_fifo_pulled_data[23]
-.sym 13049 tx_fifo.wr_addr_gray_rd[0]
-.sym 13056 smi_ctrl_ins.r_fifo_pulled_data[30]
-.sym 13057 smi_ctrl_ins.r_fifo_pulled_data[31]
-.sym 13063 i_rst_b$SB_IO_IN
-.sym 13071 tx_fifo.wr_addr_gray[0]
-.sym 13083 tx_fifo.wr_addr_gray_rd[0]
-.sym 13089 smi_ctrl_ins.int_cnt_rx[3]
-.sym 13090 smi_ctrl_ins.int_cnt_rx[4]
-.sym 13091 smi_ctrl_ins.r_fifo_pulled_data[31]
-.sym 13092 smi_ctrl_ins.r_fifo_pulled_data[23]
-.sym 13101 i_rst_b$SB_IO_IN
-.sym 13102 smi_ctrl_ins.int_cnt_rx[4]
-.sym 13103 smi_ctrl_ins.int_cnt_rx[3]
-.sym 13107 smi_ctrl_ins.r_fifo_pulled_data[30]
-.sym 13108 smi_ctrl_ins.int_cnt_rx[4]
-.sym 13109 smi_ctrl_ins.r_fifo_pulled_data[22]
-.sym 13110 smi_ctrl_ins.int_cnt_rx[3]
+.sym 12991 tx_fifo.wr_addr_gray_rd[0]
+.sym 12993 tx_fifo.wr_addr_gray_rd[5]
+.sym 12996 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 12997 tx_fifo.wr_addr_gray_rd[7]
+.sym 12998 tx_fifo.wr_addr_gray_rd[2]
+.sym 13005 rx_fifo.mem_i.0.0_WDATA_1
+.sym 13007 rx_fifo.wr_addr[6]
+.sym 13011 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 13012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 13013 rx_fifo.mem_i.0.3_WDATA_1
+.sym 13016 rx_fifo.rd_addr[1]
+.sym 13018 $PACKER_VCC_NET
+.sym 13019 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 13020 rx_fifo.wr_addr[1]
+.sym 13022 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 13024 i_ss$SB_IO_IN
+.sym 13026 rx_fifo.rd_addr[2]
+.sym 13032 tx_fifo.wr_addr_gray_rd[6]
+.sym 13040 tx_fifo.wr_addr_gray[1]
+.sym 13048 tx_fifo.wr_addr_gray_rd[0]
+.sym 13079 tx_fifo.wr_addr_gray_rd[6]
+.sym 13089 tx_fifo.wr_addr_gray_rd[0]
+.sym 13102 tx_fifo.wr_addr_gray[1]
 .sym 13112 lvds_clock_$glb_clk
-.sym 13114 smi_ctrl_ins.r_fifo_pulled_data[30]
-.sym 13115 smi_ctrl_ins.r_fifo_pulled_data[31]
-.sym 13117 smi_ctrl_ins.r_fifo_pulled_data[28]
-.sym 13118 smi_ctrl_ins.r_fifo_pulled_data[29]
-.sym 13122 io_pmod[7]$SB_IO_IN
-.sym 13125 io_pmod[7]$SB_IO_IN
-.sym 13128 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 13129 rx_fifo.mem_q.0.1_WDATA
-.sym 13130 w_rx_fifo_pulled_data[19]
-.sym 13131 rx_fifo.wr_addr[7]
-.sym 13133 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 13134 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 13135 w_rx_fifo_pulled_data[18]
-.sym 13136 rx_fifo.mem_q.0.1_WDATA_1
-.sym 13138 w_rx_fifo_empty
-.sym 13141 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 13142 rx_fifo.rd_addr[8]
-.sym 13145 i_rst_b$SB_IO_IN
-.sym 13147 i_rst_b$SB_IO_IN
-.sym 13178 w_rx_fifo_pulled_data[22]
-.sym 13186 w_rx_fifo_pulled_data[23]
-.sym 13218 w_rx_fifo_pulled_data[22]
-.sym 13226 w_rx_fifo_pulled_data[23]
-.sym 13234 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 13235 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 13116 tx_fifo.rd_addr_gray[0]
+.sym 13122 io_pmod_in[3]$SB_IO_IN
+.sym 13125 io_pmod_in[3]$SB_IO_IN
+.sym 13128 rx_fifo.mem_i.0.3_WDATA
+.sym 13131 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 13132 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 13133 w_smi_read_req
+.sym 13138 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 13140 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 13142 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 13144 $PACKER_VCC_NET
+.sym 13146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 13147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13159 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 13164 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 13165 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 13166 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 13170 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 13173 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 13179 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 13190 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 13197 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 13206 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 13214 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 13218 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 13226 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 13234 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
+.sym 13235 r_counter_$glb_clk
 .sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13237 w_rx_data[0]
-.sym 13240 w_rx_data[5]
-.sym 13242 w_rx_data[2]
-.sym 13243 i_rst_b$SB_IO_IN
-.sym 13249 rx_fifo.wr_addr[9]
-.sym 13251 rx_fifo.mem_i.0.3_WDATA
-.sym 13253 rx_fifo.rd_addr[3]
-.sym 13255 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 13256 $PACKER_VCC_NET
-.sym 13257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 13258 rx_fifo.mem_i.0.3_WDATA_2
-.sym 13259 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 13260 rx_fifo.wr_addr[7]
-.sym 13261 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
-.sym 13266 w_rx_fifo_empty
-.sym 13269 w_tx_fifo_full
-.sym 13270 w_rx_data[0]
-.sym 13271 i_rst_b$SB_IO_IN
-.sym 13289 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
-.sym 13294 w_rx_data[0]
-.sym 13299 w_rx_data[2]
+.sym 13238 $PACKER_VCC_NET
+.sym 13239 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 13240 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 13241 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 13242 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
+.sym 13244 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 13245 io_pmod_in[2]$SB_IO_IN
+.sym 13248 io_pmod_in[2]$SB_IO_IN
+.sym 13249 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 13251 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 13253 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 13257 rx_fifo.rd_addr[2]
+.sym 13258 w_rx_fifo_pulled_data[18]
+.sym 13259 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 13260 rx_fifo.mem_i.0.3_WDATA_3
+.sym 13264 rx_fifo.rd_addr[2]
+.sym 13265 i_rst_b$SB_IO_IN
+.sym 13267 rx_fifo.rd_addr[9]
+.sym 13268 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 13270 rx_fifo.rd_addr[1]
+.sym 13272 $PACKER_VCC_NET
+.sym 13280 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13288 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 13289 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 13291 spi_if_ins.r_tx_data_valid
+.sym 13294 i_ss$SB_IO_IN
+.sym 13298 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13299 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 13301 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 13303 w_smi_read_req_SB_LUT4_I1_I3[2]
 .sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 13312 w_rx_data[2]
-.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
+.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 13307 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
 .sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 13337 w_rx_data[0]
-.sym 13353 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 13357 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 13320 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 13323 spi_if_ins.r_tx_data_valid
+.sym 13325 i_ss$SB_IO_IN
+.sym 13329 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 13331 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 13335 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 13336 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 13342 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 13348 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 13350 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 13355 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 13356 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 13357 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
 .sym 13358 r_counter_$glb_clk
-.sym 13359 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13361 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 13362 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 13363 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 13364 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
-.sym 13365 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 13368 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 13372 rx_fifo.wr_addr[5]
-.sym 13373 rx_fifo.wr_addr[1]
-.sym 13374 rx_fifo.wr_addr[3]
-.sym 13376 rx_fifo.wr_addr[8]
-.sym 13382 rx_fifo.wr_addr[2]
-.sym 13383 spi_if_ins.state_if_SB_DFFESR_Q_E
-.sym 13385 w_fetch
-.sym 13388 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 13359 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 13361 w_smi_read_req
+.sym 13363 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
+.sym 13364 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13366 w_fetch
+.sym 13367 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
+.sym 13378 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 13379 o_led0_SB_LUT4_I1_O[1]
+.sym 13381 $PACKER_VCC_NET
+.sym 13382 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 13388 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 13389 w_cs[2]
 .sym 13390 w_rx_data[2]
-.sym 13408 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 13410 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
-.sym 13413 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 13414 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 13416 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
-.sym 13419 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 13420 rx_fifo.rd_addr[3]
-.sym 13421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 13422 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
-.sym 13427 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 13429 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
-.sym 13434 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
-.sym 13435 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
-.sym 13436 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
-.sym 13437 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
-.sym 13464 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
-.sym 13465 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 13466 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 13467 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 13476 rx_fifo.rd_addr[3]
-.sym 13477 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 13478 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 13391 i_rst_b$SB_IO_IN
+.sym 13392 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E
+.sym 13404 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 13405 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 13407 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 13408 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 13409 spi_if_ins.state_if[0]
+.sym 13411 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 13413 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13416 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13417 i_rst_b$SB_IO_IN
+.sym 13420 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 13421 spi_if_ins.state_if[1]
+.sym 13424 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 13425 i_rst_b$SB_IO_IN
+.sym 13427 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13431 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 13437 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 13440 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 13442 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 13446 spi_if_ins.state_if[1]
+.sym 13448 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13449 spi_if_ins.state_if[0]
+.sym 13452 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13453 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13454 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 13455 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 13459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 13460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13461 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 13464 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13465 i_rst_b$SB_IO_IN
+.sym 13466 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 13467 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 13470 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13471 i_rst_b$SB_IO_IN
+.sym 13476 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E
 .sym 13481 r_counter_$glb_clk
 .sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13483 w_cs[3]
-.sym 13484 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 13485 w_cs[1]
-.sym 13486 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 13487 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 13488 w_cs[2]
-.sym 13495 w_rx_fifo_empty
-.sym 13499 w_rx_data[3]
-.sym 13500 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 13502 rx_fifo.rd_addr[9]
-.sym 13509 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 13511 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
-.sym 13513 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 13524 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13526 w_ioc[0]
-.sym 13527 w_rx_data[4]
-.sym 13528 w_cs[0]
-.sym 13530 w_ioc[1]
-.sym 13532 w_rx_data[1]
-.sym 13534 w_ioc[1]
-.sym 13540 w_rx_data[0]
-.sym 13542 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 13543 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
-.sym 13545 w_fetch
-.sym 13550 w_rx_data[2]
-.sym 13552 w_load
-.sym 13557 w_ioc[1]
-.sym 13559 w_ioc[0]
-.sym 13560 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
-.sym 13565 w_rx_data[1]
-.sym 13571 w_rx_data[0]
-.sym 13575 w_fetch
-.sym 13576 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13577 w_load
-.sym 13578 w_cs[0]
-.sym 13582 w_rx_data[2]
-.sym 13587 w_ioc[1]
-.sym 13589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
-.sym 13590 w_ioc[0]
-.sym 13594 w_rx_data[4]
-.sym 13603 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 13483 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 13484 w_rx_data[2]
+.sym 13485 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 13486 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 13488 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 13489 w_rx_data[6]
+.sym 13490 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
+.sym 13496 w_fetch
+.sym 13497 spi_if_ins.state_if_SB_DFFESR_Q_E
+.sym 13499 rx_fifo.wr_addr[6]
+.sym 13507 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 13509 spi_if_ins.r_tx_byte[7]
+.sym 13510 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 13518 w_rx_data[2]
+.sym 13524 spi_if_ins.state_if[0]
+.sym 13526 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 13531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
+.sym 13532 spi_if_ins.state_if[0]
+.sym 13535 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
+.sym 13536 spi_if_ins.state_if[1]
+.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13538 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 13539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13541 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 13544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.sym 13549 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
+.sym 13557 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
+.sym 13558 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.sym 13559 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
+.sym 13560 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
+.sym 13563 spi_if_ins.state_if[0]
+.sym 13564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13565 spi_if_ins.state_if[1]
+.sym 13569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13571 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13576 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13581 spi_if_ins.state_if[0]
+.sym 13584 spi_if_ins.state_if[1]
+.sym 13587 spi_if_ins.state_if[1]
+.sym 13588 spi_if_ins.state_if[0]
+.sym 13590 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 13594 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 13599 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 13600 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 13602 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
 .sym 13604 r_counter_$glb_clk
 .sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13606 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
-.sym 13607 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 13608 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 13609 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 13610 r_tx_data[0]
-.sym 13611 r_tx_data[2]
-.sym 13612 r_tx_data[1]
-.sym 13613 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
-.sym 13619 io_pmod[0]$SB_IO_IN
-.sym 13620 w_ioc[1]
-.sym 13621 $PACKER_VCC_NET
-.sym 13622 w_ioc[0]
-.sym 13626 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 13628 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13630 w_cs[1]
-.sym 13631 w_tx_data_io[2]
-.sym 13632 i_rst_b$SB_IO_IN
-.sym 13633 w_load
-.sym 13634 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 13636 w_cs[2]
+.sym 13606 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 13607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
+.sym 13608 w_cs[0]
+.sym 13611 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 13612 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 13613 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 13618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 13619 w_rx_data[6]
+.sym 13620 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 13621 spi_if_ins.w_rx_data[6]
+.sym 13627 rx_fifo.rd_addr[9]
+.sym 13628 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 13629 spi_if_ins.w_rx_data[2]
+.sym 13633 spi_if_ins.r_tx_byte[7]
+.sym 13634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
 .sym 13637 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 13639 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 13647 w_tx_data_smi[1]
-.sym 13648 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 13649 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 13651 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
-.sym 13652 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 13653 w_ioc[1]
-.sym 13654 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 13655 w_fetch
-.sym 13656 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
-.sym 13657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
-.sym 13659 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13660 w_cs[0]
-.sym 13661 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
-.sym 13662 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 13666 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 13668 w_ioc[0]
-.sym 13674 w_tx_data_io[1]
-.sym 13680 w_tx_data_smi[1]
-.sym 13681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 13682 w_tx_data_io[1]
-.sym 13683 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 13686 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 13687 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0]
-.sym 13694 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
-.sym 13695 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 13698 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 13705 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 13707 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
-.sym 13710 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
-.sym 13712 w_fetch
-.sym 13713 w_cs[0]
-.sym 13716 w_ioc[1]
-.sym 13717 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13718 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 13719 w_ioc[0]
-.sym 13722 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13724 w_ioc[0]
-.sym 13725 w_ioc[1]
-.sym 13726 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 13727 r_counter_$glb_clk
-.sym 13728 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
-.sym 13730 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
-.sym 13731 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
-.sym 13732 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
-.sym 13733 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
-.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
-.sym 13735 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 13743 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 13744 $PACKER_VCC_NET
-.sym 13747 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 13753 w_ioc[1]
-.sym 13757 w_tx_fifo_full
-.sym 13758 w_rx_data[0]
-.sym 13759 io_ctrl_ins.o_pmod[3]
-.sym 13760 w_tx_data_io[1]
-.sym 13761 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
-.sym 13762 i_rst_b$SB_IO_IN
-.sym 13763 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 13770 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 13774 o_led0_SB_LUT4_I1_O[1]
-.sym 13775 w_tx_fifo_full
-.sym 13781 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 13783 w_rx_fifo_empty
-.sym 13789 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.sym 13804 w_tx_fifo_full
-.sym 13817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 13830 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.sym 13836 w_rx_fifo_empty
-.sym 13849 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 13640 i_rst_b$SB_IO_IN
+.sym 13647 rx_fifo.rd_addr_gray_wr[2]
+.sym 13651 rx_fifo.rd_addr_gray[2]
+.sym 13658 rx_fifo.rd_addr_gray[6]
+.sym 13664 rx_fifo.rd_addr_gray_wr[6]
+.sym 13677 rx_fifo.rd_addr_gray_wr[1]
+.sym 13680 rx_fifo.rd_addr_gray[2]
+.sym 13689 rx_fifo.rd_addr_gray[6]
+.sym 13704 rx_fifo.rd_addr_gray_wr[2]
+.sym 13712 rx_fifo.rd_addr_gray_wr[1]
+.sym 13724 rx_fifo.rd_addr_gray_wr[6]
+.sym 13727 lvds_clock_$glb_clk
+.sym 13729 w_tx_data_io[7]
+.sym 13730 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 13731 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 13732 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
+.sym 13733 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 13735 i_button_SB_LUT4_I0_I3[3]
+.sym 13736 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
+.sym 13748 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 13751 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 13752 w_cs[0]
+.sym 13757 i_rst_b$SB_IO_IN
+.sym 13760 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 13761 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 13772 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 13776 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 13777 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 13779 w_rx_data[0]
+.sym 13783 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 13788 w_rx_data[2]
+.sym 13805 w_rx_data[2]
+.sym 13817 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 13827 w_rx_data[0]
+.sym 13840 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 13841 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 13849 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
 .sym 13850 r_counter_$glb_clk
-.sym 13851 o_led0_SB_LUT4_I1_O[1]
-.sym 13852 w_tx_data_io[2]
-.sym 13853 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
-.sym 13854 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
-.sym 13855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.sym 13856 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 13857 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
-.sym 13858 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 13859 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 13867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
-.sym 13874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 13877 i_rst_b$SB_IO_IN
-.sym 13878 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
-.sym 13881 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 13882 w_rx_data[2]
-.sym 13887 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
-.sym 13897 o_led0_SB_LUT4_I1_O[1]
-.sym 13898 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 13901 w_fetch
-.sym 13902 w_cs[1]
-.sym 13904 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 13906 w_ioc[0]
-.sym 13907 w_load
-.sym 13909 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 13913 w_ioc[1]
-.sym 13920 io_pmod[7]$SB_IO_IN
-.sym 13921 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
-.sym 13922 i_rst_b$SB_IO_IN
-.sym 13944 w_load
-.sym 13945 w_cs[1]
-.sym 13946 w_fetch
-.sym 13947 i_rst_b$SB_IO_IN
-.sym 13950 w_ioc[1]
-.sym 13952 w_ioc[0]
-.sym 13953 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 13956 w_load
-.sym 13957 o_led0_SB_LUT4_I1_O[1]
-.sym 13958 w_fetch
-.sym 13959 w_cs[1]
-.sym 13968 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
-.sym 13969 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 13971 io_pmod[7]$SB_IO_IN
-.sym 13972 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 13852 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.sym 13853 w_tx_data_io[5]
+.sym 13854 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
+.sym 13856 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 13857 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
+.sym 13858 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
+.sym 13859 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+.sym 13871 w_cs[2]
+.sym 13872 w_cs[1]
+.sym 13878 i_rst_b$SB_IO_IN
+.sym 13880 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 13881 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 13882 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 13883 w_cs[3]
+.sym 13885 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 13887 w_rx_data[2]
+.sym 13898 rx_fifo.rd_addr_gray[1]
+.sym 13944 rx_fifo.rd_addr_gray[1]
 .sym 13973 lvds_clock_$glb_clk
-.sym 13974 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 13975 o_led0_SB_LUT4_I1_O[2]
-.sym 13976 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
-.sym 13978 w_tx_data_io[1]
-.sym 13979 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-.sym 13980 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
-.sym 13981 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
-.sym 13982 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
-.sym 13992 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 13995 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 14000 w_rx_data[0]
-.sym 14002 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 14016 w_ioc[0]
-.sym 14018 o_shdn_rx_lna$SB_IO_OUT
-.sym 14019 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 14021 o_shdn_tx_lna$SB_IO_OUT
-.sym 14022 w_rx_data[1]
-.sym 14023 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 14028 w_rx_data[0]
-.sym 14031 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 14034 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
-.sym 14039 io_ctrl_ins.o_pmod[1]
-.sym 14042 w_rx_data[2]
-.sym 14044 io_ctrl_ins.o_pmod[2]
-.sym 14046 w_rx_data[3]
-.sym 14052 w_rx_data[0]
-.sym 14061 w_ioc[0]
-.sym 14062 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 14063 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 14069 w_rx_data[3]
-.sym 14074 w_rx_data[2]
-.sym 14079 io_ctrl_ins.o_pmod[1]
-.sym 14080 w_ioc[0]
-.sym 14081 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 14082 o_shdn_rx_lna$SB_IO_OUT
-.sym 14085 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 14086 o_shdn_tx_lna$SB_IO_OUT
-.sym 14087 w_ioc[0]
-.sym 14088 io_ctrl_ins.o_pmod[2]
-.sym 14092 w_rx_data[1]
-.sym 14095 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
-.sym 14096 r_counter_$glb_clk
-.sym 14098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
-.sym 14099 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 14100 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 14101 w_smi_data_direction
-.sym 14102 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
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-.sym 14111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
-.sym 14119 i_config[0]$SB_IO_IN
-.sym 14121 o_led0_SB_LUT4_I1_O[3]
-.sym 14123 i_rst_b$SB_IO_IN
-.sym 14141 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
-.sym 14145 w_rx_data[3]
-.sym 14149 w_rx_data[4]
-.sym 14151 w_rx_data[1]
-.sym 14154 w_rx_data[2]
-.sym 14160 w_rx_data[0]
-.sym 14178 w_rx_data[0]
-.sym 14190 w_rx_data[4]
-.sym 14196 w_rx_data[3]
-.sym 14209 w_rx_data[1]
-.sym 14217 w_rx_data[2]
-.sym 14218 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
-.sym 14219 r_counter_$glb_clk
+.sym 13975 r_tx_data[2]
+.sym 13980 r_tx_data[0]
+.sym 13982 r_tx_data[7]
+.sym 13988 i_button_SB_LUT4_I0_I3[1]
+.sym 13991 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 13993 w_rx_fifo_full
+.sym 13994 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 13995 w_tx_data_io[2]
+.sym 13999 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 14001 spi_if_ins.r_tx_byte[7]
+.sym 14003 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 14006 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
+.sym 14008 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
+.sym 14018 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 14024 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 14025 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 14035 io_pmod_in[2]$SB_IO_IN
+.sym 14042 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 14043 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 14057 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 14058 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 14079 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 14080 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 14081 io_pmod_in[2]$SB_IO_IN
+.sym 14095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 14096 lvds_clock_$glb_clk
+.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 14098 spi_if_ins.r_tx_byte[2]
+.sym 14101 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 14102 spi_if_ins.r_tx_byte[0]
+.sym 14105 spi_if_ins.r_tx_byte[7]
+.sym 14107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
+.sym 14111 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 14112 o_shdn_tx_lna$SB_IO_OUT
+.sym 14114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 14118 o_tr_vc1$SB_IO_OUT
+.sym 14119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 14129 spi_if_ins.r_tx_byte[7]
+.sym 14131 i_rst_b$SB_IO_IN
+.sym 14150 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 14151 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 14159 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 14162 io_pmod_in[3]$SB_IO_IN
+.sym 14197 io_pmod_in[3]$SB_IO_IN
+.sym 14198 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 14199 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 14218 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 14219 lvds_clock_$glb_clk
 .sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 14223 r_counter
-.sym 14236 w_smi_data_direction
-.sym 14237 o_shdn_rx_lna$SB_IO_OUT
-.sym 14239 o_tr_vc1$SB_IO_OUT
-.sym 14241 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 14243 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 14248 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
+.sym 14222 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
+.sym 14223 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 14224 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
+.sym 14225 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
+.sym 14226 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 14227 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
 .sym 14249 i_rst_b$SB_IO_IN
+.sym 14276 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 14301 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
 .sym 14344 i_rst_b$SB_IO_IN
-.sym 14359 i_glob_clock$SB_IO_IN
+.sym 14360 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
 .sym 14365 i_rst_b$SB_IO_IN
-.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
-.sym 14406 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.sym 14399 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .sym 14418 i_rst_b_SB_LUT4_I3_O
 .sym 14419 w_smi_data_output[3]
 .sym 14421 w_smi_data_direction
 .sym 14425 $PACKER_VCC_NET
-.sym 14430 w_smi_data_output[3]
-.sym 14436 i_rst_b_SB_LUT4_I3_O
-.sym 14438 w_smi_data_direction
-.sym 14441 $PACKER_VCC_NET
-.sym 14445 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 14454 w_smi_data_direction
-.sym 14456 i_rst_b_SB_LUT4_I3_O
-.sym 14457 smi_ctrl_ins.r_fifo_pulled_data[20]
-.sym 14474 i_rst_b$SB_IO_IN
-.sym 14478 w_smi_data_output[4]
-.sym 14489 tx_fifo.wr_addr_gray_rd[3]
-.sym 14504 tx_fifo.wr_addr_gray[6]
-.sym 14505 tx_fifo.wr_addr_gray[2]
-.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 14510 tx_fifo.wr_addr_gray_rd[2]
-.sym 14512 w_smi_data_direction
-.sym 14513 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14514 tx_fifo.wr_addr_gray[3]
-.sym 14516 tx_fifo.wr_addr_gray_rd[6]
-.sym 14522 tx_fifo.wr_addr_gray[2]
-.sym 14526 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14528 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 14534 w_smi_data_direction
-.sym 14537 tx_fifo.wr_addr_gray[3]
-.sym 14546 tx_fifo.wr_addr_gray_rd[3]
-.sym 14551 tx_fifo.wr_addr_gray_rd[2]
-.sym 14557 tx_fifo.wr_addr_gray[6]
-.sym 14561 tx_fifo.wr_addr_gray_rd[6]
+.sym 14430 $PACKER_VCC_NET
+.sym 14431 w_smi_data_direction
+.sym 14433 i_rst_b_SB_LUT4_I3_O
+.sym 14434 w_smi_data_output[3]
+.sym 14445 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14456 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14460 i_rst_b$SB_IO_IN
+.sym 14478 i_ss$SB_IO_IN
+.sym 14487 tx_fifo.wr_addr_gray_rd[9]
+.sym 14489 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14504 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14505 tx_fifo.wr_addr_gray[3]
+.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14508 smi_ctrl_ins.int_cnt_rx[4]
+.sym 14510 i_rst_b$SB_IO_IN
+.sym 14511 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 14512 tx_fifo.wr_addr[9]
+.sym 14513 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14515 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14516 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14519 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14520 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14527 tx_fifo.wr_addr[9]
+.sym 14532 tx_fifo.wr_addr_gray_rd[9]
+.sym 14538 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14539 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14546 tx_fifo.wr_addr_gray[3]
+.sym 14551 i_rst_b$SB_IO_IN
+.sym 14555 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 14562 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14563 i_rst_b$SB_IO_IN
+.sym 14564 smi_ctrl_ins.int_cnt_rx[4]
 .sym 14566 lvds_clock_$glb_clk
-.sym 14568 $io_pmod[3]$iobuf_i
-.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 14573 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 14574 tx_fifo.wr_addr_gray[6]
-.sym 14575 tx_fifo.wr_addr_gray[2]
-.sym 14576 tx_fifo.wr_addr_gray[3]
-.sym 14577 tx_fifo.wr_addr_gray[4]
-.sym 14578 tx_fifo.wr_addr[9]
-.sym 14579 tx_fifo.wr_addr[1]
-.sym 14602 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 14613 $io_pmod[3]$iobuf_i
-.sym 14614 w_smi_data_direction
-.sym 14624 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 14627 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 14629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 14634 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 14636 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 14637 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 14638 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 14649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 14651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 14652 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14653 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 14655 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 14656 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 14657 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 14658 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 14661 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 14662 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 14663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 14666 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 14671 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 14673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 14676 i_rst_b_SB_LUT4_I3_O
-.sym 14678 w_tx_fifo_empty
-.sym 14682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 14688 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 14690 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14694 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 14695 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 14696 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 14697 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 14701 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 14703 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 14707 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 14712 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 14713 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 14715 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 14718 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 14719 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 14720 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 14721 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 14727 w_tx_fifo_empty
-.sym 14728 i_rst_b_SB_LUT4_I3_O
+.sym 14568 o_smi_write_req$SB_IO_OUT
+.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 14573 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14574 tx_fifo.wr_addr[9]
+.sym 14575 tx_fifo.wr_addr_gray[3]
+.sym 14576 tx_fifo.wr_addr[5]
+.sym 14577 tx_fifo.wr_addr[3]
+.sym 14578 tx_fifo.wr_addr[8]
+.sym 14579 tx_fifo.wr_addr[7]
+.sym 14587 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14589 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14592 tx_fifo.wr_addr[1]
+.sym 14594 tx_fifo.wr_addr_gray_rd[3]
+.sym 14623 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 14626 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 14631 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14632 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14633 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14635 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14636 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14637 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14660 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14661 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14664 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14669 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 14670 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 14671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 14674 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 14675 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 14677 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14688 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 14690 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 14694 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 14703 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 14715 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 14724 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14725 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 14727 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
 .sym 14729 lvds_clock_$glb_clk
 .sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 14732 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 14734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.sym 14737 w_smi_data_output[5]
-.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 14748 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 14750 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 14752 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 14757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 14758 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 14763 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 14764 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 14765 tx_fifo.wr_addr[1]
-.sym 14766 $PACKER_VCC_NET
-.sym 14777 tx_fifo.wr_addr_gray[4]
-.sym 14786 tx_fifo.wr_addr[9]
-.sym 14792 i_rst_b$SB_IO_IN
-.sym 14793 tx_fifo.wr_addr_gray_rd[4]
-.sym 14798 tx_fifo.wr_addr_gray_rd[9]
-.sym 14801 tx_fifo.wr_addr_gray_rd[1]
-.sym 14803 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 14814 tx_fifo.wr_addr_gray_rd[1]
-.sym 14820 tx_fifo.wr_addr[9]
-.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 14829 i_rst_b$SB_IO_IN
-.sym 14837 tx_fifo.wr_addr_gray[4]
-.sym 14842 tx_fifo.wr_addr_gray_rd[4]
-.sym 14849 tx_fifo.wr_addr_gray_rd[9]
+.sym 14731 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
+.sym 14732 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 14733 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 14734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
+.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14736 w_smi_data_output[4]
+.sym 14737 w_smi_data_output[3]
+.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.sym 14748 w_rx_fifo_pulled_data[15]
+.sym 14750 w_rx_fifo_pulled_data[13]
+.sym 14752 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14755 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 14757 tx_fifo.wr_addr[1]
+.sym 14758 tx_fifo.rd_addr_gray_wr[2]
+.sym 14760 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14762 tx_fifo.rd_addr[6]
+.sym 14763 tx_fifo.rd_addr[1]
+.sym 14764 i_sck$SB_IO_IN
+.sym 14766 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14772 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 14773 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14774 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
+.sym 14776 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 14780 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
+.sym 14781 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.sym 14782 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14783 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 14784 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 14787 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 14788 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 14789 tx_fifo.rd_addr[1]
+.sym 14791 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14792 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 14794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 14795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 14797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14798 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14799 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 14800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 14802 smi_ctrl_ins.int_cnt_rx[4]
+.sym 14805 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 14806 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14807 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 14808 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 14811 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 14812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14813 tx_fifo.rd_addr[1]
+.sym 14814 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 14818 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14823 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
+.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.sym 14826 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
+.sym 14830 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 14838 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 14842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14843 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 14844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14847 smi_ctrl_ins.int_cnt_rx[4]
+.sym 14848 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 14849 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14850 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 14851 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
 .sym 14852 lvds_clock_$glb_clk
-.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 14855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 14857 tx_fifo.rd_addr_gray_wr[5]
-.sym 14858 tx_fifo.rd_addr_gray_wr[7]
-.sym 14859 tx_fifo.rd_addr_gray_wr[3]
-.sym 14860 tx_fifo.rd_addr_gray_wr[6]
-.sym 14861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 14866 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 14874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
+.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14855 tx_fifo.rd_addr_gray_wr[9]
+.sym 14856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 14857 tx_fifo.rd_addr_gray_wr[7]
+.sym 14858 tx_fifo.rd_addr_gray_wr[4]
+.sym 14859 tx_fifo.rd_addr_gray_wr[1]
+.sym 14860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 14861 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 14865 w_fetch
+.sym 14867 w_smi_data_output[3]
+.sym 14868 rx_fifo.mem_q.0.3_WDATA_3
+.sym 14870 rx_fifo.wr_addr[0]
+.sym 14874 rx_fifo.wr_addr[8]
 .sym 14875 i_rst_b$SB_IO_IN
-.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 14881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 14886 smi_ctrl_ins.int_cnt_rx[4]
-.sym 14895 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 14897 smi_ctrl_ins.int_cnt_rx[4]
-.sym 14899 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 14902 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 14904 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 14906 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 14909 smi_ctrl_ins.int_cnt_rx[3]
-.sym 14911 smi_ctrl_ins.r_fifo_pulled_data[15]
-.sym 14912 smi_ctrl_ins.int_cnt_rx[4]
-.sym 14913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 14915 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 14918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 14922 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 14923 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 14925 tx_fifo.wr_addr[1]
-.sym 14926 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 14928 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 14929 smi_ctrl_ins.int_cnt_rx[3]
-.sym 14930 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 14931 smi_ctrl_ins.int_cnt_rx[4]
-.sym 14940 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 14946 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 14947 smi_ctrl_ins.r_fifo_pulled_data[15]
-.sym 14948 smi_ctrl_ins.int_cnt_rx[3]
-.sym 14949 smi_ctrl_ins.int_cnt_rx[4]
-.sym 14955 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 14959 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 14966 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 14970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 14971 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 14972 tx_fifo.wr_addr[1]
-.sym 14973 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 14974 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 14975 lvds_clock_$glb_clk
+.sym 14876 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 14881 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 14886 i_ss$SB_IO_IN
+.sym 14889 tx_fifo.rd_addr_gray_wr[9]
+.sym 14897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 14900 smi_ctrl_ins.int_cnt_rx[4]
+.sym 14902 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14906 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 14907 tx_fifo.rd_addr[5]
+.sym 14908 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14910 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14911 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14914 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14918 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 14920 smi_ctrl_ins.r_fifo_pulled_data[27]
+.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 14922 tx_fifo.rd_addr[6]
+.sym 14925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14926 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 14928 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 14929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14930 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 14931 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 14934 smi_ctrl_ins.int_cnt_rx[3]
+.sym 14935 smi_ctrl_ins.r_fifo_pulled_data[27]
+.sym 14936 smi_ctrl_ins.int_cnt_rx[4]
+.sym 14937 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 14941 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 14943 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 14946 tx_fifo.rd_addr[5]
+.sym 14947 tx_fifo.rd_addr[6]
+.sym 14948 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 14959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 14961 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 14974 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 14975 r_counter_$glb_clk
 .sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 14977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
-.sym 14980 o_smi_read_req$SB_IO_OUT
-.sym 14981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
-.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 14988 w_rx_data[0]
-.sym 14989 rx_fifo.wr_addr[2]
-.sym 14997 rx_fifo.wr_addr[5]
-.sym 14999 rx_fifo.wr_addr[8]
-.sym 15001 w_smi_data_direction
-.sym 15003 w_rx_fifo_pulled_data[28]
-.sym 15004 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 15008 w_smi_data_direction
-.sym 15010 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 15011 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 15020 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 15025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.sym 15026 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 15028 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 15029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 15030 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 15036 w_tx_fifo_full
-.sym 15037 tx_fifo.wr_addr[1]
-.sym 15038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
-.sym 15041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 15042 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 15044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
-.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 15047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 15052 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 15054 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 15057 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 15064 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 15065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 15066 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 15072 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 15075 w_tx_fifo_full
-.sym 15076 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 15078 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 15081 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.sym 15082 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
-.sym 15083 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
-.sym 15087 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 15090 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 15093 tx_fifo.wr_addr[1]
+.sym 14977 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 14979 spi_if_ins.spi.r_rx_done
+.sym 14980 tx_fifo.full_o_SB_LUT4_I1_O[1]
+.sym 14981 tx_fifo.full_o_SB_LUT4_I1_O[0]
+.sym 14982 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 14983 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 14984 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 14992 w_rx_fifo_pulled_data[12]
+.sym 14993 $PACKER_VCC_NET
+.sym 14994 rx_fifo.rd_addr[2]
+.sym 14995 rx_fifo.wr_addr[1]
+.sym 14996 rx_fifo.rd_addr[1]
+.sym 14997 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 15008 rx_fifo.wr_addr[4]
+.sym 15020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 15021 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 15022 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 15023 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 15024 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 15026 tx_fifo.wr_addr[1]
+.sym 15038 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 15053 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 15057 tx_fifo.wr_addr[1]
+.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 15065 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 15071 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 15075 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 15093 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 15096 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
 .sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
 .sym 15098 r_counter_$glb_clk
 .sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 15100 smi_ctrl_ins.r_fifo_pull_1
-.sym 15101 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 15102 w_tx_fifo_full
-.sym 15103 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
-.sym 15104 smi_ctrl_ins.r_fifo_pull
-.sym 15106 smi_ctrl_ins.r_fifo_push_1
-.sym 15107 smi_ctrl_ins.r_fifo_push
-.sym 15108 i_rst_b$SB_IO_IN
-.sym 15111 i_rst_b$SB_IO_IN
-.sym 15113 w_rx_fifo_empty
-.sym 15114 rx_fifo.rd_addr[8]
-.sym 15116 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
-.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 15118 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 15120 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 15121 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 15122 i_rst_b$SB_IO_IN
-.sym 15123 rx_fifo.wr_addr[8]
-.sym 15126 w_rx_fifo_pulled_data[29]
-.sym 15135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 15144 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 15145 smi_ctrl_ins.r_fifo_pulled_data[29]
-.sym 15146 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
-.sym 15152 smi_ctrl_ins.r_fifo_pulled_data[28]
-.sym 15159 smi_ctrl_ins.int_cnt_rx[3]
-.sym 15162 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 15167 smi_ctrl_ins.r_fifo_pulled_data[20]
-.sym 15168 i_rst_b$SB_IO_IN
-.sym 15169 smi_ctrl_ins.int_cnt_rx[4]
-.sym 15175 smi_ctrl_ins.int_cnt_rx[4]
-.sym 15176 smi_ctrl_ins.int_cnt_rx[3]
-.sym 15187 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 15189 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
-.sym 15204 smi_ctrl_ins.r_fifo_pulled_data[20]
-.sym 15205 smi_ctrl_ins.r_fifo_pulled_data[28]
-.sym 15206 smi_ctrl_ins.int_cnt_rx[4]
-.sym 15207 smi_ctrl_ins.int_cnt_rx[3]
-.sym 15216 smi_ctrl_ins.int_cnt_rx[4]
-.sym 15217 smi_ctrl_ins.int_cnt_rx[3]
-.sym 15218 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 15219 smi_ctrl_ins.r_fifo_pulled_data[29]
-.sym 15220 i_rst_b$SB_IO_IN
-.sym 15221 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 15223 spi_if_ins.w_rx_data[1]
-.sym 15225 spi_if_ins.w_rx_data[2]
-.sym 15226 spi_if_ins.w_rx_data[4]
-.sym 15228 spi_if_ins.w_rx_data[5]
-.sym 15229 spi_if_ins.w_rx_data[6]
-.sym 15230 spi_if_ins.w_rx_data[0]
-.sym 15233 w_smi_data_direction
-.sym 15241 w_rx_fifo_empty
-.sym 15244 smi_ctrl_ins.w_fifo_push_trigger
-.sym 15246 w_tx_fifo_full
-.sym 15252 w_rx_data[0]
-.sym 15253 $PACKER_VCC_NET
-.sym 15256 spi_if_ins.w_rx_data[1]
-.sym 15258 w_rx_data[5]
-.sym 15266 w_rx_fifo_pulled_data[31]
-.sym 15275 w_rx_fifo_pulled_data[28]
-.sym 15279 w_rx_fifo_pulled_data[30]
-.sym 15286 w_rx_fifo_pulled_data[29]
-.sym 15297 w_rx_fifo_pulled_data[30]
-.sym 15306 w_rx_fifo_pulled_data[31]
-.sym 15318 w_rx_fifo_pulled_data[28]
-.sym 15321 w_rx_fifo_pulled_data[29]
-.sym 15343 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 15100 spi_if_ins.spi.r3_rx_done
+.sym 15102 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 15104 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15105 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 15106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 15107 spi_if_ins.spi.r2_rx_done
+.sym 15111 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 15112 rx_fifo.mem_i.0.0_WDATA_3
+.sym 15113 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 15114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 15115 rx_fifo.wr_addr[2]
+.sym 15116 rx_fifo.wr_addr[1]
+.sym 15118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 15120 rx_fifo.mem_i.0.0_WDATA_2
+.sym 15126 $PACKER_VCC_NET
+.sym 15132 w_tx_fifo_full
+.sym 15133 i_ss$SB_IO_IN
+.sym 15135 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 15144 tx_fifo.wr_addr_gray[2]
+.sym 15145 tx_fifo.wr_addr_gray[5]
+.sym 15148 tx_fifo.wr_addr_gray[7]
+.sym 15150 tx_fifo.wr_addr_gray[0]
+.sym 15151 tx_fifo.wr_addr_gray_rd[5]
+.sym 15174 tx_fifo.wr_addr_gray[0]
+.sym 15186 tx_fifo.wr_addr_gray[5]
+.sym 15204 tx_fifo.wr_addr_gray_rd[5]
+.sym 15213 tx_fifo.wr_addr_gray[7]
+.sym 15218 tx_fifo.wr_addr_gray[2]
+.sym 15221 lvds_clock_$glb_clk
+.sym 15225 tx_fifo.rd_addr_gray_wr[0]
+.sym 15226 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15235 rx_fifo.rd_addr[9]
+.sym 15236 rx_fifo.rd_addr[1]
+.sym 15238 rx_fifo.mem_i.0.0_WDATA
+.sym 15244 rx_fifo.rd_addr[2]
+.sym 15250 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 15251 tx_fifo.rd_addr[1]
+.sym 15255 w_tx_data_smi[2]
+.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 15277 tx_fifo.rd_addr[1]
+.sym 15291 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 15311 tx_fifo.rd_addr[1]
+.sym 15343 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
+.sym 15344 lvds_clock_$glb_clk
 .sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 15346 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 15347 spi_if_ins.w_rx_data[3]
-.sym 15348 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 15350 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 15351 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 15352 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 15353 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 15357 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 15358 rx_fifo.rd_addr[6]
-.sym 15361 rx_fifo.rd_addr[0]
-.sym 15362 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 15367 w_rx_fifo_pulled_data[30]
-.sym 15370 spi_if_ins.w_rx_data[2]
-.sym 15372 w_rx_data[2]
-.sym 15376 spi_if_ins.w_rx_data[5]
-.sym 15378 spi_if_ins.w_rx_data[6]
-.sym 15380 spi_if_ins.w_rx_data[0]
-.sym 15381 spi_if_ins.w_rx_data[3]
-.sym 15392 spi_if_ins.w_rx_data[5]
-.sym 15394 spi_if_ins.w_rx_data[0]
-.sym 15397 spi_if_ins.w_rx_data[2]
-.sym 15398 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 15414 i_rst_b$SB_IO_IN
-.sym 15421 spi_if_ins.w_rx_data[0]
-.sym 15440 spi_if_ins.w_rx_data[5]
-.sym 15452 spi_if_ins.w_rx_data[2]
-.sym 15456 i_rst_b$SB_IO_IN
-.sym 15466 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 15346 w_tx_data_smi[1]
+.sym 15347 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
+.sym 15348 w_tx_data_smi[2]
+.sym 15349 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
+.sym 15350 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 15351 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 15353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
+.sym 15358 rx_fifo.wr_addr[5]
+.sym 15361 rx_fifo.wr_addr[4]
+.sym 15363 rx_fifo.wr_addr[0]
+.sym 15366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 15368 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 15371 w_fetch
+.sym 15379 w_tx_data_smi[1]
+.sym 15380 $PACKER_VCC_NET
+.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 15391 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 15392 spi_if_ins.r_tx_data_valid
+.sym 15396 $PACKER_VCC_NET
+.sym 15400 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 15403 i_ss$SB_IO_IN
+.sym 15404 $PACKER_VCC_NET
+.sym 15405 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 15413 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 15414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 15419 $nextpnr_ICESTORM_LC_9$O
+.sym 15422 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 15425 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
+.sym 15427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 15428 $PACKER_VCC_NET
+.sym 15433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 15434 $PACKER_VCC_NET
+.sym 15435 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
+.sym 15439 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 15440 $PACKER_VCC_NET
+.sym 15441 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 15444 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 15451 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 15452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 15453 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 15462 spi_if_ins.r_tx_data_valid
+.sym 15463 i_ss$SB_IO_IN
+.sym 15466 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
 .sym 15467 r_counter_$glb_clk
-.sym 15469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
-.sym 15470 w_rx_data[4]
-.sym 15471 w_rx_data[7]
-.sym 15472 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 15473 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 15474 w_rx_data[3]
-.sym 15475 w_rx_data[1]
-.sym 15476 w_rx_data[6]
-.sym 15481 rx_fifo.wr_addr[0]
-.sym 15482 rx_fifo.wr_addr[4]
-.sym 15485 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 15486 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 15489 rx_fifo.mem_i.0.3_WDATA_1
-.sym 15490 w_rx_fifo_pulled_data[31]
-.sym 15494 spi_if_ins.w_rx_data[1]
-.sym 15495 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 15496 w_rx_data[5]
-.sym 15500 w_rx_data[2]
-.sym 15504 w_smi_data_direction
-.sym 15513 w_rx_data[5]
-.sym 15521 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 15528 w_rx_data[7]
-.sym 15533 w_rx_data[6]
-.sym 15538 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 15539 w_rx_data[3]
-.sym 15550 w_rx_data[7]
-.sym 15558 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 15563 w_rx_data[6]
-.sym 15569 w_rx_data[3]
-.sym 15575 w_rx_data[5]
-.sym 15589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 15468 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 15469 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
+.sym 15470 spi_if_ins.spi.r_tx_byte[4]
+.sym 15471 spi_if_ins.spi.r_tx_byte[2]
+.sym 15472 spi_if_ins.spi.r_tx_byte[3]
+.sym 15473 spi_if_ins.spi.r_tx_byte[6]
+.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
+.sym 15475 spi_if_ins.spi.r_tx_byte[1]
+.sym 15476 spi_if_ins.spi.r_tx_byte[0]
+.sym 15485 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 15486 spi_if_ins.r_tx_byte[7]
+.sym 15489 rx_fifo.rd_addr[1]
+.sym 15490 rx_fifo.wr_addr[1]
+.sym 15491 $PACKER_VCC_NET
+.sym 15492 rx_fifo.wr_addr[2]
+.sym 15493 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15494 spi_if_ins.r_tx_byte[0]
+.sym 15497 w_fetch
+.sym 15498 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 15500 spi_if_ins.r_tx_byte[3]
+.sym 15502 spi_if_ins.r_tx_byte[1]
+.sym 15503 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15512 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 15517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
+.sym 15521 i_rst_b$SB_IO_IN
+.sym 15523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
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+.sym 15526 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 15530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 15533 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 15534 w_smi_read_req
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+.sym 15543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 15551 w_smi_read_req
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+.sym 15564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15567 i_rst_b$SB_IO_IN
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+.sym 15569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 15570 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 15581 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
+.sym 15586 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 15587 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 15588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15589 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
 .sym 15590 r_counter_$glb_clk
-.sym 15591 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 15592 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 15593 w_ioc[1]
-.sym 15594 w_cs[0]
-.sym 15595 w_ioc[4]
-.sym 15596 w_ioc[3]
-.sym 15597 w_ioc[0]
-.sym 15598 w_ioc[2]
-.sym 15599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 15605 w_rx_data[1]
-.sym 15606 $PACKER_VCC_NET
-.sym 15607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
-.sym 15608 w_load
-.sym 15609 i_rst_b$SB_IO_IN
-.sym 15614 rx_fifo.rd_addr[8]
-.sym 15621 i_glob_clock$SB_IO_IN
-.sym 15622 w_rx_data[3]
-.sym 15624 w_rx_data[1]
-.sym 15627 w_ioc[1]
-.sym 15635 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 15644 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 15646 w_cs[2]
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-.sym 15650 spi_if_ins.w_rx_data[6]
-.sym 15651 w_cs[1]
-.sym 15653 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 15657 w_cs[3]
-.sym 15659 w_cs[0]
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-.sym 15667 spi_if_ins.w_rx_data[6]
-.sym 15672 w_cs[3]
-.sym 15673 w_cs[2]
-.sym 15674 w_cs[0]
-.sym 15675 w_cs[1]
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-.sym 15684 spi_if_ins.w_rx_data[6]
-.sym 15687 spi_if_ins.w_rx_data[5]
-.sym 15692 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
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-.sym 15697 spi_if_ins.w_rx_data[5]
-.sym 15712 spi_if_ins.o_ioc_SB_DFFE_Q_E
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+.sym 15592 w_ioc[2]
+.sym 15593 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 15595 i_button_SB_LUT4_I0_O[1]
+.sym 15596 w_ioc[4]
+.sym 15597 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 15598 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 15599 w_ioc[3]
+.sym 15603 i_rst_b$SB_IO_IN
+.sym 15604 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 15607 i_rst_b$SB_IO_IN
+.sym 15608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 15613 spi_if_ins.r_tx_byte[7]
+.sym 15615 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 15617 spi_if_ins.r_tx_byte[2]
+.sym 15618 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 15619 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 15620 w_rx_data[6]
+.sym 15622 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
+.sym 15624 spi_if_ins.r_tx_byte[4]
+.sym 15625 w_fetch
+.sym 15626 w_rx_data[2]
+.sym 15627 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 15634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
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+.sym 15643 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 15644 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 15645 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15647 w_fetch
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+.sym 15656 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 15659 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 15663 i_rst_b$SB_IO_IN
+.sym 15664 i_rst_b$SB_IO_IN
+.sym 15667 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 15668 i_rst_b$SB_IO_IN
+.sym 15669 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 15673 spi_if_ins.w_rx_data[2]
+.sym 15678 i_rst_b$SB_IO_IN
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+.sym 15680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
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+.sym 15697 i_rst_b$SB_IO_IN
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+.sym 15710 i_rst_b$SB_IO_IN
+.sym 15711 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15712 spi_if_ins.o_data_in_SB_DFFE_Q_E
 .sym 15713 r_counter_$glb_clk
-.sym 15714 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
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-.sym 15717 spi_if_ins.r_tx_byte[1]
-.sym 15718 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 15719 spi_if_ins.r_tx_byte[0]
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-.sym 15721 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
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 .sym 15722 spi_if_ins.r_tx_byte[6]
-.sym 15734 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 15736 w_ioc[1]
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-.sym 15744 w_rx_data[0]
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-.sym 15750 w_rx_data[5]
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-.sym 15760 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
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-.sym 15765 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
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-.sym 15776 i_rst_b$SB_IO_IN
-.sym 15777 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
-.sym 15778 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 15780 w_tx_data_io[2]
-.sym 15781 i_glob_clock$SB_IO_IN
-.sym 15782 w_tx_data_smi[2]
-.sym 15783 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
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-.sym 15789 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 15790 w_tx_data_io[2]
-.sym 15791 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 15792 w_tx_data_smi[2]
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-.sym 15803 i_rst_b$SB_IO_IN
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-.sym 15814 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
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-.sym 15819 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
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-.sym 15822 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
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-.sym 15828 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
-.sym 15831 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
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-.sym 15833 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
-.sym 15834 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 15835 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 15836 i_glob_clock$SB_IO_IN
-.sym 15838 r_tx_data[6]
-.sym 15839 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
-.sym 15840 r_tx_data[3]
-.sym 15841 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 15842 r_tx_data[5]
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+.sym 15744 i_button_SB_LUT4_I0_I3[2]
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+.sym 15746 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
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+.sym 15748 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 15749 io_pmod_out[1]$SB_IO_OUT
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+.sym 15765 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
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+.sym 15780 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
+.sym 15783 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 15784 i_rst_b$SB_IO_IN
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+.sym 15789 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 15790 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 15791 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15792 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 15795 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 15796 w_fetch
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+.sym 15820 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 15821 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15826 i_rst_b$SB_IO_IN
+.sym 15828 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
+.sym 15831 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15832 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 15833 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
+.sym 15835 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 15836 r_counter_$glb_clk
+.sym 15838 r_tx_data[5]
+.sym 15839 r_tx_data[1]
+.sym 15840 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 15841 r_tx_data[6]
+.sym 15842 i_button_SB_LUT4_I0_O[2]
+.sym 15843 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
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-.sym 15845 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
-.sym 15850 w_fetch
-.sym 15855 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
-.sym 15865 w_ioc[1]
-.sym 15870 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-.sym 15872 w_rx_data[2]
-.sym 15873 w_ioc[0]
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-.sym 15884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
-.sym 15886 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 15887 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 15890 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 15892 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 15894 w_load
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-.sym 15897 w_ioc[1]
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-.sym 15903 w_fetch
-.sym 15906 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.sym 15909 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 15910 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15912 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15914 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 15920 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
-.sym 15921 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15924 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15926 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 15930 o_led1_SB_LUT4_I1_I2[3]
-.sym 15931 w_cs[2]
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+.sym 15846 o_led1_SB_DFFER_Q_E
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+.sym 15854 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
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-.sym 15936 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15937 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 15943 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 15944 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 15948 w_ioc[1]
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-.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
+.sym 15936 w_fetch
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+.sym 15939 i_rst_b$SB_IO_IN
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+.sym 15949 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 15950 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 15951 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 15954 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
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+.sym 15958 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
 .sym 15959 r_counter_$glb_clk
-.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 15961 io_ctrl_ins.pmod_dir_state[5]
-.sym 15962 o_led1_SB_LUT4_I1_I2[3]
-.sym 15963 io_ctrl_ins.pmod_dir_state[6]
-.sym 15964 o_led1_SB_LUT4_I1_I2[2]
-.sym 15965 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
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-.sym 15968 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
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-.sym 15984 lvds_clock
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-.sym 15991 w_smi_data_direction
-.sym 15992 w_rx_data[2]
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-.sym 16008 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 16009 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 16011 w_cs[1]
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-.sym 16014 w_ioc[1]
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-.sym 16021 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
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-.sym 16025 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 16029 o_led1_SB_LUT4_I1_I2[2]
-.sym 16032 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
-.sym 16033 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
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-.sym 16036 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
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-.sym 16059 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
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+.sym 16080 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
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-.sym 16084 i_config_SB_LUT4_I0_1_O[1]
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-.sym 16091 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
-.sym 16098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
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-.sym 16126 o_led1_SB_LUT4_I1_I2[3]
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-.sym 16129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
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-.sym 16132 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
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-.sym 16137 o_led0_SB_LUT4_I1_O[3]
-.sym 16139 io_ctrl_ins.pmod_dir_state[3]
-.sym 16140 io_ctrl_ins.o_pmod[3]
-.sym 16141 o_led0_SB_LUT4_I1_O[2]
-.sym 16142 o_led0_SB_LUT4_I1_O[0]
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-.sym 16150 io_ctrl_ins.mixer_en_state
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-.sym 16153 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
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-.sym 16179 o_led0_SB_LUT4_I1_O[1]
-.sym 16182 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
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-.sym 16188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 16189 o_led1_SB_LUT4_I1_I2[2]
-.sym 16190 io_ctrl_ins.pmod_dir_state[3]
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-.sym 16197 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
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-.sym 16209 o_shdn_tx_lna$SB_IO_OUT
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-.sym 16211 o_rx_h_tx_l$SB_IO_OUT
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-.sym 16213 o_tr_vc1$SB_IO_OUT
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-.sym 16219 o_led1_SB_LUT4_I1_O[3]
-.sym 16228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 16232 o_rx_h_tx_l$SB_IO_OUT
-.sym 16240 i_config[3]$SB_IO_IN
-.sym 16249 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
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-.sym 16252 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
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-.sym 16263 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
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-.sym 16272 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
-.sym 16281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 16282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 16283 o_led0_SB_LUT4_I1_O[0]
-.sym 16288 o_led1_SB_LUT4_I1_O[0]
-.sym 16290 o_led0_SB_LUT4_I1_O[0]
-.sym 16293 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 16294 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 16295 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 16296 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 16299 w_rx_data[0]
-.sym 16305 i_rst_b$SB_IO_IN
-.sym 16306 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
-.sym 16307 o_led1_SB_LUT4_I1_O[0]
-.sym 16323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 16324 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 16325 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 16326 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 16327 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
+.sym 16084 o_tr_vc2$SB_IO_OUT
+.sym 16085 o_shdn_tx_lna$SB_IO_OUT
+.sym 16086 o_rx_h_tx_l$SB_IO_OUT
+.sym 16087 o_tr_vc1_b$SB_IO_OUT
+.sym 16088 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 16089 o_shdn_rx_lna$SB_IO_OUT
+.sym 16090 io_ctrl_ins.mixer_en_state
+.sym 16091 o_tr_vc1$SB_IO_OUT
+.sym 16096 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 16098 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
+.sym 16102 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 16106 i_rst_b$SB_IO_IN
+.sym 16110 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
+.sym 16112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 16113 spi_if_ins.r_tx_byte[2]
+.sym 16114 w_rx_data[2]
+.sym 16117 w_rx_data[6]
+.sym 16118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16119 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 16125 i_glob_clock$SB_IO_IN
+.sym 16127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 16131 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
+.sym 16133 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.sym 16135 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
+.sym 16136 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 16139 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
+.sym 16141 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
+.sym 16151 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 16155 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
+.sym 16158 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 16159 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 16160 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
+.sym 16161 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
+.sym 16189 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
+.sym 16190 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
+.sym 16191 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 16200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
+.sym 16202 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.sym 16203 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 16204 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 16205 i_glob_clock$SB_IO_IN
+.sym 16207 io_ctrl_ins.rf_pin_state[4]
+.sym 16208 io_ctrl_ins.rf_pin_state[2]
+.sym 16209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.sym 16210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 16211 io_ctrl_ins.rf_pin_state[1]
+.sym 16212 io_ctrl_ins.rf_pin_state[0]
+.sym 16213 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 16214 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 16224 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 16228 o_shdn_tx_lna$SB_IO_OUT
+.sym 16229 i_glob_clock$SB_IO_IN
+.sym 16232 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 16237 o_shdn_rx_lna$SB_IO_OUT
+.sym 16256 r_tx_data[2]
+.sym 16259 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 16261 r_tx_data[0]
+.sym 16263 r_tx_data[7]
+.sym 16272 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 16284 r_tx_data[2]
+.sym 16301 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 16307 r_tx_data[0]
+.sym 16326 r_tx_data[7]
+.sym 16327 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
 .sym 16328 r_counter_$glb_clk
-.sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 16330 io_ctrl_ins.rf_pin_state[4]
-.sym 16331 io_ctrl_ins.rf_pin_state[7]
-.sym 16332 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
-.sym 16333 io_ctrl_ins.rf_pin_state[5]
-.sym 16334 io_ctrl_ins.rf_pin_state[1]
-.sym 16335 io_ctrl_ins.rf_pin_state[6]
-.sym 16336 io_ctrl_ins.rf_pin_state[3]
-.sym 16337 io_ctrl_ins.rf_pin_state[2]
-.sym 16338 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
-.sym 16344 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 16347 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 16330 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 16331 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
+.sym 16332 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
+.sym 16334 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
+.sym 16336 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 16337 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 16344 w_rx_data[2]
+.sym 16345 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 16349 i_rst_b$SB_IO_IN
 .sym 16354 i_button$SB_IO_IN
-.sym 16371 i_glob_clock$SB_IO_IN
-.sym 16389 r_counter
-.sym 16418 r_counter
-.sym 16451 i_glob_clock$SB_IO_IN
+.sym 16356 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 16358 i_button_SB_LUT4_I0_I3[0]
+.sym 16362 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 16388 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
+.sym 16390 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16391 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
+.sym 16394 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 16395 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 16397 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
+.sym 16398 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 16401 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 16410 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 16412 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16417 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16419 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 16422 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
+.sym 16424 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16429 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
+.sym 16431 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16434 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 16436 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16440 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
+.sym 16443 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 16450 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 16451 r_counter_$glb_clk
 .sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 16453 i_config[3]$SB_IO_IN
+.sym 16453 i_button_SB_LUT4_I0_I3[0]
 .sym 16455 i_button$SB_IO_IN
-.sym 16457 w_rx_data[0]
-.sym 16480 w_rx_data[2]
-.sym 16484 w_rx_data[5]
-.sym 16497 r_counter
-.sym 16517 r_counter
-.sym 16554 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 16555 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 16556 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 16557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 16558 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 16559 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 16560 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 16577 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 16585 w_smi_data_direction
-.sym 16596 tx_fifo.wr_addr[4]
-.sym 16610 tx_fifo.wr_addr[1]
-.sym 16612 tx_fifo.wr_addr[5]
-.sym 16614 tx_fifo.wr_addr[6]
-.sym 16623 tx_fifo.wr_addr[3]
-.sym 16624 tx_fifo.wr_addr[7]
-.sym 16625 tx_fifo.wr_addr[2]
-.sym 16626 tx_fifo.wr_addr[0]
-.sym 16627 $nextpnr_ICESTORM_LC_3$O
+.sym 16462 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 16497 lvds_clock
+.sym 16519 lvds_clock
+.sym 16554 tx_fifo.wr_addr[0]
+.sym 16555 tx_fifo.wr_addr[2]
+.sym 16556 tx_fifo.wr_addr[6]
+.sym 16560 tx_fifo.wr_addr[1]
+.sym 16585 o_smi_write_req$SB_IO_OUT
+.sym 16599 tx_fifo.wr_addr[5]
+.sym 16602 tx_fifo.wr_addr[7]
+.sym 16608 tx_fifo.wr_addr[3]
+.sym 16613 tx_fifo.wr_addr[2]
+.sym 16615 tx_fifo.wr_addr[4]
+.sym 16618 tx_fifo.wr_addr[1]
+.sym 16620 tx_fifo.wr_addr[0]
+.sym 16622 tx_fifo.wr_addr[6]
+.sym 16627 $nextpnr_ICESTORM_LC_5$O
 .sym 16630 tx_fifo.wr_addr[0]
-.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 16635 tx_fifo.wr_addr[1]
+.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
+.sym 16636 tx_fifo.wr_addr[1]
 .sym 16637 tx_fifo.wr_addr[0]
-.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 16641 tx_fifo.wr_addr[2]
-.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
+.sym 16642 tx_fifo.wr_addr[2]
+.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
 .sym 16645 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
-.sym 16648 tx_fifo.wr_addr[3]
-.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
-.sym 16653 tx_fifo.wr_addr[4]
+.sym 16647 tx_fifo.wr_addr[3]
+.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
+.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 16654 tx_fifo.wr_addr[4]
 .sym 16655 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
-.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
-.sym 16660 tx_fifo.wr_addr[5]
-.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
-.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 16665 tx_fifo.wr_addr[6]
-.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
-.sym 16669 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 16671 tx_fifo.wr_addr[7]
-.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 16681 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 16682 tx_fifo.wr_addr[5]
-.sym 16683 tx_fifo.wr_addr[8]
-.sym 16684 tx_fifo.wr_addr[6]
-.sym 16685 tx_fifo.wr_addr[3]
-.sym 16686 tx_fifo.wr_addr[7]
-.sym 16687 tx_fifo.wr_addr[2]
-.sym 16688 tx_fifo.wr_addr[0]
-.sym 16694 tx_fifo.wr_addr[4]
-.sym 16697 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 16703 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 16733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 16735 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 16736 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 16742 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 16744 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 16753 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 16765 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 16767 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 16659 tx_fifo.wr_addr[5]
+.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
+.sym 16666 tx_fifo.wr_addr[6]
+.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 16669 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 16672 tx_fifo.wr_addr[7]
+.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
+.sym 16682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
+.sym 16683 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 16684 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 16686 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 16688 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16698 tx_fifo.wr_addr[1]
+.sym 16703 i_sck$SB_IO_IN
+.sym 16723 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 16725 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16730 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 16734 w_smi_data_output[4]
+.sym 16735 tx_fifo.wr_addr[4]
+.sym 16736 $PACKER_VCC_NET
+.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 16743 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 16753 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 16758 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 16760 tx_fifo.wr_addr[9]
+.sym 16761 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
 .sym 16769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 16770 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 16772 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 16775 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 16776 tx_fifo.wr_addr[8]
-.sym 16780 tx_fifo.wr_addr[9]
-.sym 16783 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 16790 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 16793 tx_fifo.wr_addr[8]
-.sym 16794 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 16773 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 16782 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 16788 tx_fifo.wr_addr[8]
+.sym 16790 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 16792 tx_fifo.wr_addr[8]
+.sym 16794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
 .sym 16798 tx_fifo.wr_addr[9]
-.sym 16800 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 16812 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 16815 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 16823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 16828 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 16833 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
+.sym 16800 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 16811 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 16827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 16834 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
 .sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
 .sym 16838 r_counter_$glb_clk
 .sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
-.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
-.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 16845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 16850 w_rx_data[3]
-.sym 16851 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 16857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 16872 tx_fifo.wr_addr[2]
-.sym 16875 $PACKER_VCC_NET
-.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 16882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
+.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
+.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
+.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
+.sym 16845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 16846 tx_fifo.wr_addr[4]
+.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 16852 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 16856 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 16863 i_ss$SB_IO_IN
+.sym 16871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 16874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16882 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
 .sym 16883 i_rst_b$SB_IO_IN
-.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 16890 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 16891 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 16892 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 16894 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 16903 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 16904 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 16905 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
-.sym 16907 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
-.sym 16910 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
-.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
-.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 16933 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 16934 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 16944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 16945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 16946 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 16947 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
-.sym 16952 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 16956 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 16958 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 16959 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
+.sym 16885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 16886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16887 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 16888 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 16890 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 16891 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16893 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
+.sym 16897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
+.sym 16898 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
+.sym 16899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 16902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 16904 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
+.sym 16905 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 16906 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.sym 16908 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 16914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 16916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
+.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 16926 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
+.sym 16927 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 16928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16929 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
+.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 16933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 16934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 16940 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.sym 16945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
+.sym 16946 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 16950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
+.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
 .sym 16960 i_rst_b$SB_IO_IN
 .sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 16964 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 16965 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
-.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
-.sym 16969 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 16970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
-.sym 16973 w_ioc[0]
-.sym 16975 $io_pmod[3]$iobuf_i
-.sym 16979 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 16983 tx_fifo.rd_addr_gray_wr[4]
-.sym 16984 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 16985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 16963 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
+.sym 16964 smi_ctrl_ins.r_fifo_push_1
+.sym 16965 w_tx_fifo_full
+.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
+.sym 16967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
+.sym 16969 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 16970 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 16979 w_rx_fifo_pulled_data[14]
+.sym 16980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 16983 rx_fifo.wr_addr[4]
+.sym 16984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 16986 rx_fifo.wr_addr[9]
 .sym 16988 i_ss$SB_IO_IN
-.sym 16990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 16993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.sym 16994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.sym 17009 tx_fifo.rd_addr_gray[5]
-.sym 17012 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 17014 tx_fifo.rd_addr_gray[3]
-.sym 17016 tx_fifo.rd_addr_gray[6]
-.sym 17017 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 17018 tx_fifo.rd_addr_gray[7]
-.sym 17026 tx_fifo.rd_addr_gray_wr[6]
-.sym 17032 tx_fifo.rd_addr_gray_wr[7]
-.sym 17033 tx_fifo.rd_addr_gray_wr[3]
-.sym 17037 tx_fifo.rd_addr_gray_wr[6]
-.sym 17043 tx_fifo.rd_addr_gray_wr[7]
-.sym 17049 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 17052 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 17055 tx_fifo.rd_addr_gray[5]
-.sym 17062 tx_fifo.rd_addr_gray[7]
-.sym 17069 tx_fifo.rd_addr_gray[3]
-.sym 17074 tx_fifo.rd_addr_gray[6]
-.sym 17080 tx_fifo.rd_addr_gray_wr[3]
+.sym 16991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 16997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 17008 tx_fifo.rd_addr_gray_wr[4]
+.sym 17011 tx_fifo.rd_addr_gray_wr[2]
+.sym 17015 tx_fifo.rd_addr_gray_wr[7]
+.sym 17024 tx_fifo.rd_addr_gray[4]
+.sym 17025 tx_fifo.rd_addr_gray_wr[1]
+.sym 17030 tx_fifo.rd_addr_gray[1]
+.sym 17032 tx_fifo.rd_addr_gray[7]
+.sym 17033 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 17037 tx_fifo.rd_addr_gray_wr[7]
+.sym 17046 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 17052 tx_fifo.rd_addr_gray_wr[2]
+.sym 17057 tx_fifo.rd_addr_gray[7]
+.sym 17061 tx_fifo.rd_addr_gray[4]
+.sym 17067 tx_fifo.rd_addr_gray[1]
+.sym 17075 tx_fifo.rd_addr_gray_wr[4]
+.sym 17081 tx_fifo.rd_addr_gray_wr[1]
 .sym 17084 r_counter_$glb_clk
-.sym 17088 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 17089 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 17091 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
-.sym 17092 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 17096 w_rx_data[6]
-.sym 17100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 17101 rx_fifo.rd_addr[9]
-.sym 17105 i_sck$SB_IO_IN
-.sym 17106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 17109 i_ss$SB_IO_IN
-.sym 17129 w_tx_fifo_full
-.sym 17130 tx_fifo.rd_addr_gray_wr[5]
-.sym 17131 w_rx_fifo_empty
-.sym 17132 i_rst_b$SB_IO_IN
-.sym 17134 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
-.sym 17138 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
-.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
-.sym 17144 tx_fifo.wr_addr[2]
-.sym 17151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
-.sym 17154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.sym 17156 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 17157 w_smi_data_direction
-.sym 17160 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 17161 tx_fifo.wr_addr[2]
-.sym 17162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
-.sym 17179 w_rx_fifo_empty
-.sym 17180 w_smi_data_direction
-.sym 17181 w_tx_fifo_full
-.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
-.sym 17186 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
-.sym 17187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
-.sym 17190 tx_fifo.rd_addr_gray_wr[5]
-.sym 17204 i_rst_b$SB_IO_IN
-.sym 17205 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
-.sym 17207 r_counter_$glb_clk
-.sym 17210 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 17212 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17225 w_rx_fifo_pulled_data[6]
-.sym 17227 io_pmod[0]$SB_IO_IN
-.sym 17232 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 17234 i_mosi$SB_IO_IN
-.sym 17251 w_rx_fifo_empty
-.sym 17252 smi_ctrl_ins.w_fifo_push_trigger
-.sym 17255 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 17256 smi_ctrl_ins.r_fifo_push_1
-.sym 17257 smi_ctrl_ins.r_fifo_push
-.sym 17258 smi_ctrl_ins.w_fifo_pull_trigger
-.sym 17260 w_tx_fifo_full
-.sym 17262 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
-.sym 17265 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.sym 17270 smi_ctrl_ins.r_fifo_pull
-.sym 17274 smi_ctrl_ins.r_fifo_pull_1
-.sym 17279 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
-.sym 17285 smi_ctrl_ins.r_fifo_pull
-.sym 17289 w_rx_fifo_empty
-.sym 17291 smi_ctrl_ins.r_fifo_pull_1
-.sym 17292 smi_ctrl_ins.r_fifo_pull
-.sym 17295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.sym 17296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 17297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
-.sym 17298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
-.sym 17301 w_tx_fifo_full
-.sym 17302 smi_ctrl_ins.r_fifo_push_1
-.sym 17303 smi_ctrl_ins.r_fifo_push
-.sym 17310 smi_ctrl_ins.w_fifo_pull_trigger
-.sym 17320 smi_ctrl_ins.r_fifo_push
-.sym 17328 smi_ctrl_ins.w_fifo_push_trigger
+.sym 17087 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 17088 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 17089 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 17093 o_smi_read_req$SB_IO_OUT
+.sym 17100 rx_fifo.rd_addr[5]
+.sym 17102 i_ss$SB_IO_IN
+.sym 17103 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 17108 smi_ctrl_ins.r_fifo_push
+.sym 17109 w_tx_fifo_full
+.sym 17111 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 17112 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 17118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 17127 i_sck$SB_IO_IN
+.sym 17129 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 17130 tx_fifo.full_o_SB_LUT4_I1_O[1]
+.sym 17131 i_ss$SB_IO_IN
+.sym 17133 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 17134 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 17137 w_tx_fifo_full
+.sym 17138 tx_fifo.wr_addr[1]
+.sym 17139 i_ss$SB_IO_IN
+.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 17141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 17143 tx_fifo.full_o_SB_LUT4_I1_O[2]
+.sym 17144 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 17145 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 17147 tx_fifo.full_o_SB_LUT4_I1_O[0]
+.sym 17148 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 17154 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 17160 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 17161 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 17162 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 17163 i_ss$SB_IO_IN
+.sym 17174 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 17178 w_tx_fifo_full
+.sym 17180 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 17181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 17186 tx_fifo.wr_addr[1]
+.sym 17187 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 17190 tx_fifo.full_o_SB_LUT4_I1_O[1]
+.sym 17191 tx_fifo.full_o_SB_LUT4_I1_O[2]
+.sym 17193 tx_fifo.full_o_SB_LUT4_I1_O[0]
+.sym 17196 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 17198 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 17199 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 17204 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 17206 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 17207 i_sck$SB_IO_IN
+.sym 17208 i_ss$SB_IO_IN
+.sym 17209 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 17210 smi_ctrl_ins.r_fifo_pulled_data[17]
+.sym 17212 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 17213 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 17214 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 17216 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 17219 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
+.sym 17223 w_rx_fifo_pulled_data[16]
+.sym 17227 i_sck$SB_IO_IN
+.sym 17232 rx_fifo.wr_addr[8]
+.sym 17234 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 17236 spi_if_ins.w_rx_data[6]
+.sym 17238 $PACKER_VCC_NET
+.sym 17240 w_smi_data_direction
+.sym 17243 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17250 spi_if_ins.spi.r3_rx_done
+.sym 17252 spi_if_ins.spi.r_rx_done
+.sym 17254 tx_fifo.rd_addr_gray_wr[9]
+.sym 17259 i_ss$SB_IO_IN
+.sym 17260 tx_fifo.rd_addr_gray_wr[0]
+.sym 17264 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 17273 spi_if_ins.spi.r2_rx_done
+.sym 17284 spi_if_ins.spi.r2_rx_done
+.sym 17297 spi_if_ins.spi.r3_rx_done
+.sym 17298 spi_if_ins.spi.r2_rx_done
+.sym 17307 i_ss$SB_IO_IN
+.sym 17308 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 17316 tx_fifo.rd_addr_gray_wr[9]
+.sym 17320 tx_fifo.rd_addr_gray_wr[0]
+.sym 17328 spi_if_ins.spi.r_rx_done
 .sym 17330 r_counter_$glb_clk
-.sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 17332 spi_if_ins.spi.r_rx_byte[5]
-.sym 17333 spi_if_ins.spi.r_rx_byte[1]
-.sym 17334 spi_if_ins.spi.r_rx_byte[7]
-.sym 17335 spi_if_ins.spi.r_rx_byte[0]
-.sym 17336 spi_if_ins.spi.r_rx_byte[2]
-.sym 17337 spi_if_ins.spi.r_rx_byte[6]
-.sym 17338 spi_if_ins.spi.r_rx_byte[4]
-.sym 17339 spi_if_ins.spi.r_rx_byte[3]
-.sym 17342 w_rx_data[4]
-.sym 17347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17348 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 17351 i_ss$SB_IO_IN
-.sym 17358 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17359 $PACKER_VCC_NET
-.sym 17364 i_rst_b$SB_IO_IN
-.sym 17384 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17390 spi_if_ins.spi.r_rx_byte[1]
-.sym 17397 spi_if_ins.spi.r_rx_byte[5]
-.sym 17400 spi_if_ins.spi.r_rx_byte[0]
-.sym 17401 spi_if_ins.spi.r_rx_byte[2]
-.sym 17402 spi_if_ins.spi.r_rx_byte[6]
-.sym 17403 spi_if_ins.spi.r_rx_byte[4]
-.sym 17407 spi_if_ins.spi.r_rx_byte[1]
-.sym 17419 spi_if_ins.spi.r_rx_byte[2]
-.sym 17426 spi_if_ins.spi.r_rx_byte[4]
-.sym 17436 spi_if_ins.spi.r_rx_byte[5]
-.sym 17444 spi_if_ins.spi.r_rx_byte[6]
-.sym 17449 spi_if_ins.spi.r_rx_byte[0]
-.sym 17452 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17332 spi_if_ins.spi.r_rx_byte[0]
+.sym 17333 spi_if_ins.spi.r_rx_byte[7]
+.sym 17334 spi_if_ins.spi.r_rx_byte[2]
+.sym 17335 spi_if_ins.spi.r_rx_byte[4]
+.sym 17336 spi_if_ins.spi.r_rx_byte[5]
+.sym 17337 spi_if_ins.spi.r_rx_byte[3]
+.sym 17338 spi_if_ins.spi.r_rx_byte[1]
+.sym 17339 spi_if_ins.spi.r_rx_byte[6]
+.sym 17344 rx_fifo.rd_addr[0]
+.sym 17346 rx_fifo.rd_addr[5]
+.sym 17347 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 17350 tx_fifo.rd_addr_gray_wr[9]
+.sym 17351 $PACKER_VCC_NET
+.sym 17357 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17362 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 17363 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17377 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17383 tx_fifo.rd_addr_gray[0]
+.sym 17421 tx_fifo.rd_addr_gray[0]
+.sym 17427 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
 .sym 17453 r_counter_$glb_clk
-.sym 17455 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 17456 spi_if_ins.state_if[0]
-.sym 17457 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17458 spi_if_ins.state_if[1]
-.sym 17459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
-.sym 17460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 17461 spi_if_ins.state_if_SB_DFFESR_Q_E
-.sym 17462 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17466 w_rx_data[7]
-.sym 17467 spi_if_ins.w_rx_data[1]
-.sym 17468 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 17469 w_rx_fifo_pulled_data[28]
-.sym 17470 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 17472 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 17455 spi_if_ins.w_rx_data[2]
+.sym 17456 spi_if_ins.w_rx_data[6]
+.sym 17457 spi_if_ins.w_rx_data[0]
+.sym 17458 spi_if_ins.w_rx_data[4]
+.sym 17459 spi_if_ins.w_rx_data[5]
+.sym 17460 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 17461 spi_if_ins.w_rx_data[1]
+.sym 17462 spi_if_ins.w_rx_data[3]
+.sym 17468 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 17469 rx_fifo.wr_addr[9]
+.sym 17470 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 17471 rx_fifo.wr_addr[4]
+.sym 17472 spi_if_ins.spi.r_temp_rx_byte[5]
 .sym 17473 i_sck$SB_IO_IN
-.sym 17474 rx_fifo.mem_i.0.3_WDATA_3
-.sym 17475 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17478 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 17480 w_rx_data[1]
-.sym 17481 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17482 spi_if_ins.w_rx_data[4]
-.sym 17485 $PACKER_VCC_NET
-.sym 17486 w_rx_data[4]
-.sym 17488 w_rx_data[7]
-.sym 17490 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 17503 spi_if_ins.spi.r_rx_byte[3]
-.sym 17504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 17506 spi_if_ins.spi.r_rx_byte[7]
-.sym 17507 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17510 i_rst_b$SB_IO_IN
-.sym 17512 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 17515 spi_if_ins.state_if[1]
-.sym 17518 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17519 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17521 spi_if_ins.state_if[0]
-.sym 17522 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17527 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 17530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17531 spi_if_ins.state_if[0]
-.sym 17532 spi_if_ins.state_if[1]
-.sym 17537 spi_if_ins.spi.r_rx_byte[3]
-.sym 17542 spi_if_ins.spi.r_rx_byte[7]
-.sym 17553 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 17554 i_rst_b$SB_IO_IN
-.sym 17555 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 17559 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 17560 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17561 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17566 i_rst_b$SB_IO_IN
-.sym 17567 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17568 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 17571 spi_if_ins.state_if[1]
-.sym 17573 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17574 spi_if_ins.state_if[0]
-.sym 17575 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17476 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 17478 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 17486 spi_if_ins.w_rx_data[3]
+.sym 17488 spi_if_ins.w_rx_data[2]
+.sym 17489 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 17490 spi_if_ins.w_rx_data[6]
+.sym 17496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
+.sym 17498 spi_if_ins.spi.r_tx_byte[2]
+.sym 17499 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 17501 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
+.sym 17503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
+.sym 17505 w_tx_fifo_full
+.sym 17506 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 17507 spi_if_ins.spi.r_tx_byte[3]
+.sym 17508 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17509 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
+.sym 17514 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 17516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
+.sym 17521 w_smi_read_req
+.sym 17522 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 17523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
+.sym 17524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 17525 o_led0_SB_LUT4_I1_O[1]
+.sym 17531 w_tx_fifo_full
+.sym 17536 w_smi_read_req
+.sym 17544 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 17547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
+.sym 17548 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
+.sym 17549 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 17553 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
+.sym 17554 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
+.sym 17555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
+.sym 17556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 17559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
+.sym 17560 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 17571 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17572 spi_if_ins.spi.r_tx_byte[3]
+.sym 17574 spi_if_ins.spi.r_tx_byte[2]
+.sym 17575 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
 .sym 17576 r_counter_$glb_clk
-.sym 17579 $PACKER_VCC_NET
-.sym 17580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 17581 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
-.sym 17582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 17583 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
-.sym 17584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 17585 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 17590 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 17592 w_rx_fifo_pulled_data[29]
-.sym 17596 i_glob_clock$SB_IO_IN
-.sym 17600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 17601 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 17604 w_rx_data[3]
-.sym 17605 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 17606 w_rx_data[1]
-.sym 17607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 17609 w_ioc[1]
-.sym 17611 w_cs[0]
-.sym 17612 w_rx_data[4]
-.sym 17620 spi_if_ins.w_rx_data[3]
-.sym 17621 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 17623 spi_if_ins.w_rx_data[6]
-.sym 17627 spi_if_ins.w_rx_data[1]
-.sym 17629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17630 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17633 i_rst_b$SB_IO_IN
-.sym 17634 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17642 spi_if_ins.w_rx_data[4]
-.sym 17646 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 17652 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17654 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 17655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17658 spi_if_ins.w_rx_data[4]
-.sym 17666 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 17670 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17671 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17676 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 17677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 17678 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 17679 i_rst_b$SB_IO_IN
-.sym 17682 spi_if_ins.w_rx_data[3]
-.sym 17691 spi_if_ins.w_rx_data[1]
-.sym 17697 spi_if_ins.w_rx_data[6]
-.sym 17698 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17577 o_led0_SB_LUT4_I1_O[1]
+.sym 17580 spi_if_ins.spi.r_tx_byte[7]
+.sym 17581 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17582 spi_if_ins.spi.r_tx_byte[5]
+.sym 17583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
+.sym 17593 rx_fifo.rd_addr[5]
+.sym 17599 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 17600 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 17601 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 17602 spi_if_ins.w_rx_data[0]
+.sym 17604 spi_if_ins.w_rx_data[4]
+.sym 17606 spi_if_ins.w_rx_data[5]
+.sym 17608 o_led0_SB_LUT4_I1_O[1]
+.sym 17610 w_rx_data[4]
+.sym 17613 i_button_SB_LUT4_I0_O[1]
+.sym 17623 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 17631 spi_if_ins.spi.r_tx_byte[6]
+.sym 17635 spi_if_ins.r_tx_byte[1]
+.sym 17638 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 17639 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17640 spi_if_ins.r_tx_byte[2]
+.sym 17641 spi_if_ins.r_tx_byte[3]
+.sym 17642 spi_if_ins.r_tx_byte[6]
+.sym 17643 spi_if_ins.r_tx_byte[0]
+.sym 17644 spi_if_ins.spi.r_tx_byte[4]
+.sym 17646 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17647 spi_if_ins.r_tx_byte[4]
+.sym 17649 spi_if_ins.spi.r_tx_byte[1]
+.sym 17650 spi_if_ins.spi.r_tx_byte[0]
+.sym 17652 spi_if_ins.spi.r_tx_byte[4]
+.sym 17653 spi_if_ins.spi.r_tx_byte[6]
+.sym 17654 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 17658 spi_if_ins.r_tx_byte[4]
+.sym 17667 spi_if_ins.r_tx_byte[2]
+.sym 17673 spi_if_ins.r_tx_byte[3]
+.sym 17677 spi_if_ins.r_tx_byte[6]
+.sym 17682 spi_if_ins.spi.r_tx_byte[1]
+.sym 17683 spi_if_ins.spi.r_tx_byte[0]
+.sym 17685 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17690 spi_if_ins.r_tx_byte[1]
+.sym 17694 spi_if_ins.r_tx_byte[0]
+.sym 17698 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
 .sym 17699 r_counter_$glb_clk
-.sym 17701 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
-.sym 17702 spi_if_ins.spi.r_tx_byte[7]
-.sym 17703 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
-.sym 17704 spi_if_ins.spi.r_tx_byte[5]
-.sym 17705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 17706 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 17707 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
-.sym 17708 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
-.sym 17713 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
-.sym 17714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 17719 w_rx_data[0]
-.sym 17720 w_fetch
-.sym 17721 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 17722 $PACKER_VCC_NET
-.sym 17724 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
-.sym 17732 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 17735 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 17736 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 17743 spi_if_ins.w_rx_data[2]
-.sym 17744 spi_if_ins.w_rx_data[3]
-.sym 17745 spi_if_ins.w_rx_data[0]
-.sym 17746 w_ioc[3]
-.sym 17752 spi_if_ins.w_rx_data[4]
-.sym 17753 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 17755 spi_if_ins.w_rx_data[1]
-.sym 17760 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 17769 w_ioc[4]
-.sym 17772 w_ioc[2]
-.sym 17775 w_ioc[4]
-.sym 17777 w_ioc[3]
-.sym 17778 w_ioc[2]
-.sym 17782 spi_if_ins.w_rx_data[1]
-.sym 17789 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 17795 spi_if_ins.w_rx_data[4]
-.sym 17799 spi_if_ins.w_rx_data[3]
-.sym 17807 spi_if_ins.w_rx_data[0]
-.sym 17812 spi_if_ins.w_rx_data[2]
-.sym 17817 w_ioc[2]
-.sym 17818 w_ioc[3]
-.sym 17820 w_ioc[4]
+.sym 17700 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 17701 w_rx_data[1]
+.sym 17702 o_led0_SB_LUT4_I1_O[1]
+.sym 17703 w_rx_data[4]
+.sym 17704 w_rx_data[7]
+.sym 17705 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 17706 w_rx_data[3]
+.sym 17707 w_rx_data[0]
+.sym 17708 w_rx_data[5]
+.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 17720 io_pmod_out[1]$SB_IO_OUT
+.sym 17723 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 17725 i_glob_clock$SB_IO_IN
+.sym 17726 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+.sym 17728 spi_if_ins.r_tx_byte[6]
+.sym 17729 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 17730 w_rx_data[0]
+.sym 17731 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17732 spi_if_ins.r_tx_byte[5]
+.sym 17734 w_rx_data[1]
+.sym 17735 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 17736 spi_if_ins.w_rx_data[6]
+.sym 17742 w_ioc[2]
+.sym 17744 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 17748 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 17749 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
+.sym 17751 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 17754 w_ioc[4]
+.sym 17756 spi_if_ins.w_rx_data[3]
+.sym 17758 spi_if_ins.w_rx_data[2]
+.sym 17761 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 17762 spi_if_ins.w_rx_data[0]
+.sym 17764 spi_if_ins.w_rx_data[4]
+.sym 17773 w_ioc[3]
+.sym 17777 spi_if_ins.w_rx_data[2]
+.sym 17782 w_ioc[2]
+.sym 17783 w_ioc[4]
+.sym 17784 w_ioc[3]
+.sym 17793 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 17796 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 17801 spi_if_ins.w_rx_data[4]
+.sym 17806 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 17807 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
+.sym 17813 spi_if_ins.w_rx_data[0]
+.sym 17819 spi_if_ins.w_rx_data[3]
 .sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E
 .sym 17822 r_counter_$glb_clk
-.sym 17824 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
-.sym 17825 spi_if_ins.spi.r_tx_byte[6]
-.sym 17826 spi_if_ins.spi.r_tx_byte[2]
-.sym 17827 spi_if_ins.spi.r_tx_byte[0]
-.sym 17828 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
-.sym 17829 spi_if_ins.spi.r_tx_byte[1]
-.sym 17830 spi_if_ins.spi.r_tx_byte[4]
-.sym 17831 spi_if_ins.spi.r_tx_byte[3]
-.sym 17837 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 17838 w_ioc[0]
-.sym 17840 w_ioc[1]
-.sym 17842 w_load
-.sym 17848 spi_if_ins.r_tx_byte[5]
-.sym 17849 w_fetch
-.sym 17850 w_load
-.sym 17855 w_ioc[0]
-.sym 17856 i_rst_b$SB_IO_IN
-.sym 17859 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 17869 r_tx_data[0]
-.sym 17870 r_tx_data[2]
-.sym 17871 r_tx_data[1]
-.sym 17873 r_tx_data[6]
+.sym 17824 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 17825 w_cs[1]
+.sym 17827 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 17828 w_cs[3]
+.sym 17829 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 17830 w_cs[2]
+.sym 17831 o_led1_SB_LUT4_I1_I3[3]
+.sym 17836 w_fetch
+.sym 17837 w_rx_data[0]
+.sym 17839 w_rx_data[7]
+.sym 17840 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 17843 w_rx_data[1]
+.sym 17844 i_button_SB_LUT4_I0_O[1]
+.sym 17845 o_led0_SB_LUT4_I1_O[1]
+.sym 17848 w_rx_data[4]
+.sym 17850 io_ctrl_ins.pmod_dir_state[7]
+.sym 17851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 17852 i_button_SB_LUT4_I0_I3[2]
+.sym 17854 w_rx_data[3]
+.sym 17856 w_rx_data[0]
+.sym 17857 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 17858 w_rx_data[5]
+.sym 17859 w_cs[1]
+.sym 17866 r_tx_data[1]
+.sym 17867 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 17868 r_tx_data[6]
+.sym 17871 r_tx_data[4]
+.sym 17872 r_tx_data[3]
+.sym 17873 r_tx_data[5]
+.sym 17874 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
 .sym 17875 w_cs[0]
-.sym 17878 r_tx_data[7]
-.sym 17883 w_cs[1]
-.sym 17889 w_cs[3]
-.sym 17892 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 17894 w_cs[2]
-.sym 17904 r_tx_data[2]
-.sym 17910 r_tx_data[1]
-.sym 17916 w_cs[3]
-.sym 17917 w_cs[1]
-.sym 17918 w_cs[0]
-.sym 17919 w_cs[2]
-.sym 17922 r_tx_data[0]
-.sym 17931 r_tx_data[7]
-.sym 17934 w_cs[2]
-.sym 17935 w_cs[3]
-.sym 17936 w_cs[1]
-.sym 17937 w_cs[0]
-.sym 17942 r_tx_data[6]
-.sym 17944 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17879 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 17882 w_cs[1]
+.sym 17885 w_cs[3]
+.sym 17887 w_cs[2]
+.sym 17893 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 17898 w_cs[2]
+.sym 17899 w_cs[1]
+.sym 17900 w_cs[3]
+.sym 17901 w_cs[0]
+.sym 17906 r_tx_data[5]
+.sym 17912 r_tx_data[4]
+.sym 17918 r_tx_data[3]
+.sym 17923 r_tx_data[1]
+.sym 17935 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 17936 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 17937 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 17940 r_tx_data[6]
+.sym 17944 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
 .sym 17945 r_counter_$glb_clk
-.sym 17949 spi_if_ins.r_tx_byte[4]
-.sym 17952 spi_if_ins.r_tx_byte[3]
-.sym 17953 spi_if_ins.r_tx_byte[5]
-.sym 17960 $PACKER_GND_NET
-.sym 17961 spi_if_ins.r_tx_byte[7]
-.sym 17964 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 17969 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 17972 i_glob_clock$SB_IO_IN
-.sym 17973 w_rx_data[1]
-.sym 17975 i_config[2]$SB_IO_IN
-.sym 17976 w_rx_data[7]
-.sym 17977 w_tx_data_io[7]
-.sym 17978 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 17981 w_tx_data_io[5]
-.sym 17988 i_glob_clock$SB_IO_IN
-.sym 17989 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
-.sym 17993 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
-.sym 17995 w_tx_data_io[7]
-.sym 17996 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
-.sym 17997 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
-.sym 17998 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
-.sym 17999 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 18000 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
-.sym 18005 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-.sym 18006 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 18007 w_tx_data_io[5]
-.sym 18009 w_fetch
-.sym 18011 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
-.sym 18013 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 18015 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 18016 i_rst_b$SB_IO_IN
-.sym 18018 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
-.sym 18019 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
-.sym 18021 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 18022 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+.sym 17947 o_led1_SB_LUT4_I1_O[3]
+.sym 17948 o_led1_SB_LUT4_I1_I3[0]
+.sym 17949 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+.sym 17950 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 17951 io_ctrl_ins.pmod_dir_state[1]
+.sym 17952 io_ctrl_ins.pmod_dir_state[5]
+.sym 17953 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 17954 io_ctrl_ins.pmod_dir_state[7]
+.sym 17960 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 17961 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
+.sym 17964 o_led1_SB_LUT4_I1_I3[3]
+.sym 17966 w_fetch
+.sym 17967 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 17968 r_tx_data[3]
+.sym 17972 w_rx_data[7]
+.sym 17973 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 17974 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 17976 w_load
+.sym 17979 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 17980 i_button_SB_LUT4_I0_I3[2]
+.sym 17982 w_load
+.sym 17988 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
+.sym 17989 w_cs[1]
+.sym 17990 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 17991 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
+.sym 17992 w_cs[3]
+.sym 17993 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 17994 i_button_SB_LUT4_I0_I3[3]
+.sym 17995 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
+.sym 17996 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+.sym 17997 i_glob_clock$SB_IO_IN
+.sym 17999 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 18000 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 18001 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 18002 w_cs[2]
+.sym 18003 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 18005 i_button$SB_IO_IN
+.sym 18006 w_cs[0]
+.sym 18007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 18010 io_ctrl_ins.pmod_dir_state[7]
+.sym 18011 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+.sym 18012 i_button_SB_LUT4_I0_I3[2]
+.sym 18018 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 18019 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18021 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
+.sym 18022 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
 .sym 18023 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 18024 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
-.sym 18028 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 18029 w_tx_data_io[7]
-.sym 18030 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 18033 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 18034 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
-.sym 18035 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 18036 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-.sym 18039 w_fetch
-.sym 18041 i_rst_b$SB_IO_IN
-.sym 18045 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
-.sym 18047 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 18048 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
-.sym 18052 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
-.sym 18053 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
-.sym 18054 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 18028 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 18029 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
+.sym 18030 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 18034 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 18035 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18036 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 18039 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 18040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 18041 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+.sym 18042 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 18045 i_button_SB_LUT4_I0_I3[3]
+.sym 18046 i_button$SB_IO_IN
+.sym 18047 io_ctrl_ins.pmod_dir_state[7]
+.sym 18048 i_button_SB_LUT4_I0_I3[2]
+.sym 18051 w_cs[2]
+.sym 18052 w_cs[3]
+.sym 18053 w_cs[1]
+.sym 18054 w_cs[0]
 .sym 18057 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
 .sym 18058 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
 .sym 18059 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
 .sym 18060 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
-.sym 18064 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 18065 w_tx_data_io[5]
-.sym 18066 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
+.sym 18063 w_cs[1]
+.sym 18064 w_cs[3]
+.sym 18065 w_cs[2]
+.sym 18066 w_cs[0]
 .sym 18067 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
 .sym 18068 i_glob_clock$SB_IO_IN
-.sym 18072 o_led1_SB_DFFER_Q_E
-.sym 18073 io_ctrl_ins.pmod_dir_state[0]
-.sym 18075 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 18094 o_tr_vc2$SB_IO_OUT
-.sym 18097 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
-.sym 18100 w_rx_data[4]
-.sym 18103 w_rx_data[1]
-.sym 18104 w_rx_data[3]
-.sym 18114 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 18115 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18117 w_rx_data[2]
-.sym 18119 w_cs[1]
-.sym 18121 w_rx_data[5]
-.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 18125 w_ioc[0]
-.sym 18126 w_ioc[1]
-.sym 18128 o_led1_SB_LUT4_I1_I2[3]
-.sym 18129 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 18137 w_rx_data[3]
-.sym 18141 w_rx_data[6]
-.sym 18145 w_rx_data[5]
-.sym 18150 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 18152 w_ioc[0]
-.sym 18153 w_ioc[1]
-.sym 18157 w_rx_data[6]
-.sym 18162 w_ioc[0]
-.sym 18163 w_ioc[1]
-.sym 18164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 18168 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 18169 o_led1_SB_LUT4_I1_I2[3]
-.sym 18170 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18171 w_cs[1]
-.sym 18181 w_rx_data[3]
-.sym 18189 w_rx_data[2]
-.sym 18190 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 18070 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 18071 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
+.sym 18072 i_button_SB_LUT4_I0_I3[1]
+.sym 18073 io_ctrl_ins.pmod_dir_state[3]
+.sym 18074 o_led1_SB_LUT4_I1_I2[1]
+.sym 18075 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 18076 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 18077 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 18085 w_rx_data[2]
+.sym 18088 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 18089 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 18092 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
+.sym 18093 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 18094 o_led1$SB_IO_OUT
+.sym 18095 w_rx_data[4]
+.sym 18096 o_led0_SB_LUT4_I1_O[1]
+.sym 18097 w_cs[1]
+.sym 18099 o_led1_SB_LUT4_I1_O[0]
+.sym 18101 i_button_SB_LUT4_I0_O[1]
+.sym 18105 o_led0_SB_LUT4_I1_O[0]
+.sym 18112 o_led0_SB_LUT4_I1_O[0]
+.sym 18113 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 18114 io_pmod_out[1]$SB_IO_OUT
+.sym 18115 o_led0_SB_LUT4_I1_O[1]
+.sym 18116 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 18117 w_tx_data_smi[1]
+.sym 18118 o_led0_SB_LUT4_I1_O[3]
+.sym 18119 o_led1_SB_LUT4_I1_O[3]
+.sym 18120 io_pmod_out[0]$SB_IO_OUT
+.sym 18121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 18123 o_led1_SB_LUT4_I1_O[0]
+.sym 18124 o_shdn_rx_lna$SB_IO_OUT
+.sym 18125 io_ctrl_ins.mixer_en_state
+.sym 18126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 18127 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 18128 w_tx_data_io[0]
+.sym 18129 o_led1_SB_LUT4_I1_O[2]
+.sym 18131 o_led0_SB_LUT4_I1_O[2]
+.sym 18132 w_tx_data_io[1]
+.sym 18134 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
+.sym 18136 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
+.sym 18137 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 18139 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 18140 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 18145 w_tx_data_io[0]
+.sym 18146 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 18147 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 18150 o_led0_SB_LUT4_I1_O[0]
+.sym 18151 o_led0_SB_LUT4_I1_O[2]
+.sym 18152 o_led0_SB_LUT4_I1_O[3]
+.sym 18153 o_led0_SB_LUT4_I1_O[1]
+.sym 18156 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 18157 io_pmod_out[1]$SB_IO_OUT
+.sym 18158 o_shdn_rx_lna$SB_IO_OUT
+.sym 18159 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18162 w_tx_data_io[1]
+.sym 18163 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 18164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 18165 w_tx_data_smi[1]
+.sym 18168 io_pmod_out[0]$SB_IO_OUT
+.sym 18169 io_ctrl_ins.mixer_en_state
+.sym 18170 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 18171 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18174 o_led1_SB_LUT4_I1_O[0]
+.sym 18175 o_led1_SB_LUT4_I1_O[2]
+.sym 18176 o_led1_SB_LUT4_I1_O[3]
+.sym 18177 o_led0_SB_LUT4_I1_O[1]
+.sym 18180 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
+.sym 18181 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 18183 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
+.sym 18186 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 18187 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 18188 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
 .sym 18191 r_counter_$glb_clk
-.sym 18193 o_led1_SB_LUT4_I1_I2[1]
-.sym 18194 io_ctrl_ins.pmod_dir_state[7]
-.sym 18195 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 18196 i_config_SB_LUT4_I0_1_O[2]
-.sym 18197 o_led1_SB_LUT4_I1_O[3]
-.sym 18199 o_led0_SB_LUT4_I1_O[3]
-.sym 18200 io_ctrl_ins.pmod_dir_state[1]
-.sym 18205 w_cs[1]
-.sym 18211 w_rx_data[0]
-.sym 18212 o_rx_h_tx_l$SB_IO_OUT
-.sym 18216 o_led1_SB_DFFER_Q_E
-.sym 18234 io_ctrl_ins.pmod_dir_state[5]
-.sym 18235 o_led1_SB_LUT4_I1_I2[3]
-.sym 18236 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18237 o_led1_SB_LUT4_I1_I2[2]
-.sym 18238 o_rx_h_tx_l$SB_IO_OUT
-.sym 18240 o_tr_vc1$SB_IO_OUT
-.sym 18242 i_config_SB_LUT4_I0_1_O[1]
-.sym 18244 io_ctrl_ins.pmod_dir_state[6]
-.sym 18246 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
-.sym 18247 i_config[2]$SB_IO_IN
-.sym 18248 i_button$SB_IO_IN
-.sym 18249 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 18251 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
-.sym 18252 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 18254 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18256 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
-.sym 18259 io_ctrl_ins.pmod_dir_state[7]
-.sym 18260 w_ioc[0]
-.sym 18263 i_config[3]$SB_IO_IN
-.sym 18265 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 18268 w_ioc[0]
-.sym 18269 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 18273 i_config_SB_LUT4_I0_1_O[1]
-.sym 18274 io_ctrl_ins.pmod_dir_state[7]
-.sym 18275 o_led1_SB_LUT4_I1_I2[2]
-.sym 18276 o_rx_h_tx_l$SB_IO_OUT
-.sym 18279 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18280 o_led1_SB_LUT4_I1_I2[3]
-.sym 18281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18285 i_button$SB_IO_IN
-.sym 18286 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18287 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
-.sym 18291 io_ctrl_ins.pmod_dir_state[5]
-.sym 18292 i_config_SB_LUT4_I0_1_O[1]
-.sym 18293 o_tr_vc1$SB_IO_OUT
-.sym 18294 o_led1_SB_LUT4_I1_I2[2]
-.sym 18298 i_config[2]$SB_IO_IN
-.sym 18299 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
-.sym 18300 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18303 i_config[3]$SB_IO_IN
-.sym 18304 o_led1_SB_LUT4_I1_I2[2]
-.sym 18305 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 18306 io_ctrl_ins.pmod_dir_state[6]
-.sym 18310 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
-.sym 18311 i_config_SB_LUT4_I0_1_O[1]
-.sym 18312 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 18313 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 18192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 18193 io_ctrl_ins.rf_pin_state[3]
+.sym 18194 io_ctrl_ins.rf_pin_state[5]
+.sym 18195 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
+.sym 18196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
+.sym 18197 io_ctrl_ins.rf_pin_state[6]
+.sym 18198 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 18199 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 18200 io_ctrl_ins.rf_pin_state[7]
+.sym 18206 io_pmod_out[0]$SB_IO_OUT
+.sym 18208 io_pmod_out[3]$SB_IO_OUT
+.sym 18209 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 18210 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 18213 i_button_SB_LUT4_I0_I3[3]
+.sym 18216 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 18217 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 18218 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+.sym 18219 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 18223 w_rx_data[0]
+.sym 18226 w_rx_data[1]
+.sym 18234 io_ctrl_ins.rf_pin_state[4]
+.sym 18236 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 18238 io_ctrl_ins.rf_pin_state[1]
+.sym 18243 io_ctrl_ins.rf_pin_state[2]
+.sym 18247 io_ctrl_ins.rf_pin_state[0]
+.sym 18249 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 18250 io_ctrl_ins.rf_pin_state[3]
+.sym 18251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18254 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18256 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 18257 io_ctrl_ins.rf_pin_state[7]
+.sym 18258 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18259 io_ctrl_ins.rf_pin_state[5]
+.sym 18262 io_ctrl_ins.rf_pin_state[6]
+.sym 18267 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18268 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18269 io_ctrl_ins.rf_pin_state[3]
+.sym 18270 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18273 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18274 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18275 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18276 io_ctrl_ins.rf_pin_state[2]
+.sym 18280 io_ctrl_ins.rf_pin_state[7]
+.sym 18281 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 18282 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18285 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18286 io_ctrl_ins.rf_pin_state[4]
+.sym 18287 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18288 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 18291 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 18292 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18294 io_ctrl_ins.rf_pin_state[6]
+.sym 18297 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18299 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18300 io_ctrl_ins.rf_pin_state[1]
+.sym 18303 io_ctrl_ins.rf_pin_state[0]
+.sym 18304 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18305 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18306 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18309 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18310 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 18311 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18312 io_ctrl_ins.rf_pin_state[5]
+.sym 18313 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
 .sym 18314 r_counter_$glb_clk
-.sym 18317 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
-.sym 18318 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
-.sym 18328 o_led0$SB_IO_OUT
-.sym 18331 o_led1$SB_IO_OUT
-.sym 18336 i_button$SB_IO_IN
-.sym 18340 i_rst_b$SB_IO_IN
-.sym 18341 i_config[1]$SB_IO_IN
-.sym 18345 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 18347 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 18358 io_ctrl_ins.rf_pin_state[7]
-.sym 18359 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18360 io_ctrl_ins.rf_pin_state[5]
-.sym 18361 io_ctrl_ins.rf_pin_state[1]
-.sym 18364 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18365 io_ctrl_ins.rf_pin_state[4]
-.sym 18366 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18367 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
-.sym 18368 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
-.sym 18370 io_ctrl_ins.rf_pin_state[6]
-.sym 18371 io_ctrl_ins.rf_pin_state[3]
-.sym 18372 io_ctrl_ins.rf_pin_state[2]
-.sym 18379 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18381 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 18387 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18390 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18391 io_ctrl_ins.rf_pin_state[3]
-.sym 18392 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18393 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 18396 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
-.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18398 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 18399 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18402 io_ctrl_ins.rf_pin_state[2]
-.sym 18403 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 18404 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 18409 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18410 io_ctrl_ins.rf_pin_state[4]
-.sym 18411 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18414 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18415 io_ctrl_ins.rf_pin_state[7]
-.sym 18417 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18421 io_ctrl_ins.rf_pin_state[1]
-.sym 18422 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 18423 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18426 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18428 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18429 io_ctrl_ins.rf_pin_state[5]
-.sym 18432 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18433 io_ctrl_ins.rf_pin_state[6]
-.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 18436 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 18316 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18317 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18318 o_led1_SB_LUT4_I1_O[0]
+.sym 18319 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
+.sym 18320 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18321 o_led0_SB_LUT4_I1_O[0]
+.sym 18323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 18328 o_tr_vc2$SB_IO_OUT
+.sym 18332 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 18334 o_rx_h_tx_l$SB_IO_OUT
+.sym 18335 o_led0_SB_LUT4_I1_O[3]
+.sym 18338 w_fetch
+.sym 18340 w_rx_data[4]
+.sym 18344 w_rx_data[0]
+.sym 18345 i_config[2]$SB_IO_IN
+.sym 18346 w_rx_data[5]
+.sym 18357 i_rst_b$SB_IO_IN
+.sym 18359 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.sym 18365 w_rx_data[4]
+.sym 18367 w_rx_data[2]
+.sym 18370 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 18374 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18375 o_led1_SB_LUT4_I1_O[0]
+.sym 18377 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18378 o_led0_SB_LUT4_I1_O[0]
+.sym 18381 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18383 w_rx_data[0]
+.sym 18384 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 18386 w_rx_data[1]
+.sym 18388 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 18393 w_rx_data[4]
+.sym 18398 w_rx_data[2]
+.sym 18402 i_rst_b$SB_IO_IN
+.sym 18403 o_led0_SB_LUT4_I1_O[0]
+.sym 18404 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18405 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18409 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 18414 w_rx_data[1]
+.sym 18420 w_rx_data[0]
+.sym 18426 o_led1_SB_LUT4_I1_O[0]
+.sym 18428 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.sym 18432 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 18433 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 18434 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 18436 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
 .sym 18437 r_counter_$glb_clk
-.sym 18453 o_shdn_rx_lna$SB_IO_OUT
-.sym 18459 o_tr_vc1_b$SB_IO_OUT
-.sym 18464 o_shdn_tx_lna$SB_IO_OUT
-.sym 18471 i_config[2]$SB_IO_IN
-.sym 18480 w_rx_data[1]
-.sym 18482 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
-.sym 18483 w_rx_data[0]
-.sym 18490 w_rx_data[3]
-.sym 18503 w_rx_data[5]
-.sym 18505 w_rx_data[6]
-.sym 18507 w_rx_data[2]
-.sym 18509 w_rx_data[4]
-.sym 18511 w_rx_data[7]
-.sym 18515 w_rx_data[4]
-.sym 18522 w_rx_data[7]
+.sym 18439 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+.sym 18454 o_tr_vc1_b$SB_IO_OUT
+.sym 18460 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 18482 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 18487 w_rx_data[2]
+.sym 18488 w_rx_data[6]
+.sym 18496 w_rx_data[1]
+.sym 18500 w_rx_data[4]
+.sym 18504 w_rx_data[0]
+.sym 18506 w_rx_data[5]
+.sym 18514 w_rx_data[5]
+.sym 18521 w_rx_data[2]
 .sym 18528 w_rx_data[0]
-.sym 18533 w_rx_data[5]
-.sym 18539 w_rx_data[1]
-.sym 18546 w_rx_data[6]
-.sym 18552 w_rx_data[3]
-.sym 18556 w_rx_data[2]
-.sym 18559 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 18537 w_rx_data[1]
+.sym 18551 w_rx_data[4]
+.sym 18555 w_rx_data[6]
+.sym 18559 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
 .sym 18560 r_counter_$glb_clk
+.sym 18561 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 18562 i_config[1]$SB_IO_IN
 .sym 18564 i_config[2]$SB_IO_IN
 .sym 18636 w_smi_data_output[4]
 .sym 18638 w_smi_data_direction
+.sym 18639 o_smi_write_req$SB_IO_OUT
 .sym 18642 $PACKER_VCC_NET
-.sym 18647 w_smi_data_output[4]
-.sym 18655 $PACKER_VCC_NET
-.sym 18657 w_smi_data_direction
-.sym 18679 $PACKER_VCC_NET
-.sym 18695 i_mosi$SB_IO_IN
-.sym 18706 tx_fifo.wr_addr[6]
-.sym 18707 tx_fifo.wr_addr[4]
-.sym 18708 tx_fifo.wr_addr[7]
-.sym 18712 tx_fifo.wr_addr[5]
-.sym 18713 tx_fifo.wr_addr[8]
-.sym 18715 tx_fifo.wr_addr[3]
-.sym 18717 tx_fifo.wr_addr[2]
-.sym 18726 tx_fifo.wr_addr[1]
-.sym 18734 tx_fifo.wr_addr[1]
-.sym 18735 $nextpnr_ICESTORM_LC_1$O
-.sym 18737 tx_fifo.wr_addr[1]
-.sym 18741 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 18744 tx_fifo.wr_addr[2]
-.sym 18745 tx_fifo.wr_addr[1]
-.sym 18747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 18749 tx_fifo.wr_addr[3]
-.sym 18751 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 18753 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
-.sym 18755 tx_fifo.wr_addr[4]
-.sym 18757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 18759 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 18762 tx_fifo.wr_addr[5]
-.sym 18763 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
-.sym 18765 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 18768 tx_fifo.wr_addr[6]
-.sym 18769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 18771 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 18773 tx_fifo.wr_addr[7]
-.sym 18775 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 18777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
-.sym 18780 tx_fifo.wr_addr[8]
-.sym 18781 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 18648 w_smi_data_direction
+.sym 18656 w_smi_data_output[4]
+.sym 18657 o_smi_write_req$SB_IO_OUT
+.sym 18658 $PACKER_VCC_NET
+.sym 18694 $PACKER_VCC_NET
+.sym 18696 w_smi_data_direction
+.sym 18704 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 18705 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 18709 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 18714 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 18728 tx_fifo.wr_addr[0]
+.sym 18743 tx_fifo.wr_addr[0]
+.sym 18750 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 18757 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 18780 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 18782 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 18783 r_counter_$glb_clk
+.sym 18784 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 18785 i_smi_soe_se$SB_IO_IN
-.sym 18818 $PACKER_VCC_NET
-.sym 18831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 18835 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 18838 $PACKER_VCC_NET
-.sym 18841 w_smi_data_output[5]
-.sym 18842 w_smi_data_direction
-.sym 18843 rx_fifo.wr_addr[6]
-.sym 18844 w_smi_data_input[7]
+.sym 18800 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 18804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 18818 w_smi_data_input[7]
+.sym 18842 w_smi_data_output[5]
+.sym 18843 $PACKER_VCC_NET
+.sym 18844 tx_fifo.wr_addr[2]
+.sym 18845 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 18846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
 .sym 18848 i_smi_soe_se$SB_IO_IN
-.sym 18849 rx_fifo.wr_addr[1]
-.sym 18850 rx_fifo.wr_addr[3]
-.sym 18853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 18854 rx_fifo.wr_addr[4]
-.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 18861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
-.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 18872 tx_fifo.wr_addr[9]
-.sym 18874 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 18881 tx_fifo.wr_addr[0]
-.sym 18884 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 18885 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 18887 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 18888 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 18889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 18899 tx_fifo.wr_addr[9]
-.sym 18902 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
-.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 18914 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 18931 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 18937 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 18942 tx_fifo.wr_addr[0]
-.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 18946 r_counter_$glb_clk
-.sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 18949 w_rx_fifo_pulled_data[16]
-.sym 18953 w_rx_fifo_pulled_data[18]
+.sym 18868 tx_fifo.wr_addr[2]
+.sym 18869 tx_fifo.wr_addr[6]
+.sym 18871 tx_fifo.wr_addr[3]
+.sym 18872 tx_fifo.wr_addr[4]
+.sym 18873 tx_fifo.wr_addr[7]
+.sym 18878 tx_fifo.wr_addr[5]
+.sym 18880 tx_fifo.wr_addr[8]
+.sym 18881 tx_fifo.wr_addr[1]
+.sym 18898 $nextpnr_ICESTORM_LC_2$O
+.sym 18901 tx_fifo.wr_addr[1]
+.sym 18904 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18906 tx_fifo.wr_addr[2]
+.sym 18908 tx_fifo.wr_addr[1]
+.sym 18910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18912 tx_fifo.wr_addr[3]
+.sym 18914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18918 tx_fifo.wr_addr[4]
+.sym 18920 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18924 tx_fifo.wr_addr[5]
+.sym 18926 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18931 tx_fifo.wr_addr[6]
+.sym 18932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 18936 tx_fifo.wr_addr[7]
+.sym 18938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 18940 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 18943 tx_fifo.wr_addr[8]
+.sym 18944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 18949 w_rx_fifo_pulled_data[12]
+.sym 18953 w_rx_fifo_pulled_data[14]
 .sym 18960 i_ss$SB_IO_IN
-.sym 18964 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 18973 rx_fifo.wr_addr[0]
-.sym 18976 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 18977 w_smi_data_input[7]
-.sym 18978 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 18990 tx_fifo.rd_addr_gray_wr[2]
-.sym 18992 tx_fifo.rd_addr_gray_wr[4]
-.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 18997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 18998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 19002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 19004 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 19005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
-.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 19008 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 19012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 19015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
-.sym 19017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 19018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 19020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 19023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 19024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 19031 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
-.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
-.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 19049 tx_fifo.rd_addr_gray_wr[4]
-.sym 19052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 19055 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 19058 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 19060 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 19064 tx_fifo.rd_addr_gray_wr[2]
+.sym 18978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 18979 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 18981 rx_fifo.wr_addr[6]
+.sym 18983 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 18984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 18990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
+.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 18995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 18996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 18998 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 19000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 19005 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 19006 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 19009 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
+.sym 19011 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
+.sym 19015 tx_fifo.wr_addr[9]
+.sym 19019 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 19020 i_rst_b$SB_IO_IN
+.sym 19023 tx_fifo.wr_addr[9]
+.sym 19025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
+.sym 19034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
+.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
+.sym 19047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 19048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 19053 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 19055 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 19060 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 19065 i_rst_b$SB_IO_IN
+.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
 .sym 19069 r_counter_$glb_clk
-.sym 19072 w_rx_fifo_pulled_data[17]
-.sym 19076 w_rx_fifo_pulled_data[19]
-.sym 19084 tx_fifo.rd_addr_gray_wr[2]
-.sym 19091 rx_fifo.mem_i.0.0_WDATA_2
-.sym 19097 rx_fifo.wr_addr[7]
-.sym 19098 w_rx_fifo_pulled_data[19]
-.sym 19101 w_rx_fifo_pulled_data[18]
-.sym 19103 $PACKER_VCC_NET
-.sym 19106 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 19112 i_sck$SB_IO_IN
-.sym 19116 i_ss$SB_IO_IN
-.sym 19117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 19118 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 19119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 19120 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 19121 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 19134 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19137 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19138 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
-.sym 19144 $nextpnr_ICESTORM_LC_2$O
-.sym 19147 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19150 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
-.sym 19152 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19154 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19158 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19160 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
-.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 19165 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
-.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 19178 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 19183 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 19188 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 19189 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 19192 i_sck$SB_IO_IN
-.sym 19193 i_ss$SB_IO_IN
-.sym 19195 w_rx_fifo_pulled_data[4]
-.sym 19199 w_rx_fifo_pulled_data[6]
-.sym 19206 i_mosi$SB_IO_IN
-.sym 19207 rx_fifo.rd_addr[6]
-.sym 19211 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 19213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 19215 rx_fifo.rd_addr[0]
-.sym 19219 rx_fifo.wr_addr[9]
-.sym 19221 rx_fifo.rd_addr[3]
-.sym 19223 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 19224 $PACKER_VCC_NET
-.sym 19225 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 19226 $PACKER_VCC_NET
-.sym 19227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 19228 w_smi_data_direction
-.sym 19244 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 19072 w_rx_fifo_pulled_data[13]
+.sym 19076 w_rx_fifo_pulled_data[15]
+.sym 19081 w_rx_data[3]
+.sym 19086 rx_fifo.wr_addr[3]
+.sym 19096 rx_fifo.mem_q.0.3_WDATA_2
+.sym 19099 w_smi_read_req
+.sym 19101 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 19106 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 19112 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 19113 smi_ctrl_ins.r_fifo_push_1
+.sym 19114 w_tx_fifo_full
+.sym 19115 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
+.sym 19117 smi_ctrl_ins.r_fifo_push
+.sym 19118 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 19119 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 19120 tx_fifo.wr_addr[2]
+.sym 19122 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
+.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
+.sym 19125 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
+.sym 19126 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
+.sym 19131 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 19132 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 19135 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 19136 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
+.sym 19137 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 19141 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 19142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 19143 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 19145 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 19146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 19147 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 19148 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 19151 smi_ctrl_ins.r_fifo_push
+.sym 19157 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 19158 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 19159 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 19160 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 19163 tx_fifo.wr_addr[2]
+.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 19165 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 19169 w_tx_fifo_full
+.sym 19170 smi_ctrl_ins.r_fifo_push_1
+.sym 19172 smi_ctrl_ins.r_fifo_push
+.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 19178 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 19181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
+.sym 19182 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
+.sym 19183 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
+.sym 19184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
+.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
+.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
+.sym 19192 r_counter_$glb_clk
+.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 19195 w_rx_fifo_pulled_data[16]
+.sym 19199 w_rx_fifo_pulled_data[18]
+.sym 19205 w_rx_data[0]
+.sym 19213 rx_fifo.rd_addr[0]
+.sym 19214 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 19215 rx_fifo.mem_q.0.3_WDATA_1
+.sym 19217 $PACKER_VCC_NET
+.sym 19219 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 19220 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 19221 w_rx_fifo_pulled_data[18]
+.sym 19223 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 19224 o_smi_read_req$SB_IO_OUT
+.sym 19225 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 19227 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 19229 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 19237 w_tx_fifo_full
+.sym 19244 i_sck$SB_IO_IN
 .sym 19245 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19246 spi_if_ins.spi.r_rx_bit_count[0]
 .sym 19248 i_ss$SB_IO_IN
-.sym 19249 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19260 w_rx_fifo_pulled_data[5]
-.sym 19264 w_rx_fifo_pulled_data[7]
-.sym 19280 w_rx_fifo_pulled_data[7]
-.sym 19286 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19287 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19288 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19298 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19299 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19300 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19301 i_ss$SB_IO_IN
-.sym 19304 w_rx_fifo_pulled_data[5]
-.sym 19314 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 19315 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 19316 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 19318 w_rx_fifo_pulled_data[5]
-.sym 19322 w_rx_fifo_pulled_data[7]
-.sym 19337 o_smi_read_req$SB_IO_OUT
-.sym 19341 rx_fifo.wr_addr[1]
-.sym 19342 rx_fifo.wr_addr[5]
-.sym 19343 spi_if_ins.state_if_SB_DFFESR_Q_E
-.sym 19344 rx_fifo.wr_addr[8]
-.sym 19345 i_smi_soe_se$SB_IO_IN
-.sym 19346 rx_fifo.wr_addr[3]
-.sym 19347 rx_fifo.wr_addr[1]
-.sym 19350 rx_fifo.wr_addr[2]
-.sym 19352 rx_fifo.wr_addr[3]
-.sym 19359 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 19366 i_ss$SB_IO_IN
-.sym 19369 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 19397 i_ss$SB_IO_IN
-.sym 19400 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 19411 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 19438 r_counter_$glb_clk
+.sym 19254 w_smi_data_direction
+.sym 19259 w_smi_read_req
+.sym 19260 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19267 $nextpnr_ICESTORM_LC_4$O
+.sym 19270 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19273 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
+.sym 19275 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19277 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19281 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19283 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
+.sym 19289 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19310 w_smi_read_req
+.sym 19312 w_smi_data_direction
+.sym 19313 w_tx_fifo_full
+.sym 19315 i_sck$SB_IO_IN
+.sym 19316 i_ss$SB_IO_IN
+.sym 19318 w_rx_fifo_pulled_data[17]
+.sym 19322 w_rx_fifo_pulled_data[19]
+.sym 19327 w_rx_data[5]
+.sym 19335 rx_fifo.wr_addr[5]
+.sym 19338 rx_fifo.wr_addr[9]
+.sym 19339 rx_fifo.wr_addr[0]
+.sym 19340 rx_fifo.wr_addr[3]
+.sym 19341 $PACKER_VCC_NET
+.sym 19344 w_rx_fifo_pulled_data[29]
+.sym 19347 $PACKER_VCC_NET
+.sym 19350 i_smi_soe_se$SB_IO_IN
+.sym 19352 w_rx_fifo_pulled_data[31]
+.sym 19359 w_rx_fifo_pulled_data[31]
+.sym 19368 w_rx_fifo_pulled_data[29]
+.sym 19375 w_rx_fifo_pulled_data[28]
+.sym 19379 w_rx_fifo_pulled_data[19]
+.sym 19383 w_rx_fifo_pulled_data[17]
+.sym 19387 w_rx_fifo_pulled_data[30]
+.sym 19394 w_rx_fifo_pulled_data[28]
+.sym 19398 w_rx_fifo_pulled_data[17]
+.sym 19409 w_rx_fifo_pulled_data[29]
+.sym 19415 w_rx_fifo_pulled_data[30]
+.sym 19421 w_rx_fifo_pulled_data[19]
+.sym 19435 w_rx_fifo_pulled_data[31]
+.sym 19437 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
+.sym 19438 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 19439 i_rst_b_SB_LUT4_I3_O_$glb_sr
 .sym 19441 w_rx_fifo_pulled_data[28]
 .sym 19445 w_rx_fifo_pulled_data[30]
-.sym 19452 $PACKER_VCC_NET
-.sym 19459 rx_fifo.rd_addr[8]
-.sym 19463 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 19464 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 19466 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 19467 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19468 rx_fifo.rd_addr[9]
-.sym 19472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 19473 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 19481 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 19483 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 19485 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 19486 i_mosi$SB_IO_IN
+.sym 19450 o_led1_SB_LUT4_I1_I3[3]
+.sym 19464 rx_fifo.mem_i.0.3_WDATA_1
+.sym 19473 rx_fifo.wr_addr[6]
+.sym 19475 rx_fifo.mem_i.0.0_WDATA_1
+.sym 19481 i_mosi$SB_IO_IN
+.sym 19483 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 19485 spi_if_ins.spi.r_temp_rx_byte[3]
 .sym 19487 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 19489 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 19489 spi_if_ins.spi.r_temp_rx_byte[2]
 .sym 19490 i_sck$SB_IO_IN
-.sym 19493 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 19495 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 19508 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 19517 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 19522 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 19528 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 19532 i_mosi$SB_IO_IN
-.sym 19541 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 19545 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 19550 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 19557 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19491 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 19492 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 19493 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19495 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 19516 i_mosi$SB_IO_IN
+.sym 19520 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 19527 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 19533 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 19540 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 19546 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19551 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19557 spi_if_ins.spi.r_temp_rx_byte[5]
 .sym 19560 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
 .sym 19561 i_sck$SB_IO_IN
 .sym 19564 w_rx_fifo_pulled_data[29]
 .sym 19568 w_rx_fifo_pulled_data[31]
-.sym 19575 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 19579 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 19581 rx_fifo.wr_addr[6]
-.sym 19585 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 19594 $PACKER_VCC_NET
-.sym 19598 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 19604 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 19606 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 19608 i_rst_b$SB_IO_IN
-.sym 19611 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 19612 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 19613 spi_if_ins.state_if[0]
-.sym 19615 spi_if_ins.state_if_SB_DFFESR_Q_E
-.sym 19617 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19618 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19623 spi_if_ins.state_if[1]
-.sym 19625 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 19627 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 19631 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 19632 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
-.sym 19638 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19640 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 19645 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
-.sym 19649 spi_if_ins.state_if[0]
-.sym 19650 spi_if_ins.state_if[1]
-.sym 19655 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
-.sym 19657 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 19658 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 19661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 19663 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 19664 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19667 spi_if_ins.state_if[1]
-.sym 19668 spi_if_ins.state_if[0]
-.sym 19669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 19673 i_rst_b$SB_IO_IN
-.sym 19674 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 19675 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19676 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 19679 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 19683 spi_if_ins.state_if_SB_DFFESR_Q_E
+.sym 19575 i_mosi$SB_IO_IN
+.sym 19577 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 19585 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19587 rx_fifo.rd_addr[9]
+.sym 19589 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 19591 spi_if_ins.w_rx_data[1]
+.sym 19592 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 19593 spi_if_ins.w_rx_data[3]
+.sym 19595 spi_if_ins.w_rx_data[2]
+.sym 19597 spi_if_ins.w_rx_data[6]
+.sym 19598 rx_fifo.mem_i.0.3_WDATA
+.sym 19604 spi_if_ins.spi.r_rx_byte[0]
+.sym 19607 spi_if_ins.spi.r_rx_byte[4]
+.sym 19608 spi_if_ins.spi.r_rx_byte[5]
+.sym 19610 spi_if_ins.spi.r_rx_byte[1]
+.sym 19613 spi_if_ins.spi.r_rx_byte[7]
+.sym 19614 spi_if_ins.spi.r_rx_byte[2]
+.sym 19615 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 19617 spi_if_ins.spi.r_rx_byte[3]
+.sym 19619 spi_if_ins.spi.r_rx_byte[6]
+.sym 19640 spi_if_ins.spi.r_rx_byte[2]
+.sym 19646 spi_if_ins.spi.r_rx_byte[6]
+.sym 19649 spi_if_ins.spi.r_rx_byte[0]
+.sym 19655 spi_if_ins.spi.r_rx_byte[4]
+.sym 19663 spi_if_ins.spi.r_rx_byte[5]
+.sym 19668 spi_if_ins.spi.r_rx_byte[7]
+.sym 19673 spi_if_ins.spi.r_rx_byte[1]
+.sym 19682 spi_if_ins.spi.r_rx_byte[3]
+.sym 19683 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
 .sym 19684 r_counter_$glb_clk
-.sym 19685 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 19698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 19700 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 19702 rx_fifo.rd_addr[6]
-.sym 19704 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 19706 rx_fifo.rd_addr[3]
-.sym 19710 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 19719 w_smi_data_direction
-.sym 19720 $PACKER_VCC_NET
-.sym 19721 rx_fifo.mem_i.0.3_WDATA
-.sym 19729 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 19730 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19731 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 19732 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
-.sym 19734 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19740 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 19742 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 19746 i_rst_b$SB_IO_IN
-.sym 19750 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 19752 $PACKER_VCC_NET
-.sym 19753 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 19754 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 19756 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19757 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19759 $nextpnr_ICESTORM_LC_9$O
-.sym 19761 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19765 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
-.sym 19767 $PACKER_VCC_NET
-.sym 19768 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19773 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 19774 $PACKER_VCC_NET
-.sym 19775 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
-.sym 19778 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
-.sym 19779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 19780 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 19781 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 19784 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 19785 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 19787 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
-.sym 19791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 19792 i_rst_b$SB_IO_IN
-.sym 19796 $PACKER_VCC_NET
-.sym 19797 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19799 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19804 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19806 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 19697 w_rx_data[4]
+.sym 19699 i_glob_clock$SB_IO_IN
+.sym 19709 rx_fifo.rd_addr[0]
+.sym 19710 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 19711 w_rx_data[0]
+.sym 19713 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 19714 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 19717 o_led0_SB_LUT4_I1_O[1]
+.sym 19720 rx_fifo.rd_addr[2]
+.sym 19721 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 19740 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 19742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 19745 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19746 spi_if_ins.r_tx_byte[5]
+.sym 19747 spi_if_ins.spi.r_tx_byte[5]
+.sym 19748 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19751 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 19753 spi_if_ins.spi.r_tx_byte[7]
+.sym 19758 spi_if_ins.r_tx_byte[7]
+.sym 19774 spi_if_ins.r_tx_byte[7]
+.sym 19780 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19787 spi_if_ins.r_tx_byte[5]
+.sym 19790 spi_if_ins.spi.r_tx_byte[7]
+.sym 19791 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 19792 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 19793 spi_if_ins.spi.r_tx_byte[5]
+.sym 19806 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
 .sym 19807 r_counter_$glb_clk
-.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 19821 w_fetch
-.sym 19826 w_load
-.sym 19835 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 19836 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
-.sym 19837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 19838 i_glob_clock$SB_IO_IN
-.sym 19852 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 19854 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
-.sym 19856 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19857 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19858 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
-.sym 19859 spi_if_ins.spi.r_tx_byte[6]
-.sym 19860 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 19861 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 19862 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 19863 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 19864 spi_if_ins.spi.r_tx_byte[4]
-.sym 19865 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
-.sym 19868 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
-.sym 19869 spi_if_ins.spi.r_tx_byte[5]
-.sym 19870 spi_if_ins.r_tx_byte[5]
-.sym 19871 spi_if_ins.r_tx_byte[7]
-.sym 19872 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
-.sym 19874 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
-.sym 19875 spi_if_ins.spi.r_tx_byte[7]
-.sym 19883 spi_if_ins.spi.r_tx_byte[7]
-.sym 19884 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19885 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19886 spi_if_ins.spi.r_tx_byte[5]
-.sym 19889 spi_if_ins.r_tx_byte[7]
-.sym 19895 spi_if_ins.spi.r_tx_byte[6]
-.sym 19896 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19897 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19898 spi_if_ins.spi.r_tx_byte[4]
-.sym 19904 spi_if_ins.r_tx_byte[5]
-.sym 19907 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
-.sym 19908 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 19909 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
-.sym 19910 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
-.sym 19913 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 19914 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 19916 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
-.sym 19920 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 19921 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19922 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19925 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
-.sym 19926 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
-.sym 19928 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 19929 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
+.sym 19825 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 19829 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 19834 w_cs[2]
+.sym 19835 w_rx_data[3]
+.sym 19837 w_rx_data[0]
+.sym 19840 w_cs[1]
+.sym 19843 o_led0_SB_LUT4_I1_O[1]
+.sym 19850 spi_if_ins.w_rx_data[5]
+.sym 19851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 19854 spi_if_ins.w_rx_data[0]
+.sym 19856 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 19859 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 19860 spi_if_ins.w_rx_data[6]
+.sym 19861 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 19863 spi_if_ins.w_rx_data[1]
+.sym 19864 spi_if_ins.w_rx_data[4]
+.sym 19865 spi_if_ins.w_rx_data[3]
+.sym 19868 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 19885 spi_if_ins.w_rx_data[1]
+.sym 19889 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 19890 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 19892 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 19898 spi_if_ins.w_rx_data[4]
+.sym 19902 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 19909 spi_if_ins.w_rx_data[5]
+.sym 19910 spi_if_ins.w_rx_data[6]
+.sym 19916 spi_if_ins.w_rx_data[3]
+.sym 19919 spi_if_ins.w_rx_data[0]
+.sym 19926 spi_if_ins.w_rx_data[5]
+.sym 19929 spi_if_ins.o_data_in_SB_DFFE_Q_E
 .sym 19930 r_counter_$glb_clk
-.sym 19931 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 19944 i_glob_clock$SB_IO_IN
-.sym 19946 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 19954 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 19974 spi_if_ins.r_tx_byte[2]
-.sym 19975 spi_if_ins.r_tx_byte[4]
-.sym 19978 spi_if_ins.r_tx_byte[3]
-.sym 19980 spi_if_ins.r_tx_byte[6]
-.sym 19983 spi_if_ins.r_tx_byte[1]
-.sym 19984 spi_if_ins.spi.r_tx_byte[0]
-.sym 19985 spi_if_ins.r_tx_byte[0]
-.sym 19986 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 19987 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 19999 spi_if_ins.spi.r_tx_byte[2]
-.sym 20000 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 20002 spi_if_ins.spi.r_tx_byte[1]
-.sym 20004 spi_if_ins.spi.r_tx_byte[3]
-.sym 20006 spi_if_ins.spi.r_tx_byte[0]
-.sym 20008 spi_if_ins.spi.r_tx_byte[1]
-.sym 20009 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 20014 spi_if_ins.r_tx_byte[6]
-.sym 20019 spi_if_ins.r_tx_byte[2]
-.sym 20026 spi_if_ins.r_tx_byte[0]
-.sym 20031 spi_if_ins.spi.r_tx_byte[2]
-.sym 20032 spi_if_ins.spi.r_tx_byte[3]
-.sym 20033 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 20038 spi_if_ins.r_tx_byte[1]
-.sym 20042 spi_if_ins.r_tx_byte[4]
-.sym 20048 spi_if_ins.r_tx_byte[3]
-.sym 20052 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19949 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 19950 w_load
+.sym 19952 w_rx_data[7]
+.sym 19955 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 19957 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 19959 w_rx_data[7]
+.sym 19963 w_fetch
+.sym 19964 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 19977 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 19982 w_cs[1]
+.sym 19984 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 19985 w_cs[3]
+.sym 19986 spi_if_ins.w_rx_data[5]
+.sym 19987 w_cs[2]
+.sym 19988 spi_if_ins.w_rx_data[6]
+.sym 19989 w_ioc[2]
+.sym 19993 w_cs[0]
+.sym 19995 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 19998 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 20000 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 20001 w_ioc[4]
+.sym 20003 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 20004 w_ioc[3]
+.sym 20006 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 20007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 20008 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 20013 spi_if_ins.w_rx_data[5]
+.sym 20015 spi_if_ins.w_rx_data[6]
+.sym 20024 w_cs[3]
+.sym 20025 w_cs[1]
+.sym 20026 w_cs[2]
+.sym 20027 w_cs[0]
+.sym 20030 spi_if_ins.w_rx_data[5]
+.sym 20032 spi_if_ins.w_rx_data[6]
+.sym 20037 w_ioc[3]
+.sym 20038 w_ioc[4]
+.sym 20039 w_ioc[2]
+.sym 20042 spi_if_ins.w_rx_data[6]
+.sym 20044 spi_if_ins.w_rx_data[5]
+.sym 20049 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 20050 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 20051 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E
 .sym 20053 r_counter_$glb_clk
-.sym 20054 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 20075 o_tr_vc2$SB_IO_OUT
-.sym 20098 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 20100 r_tx_data[5]
-.sym 20102 r_tx_data[4]
-.sym 20106 r_tx_data[3]
-.sym 20141 r_tx_data[4]
-.sym 20159 r_tx_data[3]
-.sym 20167 r_tx_data[5]
-.sym 20175 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 20054 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 20071 w_cs[1]
+.sym 20075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 20076 o_led1$SB_IO_OUT
+.sym 20079 w_rx_data[6]
+.sym 20082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 20086 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 20089 o_led1_SB_LUT4_I1_I3[0]
+.sym 20090 o_led1_SB_LUT4_I1_I3[3]
+.sym 20096 w_rx_data[1]
+.sym 20099 io_ctrl_ins.pmod_dir_state[3]
+.sym 20100 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 20102 w_rx_data[5]
+.sym 20104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 20107 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 20108 w_rx_data[0]
+.sym 20109 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 20110 w_rx_data[2]
+.sym 20111 o_led1_SB_LUT4_I1_I3[3]
+.sym 20116 io_ctrl_ins.pmod_dir_state[1]
+.sym 20119 w_rx_data[7]
+.sym 20121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 20123 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 20124 o_led1$SB_IO_OUT
+.sym 20126 i_button_SB_LUT4_I0_I3[2]
+.sym 20129 o_led1_SB_LUT4_I1_I3[3]
+.sym 20130 o_led1$SB_IO_OUT
+.sym 20131 io_ctrl_ins.pmod_dir_state[1]
+.sym 20132 i_button_SB_LUT4_I0_I3[2]
+.sym 20135 w_rx_data[0]
+.sym 20142 w_rx_data[2]
+.sym 20147 i_button_SB_LUT4_I0_I3[2]
+.sym 20148 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 20149 io_ctrl_ins.pmod_dir_state[3]
+.sym 20150 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 20155 w_rx_data[1]
+.sym 20160 w_rx_data[5]
+.sym 20165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 20166 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 20167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 20173 w_rx_data[7]
+.sym 20175 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
 .sym 20176 r_counter_$glb_clk
-.sym 20206 w_smi_data_direction
-.sym 20220 w_rx_data[0]
+.sym 20196 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+.sym 20198 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 20201 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 20205 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 20206 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 20209 o_led0_SB_LUT4_I1_O[1]
+.sym 20210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 20211 o_led1$SB_IO_OUT
+.sym 20220 w_rx_data[4]
 .sym 20221 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 20222 o_led1_SB_LUT4_I1_I2[2]
-.sym 20224 w_cs[1]
-.sym 20227 w_fetch
-.sym 20228 o_led1_SB_LUT4_I1_I2[3]
-.sym 20230 w_load
-.sym 20246 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 20264 w_load
-.sym 20265 w_cs[1]
-.sym 20266 o_led1_SB_LUT4_I1_I2[3]
-.sym 20267 w_fetch
-.sym 20270 w_rx_data[0]
-.sym 20283 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 20284 o_led1_SB_LUT4_I1_I2[2]
+.sym 20222 i_button_SB_LUT4_I0_I3[3]
+.sym 20223 i_config[2]$SB_IO_IN
+.sym 20224 io_ctrl_ins.pmod_dir_state[5]
+.sym 20225 io_pmod_out[3]$SB_IO_OUT
+.sym 20227 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 20228 w_load
+.sym 20229 w_cs[1]
+.sym 20231 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 20232 i_button_SB_LUT4_I0_I3[2]
+.sym 20233 w_fetch
+.sym 20234 w_rx_data[3]
+.sym 20235 i_rst_b$SB_IO_IN
+.sym 20239 w_rx_data[6]
+.sym 20241 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 20246 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 20250 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 20252 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 20254 i_button_SB_LUT4_I0_I3[2]
+.sym 20258 i_button_SB_LUT4_I0_I3[3]
+.sym 20259 i_config[2]$SB_IO_IN
+.sym 20260 io_ctrl_ins.pmod_dir_state[5]
+.sym 20261 i_button_SB_LUT4_I0_I3[2]
+.sym 20266 w_rx_data[6]
+.sym 20273 w_rx_data[3]
+.sym 20277 w_rx_data[4]
+.sym 20283 io_pmod_out[3]$SB_IO_OUT
+.sym 20284 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 20285 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 20288 w_load
+.sym 20289 w_cs[1]
+.sym 20290 i_rst_b$SB_IO_IN
+.sym 20291 w_fetch
+.sym 20296 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 20297 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
 .sym 20298 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
 .sym 20299 r_counter_$glb_clk
-.sym 20315 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 20326 i_glob_clock$SB_IO_IN
-.sym 20344 w_rx_data[4]
-.sym 20347 w_rx_data[1]
-.sym 20348 o_led1$SB_IO_OUT
-.sym 20353 io_ctrl_ins.pmod_dir_state[0]
-.sym 20354 w_rx_data[7]
-.sym 20355 o_led0$SB_IO_OUT
-.sym 20357 io_ctrl_ins.pmod_dir_state[1]
-.sym 20358 o_led1_SB_LUT4_I1_I2[1]
-.sym 20359 o_led1_SB_LUT4_I1_I2[3]
-.sym 20361 o_led1_SB_LUT4_I1_I2[2]
-.sym 20362 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 20369 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
-.sym 20371 i_config[1]$SB_IO_IN
-.sym 20377 w_rx_data[4]
-.sym 20381 w_rx_data[7]
-.sym 20389 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 20393 o_led1_SB_LUT4_I1_I2[3]
-.sym 20394 i_config[1]$SB_IO_IN
-.sym 20395 o_led1_SB_LUT4_I1_I2[2]
+.sym 20319 i_config[2]$SB_IO_IN
+.sym 20322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 20342 w_rx_data[7]
+.sym 20344 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 20345 o_tr_vc1_b$SB_IO_OUT
+.sym 20346 o_led1_SB_LUT4_I1_I2[1]
+.sym 20348 o_led0_SB_LUT4_I1_O[1]
+.sym 20349 w_cs[1]
+.sym 20350 i_button_SB_LUT4_I0_I3[2]
+.sym 20351 w_rx_data[6]
+.sym 20352 w_load
+.sym 20353 i_button_SB_LUT4_I0_O[1]
+.sym 20354 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 20355 w_fetch
+.sym 20356 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 20357 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 20368 w_rx_data[3]
+.sym 20372 w_rx_data[5]
+.sym 20378 w_rx_data[3]
+.sym 20383 w_rx_data[5]
+.sym 20387 w_fetch
+.sym 20388 w_cs[1]
+.sym 20389 o_led0_SB_LUT4_I1_O[1]
+.sym 20390 w_load
+.sym 20393 i_button_SB_LUT4_I0_I3[2]
+.sym 20394 i_button_SB_LUT4_I0_O[1]
+.sym 20395 o_tr_vc1_b$SB_IO_OUT
 .sym 20396 o_led1_SB_LUT4_I1_I2[1]
-.sym 20399 io_ctrl_ins.pmod_dir_state[1]
-.sym 20400 o_led1_SB_LUT4_I1_I2[3]
-.sym 20401 o_led1$SB_IO_OUT
-.sym 20402 o_led1_SB_LUT4_I1_I2[2]
-.sym 20411 o_led0$SB_IO_OUT
-.sym 20412 o_led1_SB_LUT4_I1_I2[2]
-.sym 20413 io_ctrl_ins.pmod_dir_state[0]
-.sym 20414 o_led1_SB_LUT4_I1_I2[3]
-.sym 20417 w_rx_data[1]
-.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 20399 w_rx_data[6]
+.sym 20406 i_button_SB_LUT4_I0_O[1]
+.sym 20407 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 20413 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 20414 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 20418 w_rx_data[7]
+.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
 .sym 20422 r_counter_$glb_clk
-.sym 20448 o_led1$SB_IO_OUT
-.sym 20468 i_config_SB_LUT4_I0_1_O[2]
-.sym 20476 o_tr_vc1_b$SB_IO_OUT
-.sym 20481 i_config_SB_LUT4_I0_1_O[1]
-.sym 20483 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 20485 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 20491 i_config_SB_LUT4_I0_1_O[3]
-.sym 20504 i_config_SB_LUT4_I0_1_O[2]
-.sym 20505 i_config_SB_LUT4_I0_1_O[1]
-.sym 20506 i_config_SB_LUT4_I0_1_O[3]
-.sym 20507 o_tr_vc1_b$SB_IO_OUT
-.sym 20510 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
-.sym 20512 i_config_SB_LUT4_I0_1_O[1]
-.sym 20544 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
+.sym 20438 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 20440 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 20454 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 20467 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
+.sym 20470 w_rx_data[1]
+.sym 20476 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
+.sym 20477 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 20478 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 20482 w_rx_data[3]
+.sym 20483 o_led1_SB_LUT4_I1_O[0]
+.sym 20484 w_rx_data[0]
+.sym 20491 w_rx_data[2]
+.sym 20492 w_rx_data[4]
+.sym 20494 o_led0_SB_LUT4_I1_O[0]
+.sym 20498 o_led1_SB_LUT4_I1_O[0]
+.sym 20500 o_led0_SB_LUT4_I1_O[0]
+.sym 20506 w_rx_data[3]
+.sym 20513 w_rx_data[1]
+.sym 20517 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
+.sym 20518 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 20519 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 20522 w_rx_data[4]
+.sym 20530 w_rx_data[0]
+.sym 20540 w_rx_data[2]
+.sym 20544 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
 .sym 20545 r_counter_$glb_clk
-.sym 20571 i_config[0]$SB_IO_IN
+.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 20563 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 20579 i_config[0]$SB_IO_IN
+.sym 20591 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
+.sym 20592 i_config[1]$SB_IO_IN
+.sym 20599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 20609 o_led1_SB_LUT4_I1_I3[3]
+.sym 20621 i_config[1]$SB_IO_IN
+.sym 20622 o_led1_SB_LUT4_I1_I3[3]
+.sym 20624 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
+.sym 20667 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 20668 r_counter_$glb_clk
 .sym 20672 i_config[0]$SB_IO_IN
+.sym 20700 o_led1$SB_IO_OUT
 .sym 20748 w_smi_data_output[5]
 .sym 20750 w_smi_data_direction
 .sym 20751 $PACKER_VCC_NET
-.sym 20764 w_smi_data_output[5]
-.sym 20765 w_smi_data_direction
-.sym 20767 $PACKER_VCC_NET
-.sym 20772 tx_fifo.wr_addr[4]
+.sym 20757 w_smi_data_output[5]
+.sym 20759 $PACKER_VCC_NET
+.sym 20769 w_smi_data_direction
+.sym 20770 smi_ctrl_ins.swe_and_reset
+.sym 20786 rx_fifo.wr_addr[7]
+.sym 20804 i_mosi$SB_IO_IN
 .sym 20844 i_mosi$SB_IO_IN
-.sym 20931 rx_fifo.wr_addr[5]
-.sym 20938 rx_fifo.wr_addr[2]
-.sym 20940 rx_fifo.wr_addr[8]
-.sym 20942 o_miso_$_TBUF__Y_E
-.sym 20989 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 20990 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 21040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 21041 smi_ctrl_ins.r_fifo_pulled_data[16]
-.sym 21043 rx_fifo.rd_addr[8]
-.sym 21046 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21047 i_rst_b$SB_IO_IN
-.sym 21056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21058 rx_fifo.wr_addr[6]
-.sym 21060 rx_fifo.wr_addr[4]
-.sym 21062 rx_fifo.wr_addr[9]
-.sym 21063 rx_fifo.wr_addr[1]
-.sym 21064 rx_fifo.wr_addr[3]
-.sym 21065 rx_fifo.mem_i.0.0_WDATA_2
-.sym 21067 rx_fifo.mem_i.0.0_WDATA_3
-.sym 21074 $PACKER_VCC_NET
-.sym 21075 rx_fifo.wr_addr[5]
-.sym 21078 rx_fifo.wr_addr[0]
-.sym 21081 rx_fifo.wr_addr[2]
-.sym 21083 rx_fifo.wr_addr[8]
-.sym 21084 rx_fifo.wr_addr[7]
-.sym 21086 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
-.sym 21087 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
-.sym 21088 smi_ctrl_ins.tx_reg_state[1]
-.sym 21089 smi_ctrl_ins.tx_reg_state[2]
-.sym 21090 smi_ctrl_ins.tx_reg_state[3]
-.sym 21091 o_miso_$_TBUF__Y_E
-.sym 21092 smi_ctrl_ins.tx_reg_state[0]
-.sym 21093 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
+.sym 20846 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
+.sym 20847 smi_ctrl_ins.tx_reg_state[1]
+.sym 20848 smi_ctrl_ins.tx_reg_state[2]
+.sym 20849 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
+.sym 20850 smi_ctrl_ins.tx_reg_state[3]
+.sym 20851 smi_ctrl_ins.tx_reg_state[0]
+.sym 20852 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
+.sym 20900 o_miso_$_TBUF__Y_E
+.sym 20925 i_rst_b$SB_IO_IN
+.sym 20936 rx_fifo.wr_addr[1]
+.sym 20937 rx_fifo.wr_addr[5]
+.sym 20938 w_rx_fifo_pulled_data[12]
+.sym 20947 int_miso
+.sym 20986 smi_ctrl_ins.r_fifo_push
+.sym 21034 w_smi_data_input[7]
+.sym 21038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21039 o_miso_$_TBUF__Y_E
+.sym 21042 i_rst_b$SB_IO_IN
+.sym 21046 int_miso
+.sym 21048 rx_fifo.wr_addr[2]
+.sym 21054 rx_fifo.wr_addr[2]
+.sym 21058 $PACKER_VCC_NET
+.sym 21068 rx_fifo.wr_addr[3]
+.sym 21070 rx_fifo.wr_addr[6]
+.sym 21071 rx_fifo.wr_addr[9]
+.sym 21072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 21076 rx_fifo.wr_addr[4]
+.sym 21077 rx_fifo.wr_addr[0]
+.sym 21079 rx_fifo.wr_addr[1]
+.sym 21080 rx_fifo.wr_addr[5]
+.sym 21081 rx_fifo.wr_addr[8]
+.sym 21082 rx_fifo.wr_addr[7]
+.sym 21083 rx_fifo.mem_q.0.3_WDATA_2
+.sym 21085 rx_fifo.mem_q.0.3_WDATA_3
+.sym 21088 tx_fifo.rd_addr_gray_wr[8]
+.sym 21093 tx_fifo.rd_addr_gray_wr_r[8]
 .sym 21102 rx_fifo.wr_addr[2]
 .sym 21103 rx_fifo.wr_addr[3]
 .sym 21105 rx_fifo.wr_addr[4]
@@ -10325,68 +10508,63 @@
 .sym 21111 rx_fifo.wr_addr[1]
 .sym 21112 rx_fifo.wr_addr[0]
 .sym 21113 lvds_clock_$glb_clk
-.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21116 rx_fifo.mem_i.0.0_WDATA_3
-.sym 21120 rx_fifo.mem_i.0.0_WDATA_2
+.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 21116 rx_fifo.mem_q.0.3_WDATA_3
+.sym 21120 rx_fifo.mem_q.0.3_WDATA_2
 .sym 21123 $PACKER_VCC_NET
-.sym 21128 rx_fifo.wr_addr[9]
-.sym 21135 rx_fifo.mem_i.0.0_WDATA_3
-.sym 21140 smi_ctrl_ins.swe_and_reset
-.sym 21146 smi_ctrl_ins.w_fifo_push_trigger
-.sym 21148 smi_ctrl_ins.r_fifo_pulled_data[17]
-.sym 21149 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
-.sym 21156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21158 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21160 rx_fifo.rd_addr[6]
-.sym 21162 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 21163 rx_fifo.rd_addr[3]
-.sym 21164 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21166 rx_fifo.rd_addr[0]
-.sym 21167 rx_fifo.mem_i.0.0_WDATA_1
-.sym 21171 rx_fifo.mem_i.0.0_WDATA
-.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 21175 rx_fifo.rd_addr[9]
-.sym 21176 $PACKER_VCC_NET
-.sym 21177 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21181 rx_fifo.rd_addr[8]
-.sym 21189 smi_ctrl_ins.w_fifo_push_trigger
-.sym 21194 smi_ctrl_ins.swe_and_reset
-.sym 21204 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21205 rx_fifo.rd_addr[3]
-.sym 21207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21208 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21209 rx_fifo.rd_addr[6]
-.sym 21210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21211 rx_fifo.rd_addr[8]
+.sym 21137 o_smi_read_req$SB_IO_OUT
+.sym 21142 w_rx_fifo_pulled_data[15]
+.sym 21150 w_rx_fifo_pulled_data[13]
+.sym 21158 rx_fifo.mem_q.0.3_WDATA_1
+.sym 21160 $PACKER_VCC_NET
+.sym 21164 rx_fifo.rd_addr[0]
+.sym 21167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 21168 rx_fifo.rd_addr[9]
+.sym 21169 rx_fifo.mem_q.0.3_WDATA
+.sym 21172 rx_fifo.rd_addr[1]
+.sym 21175 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21176 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21178 rx_fifo.rd_addr[2]
+.sym 21182 rx_fifo.rd_addr[5]
+.sym 21183 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21187 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 21188 o_miso_$_TBUF__Y_E
+.sym 21204 rx_fifo.rd_addr[2]
+.sym 21205 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21207 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21208 rx_fifo.rd_addr[5]
+.sym 21209 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21210 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21211 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 21212 rx_fifo.rd_addr[9]
-.sym 21213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 21213 rx_fifo.rd_addr[1]
 .sym 21214 rx_fifo.rd_addr[0]
 .sym 21215 r_counter_$glb_clk
-.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 21216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 21217 $PACKER_VCC_NET
-.sym 21221 rx_fifo.mem_i.0.0_WDATA
-.sym 21225 rx_fifo.mem_i.0.0_WDATA_1
-.sym 21235 rx_fifo.mem_i.0.0_WDATA_1
-.sym 21238 w_smi_data_input[7]
-.sym 21239 rx_fifo.rd_addr[3]
-.sym 21249 rx_fifo.rd_addr[6]
-.sym 21251 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 21252 rx_fifo.rd_addr[0]
-.sym 21260 rx_fifo.wr_addr[4]
-.sym 21261 rx_fifo.wr_addr[0]
-.sym 21262 $PACKER_VCC_NET
-.sym 21264 rx_fifo.mem_q.0.1_WDATA_3
-.sym 21267 rx_fifo.wr_addr[6]
-.sym 21272 rx_fifo.wr_addr[7]
-.sym 21273 rx_fifo.mem_q.0.1_WDATA_2
-.sym 21275 rx_fifo.wr_addr[3]
-.sym 21276 rx_fifo.wr_addr[1]
-.sym 21278 rx_fifo.wr_addr[8]
-.sym 21279 rx_fifo.wr_addr[5]
-.sym 21282 rx_fifo.wr_addr[9]
-.sym 21285 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21287 rx_fifo.wr_addr[2]
-.sym 21290 spi_if_ins.spi.r_rx_done
+.sym 21221 rx_fifo.mem_q.0.3_WDATA
+.sym 21225 rx_fifo.mem_q.0.3_WDATA_1
+.sym 21235 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 21236 tx_fifo.rd_addr_gray[8]
+.sym 21237 rx_fifo.mem_q.0.3_WDATA
+.sym 21239 $PACKER_VCC_NET
+.sym 21245 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 21252 rx_fifo.wr_addr[4]
+.sym 21258 rx_fifo.wr_addr[4]
+.sym 21259 rx_fifo.wr_addr[5]
+.sym 21260 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 21263 rx_fifo.wr_addr[0]
+.sym 21268 rx_fifo.wr_addr[9]
+.sym 21270 rx_fifo.wr_addr[3]
+.sym 21271 rx_fifo.wr_addr[6]
+.sym 21278 $PACKER_VCC_NET
+.sym 21280 rx_fifo.wr_addr[2]
+.sym 21282 rx_fifo.wr_addr[7]
+.sym 21283 rx_fifo.wr_addr[8]
+.sym 21285 rx_fifo.mem_i.0.0_WDATA_2
+.sym 21287 rx_fifo.mem_i.0.0_WDATA_3
+.sym 21289 rx_fifo.wr_addr[1]
 .sym 21306 rx_fifo.wr_addr[2]
 .sym 21307 rx_fifo.wr_addr[3]
 .sym 21309 rx_fifo.wr_addr[4]
@@ -10398,82 +10576,69 @@
 .sym 21315 rx_fifo.wr_addr[1]
 .sym 21316 rx_fifo.wr_addr[0]
 .sym 21317 lvds_clock_$glb_clk
-.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21320 rx_fifo.mem_q.0.1_WDATA_3
-.sym 21324 rx_fifo.mem_q.0.1_WDATA_2
+.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 21320 rx_fifo.mem_i.0.0_WDATA_3
+.sym 21324 rx_fifo.mem_i.0.0_WDATA_2
 .sym 21327 $PACKER_VCC_NET
-.sym 21334 w_smi_data_input[7]
-.sym 21336 rx_fifo.wr_addr[4]
-.sym 21337 rx_fifo.wr_addr[0]
-.sym 21340 rx_fifo.mem_q.0.1_WDATA_3
-.sym 21341 rx_fifo.mem_q.0.1_WDATA_2
-.sym 21343 rx_fifo.wr_addr[6]
-.sym 21344 rx_fifo.wr_addr[4]
-.sym 21345 rx_fifo.wr_addr[0]
-.sym 21351 o_miso_$_TBUF__Y_E
-.sym 21360 rx_fifo.rd_addr[8]
-.sym 21361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21362 rx_fifo.mem_q.0.1_WDATA
-.sym 21365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21367 rx_fifo.rd_addr[3]
-.sym 21369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21371 rx_fifo.mem_q.0.1_WDATA_1
-.sym 21373 $PACKER_VCC_NET
-.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 21380 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21384 rx_fifo.rd_addr[9]
-.sym 21387 rx_fifo.rd_addr[6]
-.sym 21389 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 21390 rx_fifo.rd_addr[0]
-.sym 21392 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 21394 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 21395 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 21396 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 21397 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 21398 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 21399 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 21408 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21409 rx_fifo.rd_addr[3]
-.sym 21411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21412 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21413 rx_fifo.rd_addr[6]
-.sym 21414 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21415 rx_fifo.rd_addr[8]
+.sym 21339 rx_fifo.wr_addr[6]
+.sym 21344 rx_fifo.wr_addr[1]
+.sym 21346 rx_fifo.wr_addr[2]
+.sym 21362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 21363 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21373 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21374 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21375 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 21378 rx_fifo.rd_addr[2]
+.sym 21380 rx_fifo.rd_addr[1]
+.sym 21381 rx_fifo.rd_addr[9]
+.sym 21382 rx_fifo.mem_i.0.0_WDATA
+.sym 21384 rx_fifo.rd_addr[0]
+.sym 21386 rx_fifo.rd_addr[5]
+.sym 21387 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21389 $PACKER_VCC_NET
+.sym 21391 rx_fifo.mem_i.0.0_WDATA_1
+.sym 21392 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 21393 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 21394 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 21395 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 21397 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 21398 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 21399 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 21408 rx_fifo.rd_addr[2]
+.sym 21409 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21411 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21412 rx_fifo.rd_addr[5]
+.sym 21413 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21414 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21415 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 21416 rx_fifo.rd_addr[9]
-.sym 21417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 21417 rx_fifo.rd_addr[1]
 .sym 21418 rx_fifo.rd_addr[0]
 .sym 21419 r_counter_$glb_clk
-.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 21420 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 21421 $PACKER_VCC_NET
-.sym 21425 rx_fifo.mem_q.0.1_WDATA
-.sym 21429 rx_fifo.mem_q.0.1_WDATA_1
-.sym 21435 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21436 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 21437 rx_fifo.mem_q.0.1_WDATA_1
-.sym 21438 rx_fifo.mem_q.0.1_WDATA
-.sym 21446 $PACKER_VCC_NET
-.sym 21448 i_rst_b$SB_IO_IN
-.sym 21452 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
-.sym 21455 rx_fifo.rd_addr[8]
-.sym 21463 rx_fifo.wr_addr[7]
-.sym 21464 rx_fifo.wr_addr[1]
+.sym 21425 rx_fifo.mem_i.0.0_WDATA
+.sym 21429 rx_fifo.mem_i.0.0_WDATA_1
+.sym 21446 int_miso
+.sym 21448 o_miso_$_TBUF__Y_E
+.sym 21450 i_rst_b$SB_IO_IN
+.sym 21457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 21462 rx_fifo.wr_addr[8]
 .sym 21466 $PACKER_VCC_NET
-.sym 21467 rx_fifo.wr_addr[5]
-.sym 21469 rx_fifo.wr_addr[3]
-.sym 21470 rx_fifo.wr_addr[9]
-.sym 21471 rx_fifo.wr_addr[6]
-.sym 21473 rx_fifo.mem_i.0.3_WDATA_2
-.sym 21475 rx_fifo.wr_addr[2]
-.sym 21477 rx_fifo.wr_addr[8]
-.sym 21482 rx_fifo.wr_addr[4]
-.sym 21483 rx_fifo.wr_addr[0]
-.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-.sym 21491 rx_fifo.mem_i.0.3_WDATA_3
-.sym 21494 smi_ctrl_ins.soe_and_reset
-.sym 21495 spi_if_ins.r_tx_data_valid
-.sym 21496 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 21497 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 21498 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 21468 rx_fifo.mem_i.0.3_WDATA_2
+.sym 21471 rx_fifo.mem_i.0.3_WDATA_3
+.sym 21474 rx_fifo.wr_addr[3]
+.sym 21478 rx_fifo.wr_addr[6]
+.sym 21480 rx_fifo.wr_addr[4]
+.sym 21482 rx_fifo.wr_addr[1]
+.sym 21483 rx_fifo.wr_addr[5]
+.sym 21484 rx_fifo.wr_addr[2]
+.sym 21488 rx_fifo.wr_addr[9]
+.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 21490 rx_fifo.wr_addr[7]
+.sym 21492 rx_fifo.wr_addr[0]
+.sym 21498 smi_ctrl_ins.soe_and_reset
+.sym 21500 int_miso
 .sym 21510 rx_fifo.wr_addr[2]
 .sym 21511 rx_fifo.wr_addr[3]
 .sym 21513 rx_fifo.wr_addr[4]
@@ -10485,2076 +10650,2188 @@
 .sym 21519 rx_fifo.wr_addr[1]
 .sym 21520 rx_fifo.wr_addr[0]
 .sym 21521 lvds_clock_$glb_clk
-.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
+.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
 .sym 21524 rx_fifo.mem_i.0.3_WDATA_3
 .sym 21528 rx_fifo.mem_i.0.3_WDATA_2
 .sym 21531 $PACKER_VCC_NET
-.sym 21536 rx_fifo.wr_addr[9]
-.sym 21541 rx_fifo.mem_i.0.3_WDATA_2
-.sym 21542 $PACKER_VCC_NET
-.sym 21547 rx_fifo.wr_addr[7]
-.sym 21567 rx_fifo.rd_addr[3]
-.sym 21571 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21572 rx_fifo.rd_addr[9]
-.sym 21573 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 21579 rx_fifo.rd_addr[6]
-.sym 21580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21582 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 21584 $PACKER_VCC_NET
-.sym 21589 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21591 rx_fifo.mem_i.0.3_WDATA_1
-.sym 21592 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21593 rx_fifo.rd_addr[8]
-.sym 21594 rx_fifo.rd_addr[0]
-.sym 21595 rx_fifo.mem_i.0.3_WDATA
-.sym 21600 w_fetch
-.sym 21601 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
-.sym 21602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
-.sym 21612 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 21613 rx_fifo.rd_addr[3]
-.sym 21615 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 21616 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 21617 rx_fifo.rd_addr[6]
-.sym 21618 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 21619 rx_fifo.rd_addr[8]
+.sym 21538 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21547 rx_fifo.mem_i.0.3_WDATA_3
+.sym 21554 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
+.sym 21568 rx_fifo.mem_i.0.3_WDATA_1
+.sym 21575 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 21576 rx_fifo.rd_addr[0]
+.sym 21581 rx_fifo.rd_addr[9]
+.sym 21582 rx_fifo.mem_i.0.3_WDATA
+.sym 21583 rx_fifo.rd_addr[5]
+.sym 21584 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21586 rx_fifo.rd_addr[2]
+.sym 21587 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21588 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21589 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21591 rx_fifo.rd_addr[1]
+.sym 21593 $PACKER_VCC_NET
+.sym 21595 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 21601 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 21612 rx_fifo.rd_addr[2]
+.sym 21613 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 21615 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 21616 rx_fifo.rd_addr[5]
+.sym 21617 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 21618 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 21619 w_smi_read_req_SB_LUT4_I1_O[0]
 .sym 21620 rx_fifo.rd_addr[9]
-.sym 21621 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 21621 rx_fifo.rd_addr[1]
 .sym 21622 rx_fifo.rd_addr[0]
 .sym 21623 r_counter_$glb_clk
-.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 21624 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
 .sym 21625 $PACKER_VCC_NET
 .sym 21629 rx_fifo.mem_i.0.3_WDATA
 .sym 21633 rx_fifo.mem_i.0.3_WDATA_1
-.sym 21641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 21644 i_glob_clock$SB_IO_IN
-.sym 21645 i_smi_soe_se$SB_IO_IN
-.sym 21647 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
-.sym 21649 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 21651 w_fetch
-.sym 21658 io_pmod[6]$SB_IO_IN
-.sym 21660 rx_fifo.rd_addr[0]
-.sym 21698 int_miso
-.sym 21744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 21745 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 21750 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 21754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 21758 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 21802 $PACKER_GND_NET
-.sym 21807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 21843 io_pmod[0]$SB_IO_IN
-.sym 21861 w_rx_data[1]
-.sym 21953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 22005 o_led1$SB_IO_OUT
-.sym 22010 o_led0$SB_IO_OUT
-.sym 22157 o_led1$SB_IO_OUT
-.sym 22361 o_tr_vc1$SB_IO_OUT
+.sym 21641 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 21642 i_smi_soe_se$SB_IO_IN
+.sym 21644 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 21650 w_load
+.sym 21653 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 21661 w_cs[2]
+.sym 21699 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
+.sym 21704 w_load
+.sym 21754 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 21757 w_load
+.sym 21760 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 21800 o_led1_SB_DFFER_Q_E
+.sym 21805 r_tx_data[3]
+.sym 21848 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 21849 spi_if_ins.w_rx_data[1]
+.sym 21852 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 21855 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 21861 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 21865 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 21903 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 21904 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
+.sym 21905 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 21908 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
+.sym 21909 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 21948 o_led1$SB_IO_OUT
+.sym 21952 w_rx_data[0]
+.sym 21953 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 21956 o_shdn_tx_lna$SB_IO_OUT
+.sym 21957 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 21963 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 21965 w_rx_fifo_full
+.sym 21967 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 22009 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
+.sym 22011 w_tx_data_io[2]
+.sym 22049 w_rx_data[0]
+.sym 22051 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 22057 w_rx_data[3]
+.sym 22065 i_button_SB_LUT4_I0_I3[2]
+.sym 22066 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
+.sym 22068 o_led0$SB_IO_OUT
+.sym 22106 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 22107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
+.sym 22110 o_led0_SB_LUT4_I1_O[3]
+.sym 22111 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 22148 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 22150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 22153 w_tx_data_io[2]
+.sym 22154 w_rx_fifo_full
+.sym 22159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 22160 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 22171 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 22214 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 22251 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 22252 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 22254 i_config[0]$SB_IO_IN
+.sym 22256 o_led1_SB_LUT4_I1_I3[3]
+.sym 22257 o_led1_SB_LUT4_I1_I3[0]
+.sym 22258 o_tr_vc1$SB_IO_OUT
+.sym 22356 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 22360 o_led0_SB_LUT4_I1_O[1]
+.sym 22465 o_led0$SB_IO_OUT
 .sym 22487 o_led1$SB_IO_OUT
-.sym 22505 o_led1$SB_IO_OUT
+.sym 22507 o_led1$SB_IO_OUT
 .sym 22517 int_miso
 .sym 22519 o_miso_$_TBUF__Y_E
-.sym 22533 o_miso_$_TBUF__Y_E
-.sym 22537 int_miso
+.sym 22534 o_miso_$_TBUF__Y_E
+.sym 22535 int_miso
 .sym 22554 i_mosi$SB_IO_IN
-.sym 22561 int_miso
-.sym 22565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
+.sym 22559 rx_fifo.wr_addr[5]
 .sym 22576 i_ss$SB_IO_IN
-.sym 22595 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 22605 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 22632 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 22663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 22664 r_counter_$glb_clk
-.sym 22665 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 22589 i_rst_b$SB_IO_IN
+.sym 22593 o_smi_write_req$SB_IO_OUT
+.sym 22617 o_smi_write_req$SB_IO_OUT
+.sym 22620 i_rst_b$SB_IO_IN
 .sym 22666 i_sck$SB_IO_IN
 .sym 22668 i_ss$SB_IO_IN
-.sym 22687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 22677 smi_ctrl_ins.w_fifo_push_trigger
+.sym 22689 i_rst_b$SB_IO_IN
+.sym 22695 o_smi_write_req$SB_IO_OUT
 .sym 22707 i_ss$SB_IO_IN
+.sym 22711 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
 .sym 22720 i_sck$SB_IO_IN
-.sym 22729 i_sck$SB_IO_IN
 .sym 22733 i_ss$SB_IO_IN
-.sym 22879 w_rx_fifo_pulled_data[16]
-.sym 22887 w_rx_fifo_pulled_data[17]
-.sym 22934 w_rx_fifo_pulled_data[16]
-.sym 22940 w_rx_fifo_pulled_data[17]
-.sym 22949 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
-.sym 22950 smi_ctrl_ins.soe_and_reset_$glb_clk
+.sym 22734 smi_ctrl_ins.r_fifo_push
+.sym 22740 i_sck$SB_IO_IN
+.sym 22747 smi_ctrl_ins.swe_and_reset
+.sym 22748 smi_ctrl_ins.tx_reg_state[1]
+.sym 22749 i_rst_b$SB_IO_IN
+.sym 22750 w_smi_data_input[7]
+.sym 22759 smi_ctrl_ins.tx_reg_state[3]
+.sym 22763 i_rst_b$SB_IO_IN
+.sym 22765 smi_ctrl_ins.tx_reg_state[2]
+.sym 22771 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
+.sym 22774 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
+.sym 22776 smi_ctrl_ins.tx_reg_state[0]
+.sym 22781 smi_ctrl_ins.tx_reg_state[1]
+.sym 22782 smi_ctrl_ins.tx_reg_state[2]
+.sym 22783 w_smi_data_input[7]
+.sym 22786 w_smi_data_input[7]
+.sym 22787 smi_ctrl_ins.tx_reg_state[2]
+.sym 22789 i_rst_b$SB_IO_IN
+.sym 22792 smi_ctrl_ins.tx_reg_state[0]
+.sym 22793 w_smi_data_input[7]
+.sym 22794 i_rst_b$SB_IO_IN
+.sym 22798 w_smi_data_input[7]
+.sym 22799 i_rst_b$SB_IO_IN
+.sym 22800 smi_ctrl_ins.tx_reg_state[3]
+.sym 22801 smi_ctrl_ins.tx_reg_state[0]
+.sym 22804 i_rst_b$SB_IO_IN
+.sym 22805 smi_ctrl_ins.tx_reg_state[1]
+.sym 22807 w_smi_data_input[7]
+.sym 22811 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
+.sym 22812 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
+.sym 22816 i_rst_b$SB_IO_IN
+.sym 22817 smi_ctrl_ins.tx_reg_state[3]
+.sym 22818 smi_ctrl_ins.tx_reg_state[0]
+.sym 22827 smi_ctrl_ins.swe_and_reset
+.sym 22858 i_sck$SB_IO_IN
+.sym 22885 smi_ctrl_ins.w_fifo_push_trigger
+.sym 22917 smi_ctrl_ins.w_fifo_push_trigger
+.sym 22950 r_counter_$glb_clk
 .sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 22980 i_ss$SB_IO_IN
-.sym 22996 w_smi_data_input[7]
-.sym 22998 i_rst_b$SB_IO_IN
-.sym 23000 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
-.sym 23002 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
-.sym 23004 w_smi_data_input[7]
-.sym 23005 smi_ctrl_ins.tx_reg_state[3]
-.sym 23006 i_rst_b$SB_IO_IN
-.sym 23010 i_ss$SB_IO_IN
-.sym 23015 smi_ctrl_ins.tx_reg_state[0]
-.sym 23018 smi_ctrl_ins.swe_and_reset
-.sym 23019 smi_ctrl_ins.tx_reg_state[1]
-.sym 23020 smi_ctrl_ins.tx_reg_state[2]
-.sym 23026 i_rst_b$SB_IO_IN
-.sym 23028 smi_ctrl_ins.tx_reg_state[0]
-.sym 23029 smi_ctrl_ins.tx_reg_state[3]
-.sym 23032 i_rst_b$SB_IO_IN
-.sym 23033 w_smi_data_input[7]
-.sym 23034 smi_ctrl_ins.tx_reg_state[3]
-.sym 23035 smi_ctrl_ins.tx_reg_state[0]
-.sym 23038 smi_ctrl_ins.tx_reg_state[2]
-.sym 23040 w_smi_data_input[7]
-.sym 23041 i_rst_b$SB_IO_IN
-.sym 23044 w_smi_data_input[7]
-.sym 23045 smi_ctrl_ins.tx_reg_state[0]
-.sym 23047 i_rst_b$SB_IO_IN
-.sym 23050 w_smi_data_input[7]
-.sym 23052 i_rst_b$SB_IO_IN
-.sym 23053 smi_ctrl_ins.tx_reg_state[1]
-.sym 23056 i_ss$SB_IO_IN
-.sym 23062 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
-.sym 23063 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
-.sym 23068 smi_ctrl_ins.tx_reg_state[1]
-.sym 23069 w_smi_data_input[7]
-.sym 23071 smi_ctrl_ins.tx_reg_state[2]
-.sym 23073 smi_ctrl_ins.swe_and_reset
-.sym 23099 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 23103 $io_pmod[3]$iobuf_i
+.sym 22977 i_ss$SB_IO_IN
+.sym 23002 tx_fifo.rd_addr_gray[8]
+.sym 23019 tx_fifo.rd_addr_gray_wr[8]
+.sym 23038 tx_fifo.rd_addr_gray[8]
+.sym 23070 tx_fifo.rd_addr_gray_wr[8]
+.sym 23073 r_counter_$glb_clk
 .sym 23104 i_sck$SB_IO_IN
 .sym 23108 i_sck$SB_IO_IN
-.sym 23116 i_rst_b$SB_IO_IN
-.sym 23129 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
-.sym 23131 w_smi_data_input[7]
-.sym 23132 i_smi_swe_srw$rename$0
-.sym 23141 smi_ctrl_ins.swe_and_reset
-.sym 23158 w_smi_data_input[7]
-.sym 23185 i_rst_b$SB_IO_IN
-.sym 23187 i_smi_swe_srw$rename$0
-.sym 23196 smi_ctrl_ins.swe_and_reset
-.sym 23197 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
-.sym 23198 i_smi_swe_srw$rename$0
-.sym 23199 smi_ctrl_ins.swe_and_reset
-.sym 23200 spi_if_ins.spi.r2_rx_done
-.sym 23201 spi_if_ins.spi.r3_rx_done
-.sym 23204 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 23226 i_ss$SB_IO_IN
-.sym 23246 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 23252 i_ss$SB_IO_IN
-.sym 23257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
-.sym 23264 i_sck$SB_IO_IN
-.sym 23273 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 23318 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
-.sym 23319 i_sck$SB_IO_IN
-.sym 23320 i_ss$SB_IO_IN
-.sym 23328 spi_if_ins.spi.SCKr[0]
-.sym 23347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
-.sym 23354 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23365 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 23369 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 23373 o_miso_$_TBUF__Y_E
-.sym 23375 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 23376 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 23137 i_ss$SB_IO_IN
+.sym 23150 i_ss$SB_IO_IN
+.sym 23362 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 23364 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 23368 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 23373 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 23377 spi_if_ins.spi.r_temp_rx_byte[1]
 .sym 23378 i_sck$SB_IO_IN
-.sym 23382 spi_if_ins.spi.r_temp_rx_byte[4]
 .sym 23386 i_mosi$SB_IO_IN
-.sym 23388 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 23396 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 23410 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 23415 i_mosi$SB_IO_IN
-.sym 23421 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 23425 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 23432 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 23440 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 23387 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 23389 o_miso_$_TBUF__Y_E
+.sym 23395 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 23402 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 23409 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 23414 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 23428 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 23432 i_mosi$SB_IO_IN
+.sym 23440 spi_if_ins.spi.r_temp_rx_byte[0]
 .sym 23441 o_miso_$_TBUF__Y_E
 .sym 23442 i_sck$SB_IO_IN
-.sym 23445 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
-.sym 23451 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
-.sym 23455 o_led0$SB_IO_OUT
-.sym 23467 io_pmod[6]$SB_IO_IN
-.sym 23468 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 23473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23478 w_load
-.sym 23487 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
-.sym 23489 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23491 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 23493 i_smi_soe_se$SB_IO_IN
-.sym 23498 i_ss$SB_IO_IN
-.sym 23499 i_rst_b$SB_IO_IN
-.sym 23502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
-.sym 23510 spi_if_ins.r_tx_data_valid
-.sym 23511 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
-.sym 23519 i_smi_soe_se$SB_IO_IN
-.sym 23521 i_rst_b$SB_IO_IN
-.sym 23525 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 23530 i_ss$SB_IO_IN
-.sym 23532 spi_if_ins.r_tx_data_valid
-.sym 23537 spi_if_ins.r_tx_data_valid
-.sym 23539 i_ss$SB_IO_IN
-.sym 23543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
-.sym 23544 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
-.sym 23545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23564 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 23474 w_rx_data[0]
+.sym 23486 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 23493 i_rst_b$SB_IO_IN
+.sym 23496 spi_if_ins.r_tx_byte[7]
+.sym 23500 i_smi_soe_se$SB_IO_IN
+.sym 23503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 23514 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 23542 i_smi_soe_se$SB_IO_IN
+.sym 23543 i_rst_b$SB_IO_IN
+.sym 23554 spi_if_ins.r_tx_byte[7]
+.sym 23555 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 23556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 23564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
 .sym 23565 r_counter_$glb_clk
-.sym 23566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23569 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 23570 w_load
-.sym 23579 smi_ctrl_ins.soe_and_reset
-.sym 23587 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 23592 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23594 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 23602 spi_if_ins.r_tx_byte[7]
-.sym 23613 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23614 i_rst_b$SB_IO_IN
-.sym 23619 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
-.sym 23621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
-.sym 23634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 23635 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 23637 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
-.sym 23665 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
-.sym 23671 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23677 i_rst_b$SB_IO_IN
-.sym 23678 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 23679 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
-.sym 23680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-.sym 23687 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 23568 r_counter
+.sym 23582 spi_if_ins.r_tx_byte[7]
+.sym 23589 smi_ctrl_ins.soe_and_reset
+.sym 23591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 23593 o_led1_SB_LUT4_I1_I3[3]
+.sym 23601 io_pmod_out[3]$SB_IO_OUT
+.sym 23610 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
+.sym 23634 w_rx_data[0]
+.sym 23671 w_rx_data[0]
+.sym 23687 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
 .sym 23688 r_counter_$glb_clk
-.sym 23689 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
-.sym 23703 $PACKER_VCC_NET
-.sym 23705 w_load
-.sym 23710 i_rst_b$SB_IO_IN
-.sym 23714 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 23733 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 23752 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23755 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 23762 spi_if_ins.r_tx_byte[7]
-.sym 23765 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 23766 spi_if_ins.r_tx_byte[7]
-.sym 23767 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 23810 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 23689 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 23696 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 23719 i_glob_clock$SB_IO_IN
+.sym 23736 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23737 w_load
+.sym 23738 w_cs[2]
+.sym 23752 w_fetch
+.sym 23753 o_led1_SB_LUT4_I1_I3[3]
+.sym 23758 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 23760 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 23770 w_fetch
+.sym 23771 w_load
+.sym 23772 w_cs[2]
+.sym 23773 o_led1_SB_LUT4_I1_I3[3]
+.sym 23801 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23810 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
 .sym 23811 r_counter_$glb_clk
-.sym 23839 o_led1_SB_DFFER_Q_E
-.sym 23845 w_rx_data[0]
-.sym 23855 io_pmod[6]$SB_IO_IN
-.sym 23856 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 23874 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 23884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 23929 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 23930 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2]
-.sym 23931 io_pmod[6]$SB_IO_IN
-.sym 23933 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 23934 lvds_clock_$glb_clk
-.sym 23935 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 23942 $io_pmod[0]$iobuf_i
-.sym 23954 $PACKER_GND_NET
-.sym 23961 o_led0$SB_IO_OUT
-.sym 23967 o_led1$SB_IO_OUT
-.sym 24071 lvds_clock
-.sym 24111 o_led1_SB_DFFER_Q_E
-.sym 24114 w_rx_data[1]
-.sym 24117 w_rx_data[0]
-.sym 24139 w_rx_data[1]
-.sym 24172 w_rx_data[0]
-.sym 24179 o_led1_SB_DFFER_Q_E
+.sym 23812 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
+.sym 23816 o_led0$SB_IO_OUT
+.sym 23818 o_led1$SB_IO_OUT
+.sym 23829 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
+.sym 23834 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 23837 io_pmod_out[0]$SB_IO_OUT
+.sym 23839 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 23841 io_pmod_out[1]$SB_IO_OUT
+.sym 23845 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 23847 io_pmod_out[3]$SB_IO_OUT
+.sym 23856 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 23858 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 23860 w_load
+.sym 23868 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 23872 w_cs[1]
+.sym 23875 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 23876 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 23878 w_fetch
+.sym 23879 i_glob_clock$SB_IO_IN
+.sym 23884 o_led1_SB_LUT4_I1_I3[3]
+.sym 23887 w_load
+.sym 23888 o_led1_SB_LUT4_I1_I3[3]
+.sym 23889 w_cs[1]
+.sym 23890 w_fetch
+.sym 23917 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 23918 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 23919 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 23920 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 23933 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 23934 i_glob_clock$SB_IO_IN
+.sym 23936 io_pmod_out[1]$SB_IO_OUT
+.sym 23939 io_pmod_out[3]$SB_IO_OUT
+.sym 23941 io_pmod_out[2]$SB_IO_OUT
+.sym 23942 io_pmod_out[0]$SB_IO_OUT
+.sym 23951 o_led0$SB_IO_OUT
+.sym 23961 o_led0_SB_LUT4_I1_O[1]
+.sym 23962 o_led0$SB_IO_OUT
+.sym 23964 w_rx_data[1]
+.sym 23967 i_button_SB_LUT4_I0_O[1]
+.sym 23970 w_rx_data[7]
+.sym 23977 w_rx_data[7]
+.sym 23981 w_rx_data[3]
+.sym 23984 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 23988 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 23994 o_shdn_tx_lna$SB_IO_OUT
+.sym 23995 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
+.sym 23996 i_button_SB_LUT4_I0_I3[2]
+.sym 23999 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 24005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+.sym 24006 io_pmod_out[2]$SB_IO_OUT
+.sym 24007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 24017 w_rx_data[7]
+.sym 24022 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 24023 o_shdn_tx_lna$SB_IO_OUT
+.sym 24024 io_pmod_out[2]$SB_IO_OUT
+.sym 24025 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 24028 i_button_SB_LUT4_I0_I3[2]
+.sym 24030 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+.sym 24031 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
+.sym 24048 w_rx_data[3]
+.sym 24052 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 24054 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 24055 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 24056 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
+.sym 24057 r_counter_$glb_clk
+.sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 24065 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
+.sym 24085 io_pmod_out[3]$SB_IO_OUT
+.sym 24102 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
+.sym 24103 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 24104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 24105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 24117 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 24121 o_led0_SB_LUT4_I1_O[1]
+.sym 24125 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 24163 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 24164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 24165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 24175 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 24177 o_led0_SB_LUT4_I1_O[1]
+.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
 .sym 24180 r_counter_$glb_clk
-.sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr
-.sym 24443 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 24181 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.sym 24182 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 24196 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
+.sym 24206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 24208 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 24211 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 24225 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 24226 i_button_SB_LUT4_I0_I3[2]
+.sym 24227 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
+.sym 24231 o_led1_SB_LUT4_I1_I3[0]
+.sym 24232 o_led1_SB_LUT4_I1_I3[3]
+.sym 24234 o_led0$SB_IO_OUT
+.sym 24237 i_button_SB_LUT4_I0_O[1]
+.sym 24238 i_config[0]$SB_IO_IN
+.sym 24241 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 24244 o_tr_vc2$SB_IO_OUT
+.sym 24249 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 24258 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
+.sym 24259 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 24263 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 24264 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 24280 o_led0$SB_IO_OUT
+.sym 24281 o_led1_SB_LUT4_I1_I3[0]
+.sym 24282 o_led1_SB_LUT4_I1_I3[3]
+.sym 24283 i_button_SB_LUT4_I0_I3[2]
+.sym 24286 i_button_SB_LUT4_I0_O[1]
+.sym 24287 i_config[0]$SB_IO_IN
+.sym 24288 o_tr_vc2$SB_IO_OUT
+.sym 24289 o_led1_SB_LUT4_I1_I3[3]
+.sym 24302 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
+.sym 24303 r_counter_$glb_clk
+.sym 24304 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 24313 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 24317 i_glob_clock$SB_IO_IN
+.sym 24321 w_rx_fifo_full
+.sym 24349 o_led0_SB_LUT4_I1_O[1]
+.sym 24361 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 24364 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 24366 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 24372 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 24415 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 24416 o_led0_SB_LUT4_I1_O[1]
+.sym 24418 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 24425 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 24426 r_counter_$glb_clk
+.sym 24427 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .sym 24596 o_led0$SB_IO_OUT
-.sym 24609 o_led0$SB_IO_OUT
+.sym 24607 o_led0$SB_IO_OUT
 .sym 24659 i_sck$SB_IO_IN
-.sym 25401 io_pmod[7]$SB_IO_IN
-.sym 25408 io_pmod[0]$SB_IO_IN
-.sym 25480 spi_if_ins.spi.r_rx_done
-.sym 25496 i_smi_swe_srw$rename$0
-.sym 25498 spi_if_ins.spi.r2_rx_done
-.sym 25499 spi_if_ins.spi.r3_rx_done
-.sym 25502 smi_ctrl_ins.swe_and_reset
-.sym 25508 i_smi_swe_srw$rename$0
-.sym 25511 smi_ctrl_ins.swe_and_reset
-.sym 25518 spi_if_ins.spi.r_rx_done
-.sym 25523 spi_if_ins.spi.r2_rx_done
-.sym 25543 spi_if_ins.spi.r3_rx_done
-.sym 25544 spi_if_ins.spi.r2_rx_done
-.sym 25552 r_counter_$glb_clk
-.sym 25554 i_smi_swe_srw$rename$0
-.sym 25556 io_pmod[6]$SB_IO_IN
-.sym 25655 i_sck$SB_IO_IN
-.sym 25702 i_sck$SB_IO_IN
-.sym 25707 r_counter_$glb_clk
+.sym 24865 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
+.sym 24868 smi_ctrl_ins.swe_and_reset
+.sym 24882 w_smi_data_input[7]
+.sym 24927 w_smi_data_input[7]
+.sym 24932 smi_ctrl_ins.swe_and_reset
+.sym 24933 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
+.sym 25100 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 25401 io_pmod_in[3]$SB_IO_IN
+.sym 25556 io_pmod_in[2]$SB_IO_IN
 .sym 25711 i_glob_clock$SB_IO_IN
-.sym 25724 $io_pmod[3]$iobuf_i
-.sym 25797 spi_if_ins.spi.SCKr[0]
-.sym 25813 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
-.sym 25822 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
-.sym 25858 spi_if_ins.spi.SCKr[0]
-.sym 25862 r_counter_$glb_clk
+.sym 25720 io_pmod_out[3]$SB_IO_OUT
 .sym 25878 i_glob_clock$SB_IO_IN
-.sym 25950 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
-.sym 25957 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 25963 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 25964 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 25984 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 25990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 26016 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 26017 r_counter_$glb_clk
-.sym 26018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
-.sym 26329 io_pmod[0]$SB_IO_IN
-.sym 26347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
-.sym 26410 lvds_clock
-.sym 26472 lvds_clock
-.sym 26488 lvds_clock
-.sym 26648 o_rx_h_tx_l$SB_IO_OUT
-.sym 26968 o_tr_vc1_b$SB_IO_OUT
-.sym 27248 o_smi_read_req$SB_IO_OUT
+.sym 25954 r_counter
+.sym 25962 i_glob_clock$SB_IO_IN
+.sym 25978 r_counter
+.sym 26017 i_glob_clock$SB_IO_IN
+.sym 26018 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 26094 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 26113 spi_if_ins.w_rx_data[1]
+.sym 26164 spi_if_ins.w_rx_data[1]
+.sym 26171 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 26172 r_counter_$glb_clk
+.sym 26181 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 26258 o_led1_SB_DFFER_Q_E
+.sym 26263 w_rx_data[1]
+.sym 26269 w_rx_data[0]
+.sym 26301 w_rx_data[0]
+.sym 26313 w_rx_data[1]
+.sym 26326 o_led1_SB_DFFER_Q_E
+.sym 26327 r_counter_$glb_clk
+.sym 26328 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 26405 w_rx_data[2]
+.sym 26419 w_rx_data[3]
+.sym 26421 w_rx_data[0]
+.sym 26429 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 26431 w_rx_data[1]
+.sym 26435 w_rx_data[1]
+.sym 26453 w_rx_data[3]
+.sym 26467 w_rx_data[2]
+.sym 26474 w_rx_data[0]
+.sym 26481 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 26482 r_counter_$glb_clk
+.sym 26495 w_rx_data[2]
+.sym 26575 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 26577 w_rx_fifo_full
+.sym 26583 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 26626 w_rx_fifo_full
+.sym 26627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 26636 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 26637 lvds_clock_$glb_clk
+.sym 26638 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 26719 w_rx_fifo_full
+.sym 26723 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 26729 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 26730 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 26745 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 26746 w_rx_fifo_full
+.sym 26748 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 26791 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.sym 26792 lvds_clock_$glb_clk
+.sym 26793 i_rst_b_SB_LUT4_I3_O_$glb_sr
+.sym 26807 o_tr_vc2$SB_IO_OUT
+.sym 26811 o_rx_h_tx_l$SB_IO_OUT
+.sym 26960 o_tr_vc1_b$SB_IO_OUT
 .sym 27283 o_smi_read_req$SB_IO_OUT
-.sym 27292 o_smi_read_req$SB_IO_OUT
-.sym 27365 io_pmod[0]$SB_IO_IN
+.sym 27296 o_smi_read_req$SB_IO_OUT
+.sym 27307 i_mosi$SB_IO_IN
 .sym 27397 i_glob_clock$SB_IO_IN
-.sym 27400 $io_pmod[3]$iobuf_i
-.sym 27422 $io_pmod[3]$iobuf_i
+.sym 27400 io_pmod_out[3]$SB_IO_OUT
+.sym 27420 io_pmod_out[3]$SB_IO_OUT
 .sym 27429 smi_ctrl_ins.soe_and_reset
 .sym 27444 smi_ctrl_ins.soe_and_reset
-.sym 27457 lvds_clock
-.sym 27459 lvds_clock
-.sym 27483 lvds_clock
-.sym 27485 io_pmod[0]$SB_IO_IN
-.sym 27514 io_pmod[0]$SB_IO_IN
-.sym 27519 $PACKER_GND_NET
-.sym 27522 $PACKER_GND_NET
-.sym 27529 $PACKER_GND_NET
-.sym 27537 $PACKER_GND_NET
-.sym 27545 o_tr_vc1$SB_IO_OUT
-.sym 27547 o_tr_vc2$SB_IO_OUT
-.sym 27549 $io_pmod[0]$iobuf_i
-.sym 27564 $io_pmod[0]$iobuf_i
+.sym 27459 r_counter
+.sym 27470 r_counter
+.sym 27515 o_rx_h_tx_l$SB_IO_OUT
+.sym 27516 i_glob_clock$SB_IO_IN
+.sym 27519 io_pmod_out[2]$SB_IO_OUT
+.sym 27522 io_pmod_out[1]$SB_IO_OUT
+.sym 27536 io_pmod_out[1]$SB_IO_OUT
+.sym 27541 io_pmod_out[2]$SB_IO_OUT
+.sym 27549 io_pmod_out[0]$SB_IO_OUT
+.sym 27564 io_pmod_out[0]$SB_IO_OUT
+.sym 27577 o_rx_h_tx_l_b$SB_IO_OUT
 .sym 27582 o_rx_h_tx_l$SB_IO_OUT
-.sym 27589 o_rx_h_tx_l$SB_IO_OUT
+.sym 27593 o_rx_h_tx_l$SB_IO_OUT
 .sym 27605 o_tr_vc1$SB_IO_OUT
 .sym 27608 o_tr_vc2$SB_IO_OUT
-.sym 27621 o_tr_vc2$SB_IO_OUT
-.sym 27627 o_tr_vc1$SB_IO_OUT
+.sym 27617 o_tr_vc2$SB_IO_OUT
+.sym 27620 o_tr_vc1$SB_IO_OUT
 .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
 .sym 27634 o_tr_vc1_b$SB_IO_OUT
-.sym 27641 o_tr_vc1_b$SB_IO_OUT
-.sym 27646 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 27715 w_rx_24_fifo_data[15]
-.sym 27716 w_rx_09_fifo_data[15]
-.sym 27717 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27720 w_rx_09_fifo_data[13]
-.sym 27721 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27732 w_rx_09_fifo_data[11]
-.sym 27733 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27744 w_rx_09_fifo_data[15]
-.sym 27745 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27747 w_rx_09_fifo_data[9]
-.sym 27748 w_rx_24_fifo_data[9]
-.sym 27749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27751 w_rx_09_fifo_data[17]
-.sym 27752 w_rx_24_fifo_data[17]
-.sym 27753 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27756 w_rx_09_fifo_data[6]
-.sym 27757 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27760 w_rx_09_fifo_data[9]
-.sym 27761 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27764 w_rx_09_fifo_data[17]
-.sym 27765 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27768 w_rx_09_fifo_data[7]
-.sym 27769 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27772 w_rx_09_fifo_data[5]
-.sym 27773 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27775 w_rx_09_fifo_data[11]
-.sym 27776 w_rx_24_fifo_data[11]
-.sym 27777 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27780 w_rx_24_fifo_data[7]
-.sym 27781 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27784 w_rx_24_fifo_data[15]
-.sym 27785 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27788 w_rx_24_fifo_data[13]
-.sym 27789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27796 w_rx_24_fifo_data[17]
-.sym 27797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27800 w_rx_24_fifo_data[11]
-.sym 27801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27803 w_rx_24_fifo_data[19]
-.sym 27804 w_rx_09_fifo_data[19]
-.sym 27805 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27808 w_rx_24_fifo_data[9]
-.sym 27809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27812 w_rx_24_fifo_data[21]
-.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27815 w_rx_24_fifo_data[5]
-.sym 27816 w_rx_09_fifo_data[5]
-.sym 27817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27819 w_rx_24_fifo_data[7]
-.sym 27820 w_rx_09_fifo_data[7]
-.sym 27821 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27824 w_rx_24_fifo_data[3]
-.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27828 w_rx_24_fifo_data[23]
-.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27832 w_rx_24_fifo_data[19]
-.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27836 i_rst_b$SB_IO_IN
-.sym 27837 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
-.sym 27840 w_rx_24_fifo_data[5]
-.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 27844 w_rx_09_fifo_data[4]
-.sym 27845 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27848 w_rx_09_fifo_data[23]
-.sym 27849 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27852 w_rx_09_fifo_data[21]
-.sym 27853 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27855 w_rx_24_fifo_data[23]
-.sym 27856 w_rx_09_fifo_data[23]
-.sym 27857 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27859 w_rx_09_fifo_data[21]
-.sym 27860 w_rx_24_fifo_data[21]
-.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27863 w_rx_09_fifo_data[27]
-.sym 27864 w_rx_24_fifo_data[27]
-.sym 27865 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
-.sym 27868 w_rx_09_fifo_data[19]
-.sym 27869 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27872 w_rx_09_fifo_data[25]
-.sym 27873 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27876 w_rx_09_fifo_data[29]
-.sym 27877 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27880 w_rx_09_fifo_data[27]
-.sym 27881 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27884 w_rx_09_fifo_data[0]
-.sym 27885 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27888 w_rx_09_fifo_data[1]
-.sym 27889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27892 w_rx_09_fifo_data[28]
-.sym 27893 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27896 w_rx_09_fifo_data[2]
-.sym 27897 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27900 w_rx_09_fifo_data[3]
-.sym 27901 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 27909 rx_fifo.wr_addr[0]
-.sym 27910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 27914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 27933 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
+.sym 27643 o_tr_vc1_b$SB_IO_OUT
+.sym 27655 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 27720 w_rx_09_fifo_data[12]
+.sym 27721 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27724 w_rx_09_fifo_data[10]
+.sym 27725 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27748 w_rx_09_fifo_data[21]
+.sym 27749 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27752 w_rx_09_fifo_data[23]
+.sym 27753 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27759 w_rx_24_fifo_data[25]
+.sym 27760 w_rx_09_fifo_data[25]
+.sym 27761 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27763 w_rx_24_fifo_data[27]
+.sym 27764 w_rx_09_fifo_data[27]
+.sym 27765 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27768 w_rx_09_fifo_data[25]
+.sym 27769 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27771 w_rx_09_fifo_data[23]
+.sym 27772 w_rx_24_fifo_data[23]
+.sym 27773 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27780 w_rx_09_fifo_data[13]
+.sym 27781 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27784 w_rx_09_fifo_data[17]
+.sym 27785 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27787 w_rx_24_fifo_data[13]
+.sym 27788 w_rx_09_fifo_data[13]
+.sym 27789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27796 w_rx_09_fifo_data[19]
+.sym 27797 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27800 w_rx_09_fifo_data[27]
+.sym 27801 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27804 w_rx_09_fifo_data[15]
+.sym 27805 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27808 w_rx_09_fifo_data[8]
+.sym 27809 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27812 w_rx_09_fifo_data[4]
+.sym 27813 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27816 w_rx_09_fifo_data[7]
+.sym 27817 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27820 w_rx_09_fifo_data[9]
+.sym 27821 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27824 w_rx_09_fifo_data[29]
+.sym 27825 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27828 w_rx_09_fifo_data[5]
+.sym 27829 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27832 w_rx_09_fifo_data[6]
+.sym 27833 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27836 w_rx_09_fifo_data[11]
+.sym 27837 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27839 w_rx_24_fifo_data[7]
+.sym 27840 w_rx_09_fifo_data[7]
+.sym 27841 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27843 w_rx_09_fifo_data[4]
+.sym 27844 w_rx_24_fifo_data[4]
+.sym 27845 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27847 w_rx_09_fifo_data[9]
+.sym 27848 w_rx_24_fifo_data[9]
+.sym 27849 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27852 w_rx_24_fifo_data[13]
+.sym 27853 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27856 w_rx_24_fifo_data[9]
+.sym 27857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27859 w_rx_24_fifo_data[11]
+.sym 27860 w_rx_09_fifo_data[11]
+.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27864 w_rx_24_fifo_data[4]
+.sym 27865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27868 w_rx_24_fifo_data[11]
+.sym 27869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27872 w_rx_24_fifo_data[7]
+.sym 27873 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27876 w_rx_24_fifo_data[5]
+.sym 27877 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27880 w_rx_24_fifo_data[0]
+.sym 27881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27889 lvds_clock
+.sym 27892 w_rx_24_fifo_data[3]
+.sym 27893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27895 w_rx_24_fifo_data[5]
+.sym 27896 w_rx_09_fifo_data[5]
+.sym 27897 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27900 w_rx_24_fifo_data[1]
+.sym 27901 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27904 w_rx_24_fifo_data[2]
+.sym 27905 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 27908 w_rx_09_fifo_data[3]
+.sym 27909 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27912 w_rx_09_fifo_data[28]
+.sym 27913 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27916 w_rx_09_fifo_data[2]
+.sym 27917 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27919 w_rx_09_fifo_data[3]
+.sym 27920 w_rx_24_fifo_data[3]
+.sym 27921 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27924 w_rx_09_fifo_data[0]
+.sym 27925 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27927 w_rx_24_fifo_data[2]
+.sym 27928 w_rx_09_fifo_data[2]
+.sym 27929 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 27932 w_rx_09_fifo_data[1]
+.sym 27933 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 27937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
 .sym 27939 rx_fifo.wr_addr[1]
 .sym 27944 rx_fifo.wr_addr[2]
 .sym 27945 rx_fifo.wr_addr[1]
 .sym 27948 rx_fifo.wr_addr[3]
-.sym 27949 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3
+.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
 .sym 27952 rx_fifo.wr_addr[4]
-.sym 27953 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
+.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
 .sym 27956 rx_fifo.wr_addr[5]
-.sym 27957 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
 .sym 27960 rx_fifo.wr_addr[6]
-.sym 27961 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
 .sym 27964 rx_fifo.wr_addr[7]
-.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 27965 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
 .sym 27968 rx_fifo.wr_addr[8]
-.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 27969 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
 .sym 27972 rx_fifo.wr_addr[9]
-.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 27975 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 27976 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
-.sym 27977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.sym 27978 rx_fifo.rd_addr_gray_wr[6]
-.sym 27982 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 27983 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
-.sym 27984 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.sym 27985 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
-.sym 27986 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 27987 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.sym 27988 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 27989 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
-.sym 27991 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 27992 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.sym 27993 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 27996 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 27997 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-.sym 27999 rx_fifo.rd_addr_gray_wr_r[3]
-.sym 28000 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.sym 28001 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
-.sym 28002 rx_fifo.rd_addr_gray_wr[4]
-.sym 28008 i_rst_b$SB_IO_IN
-.sym 28009 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
-.sym 28010 rx_fifo.rd_addr_gray[4]
-.sym 28016 rx_fifo.rd_addr_gray_wr_r[5]
-.sym 28017 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 28018 rx_fifo.rd_addr_gray_wr[2]
-.sym 28024 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
-.sym 28025 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
-.sym 28026 rx_fifo.rd_addr_gray_wr_r[6]
-.sym 28027 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 28028 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 28029 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 28031 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 28032 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 28033 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 28034 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 28040 rx_fifo.rd_addr_gray_wr_r[7]
-.sym 28041 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 28042 w_lvds_rx_09_d0
-.sym 28043 w_lvds_rx_09_d1
-.sym 28044 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28045 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 28051 rx_fifo.rd_addr_gray_wr_r[9]
-.sym 28052 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 28054 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
-.sym 28055 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
-.sym 28056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
-.sym 28057 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
-.sym 28060 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 28061 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.sym 28062 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 28063 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 28064 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 28065 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 28068 rx_fifo.rd_addr_gray_wr_r[4]
-.sym 28069 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 28072 w_lvds_rx_24_d1
-.sym 28073 w_lvds_rx_24_d0
-.sym 28076 w_lvds_rx_09_d0
-.sym 28077 w_lvds_rx_09_d1
-.sym 28079 w_rx_fifo_full
-.sym 28080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 28083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28084 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 28085 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.sym 28086 w_lvds_rx_24_d1
-.sym 28087 w_lvds_rx_24_d0
-.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28089 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
+.sym 27973 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
+.sym 27977 w_lvds_rx_24_d0
+.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
+.sym 27983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
+.sym 27984 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
+.sym 27985 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
+.sym 27987 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 27988 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.sym 27989 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 27991 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 27992 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
+.sym 27993 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 27995 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 27996 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.sym 27997 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 27998 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
+.sym 28002 w_lvds_rx_09_d0
+.sym 28012 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 28013 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 28016 i_rst_b$SB_IO_IN
+.sym 28017 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
+.sym 28035 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 28038 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28039 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
+.sym 28040 $PACKER_VCC_NET
+.sym 28041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
+.sym 28042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 28044 $PACKER_VCC_NET
+.sym 28045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28048 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 28049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+.sym 28061 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
+.sym 28062 w_lvds_rx_09_d1
+.sym 28063 w_lvds_rx_09_d0
+.sym 28064 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 28065 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 28066 w_lvds_rx_24_d1
+.sym 28067 w_lvds_rx_24_d0
+.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28073 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 28075 w_lvds_rx_24_d1
+.sym 28076 w_lvds_rx_24_d0
+.sym 28077 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 28084 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
+.sym 28085 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
+.sym 28086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
+.sym 28087 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28089 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
 .sym 28090 w_lvds_rx_24_d1
 .sym 28091 w_lvds_rx_24_d0
-.sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
-.sym 28096 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28097 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
-.sym 28100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
-.sym 28101 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
-.sym 28110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
-.sym 28111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3]
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-.sym 28979 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 28980 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 28982 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 28986 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 28987 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 28988 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 28989 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 28991 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-.sym 28993 rx_fifo.rd_addr[3]
-.sym 28996 rx_fifo.rd_addr[8]
-.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-.sym 28998 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 28999 rx_fifo.rd_addr[6]
-.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 29001 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 29003 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
-.sym 29004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
-.sym 29005 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
-.sym 29006 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 29007 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-.sym 29008 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 29009 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
-.sym 29010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 29011 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 29012 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
-.sym 29013 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.sym 29014 rx_fifo.rd_addr_gray[6]
-.sym 29020 rx_fifo.rd_addr[6]
-.sym 29021 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 29022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-.sym 29023 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 29024 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 29025 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
-.sym 29026 rx_fifo.rd_addr_gray[8]
-.sym 29030 rx_fifo.rd_addr_gray_wr[8]
-.sym 29034 rx_fifo.rd_addr_gray_wr[9]
-.sym 29038 rx_fifo.rd_addr_gray[2]
-.sym 29043 rx_fifo.rd_addr_gray_wr_r[2]
-.sym 29044 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 29045 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29046 rx_fifo.rd_addr[9]
-.sym 29050 rx_fifo.rd_addr_gray_wr[5]
-.sym 29054 rx_fifo.rd_addr_gray[5]
-.sym 29065 w_lvds_rx_24_d0
-.sym 29066 rx_fifo.rd_addr_gray_wr_r[8]
-.sym 29067 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29071 w_lvds_rx_24_d1
-.sym 29072 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
-.sym 29073 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-.sym 29090 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 29094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
-.sym 29098 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
-.sym 29104 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-.sym 29105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29106 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
-.sym 29112 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
-.sym 29113 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29121 rx_fifo.wr_addr[1]
-.sym 29122 rx_fifo.wr_addr_gray[7]
-.sym 29126 rx_fifo.wr_addr_gray_rd[6]
-.sym 29130 rx_fifo.wr_addr_gray[4]
-.sym 29138 rx_fifo.wr_addr_gray_rd[4]
-.sym 29146 rx_fifo.wr_addr_gray[6]
-.sym 29150 rx_fifo.wr_addr_gray_rd[7]
-.sym 29166 rx_fifo.rd_addr_gray[3]
-.sym 29174 rx_fifo.rd_addr_gray_wr[3]
-.sym 29220 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29221 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29224 tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.sym 29225 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29226 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29232 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 29233 tx_fifo.rd_addr[2]
-.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29241 tx_fifo.rd_addr[0]
-.sym 29242 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29251 tx_fifo.rd_addr[0]
-.sym 29256 tx_fifo.rd_addr[1]
-.sym 29257 tx_fifo.rd_addr[0]
-.sym 29260 tx_fifo.rd_addr[2]
-.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 29264 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 29265 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 29268 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 29272 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 29273 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 29276 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 29277 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3
-.sym 29280 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 29284 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 29285 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 29288 tx_fifo.rd_addr[9]
-.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 29292 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 29293 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.sym 29294 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 29295 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 29296 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 29297 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 29299 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 29300 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
-.sym 29301 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 29302 tx_fifo.rd_addr_gray[2]
-.sym 29306 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
-.sym 29307 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
-.sym 29308 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
-.sym 29309 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
-.sym 29310 tx_fifo.rd_addr_gray[4]
-.sym 29314 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
-.sym 29321 tx_fifo.rd_addr[1]
-.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[8]
-.sym 29323 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29324 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29325 smi_ctrl_ins.r_fifo_pulled_data[0]
-.sym 29328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29329 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[14]
-.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[6]
+.sym 28297 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28299 w_rx_24_fifo_data[21]
+.sym 28300 w_rx_09_fifo_data[21]
+.sym 28301 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28303 w_rx_24_fifo_data[15]
+.sym 28304 w_rx_09_fifo_data[15]
+.sym 28305 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28308 w_rx_09_fifo_data[26]
+.sym 28309 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 28311 w_rx_24_fifo_data[10]
+.sym 28312 w_rx_09_fifo_data[10]
+.sym 28313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28315 w_rx_09_fifo_data[18]
+.sym 28316 w_rx_24_fifo_data[18]
+.sym 28317 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28320 w_rx_09_fifo_data[16]
+.sym 28321 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 28322 w_rx_fifo_pulled_data[5]
+.sym 28335 w_rx_24_fifo_data[8]
+.sym 28336 w_rx_09_fifo_data[8]
+.sym 28337 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28339 w_rx_24_fifo_data[29]
+.sym 28340 w_rx_09_fifo_data[29]
+.sym 28341 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28343 w_rx_09_fifo_data[17]
+.sym 28344 w_rx_24_fifo_data[17]
+.sym 28345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28347 w_rx_09_fifo_data[6]
+.sym 28348 w_rx_24_fifo_data[6]
+.sym 28349 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28351 w_rx_24_fifo_data[19]
+.sym 28352 w_rx_09_fifo_data[19]
+.sym 28353 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28356 w_rx_24_fifo_data[6]
+.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28360 w_rx_24_fifo_data[19]
+.sym 28361 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28364 w_rx_24_fifo_data[28]
+.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28368 w_rx_24_fifo_data[17]
+.sym 28369 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28372 w_rx_24_fifo_data[21]
+.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28375 w_rx_09_fifo_data[31]
+.sym 28376 w_rx_24_fifo_data[31]
+.sym 28377 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28380 w_rx_24_fifo_data[29]
+.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28384 w_rx_24_fifo_data[15]
+.sym 28385 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28391 i_rst_b$SB_IO_IN
+.sym 28392 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28393 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 28394 w_rx_fifo_pulled_data[11]
+.sym 28399 w_rx_09_fifo_data[28]
+.sym 28400 w_rx_24_fifo_data[28]
+.sym 28401 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28402 w_rx_fifo_pulled_data[10]
+.sym 28406 w_rx_fifo_pulled_data[18]
+.sym 28410 w_rx_fifo_pulled_data[9]
+.sym 28415 w_rx_09_fifo_data[30]
+.sym 28416 w_rx_24_fifo_data[30]
+.sym 28417 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28418 w_rx_fifo_pulled_data[0]
+.sym 28426 w_rx_fifo_pulled_data[3]
+.sym 28438 w_rx_fifo_pulled_data[1]
+.sym 28442 w_rx_fifo_pulled_data[2]
+.sym 28450 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 28455 w_rx_24_fifo_data[0]
+.sym 28456 w_rx_09_fifo_data[0]
+.sym 28457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28460 rx_fifo.wr_addr[1]
+.sym 28461 rx_fifo.wr_addr[0]
+.sym 28462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 28470 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28475 w_rx_24_fifo_data[1]
+.sym 28476 w_rx_09_fifo_data[1]
+.sym 28477 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28483 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 28484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.sym 28485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.sym 28487 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28488 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
+.sym 28489 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
+.sym 28492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28496 i_rst_b$SB_IO_IN
+.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 28498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 28499 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 28500 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
+.sym 28501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
+.sym 28504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 28505 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.sym 28506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
+.sym 28507 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
+.sym 28508 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
+.sym 28509 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
+.sym 28510 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 28511 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 28512 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
+.sym 28513 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.sym 28514 w_rx_fifo_full
+.sym 28515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 28516 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 28519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 28520 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 28523 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 28526 rx_fifo.rd_addr_gray_wr[0]
+.sym 28530 rx_fifo.rd_addr_gray[0]
+.sym 28535 rx_fifo.full_o_SB_LUT4_I0_O[0]
+.sym 28536 rx_fifo.full_o_SB_LUT4_I0_O[1]
+.sym 28537 rx_fifo.full_o_SB_LUT4_I0_O[2]
+.sym 28538 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
+.sym 28539 rx_fifo.wr_addr[1]
+.sym 28540 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
+.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 28542 rx_fifo.wr_addr[2]
+.sym 28543 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
+.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
+.sym 28546 rx_fifo.rd_addr[9]
+.sym 28554 rx_fifo.rd_addr_gray_wr[9]
+.sym 28562 rx_fifo.rd_addr_gray[5]
+.sym 28566 rx_fifo.rd_addr_gray_wr[5]
+.sym 28584 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 28585 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 28587 w_lvds_rx_24_d1
+.sym 28588 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 28589 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 28604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.sym 28605 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28620 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 28621 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.sym 28624 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28625 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.sym 28636 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.sym 28637 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 28638 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.sym 28664 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
+.sym 28665 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 28670 w_lvds_rx_09_d1
+.sym 28671 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
+.sym 28672 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 28673 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.sym 28706 tx_fifo.rd_addr_gray[3]
+.sym 28710 tx_fifo.rd_addr_gray[2]
+.sym 28714 tx_fifo.rd_addr_gray_wr[5]
+.sym 28718 tx_fifo.rd_addr_gray[5]
+.sym 28722 tx_fifo.rd_addr_gray_wr[6]
+.sym 28726 tx_fifo.rd_addr_gray_wr[3]
+.sym 28730 tx_fifo.rd_addr_gray[6]
+.sym 28738 smi_ctrl_ins.r_fifo_pulled_data[26]
+.sym 28739 smi_ctrl_ins.r_fifo_pulled_data[18]
+.sym 28740 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28741 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28742 w_rx_fifo_pulled_data[13]
+.sym 28746 w_rx_fifo_pulled_data[26]
+.sym 28750 w_rx_fifo_pulled_data[15]
+.sym 28754 w_rx_fifo_pulled_data[23]
+.sym 28758 w_rx_fifo_pulled_data[21]
+.sym 28762 w_rx_fifo_pulled_data[20]
+.sym 28766 w_rx_fifo_pulled_data[22]
+.sym 28782 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 28786 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 28791 tx_fifo.rd_addr[2]
+.sym 28792 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 28793 tx_fifo.rd_addr[1]
+.sym 28794 smi_ctrl_ins.r_fifo_pulled_data[15]
+.sym 28795 smi_ctrl_ins.r_fifo_pulled_data[7]
+.sym 28796 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28797 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28799 w_rx_09_fifo_data[26]
+.sym 28800 w_rx_24_fifo_data[26]
+.sym 28801 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 28802 w_rx_fifo_pulled_data[24]
+.sym 28806 w_rx_fifo_pulled_data[25]
+.sym 28810 w_rx_fifo_pulled_data[27]
+.sym 28814 w_rx_fifo_pulled_data[12]
+.sym 28818 w_rx_fifo_pulled_data[6]
+.sym 28822 w_rx_fifo_pulled_data[14]
+.sym 28826 smi_ctrl_ins.r_fifo_pulled_data[13]
+.sym 28827 smi_ctrl_ins.r_fifo_pulled_data[5]
+.sym 28828 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28829 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[14]
+.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[6]
+.sym 28832 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28833 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28834 w_rx_fifo_pulled_data[8]
+.sym 28842 w_rx_fifo_pulled_data[16]
+.sym 28846 w_rx_fifo_pulled_data[7]
+.sym 28850 smi_ctrl_ins.r_fifo_pulled_data[24]
+.sym 28851 smi_ctrl_ins.r_fifo_pulled_data[16]
+.sym 28852 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28853 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28854 smi_ctrl_ins.r_fifo_pulled_data[10]
+.sym 28855 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28856 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28857 smi_ctrl_ins.r_fifo_pulled_data[2]
+.sym 28862 w_rx_fifo_pulled_data[4]
+.sym 28869 rx_fifo.rd_addr[0]
+.sym 28877 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 28878 smi_ctrl_ins.r_fifo_pulled_data[8]
+.sym 28879 smi_ctrl_ins.int_cnt_rx[4]
+.sym 28880 smi_ctrl_ins.int_cnt_rx[3]
+.sym 28881 smi_ctrl_ins.r_fifo_pulled_data[0]
+.sym 28882 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 28886 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 28897 rx_fifo.wr_addr[4]
+.sym 28899 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 28900 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28901 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 28907 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 28908 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 28909 rx_fifo.rd_addr[5]
+.sym 28910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28922 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 28929 rx_fifo.wr_addr[0]
+.sym 28931 rx_fifo.wr_addr[0]
+.sym 28936 rx_fifo.wr_addr[1]
+.sym 28940 rx_fifo.wr_addr[2]
+.sym 28941 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 28944 rx_fifo.wr_addr[3]
+.sym 28945 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 28948 rx_fifo.wr_addr[4]
+.sym 28949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 28952 rx_fifo.wr_addr[5]
+.sym 28953 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 28956 rx_fifo.wr_addr[6]
+.sym 28957 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 28960 rx_fifo.wr_addr[7]
+.sym 28961 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 28964 rx_fifo.wr_addr[8]
+.sym 28965 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 28968 rx_fifo.wr_addr[9]
+.sym 28969 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 28972 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 28974 rx_fifo.rd_addr_gray_wr_r[1]
+.sym 28975 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 28976 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.sym 28977 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
+.sym 28980 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 28983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 28984 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28985 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28988 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28989 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 28992 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28993 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 28997 rx_fifo.rd_addr[1]
+.sym 28998 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
+.sym 28999 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
+.sym 29000 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
+.sym 29001 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
+.sym 29002 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+.sym 29003 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 29004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 29005 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.sym 29006 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.sym 29007 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 29008 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 29009 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 29014 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 29015 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 29016 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 29017 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 29018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
+.sym 29025 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 29026 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 29031 rx_fifo.rd_addr[5]
+.sym 29032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 29033 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 29038 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 29039 rx_fifo.rd_addr[9]
+.sym 29040 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 29041 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 29042 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 29046 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.sym 29057 rx_fifo.wr_addr[1]
+.sym 29062 rx_fifo.wr_addr_gray_rd[4]
+.sym 29066 rx_fifo.wr_addr_gray_rd[5]
+.sym 29070 rx_fifo.wr_addr_gray_rd[8]
+.sym 29074 rx_fifo.wr_addr_gray[5]
+.sym 29082 rx_fifo.wr_addr_gray[8]
+.sym 29086 rx_fifo.wr_addr_gray[1]
+.sym 29090 rx_fifo.wr_addr_gray[4]
+.sym 29098 rx_fifo.wr_addr_gray[2]
+.sym 29102 rx_fifo.wr_addr_gray[6]
+.sym 29108 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 29110 rx_fifo.wr_addr_gray_rd[2]
+.sym 29118 rx_fifo.wr_addr_gray[3]
+.sym 29124 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 29125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29126 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 29134 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 29150 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 29221 tx_fifo.rd_addr[0]
+.sym 29222 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 29226 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 29230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29238 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29242 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 29251 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29252 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 29253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
+.sym 29255 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 29256 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 29257 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29260 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29264 i_rst_b$SB_IO_IN
+.sym 29265 w_tx_fifo_pull
+.sym 29268 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 29270 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 29275 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 29276 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
+.sym 29277 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.sym 29279 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 29280 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29283 tx_fifo.rd_addr[3]
+.sym 29284 tx_fifo.rd_addr[2]
+.sym 29285 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 29286 tx_fifo.rd_addr[4]
+.sym 29287 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
+.sym 29288 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
+.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
+.sym 29290 smi_ctrl_ins.r_fifo_pulled_data[11]
+.sym 29291 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29292 smi_ctrl_ins.r_fifo_pulled_data[3]
+.sym 29293 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29294 tx_fifo.rd_addr[7]
+.sym 29295 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
+.sym 29296 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
+.sym 29297 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
+.sym 29298 smi_ctrl_ins.r_fifo_pulled_data[31]
+.sym 29299 smi_ctrl_ins.r_fifo_pulled_data[23]
+.sym 29300 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29301 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29302 tx_fifo.rd_addr[7]
+.sym 29303 tx_fifo.rd_addr[6]
+.sym 29304 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 29305 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
+.sym 29307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 29308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.sym 29309 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
+.sym 29310 tx_fifo.wr_addr_gray_rd[1]
+.sym 29316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
+.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
+.sym 29320 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
+.sym 29321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
+.sym 29324 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
+.sym 29325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
+.sym 29328 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29329 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[30]
+.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[22]
 .sym 29332 smi_ctrl_ins.int_cnt_rx[4]
 .sym 29333 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29334 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29339 tx_fifo.rd_addr[9]
-.sym 29340 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 29341 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-.sym 29342 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29346 w_rx_fifo_pulled_data[6]
-.sym 29350 smi_ctrl_ins.r_fifo_pulled_data[12]
-.sym 29351 smi_ctrl_ins.r_fifo_pulled_data[4]
-.sym 29352 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29353 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29354 w_rx_fifo_pulled_data[19]
-.sym 29358 smi_ctrl_ins.r_fifo_pulled_data[27]
-.sym 29359 smi_ctrl_ins.r_fifo_pulled_data[19]
-.sym 29360 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29361 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29362 smi_ctrl_ins.r_fifo_pulled_data[26]
-.sym 29363 smi_ctrl_ins.r_fifo_pulled_data[18]
-.sym 29364 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29365 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29366 w_rx_fifo_pulled_data[18]
-.sym 29370 w_rx_fifo_pulled_data[4]
-.sym 29374 smi_ctrl_ins.r_fifo_pulled_data[11]
-.sym 29375 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29376 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29377 smi_ctrl_ins.r_fifo_pulled_data[3]
-.sym 29388 smi_ctrl_ins.int_cnt_rx[4]
-.sym 29389 smi_ctrl_ins.int_cnt_rx[3]
-.sym 29401 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29336 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
+.sym 29337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
+.sym 29338 smi_ctrl_ins.r_fifo_pulled_data[12]
+.sym 29339 smi_ctrl_ins.r_fifo_pulled_data[4]
+.sym 29340 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29341 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29346 smi_ctrl_ins.w_fifo_pull_trigger
+.sym 29359 smi_ctrl_ins.r_fifo_pull_1
+.sym 29360 w_smi_read_req
+.sym 29361 smi_ctrl_ins.r_fifo_pull
+.sym 29370 smi_ctrl_ins.r_fifo_pulled_data[29]
+.sym 29371 smi_ctrl_ins.r_fifo_pulled_data[21]
+.sym 29372 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29373 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29374 smi_ctrl_ins.r_fifo_pull
+.sym 29378 smi_ctrl_ins.r_fifo_pulled_data[9]
+.sym 29379 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29380 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29381 smi_ctrl_ins.r_fifo_pulled_data[1]
+.sym 29384 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
+.sym 29385 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
+.sym 29388 i_rst_b$SB_IO_IN
+.sym 29389 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 29392 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
+.sym 29393 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
+.sym 29402 smi_ctrl_ins.r_fifo_pulled_data[25]
+.sym 29403 smi_ctrl_ins.r_fifo_pulled_data[17]
+.sym 29404 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29405 smi_ctrl_ins.int_cnt_rx[3]
 .sym 29411 rx_fifo.rd_addr[0]
-.sym 29416 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+.sym 29416 rx_fifo.rd_addr[1]
 .sym 29417 rx_fifo.rd_addr[0]
-.sym 29420 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
+.sym 29420 rx_fifo.rd_addr[2]
 .sym 29421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 29424 rx_fifo.rd_addr[3]
+.sym 29424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
 .sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
-.sym 29428 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
+.sym 29428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
 .sym 29429 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
-.sym 29432 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
-.sym 29436 rx_fifo.rd_addr[6]
-.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
-.sym 29440 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 29444 rx_fifo.rd_addr[8]
-.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29432 rx_fifo.rd_addr[5]
+.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 29436 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29440 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29444 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
 .sym 29448 rx_fifo.rd_addr[9]
-.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 29450 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 29454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
-.sym 29460 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.sym 29461 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
-.sym 29472 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-.sym 29474 rx_fifo.wr_addr_gray[3]
-.sym 29479 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 29480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
-.sym 29481 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.sym 29484 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29485 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 29486 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 29488 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 29490 rx_fifo.wr_addr_gray_rd[2]
-.sym 29494 rx_fifo.wr_addr_gray_rd[3]
-.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-.sym 29499 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 29502 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
-.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
-.sym 29508 i_rst_b$SB_IO_IN
-.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.sym 29512 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-.sym 29513 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 29514 rx_fifo.wr_addr_gray_rd[5]
-.sym 29518 rx_fifo.wr_addr_gray_rd[9]
-.sym 29522 rx_fifo.empty_o_SB_LUT4_I0_O[0]
-.sym 29523 rx_fifo.empty_o_SB_LUT4_I0_O[1]
-.sym 29524 rx_fifo.empty_o_SB_LUT4_I0_O[2]
-.sym 29525 rx_fifo.empty_o_SB_LUT4_I0_O[3]
-.sym 29526 w_rx_fifo_empty
-.sym 29527 rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-.sym 29528 rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-.sym 29529 rx_fifo.empty_o_SB_LUT4_I0_I3[3]
-.sym 29530 rx_fifo.wr_addr_gray_rd[1]
-.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 29535 rx_fifo.rd_addr[9]
-.sym 29536 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-.sym 29537 rx_fifo.rd_addr[8]
-.sym 29538 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.sym 29558 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 29562 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.sym 29566 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.sym 29570 rx_fifo.rd_addr_gray_wr[7]
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-.sym 29582 rx_fifo.rd_addr_gray[0]
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-.sym 29590 rx_fifo.rd_addr_gray_wr[1]
-.sym 29598 rx_fifo.rd_addr_gray[7]
-.sym 29602 rx_fifo.wr_addr_gray[8]
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-.sym 29610 rx_fifo.wr_addr_gray_rd[8]
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-.sym 29622 rx_fifo.wr_addr_gray[5]
-.sym 29630 rx_fifo.wr_addr_gray[1]
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-.sym 29701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q
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-.sym 29746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 29747 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
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-.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 29761 w_smi_data_output[2]
-.sym 29762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-.sym 29763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
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-.sym 29765 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
-.sym 29767 tx_fifo.rd_addr[2]
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-.sym 29771 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-.sym 29772 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 29773 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
-.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
-.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 29779 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
-.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 29782 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-.sym 29784 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.sym 29785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 29787 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-.sym 29788 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-.sym 29789 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-.sym 29790 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
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-.sym 29793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 29794 tx_fifo.empty_o_SB_LUT4_I1_O[0]
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-.sym 29800 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
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-.sym 29802 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 29803 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
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-.sym 29805 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 29806 w_tx_fifo_pull
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-.sym 29808 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
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-.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 30280 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 30281 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 30282 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 30283 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 30284 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 30285 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 30288 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 30289 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 30291 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 30295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 30296 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 30297 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 30298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 30299 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 30300 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 30301 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.sym 30305 w_tx_fifo_empty
-.sym 30310 tx_fifo.wr_addr_gray_rd[1]
-.sym 30314 tx_fifo.wr_addr[9]
-.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
-.sym 30325 i_rst_b$SB_IO_IN
-.sym 30326 tx_fifo.wr_addr_gray[4]
-.sym 30330 tx_fifo.wr_addr_gray_rd[4]
-.sym 30334 tx_fifo.wr_addr_gray_rd[9]
-.sym 30338 smi_ctrl_ins.r_fifo_pulled_data[13]
-.sym 30339 smi_ctrl_ins.r_fifo_pulled_data[5]
-.sym 30340 smi_ctrl_ins.int_cnt_rx[4]
-.sym 30341 smi_ctrl_ins.int_cnt_rx[3]
-.sym 30346 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.sym 30350 smi_ctrl_ins.r_fifo_pulled_data[15]
-.sym 30351 smi_ctrl_ins.r_fifo_pulled_data[7]
-.sym 30352 smi_ctrl_ins.int_cnt_rx[4]
-.sym 30353 smi_ctrl_ins.int_cnt_rx[3]
-.sym 30354 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
-.sym 30358 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
-.sym 30362 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
-.sym 30366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 30367 tx_fifo.wr_addr[1]
-.sym 30368 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 30369 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 30372 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 30373 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 30374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 30378 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 30379 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 30382 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.sym 30387 w_tx_fifo_full
-.sym 30388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 30389 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 30391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.sym 30392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
-.sym 30393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
-.sym 30396 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 30397 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 30401 tx_fifo.wr_addr[1]
-.sym 30404 smi_ctrl_ins.int_cnt_rx[4]
-.sym 30405 smi_ctrl_ins.int_cnt_rx[3]
-.sym 30412 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
-.sym 30413 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
-.sym 30422 smi_ctrl_ins.r_fifo_pulled_data[28]
-.sym 30423 smi_ctrl_ins.r_fifo_pulled_data[20]
-.sym 30424 smi_ctrl_ins.int_cnt_rx[4]
-.sym 30425 smi_ctrl_ins.int_cnt_rx[3]
-.sym 30430 smi_ctrl_ins.r_fifo_pulled_data[29]
-.sym 30431 smi_ctrl_ins.r_fifo_pulled_data[21]
-.sym 30432 smi_ctrl_ins.int_cnt_rx[4]
-.sym 30433 smi_ctrl_ins.int_cnt_rx[3]
-.sym 30434 w_rx_fifo_pulled_data[30]
-.sym 30438 w_rx_fifo_pulled_data[31]
-.sym 30446 w_rx_fifo_pulled_data[28]
-.sym 30450 w_rx_fifo_pulled_data[29]
-.sym 30466 spi_if_ins.w_rx_data[0]
-.sym 30478 spi_if_ins.w_rx_data[5]
-.sym 30486 spi_if_ins.w_rx_data[2]
-.sym 30493 i_rst_b$SB_IO_IN
-.sym 30502 w_rx_data[7]
-.sym 30509 spi_if_ins.o_ioc_SB_DFFE_Q_E
-.sym 30510 w_rx_data[6]
-.sym 30514 w_rx_data[3]
-.sym 30518 w_rx_data[5]
-.sym 30532 spi_if_ins.w_rx_data[6]
-.sym 30533 spi_if_ins.w_rx_data[5]
-.sym 30534 w_cs[3]
-.sym 30535 w_cs[2]
-.sym 30536 w_cs[1]
-.sym 30537 w_cs[0]
-.sym 30540 spi_if_ins.w_rx_data[6]
-.sym 30541 spi_if_ins.w_rx_data[5]
-.sym 30544 spi_if_ins.w_rx_data[6]
-.sym 30545 spi_if_ins.w_rx_data[5]
-.sym 30549 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 30552 spi_if_ins.w_rx_data[6]
-.sym 30553 spi_if_ins.w_rx_data[5]
-.sym 30562 w_tx_data_smi[2]
-.sym 30563 w_tx_data_io[2]
-.sym 30564 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 30565 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 30566 w_cs[3]
-.sym 30567 w_cs[2]
-.sym 30568 w_cs[1]
-.sym 30569 w_cs[0]
-.sym 30572 i_rst_b$SB_IO_IN
-.sym 30573 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 30574 w_cs[3]
-.sym 30575 w_cs[2]
-.sym 30576 w_cs[1]
-.sym 30577 w_cs[0]
-.sym 30578 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
-.sym 30579 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 30580 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 30581 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
-.sym 30582 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0]
-.sym 30583 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 30584 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 30585 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
-.sym 30587 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
-.sym 30588 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 30589 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
-.sym 30590 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
-.sym 30591 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
-.sym 30592 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.sym 30593 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 30596 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 30597 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 30600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
-.sym 30601 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 30604 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-.sym 30605 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29453 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29454 w_rx_data[0]
+.sym 29459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+.sym 29460 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 29461 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29466 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 29467 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 29468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 29469 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
+.sym 29471 rx_fifo.wr_addr_gray_rd_r[5]
+.sym 29472 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29476 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+.sym 29477 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
+.sym 29478 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+.sym 29479 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 29480 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+.sym 29481 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
+.sym 29482 i_sck$SB_IO_IN
+.sym 29486 rx_fifo.wr_addr_gray_rd[3]
+.sym 29490 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 29494 spi_if_ins.spi.SCKr[0]
+.sym 29499 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 29500 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
+.sym 29501 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 29502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 29506 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 29507 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 29508 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 29509 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 29512 rx_fifo.rd_addr[2]
+.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 29514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 29515 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 29516 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 29517 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 29518 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 29519 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 29521 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 29522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
+.sym 29523 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
+.sym 29524 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
+.sym 29525 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.sym 29527 rx_fifo.rd_addr[2]
+.sym 29528 rx_fifo.rd_addr[1]
+.sym 29529 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 29531 rx_fifo.wr_addr_gray_rd_r[8]
+.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 29535 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+.sym 29539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
+.sym 29540 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
+.sym 29541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
+.sym 29543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 29544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
+.sym 29545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 29546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
+.sym 29562 rx_fifo.wr_addr_gray_rd_r[9]
+.sym 29563 rx_fifo.rd_addr[1]
+.sym 29564 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 29565 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29568 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29569 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29570 rx_fifo.wr_addr_gray_rd[9]
+.sym 29574 rx_fifo.wr_addr_gray_rd[0]
+.sym 29578 rx_fifo.wr_addr_gray_rd[6]
+.sym 29582 rx_fifo.wr_addr[9]
+.sym 29586 w_smi_read_req_SB_LUT4_I1_I3[0]
+.sym 29587 w_smi_read_req
+.sym 29588 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 29589 w_smi_read_req_SB_LUT4_I1_I3[3]
+.sym 29590 rx_fifo.wr_addr_gray[0]
+.sym 29594 rx_fifo.wr_addr_gray_rd[1]
+.sym 29598 w_smi_read_req_SB_LUT4_I1_O[0]
+.sym 29599 w_smi_read_req_SB_LUT4_I1_O[1]
+.sym 29600 w_smi_read_req_SB_LUT4_I1_O[2]
+.sym 29601 w_smi_read_req_SB_LUT4_I1_O[3]
+.sym 29608 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+.sym 29609 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29610 rx_fifo.rd_addr_gray_wr_r[7]
+.sym 29611 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
+.sym 29612 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
+.sym 29613 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
+.sym 29620 rx_fifo.rd_addr_gray_wr_r[4]
+.sym 29621 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 29622 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
+.sym 29626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29634 rx_fifo.rd_addr_gray[7]
+.sym 29638 rx_fifo.rd_addr_gray_wr[8]
+.sym 29642 rx_fifo.rd_addr_gray_wr[4]
+.sym 29646 rx_fifo.rd_addr_gray_wr[7]
+.sym 29650 rx_fifo.rd_addr_gray[8]
+.sym 29654 rx_fifo.rd_addr_gray[4]
+.sym 29658 rx_fifo.rd_addr_gray[3]
+.sym 29662 rx_fifo.rd_addr_gray_wr[3]
+.sym 29666 rx_fifo.wr_addr_gray_rd[7]
+.sym 29678 rx_fifo.wr_addr_gray[7]
+.sym 29731 tx_fifo.rd_addr[0]
+.sym 29736 tx_fifo.rd_addr[1]
+.sym 29737 tx_fifo.rd_addr[0]
+.sym 29740 tx_fifo.rd_addr[2]
+.sym 29741 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
+.sym 29744 tx_fifo.rd_addr[3]
+.sym 29745 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 29748 tx_fifo.rd_addr[4]
+.sym 29749 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 29752 tx_fifo.rd_addr[5]
+.sym 29753 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
+.sym 29756 tx_fifo.rd_addr[6]
+.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 29760 tx_fifo.rd_addr[7]
+.sym 29761 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29764 tx_fifo.rd_addr[8]
+.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29768 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 29769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 29770 w_tx_fifo_pull
+.sym 29771 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 29772 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 29773 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
+.sym 29777 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29782 tx_fifo.rd_addr[4]
+.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 29784 tx_fifo.rd_addr[2]
+.sym 29785 tx_fifo.wr_addr_gray_rd_r[2]
+.sym 29788 smi_ctrl_ins.int_cnt_rx[4]
+.sym 29789 smi_ctrl_ins.int_cnt_rx[3]
+.sym 29791 tx_fifo.rd_addr[4]
+.sym 29792 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
+.sym 29793 tx_fifo.rd_addr[3]
+.sym 29794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
+.sym 29795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
+.sym 29796 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
+.sym 29800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 29801 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 29803 w_tx_fifo_pull
+.sym 29804 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 29805 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29806 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 29807 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 29808 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 29809 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 29812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29813 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29814 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 29815 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 29816 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
+.sym 29817 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
+.sym 29818 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 29819 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 29820 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
+.sym 29821 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
+.sym 29823 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 29824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.sym 29825 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 29828 tx_fifo.rd_addr[5]
+.sym 29829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+.sym 29834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.sym 29842 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29846 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 29847 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 29848 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+.sym 29849 tx_fifo.rd_addr[8]
+.sym 29850 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
+.sym 29856 tx_fifo.rd_addr[8]
+.sym 29857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+.sym 29858 tx_fifo.wr_addr_gray[6]
+.sym 29862 tx_fifo.wr_addr_gray[8]
+.sym 29866 tx_fifo.wr_addr_gray_rd[3]
+.sym 29870 tx_fifo.wr_addr_gray_rd[2]
+.sym 29874 tx_fifo.wr_addr_gray[4]
+.sym 29878 tx_fifo.wr_addr_gray_rd[7]
+.sym 29882 tx_fifo.wr_addr_gray_rd[8]
+.sym 29886 tx_fifo.wr_addr_gray_rd[4]
+.sym 29898 tx_fifo.wr_addr_gray_rd[6]
+.sym 29906 tx_fifo.wr_addr_gray_rd[0]
+.sym 29914 tx_fifo.wr_addr_gray[1]
+.sym 29922 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 29926 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 29934 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 29938 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 29942 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 29946 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 29960 w_smi_read_req_SB_LUT4_I1_I3[2]
+.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 29964 i_ss$SB_IO_IN
+.sym 29965 spi_if_ins.r_tx_data_valid
+.sym 29968 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 29969 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.sym 29972 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
+.sym 29973 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 29974 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 29979 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 29980 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 29981 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+.sym 29986 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 29992 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+.sym 29993 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29995 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 29996 spi_if_ins.state_if[1]
+.sym 29997 spi_if_ins.state_if[0]
+.sym 29998 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 29999 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30001 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 30003 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 30004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 30005 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.sym 30006 i_rst_b$SB_IO_IN
+.sym 30007 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 30008 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 30009 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 30012 i_rst_b$SB_IO_IN
+.sym 30013 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 30014 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 30018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
+.sym 30019 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
+.sym 30020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.sym 30021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
+.sym 30023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30024 spi_if_ins.state_if[1]
+.sym 30025 spi_if_ins.state_if[0]
+.sym 30028 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30029 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 30033 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30036 spi_if_ins.state_if[1]
+.sym 30037 spi_if_ins.state_if[0]
+.sym 30039 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30040 spi_if_ins.state_if[1]
+.sym 30041 spi_if_ins.state_if[0]
+.sym 30043 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 30047 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.sym 30049 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
+.sym 30050 rx_fifo.rd_addr_gray[2]
+.sym 30054 rx_fifo.rd_addr_gray[6]
+.sym 30066 rx_fifo.rd_addr_gray_wr[2]
+.sym 30070 rx_fifo.rd_addr_gray_wr[1]
+.sym 30078 rx_fifo.rd_addr_gray_wr[6]
+.sym 30082 w_rx_data[2]
+.sym 30093 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
+.sym 30098 w_rx_data[0]
+.sym 30108 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+.sym 30109 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.sym 30126 rx_fifo.rd_addr_gray[1]
+.sym 30152 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 30153 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 30167 io_pmod_in[2]$SB_IO_IN
+.sym 30168 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 30169 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 30195 io_pmod_in[3]$SB_IO_IN
+.sym 30196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 30197 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 30217 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+.sym 30244 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 30245 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 30246 tx_fifo.wr_addr[9]
+.sym 30250 tx_fifo.wr_addr_gray_rd[9]
+.sym 30256 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30257 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 30258 tx_fifo.wr_addr_gray[3]
+.sym 30265 i_rst_b$SB_IO_IN
+.sym 30268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 30269 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 30271 i_rst_b$SB_IO_IN
+.sym 30272 smi_ctrl_ins.int_cnt_rx[4]
+.sym 30273 smi_ctrl_ins.int_cnt_rx[3]
+.sym 30275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 30280 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
+.sym 30281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 30284 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
+.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 30294 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30298 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.sym 30303 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 30304 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 30305 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 30306 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 30307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 30308 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 30309 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 30310 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
+.sym 30311 tx_fifo.rd_addr[1]
+.sym 30312 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
+.sym 30313 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30314 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 30319 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.sym 30320 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
+.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
+.sym 30322 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
+.sym 30326 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30330 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 30332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 30334 smi_ctrl_ins.r_fifo_pulled_data[28]
+.sym 30335 smi_ctrl_ins.r_fifo_pulled_data[20]
+.sym 30336 smi_ctrl_ins.int_cnt_rx[4]
+.sym 30337 smi_ctrl_ins.int_cnt_rx[3]
+.sym 30338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30339 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 30340 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 30341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 30342 smi_ctrl_ins.r_fifo_pulled_data[27]
+.sym 30343 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 30344 smi_ctrl_ins.int_cnt_rx[4]
+.sym 30345 smi_ctrl_ins.int_cnt_rx[3]
+.sym 30348 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 30349 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 30351 tx_fifo.rd_addr[6]
+.sym 30352 tx_fifo.rd_addr[5]
+.sym 30353 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 30360 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 30361 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30370 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 30377 tx_fifo.wr_addr[1]
+.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30382 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 30386 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 30400 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 30401 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30402 tx_fifo.wr_addr_gray[0]
+.sym 30410 tx_fifo.wr_addr_gray[5]
+.sym 30422 tx_fifo.wr_addr_gray_rd[5]
+.sym 30426 tx_fifo.wr_addr_gray[7]
+.sym 30430 tx_fifo.wr_addr_gray[2]
+.sym 30445 tx_fifo.rd_addr[1]
+.sym 30467 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 30471 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 30472 $PACKER_VCC_NET
+.sym 30475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 30476 $PACKER_VCC_NET
+.sym 30477 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
+.sym 30479 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 30480 $PACKER_VCC_NET
+.sym 30481 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 30485 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 30487 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 30488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 30489 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 30496 i_ss$SB_IO_IN
+.sym 30497 spi_if_ins.r_tx_data_valid
+.sym 30501 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30505 w_smi_read_req
+.sym 30512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30514 i_rst_b$SB_IO_IN
+.sym 30515 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30516 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 30517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
+.sym 30522 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
+.sym 30527 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+.sym 30528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30531 i_rst_b$SB_IO_IN
+.sym 30532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
+.sym 30533 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
+.sym 30534 spi_if_ins.w_rx_data[2]
+.sym 30538 i_rst_b$SB_IO_IN
+.sym 30539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30540 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+.sym 30541 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 30545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
+.sym 30551 i_rst_b$SB_IO_IN
+.sym 30552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+.sym 30553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+.sym 30554 spi_if_ins.w_rx_data[6]
+.sym 30558 i_rst_b$SB_IO_IN
+.sym 30559 w_cs[2]
+.sym 30560 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30561 w_fetch
+.sym 30562 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30563 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 30564 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 30565 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 30566 w_load
+.sym 30567 w_fetch
+.sym 30568 w_cs[0]
+.sym 30569 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 30570 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
+.sym 30583 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30584 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 30585 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
+.sym 30588 i_rst_b$SB_IO_IN
+.sym 30589 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
+.sym 30591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30592 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 30593 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
+.sym 30595 o_rx_h_tx_l$SB_IO_OUT
+.sym 30596 i_button_SB_LUT4_I0_O[1]
+.sym 30597 i_button_SB_LUT4_I0_O[2]
+.sym 30600 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 30601 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.sym 30602 w_cs[3]
+.sym 30603 w_cs[2]
+.sym 30604 w_cs[1]
+.sym 30605 w_cs[0]
 .sym 30606 w_cs[2]
 .sym 30607 w_load
 .sym 30608 w_fetch
-.sym 30609 o_led1_SB_LUT4_I1_I2[3]
-.sym 30612 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1]
-.sym 30613 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 30616 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
-.sym 30617 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-.sym 30618 w_cs[2]
-.sym 30619 w_ioc[1]
-.sym 30620 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 30621 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 30627 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 30628 o_led0_SB_LUT4_I1_O[1]
-.sym 30629 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
-.sym 30630 w_cs[2]
-.sym 30631 w_load
-.sym 30632 w_fetch
-.sym 30633 o_led1_SB_LUT4_I1_I2[2]
-.sym 30635 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
-.sym 30636 o_led1_SB_LUT4_I1_I2[2]
-.sym 30637 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
-.sym 30639 w_ioc[0]
-.sym 30640 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 30641 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 30642 w_ioc[1]
-.sym 30643 w_ioc[0]
-.sym 30644 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 30645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 30647 w_ioc[1]
-.sym 30648 w_ioc[0]
-.sym 30649 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.sym 30650 w_cs[1]
-.sym 30651 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 30652 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 30653 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 30656 w_ioc[1]
-.sym 30657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.sym 30658 w_ioc[0]
-.sym 30659 io_ctrl_ins.o_pmod[0]
-.sym 30660 io_ctrl_ins.mixer_en_state
-.sym 30661 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 30662 o_tr_vc2$SB_IO_OUT
-.sym 30663 w_ioc[0]
-.sym 30664 io_ctrl_ins.o_pmod[3]
-.sym 30665 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 30670 o_led1_SB_LUT4_I1_O[0]
-.sym 30671 o_led0_SB_LUT4_I1_O[1]
-.sym 30672 o_led1_SB_LUT4_I1_O[2]
-.sym 30673 o_led1_SB_LUT4_I1_O[3]
-.sym 30674 i_config[0]$SB_IO_IN
-.sym 30675 o_led1_SB_LUT4_I1_I2[3]
-.sym 30676 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
-.sym 30677 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
-.sym 30678 io_ctrl_ins.pmod_dir_state[3]
-.sym 30679 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 30680 o_led1_SB_LUT4_I1_I2[2]
-.sym 30681 o_led0_SB_LUT4_I1_O[1]
-.sym 30684 o_led1_SB_LUT4_I1_I2[3]
-.sym 30685 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.sym 30686 o_led0_SB_LUT4_I1_O[0]
-.sym 30687 o_led0_SB_LUT4_I1_O[1]
-.sym 30688 o_led0_SB_LUT4_I1_O[2]
-.sym 30689 o_led0_SB_LUT4_I1_O[3]
-.sym 30691 o_led0_SB_LUT4_I1_O[0]
-.sym 30692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 30693 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 30696 o_led0_SB_LUT4_I1_O[0]
-.sym 30697 o_led1_SB_LUT4_I1_O[0]
-.sym 30698 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 30699 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 30700 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 30701 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 30702 w_rx_data[0]
-.sym 30707 i_rst_b$SB_IO_IN
-.sym 30708 o_led1_SB_LUT4_I1_O[0]
-.sym 30709 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
-.sym 30718 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 30719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
-.sym 30720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 30721 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 30733 r_counter
+.sym 30609 i_button_SB_LUT4_I0_I3[2]
+.sym 30611 i_rst_b$SB_IO_IN
+.sym 30612 w_cs[1]
+.sym 30613 w_fetch
+.sym 30618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30619 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 30620 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 30621 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 30623 w_tx_data_io[5]
+.sym 30624 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 30625 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 30627 w_tx_data_io[7]
+.sym 30628 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 30629 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 30631 o_tr_vc1$SB_IO_OUT
+.sym 30632 i_button_SB_LUT4_I0_O[1]
+.sym 30633 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
+.sym 30634 i_button_SB_LUT4_I0_I3[0]
+.sym 30635 i_button_SB_LUT4_I0_I3[1]
+.sym 30636 i_button_SB_LUT4_I0_I3[2]
+.sym 30637 i_button_SB_LUT4_I0_I3[3]
+.sym 30643 w_fetch
+.sym 30644 w_cs[0]
+.sym 30645 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
+.sym 30646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 30647 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 30648 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 30649 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 30650 w_tx_data_io[2]
+.sym 30651 w_tx_data_smi[2]
+.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 30655 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 30656 i_button_SB_LUT4_I0_O[1]
+.sym 30657 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
+.sym 30658 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
+.sym 30659 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 30660 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 30661 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
+.sym 30679 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
+.sym 30680 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 30681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
+.sym 30687 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
+.sym 30688 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 30689 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.sym 30690 r_tx_data[2]
+.sym 30705 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 30706 r_tx_data[0]
+.sym 30718 r_tx_data[7]
+.sym 30728 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
+.sym 30729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 30732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 30733 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 30736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
+.sym 30737 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 30740 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
+.sym 30741 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 30744 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
+.sym 30745 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 30748 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
+.sym 30749 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
 .sym 30755 tx_fifo.wr_addr[0]
 .sym 30760 tx_fifo.wr_addr[1]
 .sym 30761 tx_fifo.wr_addr[0]
 .sym 30764 tx_fifo.wr_addr[2]
-.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
 .sym 30768 tx_fifo.wr_addr[3]
-.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
 .sym 30772 tx_fifo.wr_addr[4]
 .sym 30773 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
 .sym 30776 tx_fifo.wr_addr[5]
-.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
 .sym 30780 tx_fifo.wr_addr[6]
-.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
 .sym 30784 tx_fifo.wr_addr[7]
-.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
+.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
 .sym 30788 tx_fifo.wr_addr[8]
-.sym 30789 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 30789 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
 .sym 30792 tx_fifo.wr_addr[9]
-.sym 30793 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
-.sym 30796 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 30798 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
-.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.sym 30808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
-.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 30810 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
+.sym 30793 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
+.sym 30794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30798 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30806 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.sym 30810 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 30818 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 30820 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 30821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
 .sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
 .sym 30823 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
 .sym 30824 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
 .sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 30832 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 30833 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.sym 30838 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 30839 tx_fifo.rd_addr_gray_wr_r[0]
-.sym 30840 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 30841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
-.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
-.sym 30846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 30847 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 30849 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
-.sym 30850 tx_fifo.rd_addr_gray_wr[6]
-.sym 30854 tx_fifo.rd_addr_gray_wr[7]
-.sym 30860 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 30862 tx_fifo.rd_addr_gray[5]
-.sym 30866 tx_fifo.rd_addr_gray[7]
-.sym 30870 tx_fifo.rd_addr_gray[3]
-.sym 30874 tx_fifo.rd_addr_gray[6]
-.sym 30878 tx_fifo.rd_addr_gray_wr[3]
-.sym 30883 tx_fifo.wr_addr[2]
-.sym 30884 tx_fifo.rd_addr_gray_wr_r[1]
-.sym 30885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 30826 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
+.sym 30828 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.sym 30829 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
+.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30832 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 30833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.sym 30836 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.sym 30840 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
+.sym 30841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
+.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
+.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 30850 tx_fifo.rd_addr_gray_wr[7]
+.sym 30854 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+.sym 30858 tx_fifo.rd_addr_gray_wr[2]
+.sym 30862 tx_fifo.rd_addr_gray[7]
+.sym 30866 tx_fifo.rd_addr_gray[4]
+.sym 30870 tx_fifo.rd_addr_gray[1]
+.sym 30874 tx_fifo.rd_addr_gray_wr[4]
+.sym 30878 tx_fifo.rd_addr_gray_wr[1]
+.sym 30882 i_ss$SB_IO_IN
+.sym 30883 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 30884 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 30885 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 30890 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
 .sym 30895 w_tx_fifo_full
-.sym 30896 w_rx_fifo_empty
-.sym 30897 w_smi_data_direction
-.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
-.sym 30899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
-.sym 30901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
-.sym 30902 tx_fifo.rd_addr_gray_wr[5]
-.sym 30912 i_rst_b$SB_IO_IN
-.sym 30913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
-.sym 30914 smi_ctrl_ins.r_fifo_pull
-.sym 30919 w_rx_fifo_empty
-.sym 30920 smi_ctrl_ins.r_fifo_pull_1
-.sym 30921 smi_ctrl_ins.r_fifo_pull
-.sym 30922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.sym 30923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
-.sym 30924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.sym 30925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
-.sym 30927 w_tx_fifo_full
-.sym 30928 smi_ctrl_ins.r_fifo_push
-.sym 30929 smi_ctrl_ins.r_fifo_push_1
-.sym 30930 smi_ctrl_ins.w_fifo_pull_trigger
-.sym 30938 smi_ctrl_ins.r_fifo_push
-.sym 30942 smi_ctrl_ins.w_fifo_push_trigger
-.sym 30946 spi_if_ins.spi.r_rx_byte[1]
-.sym 30954 spi_if_ins.spi.r_rx_byte[2]
-.sym 30958 spi_if_ins.spi.r_rx_byte[4]
-.sym 30966 spi_if_ins.spi.r_rx_byte[5]
-.sym 30970 spi_if_ins.spi.r_rx_byte[6]
-.sym 30974 spi_if_ins.spi.r_rx_byte[0]
-.sym 30979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 30980 spi_if_ins.state_if[1]
-.sym 30981 spi_if_ins.state_if[0]
-.sym 30982 spi_if_ins.spi.r_rx_byte[3]
-.sym 30986 spi_if_ins.spi.r_rx_byte[7]
-.sym 30995 i_rst_b$SB_IO_IN
-.sym 30996 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 30997 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
-.sym 30999 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 31000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 31001 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 31003 i_rst_b$SB_IO_IN
-.sym 31004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 31005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.sym 31007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 31008 spi_if_ins.state_if[1]
-.sym 31009 spi_if_ins.state_if[0]
-.sym 31011 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 31012 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 31013 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 31014 spi_if_ins.w_rx_data[4]
-.sym 31018 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-.sym 31024 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 31025 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 31026 i_rst_b$SB_IO_IN
-.sym 31027 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 31028 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-.sym 31029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 31030 spi_if_ins.w_rx_data[3]
-.sym 31034 spi_if_ins.w_rx_data[1]
-.sym 31038 spi_if_ins.w_rx_data[6]
-.sym 31043 w_ioc[4]
-.sym 31044 w_ioc[3]
-.sym 31045 w_ioc[2]
-.sym 31046 spi_if_ins.w_rx_data[1]
-.sym 31050 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
-.sym 31054 spi_if_ins.w_rx_data[4]
-.sym 31058 spi_if_ins.w_rx_data[3]
-.sym 31062 spi_if_ins.w_rx_data[0]
-.sym 31066 spi_if_ins.w_rx_data[2]
-.sym 31071 w_ioc[4]
-.sym 31072 w_ioc[3]
-.sym 31073 w_ioc[2]
-.sym 31078 r_tx_data[2]
-.sym 31082 r_tx_data[1]
-.sym 31086 w_cs[3]
-.sym 31087 w_cs[2]
-.sym 31088 w_cs[1]
-.sym 31089 w_cs[0]
-.sym 31090 r_tx_data[0]
-.sym 31094 r_tx_data[7]
-.sym 31098 w_cs[3]
-.sym 31099 w_cs[2]
-.sym 31100 w_cs[1]
-.sym 31101 w_cs[0]
+.sym 30896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 30897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 30899 tx_fifo.wr_addr[1]
+.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 30901 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 30903 tx_fifo.full_o_SB_LUT4_I1_O[0]
+.sym 30904 tx_fifo.full_o_SB_LUT4_I1_O[1]
+.sym 30905 tx_fifo.full_o_SB_LUT4_I1_O[2]
+.sym 30907 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 30908 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 30909 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 30913 smi_ctrl_ins.r_fifo_pulled_data[19]
+.sym 30914 spi_if_ins.spi.r2_rx_done
+.sym 30924 spi_if_ins.spi.r3_rx_done
+.sym 30925 spi_if_ins.spi.r2_rx_done
+.sym 30932 i_ss$SB_IO_IN
+.sym 30933 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 30934 tx_fifo.rd_addr_gray_wr[9]
+.sym 30938 tx_fifo.rd_addr_gray_wr[0]
+.sym 30942 spi_if_ins.spi.r_rx_done
+.sym 30954 tx_fifo.rd_addr_gray[0]
+.sym 30961 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 30978 w_tx_fifo_full
+.sym 30985 w_smi_read_req
+.sym 30986 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
+.sym 30991 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 30992 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
+.sym 30993 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
+.sym 30994 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.sym 30995 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
+.sym 30996 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
+.sym 30997 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
+.sym 30999 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
+.sym 31001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
+.sym 31007 spi_if_ins.spi.r_tx_byte[3]
+.sym 31008 spi_if_ins.spi.r_tx_byte[2]
+.sym 31009 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 31010 spi_if_ins.spi.r_tx_byte[6]
+.sym 31011 spi_if_ins.spi.r_tx_byte[4]
+.sym 31012 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 31013 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 31014 spi_if_ins.r_tx_byte[4]
+.sym 31018 spi_if_ins.r_tx_byte[2]
+.sym 31022 spi_if_ins.r_tx_byte[3]
+.sym 31026 spi_if_ins.r_tx_byte[6]
+.sym 31031 spi_if_ins.spi.r_tx_byte[1]
+.sym 31032 spi_if_ins.spi.r_tx_byte[0]
+.sym 31033 spi_if_ins.spi.r_tx_bit_count[0]
+.sym 31034 spi_if_ins.r_tx_byte[1]
+.sym 31038 spi_if_ins.r_tx_byte[0]
+.sym 31042 spi_if_ins.w_rx_data[2]
+.sym 31047 w_ioc[4]
+.sym 31048 w_ioc[3]
+.sym 31049 w_ioc[2]
+.sym 31056 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 31057 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 31058 spi_if_ins.w_rx_data[4]
+.sym 31064 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 31065 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
+.sym 31066 spi_if_ins.w_rx_data[0]
+.sym 31070 spi_if_ins.w_rx_data[3]
+.sym 31074 w_cs[3]
+.sym 31075 w_cs[2]
+.sym 31076 w_cs[1]
+.sym 31077 w_cs[0]
+.sym 31078 r_tx_data[5]
+.sym 31082 r_tx_data[4]
+.sym 31086 r_tx_data[3]
+.sym 31090 r_tx_data[1]
+.sym 31099 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 31100 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 31101 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
 .sym 31102 r_tx_data[6]
-.sym 31106 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
-.sym 31107 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 31107 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
 .sym 31108 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 31109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 31111 w_tx_data_io[7]
-.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 31113 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 31114 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-.sym 31115 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
-.sym 31116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 31117 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 31120 i_rst_b$SB_IO_IN
-.sym 31121 w_fetch
-.sym 31123 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0]
-.sym 31124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 31125 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
-.sym 31127 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
-.sym 31128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-.sym 31129 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.sym 31109 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
+.sym 31111 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
+.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 31113 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
+.sym 31115 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 31116 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 31117 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 31118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+.sym 31119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
+.sym 31120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 31121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 31122 i_button$SB_IO_IN
+.sym 31123 io_ctrl_ins.pmod_dir_state[7]
+.sym 31124 i_button_SB_LUT4_I0_I3[2]
+.sym 31125 i_button_SB_LUT4_I0_I3[3]
+.sym 31126 w_cs[3]
+.sym 31127 w_cs[2]
+.sym 31128 w_cs[1]
+.sym 31129 w_cs[0]
 .sym 31130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
 .sym 31131 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
 .sym 31132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
 .sym 31133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 31135 w_tx_data_io[5]
-.sym 31136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-.sym 31137 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
-.sym 31138 w_rx_data[5]
-.sym 31143 w_ioc[1]
-.sym 31144 w_ioc[0]
-.sym 31145 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 31146 w_rx_data[6]
-.sym 31151 w_ioc[1]
-.sym 31152 w_ioc[0]
-.sym 31153 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-.sym 31154 w_cs[1]
-.sym 31155 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 31156 o_led1_SB_LUT4_I1_I2[3]
-.sym 31157 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 31162 w_rx_data[3]
-.sym 31166 w_rx_data[2]
-.sym 31172 w_ioc[0]
-.sym 31173 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-.sym 31174 o_rx_h_tx_l$SB_IO_OUT
-.sym 31175 io_ctrl_ins.pmod_dir_state[7]
-.sym 31176 o_led1_SB_LUT4_I1_I2[2]
-.sym 31177 i_config_SB_LUT4_I0_1_O[1]
-.sym 31179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 31180 o_led1_SB_LUT4_I1_I2[3]
-.sym 31181 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 31183 i_button$SB_IO_IN
-.sym 31184 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 31185 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
-.sym 31186 o_tr_vc1$SB_IO_OUT
-.sym 31187 io_ctrl_ins.pmod_dir_state[5]
-.sym 31188 o_led1_SB_LUT4_I1_I2[2]
-.sym 31189 i_config_SB_LUT4_I0_1_O[1]
-.sym 31191 i_config[2]$SB_IO_IN
-.sym 31192 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 31193 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
-.sym 31194 i_config[3]$SB_IO_IN
-.sym 31195 io_ctrl_ins.pmod_dir_state[6]
-.sym 31196 o_led1_SB_LUT4_I1_I2[2]
-.sym 31197 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-.sym 31199 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 31200 i_config_SB_LUT4_I0_1_O[1]
-.sym 31201 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
-.sym 31202 io_ctrl_ins.rf_pin_state[3]
-.sym 31203 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 31204 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 31205 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
-.sym 31207 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 31209 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31210 io_ctrl_ins.rf_pin_state[2]
-.sym 31211 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
-.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 31213 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31215 io_ctrl_ins.rf_pin_state[4]
-.sym 31216 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31217 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 31219 io_ctrl_ins.rf_pin_state[7]
-.sym 31220 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31221 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 31223 io_ctrl_ins.rf_pin_state[1]
-.sym 31224 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
-.sym 31225 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31227 io_ctrl_ins.rf_pin_state[5]
-.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31229 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 31231 io_ctrl_ins.rf_pin_state[6]
-.sym 31232 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 31234 w_rx_data[4]
-.sym 31238 w_rx_data[7]
+.sym 31134 w_cs[3]
+.sym 31135 w_cs[2]
+.sym 31136 w_cs[1]
+.sym 31137 w_cs[0]
+.sym 31139 w_tx_data_io[0]
+.sym 31140 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
+.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 31142 o_led0_SB_LUT4_I1_O[0]
+.sym 31143 o_led0_SB_LUT4_I1_O[1]
+.sym 31144 o_led0_SB_LUT4_I1_O[2]
+.sym 31145 o_led0_SB_LUT4_I1_O[3]
+.sym 31146 io_pmod_out[1]$SB_IO_OUT
+.sym 31147 o_shdn_rx_lna$SB_IO_OUT
+.sym 31148 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 31149 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 31150 w_tx_data_smi[1]
+.sym 31151 w_tx_data_io[1]
+.sym 31152 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 31153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 31154 io_pmod_out[0]$SB_IO_OUT
+.sym 31155 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 31156 io_ctrl_ins.mixer_en_state
+.sym 31157 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 31158 o_led1_SB_LUT4_I1_O[0]
+.sym 31159 o_led0_SB_LUT4_I1_O[1]
+.sym 31160 o_led1_SB_LUT4_I1_O[2]
+.sym 31161 o_led1_SB_LUT4_I1_O[3]
+.sym 31163 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
+.sym 31164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
+.sym 31165 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
+.sym 31167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 31168 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 31169 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.sym 31170 io_ctrl_ins.rf_pin_state[3]
+.sym 31171 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 31173 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31174 io_ctrl_ins.rf_pin_state[2]
+.sym 31175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 31177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31179 io_ctrl_ins.rf_pin_state[7]
+.sym 31180 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31181 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 31182 io_ctrl_ins.rf_pin_state[4]
+.sym 31183 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31184 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 31185 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31187 io_ctrl_ins.rf_pin_state[6]
+.sym 31188 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31189 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 31191 io_ctrl_ins.rf_pin_state[1]
+.sym 31192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31193 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31194 io_ctrl_ins.rf_pin_state[0]
+.sym 31195 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 31197 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31198 io_ctrl_ins.rf_pin_state[5]
+.sym 31199 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31200 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.sym 31201 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31202 w_rx_data[4]
+.sym 31206 w_rx_data[2]
+.sym 31210 i_rst_b$SB_IO_IN
+.sym 31211 o_led0_SB_LUT4_I1_O[0]
+.sym 31212 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 31217 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.sym 31218 w_rx_data[1]
+.sym 31222 w_rx_data[0]
+.sym 31228 o_led1_SB_LUT4_I1_O[0]
+.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.sym 31230 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 31231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 31232 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
+.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+.sym 31234 w_rx_data[5]
+.sym 31238 w_rx_data[2]
 .sym 31242 w_rx_data[0]
-.sym 31246 w_rx_data[5]
 .sym 31250 w_rx_data[1]
-.sym 31254 w_rx_data[6]
-.sym 31258 w_rx_data[3]
-.sym 31262 w_rx_data[2]
-.sym 31267 tx_fifo.wr_addr[1]
-.sym 31272 tx_fifo.wr_addr[2]
-.sym 31273 tx_fifo.wr_addr[1]
-.sym 31276 tx_fifo.wr_addr[3]
-.sym 31277 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
-.sym 31280 tx_fifo.wr_addr[4]
-.sym 31281 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
-.sym 31284 tx_fifo.wr_addr[5]
-.sym 31285 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
-.sym 31288 tx_fifo.wr_addr[6]
-.sym 31289 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO
-.sym 31292 tx_fifo.wr_addr[7]
-.sym 31293 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 31296 tx_fifo.wr_addr[8]
-.sym 31297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
-.sym 31300 tx_fifo.wr_addr[9]
-.sym 31301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3
-.sym 31302 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
-.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
-.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
-.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.sym 31329 tx_fifo.wr_addr[0]
-.sym 31331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
-.sym 31332 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 31334 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
-.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
-.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
-.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
-.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
-.sym 31346 tx_fifo.rd_addr_gray_wr[4]
-.sym 31352 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 31353 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 31354 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-.sym 31355 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-.sym 31356 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
-.sym 31358 tx_fifo.rd_addr_gray_wr[2]
-.sym 31363 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 31368 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 31369 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 31372 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 31373 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
-.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 31383 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
-.sym 31389 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 31390 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-.sym 31391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.sym 31402 w_rx_fifo_pulled_data[7]
-.sym 31407 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 31408 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31258 w_rx_data[4]
+.sym 31262 w_rx_data[6]
+.sym 31273 tx_fifo.wr_addr[0]
+.sym 31274 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
+.sym 31278 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+.sym 31294 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 31299 tx_fifo.wr_addr[1]
+.sym 31304 tx_fifo.wr_addr[2]
+.sym 31305 tx_fifo.wr_addr[1]
+.sym 31308 tx_fifo.wr_addr[3]
+.sym 31309 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 31312 tx_fifo.wr_addr[4]
+.sym 31313 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 31316 tx_fifo.wr_addr[5]
+.sym 31317 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 31320 tx_fifo.wr_addr[6]
+.sym 31321 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 31324 tx_fifo.wr_addr[7]
+.sym 31325 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
+.sym 31328 tx_fifo.wr_addr[8]
+.sym 31329 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
+.sym 31332 tx_fifo.wr_addr[9]
+.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
+.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
+.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
+.sym 31347 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.sym 31348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 31351 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.sym 31354 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.sym 31360 i_rst_b$SB_IO_IN
+.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 31362 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 31363 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+.sym 31364 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.sym 31365 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 31366 smi_ctrl_ins.r_fifo_push
+.sym 31370 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.sym 31371 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
+.sym 31372 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
+.sym 31373 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.sym 31375 tx_fifo.wr_addr[2]
+.sym 31376 tx_fifo.rd_addr_gray_wr_r[1]
+.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
+.sym 31379 w_tx_fifo_full
+.sym 31380 smi_ctrl_ins.r_fifo_push
+.sym 31381 smi_ctrl_ins.r_fifo_push_1
+.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+.sym 31383 tx_fifo.rd_addr_gray_wr_r[8]
+.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.sym 31386 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
+.sym 31387 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
+.sym 31388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
+.sym 31389 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
+.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
+.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
+.sym 31395 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31400 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31401 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31404 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 31405 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
 .sym 31409 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 31414 i_ss$SB_IO_IN
-.sym 31415 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 31416 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 31417 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 31418 w_rx_fifo_pulled_data[5]
-.sym 31432 i_ss$SB_IO_IN
-.sym 31433 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
-.sym 31438 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 31458 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 31462 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 31466 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 31470 i_mosi$SB_IO_IN
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-.sym 31504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
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-.sym 31514 i_rst_b$SB_IO_IN
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-.sym 31517 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 31518 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
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-.sym 31527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31528 $PACKER_VCC_NET
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-.sym 31532 $PACKER_VCC_NET
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-.sym 31534 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-.sym 31535 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
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-.sym 31541 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
-.sym 31544 i_rst_b$SB_IO_IN
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-.sym 31547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31548 $PACKER_VCC_NET
-.sym 31549 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 31553 spi_if_ins.spi.r_tx_bit_count[0]
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-.sym 31555 spi_if_ins.spi.r_tx_byte[5]
-.sym 31556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31557 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 31558 spi_if_ins.r_tx_byte[7]
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-.sym 31564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31565 spi_if_ins.spi.r_tx_bit_count[0]
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-.sym 31570 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 31571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
-.sym 31572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
-.sym 31573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
-.sym 31575 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
-.sym 31576 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
-.sym 31577 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
-.sym 31579 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
-.sym 31580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31581 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 31583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-.sym 31584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
-.sym 31585 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
-.sym 31587 spi_if_ins.spi.r_tx_byte[1]
-.sym 31588 spi_if_ins.spi.r_tx_byte[0]
-.sym 31589 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 31590 spi_if_ins.r_tx_byte[6]
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-.sym 31604 spi_if_ins.spi.r_tx_byte[2]
-.sym 31605 spi_if_ins.spi.r_tx_bit_count[0]
-.sym 31606 spi_if_ins.r_tx_byte[1]
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-.sym 31660 w_fetch
-.sym 31661 o_led1_SB_LUT4_I1_I2[3]
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-.sym 31673 o_led1_SB_LUT4_I1_I2[2]
-.sym 31682 w_rx_data[4]
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-.sym 31693 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 31694 i_config[1]$SB_IO_IN
+.sym 31423 w_tx_fifo_full
+.sym 31424 w_smi_read_req
+.sym 31425 w_smi_data_direction
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+.sym 31454 w_rx_fifo_pulled_data[31]
+.sym 31458 i_mosi$SB_IO_IN
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+.sym 31470 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 31474 spi_if_ins.spi.r_temp_rx_byte[4]
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+.sym 31498 spi_if_ins.spi.r_rx_byte[0]
+.sym 31502 spi_if_ins.spi.r_rx_byte[4]
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+.sym 31510 spi_if_ins.spi.r_rx_byte[7]
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+.sym 31518 spi_if_ins.spi.r_rx_byte[3]
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+.sym 31537 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 31538 spi_if_ins.r_tx_byte[5]
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+.sym 31543 spi_if_ins.spi.r_tx_byte[5]
+.sym 31544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+.sym 31545 spi_if_ins.spi.r_tx_bit_count[0]
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+.sym 31559 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
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+.sym 31617 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+.sym 31618 io_ctrl_ins.pmod_dir_state[1]
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+.sym 31622 w_rx_data[0]
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+.sym 31653 i_button_SB_LUT4_I0_I3[2]
+.sym 31654 i_config[2]$SB_IO_IN
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+.sym 31674 i_rst_b$SB_IO_IN
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+.sym 31682 w_rx_data[3]
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+.sym 31693 o_led0_SB_LUT4_I1_O[1]
+.sym 31694 o_tr_vc1_b$SB_IO_OUT
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-.sym 31697 o_led1_SB_LUT4_I1_I2[3]
-.sym 31698 io_ctrl_ins.pmod_dir_state[1]
-.sym 31699 o_led1$SB_IO_OUT
-.sym 31700 o_led1_SB_LUT4_I1_I2[2]
-.sym 31701 o_led1_SB_LUT4_I1_I2[3]
-.sym 31706 io_ctrl_ins.pmod_dir_state[0]
-.sym 31707 o_led0$SB_IO_OUT
-.sym 31708 o_led1_SB_LUT4_I1_I2[2]
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-.sym 31710 w_rx_data[1]
-.sym 31718 o_tr_vc1_b$SB_IO_OUT
-.sym 31719 i_config_SB_LUT4_I0_1_O[1]
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-.sym 31875 i_rst_b$SB_IO_IN
-.sym 31876 smi_ctrl_ins.tx_reg_state[3]
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-.sym 31878 i_rst_b$SB_IO_IN
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-.sym 31883 i_rst_b$SB_IO_IN
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-.sym 31887 i_rst_b$SB_IO_IN
-.sym 31888 w_smi_data_input[7]
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-.sym 31891 i_rst_b$SB_IO_IN
-.sym 31892 w_smi_data_input[7]
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-.sym 31903 w_smi_data_input[7]
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-.sym 31913 w_smi_data_input[7]
-.sym 31932 i_smi_swe_srw$rename$0
-.sym 31933 i_rst_b$SB_IO_IN
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-.sym 32016 i_ss$SB_IO_IN
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-.sym 32058 i_rst_b$SB_IO_IN
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-.sym 32166 w_rx_data[1]
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-.sym 32453 i_smi_swe_srw$rename$0
-.sym 32457 smi_ctrl_ins.swe_and_reset
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+.sym 31716 o_led1_SB_LUT4_I1_O[0]
+.sym 31717 o_led0_SB_LUT4_I1_O[0]
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+.sym 31747 i_config[1]$SB_IO_IN
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+.sym 31816 w_smi_data_input[7]
+.sym 31817 smi_ctrl_ins.tx_reg_state[2]
+.sym 31819 i_rst_b$SB_IO_IN
+.sym 31820 w_smi_data_input[7]
+.sym 31821 smi_ctrl_ins.tx_reg_state[0]
+.sym 31822 i_rst_b$SB_IO_IN
+.sym 31823 w_smi_data_input[7]
+.sym 31824 smi_ctrl_ins.tx_reg_state[3]
+.sym 31825 smi_ctrl_ins.tx_reg_state[0]
+.sym 31827 i_rst_b$SB_IO_IN
+.sym 31828 w_smi_data_input[7]
+.sym 31829 smi_ctrl_ins.tx_reg_state[1]
+.sym 31832 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
+.sym 31833 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
+.sym 31835 i_rst_b$SB_IO_IN
+.sym 31836 smi_ctrl_ins.tx_reg_state[3]
+.sym 31837 smi_ctrl_ins.tx_reg_state[0]
+.sym 31850 smi_ctrl_ins.w_fifo_push_trigger
+.sym 31882 tx_fifo.rd_addr_gray[8]
+.sym 31902 tx_fifo.rd_addr_gray_wr[8]
+.sym 31909 i_ss$SB_IO_IN
+.sym 31970 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 31974 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 31978 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 31982 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 31990 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 31994 i_mosi$SB_IO_IN
+.sym 31998 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 32020 i_smi_soe_se$SB_IO_IN
+.sym 32021 i_rst_b$SB_IO_IN
+.sym 32027 spi_if_ins.r_tx_byte[7]
+.sym 32028 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 32029 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 32054 w_rx_data[0]
+.sym 32070 w_cs[2]
+.sym 32071 w_load
+.sym 32072 w_fetch
+.sym 32073 o_led1_SB_LUT4_I1_I3[3]
+.sym 32090 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 32098 w_cs[1]
+.sym 32099 w_load
+.sym 32100 w_fetch
+.sym 32101 o_led1_SB_LUT4_I1_I3[3]
+.sym 32118 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+.sym 32119 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 32120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+.sym 32121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+.sym 32134 w_rx_data[7]
+.sym 32138 io_pmod_out[2]$SB_IO_OUT
+.sym 32139 o_shdn_tx_lna$SB_IO_OUT
+.sym 32140 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 32141 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 32143 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+.sym 32144 i_button_SB_LUT4_I0_I3[2]
+.sym 32145 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
+.sym 32154 w_rx_data[3]
+.sym 32159 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 32160 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.sym 32161 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.sym 32183 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+.sym 32184 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+.sym 32185 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.sym 32191 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.sym 32192 o_led0_SB_LUT4_I1_O[1]
+.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.sym 32196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
+.sym 32197 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 32200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
+.sym 32201 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+.sym 32210 o_led1_SB_LUT4_I1_I3[0]
+.sym 32211 o_led0$SB_IO_OUT
+.sym 32212 i_button_SB_LUT4_I0_I3[2]
+.sym 32213 o_led1_SB_LUT4_I1_I3[3]
+.sym 32214 i_config[0]$SB_IO_IN
+.sym 32215 o_tr_vc2$SB_IO_OUT
+.sym 32216 o_led1_SB_LUT4_I1_I3[3]
+.sym 32217 i_button_SB_LUT4_I0_O[1]
+.sym 32251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
+.sym 32252 o_led0_SB_LUT4_I1_O[1]
+.sym 32253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
+.sym 32353 w_smi_data_input[7]
+.sym 32553 r_counter
+.sym 32602 spi_if_ins.w_rx_data[1]
+.sym 32622 w_rx_data[0]
+.sym 32630 w_rx_data[1]
+.sym 32642 w_rx_data[1]
+.sym 32654 w_rx_data[3]
+.sym 32662 w_rx_data[2]
+.sym 32666 w_rx_data[0]
+.sym 32700 w_rx_fifo_full
+.sym 32701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+.sym 32707 w_rx_fifo_full
+.sym 32708 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+.sym 32709 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
diff --git a/firmware/top.bin b/firmware/top.bin
index 605814c..48191cd 100644
Binary files a/firmware/top.bin and b/firmware/top.bin differ
diff --git a/firmware/top.blif b/firmware/top.blif
index bf08b39..361df8a 100644
--- a/firmware/top.blif
+++ b/firmware/top.blif
@@ -1,32 +1,32 @@
 # Generated by Yosys 0.39+0 (git sha1 18cec2d9a, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
 
 .model top
-.inputs i_glob_clock i_rst_b i_iq_rx_09_p i_iq_rx_24_n i_iq_rx_clk_p i_config[0] i_config[1] i_config[2] i_config[3] i_button io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] i_smi_a2 i_smi_a3 i_smi_soe_se i_smi_swe_srw io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] i_mosi i_sck i_ss
-.outputs o_rx_h_tx_l o_rx_h_tx_l_b o_tr_vc1 o_tr_vc1_b o_tr_vc2 o_shdn_rx_lna o_shdn_tx_lna o_iq_tx_p o_iq_tx_n o_iq_tx_clk_p o_iq_tx_clk_n o_mixer_fm o_mixer_en io_pmod[0] io_pmod[1] io_pmod[2] io_pmod[3] io_pmod[4] io_pmod[5] io_pmod[6] io_pmod[7] o_led0 o_led1 io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] o_smi_write_req o_smi_read_req o_miso
+.inputs i_glob_clock i_rst_b i_iq_rx_09_p i_iq_rx_24_n i_iq_rx_clk_p i_config[0] i_config[1] i_config[2] i_config[3] i_button io_pmod_in[0] io_pmod_in[1] io_pmod_in[2] io_pmod_in[3] i_smi_a2 i_smi_a3 i_smi_soe_se i_smi_swe_srw io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] i_mosi i_sck i_ss
+.outputs o_rx_h_tx_l o_rx_h_tx_l_b o_tr_vc1 o_tr_vc1_b o_tr_vc2 o_shdn_rx_lna o_shdn_tx_lna o_iq_tx_p o_iq_tx_n o_iq_tx_clk_p o_iq_tx_clk_n o_mixer_fm o_mixer_en io_pmod_out[0] io_pmod_out[1] io_pmod_out[2] io_pmod_out[3] o_led0 o_led1 io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] o_smi_write_req o_smi_read_req o_miso
 .names $false
 .names $true
 1
 .names $undef
-.gate SB_LUT4 I0=$false I1=i_button I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000011111111
-.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
+.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=i_button_SB_LUT4_I0_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0001010100111111
-.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=i_config_SB_LUT4_I0_1_O[2]
+.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=i_button_SB_LUT4_I0_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0010011010101111
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100000000
+.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0001010100111111
-.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=i_config_SB_LUT4_I0_1_O[1]
+.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=i_config_SB_LUT4_I0_1_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000110000000000
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0001010100111111
 .gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
@@ -49,108 +49,76 @@
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000111111001100
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1111001110101010
-.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
+.param LUT_INIT 1100111110101010
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1011100000000000
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
+.param LUT_INIT 1100101000000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000000111111
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000000000001111
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011000000000000
-.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000000001100
-.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000001000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100111111111111
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0011110010101010
-.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_ctrl_ins.pmod_state[0] I2=io_ctrl_ins.mixer_en_state I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led0_SB_LUT4_I1_O[2]
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[0] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.mixer_en_state I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led0_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1110010000000000
-.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.param LUT_INIT 1110001000000000
+.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=i_config[0] I1=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1111100011111111
-.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=o_led0_SB_LUT4_I1_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000110011111111
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
+.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=o_led0_SB_LUT4_I1_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000110011111111
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111001100000000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000000111111
-.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D
+.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=o_led0_SB_LUT4_I1_O[1] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1111001011111111
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111100000000
-.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011111100000000
+.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
-.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D
+.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=o_led0_SB_LUT4_I1_O[1] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1111001011111111
@@ -163,25 +131,29 @@
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[5]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=i_config[2] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D
+.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=$false I1=i_config[1] I2=o_led1_SB_LUT4_I1_I3[3] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000011111111
-.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4]
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000000010001000
-.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000100010000000
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011111100000000
+.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100110011000000
+.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
 .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
@@ -218,7 +190,7 @@
 .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0011000000000000
@@ -226,7 +198,7 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
+.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
@@ -261,204 +233,190 @@
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000011111100
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=i_config_SB_LUT4_I0_1_O[1] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=o_led1_SB_LUT4_I1_I2[3] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000011111111
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111111100001100
-.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001100000000000
-.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2]
+.param LUT_INIT 0100001000000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=o_led1_SB_LUT4_I1_I2[3] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001010100111111
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000011111111
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[4] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000011111100
-.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=i_config_SB_LUT4_I0_1_O[1] I2=i_config_SB_LUT4_I0_1_O[2] I3=i_config_SB_LUT4_I0_1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D
+.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1111111110001111
-.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[5] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111111100001100
-.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000111000000000
-.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2]
+.param LUT_INIT 1111110010101010
+.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0001010100111111
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000000000001111
+.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1000101010101010
+.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111100000000
+.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led0_SB_LUT4_I1_O[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000000001000
+.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000010010101111
+.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000001110101010
+.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000000000001111
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=o_led1_SB_LUT4_I1_I2[3] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000011111111
 .gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D
+.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0011110010101010
-.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
+.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.tr_vc_2_state I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1011100000000000
-.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
+.param LUT_INIT 0001001101011111
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=o_led1_SB_LUT4_I1_I2[2] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0101111100010011
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=io_pmod[0]
+.param LUT_INIT 0000011100000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_state[3] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000110000000000
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:293.7-298.4"
+.attr src "top.v:289.7-294.4"
 .param IO_STANDARD "SB_LVDS_INPUT"
 .param NEG_TRIGGER 0
 .param PIN_TYPE 000000
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_24_n
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:278.7-284.4"
+.attr src "top.v:274.7-280.4"
 .param IO_STANDARD "SB_LVDS_INPUT"
 .param NEG_TRIGGER 0
 .param PIN_TYPE 000000
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=lvds_clock PACKAGE_PIN=i_iq_rx_clk_p
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:260.7-263.4"
+.attr src "top.v:256.7-259.4"
 .param IO_STANDARD "SB_LVDS_INPUT"
 .param PIN_TYPE 000001
-.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=io_pmod[0] PACKAGE_PIN=o_iq_tx_clk_n
+.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_clk_n
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:339.5-342.4"
+.attr src "top.v:335.5-338.4"
 .param IO_STANDARD "SB_LVCMOS"
 .param PIN_TYPE 011001
 .gate SB_IO CLOCK_ENABLE=$true D_OUT_0=lvds_clock PACKAGE_PIN=o_iq_tx_clk_p
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:330.5-333.4"
+.attr src "top.v:326.5-329.4"
 .param IO_STANDARD "SB_LVCMOS"
 .param PIN_TYPE 011001
-.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_n
+.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_n
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:319.5-324.4"
+.attr src "top.v:315.5-320.4"
 .param IO_STANDARD "SB_LVCMOS"
 .param PIN_TYPE 010000
-.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_p
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=iq_tx_n_OUTPUT_CLK
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:308.5-313.4"
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_p
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "top.v:304.5-309.4"
 .param IO_STANDARD "SB_LVCMOS"
 .param PIN_TYPE 010000
 .gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111111110000
 .gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010100010000010
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
-.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0111001101010000
-.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000001000101000
-.gate SB_CARRY CI=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 CO=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I1=$true
-.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0101000011011101
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0011000000000000
-.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=w_lvds_rx_09_d0 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111100000000
-.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000000010
-.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D
+.param LUT_INIT 0000000000000100
+.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1100101010101010
-.gate SB_LUT4 I0=$false I1=io_pmod[7] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] O=lvds_rx_09_inst.i_sync_input
+.gate SB_LUT4 I0=$false I1=io_pmod_in[3] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100110011110000
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O
+.param LUT_INIT 1100111111000000
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
 .gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
@@ -470,7 +428,7 @@
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O
@@ -479,278 +437,224 @@
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=sys_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
+.gate SB_LUT4 I0=spi_if_ins.o_load_cmd I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000100000000000
-.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0111011100100000
-.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010011010101111
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000110000000000
-.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.i_cs I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000110000000000
-.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111100000000
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000011111111
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000001100000000
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.param LUT_INIT 0010000000000000
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFE C=lvds_clock D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[1]
+.gate SB_DFFE C=lvds_clock D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[0]
+.gate SB_DFFE C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
 .gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
@@ -760,268 +664,285 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111111110000
-.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111111100001111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011111100001111
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d1 I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111100000000
-.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
+.gate SB_LUT4 I0=$false I1=i_rst_b I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000000010
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100110011000000
+.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=w_lvds_rx_24_d0 I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000000000001100
 .gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000000110011
-.gate SB_LUT4 I0=$false I1=io_pmod[6] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input
+.gate SB_LUT4 I0=$false I1=io_pmod_in[2] I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_24_inst.i_sync_input
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100111111000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.param LUT_INIT 1100110011110000
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
+.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[1]
+.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[0]
+.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFNESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_tx.v:58.5-128.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.empty_o O=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D
+.attr src "lvds_tx.v:58.5-128.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFNSR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D_SB_DFFNSR_Q_D Q=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
-.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
+.attr src "complex_fifo.v:88.2-96.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
+.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D_SB_DFFNSR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0001010101010101
+.gate SB_LUT4 I0=lvds_tx_inst.r_pulled I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.wr_addr_gray_rd_r[9] I3=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000001010001
+.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[2] I3=tx_fifo.wr_addr_gray_rd_r[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110000000000110
+.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110000001100
@@ -1029,7 +950,7 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000000000000000
@@ -1037,51 +958,15 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000110000
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[6] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[7] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1001000000000000
-.gate SB_LUT4 I0=tx_fifo.rd_addr[8] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr[6] I2=tx_fifo.wr_addr_gray_rd_r[6] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[8] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0011101010100011
-.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1001100111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000001111
-.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[6] I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[5] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
+.param LUT_INIT 0000100100000000
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0010100000111100
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000001001000001
@@ -1092,212 +977,188 @@
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led0 R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led0_SB_LUT4_I1_O[3]
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led0_SB_LUT4_I1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0001001101011111
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led0_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_DFFER_Q_E
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000100000000000
-.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_LUT4_I1_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001001101011111
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[2]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100111111111111
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led1_SB_LUT4_I1_I2[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led1_SB_LUT4_I1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1011100000000000
-.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso
-.attr src "top.v:150.19-150.43"
-.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=rx_fifo.empty_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000111100110011
+.param LUT_INIT 0000000000000011
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_DFFER_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000100000000000
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_LUT4_I1_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0001001101011111
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led1_SB_LUT4_I1_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000110000000000
+.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[1] I1=io_ctrl_ins.lna_rx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1100101000000000
+.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_I2[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111100000000
+.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso
+.attr src "top.v:152.19-152.43"
+.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=w_smi_read_req I3=smi_ctrl_ins.r_dir O=o_smi_read_req
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1111000000110011
 .gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_1_D
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1010111000001100
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D
+.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] O=r_tx_data_SB_DFFE_Q_2_D
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000110011111111
-.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_3_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1010111000001100
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3]
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_4_D
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100001111
+.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1010111000001100
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1010111000001100
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_5_D
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] O=r_tx_data_SB_DFFE_Q_5_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1111001011111111
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[2] I1=io_ctrl_ins.o_data_out[2] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001001101011111
+.param LUT_INIT 1100111011111111
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000110011111111
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
+.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0001001101011111
 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_7_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1111001011111111
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001001101011111
-.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000000100
-.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D
+.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_7_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000110011111111
-.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D
+.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011111100000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100001111
+.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000110011111111
+.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000000111111
-.gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105"
-.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1110110011001100
-.gate SB_LUT4 I0=rx_fifo.empty_o I1=rx_fifo.wr_addr_gray_rd_r[0] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.empty_o_SB_LUT4_I0_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000010000010
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_I3[3]
+.param LUT_INIT 0000110000000000
+.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000001100110000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.empty_o_SB_LUT4_I0_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1110011101111110
-.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000001101001
-.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.rd_addr[6] I2=rx_fifo.wr_addr_gray_rd_r[6] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001010011010111
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr[5] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000001111
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000001111
-.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] O=rx_fifo.empty_o_SB_LUT4_I0_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000011111001
-.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0001010000111100
-.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000001101111
-.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110000000000110
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100001100000000
+.param LUT_INIT 0000001100001111
 .gate SB_DFFSR C=lvds_clock D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.attr src "complex_fifo.v:62.2-70.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
 .gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
@@ -1318,11 +1179,101 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0010000000000000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
+.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000000000000000
-.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0]
+.param LUT_INIT 0100000000000000
+.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0011001101011010
+.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000110000000101
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[8]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[7]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000110000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[3] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 I0=$false I1=rx_fifo.wr_addr[2]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[3]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110000000000000
+.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000000001001
@@ -1330,21 +1281,21 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0010100000111100
-.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O
+.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I1_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0011000000000000
-.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
-.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
+.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000100000000000
@@ -1352,61 +1303,65 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111100000000
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1]
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O
+.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0101000011011101
-.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3]
+.param LUT_INIT 1111101100000000
+.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000000000000000
-.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
+.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000000011110000
-.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1010101000101010
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
-.param LUT_INIT 0000000011111111
-.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O CO=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I1=$true
-.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D
+.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0010100010000010
-.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1]
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 I0=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] I1=$true
+.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D
+.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0111000001010000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000001000101000
-.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1427,31 +1382,31 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.mem_i.0.0_WCLKE O=rx_fifo.wr_addr_SB_DFFESR_Q_E
+.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.mem_i.0.0_WCLKE O=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
 .gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100111111000000
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_1
+.param LUT_INIT 1111110000110000
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_2
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_3
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_3
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1472,23 +1427,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_1
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_2
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[20] I2=lvds_rx_09_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_3
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[21] I2=lvds_rx_09_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[23] I2=lvds_rx_09_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[22] I2=lvds_rx_09_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[20] I2=lvds_rx_09_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100110011110000
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1111000011001100
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1509,23 +1464,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_1
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_2
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[24] I2=lvds_rx_09_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_3
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[24] I2=lvds_rx_09_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_3
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[27] I2=lvds_rx_09_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.param LUT_INIT 1100110011110000
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1546,23 +1501,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_1
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[30] I2=lvds_rx_09_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_2
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_3
+.param LUT_INIT 1111000011001100
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[28] I2=lvds_rx_24_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_3
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[31] I2=lvds_rx_09_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA
+.param LUT_INIT 1111000011001100
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100110011110000
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.param LUT_INIT 1111000011001100
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1583,23 +1538,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[1] I2=lvds_rx_24_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_1
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[2] I2=lvds_rx_24_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_2
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_3
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[3] I2=lvds_rx_09_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100110011110000
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1111000011001100
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1620,23 +1575,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[5] I2=lvds_rx_09_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_1
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[5] I2=lvds_rx_09_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_2
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_3
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[4] I2=lvds_rx_24_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1111000011001100
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[7] I2=lvds_rx_09_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[7] I2=lvds_rx_09_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100110011110000
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1657,23 +1612,23 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_1
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_2
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[10] I2=lvds_rx_09_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[8] I2=lvds_rx_24_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_3
+.param LUT_INIT 1100110011110000
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_3
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA
+.param LUT_INIT 1100110011110000
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[11] I2=lvds_rx_09_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
+.param LUT_INIT 1100110011110000
+.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765"
 .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
@@ -1694,443 +1649,361 @@
 .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 .param READ_MODE 10
 .param WRITE_MODE 10
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_1
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_1
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_2
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_3
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1111000011001100
-.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[14] I2=lvds_rx_09_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_2
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_3
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1111000011001100
+.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100110011110000
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[7]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[5]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[4]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000000001000000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000001001000001
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+.gate SB_LUT4 I0=$false I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000100100000000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[4]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[5]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[7]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[3]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2]
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[5] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000001001000001
-.gate SB_LUT4 I0=rx_fifo.empty_o_SB_LUT4_I0_O[0] I1=rx_fifo.empty_o_SB_LUT4_I0_O[1] I2=rx_fifo.empty_o_SB_LUT4_I0_O[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0100000000000000
-.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000110000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1001000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000001001000001
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
+.param LUT_INIT 0000110000000011
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[1]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100001100111100
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr[1] I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0010100000010100
+.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010100000111100
-.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110000000000000
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[5] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 I0=$false I1=rx_fifo.wr_addr[3]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[2]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000010010
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[6]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[7]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000001100
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000001111
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[8] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000000111100
-.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[5]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000001100
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000001100110000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000001100
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[7]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[1]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0010100000111100
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100110000
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000001100
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
 .attr module_not_derived 00000000000000000000000000000001
@@ -2138,11 +2011,11 @@
 .param LUT_INIT 0000111111110000
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
 .attr module_not_derived 00000000000000000000000000000001
@@ -2150,27 +2023,27 @@
 .param LUT_INIT 0000111111110000
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2187,7 +2060,7 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000011101011
-.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000001100110000
@@ -2195,12 +2068,12 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2213,87 +2086,87 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111100000000
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[9] Q=rx_fifo.wr_addr_gray_rd[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[8] Q=rx_fifo.wr_addr_gray_rd[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[7] Q=rx_fifo.wr_addr_gray_rd[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[6] Q=rx_fifo.wr_addr_gray_rd[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[5] Q=rx_fifo.wr_addr_gray_rd[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[4] Q=rx_fifo.wr_addr_gray_rd[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[3] Q=rx_fifo.wr_addr_gray_rd[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[2] Q=rx_fifo.wr_addr_gray_rd[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[1] Q=rx_fifo.wr_addr_gray_rd[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[0] Q=rx_fifo.wr_addr_gray_rd[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[9] Q=rx_fifo.wr_addr_gray_rd_r[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[8] Q=rx_fifo.wr_addr_gray_rd_r[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[7] Q=rx_fifo.wr_addr_gray_rd_r[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[6] Q=rx_fifo.wr_addr_gray_rd_r[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[5] Q=rx_fifo.wr_addr_gray_rd_r[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[4] Q=rx_fifo.wr_addr_gray_rd_r[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[3] Q=rx_fifo.wr_addr_gray_rd_r[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[2] Q=rx_fifo.wr_addr_gray_rd_r[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[1] Q=rx_fifo.wr_addr_gray_rd_r[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[0] Q=rx_fifo.wr_addr_gray_rd_r[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFFESR C=r_counter D=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
@@ -2303,10 +2176,10 @@
 .param LUT_INIT 0000000011110000
 .gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
 .gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
@@ -2315,29 +2188,37 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
+.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=o_led0_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
+.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=o_led0_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
+.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESS C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=o_led0_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
-.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_smi_read_req O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=i_rst_b I1=smi_ctrl_ins.i_cs I2=spi_if_ins.o_ioc[1] I3=spi_if_ins.o_fetch_cmd O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010000000000000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3]
+.param LUT_INIT 0000100000000000
+.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[2] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000000000011
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0001010100111111
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2352,7 +2233,7 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2367,7 +2248,7 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2382,22 +2263,22 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111111110000
-.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
+.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.r_fifo_pulled_data[3] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010001100100000
+.param LUT_INIT 0010001000110000
 .gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[27] I1=smi_ctrl_ins.r_fifo_pulled_data[19] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2412,7 +2293,7 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2427,7 +2308,7 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2454,124 +2335,124 @@
 .param LUT_INIT 1010000011000000
 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
 .gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I2[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000100000000000
 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
-.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=smi_ctrl_ins.r_fifo_pull_1 I3=smi_ctrl_ins.r_fifo_pull O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O
+.attr src "smi_ctrl.v:142.5-151.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_pull_1 I2=w_smi_read_req I3=smi_ctrl_ins.r_fifo_pull O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000001100000000
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O
+.param LUT_INIT 0011000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_pull_trigger Q=smi_ctrl_ins.r_fifo_pull R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.attr src "smi_ctrl.v:142.5-151.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[31] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[31] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[30] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[30] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[21] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[21] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[20] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[20] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[19] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[19] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[18] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[18] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[17] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[17] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[16] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[16] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[15] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[15] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[14] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[14] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[13] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[13] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[12] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[12] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[29] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[29] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[11] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[11] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[10] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[10] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[9] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[9] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[8] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[7] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[6] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[6] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[5] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[4] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[3] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[2] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[28] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[28] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[1] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[0] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[27] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[27] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[26] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[26] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[25] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[25] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[24] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[24] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[23] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[23] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[22] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[22] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_push Q=smi_ctrl_ins.r_fifo_push_1 R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.attr src "smi_ctrl.v:260.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
 .gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push I3=smi_ctrl_ins.r_fifo_push_1 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
@@ -2584,111 +2465,87 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0011110000000000
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010100000111100
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0011001101011010
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 1111000000000000
-.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010000000000000
-.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000100000000000
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0010100000111100
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100100000000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011110011000011
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[5]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[7]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 I0=$false I1=tx_fifo.wr_addr[8]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000001010111110
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2]
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000001111011
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+.param LUT_INIT 0010100000111100
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[4]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2]
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[5] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_push_trigger Q=smi_ctrl_ins.r_fifo_push R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.attr src "smi_ctrl.v:260.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
 .gate SB_LUT4 I0=$false I1=$false I2=i_smi_soe_se I3=i_rst_b O=smi_ctrl_ins.soe_and_reset
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
@@ -2735,14 +2592,14 @@
 .param LUT_INIT 0000110000000000
 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.w_fifo_pull_trigger
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
+.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103"
 .gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111100000000
 .gate SB_DFFNSR C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D Q=smi_ctrl_ins.w_fifo_push_trigger R=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "smi_ctrl.v:189.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
+.attr src "smi_ctrl.v:178.5-258.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.i_smi_data_in[7] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
@@ -2753,42 +2610,42 @@
 .param LUT_INIT 0011001100111111
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:526.5-531.4"
+.attr src "top.v:532.5-537.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:535.5-540.4"
+.attr src "top.v:541.5-546.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:544.5-549.4"
+.attr src "top.v:550.5-555.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:553.5-558.4"
+.attr src "top.v:559.5-564.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:562.5-567.4"
+.attr src "top.v:568.5-573.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:571.5-576.4"
+.attr src "top.v:577.5-582.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:580.5-585.4"
+.attr src "top.v:586.5-591.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "top.v:589.5-594.4"
+.attr src "top.v:595.5-600.4"
 .param PIN_TYPE 101001
 .param PULLUP 0
 .gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D
@@ -2802,24 +2659,40 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1111111011101000
-.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000010111
-.gate SB_DFFER C=r_counter D=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000000000111111
 .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000000000010
+.param LUT_INIT 0000000000010111
+.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000000000100
 .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000000000010
+.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000000010000
 .gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_cs_SB_LUT4_I0_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
@@ -2856,11 +2729,7 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111100001111
-.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0011000000000000
-.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1010100000100000
@@ -2890,42 +2759,50 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 1111111111110000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011000000000000
+.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000000110000
+.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000000011110000
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[7]
+.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[7]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[6]
+.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[6]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[5]
+.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[5]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[4]
+.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[4]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[3]
+.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[2]
+.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[1]
+.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[0]
+.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
-.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid
+.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0101011100000000
@@ -2985,7 +2862,7 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000000001000
-.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_data_in_SB_DFFE_Q_E
+.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.o_data_in_SB_DFFE_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000000000
@@ -3164,48 +3041,44 @@
 .gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D
+.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110011110000
-.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 0000110000000000
-.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=spi_if_ins.state_if_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100000000000000
-.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000000000001111
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] O=spi_if_ins.r_tx_byte_SB_DFFE_Q_E
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000000011110000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000000110000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000000011000000
-.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1]
+.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 0000001100000000
-.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D[2] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.state_if_SB_DFFESR_Q_E
+.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000110000000000
+.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] O=spi_if_ins.state_if_SB_DFFESR_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0101010111011111
@@ -3216,577 +3089,882 @@
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000000000001111
-.gate SB_DFFNSS C=lvds_clock D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105"
-.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_DFFNSS_Q_D
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1110101010101010
-.gate SB_LUT4 I0=lvds_tx_inst.r_pulled I1=tx_fifo.empty_o I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_gray[9] O=tx_fifo.empty_o_SB_LUT4_I1_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0100010000000100
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.empty_o_SB_LUT4_I1_O[1] I2=tx_fifo.empty_o_SB_LUT4_I1_O[2] I3=tx_fifo.empty_o_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000010010000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.empty_o_SB_LUT4_I1_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_LUT4_I1_O[3]
+.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-.param LUT_INIT 1100001100000000
-.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
-.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1110101011000000
-.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
+.param LUT_INIT 0111011100100000
+.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:62.2-70.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1111100010001000
+.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100110000001100
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=tx_fifo.full_o_SB_LUT4_I1_O[0] I2=tx_fifo.full_o_SB_LUT4_I1_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2]
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1010001011110011
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[7] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3]
+.param LUT_INIT 0010000000000000
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1000001001000001
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3]
+.param LUT_INIT 0010000000000000
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0010100000111100
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.empty_o_SB_LUT4_I1_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[5]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[7]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[8]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[4]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[3]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[2]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[1]
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000010010000
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[6] I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000000000110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[4] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[3] I2=tx_fifo.rd_addr[2] I3=tx_fifo.wr_addr_gray_rd_r[2] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100110000
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100001100000000
+.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1001000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[7] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=tx_fifo.rd_addr[8] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[7]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[8]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0011101010100011
+.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr[6] I2=tx_fifo.wr_addr_gray_rd_r[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[5]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[4]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[3]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[2]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[1]
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.empty_o_SB_LUT4_I1_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000111100000011
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 1100111101000101
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
+.param LUT_INIT 0000000011101011
+.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000001100
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3]
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100001100000000
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
-.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000001100110000
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
+.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[8] Q=tx_fifo.rd_addr_gray_wr[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[7] Q=tx_fifo.rd_addr_gray_wr[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[6] Q=tx_fifo.rd_addr_gray_wr[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[5] Q=tx_fifo.rd_addr_gray_wr[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[4] Q=tx_fifo.rd_addr_gray_wr[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[3] Q=tx_fifo.rd_addr_gray_wr[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[2] Q=tx_fifo.rd_addr_gray_wr[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[1] Q=tx_fifo.rd_addr_gray_wr[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[0] Q=tx_fifo.rd_addr_gray_wr[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[9] Q=tx_fifo.rd_addr_gray_wr_r[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[8] Q=tx_fifo.rd_addr_gray_wr_r[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[7] Q=tx_fifo.rd_addr_gray_wr_r[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[6] Q=tx_fifo.rd_addr_gray_wr_r[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[5] Q=tx_fifo.rd_addr_gray_wr_r[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[4] Q=tx_fifo.rd_addr_gray_wr_r[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[3] Q=tx_fifo.rd_addr_gray_wr_r[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[2] Q=tx_fifo.rd_addr_gray_wr_r[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[1] Q=tx_fifo.rd_addr_gray_wr_r[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3]
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100001100111100
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[7]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[8]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[6]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[4]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[3]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[2]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100000000001100
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[5]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-.param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[3]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[1]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[1]
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1000001001000001
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
 .gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0110100110010110
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_8_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
-.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
+.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 1100111101000101
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100001100111100
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000001101001
-.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
+.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
 .param LUT_INIT 1100001100111100
-.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
 .param LUT_INIT 0000000000100011
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
+.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000111111110000
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
 .param LUT_INIT 0000000011111111
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
-.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7]
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
-.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0110100110010110
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0]
 .attr module_not_derived 00000000000000000000000000000001
-.attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
-.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
+.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90"
+.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=w_lvds_rx_09_d0 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000011111101
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
+.param LUT_INIT 0000000011111011
+.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d1_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000000011110000
-.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
-.param LUT_INIT 0000000011111101
-.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] O=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d1 I3=w_lvds_rx_09_d0 O=w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
 .param LUT_INIT 0000000011110000
-.names tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1]
+.gate SB_LUT4 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 I2=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1000000000000000
+.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] I2=$true I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_DFFER_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0010100010000010
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I2=w_lvds_rx_09_d1_SB_LUT4_I2_O[2] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0101000011011101
+.gate SB_LUT4 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0111001101010000
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O CO=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] I1=$true
+.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
+.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
+.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] I2=$true I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1000001000101000
+.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000010000000000
+.gate SB_DFFSR C=r_counter D=w_smi_read_req_SB_DFFSR_Q_D Q=w_smi_read_req R=i_rst_b_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "complex_fifo.v:88.2-96.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
+.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=w_smi_read_req_SB_DFFSR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0001001100110011
+.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[0] I1=w_smi_read_req I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=w_smi_read_req_SB_LUT4_I1_I3[3] O=w_smi_read_req_SB_LUT4_I1_O[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000000100001
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=w_smi_read_req_SB_LUT4_I1_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 1100000000001100
+.gate SB_LUT4 I0=rx_fifo.rd_addr[8] I1=rx_fifo.rd_addr[7] I2=rx_fifo.wr_addr_gray_rd_r[7] I3=w_smi_read_req_SB_LUT4_I1_O[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110100100000000
+.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000001101001
+.gate SB_LUT4 I0=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000001000000000
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[2] I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[1] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0011110011000011
+.gate SB_LUT4 I0=rx_fifo.rd_addr[6] I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000100110010000
+.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 1110011101111110
+.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[3] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0000000001101111
+.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[6] I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr[5] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+.param LUT_INIT 0000000000111100
+.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[3] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+.param LUT_INIT 0110011000001111
+.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+.param LUT_INIT 1111000000001111
+.names rx_fifo.wr_addr[2] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[0]
 1 1
-.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0]
+.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[1]
 1 1
-.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[0]
+.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
 1 1
-.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[1]
 1 1
-.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
+.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[0]
 1 1
-.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[2]
 1 1
-.names i_rst_b io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0]
+.names io_ctrl_ins.tr_vc_1_b_state o_led1_SB_LUT4_I1_I2[0]
 1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
+.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I2[1]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0]
+.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0]
+.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
 1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[2]
+.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
 1 1
-.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
+.names i_config[3] i_button_SB_LUT4_I0_I3[0]
 1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
+.names io_ctrl_ins.pmod_dir_state[6] i_button_SB_LUT4_I0_I3[1]
 1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
+.names o_led1_SB_LUT4_I1_I2[2] i_button_SB_LUT4_I0_I3[2]
 1 1
-.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0]
+.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0]
 1 1
-.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+1 1
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
+1 1
+.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
+1 1
+.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
+1 1
+.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
+1 1
+.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1]
+1 1
+.names io_ctrl_ins.rf_pin_state[6] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
+1 1
+.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0]
+1 1
+.names o_led1_SB_LUT4_I1_I2[3] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
+1 1
+.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0]
+1 1
+.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
+1 1
+.names tx_fifo.rd_addr[4] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[0]
+1 1
+.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
 1 1
 .names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0]
 1 1
 .names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
 1 1
-.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[3]
+.names w_lvds_rx_09_d1_SB_LUT4_I2_O[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[3]
 1 1
-.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.names spi_if_ins.o_ioc[0] o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[0]
 1 1
-.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
+1 1
+.names $true rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
+1 1
+.names i_rst_b w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
+1 1
+.names io_ctrl_ins.rx_h_state i_button_SB_LUT4_I0_O[0]
+1 1
+.names o_led1_SB_LUT4_I1_I2[3] i_button_SB_LUT4_I0_O[1]
+1 1
+.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
+1 1
+.names w_lvds_rx_24_d0 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1]
+1 1
+.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
+1 1
+.names i_config[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[0]
+1 1
+.names o_led1_SB_LUT4_I1_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0]
 1 1
 .names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0]
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[1]
 1 1
-.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[0]
+.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0]
 1 1
-.names lvds_tx_inst.r_pulled tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
+.names io_ctrl_ins.pmod_dir_state[0] o_led1_SB_LUT4_I1_I3[0]
 1 1
-.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
+.names o_led0 o_led1_SB_LUT4_I1_I3[1]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
+.names o_led1_SB_LUT4_I1_I2[2] o_led1_SB_LUT4_I1_I3[2]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.names smi_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
 1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
 1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[0]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
+.names $true rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[2]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[3]
+1 1
+.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
+1 1
+.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0]
+1 1
+.names rx_fifo.rd_addr[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
+1 1
+.names rx_fifo.rd_addr[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
+1 1
+.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[0]
+1 1
+.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
+1 1
+.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[2]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0]
+1 1
+.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+1 1
+.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+1 1
+.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+1 1
+.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[0]
+1 1
+.names o_led1_SB_LUT4_I1_I2[3] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1]
+1 1
+.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0]
+1 1
+.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1]
+1 1
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led0_SB_LUT4_I1_O[0]
+1 1
+.names io_pmod_in[3] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0]
+1 1
+.names spi_if_ins.o_ioc[1] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
+1 1
+.names spi_if_ins.o_ioc[0] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
+1 1
+.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
+1 1
+.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[0]
+1 1
+.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[1]
+1 1
+.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[3]
+1 1
+.names tx_fifo.rd_addr[7] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[0]
+1 1
+.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1]
+1 1
+.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[1]
+1 1
+.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
+1 1
+.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
+1 1
+.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[0]
+1 1
+.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[0]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
+1 1
+.names io_ctrl_ins.pmod_dir_state[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[0]
+1 1
+.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[1]
 1 1
 .names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
 1 1
@@ -3794,387 +3972,245 @@
 1 1
 .names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
 1 1
-.names io_ctrl_ins.rf_pin_state[0] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0]
+.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0]
 1 1
-.names i_rst_b w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
+.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
 1 1
-.names rx_fifo.rd_addr[7] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
+.names rx_fifo.wr_addr_gray_rd_r[0] w_smi_read_req_SB_LUT4_I1_I3[0]
 1 1
-.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
+.names w_smi_read_req w_smi_read_req_SB_LUT4_I1_I3[1]
 1 1
-.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0]
-1 1
-.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
-1 1
-.names tx_fifo.rd_addr[4] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1]
-1 1
-.names tx_fifo.rd_addr[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[1]
-1 1
-.names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0]
-1 1
-.names io_ctrl_ins.o_data_out[5] spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[1]
-1 1
-.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
-1 1
-.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[2]
-1 1
-.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
-1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
-1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[1]
-1 1
-.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[0]
-1 1
-.names smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3]
-1 1
-.names rx_fifo.wr_addr[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1]
-1 1
-.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2]
-1 1
-.names rx_fifo.rd_addr[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]
-1 1
-.names rx_fifo.rd_addr[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-1 1
-.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[0]
-1 1
-.names $true rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[2]
-1 1
-.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[3]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0]
-1 1
-.names rx_fifo.empty_o rx_fifo.empty_o_SB_LUT4_I0_I3[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.empty_o_SB_LUT4_I0_I3[1]
-1 1
-.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.empty_o_SB_LUT4_I0_I3[2]
-1 1
-.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
-1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2]
-1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0]
-1 1
-.names $true lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1]
-1 1
-.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0]
-1 1
-.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1]
-1 1
-.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
-1 1
-.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
-1 1
-.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1]
-1 1
-.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
-1 1
-.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
-1 1
-.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
-1 1
-.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
-1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
-1 1
-.names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
-1 1
-.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
-1 1
-.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
-1 1
-.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
-1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-1 1
-.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
-1 1
-.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
-1 1
-.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
-1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
-1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0]
-1 1
-.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led1_SB_LUT4_I1_O[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led1_SB_LUT4_I1_O[1]
-1 1
-.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
-1 1
-.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I1_O[0]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
-1 1
-.names i_button io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[0]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1]
-1 1
-.names io_ctrl_ins.rf_pin_state[5] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[0]
-1 1
-.names io_pmod[6] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
-1 1
-.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0]
-1 1
-.names i_config_SB_LUT4_I0_1_O[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1]
-1 1
-.names tx_fifo.rd_addr[8] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-1 1
-.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[0]
-1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[1]
-1 1
-.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
-1 1
-.names tx_fifo.rd_addr[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[8] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
-1 1
-.names i_config[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
-1 1
-.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
-1 1
-.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
-1 1
-.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0]
-1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2]
-1 1
-.names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
-1 1
-.names spi_if_ins.o_ioc[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[0]
-1 1
-.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[1]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
-1 1
-.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
-1 1
-.names spi_if_ins.o_load_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[1]
-1 1
-.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
-1 1
-.names io_ctrl_ins.tr_vc_1_b_state i_config_SB_LUT4_I0_1_O[0]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0]
-1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1]
-1 1
-.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2]
-1 1
-.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[0]
-1 1
-.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[0]
-1 1
-.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[1]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[3]
-1 1
-.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0]
-1 1
-.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_D[0]
-1 1
-.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[0]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[1]
-1 1
-.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[2]
-1 1
-.names i_config[1] o_led1_SB_LUT4_I1_I2[0]
-1 1
-.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I2[1]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] o_led1_SB_LUT4_I1_I2[3]
-1 1
-.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
-1 1
-.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[0]
-1 1
-.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
-1 1
-.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0]
-1 1
-.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] o_led0_SB_LUT4_I1_O[0]
-1 1
-.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led0_SB_LUT4_I1_O[1]
-1 1
-.names i_config[0] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0]
-1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1]
+.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] w_smi_read_req_SB_LUT4_I1_I3[2]
 1 1
 .names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
+.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
+.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
 1 1
-.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
 1 1
-.names spi_if_ins.o_ioc[1] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0]
+.names w_lvds_rx_24_d1 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[0]
 1 1
-.names spi_if_ins.o_ioc[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
+.names w_lvds_rx_24_d0 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[1]
 1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2]
+.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[2]
 1 1
 .names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0]
 1 1
 .names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
 1 1
-.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
+.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[1]
+.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2]
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[1]
+1 1
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[2]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+1 1
+.names rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
+1 1
+.names rx_fifo.rd_addr[8] w_smi_read_req_SB_LUT4_I1_O[0]
+1 1
+.names rx_fifo.rd_addr[7] w_smi_read_req_SB_LUT4_I1_O[1]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[7] w_smi_read_req_SB_LUT4_I1_O[2]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
+1 1
+.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[0]
+1 1
+.names $true w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[2]
+1 1
+.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
+1 1
+.names io_pmod_in[2] lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+1 1
+.names rx_fifo.rd_addr[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.rd_addr[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
+1 1
+.names rx_fifo.rd_addr[7] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.rd_addr[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+1 1
+.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
+1 1
+.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[1]
+1 1
+.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
+1 1
+.names tx_fifo.rd_addr[7] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0]
+1 1
+.names tx_fifo.rd_addr[6] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
+1 1
+.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[2]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
+1 1
+.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
+1 1
+.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[1]
+1 1
+.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[2]
+1 1
+.names spi_if_ins.o_ioc[1] o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[0]
+1 1
+.names spi_if_ins.o_ioc[0] o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[1]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+1 1
+.names spi_if_ins.o_ioc[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[0]
+1 1
+.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[1]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
+1 1
+.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[0]
+1 1
+.names sys_ctrl_ins.i_cs sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[1]
+1 1
+.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+1 1
+.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
+1 1
+.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[1]
+1 1
+.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
+1 1
+.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_5_D[1]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1]
+1 1
+.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0]
+1 1
+.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1]
+1 1
+.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+1 1
+.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
+1 1
+.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[0]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
+1 1
+.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[0]
+1 1
+.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
+1 1
+.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1]
+1 1
+.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
+1 1
+.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
+1 1
+.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
+1 1
+.names w_lvds_rx_09_d1_SB_LUT4_I2_O[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1]
+1 1
+.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0]
+1 1
+.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[0]
+1 1
+.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
+1 1
+.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[1]
 1 1
 .names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
 1 1
 .names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
 1 1
-.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[0]
+.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
 1 1
-.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[1]
+.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[1]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
 1 1
-.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[1]
+.names o_led0_SB_LUT4_I1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[1]
 1 1
-.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
+.names o_led0_SB_LUT4_I1_O[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
 1 1
-.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] o_led1_SB_LUT4_I1_O[0]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2]
+.names o_led0_SB_LUT4_I1_O[1] o_led1_SB_LUT4_I1_O[1]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
+.names tx_fifo.wr_addr_gray_rd_r[0] lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
 1 1
-.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1]
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
 1 1
-.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5]
+.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
 1 1
-.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9]
+.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
 1 1
-.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13]
+.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[1]
 1 1
-.names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1]
+.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
 1 1
-.names rx_fifo.rd_data_o[2] rx_fifo.mem_q.0.0_RDATA[5]
+.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
 1 1
-.names rx_fifo.rd_data_o[1] rx_fifo.mem_q.0.0_RDATA[9]
-1 1
-.names rx_fifo.rd_data_o[3] rx_fifo.mem_q.0.0_RDATA[13]
+.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
 1 1
 .names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1]
 1 1
@@ -4184,30 +4220,6 @@
 1 1
 .names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13]
 1 1
-.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1]
-1 1
-.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5]
-1 1
-.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9]
-1 1
-.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13]
-1 1
-.names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1]
-1 1
-.names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5]
-1 1
-.names rx_fifo.rd_data_o[5] rx_fifo.mem_q.0.1_RDATA[9]
-1 1
-.names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13]
-1 1
-.names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1]
-1 1
-.names rx_fifo.rd_data_o[30] rx_fifo.mem_i.0.3_RDATA[5]
-1 1
-.names rx_fifo.rd_data_o[29] rx_fifo.mem_i.0.3_RDATA[9]
-1 1
-.names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13]
-1 1
 .names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1]
 1 1
 .names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5]
@@ -4224,15 +4236,53 @@
 1 1
 .names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13]
 1 1
-.names smi_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
+.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1]
 1 1
-.names io_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1]
+.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5]
 1 1
-.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
+.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13]
 1 1
-.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1]
+1 1
+.names rx_fifo.rd_data_o[2] rx_fifo.mem_q.0.0_RDATA[5]
+1 1
+.names rx_fifo.rd_data_o[1] rx_fifo.mem_q.0.0_RDATA[9]
+1 1
+.names rx_fifo.rd_data_o[3] rx_fifo.mem_q.0.0_RDATA[13]
+1 1
+.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1]
+1 1
+.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5]
+1 1
+.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9]
+1 1
+.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13]
+1 1
+.names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1]
+1 1
+.names rx_fifo.rd_data_o[30] rx_fifo.mem_i.0.3_RDATA[5]
+1 1
+.names rx_fifo.rd_data_o[29] rx_fifo.mem_i.0.3_RDATA[9]
+1 1
+.names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13]
+1 1
+.names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1]
+1 1
+.names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5]
+1 1
+.names rx_fifo.rd_data_o[5] rx_fifo.mem_q.0.1_RDATA[9]
+1 1
+.names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13]
+1 1
+.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
+1 1
+.names lvds_tx_inst.r_pulled lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[0]
+1 1
+.names tx_fifo.rd_addr_gray[9] lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
+1 1
+.names tx_fifo.wr_addr_gray_rd_r[9] lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
 1 1
 .names spi_if_ins.spi.o_spi_miso int_miso
 1 1
@@ -4314,11 +4364,13 @@
 1 1
 .names io_ctrl_ins.tr_vc_2_state io_ctrl_ins.o_tr_vc2
 1 1
-.names $false io_pmod[1]
+.names io_ctrl_ins.pmod_state[0] io_pmod_out[0]
 1 1
-.names $false io_pmod[2]
+.names io_ctrl_ins.pmod_state[1] io_pmod_out[1]
 1 1
-.names i_smi_swe_srw io_pmod[3]
+.names io_ctrl_ins.pmod_state[2] io_pmod_out[2]
+1 1
+.names io_ctrl_ins.pmod_state[3] io_pmod_out[3]
 1 1
 .names lvds_clock lvds_clock_buf
 1 1
@@ -4342,9 +4394,9 @@
 1 1
 .names lvds_clock lvds_rx_24_inst.o_fifo_write_clk
 1 1
-.names $undef lvds_tx_inst.i_debug_lb
+.names lvds_clock lvds_tx_inst.i_ddr_clk
 1 1
-.names tx_fifo.empty_o lvds_tx_inst.i_fifo_empty
+.names $undef lvds_tx_inst.i_debug_lb
 1 1
 .names i_rst_b lvds_tx_inst.i_rst_b
 1 1
@@ -4362,6 +4414,8 @@
 1 1
 .names lvds_tx_inst.r_pulled lvds_tx_inst.o_fifo_pull
 1 1
+.names lvds_clock lvds_tx_inst.o_fifo_read_clk
+1 1
 .names $false lvds_tx_inst.o_sync_state_bit
 1 1
 .names $false lvds_tx_inst.o_tx_state_bit
@@ -4444,7 +4498,7 @@
 1 1
 .names io_ctrl_ins.lna_tx_shutdown_state o_shdn_tx_lna
 1 1
-.names $undef o_smi_write_req
+.names i_smi_swe_srw o_smi_write_req
 1 1
 .names io_ctrl_ins.tr_vc_1_state o_tr_vc1
 1 1
@@ -4452,10 +4506,6 @@
 1 1
 .names io_ctrl_ins.tr_vc_2_state o_tr_vc2
 1 1
-.names $false rx_fifo.debug_pull
-1 1
-.names $false rx_fifo.debug_push
-1 1
 .names rx_fifo.rd_addr_gray[9] rx_fifo.rd_addr[9]
 1 1
 .names r_counter rx_fifo.rd_clk_i
@@ -4500,8 +4550,6 @@
 1 1
 .names i_rst_b smi_ctrl_ins.i_rst_b
 1 1
-.names rx_fifo.empty_o smi_ctrl_ins.i_rx_fifo_empty
-1 1
 .names rx_fifo.rd_data_o[0] smi_ctrl_ins.i_rx_fifo_pulled_data[0]
 1 1
 .names rx_fifo.rd_data_o[1] smi_ctrl_ins.i_rx_fifo_pulled_data[1]
@@ -4584,8 +4632,6 @@
 1 1
 .names i_smi_swe_srw smi_ctrl_ins.i_smi_swe_srw
 1 1
-.names $false smi_ctrl_ins.i_smi_test
-1 1
 .names r_counter smi_ctrl_ins.i_sys_clk
 1 1
 .names tx_fifo.full_o smi_ctrl_ins.i_tx_fifo_full
@@ -4634,6 +4680,8 @@
 1 1
 .names smi_ctrl_ins.r_dir smi_ctrl_ins.o_dir
 1 1
+.names w_smi_read_req smi_ctrl_ins.o_smi_read_req
+1 1
 .names r_counter smi_ctrl_ins.o_tx_fifo_clock
 1 1
 .names $false smi_ctrl_ins.o_tx_fifo_pushed_data[0]
@@ -4824,10 +4872,6 @@
 1 1
 .names $undef sys_ctrl_ins.o_tx_sample_gap[3]
 1 1
-.names $false tx_fifo.debug_pull
-1 1
-.names $false tx_fifo.debug_push
-1 1
 .names tx_fifo.rd_addr_gray[9] tx_fifo.rd_addr[9]
 1 1
 .names lvds_tx_inst.r_pulled tx_fifo.rd_en_i
@@ -5090,8 +5134,6 @@
 1 1
 .names spi_if_ins.o_data_in[7] w_rx_data[7]
 1 1
-.names rx_fifo.empty_o w_rx_fifo_empty
-1 1
 .names rx_fifo.full_o w_rx_fifo_full
 1 1
 .names rx_fifo.rd_data_o[0] w_rx_fifo_pulled_data[0]
@@ -5206,8 +5248,6 @@
 1 1
 .names smi_ctrl_ins.o_data_out[2] w_tx_data_smi[2]
 1 1
-.names r_counter w_tx_fifo_clock
-1 1
 .names $false w_tx_fifo_data[0]
 1 1
 .names $undef w_tx_fifo_data[1]
@@ -5272,10 +5312,10 @@
 1 1
 .names $undef w_tx_fifo_data[31]
 1 1
-.names tx_fifo.empty_o w_tx_fifo_empty
-1 1
 .names tx_fifo.full_o w_tx_fifo_full
 1 1
 .names lvds_tx_inst.r_pulled w_tx_fifo_pull
 1 1
+.names lvds_clock w_tx_fifo_read_clk
+1 1
 .end
diff --git a/firmware/top.json b/firmware/top.json
index f891558..884d0c0 100644
--- a/firmware/top.json
+++ b/firmware/top.json
@@ -21,7 +21,7 @@
         }
       },
       "cells": {
-        "$specify$8471": {
+        "$specify$8308": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -404,7 +404,7 @@
         }
       },
       "cells": {
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8346": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8183": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -428,7 +428,7 @@
             "Y": [ 78 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8347": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8184": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -452,7 +452,7 @@
             "Y": [ 79 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8348": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8185": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -476,7 +476,7 @@
             "Y": [ 80 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8349": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8186": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -819,28 +819,28 @@
         }
       },
       "netnames": {
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8346_Y": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8183_Y": {
           "hide_name": 1,
           "bits": [ 78 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661.33-1661.44"
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8347_Y": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8184_Y": {
           "hide_name": 1,
           "bits": [ 79 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663.34-1663.45"
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8348_Y": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8185_Y": {
           "hide_name": 1,
           "bits": [ 80 ],
           "attributes": {
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@@ -952,7 +952,7 @@
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@@ -1022,7 +1022,7 @@
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@@ -1092,7 +1092,7 @@
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@@ -1162,7 +1162,7 @@
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@@ -1232,7 +1232,7 @@
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@@ -1302,7 +1302,7 @@
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@@ -1372,7 +1372,7 @@
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@@ -1442,7 +1442,7 @@
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@@ -4788,8 +4788,9 @@
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@@ -5020,8 +5021,9 @@
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@@ -11211,7 +11213,7 @@
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@@ -11294,69 +11296,123 @@
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-          "bits": [ 23, "0", "0", 24, 25, 26, 27, 28 ]
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@@ -11371,10 +11427,10 @@
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@@ -11395,11 +11451,11 @@
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@@ -11420,61 +11476,11 @@
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@@ -11497,9 +11503,9 @@
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@@ -11524,7 +11530,7 @@
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@@ -11548,8 +11554,8 @@
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@@ -11569,11 +11575,11 @@
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@@ -11596,9 +11602,9 @@
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@@ -11617,9 +11623,9 @@
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@@ -11642,10 +11648,10 @@
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@@ -11664,9 +11670,9 @@
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@@ -11674,7 +11680,7 @@
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@@ -11688,18 +11694,18 @@
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0": {
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           "type": "SB_LUT4",
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@@ -11713,14 +11719,14 @@
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3": {
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@@ -11739,13 +11745,13 @@
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q": {
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@@ -11762,232 +11768,11 @@
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@@ -12440,67 +12200,67 @@
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@@ -12537,10 +12347,10 @@
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@@ -12559,10 +12369,10 @@
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@@ -12581,10 +12391,10 @@
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@@ -12603,10 +12413,10 @@
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@@ -12625,9 +12435,9 @@
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@@ -12669,10 +12479,10 @@
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@@ -12691,10 +12501,10 @@
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@@ -12713,10 +12523,10 @@
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@@ -12735,10 +12545,10 @@
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@@ -12757,10 +12567,10 @@
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@@ -13296,10 +13106,231 @@
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@@ -13318,9 +13349,9 @@
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@@ -13328,7 +13359,57 @@
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@@ -13343,60 +13424,10 @@
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-          "port_directions": {
-            "I0": "input",
-            "I1": "input",
-            "I2": "input",
-            "I3": "input",
-            "O": "output"
-          },
-          "connections": {
-            "I0": [ 6 ],
-            "I1": [ 136 ],
-            "I2": [ 51 ],
-            "I3": [ 58 ],
-            "O": [ 127 ]
+            "I1": [ 6 ],
+            "I2": [ 144 ],
+            "I3": [ 62 ],
+            "O": [ 120 ]
           }
         },
         "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q": {
@@ -13415,9 +13446,9 @@
             "Q": "output"
           },
           "connections": {
-            "C": [ 66 ],
-            "D": [ 156 ],
-            "E": [ 74 ],
+            "C": [ 70 ],
+            "D": [ 159 ],
+            "E": [ 78 ],
             "Q": [ 8 ]
           }
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@@ -13439,18 +13470,18 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 149 ],
-            "I1": [ 59 ],
-            "I2": [ 76 ],
-            "I3": [ 77 ],
-            "O": [ 156 ]
+            "I0": [ 151 ],
+            "I1": [ 80 ],
+            "I2": [ 84 ],
+            "I3": [ 81 ],
+            "O": [ 159 ]
           }
         },
-        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1011100000000000"
+            "LUT_INIT": "0001001101011111"
           },
           "attributes": {
             "module_not_derived": "00000000000000000000000000000001",
@@ -13464,18 +13495,18 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 8 ],
-            "I1": [ 56 ],
-            "I2": [ 141 ],
-            "I3": [ 57 ],
-            "O": [ 110 ]
+            "I0": [ 18 ],
+            "I1": [ 8 ],
+            "I2": [ 124 ],
+            "I3": [ 144 ],
+            "O": [ 160 ]
           }
         },
-        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O_SB_LUT4_O": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O_SB_LUT4_I2": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "0101111100010011"
+            "LUT_INIT": "0000011100000000"
           },
           "attributes": {
             "module_not_derived": "00000000000000000000000000000001",
@@ -13490,13 +13521,184 @@
           },
           "connections": {
             "I0": [ 137 ],
-            "I1": [ 76 ],
-            "I2": [ 51 ],
-            "I3": [ 96 ],
-            "O": [ 111 ]
+            "I1": [ 51 ],
+            "I2": [ 161 ],
+            "I3": [ 160 ],
+            "O": [ 103 ]
           }
         },
-        "io_pmod_SB_LUT4_O": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O_SB_LUT4_O": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000110000000000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
+          },
+          "connections": {
+            "I0": [ "0" ],
+            "I1": [ 26 ],
+            "I2": [ 55 ],
+            "I3": [ 85 ],
+            "O": [ 161 ]
+          }
+        },
+        "iq_rx_09": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVDS_INPUT",
+            "NEG_TRIGGER": "0",
+            "PIN_TYPE": "000000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "top.v:289.7-294.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_IN_0": "output",
+            "D_IN_1": "output",
+            "INPUT_CLK": "input",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_IN_0": [ 162 ],
+            "D_IN_1": [ 163 ],
+            "INPUT_CLK": [ 164 ],
+            "PACKAGE_PIN": [ 15 ]
+          }
+        },
+        "iq_rx_24": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVDS_INPUT",
+            "NEG_TRIGGER": "0",
+            "PIN_TYPE": "000000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "top.v:274.7-280.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_IN_0": "output",
+            "D_IN_1": "output",
+            "INPUT_CLK": "input",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_IN_0": [ 165 ],
+            "D_IN_1": [ 166 ],
+            "INPUT_CLK": [ 164 ],
+            "PACKAGE_PIN": [ 16 ]
+          }
+        },
+        "iq_rx_clk": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVDS_INPUT",
+            "PIN_TYPE": "000001"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "top.v:256.7-259.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_IN_0": "output",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_IN_0": [ 164 ],
+            "PACKAGE_PIN": [ 17 ]
+          }
+        },
+        "iq_tx_clk_n": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVCMOS",
+            "PIN_TYPE": "011001"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "top.v:335.5-338.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_OUT_0": "input",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_OUT_0": [ 167 ],
+            "PACKAGE_PIN": [ 14 ]
+          }
+        },
+        "iq_tx_clk_p": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVCMOS",
+            "PIN_TYPE": "011001"
+          },
+          "attributes": {
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+            "src": "top.v:326.5-329.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_OUT_0": "input",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_OUT_0": [ 164 ],
+            "PACKAGE_PIN": [ 13 ]
+          }
+        },
+        "iq_tx_n": {
+          "hide_name": 0,
+          "type": "SB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVCMOS",
+            "PIN_TYPE": "010000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "top.v:315.5-320.4"
+          },
+          "port_directions": {
+            "CLOCK_ENABLE": "input",
+            "D_OUT_0": "input",
+            "D_OUT_1": "input",
+            "OUTPUT_CLK": "input",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "CLOCK_ENABLE": [ "1" ],
+            "D_OUT_0": [ "0" ],
+            "D_OUT_1": [ "0" ],
+            "OUTPUT_CLK": [ 167 ],
+            "PACKAGE_PIN": [ 12 ]
+          }
+        },
+        "iq_tx_n_OUTPUT_CLK_SB_LUT4_O": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
@@ -13517,154 +13719,8 @@
             "I0": [ "0" ],
             "I1": [ "0" ],
             "I2": [ "0" ],
-            "I3": [ 157 ],
-            "O": [ 23 ]
-          }
-        },
-        "iq_rx_09": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVDS_INPUT",
-            "NEG_TRIGGER": "0",
-            "PIN_TYPE": "000000"
-          },
-          "attributes": {
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-            "src": "top.v:293.7-298.4"
-          },
-          "port_directions": {
-            "CLOCK_ENABLE": "input",
-            "D_IN_0": "output",
-            "D_IN_1": "output",
-            "INPUT_CLK": "input",
-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_IN_0": [ 158 ],
-            "D_IN_1": [ 159 ],
-            "INPUT_CLK": [ 157 ],
-            "PACKAGE_PIN": [ 15 ]
-          }
-        },
-        "iq_rx_24": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVDS_INPUT",
-            "NEG_TRIGGER": "0",
-            "PIN_TYPE": "000000"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "top.v:278.7-284.4"
-          },
-          "port_directions": {
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-            "D_IN_0": "output",
-            "D_IN_1": "output",
-            "INPUT_CLK": "input",
-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_IN_0": [ 160 ],
-            "D_IN_1": [ 161 ],
-            "INPUT_CLK": [ 157 ],
-            "PACKAGE_PIN": [ 16 ]
-          }
-        },
-        "iq_rx_clk": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVDS_INPUT",
-            "PIN_TYPE": "000001"
-          },
-          "attributes": {
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-            "src": "top.v:260.7-263.4"
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-          "port_directions": {
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-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_IN_0": [ 157 ],
-            "PACKAGE_PIN": [ 17 ]
-          }
-        },
-        "iq_tx_clk_n": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVCMOS",
-            "PIN_TYPE": "011001"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "top.v:339.5-342.4"
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-          "port_directions": {
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-            "D_OUT_0": "input",
-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_OUT_0": [ 23 ],
-            "PACKAGE_PIN": [ 14 ]
-          }
-        },
-        "iq_tx_clk_p": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVCMOS",
-            "PIN_TYPE": "011001"
-          },
-          "attributes": {
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-            "src": "top.v:330.5-333.4"
-          },
-          "port_directions": {
-            "CLOCK_ENABLE": "input",
-            "D_OUT_0": "input",
-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_OUT_0": [ 157 ],
-            "PACKAGE_PIN": [ 13 ]
-          }
-        },
-        "iq_tx_n": {
-          "hide_name": 0,
-          "type": "SB_IO",
-          "parameters": {
-            "IO_STANDARD": "SB_LVCMOS",
-            "PIN_TYPE": "010000"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "top.v:319.5-324.4"
-          },
-          "port_directions": {
-            "CLOCK_ENABLE": "input",
-            "D_OUT_0": "input",
-            "D_OUT_1": "input",
-            "OUTPUT_CLK": "input",
-            "PACKAGE_PIN": "inout"
-          },
-          "connections": {
-            "CLOCK_ENABLE": [ "1" ],
-            "D_OUT_0": [ "0" ],
-            "D_OUT_1": [ "0" ],
-            "OUTPUT_CLK": [ 23 ],
-            "PACKAGE_PIN": [ 12 ]
+            "I3": [ 164 ],
+            "O": [ 167 ]
           }
         },
         "iq_tx_p": {
@@ -13676,7 +13732,7 @@
           },
           "attributes": {
             "module_not_derived": "00000000000000000000000000000001",
-            "src": "top.v:308.5-313.4"
+            "src": "top.v:304.5-309.4"
           },
           "port_directions": {
             "CLOCK_ENABLE": "input",
@@ -13689,7 +13745,7 @@
             "CLOCK_ENABLE": [ "1" ],
             "D_OUT_0": [ "1" ],
             "D_OUT_1": [ "1" ],
-            "OUTPUT_CLK": [ 23 ],
+            "OUTPUT_CLK": [ 167 ],
             "PACKAGE_PIN": [ 11 ]
           }
         },
@@ -13710,11 +13766,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 157 ],
-            "D": [ 162 ],
-            "E": [ 163 ],
-            "Q": [ 164 ],
-            "R": [ 64 ]
+            "C": [ 164 ],
+            "D": [ 168 ],
+            "E": [ 169 ],
+            "Q": [ 170 ],
+            "R": [ 68 ]
           }
         },
         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2": {
@@ -13737,9 +13793,9 @@
           "connections": {
             "I0": [ "0" ],
             "I1": [ "0" ],
-            "I2": [ 163 ],
-            "I3": [ 165 ],
-            "O": [ 166 ]
+            "I2": [ 169 ],
+            "I3": [ 171 ],
+            "O": [ 172 ]
           }
         },
         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E": {
@@ -13759,11 +13815,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 157 ],
-            "D": [ 167 ],
-            "E": [ 166 ],
-            "Q": [ 168 ],
-            "R": [ 64 ]
+            "C": [ 164 ],
+            "D": [ 173 ],
+            "E": [ 172 ],
+            "Q": [ 174 ],
+            "R": [ 68 ]
           }
         },
         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1": {
@@ -13783,279 +13839,11 @@
             "R": "input"
           },
           "connections": {
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-            "D": [ 169 ],
-            "E": [ 166 ],
-            "Q": [ 170 ],
-            "R": [ 64 ]
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q": {
-          "hide_name": 0,
-          "type": "SB_DFFER",
-          "parameters": {
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-          "attributes": {
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-            "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116"
-          },
-          "port_directions": {
-            "C": "input",
-            "D": "input",
-            "E": "input",
-            "Q": "output",
-            "R": "input"
-          },
-          "connections": {
-            "C": [ 157 ],
-            "D": [ 171 ],
+            "C": [ 164 ],
+            "D": [ 175 ],
             "E": [ 172 ],
-            "Q": [ 173 ],
-            "R": [ 64 ]
-          }
-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1": {
-          "hide_name": 0,
-          "type": "SB_DFFER",
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "0010100010000010"
-          },
-          "attributes": {
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-            "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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-            "I1": "input",
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-            "I0": [ 170 ],
-            "I1": [ 176 ],
-            "I2": [ "1" ],
-            "I3": [ 177 ],
-            "O": [ 174 ]
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
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-          },
-          "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52"
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-            "I1": [ "0" ],
-            "I2": [ "0" ],
-            "I3": [ 175 ],
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
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-          },
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-            "I3": [ 178 ],
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-          }
-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2": {
-          "hide_name": 0,
-          "type": "SB_DFFER",
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-          "hide_name": 0,
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-            "LUT_INIT": "0111001101010000"
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-            "O": [ 179 ]
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@@ -16604,17 +15970,17 @@
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@@ -20806,15 +20566,15 @@
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@@ -20862,10 +20622,10 @@
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@@ -20887,10 +20647,10 @@
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@@ -20912,10 +20672,10 @@
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@@ -20937,10 +20697,10 @@
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@@ -20962,10 +20722,10 @@
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@@ -21010,15 +20770,15 @@
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@@ -21026,7 +20786,7 @@
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-            "LUT_INIT": "1111000011001100"
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@@ -21041,17 +20801,17 @@
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-            "LUT_INIT": "1111000011001100"
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@@ -21066,10 +20826,10 @@
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@@ -21091,17 +20851,17 @@
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           "type": "SB_LUT4",
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-            "LUT_INIT": "1100110011110000"
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@@ -21116,10 +20876,10 @@
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@@ -21164,15 +20924,15 @@
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@@ -21195,10 +20955,10 @@
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@@ -21220,10 +20980,10 @@
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@@ -21245,17 +21005,17 @@
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-            "LUT_INIT": "1111000011001100"
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@@ -21270,10 +21030,10 @@
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@@ -21318,15 +21078,15 @@
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@@ -21349,17 +21109,17 @@
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@@ -21374,17 +21134,17 @@
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@@ -21399,17 +21159,17 @@
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@@ -21424,10 +21184,10 @@
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@@ -21472,15 +21232,15 @@
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@@ -21488,7 +21248,7 @@
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-            "LUT_INIT": "1111000011001100"
+            "LUT_INIT": "1100110011110000"
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@@ -21503,17 +21263,17 @@
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-            "LUT_INIT": "1111000011001100"
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@@ -21528,10 +21288,10 @@
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@@ -21553,17 +21313,17 @@
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           "type": "SB_LUT4",
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-            "LUT_INIT": "1100110011110000"
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@@ -21578,10 +21338,10 @@
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         "rx_fifo.mem_q.0.1": {
@@ -21626,15 +21386,15 @@
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@@ -21657,10 +21417,10 @@
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@@ -21682,17 +21442,17 @@
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-            "LUT_INIT": "1100110011110000"
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@@ -21707,10 +21467,10 @@
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@@ -21732,10 +21492,10 @@
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         "rx_fifo.mem_q.0.2": {
@@ -21780,15 +21540,15 @@
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@@ -21811,17 +21571,17 @@
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@@ -21836,17 +21596,17 @@
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@@ -21861,17 +21621,17 @@
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           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1111000011001100"
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@@ -21886,10 +21646,10 @@
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-            "O": [ 684 ]
+            "I1": [ 278 ],
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         "rx_fifo.mem_q.0.3": {
@@ -21934,15 +21694,15 @@
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-            "RDATA": [ 685, 686, 687, 688, 689, 690, 691, 692, 693, 694, 695, 696, 697, 698, 699, 700 ],
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+            "RCLKE": [ 521 ],
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@@ -29458,10 +28546,10 @@
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@@ -29473,7 +28561,7 @@
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@@ -29484,10 +28572,10 @@
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@@ -29499,7 +28587,7 @@
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@@ -29510,10 +28598,10 @@
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@@ -29533,11 +28621,11 @@
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@@ -29560,9 +28648,9 @@
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@@ -29583,11 +28671,11 @@
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@@ -29608,46 +28696,22 @@
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@@ -29657,14 +28721,14 @@
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@@ -29682,14 +28746,138 @@
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@@ -29707,11 +28895,11 @@
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@@ -29735,8 +28923,8 @@
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@@ -29755,10 +28943,10 @@
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@@ -29777,10 +28965,10 @@
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@@ -29799,10 +28987,10 @@
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@@ -29821,10 +29009,10 @@
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@@ -29843,10 +29031,10 @@
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@@ -29865,10 +29053,10 @@
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@@ -29887,10 +29075,10 @@
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@@ -29909,10 +29097,10 @@
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@@ -29932,11 +29120,11 @@
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@@ -29959,34 +29147,9 @@
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@@ -30008,10 +29171,10 @@
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@@ -30033,10 +29196,10 @@
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@@ -30055,10 +29218,10 @@
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@@ -30077,10 +29240,10 @@
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@@ -30099,10 +29262,10 @@
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@@ -30121,10 +29284,10 @@
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@@ -30143,10 +29306,10 @@
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@@ -30166,11 +29329,11 @@
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@@ -30193,9 +29356,34 @@
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+        },
+        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_O_1": {
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+          "type": "SB_LUT4",
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+          "attributes": {
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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@@ -30217,10 +29405,35 @@
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@@ -30824,9 +30037,9 @@
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@@ -30848,10 +30061,10 @@
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@@ -30874,9 +30087,9 @@
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@@ -30895,10 +30108,10 @@
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@@ -30920,10 +30133,10 @@
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@@ -30944,11 +30157,11 @@
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@@ -30969,11 +30182,11 @@
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@@ -30994,11 +30207,11 @@
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@@ -31020,10 +30233,10 @@
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@@ -31045,10 +30258,10 @@
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@@ -31070,10 +30283,10 @@
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@@ -31095,10 +30308,10 @@
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@@ -31116,9 +30329,9 @@
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@@ -31136,9 +30349,9 @@
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@@ -31161,9 +30374,9 @@
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@@ -31182,10 +30395,10 @@
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@@ -31204,10 +30417,10 @@
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@@ -31251,10 +30464,10 @@
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@@ -31278,8 +30491,8 @@
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@@ -31302,9 +30515,9 @@
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@@ -31322,10 +30535,10 @@
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@@ -31919,9 +31132,9 @@
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@@ -32158,11 +31371,11 @@
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@@ -32184,10 +31397,135 @@
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@@ -32207,11 +31545,11 @@
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@@ -32233,160 +31571,10 @@
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@@ -34236,7 +33827,7 @@
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@@ -34260,7 +33851,7 @@
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@@ -34320,38 +33887,13 @@
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@@ -34359,7 +33901,7 @@
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@@ -34371,18 +33913,18 @@
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@@ -34391,13 +33933,34 @@
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@@ -34405,7 +33968,7 @@
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@@ -34417,18 +33980,43 @@
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@@ -34437,10 +34025,80 @@
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@@ -34450,7 +34108,7 @@
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@@ -34460,14 +34118,38 @@
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@@ -34475,7 +34157,7 @@
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@@ -34487,18 +34169,18 @@
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@@ -34507,20 +34189,66 @@
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@@ -36023,9 +36229,9 @@
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@@ -36037,6 +36243,30 @@
             "src": "top.v:42.11-42.19"
           }
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+          "attributes": {
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+        "i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 54, 55, 56, 57 ],
+          "attributes": {
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+          "attributes": {
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@@ -36044,14 +36274,6 @@
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@@ -36082,9 +36304,9 @@
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+          "bits": [ 46 ],
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+            "src": "top.v:87.12-87.18"
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         "i_rst_b": {
@@ -36096,57 +36318,57 @@
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           "hide_name": 0,
-          "bits": [ 64 ],
+          "bits": [ 68 ],
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         "i_sck": {
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-          "bits": [ 44 ],
+          "bits": [ 47 ],
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           "hide_name": 0,
-          "bits": [ 31 ],
+          "bits": [ 33 ],
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+            "src": "top.v:77.11-77.19"
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         "i_smi_a3": {
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-          "bits": [ 32 ],
+          "bits": [ 34 ],
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+            "src": "top.v:78.11-78.19"
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+          "bits": [ 35 ],
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+            "src": "top.v:80.11-80.23"
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         "i_smi_swe_srw": {
           "hide_name": 0,
-          "bits": [ 24 ],
+          "bits": [ 36 ],
           "attributes": {
-            "src": "top.v:79.11-79.24"
+            "src": "top.v:81.11-81.24"
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         "i_ss": {
           "hide_name": 0,
-          "bits": [ 45 ],
+          "bits": [ 48 ],
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+            "src": "top.v:89.12-89.16"
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         "int_miso": {
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+          "bits": [ 370 ],
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@@ -36167,7 +36389,7 @@
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@@ -36175,13 +36397,13 @@
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+          "bits": [ 71 ],
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         "io_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ],
+          "bits": [ 140, 138, 89, 136, 134, 133, 132, 130 ],
           "attributes": {
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             "src": "io_ctrl.v:7.22-7.31"
@@ -36189,7 +36411,7 @@
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@@ -36197,7 +36419,7 @@
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           "hide_name": 0,
-          "bits": [ 56, 97, 208, 207, 206 ],
+          "bits": [ 55, 54, 60, 59, 58 ],
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             "src": "io_ctrl.v:6.22-6.27"
@@ -36205,7 +36427,7 @@
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         "io_ctrl_ins.i_load_cmd": {
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@@ -36221,7 +36443,7 @@
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         "io_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
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@@ -36229,7 +36451,7 @@
         },
         "io_ctrl_ins.led0_state": {
           "hide_name": 0,
-          "bits": [ 29 ],
+          "bits": [ 31 ],
           "attributes": {
             "hdlname": "io_ctrl_ins led0_state",
             "src": "io_ctrl.v:73.17-73.27"
@@ -36237,7 +36459,7 @@
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         "io_ctrl_ins.led1_state": {
           "hide_name": 0,
-          "bits": [ 30 ],
+          "bits": [ 32 ],
           "attributes": {
             "hdlname": "io_ctrl_ins led1_state",
             "src": "io_ctrl.v:74.17-74.27"
@@ -36253,7 +36475,7 @@
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         "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 73 ],
+          "bits": [ 77 ],
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@@ -36267,53 +36489,21 @@
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         "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": {
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-          "bits": [ 78 ],
+          "bits": [ 82 ],
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 82, 51, 81 ],
+          "bits": [ 87, 51, 86 ],
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O": {
+        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O": {
           "hide_name": 0,
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E": {
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-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 3, 88, 93 ],
+          "bits": [ 91, 102, 88 ],
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@@ -36321,7 +36511,7 @@
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           "hide_name": 0,
-          "bits": [ 100 ],
+          "bits": [ 93 ],
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@@ -36329,13 +36519,13 @@
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-          "bits": [ 99 ],
+          "bits": [ 92 ],
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         "io_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 119, 106, 114, 109, 129, 126, 124, 122 ],
+          "bits": [ 112, 98, 106, 101, 123, 121, 119, 117 ],
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             "src": "io_ctrl.v:8.22-8.32"
@@ -36343,25 +36533,33 @@
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         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D": {
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-          "bits": [ 108 ],
+          "bits": [ 100 ],
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+        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 80, 102, 103 ],
+          "attributes": {
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           "hide_name": 0,
-          "bits": [ 112 ],
+          "bits": [ 104 ],
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         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E": {
           "hide_name": 0,
-          "bits": [ 113 ],
+          "bits": [ 105 ],
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         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R": {
           "hide_name": 0,
-          "bits": [ 54, 115 ],
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@@ -36369,63 +36567,71 @@
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           "hide_name": 0,
-          "bits": [ 107 ],
+          "bits": [ 99 ],
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         "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": {
           "hide_name": 0,
-          "bits": [ 118 ],
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         "io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D": {
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-          "bits": [ 123 ],
+          "bits": [ 118 ],
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         "io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 125 ],
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-        "io_ctrl_ins.o_data_out_SB_DFFE_Q_D": {
+        "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3": {
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-        "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1": {
-          "hide_name": 0,
-          "bits": [ 69, 130, 98, 57 ],
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-        "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O": {
+        "io_ctrl_ins.o_data_out_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 97, 56, 105 ],
+          "bits": [ 115 ],
+          "attributes": {
+          }
+        },
+        "io_ctrl_ins.o_data_out_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 116 ],
+          "attributes": {
+          }
+        },
+        "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 128, 126 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O": {
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+          "bits": [ 54, 55, 97 ],
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@@ -36433,7 +36639,7 @@
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         "io_ctrl_ins.o_led0": {
           "hide_name": 0,
-          "bits": [ 29 ],
+          "bits": [ 31 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_led0",
             "src": "io_ctrl.v:16.22-16.28"
@@ -36441,7 +36647,7 @@
         },
         "io_ctrl_ins.o_led1": {
           "hide_name": 0,
-          "bits": [ 30 ],
+          "bits": [ 32 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_led1",
             "src": "io_ctrl.v:17.22-17.28"
@@ -36465,7 +36671,7 @@
         },
         "io_ctrl_ins.o_pmod": {
           "hide_name": 0,
-          "bits": [ 102, 142, 80, 141 ],
+          "bits": [ 23, 24, 25, 26 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_pmod",
             "src": "io_ctrl.v:18.22-18.28"
@@ -36529,7 +36735,7 @@
         },
         "io_ctrl_ins.pmod_dir_state": {
           "hide_name": 0,
-          "bits": [ 139, 138, 82, 137, 53, 136, 50, 133 ],
+          "bits": [ 141, 139, 87, 137, 135, 61, 63, 50 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_dir_state",
             "src": "io_ctrl.v:75.17-75.31"
@@ -36537,7 +36743,7 @@
         },
         "io_ctrl_ins.pmod_state": {
           "hide_name": 0,
-          "bits": [ 102, 142, 80, 141 ],
+          "bits": [ 23, 24, 25, 26 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_state",
             "src": "io_ctrl.v:76.17-76.27"
@@ -36545,7 +36751,7 @@
         },
         "io_ctrl_ins.pmod_state_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 140 ],
+          "bits": [ 142 ],
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@@ -36559,19 +36765,19 @@
         },
         "io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O": {
           "hide_name": 0,
-          "bits": [ 144 ],
+          "bits": [ 145 ],
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         "io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 132 ],
+          "bits": [ 131 ],
           "attributes": {
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         },
         "io_ctrl_ins.rf_pin_state": {
           "hide_name": 0,
-          "bits": [ 101, 75, 79, 149, 148, 147, 146, 145 ],
+          "bits": [ 94, 79, 83, 151, 150, 149, 148, 147 ],
           "attributes": {
             "hdlname": "io_ctrl_ins rf_pin_state",
             "src": "io_ctrl.v:77.17-77.29"
@@ -36587,13 +36793,13 @@
         },
         "io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 150 ],
+          "bits": [ 152 ],
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           }
         },
         "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3": {
           "hide_name": 0,
-          "bits": [ 5, 58, 52 ],
+          "bits": [ 5, 144, 64 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36609,13 +36815,13 @@
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 152 ],
+          "bits": [ 154 ],
           "attributes": {
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         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 145, 77, 151 ],
+          "bits": [ 148, 81, 153 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36623,18 +36829,10 @@
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 74 ],
+          "bits": [ 78 ],
           "attributes": {
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-        "io_ctrl_ins.rx_h_state_SB_LUT4_I0_O": {
-          "hide_name": 0,
-          "bits": [ 22, 47, 48 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        },
         "io_ctrl_ins.tr_vc_1_b_state": {
           "hide_name": 0,
           "bits": [ 7 ],
@@ -36645,10 +36843,50 @@
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         "io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 153 ],
+          "bits": [ 155 ],
           "attributes": {
           }
         },
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 84, 126, 127 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E": {
+          "hide_name": 0,
+          "bits": [ 90 ],
+          "attributes": {
+            "defaultvalue": "1",
+            "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
+          }
+        },
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q": {
+          "hide_name": 0,
+          "bits": [ 151, 80, 84, 81 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q": {
+          "hide_name": 0,
+          "bits": [ 108, 113 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O": {
+          "hide_name": 0,
+          "bits": [ 108, 157 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "io_ctrl_ins.tr_vc_1_state": {
           "hide_name": 0,
           "bits": [ 6 ],
@@ -36659,21 +36897,21 @@
         },
         "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 155 ],
+          "bits": [ 158 ],
           "attributes": {
           }
         },
-        "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3": {
+        "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 147, 77, 154 ],
+          "bits": [ 150, 80, 156, 81 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3": {
           "hide_name": 0,
-          "bits": [ 20, 47, 127 ],
+          "bits": [ 6, 144, 62 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36689,49 +36927,62 @@
         },
         "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 156 ],
+          "bits": [ 159 ],
           "attributes": {
           }
         },
-        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 18, 54, 110, 111 ],
+          "bits": [ 137, 51, 161, 160 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "io_pmod": {
+        "io_pmod_in": {
           "hide_name": 0,
-          "bits": [ 23, "0", "0", 24, 25, 26, 27, 28 ],
+          "bits": [ 27, 28, 29, 30 ],
           "attributes": {
-            "src": "top.v:43.17-43.24"
+            "src": "top.v:45.17-45.27"
+          }
+        },
+        "io_pmod_out": {
+          "hide_name": 0,
+          "bits": [ 23, 24, 25, 26 ],
+          "attributes": {
+            "src": "top.v:44.18-44.29"
           }
         },
         "io_smi_data": {
           "hide_name": 0,
-          "bits": [ 34, 35, 36, 37, 38, 39, 40, 41 ],
+          "bits": [ 37, 38, 39, 40, 41, 42, 43, 44 ],
+          "attributes": {
+            "src": "top.v:82.17-82.28"
+          }
+        },
+        "iq_tx_n_OUTPUT_CLK": {
+          "hide_name": 0,
+          "bits": [ 167 ],
           "attributes": {
-            "src": "top.v:80.17-80.28"
           }
         },
         "lvds_clock": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
-            "src": "top.v:253.8-253.18"
+            "src": "top.v:249.8-249.18"
           }
         },
         "lvds_clock_buf": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
-            "src": "top.v:254.8-254.22"
+            "src": "top.v:250.8-250.22"
           }
         },
         "lvds_rx_09_inst.i_ddr_clk": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_clk",
             "src": "lvds_rx.v:3.17-3.26"
@@ -36739,7 +36990,7 @@
         },
         "lvds_rx_09_inst.i_ddr_data": {
           "hide_name": 0,
-          "bits": [ 159, 158 ],
+          "bits": [ 163, 162 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_data",
             "src": "lvds_rx.v:4.17-4.27"
@@ -36747,7 +36998,7 @@
         },
         "lvds_rx_09_inst.i_fifo_full": {
           "hide_name": 0,
-          "bits": [ 485 ],
+          "bits": [ 424 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_fifo_full",
             "src": "lvds_rx.v:6.23-6.34"
@@ -36763,7 +37014,7 @@
         },
         "lvds_rx_09_inst.i_sync_input": {
           "hide_name": 0,
-          "bits": [ 162 ],
+          "bits": [ 168 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_sync_input",
             "src": "lvds_rx.v:10.23-10.35"
@@ -36771,71 +37022,13 @@
         },
         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E": {
           "hide_name": 0,
-          "bits": [ 163, 165 ],
+          "bits": [ 169, 171 ],
           "attributes": {
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         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O": {
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-          "bits": [ 166 ],
-          "attributes": {
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-            "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
-          }
-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q": {
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-          "bits": [ 175, 178, 173, 170 ],
-          "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D": {
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-          "bits": [ 174 ],
-          "attributes": {
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-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1": {
-          "hide_name": 0,
-          "bits": [ 170, 176, "1", 177 ],
-          "attributes": {
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-            "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 177 ],
-          "attributes": {
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-            "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:8.8-8.10"
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D": {
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-          "bits": [ 179 ],
-          "attributes": {
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-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D": {
-          "hide_name": 0,
-          "bits": [ 171 ],
-          "attributes": {
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 180 ],
-          "attributes": {
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-            "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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-        },
-        "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E": {
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@@ -36845,7 +37038,7 @@
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         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D": {
           "hide_name": 0,
-          "bits": [ 169, 167 ],
+          "bits": [ 175, 173 ],
           "attributes": {
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             "src": "lvds_rx.v:0.0-0.0|lvds_rx.v:43.7-82.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
@@ -36853,7 +37046,7 @@
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         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q": {
           "hide_name": 0,
-          "bits": [ 168, 170, 181, 165 ],
+          "bits": [ 174, 176 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36861,7 +37054,7 @@
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         "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q": {
           "hide_name": 0,
-          "bits": [ 159, 164, 168, 165 ],
+          "bits": [ 163, 170, 174, 171 ],
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36869,7 +37062,7 @@
         },
         "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 28, 184, 185 ],
+          "bits": [ 30, 180, 181 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -36877,29 +37070,15 @@
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         "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E": {
           "hide_name": 0,
-          "bits": [ 186 ],
+          "bits": [ 182 ],
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q": {
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O": {
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         "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 97, 56, 192 ],
+          "bits": [ 54, 55, 184 ],
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@@ -36907,23 +37086,15 @@
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           "hide_name": 0,
-          "bits": [ 188 ],
+          "bits": [ 183 ],
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         "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q": {
           "hide_name": 0,
-          "bits": [ 195, 190 ],
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@@ -36931,7 +37102,7 @@
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         "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q": {
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-          "bits": [ 196, 190 ],
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@@ -36939,63 +37110,7 @@
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O": {
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O": {
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O": {
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-        "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 185, 190 ],
+          "bits": [ 185, 386 ],
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@@ -37003,7 +37118,7 @@
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           "hide_name": 0,
-          "bits": [ 272, 237, 212, 214, 239, 261, 263, 265, 267, 269, 217, 220, 216, 219, 222, 224, 226, 228, 230, 232, 234, 236, 241, 243, 245, 247, 249, 251, 253, 255, 257, 259 ],
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             "src": "lvds_rx.v:9.23-9.34"
@@ -37011,199 +37126,199 @@
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D": {
           "hide_name": 0,
-          "bits": [ 215 ],
+          "bits": [ 195 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D": {
           "hide_name": 0,
-          "bits": [ 218 ],
+          "bits": [ 198 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D": {
           "hide_name": 0,
-          "bits": [ 223 ],
+          "bits": [ 203 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D": {
           "hide_name": 0,
-          "bits": [ 225 ],
+          "bits": [ 205 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 264 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D": {
           "hide_name": 0,
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D": {
           "hide_name": 0,
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+          "bits": [ 251 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 210 ],
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 182 ],
+          "bits": [ 178 ],
           "attributes": {
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         "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 183 ],
+          "bits": [ 179 ],
           "attributes": {
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         "lvds_rx_09_inst.o_fifo_write_clk": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_write_clk",
             "src": "lvds_rx.v:7.23-7.39"
@@ -37211,7 +37326,7 @@
         },
         "lvds_rx_24_inst.i_ddr_clk": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_ddr_clk",
             "src": "lvds_rx.v:3.17-3.26"
@@ -37219,7 +37334,7 @@
         },
         "lvds_rx_24_inst.i_fifo_full": {
           "hide_name": 0,
-          "bits": [ 485 ],
+          "bits": [ 424 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_fifo_full",
             "src": "lvds_rx.v:6.23-6.34"
@@ -37235,7 +37350,7 @@
         },
         "lvds_rx_24_inst.i_sync_input": {
           "hide_name": 0,
-          "bits": [ 273 ],
+          "bits": [ 253 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_sync_input",
             "src": "lvds_rx.v:10.23-10.35"
@@ -37243,7 +37358,7 @@
         },
         "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E": {
           "hide_name": 0,
-          "bits": [ 274, 276 ],
+          "bits": [ 254, 256 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37251,23 +37366,15 @@
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         "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 277 ],
+          "bits": [ 257 ],
           "attributes": {
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             "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
           }
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-        "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q": {
-          "hide_name": 0,
-          "bits": [ 281 ],
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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         "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D": {
           "hide_name": 0,
-          "bits": [ 280, 278 ],
+          "bits": [ 260, 258 ],
           "attributes": {
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             "src": "lvds_rx.v:0.0-0.0|lvds_rx.v:43.7-82.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
@@ -37275,15 +37382,37 @@
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           "hide_name": 0,
-          "bits": [ 279, 281, 283 ],
+          "bits": [ 166, 165, 259, 261 ],
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 261, 263 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 264 ],
+          "attributes": {
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+        },
         "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q": {
           "hide_name": 0,
-          "bits": [ 161, 275, 284 ],
+          "bits": [ 166, 255, 265 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 29, 267, 268 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37291,7 +37420,7 @@
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           "hide_name": 0,
-          "bits": [ 348, 313, 288, 290, 315, 337, 339, 341, 343, 345, 293, 296, 292, 295, 298, 300, 302, 304, 306, 308, 310, 312, 317, 319, 321, 323, 325, 327, 329, 331, 333, 335 ],
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             "hdlname": "lvds_rx_24_inst o_fifo_data",
             "src": "lvds_rx.v:9.23-9.34"
@@ -37299,210 +37428,218 @@
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-          "bits": [ 291 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D": {
           "hide_name": 0,
-          "bits": [ 294 ],
+          "bits": [ 276 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D": {
           "hide_name": 0,
-          "bits": [ 297 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D": {
           "hide_name": 0,
-          "bits": [ 299 ],
+          "bits": [ 281 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D": {
           "hide_name": 0,
-          "bits": [ 301 ],
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           "hide_name": 0,
-          "bits": [ 303 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D": {
           "hide_name": 0,
-          "bits": [ 309 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 289 ],
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           "hide_name": 0,
-          "bits": [ 316 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D": {
           "hide_name": 0,
-          "bits": [ 318 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D": {
           "hide_name": 0,
-          "bits": [ 320 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D": {
           "hide_name": 0,
-          "bits": [ 322 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D": {
           "hide_name": 0,
-          "bits": [ 324 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D": {
           "hide_name": 0,
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+          "bits": [ 314 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D": {
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D": {
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 336 ],
+          "bits": [ 318 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 340 ],
+          "bits": [ 322 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 342 ],
+          "bits": [ 324 ],
           "attributes": {
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         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 344 ],
+          "bits": [ 326 ],
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         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D": {
           "hide_name": 0,
-          "bits": [ 346 ],
+          "bits": [ 328 ],
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         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D": {
           "hide_name": 0,
-          "bits": [ 347 ],
+          "bits": [ 329 ],
           "attributes": {
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         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 286 ],
+          "bits": [ 269 ],
           "attributes": {
           }
         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 282 ],
+          "bits": [ 262 ],
           "attributes": {
           }
         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 285 ],
+          "bits": [ 266 ],
           "attributes": {
           }
         },
         "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 349 ],
+          "bits": [ 331 ],
           "attributes": {
           }
         },
         "lvds_rx_24_inst.o_fifo_write_clk": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst o_fifo_write_clk",
             "src": "lvds_rx.v:7.23-7.39"
           }
         },
+        "lvds_tx_inst.i_ddr_clk": {
+          "hide_name": 0,
+          "bits": [ 164 ],
+          "attributes": {
+            "hdlname": "lvds_tx_inst i_ddr_clk",
+            "src": "lvds_tx.v:3.21-3.30"
+          }
+        },
         "lvds_tx_inst.i_debug_lb": {
           "hide_name": 0,
           "bits": [ "x" ],
@@ -37511,14 +37648,6 @@
             "src": "lvds_tx.v:13.21-13.31"
           }
         },
-        "lvds_tx_inst.i_fifo_empty": {
-          "hide_name": 0,
-          "bits": [ 352 ],
-          "attributes": {
-            "hdlname": "lvds_tx_inst i_fifo_empty",
-            "src": "lvds_tx.v:6.21-6.33"
-          }
-        },
         "lvds_tx_inst.i_rst_b": {
           "hide_name": 0,
           "bits": [ 3 ],
@@ -37545,12 +37674,20 @@
         },
         "lvds_tx_inst.o_fifo_pull": {
           "hide_name": 0,
-          "bits": [ 351 ],
+          "bits": [ 333 ],
           "attributes": {
             "hdlname": "lvds_tx_inst o_fifo_pull",
             "src": "lvds_tx.v:8.21-8.32"
           }
         },
+        "lvds_tx_inst.o_fifo_read_clk": {
+          "hide_name": 0,
+          "bits": [ 164 ],
+          "attributes": {
+            "hdlname": "lvds_tx_inst o_fifo_read_clk",
+            "src": "lvds_tx.v:7.21-7.36"
+          }
+        },
         "lvds_tx_inst.o_sync_state_bit": {
           "hide_name": 0,
           "bits": [ "0" ],
@@ -37577,21 +37714,37 @@
         },
         "lvds_tx_inst.r_pulled": {
           "hide_name": 0,
-          "bits": [ 351 ],
+          "bits": [ 333 ],
           "attributes": {
             "hdlname": "lvds_tx_inst r_pulled",
             "src": "lvds_tx.v:33.9-33.17"
           }
         },
-        "lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D": {
+        "lvds_tx_inst.r_pulled_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 350 ],
+          "bits": [ 333, 339, 340, 332 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "lvds_tx_inst.r_pulled_SB_DFFESR_Q_D_SB_DFFNSR_Q_D": {
+          "hide_name": 0,
+          "bits": [ 334 ],
+          "attributes": {
+          }
+        },
+        "lvds_tx_inst.r_pulled_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 363, 1081, 341, 346 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "lvds_tx_inst.r_pulled_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 356, 355, 357 ],
+          "bits": [ 349, 348, 350 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37599,47 +37752,7 @@
         },
         "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 363, 367, 358, 372 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 359, 360, 361, 362 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3": {
-          "hide_name": 0,
-          "bits": [ 374, 377, 368, 378 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2": {
-          "hide_name": 0,
-          "bits": [ 382, 383 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3": {
-          "hide_name": 0,
-          "bits": [ 385, 386, 387, 388 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 373, 374, 375, 376 ],
+          "bits": [ 335, 336, 337, 338 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37647,7 +37760,7 @@
         },
         "lvds_tx_inst.r_pulled_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 397 ],
+          "bits": [ 368 ],
           "attributes": {
           }
         },
@@ -37689,14 +37802,22 @@
         },
         "o_led0": {
           "hide_name": 0,
-          "bits": [ 29 ],
+          "bits": [ 31 ],
           "attributes": {
-            "src": "top.v:44.12-44.18"
+            "src": "top.v:46.12-46.18"
           }
         },
         "o_led0_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 90, 96, 103, 120 ],
+          "bits": [ 113, 102, 95, 114 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 54, 55, 57 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37704,14 +37825,14 @@
         },
         "o_led1": {
           "hide_name": 0,
-          "bits": [ 30 ],
+          "bits": [ 32 ],
           "attributes": {
-            "src": "top.v:45.12-45.18"
+            "src": "top.v:47.12-47.18"
           }
         },
         "o_led1_SB_DFFER_Q_E": {
           "hide_name": 0,
-          "bits": [ 398 ],
+          "bits": [ 369 ],
           "attributes": {
             "defaultvalue": "1",
             "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
@@ -37719,7 +37840,15 @@
         },
         "o_led1_SB_LUT4_I1_I2": {
           "hide_name": 0,
-          "bits": [ 19, 53, 51, 54 ],
+          "bits": [ 7, 135, 51, 144 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "o_led1_SB_LUT4_I1_I3": {
+          "hide_name": 0,
+          "bits": [ 141, 31, 51, 124 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37727,7 +37856,15 @@
         },
         "o_led1_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 88, 96, 116, 117 ],
+          "bits": [ 108, 102, 109, 110 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 55, 85 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37735,14 +37872,14 @@
         },
         "o_miso": {
           "hide_name": 0,
-          "bits": [ 46 ],
+          "bits": [ 49 ],
           "attributes": {
-            "src": "top.v:88.12-88.18"
+            "src": "top.v:90.12-90.18"
           }
         },
         "o_miso_$_TBUF__Y_E": {
           "hide_name": 0,
-          "bits": [ 65 ],
+          "bits": [ 69 ],
           "attributes": {
           }
         },
@@ -37790,16 +37927,16 @@
         },
         "o_smi_read_req": {
           "hide_name": 0,
-          "bits": [ 42 ],
+          "bits": [ 45 ],
           "attributes": {
-            "src": "top.v:82.12-82.26"
+            "src": "top.v:84.12-84.26"
           }
         },
         "o_smi_write_req": {
           "hide_name": 0,
-          "bits": [ "z" ],
+          "bits": [ 36 ],
           "attributes": {
-            "src": "top.v:81.12-81.27"
+            "src": "top.v:83.12-83.27"
           }
         },
         "o_tr_vc1": {
@@ -37825,33 +37962,33 @@
         },
         "r_counter": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
-            "src": "top.v:95.14-95.23"
+            "src": "top.v:97.14-97.23"
           }
         },
         "r_counter_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 403 ],
+          "bits": [ 374 ],
           "attributes": {
           }
         },
         "r_tx_data": {
           "hide_name": 0,
-          "bits": [ 436, 431, 424, 421, 418, 414, 408, 406 ],
+          "bits": [ 413, 406, 402, 398, 394, 388, 379, 377 ],
           "attributes": {
-            "src": "top.v:100.14-100.23"
+            "src": "top.v:102.14-102.23"
           }
         },
         "r_tx_data_SB_DFFE_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 407 ],
+          "bits": [ 378 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 124, 409, 410, 411 ],
+          "bits": [ 119, 380, 381, 382 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37859,25 +37996,47 @@
         },
         "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D": {
           "hide_name": 0,
-          "bits": [ 412 ],
+          "bits": [ 383 ],
           "attributes": {
           }
         },
+        "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 385, 386 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "r_tx_data_SB_DFFE_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 413 ],
+          "bits": [ 387 ],
+          "attributes": {
+          }
+        },
+        "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 389, 381, 390 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D": {
+          "hide_name": 0,
+          "bits": [ 391 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 417 ],
+          "bits": [ 393 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 129, 419, 410, 411 ],
+          "bits": [ 123, 395, 381, 382 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37885,19 +38044,19 @@
         },
         "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D": {
           "hide_name": 0,
-          "bits": [ 209 ],
+          "bits": [ 396 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 420 ],
+          "bits": [ 397 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 109, 422, 410, 411 ],
+          "bits": [ 101, 399, 381, 382 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37905,27 +38064,19 @@
         },
         "r_tx_data_SB_DFFE_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 423 ],
+          "bits": [ 401 ],
           "attributes": {
           }
         },
-        "r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 425, 410, 426, 427 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "r_tx_data_SB_DFFE_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 430 ],
+          "bits": [ 405 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 432, 410, 433 ],
+          "bits": [ 407, 381, 408 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37933,27 +38084,21 @@
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         "r_tx_data_SB_DFFE_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 435 ],
+          "bits": [ 412 ],
           "attributes": {
           }
         },
-        "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0": {
+        "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 437, 410, 426, 438 ],
+          "bits": [ 414, 381, 415 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D": {
+        "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 202, 205, 204, 203 ],
-          "attributes": {
-          }
-        },
-        "r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2": {
-          "hide_name": 0,
-          "bits": [ 439, 119, 429, 411 ],
+          "bits": [ 417, 411, 418 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37961,13 +38106,13 @@
         },
         "r_tx_data_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 404 ],
+          "bits": [ 375 ],
           "attributes": {
           }
         },
         "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 442, 410, 443 ],
+          "bits": [ 419, 381, 420 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -37975,99 +38120,21 @@
         },
         "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D": {
           "hide_name": 0,
-          "bits": [ 444 ],
+          "bits": [ 421 ],
           "attributes": {
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         "r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 445, 190 ],
+          "bits": [ 422, 386 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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@@ -38731,7 +38936,7 @@
         },
         "rx_fifo.rd_data_o": {
           "hide_name": 0,
-          "bits": [ 626, 634, 630, 638, 646, 654, 650, 658, 666, 674, 670, 678, 686, 694, 690, 698, 536, 544, 540, 548, 566, 574, 570, 578, 586, 594, 590, 598, 606, 614, 610, 618 ],
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           "attributes": {
             "hdlname": "rx_fifo rd_data_o",
             "src": "complex_fifo.v:14.32-14.41"
@@ -38747,165 +38952,21 @@
         },
         "rx_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 559, 512, 551, 552, 553, 554, 555, 556, 557, 558 ],
+          "bits": [ 538, 476, 475, 478, 480, 463, 461, 459, 457, 454 ],
           "attributes": {
             "hdlname": "rx_fifo wr_addr",
-            "src": "complex_fifo.v:23.23-23.30"
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O": {
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2": {
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2": {
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3": {
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": {
-          "hide_name": 0,
-          "bits": [ 508, 509, 510, 511 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+            "src": "complex_fifo.v:20.23-20.30"
           }
         },
         "rx_fifo.wr_addr_SB_DFFESR_Q_8_D": {
           "hide_name": 0,
-          "bits": [ 792 ],
+          "bits": [ 762 ],
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 762, 761 ],
+          "bits": [ 755, 754 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -38913,23 +38974,23 @@
         },
         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 793 ],
+          "bits": [ 763 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
           "hide_name": 0,
-          "bits": [ 794 ],
+          "bits": [ 764 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 755, 761, 492, 795 ],
+          "bits": [ 464, 754, 431, 765 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -38937,55 +38998,71 @@
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 796 ],
+          "bits": [ 766 ],
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             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 797 ],
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             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 798 ],
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           "hide_name": 0,
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+        "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O": {
+          "hide_name": 0,
+          "bits": [ 475, 484, 430, 485 ],
+          "attributes": {
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         "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
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@@ -38993,7 +39070,7 @@
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@@ -39001,35 +39078,29 @@
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           "hide_name": 0,
-          "bits": [ 763, 762 ],
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        "rx_fifo.wr_addr_SB_DFFESR_Q_E": {
-          "hide_name": 0,
-          "bits": [ 564 ],
-          "attributes": {
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         "rx_fifo.wr_addr_gray": {
           "hide_name": 0,
-          "bits": [ 818, 816, 815, 813, 811, 809, 807, 806, 805, 558 ],
+          "bits": [ 788, 786, 785, 783, 781, 779, 777, 776, 775, 454 ],
           "attributes": {
             "hdlname": "rx_fifo wr_addr_gray",
-            "src": "complex_fifo.v:24.23-24.35"
+            "src": "complex_fifo.v:21.23-21.35"
           }
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 804 ],
+          "bits": [ 774 ],
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         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 757, 808 ],
+          "bits": [ 483, 778 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39037,7 +39108,7 @@
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         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 500, 501, 502, 503 ],
+          "bits": [ 439, 440, 441, 442 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39045,7 +39116,7 @@
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 755, 810, 761, 492 ],
+          "bits": [ 464, 780, 754, 431 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39053,7 +39124,7 @@
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 756, 758, 802, 803 ],
+          "bits": [ 447, 469, 772, 773 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39061,7 +39132,7 @@
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 759, 812 ],
+          "bits": [ 472, 782 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39069,7 +39140,7 @@
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 496, 497, 498, 499 ],
+          "bits": [ 435, 436, 437, 438 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39077,35 +39148,43 @@
         },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 814 ],
+          "bits": [ 784 ],
           "attributes": {
           }
         },
+        "rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D": {
+          "hide_name": 0,
+          "bits": [ 484, 486, 487, 488 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D": {
           "hide_name": 0,
-          "bits": [ 817 ],
+          "bits": [ 787 ],
           "attributes": {
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         },
         "rx_fifo.wr_addr_gray_rd": {
           "hide_name": 0,
-          "bits": [ 828, 827, 826, 825, 824, 823, 822, 821, 820, 819 ],
+          "bits": [ 798, 797, 796, 795, 794, 793, 792, 791, 790, 789 ],
           "attributes": {
             "hdlname": "rx_fifo wr_addr_gray_rd",
-            "src": "complex_fifo.v:25.23-25.38"
+            "src": "complex_fifo.v:22.23-22.38"
           }
         },
         "rx_fifo.wr_addr_gray_rd_r": {
           "hide_name": 0,
-          "bits": [ 451, 478, 457, 483, 465, 481, 470, 473, 460, 458 ],
+          "bits": [ 740, 734, 699, 730, 692, 723, 691, 714, 741, 739 ],
           "attributes": {
             "hdlname": "rx_fifo wr_addr_gray_rd_r",
-            "src": "complex_fifo.v:26.23-26.40"
+            "src": "complex_fifo.v:23.23-23.40"
           }
         },
         "rx_fifo.wr_clk_i": {
           "hide_name": 0,
-          "bits": [ 157 ],
+          "bits": [ 164 ],
           "attributes": {
             "hdlname": "rx_fifo wr_clk_i",
             "src": "complex_fifo.v:7.28-7.36"
@@ -39121,7 +39200,7 @@
         },
         "smi_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 441 ],
+          "bits": [ 495 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_cs",
             "src": "smi_ctrl.v:9.25-9.29"
@@ -39129,13 +39208,13 @@
         },
         "smi_ctrl_ins.i_cs_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 829 ],
+          "bits": [ 799 ],
           "attributes": {
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         },
         "smi_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ],
+          "bits": [ 140, 138, 89, 136, 134, 133, 132, 130 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_data_in",
             "src": "smi_ctrl.v:7.25-7.34"
@@ -39143,7 +39222,7 @@
         },
         "smi_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 95 ],
+          "bits": [ 129 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fetch_cmd",
             "src": "smi_ctrl.v:10.25-10.36"
@@ -39151,7 +39230,7 @@
         },
         "smi_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 56, 97, 208, 207, 206 ],
+          "bits": [ 55, 54, 60, 59, 58 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_ioc",
             "src": "smi_ctrl.v:6.25-6.30"
@@ -39159,7 +39238,7 @@
         },
         "smi_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 94 ],
+          "bits": [ 146 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_load_cmd",
             "src": "smi_ctrl.v:11.25-11.35"
@@ -39173,17 +39252,9 @@
             "src": "smi_ctrl.v:3.25-3.32"
           }
         },
-        "smi_ctrl_ins.i_rx_fifo_empty": {
-          "hide_name": 0,
-          "bits": [ 401 ],
-          "attributes": {
-            "hdlname": "smi_ctrl_ins i_rx_fifo_empty",
-            "src": "smi_ctrl.v:16.25-16.40"
-          }
-        },
         "smi_ctrl_ins.i_rx_fifo_pulled_data": {
           "hide_name": 0,
-          "bits": [ 626, 634, 630, 638, 646, 654, 650, 658, 666, 674, 670, 678, 686, 694, 690, 698, 536, 544, 540, 548, 566, 574, 570, 578, 586, 594, 590, 598, 606, 614, 610, 618 ],
+          "bits": [ 605, 613, 609, 617, 625, 633, 629, 637, 645, 653, 649, 657, 665, 673, 669, 677, 523, 531, 527, 535, 545, 553, 549, 557, 565, 573, 569, 577, 585, 593, 589, 597 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_rx_fifo_pulled_data",
             "src": "smi_ctrl.v:15.25-15.46"
@@ -39191,7 +39262,7 @@
         },
         "smi_ctrl_ins.i_smi_data_in": {
           "hide_name": 0,
-          "bits": [ 979, 980, 981, 982, 983, 984, 985, 969 ],
+          "bits": [ 939, 940, 941, 942, 943, 944, 945, 929 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_smi_data_in",
             "src": "smi_ctrl.v:27.25-27.38",
@@ -39200,7 +39271,7 @@
         },
         "smi_ctrl_ins.i_smi_soe_se": {
           "hide_name": 0,
-          "bits": [ 33 ],
+          "bits": [ 35 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_smi_soe_se",
             "src": "smi_ctrl.v:24.25-24.37"
@@ -39208,23 +39279,15 @@
         },
         "smi_ctrl_ins.i_smi_swe_srw": {
           "hide_name": 0,
-          "bits": [ 24 ],
+          "bits": [ 36 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_smi_swe_srw",
             "src": "smi_ctrl.v:25.25-25.38"
           }
         },
-        "smi_ctrl_ins.i_smi_test": {
-          "hide_name": 0,
-          "bits": [ "0" ],
-          "attributes": {
-            "hdlname": "smi_ctrl_ins i_smi_test",
-            "src": "smi_ctrl.v:30.25-30.35"
-          }
-        },
         "smi_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_sys_clk",
             "src": "smi_ctrl.v:4.25-4.34"
@@ -39232,7 +39295,7 @@
         },
         "smi_ctrl_ins.i_tx_fifo_full": {
           "hide_name": 0,
-          "bits": [ 400 ],
+          "bits": [ 371 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_tx_fifo_full",
             "src": "smi_ctrl.v:20.25-20.39"
@@ -39240,21 +39303,21 @@
         },
         "smi_ctrl_ins.int_cnt_rx": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", 62, 61 ],
+          "bits": [ "0", "0", "0", 66, 65 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins int_cnt_rx",
-            "src": "smi_ctrl.v:110.15-110.25"
+            "src": "smi_ctrl.v:108.15-108.25"
           }
         },
         "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 832 ],
+          "bits": [ 802 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 831 ],
+          "bits": [ 801 ],
           "attributes": {
           }
         },
@@ -39263,26 +39326,32 @@
           "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x" ],
           "attributes": {
             "hdlname": "smi_ctrl_ins int_cnt_tx",
-            "src": "smi_ctrl.v:174.16-174.26"
+            "src": "smi_ctrl.v:162.16-162.26"
           }
         },
         "smi_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 439, 434, 428, "0", "0", "0", "0", "0" ],
+          "bits": [ 417, 410, 804, "0", "0", "0", "0", "0" ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_data_out",
             "src": "smi_ctrl.v:8.25-8.35"
           }
         },
+        "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_D": {
+          "hide_name": 0,
+          "bits": [ 805 ],
+          "attributes": {
+          }
+        },
         "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 833 ],
+          "bits": [ 803 ],
           "attributes": {
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         },
         "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 97, 56, 198, 98 ],
+          "bits": [ 57, 806 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39290,15 +39359,15 @@
         },
         "smi_ctrl_ins.o_dir": {
           "hide_name": 0,
-          "bits": [ 402 ],
+          "bits": [ 373 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_dir",
-            "src": "smi_ctrl.v:32.25-32.30"
+            "src": "smi_ctrl.v:31.25-31.30"
           }
         },
         "smi_ctrl_ins.o_smi_data_out": {
           "hide_name": 0,
-          "bits": [ 885, 877, 869, 861, 853, 845, 837, 835 ],
+          "bits": [ 858, 850, 842, 834, 826, 818, 810, 808 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_smi_data_out",
             "src": "smi_ctrl.v:26.25-26.39"
@@ -39306,13 +39375,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 836 ],
+          "bits": [ 809 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 838, 839 ],
+          "bits": [ 811, 812 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39320,13 +39389,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 844 ],
+          "bits": [ 817 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 846, 847 ],
+          "bits": [ 819, 820 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39334,13 +39403,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 852 ],
+          "bits": [ 825 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 854, 855 ],
+          "bits": [ 827, 828 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39348,13 +39417,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 860 ],
+          "bits": [ 833 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 862, 863 ],
+          "bits": [ 835, 836 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39362,13 +39431,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 868 ],
+          "bits": [ 841 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 870, 871 ],
+          "bits": [ 843, 844 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39376,13 +39445,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 876 ],
+          "bits": [ 849 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 878, 879 ],
+          "bits": [ 851, 852 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39390,13 +39459,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 884 ],
+          "bits": [ 857 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 886, 887 ],
+          "bits": [ 859, 860 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39404,21 +39473,29 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 807 ],
           "attributes": {
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 892, 893 ],
+          "bits": [ 865, 866 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "smi_ctrl_ins.o_smi_read_req": {
+          "hide_name": 0,
+          "bits": [ 372 ],
+          "attributes": {
+            "hdlname": "smi_ctrl_ins o_smi_read_req",
+            "src": "smi_ctrl.v:28.25-28.39"
+          }
+        },
         "smi_ctrl_ins.o_tx_fifo_clock": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_tx_fifo_clock",
             "src": "smi_ctrl.v:21.25-21.40"
@@ -39434,83 +39511,83 @@
         },
         "smi_ctrl_ins.r_dir": {
           "hide_name": 0,
-          "bits": [ 402 ],
+          "bits": [ 373 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_dir",
-            "src": "smi_ctrl.v:116.9-116.14"
+            "src": "smi_ctrl.v:114.9-114.14"
           }
         },
         "smi_ctrl_ins.r_dir_SB_DFFER_Q_E": {
           "hide_name": 0,
-          "bits": [ 898 ],
+          "bits": [ 871 ],
           "attributes": {
             "defaultvalue": "1",
-            "src": "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
+            "src": "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
           }
         },
         "smi_ctrl_ins.r_fifo_pull": {
           "hide_name": 0,
-          "bits": [ 899 ],
+          "bits": [ 872 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_pull",
-            "src": "smi_ctrl.v:112.9-112.20"
+            "src": "smi_ctrl.v:110.9-110.20"
           }
         },
         "smi_ctrl_ins.r_fifo_pull_1": {
           "hide_name": 0,
-          "bits": [ 900 ],
+          "bits": [ 873 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_pull_1",
-            "src": "smi_ctrl.v:113.9-113.22"
+            "src": "smi_ctrl.v:111.9-111.22"
           }
         },
-        "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O": {
+        "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 534 ],
+          "bits": [ 521 ],
           "attributes": {
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           }
         },
-        "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O": {
+        "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 706 ],
+          "bits": [ 685 ],
           "attributes": {
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         "smi_ctrl_ins.r_fifo_pulled_data": {
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           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_pulled_data",
-            "src": "smi_ctrl.v:117.16-117.34"
+            "src": "smi_ctrl.v:115.16-115.34"
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         "smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 63 ],
+          "bits": [ 67 ],
           "attributes": {
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         },
         "smi_ctrl_ins.r_fifo_push": {
           "hide_name": 0,
-          "bits": [ 902 ],
+          "bits": [ 875 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39725,47 +39778,47 @@
         },
         "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D": {
           "hide_name": 0,
-          "bits": [ 965 ],
+          "bits": [ 925 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.w_fifo_pull_trigger": {
           "hide_name": 0,
-          "bits": [ 901 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins w_fifo_pull_trigger",
-            "src": "smi_ctrl.v:114.10-114.29"
+            "src": "smi_ctrl.v:112.10-112.29"
           }
         },
         "smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D": {
           "hide_name": 0,
-          "bits": [ 976 ],
+          "bits": [ 936 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.w_fifo_push_trigger": {
           "hide_name": 0,
-          "bits": [ 963 ],
+          "bits": [ 923 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins w_fifo_push_trigger",
-            "src": "smi_ctrl.v:181.10-181.29"
+            "src": "smi_ctrl.v:169.10-169.29"
           }
         },
         "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 977 ],
+          "bits": [ 937 ],
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         },
         "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R": {
           "hide_name": 0,
-          "bits": [ 978 ],
+          "bits": [ 938 ],
           "attributes": {
           }
         },
         "spi_if_ins.i_data_out": {
           "hide_name": 0,
-          "bits": [ 436, 431, 424, 421, 418, 414, 408, 406 ],
+          "bits": [ 413, 406, 402, 398, 394, 388, 379, 377 ],
           "attributes": {
             "hdlname": "spi_if_ins i_data_out",
             "src": "spi_if.v:9.22-9.32"
@@ -39781,7 +39834,7 @@
         },
         "spi_if_ins.i_spi_cs_b": {
           "hide_name": 0,
-          "bits": [ 45 ],
+          "bits": [ 48 ],
           "attributes": {
             "hdlname": "spi_if_ins i_spi_cs_b",
             "src": "spi_if.v:18.12-18.22"
@@ -39789,7 +39842,7 @@
         },
         "spi_if_ins.i_spi_mosi": {
           "hide_name": 0,
-          "bits": [ 43 ],
+          "bits": [ 46 ],
           "attributes": {
             "hdlname": "spi_if_ins i_spi_mosi",
             "src": "spi_if.v:17.12-17.22"
@@ -39797,7 +39850,7 @@
         },
         "spi_if_ins.i_spi_sck": {
           "hide_name": 0,
-          "bits": [ 44 ],
+          "bits": [ 47 ],
           "attributes": {
             "hdlname": "spi_if_ins i_spi_sck",
             "src": "spi_if.v:15.12-15.21"
@@ -39805,7 +39858,7 @@
         },
         "spi_if_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "spi_if_ins i_sys_clk",
             "src": "spi_if.v:5.11-5.20"
@@ -39813,7 +39866,7 @@
         },
         "spi_if_ins.o_cs": {
           "hide_name": 0,
-          "bits": [ 197, 69, 441, 440 ],
+          "bits": [ 189, 73, 495, 947 ],
           "attributes": {
             "hdlname": "spi_if_ins o_cs",
             "src": "spi_if.v:10.22-10.26"
@@ -39821,21 +39874,35 @@
         },
         "spi_if_ins.o_cs_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 986 ],
+          "bits": [ 946 ],
           "attributes": {
           }
         },
-        "spi_if_ins.o_cs_SB_LUT4_I0_1_O": {
+        "spi_if_ins.o_cs_SB_LUT4_I0_3_O": {
           "hide_name": 0,
-          "bits": [ 415, 410, 416 ],
+          "bits": [ 403, 392, 381, 404 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "spi_if_ins.o_cs_SB_LUT4_I0_3_O": {
+        "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D": {
           "hide_name": 0,
-          "bits": [ 126, 411, 426 ],
+          "bits": [ 416, 409, 949, 400 ],
+          "attributes": {
+          }
+        },
+        "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E": {
+          "hide_name": 0,
+          "bits": [ 384 ],
+          "attributes": {
+            "defaultvalue": "1",
+            "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9"
+          }
+        },
+        "spi_if_ins.o_cs_SB_LUT4_I0_4_O": {
+          "hide_name": 0,
+          "bits": [ 106, 804, 411, 382 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39843,7 +39910,7 @@
         },
         "spi_if_ins.o_cs_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 3, 987 ],
+          "bits": [ 3, 948 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39851,13 +39918,13 @@
         },
         "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 405 ],
+          "bits": [ 376 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_data_in": {
           "hide_name": 0,
-          "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ],
+          "bits": [ 140, 138, 89, 136, 134, 133, 132, 130 ],
           "attributes": {
             "hdlname": "spi_if_ins o_data_in",
             "src": "spi_if.v:8.22-8.31"
@@ -39865,13 +39932,13 @@
         },
         "spi_if_ins.o_data_in_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 989 ],
+          "bits": [ 951 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 95 ],
+          "bits": [ 129 ],
           "attributes": {
             "hdlname": "spi_if_ins o_fetch_cmd",
             "src": "spi_if.v:11.22-11.33"
@@ -39879,7 +39946,7 @@
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 1003, 1002, 995 ],
+          "bits": [ 962, 968, 957 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39887,13 +39954,13 @@
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 996 ],
+          "bits": [ 958 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 3, 1003, 1004, 1005 ],
+          "bits": [ 3, 962, 963, 964 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39901,7 +39968,7 @@
         },
         "spi_if_ins.o_ioc": {
           "hide_name": 0,
-          "bits": [ 56, 97, 208, 207, 206 ],
+          "bits": [ 55, 54, 60, 59, 58 ],
           "attributes": {
             "hdlname": "spi_if_ins o_ioc",
             "src": "spi_if.v:7.22-7.27"
@@ -39909,13 +39976,13 @@
         },
         "spi_if_ins.o_ioc_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 68 ],
+          "bits": [ 72 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_load_cmd": {
           "hide_name": 0,
-          "bits": [ 94 ],
+          "bits": [ 146 ],
           "attributes": {
             "hdlname": "spi_if_ins o_load_cmd",
             "src": "spi_if.v:12.22-12.32"
@@ -39923,7 +39990,7 @@
         },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 998, 999 ],
+          "bits": [ 962, 961, 968 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39931,19 +39998,27 @@
         },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 1006 ],
+          "bits": [ 965 ],
           "attributes": {
           }
         },
+        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 962, 960, 961, 970 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 997 ],
+          "bits": [ 959 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 399 ],
+          "bits": [ 370 ],
           "attributes": {
             "hdlname": "spi_if_ins o_spi_miso",
             "src": "spi_if.v:16.12-16.22"
@@ -39951,15 +40026,21 @@
         },
         "spi_if_ins.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 1018, 1017, 1016, 1015, 1014, 1013, 1012, 1011 ],
+          "bits": [ 980, 979, 978, 977, 976, 975, 974, 973 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_byte",
             "src": "spi_if.v:33.14-33.23"
           }
         },
+        "spi_if_ins.r_tx_byte_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 972 ],
+          "attributes": {
+          }
+        },
         "spi_if_ins.r_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 1020 ],
+          "bits": [ 982 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_data_valid",
             "src": "spi_if.v:32.14-32.29"
@@ -39967,19 +40048,19 @@
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 1019 ],
+          "bits": [ 981 ],
           "attributes": {
           }
         },
         "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O": {
           "hide_name": 0,
-          "bits": [ 1022 ],
+          "bits": [ 984 ],
           "attributes": {
           }
         },
         "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 1027, 1026, 1021 ],
+          "bits": [ 989, 988, 983 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -39987,7 +40068,7 @@
         },
         "spi_if_ins.spi.SCKr": {
           "hide_name": 0,
-          "bits": [ 1028, 1026, 1027 ],
+          "bits": [ 990, 988, 989 ],
           "attributes": {
             "hdlname": "spi_if_ins spi SCKr",
             "src": "spi_slave.v:61.13-61.17"
@@ -39995,7 +40076,7 @@
         },
         "spi_if_ins.spi.i_spi_cs_b": {
           "hide_name": 0,
-          "bits": [ 45 ],
+          "bits": [ 48 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_spi_cs_b",
             "src": "spi_slave.v:13.16-13.26"
@@ -40003,7 +40084,7 @@
         },
         "spi_if_ins.spi.i_spi_mosi": {
           "hide_name": 0,
-          "bits": [ 43 ],
+          "bits": [ 46 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_spi_mosi",
             "src": "spi_slave.v:12.16-12.26"
@@ -40011,7 +40092,7 @@
         },
         "spi_if_ins.spi.i_spi_sck": {
           "hide_name": 0,
-          "bits": [ 44 ],
+          "bits": [ 47 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_spi_sck",
             "src": "spi_slave.v:10.16-10.25"
@@ -40019,7 +40100,7 @@
         },
         "spi_if_ins.spi.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_sys_clk",
             "src": "spi_slave.v:3.22-3.31"
@@ -40027,7 +40108,7 @@
         },
         "spi_if_ins.spi.i_tx_byte": {
           "hide_name": 0,
-          "bits": [ 1018, 1017, 1016, 1015, 1014, 1013, 1012, 1011 ],
+          "bits": [ 980, 979, 978, 977, 976, 975, 974, 973 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_byte",
             "src": "spi_slave.v:7.22-7.31"
@@ -40035,7 +40116,7 @@
         },
         "spi_if_ins.spi.i_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 1020 ],
+          "bits": [ 982 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_data_valid",
             "src": "spi_slave.v:6.22-6.37"
@@ -40043,7 +40124,7 @@
         },
         "spi_if_ins.spi.o_rx_byte": {
           "hide_name": 0,
-          "bits": [ 994, 993, 992, 991, 990, 72, 71, 988 ],
+          "bits": [ 956, 955, 954, 953, 952, 76, 75, 950 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_byte",
             "src": "spi_slave.v:5.22-5.31"
@@ -40051,7 +40132,7 @@
         },
         "spi_if_ins.spi.o_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 1003 ],
+          "bits": [ 962 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_data_valid",
             "src": "spi_slave.v:4.22-4.37"
@@ -40059,7 +40140,7 @@
         },
         "spi_if_ins.spi.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 399 ],
+          "bits": [ 370 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_spi_miso",
             "src": "spi_slave.v:11.16-11.26"
@@ -40067,13 +40148,13 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 1038 ],
+          "bits": [ 1000 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1011, 1021, 1039 ],
+          "bits": [ 973, 983, 1001 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40081,7 +40162,7 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 1040, 1041, 1042, 1043 ],
+          "bits": [ 1002, 1003, 1004, 1005 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40089,7 +40170,7 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2": {
           "hide_name": 0,
-          "bits": [ 1046, 1050, 1051 ],
+          "bits": [ 1008, 1012, 1013 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40097,7 +40178,7 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 1021, 1023, 1024 ],
+          "bits": [ 983, 985, 986 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40105,7 +40186,7 @@
         },
         "spi_if_ins.spi.r2_rx_done": {
           "hide_name": 0,
-          "bits": [ 1057 ],
+          "bits": [ 1019 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r2_rx_done",
             "src": "spi_slave.v:21.7-21.17"
@@ -40113,7 +40194,7 @@
         },
         "spi_if_ins.spi.r3_rx_done": {
           "hide_name": 0,
-          "bits": [ 1058 ],
+          "bits": [ 1020 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r3_rx_done",
             "src": "spi_slave.v:22.7-22.17"
@@ -40121,13 +40202,13 @@
         },
         "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 1030 ],
+          "bits": [ 992 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_bit_count": {
           "hide_name": 0,
-          "bits": [ 1063, 1062, 1060 ],
+          "bits": [ 1025, 1024, 1022 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_bit_count",
             "src": "spi_slave.v:16.13-16.27"
@@ -40135,25 +40216,25 @@
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 1061 ],
+          "bits": [ 1023 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 1064 ],
+          "bits": [ 1026 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 1059 ],
+          "bits": [ 1021 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1065 ],
+          "bits": [ 1027 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
             "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
@@ -40161,7 +40242,7 @@
         },
         "spi_if_ins.spi.r_rx_byte": {
           "hide_name": 0,
-          "bits": [ 1037, 1036, 1035, 1034, 1033, 1032, 1031, 1029 ],
+          "bits": [ 999, 998, 997, 996, 995, 994, 993, 991 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_byte",
             "src": "spi_slave.v:19.13-19.22"
@@ -40169,7 +40250,7 @@
         },
         "spi_if_ins.spi.r_rx_done": {
           "hide_name": 0,
-          "bits": [ 1056 ],
+          "bits": [ 1018 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_done",
             "src": "spi_slave.v:20.7-20.16"
@@ -40177,7 +40258,7 @@
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 45, 1074 ],
+          "bits": [ 48, 1036 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40185,19 +40266,19 @@
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 1067 ],
+          "bits": [ 1029 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 1075 ],
+          "bits": [ 1037 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_temp_rx_byte": {
           "hide_name": 0,
-          "bits": [ 1073, 1072, 1071, 1070, 1069, 1068, 1066, "x" ],
+          "bits": [ 1035, 1034, 1033, 1032, 1031, 1030, 1028, "x" ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_temp_rx_byte",
             "src": "spi_slave.v:18.13-18.27"
@@ -40205,7 +40286,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count": {
           "hide_name": 0,
-          "bits": [ 1047, 1046, 1040 ],
+          "bits": [ 1009, 1008, 1002 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_bit_count",
             "src": "spi_slave.v:17.13-17.27"
@@ -40213,25 +40294,25 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 1076 ],
+          "bits": [ 1038 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 1078 ],
+          "bits": [ 1040 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D": {
           "hide_name": 0,
-          "bits": [ 1077 ],
+          "bits": [ 1039 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1079 ],
+          "bits": [ 1041 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
             "src": "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
@@ -40239,7 +40320,7 @@
         },
         "spi_if_ins.spi.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 1053, 1052, 1055, 1054, 1049, 1045, 1048, 1044 ],
+          "bits": [ 1015, 1014, 1017, 1016, 1011, 1007, 1010, 1006 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_byte",
             "src": "spi_slave.v:23.13-23.22"
@@ -40247,13 +40328,13 @@
         },
         "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 1025 ],
+          "bits": [ 987 ],
           "attributes": {
           }
         },
         "spi_if_ins.state_if": {
           "hide_name": 0,
-          "bits": [ 1001, 1000, 998 ],
+          "bits": [ 967, 966, 960 ],
           "attributes": {
             "hdlname": "spi_if_ins state_if",
             "src": "spi_if.v:29.14-29.22"
@@ -40261,43 +40342,29 @@
         },
         "spi_if_ins.state_if_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 1082 ],
+          "bits": [ 1044 ],
           "attributes": {
           }
         },
+        "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 962, 963 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 3, 969, 1042, 971 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "spi_if_ins.state_if_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 988, 1004, 1083 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.state_if_SB_DFFESR_Q_D": {
-          "hide_name": 0,
-          "bits": [ 3, 1007, 1080 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 1010 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 1003, 1004 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 1007, 1008, 1009 ],
+          "bits": [ 950, 963, 1045 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40305,13 +40372,13 @@
         },
         "spi_if_ins.state_if_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 1081 ],
+          "bits": [ 1043 ],
           "attributes": {
           }
         },
         "spi_if_ins.w_rx_data": {
           "hide_name": 0,
-          "bits": [ 994, 993, 992, 991, 990, 72, 71, 988 ],
+          "bits": [ 956, 955, 954, 953, 952, 76, 75, 950 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data",
             "src": "spi_if.v:31.14-31.23"
@@ -40319,7 +40386,7 @@
         },
         "spi_if_ins.w_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 1003 ],
+          "bits": [ 962 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data_valid",
             "src": "spi_if.v:30.14-30.29"
@@ -40327,7 +40394,7 @@
         },
         "sys_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 197 ],
+          "bits": [ 189 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_cs",
             "src": "sys_ctrl.v:9.29-9.33"
@@ -40335,13 +40402,21 @@
         },
         "sys_ctrl_ins.i_cs_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 70 ],
+          "bits": [ 74 ],
           "attributes": {
           }
         },
+        "sys_ctrl_ins.i_cs_SB_LUT4_I2_I3": {
+          "hide_name": 0,
+          "bits": [ 129, 189, 1046 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "sys_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ],
+          "bits": [ 140, 138, 89, 136, 134, 133, 132, 130 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_data_in",
             "src": "sys_ctrl.v:7.29-7.38"
@@ -40349,7 +40424,7 @@
         },
         "sys_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 95 ],
+          "bits": [ 129 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_fetch_cmd",
             "src": "sys_ctrl.v:10.29-10.40"
@@ -40357,7 +40432,7 @@
         },
         "sys_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 56, 97, 208, 207, 206 ],
+          "bits": [ 55, 54, 60, 59, 58 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_ioc",
             "src": "sys_ctrl.v:6.29-6.34"
@@ -40365,7 +40440,7 @@
         },
         "sys_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 94 ],
+          "bits": [ 146 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_load_cmd",
             "src": "sys_ctrl.v:11.29-11.39"
@@ -40381,7 +40456,7 @@
         },
         "sys_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 66 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_sys_clk",
             "src": "sys_ctrl.v:4.29-4.38"
@@ -40403,55 +40478,9 @@
             "src": "sys_ctrl.v:18.29-18.44"
           }
         },
-        "tx_fifo.debug_pull": {
-          "hide_name": 0,
-          "bits": [ "0" ],
-          "attributes": {
-            "hdlname": "tx_fifo debug_pull",
-            "src": "complex_fifo.v:19.18-19.28"
-          }
-        },
-        "tx_fifo.debug_push": {
-          "hide_name": 0,
-          "bits": [ "0" ],
-          "attributes": {
-            "hdlname": "tx_fifo debug_push",
-            "src": "complex_fifo.v:20.18-20.28"
-          }
-        },
-        "tx_fifo.empty_o": {
-          "hide_name": 0,
-          "bits": [ 352 ],
-          "attributes": {
-            "hdlname": "tx_fifo empty_o",
-            "src": "complex_fifo.v:17.19-17.26"
-          }
-        },
-        "tx_fifo.empty_o_SB_DFFNSS_Q_D": {
-          "hide_name": 0,
-          "bits": [ 1084 ],
-          "attributes": {
-          }
-        },
-        "tx_fifo.empty_o_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 394, 1086, 1085, 1087 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 390, 391, 385, 392 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "tx_fifo.full_o": {
           "hide_name": 0,
-          "bits": [ 400 ],
+          "bits": [ 371 ],
           "attributes": {
             "hdlname": "tx_fifo full_o",
             "src": "complex_fifo.v:16.19-16.25"
@@ -40459,133 +40488,181 @@
         },
         "tx_fifo.full_o_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 1089 ],
+          "bits": [ 1047 ],
           "attributes": {
           }
         },
+        "tx_fifo.full_o_SB_LUT4_I1_O": {
+          "hide_name": 0,
+          "bits": [ 1054, 1053, 1055 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O": {
+          "hide_name": 0,
+          "bits": [ 1048, 1049, 1050, 1051 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "tx_fifo.rd_addr": {
           "hide_name": 0,
-          "bits": [ 1088, 380, 379, 387, 385, 390, 377, 374, 373, 384 ],
+          "bits": [ 1080, 362, 344, 1075, 342, 1067, 1065, 1063, 1061, 339 ],
           "attributes": {
             "hdlname": "tx_fifo rd_addr",
-            "src": "complex_fifo.v:27.23-27.30"
+            "src": "complex_fifo.v:24.23-24.30"
           }
         },
-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 1092, 1091 ],
+          "bits": [ 1077, 1066 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 368, 369, 370, 371 ],
+          "bits": [ 1068 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
+          "hide_name": 0,
+          "bits": [ 1069 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
+          "hide_name": 0,
+          "bits": [ 1070 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
+          "hide_name": 0,
+          "bits": [ 1071 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
+          "hide_name": 0,
+          "bits": [ 1072 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 1060, 347 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 393, 381, 395, 396 ],
+          "bits": [ 1064, 1062 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 1099 ],
+          "bits": [ 1073 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
           }
         },
-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 1100 ],
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             "abc9_carry": "00000000000000000000000000000001",
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
           "hide_name": 0,
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
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-          "hide_name": 0,
-          "bits": [ 351, 353, 354 ],
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           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
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           "hide_name": 0,
-          "bits": [ 1091, 1090 ],
+          "bits": [ 1079, 1078 ],
           "attributes": {
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           }
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": {
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1103 ],
+          "bits": [ 1076 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": {
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-          "bits": [ 1104 ],
-          "attributes": {
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
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-        "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
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           "hide_name": 0,
-          "bits": [ 1108, 1097 ],
+          "bits": [ 351, 352, 353, 354 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1": {
+          "hide_name": 0,
+          "bits": [ 342, 1082, 1083, 1084 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1": {
+          "hide_name": 0,
+          "bits": [ 1063, 1086, 1087, 1088 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3": {
+          "hide_name": 0,
+          "bits": [ 1063, 1065, 1089, 1090 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 364, 365, 366, 367 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40593,21 +40670,37 @@
         },
         "tx_fifo.rd_addr_SB_DFFNESR_Q_8_D": {
           "hide_name": 0,
-          "bits": [ 1109 ],
+          "bits": [ 1091 ],
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           }
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         "tx_fifo.rd_addr_gray": {
           "hide_name": 0,
-          "bits": [ 1119, 1117, 1116, 1115, 1114, 1113, 1112, 1111, 1110, 384 ],
+          "bits": [ 1108, 1106, 1105, 1103, 1102, 1100, 1097, 1095, 1092, 339 ],
           "attributes": {
             "hdlname": "tx_fifo rd_addr_gray",
-            "src": "complex_fifo.v:28.23-28.35"
+            "src": "complex_fifo.v:25.23-25.35"
           }
         },
         "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 364, 365, 366 ],
+          "bits": [ 355, 356, 357 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D": {
+          "hide_name": 0,
+          "bits": [ 1089, 1096, 1099 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3": {
+          "hide_name": 0,
+          "bits": [ 343, 1078, 1077, 1098 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40615,7 +40708,23 @@
         },
         "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 375, 391, 1095, 1096 ],
+          "bits": [ 1085, 1101 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 358, 359, 360, 361 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D": {
+          "hide_name": 0,
+          "bits": [ 343, 1093, 1094 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40623,37 +40732,35 @@
         },
         "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 386, 389, 1093, 1094 ],
+          "bits": [ 1104 ],
           "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D": {
           "hide_name": 0,
-          "bits": [ 1118 ],
+          "bits": [ 1107 ],
           "attributes": {
           }
         },
         "tx_fifo.rd_addr_gray_wr": {
           "hide_name": 0,
-          "bits": [ 1129, 1128, 1127, 1126, 1125, 1124, 1123, 1122, 1121, 1120 ],
+          "bits": [ 1118, 1117, 1116, 1115, 1114, 1113, 1112, 1111, 1110, 1109 ],
           "attributes": {
             "hdlname": "tx_fifo rd_addr_gray_wr",
-            "src": "complex_fifo.v:29.23-29.38"
+            "src": "complex_fifo.v:26.23-26.38"
           }
         },
         "tx_fifo.rd_addr_gray_wr_r": {
           "hide_name": 0,
-          "bits": [ 910, 907, 948, 944, 921, 919, 914, 926, 958, 909 ],
+          "bits": [ 887, 880, 920, 915, 916, 922, 912, 890, 883, 882 ],
           "attributes": {
             "hdlname": "tx_fifo rd_addr_gray_wr_r",
-            "src": "complex_fifo.v:30.23-30.40"
+            "src": "complex_fifo.v:27.23-27.40"
           }
         },
         "tx_fifo.rd_en_i": {
           "hide_name": 0,
-          "bits": [ 351 ],
+          "bits": [ 333 ],
           "attributes": {
             "hdlname": "tx_fifo rd_en_i",
             "src": "complex_fifo.v:13.28-13.35"
@@ -40669,71 +40776,79 @@
         },
         "tx_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 1146, 942, 906, 961, 924, 949, 953, 955, 957, 962 ],
+          "bits": [ 1137, 908, 879, 907, 905, 903, 901, 899, 897, 894 ],
           "attributes": {
             "hdlname": "tx_fifo wr_addr",
-            "src": "complex_fifo.v:23.23-23.30"
+            "src": "complex_fifo.v:20.23-20.30"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_2_D": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 1140, 1132 ],
+          "bits": [ 1121, 1120 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 944, 1136, 1143, 1133 ],
+          "bits": [ 915, 1136, 1133, 1122 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1137 ],
+          "bits": [ 1123 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
           "hide_name": 0,
-          "bits": [ 1138 ],
+          "bits": [ 1124 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
           }
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-        "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO": {
           "hide_name": 0,
-          "bits": [ 1131, 1130 ],
+          "bits": [ 1125 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 1119, 1052 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_3_D": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": {
           "hide_name": 0,
-          "bits": [ 1142, 1140 ],
+          "bits": [ 1126 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 1128, 1121 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 1139 ],
-          "attributes": {
-            "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
-          }
-        },
         "tx_fifo.wr_addr_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 1135, 1142 ],
+          "bits": [ 1129, 1128 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40741,39 +40856,55 @@
         },
         "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 1141 ],
+          "bits": [ 1130 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": {
           "hide_name": 0,
-          "bits": [ 1144 ],
+          "bits": [ 1127 ],
           "attributes": {
             "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
           }
         },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": {
+        "tx_fifo.wr_addr_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 1145 ],
-          "attributes": {
-            "abc9_carry": "00000000000000000000000000000001",
-            "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
-          }
-        },
-        "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 1134, 1135 ],
+          "bits": [ 1132, 1129 ],
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             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 1131 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
+        "tx_fifo.wr_addr_SB_DFFESR_Q_6_D": {
+          "hide_name": 0,
+          "bits": [ 1135, 1132 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 1134 ],
+          "attributes": {
+            "abc9_carry": "00000000000000000000000000000001",
+            "src": "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11"
+          }
+        },
         "tx_fifo.wr_addr_SB_DFFESR_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 911, 1134 ],
+          "bits": [ 888, 1135 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40781,7 +40912,7 @@
         },
         "tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 919, 907, 1147, 1148 ],
+          "bits": [ 922, 880, 1138, 1139 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40789,45 +40920,45 @@
         },
         "tx_fifo.wr_addr_SB_DFFESR_Q_8_D": {
           "hide_name": 0,
-          "bits": [ 1149 ],
+          "bits": [ 1140 ],
           "attributes": {
           }
         },
         "tx_fifo.wr_addr_gray": {
           "hide_name": 0,
-          "bits": [ 1165, 1163, 1161, 1159, 1158, 1156, 1155, 1153, 1151, 962 ],
+          "bits": [ 1156, 1154, 1152, 1150, 1149, 1147, 1146, 1144, 1142, 894 ],
           "attributes": {
             "hdlname": "tx_fifo wr_addr_gray",
-            "src": "complex_fifo.v:24.23-24.35"
+            "src": "complex_fifo.v:21.23-21.35"
           }
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 1150 ],
+          "bits": [ 1141 ],
           "attributes": {
           }
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 1152 ],
+          "bits": [ 1143 ],
           "attributes": {
           }
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 1154 ],
+          "bits": [ 1145 ],
           "attributes": {
           }
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 1157 ],
+          "bits": [ 1148 ],
           "attributes": {
           }
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 944, 948, 1160, 1143 ],
+          "bits": [ 915, 920, 1151, 1133 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -40835,7 +40966,7 @@
         },
         "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 935, 936, 937, 938 ],
+          "bits": [ 1056, 1057, 1058, 1059 ],
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           "hide_name": 0,
           "bits": [ "0", "x", "x", "x", "x", "x", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x", "0", "x" ],
           "attributes": {
-            "src": "top.v:448.15-448.29"
-          }
-        },
-        "w_tx_fifo_empty": {
-          "hide_name": 0,
-          "bits": [ 352 ],
-          "attributes": {
-            "src": "top.v:444.8-444.23"
+            "src": "top.v:458.15-458.29"
           }
         },
         "w_tx_fifo_full": {
           "hide_name": 0,
-          "bits": [ 400 ],
+          "bits": [ 371 ],
           "attributes": {
-            "src": "top.v:443.8-443.22"
+            "src": "top.v:454.8-454.22"
           }
         },
         "w_tx_fifo_pull": {
           "hide_name": 0,
-          "bits": [ 351 ],
+          "bits": [ 333 ],
           "attributes": {
-            "src": "top.v:449.8-449.22"
+            "src": "top.v:459.8-459.22"
+          }
+        },
+        "w_tx_fifo_read_clk": {
+          "hide_name": 0,
+          "bits": [ 164 ],
+          "attributes": {
+            "src": "top.v:456.8-456.26"
           }
         }
       }
diff --git a/firmware/top.v b/firmware/top.v
index 54680a5..b7cd827 100644
--- a/firmware/top.v
+++ b/firmware/top.v
@@ -40,7 +40,9 @@ module top (
     // DIGITAL I/F
     input [3:0] i_config,
     input i_button,
-    inout [7:0] io_pmod,
+    //inout [7:0] io_pmod,
+    output [3:0] io_pmod_out,
+    input [3:0] io_pmod_in,
     output o_led0,
     output o_led1,
 
@@ -121,10 +123,10 @@ module top (
   wire w_tx_sync_input_09;
   wire w_tx_sync_input_24;
 
-  assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod[7] : w_rx_sync_09;
-  assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod[6] : w_rx_sync_24;
-  assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod[5] : w_tx_sync_09;
-  assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod[4] : w_tx_sync_24;
+  assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod_in[3] : w_rx_sync_09;
+  assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod_in[2] : w_rx_sync_24;
+  assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod_in[1] : w_tx_sync_09;
+  assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod_in[0] : w_tx_sync_24;
 
   //=========================================================================
   // INSTANCES
@@ -179,7 +181,6 @@ module top (
 
   wire w_debug_fifo_push;
   wire w_debug_fifo_pull;
-  wire w_debug_smi_test;
   wire w_debug_lb_tx;
   wire [3:0] tx_sample_gap;
 
@@ -199,7 +200,7 @@ module top (
       .i_config(i_config),
       .o_led0  (o_led0),
       .o_led1  (o_led1),
-      .o_pmod  (/*io_pmod[3:0]*/),
+      .o_pmod  (io_pmod_out[3:0]),
 
       // Analog interfaces
       .o_mixer_fm(/*o_mixer_fm*/),
@@ -213,11 +214,6 @@ module top (
       .o_mixer_en(/*o_mixer_en*/)
   );
 
-  assign io_pmod[0] = ~lvds_clock_buf;
-  assign io_pmod[1] = w_lvds_tx_d0;
-  assign io_pmod[2] = w_lvds_tx_d1;
-  assign io_pmod[3] = i_smi_swe_srw;
-
   //=========================================================================
   // CONBINATORIAL ASSIGNMENTS
   //=========================================================================
@@ -401,21 +397,21 @@ module top (
   wire w_rx_fifo_empty;
 
   complex_fifo  #(
-      .ADDR_WIDTH(10),  // 1024 samples
+      .ADDR_WIDTH(10),   // 1024 samples
       .DATA_WIDTH(16),  // 2x16 for I and Q 
   ) rx_fifo (
       .wr_rst_b_i(i_rst_b),
       .wr_clk_i(w_rx_fifo_write_clk),
       .wr_en_i(w_rx_fifo_push),
       .wr_data_i(w_rx_fifo_data),
+
       .rd_rst_b_i(i_rst_b),
       .rd_clk_i(w_clock_sys),
       .rd_en_i(w_rx_fifo_pull),
       .rd_data_o(w_rx_fifo_pulled_data),
+
       .full_o(w_rx_fifo_full),
       .empty_o(w_rx_fifo_empty),
-      .debug_pull(1'b0/*w_debug_fifo_pull*/),
-      .debug_push(1'b0/*w_debug_fifo_push*/)
   );
   
   //=========================================================================
@@ -426,7 +422,7 @@ module top (
   
   lvds_tx lvds_tx_inst (
       .i_rst_b(i_rst_b),
-      .i_ddr_clk(~lvds_clock_buf),
+      .i_ddr_clk(lvds_clock_buf),
       .o_ddr_data({w_lvds_tx_d0, w_lvds_tx_d1}),
       .i_fifo_empty(w_tx_fifo_empty),
       .o_fifo_read_clk(w_tx_fifo_read_clk),
@@ -440,11 +436,25 @@ module top (
       .o_sync_state_bit(),
   );
 
+  //assign io_pmod[0] = ~lvds_clock_buf;
+  //assign io_pmod[1] = w_lvds_tx_d0;
+  //assign io_pmod[2] = w_lvds_tx_d1;
+  //assign io_pmod[0] = w_smi_write_req;
+  //assign io_pmod[1] = i_smi_swe_srw;
+  //assign io_pmod[2] = w_tx_fifo_push;
+  //assign io_pmod[3] = w_smi_tx_state[0];
+  //assign io_pmod[4] = w_smi_tx_state[1];
+  //assign io_pmod[5] = w_tx_fifo_full;
+  //assign io_pmod[6] = w_tx_fifo_empty;
+  //assign io_pmod[7] = w_tx_fifo_pull;
+
+  //assign io_pmod[7:0] = w_smi_data_input;
+  assign o_smi_write_req = i_smi_swe_srw;
+
   wire w_tx_fifo_full;
   wire w_tx_fifo_empty;
   wire w_tx_fifo_read_clk;
   wire w_tx_fifo_push;
-  wire w_tx_fifo_clock;
   wire [31:0] w_tx_fifo_data;
   wire w_tx_fifo_pull;
   wire [31:0] w_tx_fifo_pulled_data;
@@ -455,25 +465,21 @@ module top (
   ) tx_fifo (
       // smi clock is writing
       .wr_rst_b_i(i_rst_b),
-      .wr_clk_i(w_tx_fifo_clock),
+      .wr_clk_i(w_clock_sys),
       .wr_en_i(w_tx_fifo_push),
       .wr_data_i(w_tx_fifo_data),
+      .full_o(w_tx_fifo_full),
 	  
       // lvds clock is pulling (reading)
       .rd_rst_b_i(i_rst_b),
-      .rd_clk_i(w_tx_fifo_read_clk),
+      .rd_clk_i(~lvds_clock_buf),
       .rd_en_i(w_tx_fifo_pull),
       .rd_data_o(w_tx_fifo_pulled_data),
-      .full_o(w_tx_fifo_full),
       .empty_o(w_tx_fifo_empty),
-      .debug_pull(1'b0),
-      .debug_push(1'b0)
   );
 
   wire channel;
   wire w_smi_data_direction;
-  //assign channel = i_smi_a3;
-  //assign w_smi_data_direction = i_smi_a2;
 
   smi_ctrl smi_ctrl_ins (
       .i_rst_b(i_rst_b),
@@ -494,7 +500,7 @@ module top (
       .o_tx_fifo_push(w_tx_fifo_push),
       .o_tx_fifo_pushed_data(w_tx_fifo_data),
       .i_tx_fifo_full(w_tx_fifo_full),
-      .o_tx_fifo_clock(w_tx_fifo_clock),
+      .o_tx_fifo_clock(/*w_tx_fifo_clock*/),
 
       .i_smi_soe_se(i_smi_soe_se),
       .i_smi_swe_srw(i_smi_swe_srw),
@@ -504,15 +510,15 @@ module top (
       .o_smi_write_req(w_smi_write_req),
       .o_channel(channel),
       .o_dir (w_smi_data_direction),
-      .i_smi_test(1'b0/*w_debug_smi_test*/),
       .o_cond_tx(),
-      .o_address_error()
+      .o_state(w_smi_tx_state)
   );
 
   wire [7:0] w_smi_data_output;
   wire [7:0] w_smi_data_input;
   wire w_smi_read_req;
   wire w_smi_write_req;
+  wire [1:0] w_smi_tx_state;
 
   // the "Writing" flag indicates that the data[7:0] direction (inout)
   // from the FPGA's SMI module should be "output". This happens when the
@@ -594,7 +600,7 @@ module top (
   );
 
   assign o_smi_read_req  = (w_smi_data_direction) ? w_smi_read_req : w_smi_write_req;
-  assign o_smi_write_req = 1'bZ;
+  //assign o_smi_write_req = 1'bZ;
 
   //assign o_led0 = w_smi_data_direction;
   //assign o_led1 = channel;
diff --git a/firmware/try-seeds.sh b/firmware/try-seeds.sh
new file mode 100644
index 0000000..365a8eb
--- /dev/null
+++ b/firmware/try-seeds.sh
@@ -0,0 +1,22 @@
+#! /usr/bin/bash
+
+# Decimate
+FSTART="125"
+FSTOP="125"
+MOD="top"
+
+f=${FSTART}
+while [ $f -le ${FSTOP} ]
+  do
+  i=1
+  while [ $i -le 30 ]
+    do
+      echo "freq $f seed $i"
+      nextpnr-ice40 --lp1k --package qn84 --asc ${MOD}.asc --pcf io.pcf --json ${MOD}.json --seed $i --parallel-refine --opt-timing --timing-allow-fail 2>&1 | fgrep 'Info: Max frequency for clock'
+      
+      icetime -d lp1k -P qn84 -p io.pcf -t ${MOD}.asc 2>&1 | fgrep 'Total path delay'
+      #icepack ${MOD}.asc ${MOD}.bin
+      i=$((i+1))
+    done
+  f=$((f+5))
+  done
diff --git a/software/libcariboulite/src/at86rf215/at86rf215.c b/software/libcariboulite/src/at86rf215/at86rf215.c
index cf19a0d..a4042ed 100644
--- a/software/libcariboulite/src/at86rf215/at86rf215.c
+++ b/software/libcariboulite/src/at86rf215/at86rf215.c
@@ -181,7 +181,7 @@ int at86rf215_init(at86rf215_st* dev,
 
     ZF_LOGD("Adding chip definition to io_utils_spi");
     io_utils_hard_spi_st hard_dev_modem = { .spi_dev_id = dev->spi_dev, .spi_dev_channel = dev->spi_channel, };
-	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 1000000, 0, 0,
+	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 4000000, 0, 0,
                         						io_utils_spi_chip_type_modem,
                                                 &hard_dev_modem);
 
diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi.c b/software/libcariboulite/src/caribou_smi/caribou_smi.c
index ecfa0b3..7240832 100644
--- a/software/libcariboulite/src/caribou_smi/caribou_smi.c
+++ b/software/libcariboulite/src/caribou_smi/caribou_smi.c
@@ -689,11 +689,18 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
 {
     caribou_smi_sample_complex_int16* cmplx_vec = sample_offset;  
     uint32_t *samples = (uint32_t*)(data);
-	
+    
+    // Sample Structure
+    // [                 BYTE 0      ] [           BYTE 1     ] [           BYTE 2        ] [          BYTE 3      ]
+    // [SOF TXC CTX I12 I11 I10 I9 I8] [0 I7 I6 I5 I4 I3 I2 I1] [0 I0 Q12 Q11 Q10 Q9 Q8 Q7] [0 Q6 Q5 Q4 Q3 Q2 Q1 Q0]
+	//   1  0/1 0/1
+    
     for (unsigned int i = 0; i < (data_length / CARIBOU_SMI_BYTES_PER_SAMPLE); i++)
     {                    
-        int32_t ii = cmplx_vec[i].i;
-        int32_t qq = cmplx_vec[i].q;
+        int32_t ii = 0xFFFF; //cmplx_vec[i].i;
+        int32_t qq = 0; //cmplx_vec[i].q;
+        ii &= 0x1FFF;
+        qq &= 0x1FFF;
 		
         uint32_t s = SMI_TX_SAMPLE_SOF | SMI_TX_SAMPLE_MODEM_TX_CTRL | SMI_TX_SAMPLE_COND_TX_CTRL; s <<= 5;
         s |= (ii >> 8) & 0x1F; s <<= 8;
@@ -705,6 +712,7 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
 		//if (i < 2) printf("0x%08X\n", s);
 		
         samples[i] = __builtin_bswap32(s);
+        //samples[i] = s;
     }
 }
 
diff --git a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h
index 13cd398..799a525 100644
--- a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h
+++ b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h
@@ -17,27 +17,27 @@ extern "C" {
 
 /*
  * Time tagging of the module through the 'struct tm' structure 
- *     Date: 2024-03-15
- *     Time: 00:30:30
+ *     Date: 2024-04-09
+ *     Time: 11:55:21
  */
 struct tm smi_stream_dev_date_time = {
-   .tm_sec = 30,
-   .tm_min = 30,
-   .tm_hour = 0,
-   .tm_mday = 15,
-   .tm_mon = 2,   /* +1    */
+   .tm_sec = 21,
+   .tm_min = 55,
+   .tm_hour = 11,
+   .tm_mday = 9,
+   .tm_mon = 3,   /* +1    */
    .tm_year = 124,  /* +1900 */
 };
 
 /*
  * Data blob of variable smi_stream_dev:
- *     Size: 35136 bytes
+ *     Size: 33144 bytes
  *     Original filename: /home/pi/cariboulite/driver/build/smi_stream_dev.ko
  */
 uint8_t smi_stream_dev[] = {
 	0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x01, 0x00, 0xB7, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x28, 0x00, 0x27, 0x00, 
 	0x3F, 0x23, 0x03, 0xD5, 0x00, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE1, 0x03, 0x00, 0x2A, 
 	0x21, 0x00, 0x01, 0xCA, 0x01, 0x00, 0x00, 0xB5, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 
@@ -58,51 +58,41 @@ uint8_t smi_stream_dev[] = {
 	0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 
 	0x00, 0x00, 0x80, 0x52, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 
 	0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 
-	0xFD, 0x7B, 0xB9, 0xA9, 0x03, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 
-	0x14, 0x00, 0x00, 0x90, 0xF5, 0x5B, 0x02, 0xA9, 0xF6, 0x03, 0x01, 0xAA, 0xF5, 0x03, 0x02, 0xAA, 
-	0x80, 0x02, 0x40, 0xF9, 0x61, 0xCC, 0x42, 0xF9, 0xE1, 0x37, 0x00, 0xF9, 0x01, 0x00, 0x80, 0xD2, 
-	0xFF, 0x3F, 0x00, 0xB9, 0x00, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x20, 0x09, 0x00, 0x35, 
-	0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x01, 0x91, 0x00, 0x40, 0x40, 0xB9, 0x22, 0x84, 0x40, 0x29, 
-	0x00, 0x00, 0x02, 0x4B, 0x3F, 0x00, 0x00, 0x6B, 0xC2, 0x02, 0x00, 0x54, 0x93, 0x02, 0x00, 0x91, 
-	0xE0, 0x03, 0x01, 0x91, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x03, 0x00, 0x00, 0x14, 
-	0xE0, 0x06, 0x00, 0xB5, 0x00, 0x00, 0x00, 0x94, 0x60, 0x02, 0x40, 0xF9, 0xE1, 0x03, 0x01, 0x91, 
-	0x22, 0x00, 0x80, 0x52, 0x00, 0xE0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x64, 0x02, 0x40, 0xF9, 
-	0x83, 0x08, 0x48, 0x29, 0x81, 0x48, 0x40, 0xB9, 0x63, 0x00, 0x02, 0x4B, 0x3F, 0x00, 0x03, 0x6B, 
-	0x83, 0xFE, 0xFF, 0x54, 0xE1, 0x03, 0x01, 0x91, 0x80, 0xE0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 
-	0x82, 0x02, 0x40, 0xF9, 0xE1, 0x03, 0x16, 0xAA, 0xE3, 0xF3, 0x00, 0x91, 0x40, 0x00, 0x01, 0x91, 
+	0xFD, 0x7B, 0xBC, 0xA9, 0x03, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 
+	0xF4, 0x03, 0x01, 0xAA, 0xF3, 0x03, 0x02, 0xAA, 0xF5, 0x13, 0x00, 0xF9, 0x15, 0x00, 0x00, 0x90, 
+	0x61, 0xCC, 0x42, 0xF9, 0xE1, 0x1F, 0x00, 0xF9, 0x01, 0x00, 0x80, 0xD2, 0xFF, 0x37, 0x00, 0xB9, 
+	0xA0, 0x02, 0x40, 0xF9, 0x00, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x03, 0x00, 0x35, 
+	0xA2, 0x02, 0x40, 0xF9, 0xE1, 0x03, 0x14, 0xAA, 0xE3, 0xD3, 0x00, 0x91, 0x40, 0x00, 0x01, 0x91, 
 	0x42, 0x40, 0x40, 0xB9, 0x05, 0x90, 0x40, 0x29, 0x84, 0x00, 0x05, 0x0B, 0x84, 0x00, 0x02, 0x4B, 
-	0x82, 0x04, 0x00, 0x11, 0x93, 0x04, 0x00, 0x11, 0x5F, 0x00, 0x15, 0xEB, 0x42, 0x90, 0x95, 0x9A, 
-	0x00, 0x00, 0x00, 0x94, 0xE2, 0x3F, 0x40, 0xB9, 0x85, 0x02, 0x40, 0xF9, 0xE4, 0x03, 0x13, 0x2A, 
-	0x13, 0x7C, 0x40, 0x93, 0xE3, 0x03, 0x15, 0xAA, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 
-	0xA0, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x00, 0x40, 0x02, 0x91, 
-	0x00, 0x00, 0x00, 0x94, 0xE0, 0x3F, 0x40, 0xB9, 0x7F, 0x02, 0x00, 0x71, 0x00, 0x00, 0x93, 0x9A, 
-	0x01, 0x41, 0x38, 0xD5, 0xE2, 0x37, 0x40, 0xF9, 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 
-	0x03, 0x00, 0x80, 0xD2, 0xA1, 0x01, 0x00, 0x54, 0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x5B, 0x42, 0xA9, 
-	0xFD, 0x7B, 0xC7, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x20, 0xFB, 0xFF, 0x34, 
-	0x80, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x40, 0x01, 0x80, 0x92, 0xF1, 0xFF, 0xFF, 0x17, 
-	0x40, 0x01, 0x80, 0x92, 0xEF, 0xFF, 0xFF, 0x17, 0x00, 0x00, 0x00, 0x94, 0x1F, 0x20, 0x03, 0xD5, 
-	0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBC, 0xA9, 
-	0x00, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 0x14, 0x00, 0x00, 0x90, 
-	0x03, 0xCC, 0x42, 0xF9, 0xE3, 0x1F, 0x00, 0xF9, 0x03, 0x00, 0x80, 0xD2, 0xFF, 0x37, 0x00, 0xB9, 
-	0x80, 0x02, 0x40, 0xF9, 0x00, 0xC0, 0x01, 0x91, 0xC1, 0x03, 0x00, 0xB4, 0xF3, 0x03, 0x01, 0xAA, 
-	0xF5, 0x13, 0x00, 0xF9, 0xF5, 0x03, 0x02, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x04, 0x00, 0x35, 
-	0x80, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x15, 0x2A, 0xE1, 0x03, 0x13, 0xAA, 0xE3, 0xD3, 0x00, 0x91, 
-	0x00, 0xA0, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, 0x13, 0x7C, 0x40, 0x93, 
-	0x20, 0xC0, 0x01, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x37, 0x40, 0xB9, 0x7F, 0x02, 0x00, 0x71, 
-	0xF5, 0x13, 0x40, 0xF9, 0x00, 0xA0, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, 0xE2, 0x1F, 0x40, 0xF9, 
-	0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, 0x81, 0x02, 0x00, 0x54, 
-	0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC4, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 
-	0x00, 0x00, 0x00, 0x94, 0x80, 0x01, 0x00, 0x35, 0x81, 0x02, 0x40, 0xF9, 0x20, 0xC0, 0x01, 0x91, 
-	0x22, 0x28, 0x40, 0xB9, 0x22, 0x2C, 0x00, 0xB9, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, 
-	0x22, 0x00, 0x80, 0x52, 0x00, 0x00, 0x80, 0xD2, 0x22, 0x18, 0x00, 0xB9, 0xEB, 0xFF, 0xFF, 0x17, 
-	0xF5, 0x13, 0x40, 0xF9, 0x60, 0x00, 0x80, 0x92, 0xE8, 0xFF, 0xFF, 0x17, 0xF5, 0x13, 0x00, 0xF9, 
-	0x00, 0x00, 0x00, 0x94, 0x04, 0x41, 0x38, 0xD5, 0x85, 0x2C, 0x40, 0xB9, 0xE3, 0x03, 0x00, 0xAA, 
-	0xE0, 0x03, 0x02, 0xAA, 0x45, 0x02, 0xA8, 0x36, 0x62, 0xDC, 0x40, 0x93, 0x62, 0x00, 0x02, 0x8A, 
-	0x04, 0x10, 0xC0, 0xD2, 0x84, 0x00, 0x00, 0xCB, 0x9F, 0x00, 0x02, 0xEB, 0x63, 0x01, 0x00, 0x54, 
-	0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBF, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0x63, 0xF8, 0x48, 0x92, 
-	0xE2, 0x03, 0x00, 0xAA, 0xE0, 0x03, 0x03, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xFD, 0x7B, 0xC1, 0xA8, 
-	0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0xC0, 0x03, 0x5F, 0xD6, 0x84, 0x00, 0x40, 0xF9, 
-	0xE2, 0x03, 0x03, 0xAA, 0x9F, 0x00, 0x06, 0x72, 0xC0, 0xFD, 0xFF, 0x54, 0xEB, 0xFF, 0xFF, 0x17, 
+	0x84, 0x04, 0x00, 0x11, 0x9F, 0x00, 0x13, 0xEB, 0x82, 0x90, 0x93, 0x9A, 0x00, 0x00, 0x00, 0x94, 
+	0x13, 0x7C, 0x40, 0x93, 0xA1, 0x02, 0x40, 0xF9, 0x20, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 
+	0xE0, 0x37, 0x40, 0xB9, 0x7F, 0x02, 0x00, 0x71, 0x00, 0x00, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, 
+	0xE2, 0x1F, 0x40, 0xF9, 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, 
+	0x01, 0x01, 0x00, 0x54, 0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x13, 0x40, 0xF9, 0xFD, 0x7B, 0xC4, 0xA8, 
+	0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x40, 0x01, 0x80, 0x92, 0xF4, 0xFF, 0xFF, 0x17, 
+	0x00, 0x00, 0x00, 0x94, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 
+	0xFD, 0x7B, 0xBC, 0xA9, 0x00, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 
+	0x14, 0x00, 0x00, 0x90, 0x03, 0xCC, 0x42, 0xF9, 0xE3, 0x1F, 0x00, 0xF9, 0x03, 0x00, 0x80, 0xD2, 
+	0xFF, 0x37, 0x00, 0xB9, 0x80, 0x02, 0x40, 0xF9, 0x00, 0xC0, 0x01, 0x91, 0xC1, 0x03, 0x00, 0xB4, 
+	0xF3, 0x03, 0x01, 0xAA, 0xF5, 0x13, 0x00, 0xF9, 0xF5, 0x03, 0x02, 0xAA, 0x00, 0x00, 0x00, 0x94, 
+	0xA0, 0x04, 0x00, 0x35, 0x80, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x15, 0x2A, 0xE1, 0x03, 0x13, 0xAA, 
+	0xE3, 0xD3, 0x00, 0x91, 0x00, 0xA0, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, 
+	0x13, 0x7C, 0x40, 0x93, 0x20, 0xC0, 0x01, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x37, 0x40, 0xB9, 
+	0x7F, 0x02, 0x00, 0x71, 0xF5, 0x13, 0x40, 0xF9, 0x00, 0xA0, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, 
+	0xE2, 0x1F, 0x40, 0xF9, 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, 
+	0x81, 0x02, 0x00, 0x54, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC4, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 
+	0xC0, 0x03, 0x5F, 0xD6, 0x00, 0x00, 0x00, 0x94, 0x80, 0x01, 0x00, 0x35, 0x81, 0x02, 0x40, 0xF9, 
+	0x20, 0xC0, 0x01, 0x91, 0x22, 0x28, 0x40, 0xB9, 0x22, 0x2C, 0x00, 0xB9, 0x00, 0x00, 0x00, 0x94, 
+	0x81, 0x02, 0x40, 0xF9, 0x22, 0x00, 0x80, 0x52, 0x00, 0x00, 0x80, 0xD2, 0x22, 0x18, 0x00, 0xB9, 
+	0xEB, 0xFF, 0xFF, 0x17, 0xF5, 0x13, 0x40, 0xF9, 0x60, 0x00, 0x80, 0x92, 0xE8, 0xFF, 0xFF, 0x17, 
+	0xF5, 0x13, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 
+	0x04, 0x41, 0x38, 0xD5, 0x85, 0x2C, 0x40, 0xB9, 0xE3, 0x03, 0x00, 0xAA, 0xE0, 0x03, 0x02, 0xAA, 
+	0x45, 0x02, 0xA8, 0x36, 0x62, 0xDC, 0x40, 0x93, 0x62, 0x00, 0x02, 0x8A, 0x04, 0x10, 0xC0, 0xD2, 
+	0x84, 0x00, 0x00, 0xCB, 0x9F, 0x00, 0x02, 0xEB, 0x63, 0x01, 0x00, 0x54, 0x3F, 0x23, 0x03, 0xD5, 
+	0xFD, 0x7B, 0xBF, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0x63, 0xF8, 0x48, 0x92, 0xE2, 0x03, 0x00, 0xAA, 
+	0xE0, 0x03, 0x03, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xFD, 0x7B, 0xC1, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 
+	0xC0, 0x03, 0x5F, 0xD6, 0xC0, 0x03, 0x5F, 0xD6, 0x84, 0x00, 0x40, 0xF9, 0xE2, 0x03, 0x03, 0xAA, 
+	0x9F, 0x00, 0x06, 0x72, 0xC0, 0xFD, 0xFF, 0x54, 0xEB, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 
 	0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0x01, 0x24, 0x40, 0xF9, 
 	0x21, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE2, 0x03, 0x01, 0x2A, 0x42, 0x00, 0x02, 0xCA, 
 	0x02, 0x00, 0x00, 0xB5, 0x22, 0x04, 0x80, 0x12, 0x21, 0x00, 0x02, 0x0A, 0x02, 0x24, 0x40, 0xF9, 
@@ -154,41 +144,16 @@ uint8_t smi_stream_dev[] = {
 	0xBF, 0x31, 0x03, 0xD5, 0xE0, 0x03, 0x06, 0x2A, 0x00, 0x00, 0x00, 0xCA, 0x00, 0x00, 0x00, 0xB5, 
 	0xE0, 0x00, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 
 	0x00, 0x00, 0x00, 0x94, 0xFD, 0x7B, 0xC1, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 
-	0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBD, 0xA9, 
-	0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 0xF4, 0x03, 0x00, 0xAA, 0xF5, 0x5B, 0x02, 0xA9, 
-	0x00, 0x20, 0x40, 0xB9, 0x95, 0x06, 0x40, 0xF9, 0x00, 0x04, 0x00, 0x11, 0x80, 0x22, 0x00, 0xB9, 
-	0x1F, 0xFC, 0x00, 0x71, 0x69, 0x04, 0x00, 0x54, 0x13, 0x7D, 0x80, 0x52, 0x05, 0x00, 0x00, 0x14, 
-	0xE0, 0x18, 0x82, 0xD2, 0x00, 0x00, 0x00, 0x94, 0x73, 0x06, 0x00, 0x71, 0xC0, 0x08, 0x00, 0x54, 
-	0xA1, 0x26, 0x40, 0xF9, 0x21, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE2, 0x03, 0x01, 0x2A, 
-	0x42, 0x00, 0x02, 0xCA, 0x02, 0x00, 0x00, 0xB5, 0xC1, 0xFE, 0x17, 0x37, 0xA0, 0x26, 0x40, 0xF9, 
-	0x00, 0x10, 0x00, 0x91, 0xBF, 0x32, 0x03, 0xD5, 0x01, 0x10, 0xA0, 0x52, 0x01, 0x00, 0x00, 0xB9, 
-	0x9F, 0x3F, 0x03, 0xD5, 0xA0, 0x26, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 
-	0xE1, 0x03, 0x00, 0x2A, 0x21, 0x00, 0x01, 0xCA, 0x01, 0x00, 0x00, 0xB5, 0x00, 0x00, 0x1D, 0x32, 
-	0x00, 0x3C, 0x00, 0x12, 0xA1, 0x26, 0x40, 0xF9, 0xBF, 0x32, 0x03, 0xD5, 0x20, 0x00, 0x00, 0xB9, 
-	0x9F, 0x3F, 0x03, 0xD5, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x40, 0xF9, 0x1F, 0x20, 0x00, 0xB9, 
-	0x82, 0xD2, 0x40, 0xB9, 0x80, 0x02, 0x01, 0x91, 0x83, 0x42, 0x40, 0xB9, 0xC4, 0xFF, 0xBF, 0x12, 
-	0x42, 0x04, 0x00, 0x11, 0x82, 0xD2, 0x00, 0xB9, 0x01, 0x04, 0x40, 0xB9, 0x53, 0x04, 0x6F, 0xD3, 
-	0xB6, 0x62, 0x40, 0xF9, 0x63, 0x00, 0x01, 0x4B, 0xC1, 0x02, 0x13, 0x8B, 0x7F, 0x00, 0x04, 0x6B, 
-	0x28, 0x03, 0x00, 0x54, 0x80, 0xD6, 0x40, 0xB9, 0x00, 0x04, 0x00, 0x11, 0x80, 0xD6, 0x00, 0xB9, 
-	0xE1, 0xD1, 0x8B, 0x52, 0xE0, 0x42, 0x8D, 0x52, 0x21, 0x63, 0xBB, 0x72, 0xC0, 0x49, 0xA0, 0x72, 
-	0x42, 0x7C, 0x01, 0x1B, 0x5F, 0x00, 0x00, 0x6B, 0xE9, 0x02, 0x00, 0x54, 0xA0, 0xA2, 0x02, 0x91, 
-	0x00, 0x00, 0x00, 0x94, 0x20, 0x00, 0x80, 0x52, 0x80, 0x66, 0x03, 0x39, 0x22, 0x00, 0x80, 0x52, 
-	0x80, 0xE2, 0x02, 0x91, 0xE1, 0x03, 0x02, 0x2A, 0x03, 0x00, 0x80, 0xD2, 0x00, 0x00, 0x00, 0x94, 
-	0xF3, 0x53, 0x41, 0xA9, 0xF5, 0x5B, 0x42, 0xA9, 0xFD, 0x7B, 0xC3, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 
-	0xC0, 0x03, 0x5F, 0xD6, 0x42, 0x00, 0xA0, 0x52, 0x00, 0x00, 0x00, 0x94, 0x82, 0xD2, 0x40, 0xB9, 
-	0xE8, 0xFF, 0xFF, 0x17, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 
-	0xBF, 0xFF, 0xFF, 0x17, 0xC4, 0x6A, 0x73, 0xB8, 0x01, 0x00, 0x00, 0x90, 0x82, 0xD6, 0x40, 0xB9, 
-	0x21, 0x00, 0x00, 0x91, 0xA3, 0xAE, 0x40, 0xB9, 0x80, 0x02, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 
-	0xE3, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 
-	0xFD, 0x7B, 0xBE, 0xA9, 0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 
-	0xF3, 0x03, 0x00, 0xAA, 0x20, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 
-	0x00, 0xE0, 0x05, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0x14, 0x2C, 0x40, 0xF9, 
-	0x81, 0x02, 0x40, 0xF9, 0x21, 0xA4, 0x40, 0xF9, 0x41, 0x01, 0x00, 0xB4, 0xE0, 0x03, 0x14, 0xAA, 
-	0x20, 0x00, 0x3F, 0xD6, 0xC0, 0x00, 0x00, 0x35, 0x80, 0x02, 0x40, 0xF9, 0x01, 0xA8, 0x40, 0xF9, 
-	0x61, 0x00, 0x00, 0xB4, 0xE0, 0x03, 0x14, 0xAA, 0x20, 0x00, 0x3F, 0xD6, 0x60, 0x06, 0x40, 0xF9, 
-	0x00, 0xE0, 0x05, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0xB1, 0xFE, 0xFF, 0x97, 
-	0x60, 0x06, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x7F, 0xB6, 0x01, 0x79, 0xF3, 0x53, 0x41, 0xA9, 
-	0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 
+	0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBE, 0xA9, 
+	0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 0xF3, 0x03, 0x00, 0xAA, 
+	0x20, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0x00, 0xE0, 0x05, 0x91, 
+	0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0x14, 0x2C, 0x40, 0xF9, 0x81, 0x02, 0x40, 0xF9, 
+	0x21, 0xA4, 0x40, 0xF9, 0x41, 0x01, 0x00, 0xB4, 0xE0, 0x03, 0x14, 0xAA, 0x20, 0x00, 0x3F, 0xD6, 
+	0xC0, 0x00, 0x00, 0x35, 0x80, 0x02, 0x40, 0xF9, 0x01, 0xA8, 0x40, 0xF9, 0x61, 0x00, 0x00, 0xB4, 
+	0xE0, 0x03, 0x14, 0xAA, 0x20, 0x00, 0x3F, 0xD6, 0x60, 0x06, 0x40, 0xF9, 0x00, 0xE0, 0x05, 0x91, 
+	0x00, 0x00, 0x00, 0x94, 0x60, 0x06, 0x40, 0xF9, 0x16, 0xFF, 0xFF, 0x97, 0x60, 0x06, 0x40, 0xF9, 
+	0x00, 0x00, 0x00, 0x94, 0x7F, 0xB6, 0x01, 0x79, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 
+	0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 
 	0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBC, 0xA9, 
 	0x01, 0x00, 0x00, 0x90, 0xFD, 0x03, 0x00, 0x91, 0x21, 0x00, 0x00, 0x91, 0x22, 0x00, 0x80, 0x52, 
 	0xF3, 0x53, 0x01, 0xA9, 0xF3, 0x03, 0x00, 0x2A, 0xF5, 0x5B, 0x02, 0xA9, 0x20, 0xCC, 0x40, 0xB9, 
@@ -201,248 +166,250 @@ uint8_t smi_stream_dev[] = {
 	0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 
 	0x00, 0xC0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x68, 0x40, 0xB9, 
 	0x3F, 0x00, 0x13, 0x6B, 0xC0, 0x01, 0x00, 0x54, 0xF7, 0x1B, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, 
-	0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x75, 0xFD, 0xFF, 0x97, 
+	0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x01, 0xFE, 0xFF, 0x97, 
 	0x15, 0x00, 0x1E, 0x12, 0xC0, 0x01, 0x10, 0x36, 0xE0, 0xC2, 0x02, 0x91, 0x55, 0x01, 0x80, 0x12, 
 	0x00, 0x00, 0x00, 0x94, 0xF7, 0x1B, 0x40, 0xF9, 0xDD, 0xFF, 0xFF, 0x17, 0x00, 0xC0, 0x02, 0x91, 
 	0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 
 	0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xD5, 0xFF, 0xFF, 0x17, 0xE0, 0x06, 0x40, 0xF9, 
-	0xFF, 0x6A, 0x00, 0xB9, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0x13, 0x02, 0x00, 0x34, 
+	0xFF, 0x6A, 0x00, 0xB9, 0x01, 0x00, 0x80, 0x52, 0x00, 0x00, 0x00, 0x94, 0xF3, 0x02, 0x00, 0x34, 
 	0x80, 0x02, 0x40, 0xF9, 0xE1, 0x03, 0x16, 0x2A, 0x00, 0x04, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 
-	0x80, 0x02, 0x40, 0xF9, 0x7F, 0x0E, 0x00, 0x71, 0xE1, 0x01, 0x00, 0x54, 0x02, 0x00, 0x00, 0x90, 
-	0x21, 0x00, 0x80, 0x52, 0x42, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0xF5, 0x03, 0x00, 0x2A, 
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+	0x38, 0x58, 0x20, 0x73, 0x6D, 0x69, 0x64, 0x73, 0x20, 0x25, 0x30, 0x38, 0x58, 0x20, 0x73, 0x6D, 
+	0x69, 0x73, 0x77, 0x30, 0x20, 0x25, 0x30, 0x38, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
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+	0x25, 0x30, 0x38, 0x58, 0x20, 0x73, 0x6D, 0x69, 0x6C, 0x20, 0x25, 0x30, 0x38, 0x58, 0x20, 0x73, 
+	0x6D, 0x69, 0x64, 0x73, 0x20, 0x25, 0x30, 0x38, 0x58, 0x20, 0x73, 0x6D, 0x69, 0x73, 0x77, 0x30, 
+	0x20, 0x25, 0x30, 0x38, 0x58, 0x00, 0x00, 0x00, 0x53, 0x74, 0x61, 0x72, 0x74, 0x69, 0x6E, 0x67, 
 	0x20, 0x63, 0x79, 0x63, 0x6C, 0x69, 0x63, 0x20, 0x74, 0x72, 0x61, 0x6E, 0x73, 0x66, 0x65, 0x72, 
 	0x2C, 0x20, 0x64, 0x6D, 0x61, 0x20, 0x64, 0x69, 0x72, 0x3A, 0x20, 0x25, 0x64, 0x00, 0x00, 0x00, 
 	0x73, 0x6D, 0x69, 0x5F, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6C, 0x65, 0x5F, 0x73, 0x79, 0x6E, 0x63, 
@@ -684,8 +641,8 @@ uint8_t smi_stream_dev[] = {
 	0x66, 0x66, 0x73, 0x65, 0x74, 0x3A, 0x69, 0x6E, 0x74, 0x00, 0x70, 0x61, 0x72, 0x6D, 0x74, 0x79, 
 	0x70, 0x65, 0x3D, 0x66, 0x69, 0x66, 0x6F, 0x5F, 0x6D, 0x74, 0x75, 0x5F, 0x6D, 0x75, 0x6C, 0x74, 
 	0x69, 0x70, 0x6C, 0x69, 0x65, 0x72, 0x3A, 0x69, 0x6E, 0x74, 0x00, 0x73, 0x72, 0x63, 0x76, 0x65, 
-	0x72, 0x73, 0x69, 0x6F, 0x6E, 0x3D, 0x33, 0x41, 0x41, 0x44, 0x46, 0x34, 0x41, 0x46, 0x34, 0x44, 
-	0x35, 0x33, 0x46, 0x43, 0x39, 0x31, 0x43, 0x31, 0x32, 0x39, 0x36, 0x35, 0x44, 0x00, 0x61, 0x6C, 
+	0x72, 0x73, 0x69, 0x6F, 0x6E, 0x3D, 0x44, 0x43, 0x34, 0x32, 0x30, 0x43, 0x32, 0x36, 0x37, 0x36, 
+	0x36, 0x38, 0x46, 0x42, 0x38, 0x37, 0x41, 0x32, 0x43, 0x38, 0x31, 0x35, 0x39, 0x00, 0x61, 0x6C, 
 	0x69, 0x61, 0x73, 0x3D, 0x6F, 0x66, 0x3A, 0x4E, 0x2A, 0x54, 0x2A, 0x43, 0x62, 0x72, 0x63, 0x6D, 
 	0x2C, 0x62, 0x63, 0x6D, 0x32, 0x38, 0x33, 0x35, 0x2D, 0x73, 0x6D, 0x69, 0x2D, 0x64, 0x65, 0x76, 
 	0x43, 0x2A, 0x00, 0x61, 0x6C, 0x69, 0x61, 0x73, 0x3D, 0x6F, 0x66, 0x3A, 0x4E, 0x2A, 0x54, 0x2A, 
@@ -707,8 +664,8 @@ uint8_t smi_stream_dev[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 
 	0x05, 0x00, 0x00, 0x00, 0x47, 0x4E, 0x55, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x04, 0x00, 0x00, 0x00, 
 	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 
-	0x03, 0x00, 0x00, 0x00, 0x47, 0x4E, 0x55, 0x00, 0x83, 0x60, 0xC2, 0xE5, 0x66, 0x77, 0xC1, 0x1C, 
-	0xC1, 0x86, 0x63, 0xA3, 0xEC, 0x00, 0x24, 0x78, 0x14, 0x9F, 0x97, 0xA1, 0x06, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x47, 0x4E, 0x55, 0x00, 0x8A, 0x7D, 0x31, 0xFB, 0x47, 0x0F, 0xE3, 0xDD, 
+	0x6E, 0xEB, 0x37, 0xC3, 0x3F, 0xF4, 0x31, 0x0D, 0x23, 0x87, 0x9A, 0x79, 0x06, 0x00, 0x00, 0x00, 
 	0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x4C, 0x69, 0x6E, 0x75, 0x78, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 
 	0x4C, 0x69, 0x6E, 0x75, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -740,22 +697,6 @@ uint8_t smi_stream_dev[] = {
 	0x63, 0x6B, 0x5F, 0x69, 0x6E, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x69, 0x62, 0x6C, 0x65, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x75, 0x79, 0x48, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x69, 0x6E, 0x69, 0x74, 0x5F, 0x77, 0x61, 0x69, 
-	0x74, 0x5F, 0x65, 0x6E, 0x74, 0x72, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x51, 0x0E, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x73, 0x63, 0x68, 0x65, 0x64, 0x75, 0x6C, 0x65, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x95, 0xD4, 0x26, 0x8C, 0x00, 0x00, 0x00, 0x00, 0x70, 0x72, 0x65, 0x70, 0x61, 0x72, 0x65, 0x5F, 
-	0x74, 0x6F, 0x5F, 0x77, 0x61, 0x69, 0x74, 0x5F, 0x65, 0x76, 0x65, 0x6E, 0x74, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xBF, 0x0F, 0x54, 0x92, 0x00, 0x00, 0x00, 0x00, 0x66, 0x69, 0x6E, 0x69, 0x73, 0x68, 0x5F, 0x77, 
-	0x61, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x26, 0x08, 0xA8, 0x30, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x5F, 0x6B, 0x66, 0x69, 0x66, 0x6F, 0x5F, 
 	0x66, 0x72, 0x6F, 0x6D, 0x5F, 0x75, 0x73, 0x65, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -840,14 +781,6 @@ uint8_t smi_stream_dev[] = {
 	0x69, 0x6E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xD6, 0xDF, 0xE3, 0xEA, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x5F, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x5F, 
-	0x75, 0x64, 0x65, 0x6C, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xF7, 0xAD, 0xD0, 0x13, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x5F, 0x6B, 0x66, 0x69, 0x66, 0x6F, 0x5F, 
-	0x6F, 0x75, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x64, 0xBD, 0x8F, 0xBA, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x72, 0x61, 0x77, 0x5F, 0x73, 0x70, 0x69, 
 	0x6E, 0x5F, 0x6C, 0x6F, 0x63, 0x6B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -917,8 +850,7 @@ uint8_t smi_stream_dev[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 
-	0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -1032,302 +964,285 @@ uint8_t smi_stream_dev[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
 	0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x5F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x78, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
-	0xA0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xD0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
+	0xF4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x05, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x00, 0x02, 0x00, 0x07, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xD3, 0x05, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x94, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x8A, 0x05, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0xF0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBF, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
-	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xD0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x90, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x60, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xD0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xED, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
-	0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x0B, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x60, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xA4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x02, 0x00, 0x07, 0x00, 
-	0xCC, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x28, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x04, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 
-	0x24, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x49, 0x01, 0x00, 0x00, 0x01, 0x00, 0x0C, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 
+	0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xF7, 0x00, 0x00, 0x00, 0x02, 0x00, 0x07, 0x00, 0xCC, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
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-	0x1B, 0x01, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x90, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xD4, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
-	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x58, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x60, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xB8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xE8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x58, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xB8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x6E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x2C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x70, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xD0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x34, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x70, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xD0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x44, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x90, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x4C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 
+	0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x4C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x1E, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x6C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x98, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x98, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x74, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 
+	0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x74, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x9C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0xA0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xA0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xA4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 
+	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xA4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xA8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xD4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0xA8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xEC, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x1E, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -1879,132 +1762,126 @@ uint8_t smi_stream_dev[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x30, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0xB0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xB0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x38, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 
+	0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x38, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x50, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0xE8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xE8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x5C, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x7B, 0x00, 0x00, 0x00, 
+	0x48, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x48, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x5C, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x60, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x7C, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x18, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x18, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x84, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 
+	0x78, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x84, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xA4, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x71, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xA4, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x6E, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB8, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xC0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x20, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x28, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 
+	0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x1B, 0x01, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x28, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x1E, 0x01, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x90, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x48, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x13, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xA8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0xA4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 
-	0x48, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA8, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x1B, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
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@@ -2014,223 +1891,222 @@ uint8_t smi_stream_dev[] = {
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x6C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD4, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xA0, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xA0, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDF, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x90, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x25, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x20, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x21, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x22, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x28, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x10, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x25, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2E, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x88, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x25, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x08, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xA0, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x25, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x53, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x40, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4E, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xB8, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x25, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6D, 0x01, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x80, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x82, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x58, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 
-	0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x09, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x35, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x11, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x8B, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x80, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 
+	0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x80, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xD0, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x26, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x80, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xE8, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 };
 
 #ifdef __cplusplus
diff --git a/software/libcariboulite/src/cariboulite_fpga_firmware.h b/software/libcariboulite/src/cariboulite_fpga_firmware.h
index d76d608..e610570 100644
--- a/software/libcariboulite/src/cariboulite_fpga_firmware.h
+++ b/software/libcariboulite/src/cariboulite_fpga_firmware.h
@@ -17,15 +17,15 @@ extern "C" {
 
 /*
  * Time tagging of the module through the 'struct tm' structure 
- *     Date: 2024-03-15
- *     Time: 03:49:31
+ *     Date: 2024-04-09
+ *     Time: 13:13:50
  */
 struct tm cariboulite_firmware_date_time = {
-   .tm_sec = 31,
-   .tm_min = 49,
-   .tm_hour = 3,
-   .tm_mday = 15,
-   .tm_mon = 2,   /* +1    */
+   .tm_sec = 50,
+   .tm_min = 13,
+   .tm_hour = 13,
+   .tm_mday = 9,
+   .tm_mon = 3,   /* +1    */
    .tm_year = 124,  /* +1900 */
 };
 
@@ -38,382 +38,382 @@ uint8_t cariboulite_firmware[] = {
 	0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 
 	0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 
+	0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 
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+	0x00, 0x00, 0x01, 0x08, 0xDC, 0x2A, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 
+	0x08, 0x0D, 0x00, 0x00, 0x00, 0x14, 0x00, 0x0A, 0xCC, 0x09, 0x40, 0x00, 0x98, 0x00, 0x00, 0x01, 
+	0x82, 0x00, 0x00, 0x00, 0x1C, 0xC9, 0x90, 0x90, 0x00, 0x00, 0x00, 0x00, 0x01, 0xE3, 0x02, 0x05, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x03, 0x9C, 0x00, 0x00, 0x04, 0x18, 0x00, 
+	0x04, 0x83, 0x38, 0x00, 0x00, 0x08, 0x01, 0x52, 0x45, 0x00, 0x40, 0x00, 0x80, 0x01, 0xC0, 0x00, 
+	0x01, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x0B, 0xA0, 0x40, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x91, 0x03, 0x00, 0x00, 0xAB, 0x40, 0x00, 0x20, 0xCC, 0x01, 0x00, 0x00, 0x10, 
+	0x90, 0xF8, 0x50, 0x00, 0x00, 0x14, 0x40, 0x3E, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
+	0x05, 0xAF, 0x88, 0x80, 0x04, 0x95, 0x40, 0x00, 0x81, 0x04, 0x00, 0x00, 0x50, 0x00, 0x18, 0x00, 
+	0x00, 0x00, 0x00, 0x0E, 0x83, 0x3A, 0x00, 0x08, 0x03, 0x80, 0x18, 0x59, 0x80, 0x40, 0x08, 0x06, 
+	0x28, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x80, 0x80, 0x0A, 0xB8, 0x80, 0x00, 0x20, 0x80, 
+	0x00, 0x10, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xE9, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0xCC, 0x00, 
+	0x01, 0x00, 0x08, 0x00, 0xA5, 0x98, 0x01, 0x08, 0x03, 0x64, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x30, 0x03, 0x82, 0x05, 0x00, 0x00, 0x09, 0x40, 0x01, 0xC1, 0x04, 0x00, 0x00, 0x00, 
+	0x0E, 0x80, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x83, 0x38, 0x00, 0x10, 0x00, 0x00, 0x5A, 0x83, 0x00, 
+	0x10, 0x00, 0x06, 0x66, 0xEA, 0xF0, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0xA0, 0x40, 
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 
+	0x20, 0xCC, 0x00, 0x80, 0x80, 0x00, 0x0D, 0x34, 0xF0, 0x00, 0x00, 0x00, 0x26, 0x5F, 0x0F, 0xA2, 
+	0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x04, 0xF0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x01, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x38, 0x01, 0x00, 0x01, 0x00, 
+	0x98, 0x30, 0xC0, 0x0C, 0xA0, 0x34, 0x00, 0x0F, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 
+	0x03, 0x8F, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x00, 0x08, 0x03, 0x00, 0x00, 
+	0x00, 0x80, 0x20, 0x0E, 0xCC, 0x00, 0x80, 0x00, 0x08, 0x01, 0xA0, 0xF0, 0x00, 0x40, 0x02, 0x60, 
+	0x01, 0xE3, 0x30, 0x10, 0x00, 0x00, 0x11, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -421,26 +421,26 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0xF0, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -448,19 +448,10 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -468,696 +459,705 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAD, 0xB0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x41, 0xDB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x14, 0x03, 0xC4, 0x00, 0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
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-	0x40, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x20, 0xF0, 0x00, 
-	0xC8, 0x00, 0x53, 0x02, 0x01, 0x32, 0x00, 0x01, 0x40, 0x10, 0x50, 0xA2, 0x00, 0x00, 0x00, 0x27, 
-	0xC0, 0x00, 0x00, 0x10, 0x22, 0x08, 0x01, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 
-	0x78, 0x00, 0x00, 0x04, 0x00, 0x80, 0x01, 0x80, 0x00, 0x00, 0x10, 0x18, 0x39, 0xE0, 0x00, 0x84, 
-	0x00, 0x90, 0x20, 0x05, 0x80, 0x00, 0x10, 0x02, 0x40, 0x80, 0x06, 0x00, 0x00, 0x40, 0x00, 0x00, 
-	0x00, 0x19, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x40, 0x10, 0x00, 0x80, 
-	0x10, 0xF0, 0x90, 0x00, 0x40, 0xF6, 0x42, 0x00, 0x00, 0x10, 0x00, 0x01, 0xC0, 0x00, 0xE0, 0x00, 
-	0x48, 0x00, 0x09, 0x00, 0x20, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x04, 0x20, 0x70, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x39, 0xC0, 0x10, 0x01, 0x00, 0x08, 0x00, 0x00, 
-	0x07, 0x90, 0x53, 0x80, 0x29, 0x40, 0xC1, 0x19, 0x04, 0x08, 0x02, 0x00, 0x02, 0xA4, 0x04, 0x04, 
-	0x20, 0x00, 0x00, 0x00, 0xD8, 0x00, 0x00, 0x82, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x08, 0x03, 0x6D, 0xCA, 0x00, 0xF0, 0x00, 0x80, 0x03, 0x80, 0x78, 0xF2, 0x20, 0x03, 0xFC, 0x1A, 
-	0x00, 0x80, 0x00, 0xC0, 0x02, 0x00, 0x42, 0x62, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x80, 0x00, 
-	0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 0x01, 0x00, 0x01, 0x14, 0x16, 0xE8, 0x08, 0x00, 
-	0x00, 0x00, 0x05, 0xE0, 0x28, 0x50, 0x00, 0x91, 0xE4, 0x18, 0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x20, 0x00, 0x00, 0x08, 0x09, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x08, 0x01, 0x40, 0x00, 0xB0, 0x00, 0x00, 0x00, 0x03, 0x80, 0x01, 0x32, 0x00, 
-	0x02, 0x2C, 0xEE, 0xB0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x40, 0x03, 0x00, 0x80, 0x00, 0x04, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x13, 0xFC, 
-	0xC0, 0x1A, 0x00, 0x80, 0x00, 0x06, 0x00, 0x24, 0x00, 0x00, 0x01, 0x16, 0x01, 0x80, 0x00, 0x01, 
-	0x00, 0x81, 0x06, 0xD6, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x3F, 0xE0, 0x00, 0x00, 0x04, 0x00, 0x02, 0xEC, 
-	0x3D, 0x70, 0x00, 0x00, 0x20, 0x6F, 0x00, 0x00, 0x10, 0x00, 0x80, 0x03, 0x7C, 0x02, 0x88, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x7C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, 0xA1, 
-	0x98, 0x01, 0x40, 0x00, 0x00, 0x07, 0x16, 0x00, 0x00, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 
-	0x00, 0x06, 0x40, 0x20, 0x00, 0x00, 0x00, 0x92, 0xCD, 0x00, 0x00, 0x08, 0x00, 0x08, 0x1F, 0x68, 
-	0x40, 0x00, 0x00, 0x80, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x18, 0x00, 0x00, 0x00, 0x05, 0xE7, 0x80, 0x00, 0x00, 
-	0x1F, 0xB5, 0x95, 0x00, 0x04, 0x01, 0x08, 0x01, 0xD6, 0xA0, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x30, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x10, 0x00, 0x00, 0x00, 0x03, 0x82, 0x00, 0x30, 0x00, 0x22, 0xD5, 0x58, 0x08, 0x00, 0x00, 0x00, 
-	0x00, 0x1B, 0x41, 0x40, 0x00, 0x50, 0x00, 0x04, 0x00, 0xF0, 0x80, 0x0C, 0x00, 0x00, 0x00, 0x00, 
-	0x20, 0x00, 0x68, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00, 0x08, 0x00, 0x01, 0xC2, 
-	0x40, 0x03, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x20, 0xF0, 0x06, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0xA4, 0x34, 0x00, 0x20, 0x00, 0x40, 0x0A, 0x00, 
-	0x81, 0x00, 0x00, 0x41, 0x0B, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x08, 0x07, 0x5E, 0x34, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x80, 0x10, 0x0C, 0x37, 0x20, 
+	0x03, 0xC0, 0x00, 0x00, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0xAF, 0x60, 0x80, 0x00, 0x00, 0x00, 0x00, 0x05, 0xE7, 0x90, 0x00, 0x80, 
+	0x80, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x29, 0x02, 0x00, 0x00, 0x00, 0x00, 
+	0x98, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x61, 0xCB, 
+	0x00, 0x0A, 0x00, 0x00, 0x03, 0xC2, 0x3A, 0x00, 0x00, 0x00, 0x40, 0x09, 0x00, 0x00, 0x10, 0x00, 
+	0x00, 0x00, 0x00, 0x44, 0x27, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x01, 0xC7, 
+	0x80, 0x03, 0x80, 0x82, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x12, 0xC0, 0x3C, 0x00, 0x30, 
+	0x01, 0x68, 0x0D, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x40, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 
+	0x01, 0x80, 0x00, 0x00, 0x50, 0xE8, 0x07, 0x80, 0x03, 0x44, 0x00, 0x00, 0x80, 0x00, 0x80, 0x0C, 
 	0x00, 0x00, 0x11, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -1165,373 +1165,373 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 
+	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 
-	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x20, 0x00, 0x2C, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x40, 0x04, 0x00, 0x40, 
+	0x30, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x40, 
 	0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 
+	0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 
+	0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC0, 
 	0x08, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x20, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x02, 0x40, 0x00, 
+	0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x02, 0x80, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
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-	0xA0, 0x00, 0xA0, 0x24, 0x00, 0x01, 0x60, 0x00, 0x03, 0x00, 0xA8, 0x0C, 0x11, 0x80, 0x00, 0x08, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0xC5, 0x0B, 0x00, 0x84, 0x8C, 0x20, 0x00, 0x00, 
-	0x21, 0x00, 0x10, 0x00, 0x83, 0xEE, 0x00, 0x0B, 0xC0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x08, 
-	0x00, 0x01, 0x50, 0x00, 0x05, 0x20, 0xE0, 0x00, 0x68, 0x00, 0x60, 0x04, 0x00, 0x00, 0x0D, 0xA0, 
-	0x00, 0x40, 0x10, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x7C, 0x09, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x67, 0xE7, 0x00, 0x00, 0x00, 0x08, 
-	0x04, 0x1B, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0B, 0x47, 0xDC, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x82, 0xD8, 0x80, 0x00, 0x00, 0x20, 0x40, 0x8F, 0x82, 0xE7, 0x00, 0x00, 0x00, 
-	0xA9, 0x40, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x24, 0x01, 0x10, 
-	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x14, 0x00, 
-	0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x80, 
-	0x00, 0x00, 0x00, 0x00, 0x02, 0x08, 0xF2, 0x00, 0x81, 0x80, 0x00, 0x90, 0x20, 0x81, 0x80, 0x00, 
-	0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE0, 
-	0x00, 0x00, 0x02, 0x02, 0x9E, 0x97, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4C, 
-	0xC3, 0xE1, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x02, 0x07, 0xD9, 0x78, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x31, 0xF8, 0xF1, 0x80, 0x04, 0x28, 0x20, 
-	0x85, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x29, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x10, 0xAC, 0x00, 0x80, 0x00, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 
-	0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 
-	0x68, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x1A, 0x18, 0x00, 
-	0x00, 0x38, 0x60, 0x00, 0x00, 0x40, 0x01, 0x00, 0xA0, 0x90, 0x00, 0x05, 0x80, 0x00, 0x00, 0x00, 
-	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x04, 0x00, 0xF0, 0x00, 0x40, 0x40, 0x00, 
-	0x00, 0x00, 0x28, 0x00, 0x40, 0x00, 0x01, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x08, 0xDE, 0xC0, 0x00, 
-	0x10, 0x00, 0x08, 0x01, 0xC0, 0x50, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 
-	0x7D, 0x70, 0x00, 0x00, 0x00, 0x00, 0x0D, 0xA8, 0x00, 0x00, 0x00, 0x20, 0x90, 0x20, 0x08, 0x00, 
-	0x41, 0x00, 0x00, 0x00, 0x01, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, 0x27, 0x80, 0x00, 0x00, 0x80, 0x04, 0x5A, 
-	0x06, 0xDE, 0x01, 0x25, 0x02, 0x08, 0x02, 0xC0, 0x00, 0x04, 0x00, 0x00, 0x00, 0x30, 0x06, 0x40, 
-	0x00, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x91, 0x69, 0x50, 0xA0, 0x04, 0x00, 0x0F, 0xF0, 0x6A, 0x60, 0x20, 0x00, 0x00, 0x90, 
-	0x20, 0x00, 0x00, 0x20, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x8C, 0x00, 0x00, 0x00, 0x10, 0x70, 0x00, 0x4C, 0xDD, 0x00, 0x00, 0x00, 
-	0x0C, 0x00, 0x00, 0x90, 0x24, 0x34, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0xC3, 0x00, 
-	0x00, 0x00, 0x40, 0x80, 0x00, 0x00, 0x05, 0x30, 0x00, 0x00, 0x00, 0x10, 0x00, 0x04, 0x80, 0x00, 
-	0x00, 0x02, 0x03, 0x00, 0x0B, 0x30, 0x4E, 0x00, 0x00, 0x00, 0xF0, 0x24, 0x00, 0x02, 0x40, 0x43, 
-	0x03, 0x00, 0x02, 0x1E, 0x07, 0x80, 0x80, 0x88, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x01, 0x00, 0x00, 0x00, 0x0F, 0x10, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x28, 0x3C, 
-	0x00, 0x0E, 0x00, 0x86, 0x00, 0x10, 0x03, 0x40, 0x38, 0x00, 0x10, 0x08, 0x80, 0x10, 0x00, 0x04, 
-	0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x01, 0xE4, 
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x55, 0x42, 0x0E, 0x19, 0x90, 0x05, 0x30, 0x20, 0x00, 
-	0x04, 0x00, 0x00, 0x04, 0x04, 0x80, 0x00, 0xC0, 0x00, 0x80, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x28, 0x80, 
-	0x10, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x04, 0x70, 0x9A, 0xD4, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x00, 0x18, 0x38, 0x00, 0x00, 
-	0x00, 0x0B, 0x05, 0x04, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x01, 0x8B, 0x68, 0x00, 0x00, 0x00, 0x00, 0x16, 0x80, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 
 	0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
@@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8D, 0x0D, 0x01, 0x06, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8B, 0x30, 0x01, 0x06, 0x00, 
 };
 
 #ifdef __cplusplus