diff --git a/driver/install.sh b/driver/install.sh index df0bca8..74ea739 100755 --- a/driver/install.sh +++ b/driver/install.sh @@ -15,7 +15,7 @@ USERSPACE_SMI_DIR="../software/libcariboulite/src/caribou_smi/kernel" ## FUNCTIONS install() { - local mtu_mult=${1:-6} + local mtu_mult=${1:-16} local dir_offs=${2:-2} local ch_offs=${3:-3} diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c index 97a7788..0c27b5c 100644 --- a/driver/smi_stream_dev.c +++ b/driver/smi_stream_dev.c @@ -262,11 +262,11 @@ static int set_state(smi_stream_state_en new_state) if (new_state == smi_stream_tx_channel) { - ret = transfer_thread_init(inst,DMA_MEM_TO_DEV,stream_smi_write_dma_callback); + ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback); } else { - ret = transfer_thread_init(inst,DMA_DEV_TO_MEM,stream_smi_read_dma_callback); + ret = transfer_thread_init(inst, DMA_DEV_TO_MEM, stream_smi_read_dma_callback); } // if starting the transfer succeeded update the state @@ -329,12 +329,14 @@ static int smi_disable_sync(struct bcm2835_smi_instance *smi_inst) } +/***************************************************************************/ static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers) { int smics_temp = 0; //print_smil_registers_ext("refresh 1"); write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting //print_smil_registers_ext("refresh 2"); + // Start the transaction smics_temp = read_smi_reg(smi_inst, SMICS); smics_temp |= SMICS_START; @@ -345,7 +347,7 @@ static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int n } /***************************************************************************/ -static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, enum dma_transfer_direction dma_dir,int num_transfers) +static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, enum dma_transfer_direction dma_dir, int num_transfers) { int smics_temp = 0; int success = 0; @@ -597,6 +599,7 @@ static void stream_smi_read_dma_callback(void *param) inst->current_read_chunk++; } +/***************************************************************************/ static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) { struct bcm2835_smi_instance *smi_inst = inst->smi_inst; @@ -621,6 +624,7 @@ static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) } } +/***************************************************************************/ static void stream_smi_write_dma_callback(void *param) { /* Notify the bottom half that a chunk is ready for user copy */ @@ -656,7 +660,7 @@ static void stream_smi_write_dma_callback(void *param) } - +/***************************************************************************/ static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm2835_smi_instance *inst, enum dma_transfer_direction dir, dma_async_tx_callback callback, void*param) @@ -691,14 +695,13 @@ static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm28 * ***************************************************************************/ -int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfer_direction dir,dma_async_tx_callback callback) +int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfer_direction dir, dma_async_tx_callback callback) { - unsigned int errors = 0; int ret; int success; - dev_info(inst->dev, "Starting cyclic transfer"); + dev_info(inst->dev, "Starting cyclic transfer, dma dir: %d", dir); inst->transfer_thread_running = true; /* Disable the peripheral: */ @@ -723,6 +726,7 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe { spin_unlock(&inst->smi_inst->transaction_lock); } + inst->current_read_chunk = 0; inst->counter_missed = 0; if(!errors) @@ -896,6 +900,7 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr num_to_push = num_bytes_available > count ? count : num_bytes_available; ret = kfifo_from_user(&inst->tx_fifo, user_ptr, num_to_push, &actual_copied); + //dev_info(inst->dev, "smi_stream_write_file: pushed %ld bytes of %ld, available was %ld", actual_copied, count, num_bytes_available); mutex_unlock(&inst->write_lock); return ret ? ret : (ssize_t)actual_copied; @@ -949,6 +954,7 @@ static dev_t smi_stream_devid; static struct class *smi_stream_class; static struct device *smi_stream_dev; +/***************************************************************************/ static int smi_stream_dev_probe(struct platform_device *pdev) { int err; diff --git a/examples/cpp_api/async_sample_process/CMakeLists.txt b/examples/cpp_api/async_sample_process/CMakeLists.txt new file mode 100644 index 0000000..7562635 --- /dev/null +++ b/examples/cpp_api/async_sample_process/CMakeLists.txt @@ -0,0 +1,15 @@ +cmake_minimum_required(VERSION 3.2) +project(test_app) + +# Find the package using pkg-config +find_package(PkgConfig REQUIRED) +pkg_check_modules(CARIBOULITE REQUIRED cariboulite) + +# Add the executable +add_executable(test_app main.cpp) + +# Include directories from the cariboulite package +target_include_directories(test_app PRIVATE ${CARIBOULITE_INCLUDE_DIRS}) + +# Link against the cariboulite library +target_link_libraries(test_app PRIVATE ${CARIBOULITE_LIBRARIES} -lcariboulite) diff --git a/examples/cpp_api/async_sample_process/circular_buffer.hpp b/examples/cpp_api/async_sample_process/circular_buffer.hpp new file mode 100644 index 0000000..b5b7582 --- /dev/null +++ b/examples/cpp_api/async_sample_process/circular_buffer.hpp @@ -0,0 +1,165 @@ +#ifndef __CIRC_BUFFER_H__ +#define __CIRC_BUFFER_H__ + +#include +#include +#include +#include +#include +#include + +#define IS_POWER_OF_2(x) (!((x) == 0) && !((x) & ((x) - 1))) +#define MIN(x,y) ((x)>(y)?(y):(x)) + + +template +class circular_buffer { +public: + circular_buffer(size_t size, bool override_write = true, bool block_read = true) + { + max_size_ = size; + if (!IS_POWER_OF_2(max_size_)) + { + max_size_ = next_power_of_2(max_size_); + } + buf_ = new T[max_size_]; + override_write_ = override_write; + block_read_ = block_read; + } + + ~circular_buffer() + { + std::unique_lock lock(mutex_); + delete []buf_; + } + + size_t put(const T *data, size_t length) + { + std::lock_guard lock(mutex_); + + if ((max_size_ - size()) < length && override_write_) + { + // pop the amount of data the is needed + tail_ += length - (max_size_ - size()); + } + + size_t len = MIN(length, max_size_ - head_ + tail_); + auto l = MIN(len, max_size_ - (head_ & (max_size_ - 1))); + + memcpy(buf_ + (head_ & (max_size_ - 1)), data, l * sizeof(T)); + memcpy(buf_, data + l, (len - l) * sizeof(T)); + + head_ += len; + + if (block_read_) + { + cond_var_.notify_one(); + } + + return len; + } + + size_t get(T *data, size_t length, int timeout_us = 100000) + { + std::unique_lock lock(mutex_); + + if (block_read_) + { + cond_var_.wait_for(lock, std::chrono::microseconds(timeout_us), [&]() + { + // Acquire the lock only if + // we got enough items + return size() >= length; + }); + + if (size() < length) + { + return 0; + } + } + + size_t len = MIN(length, head_ - tail_); + auto l = MIN(len, max_size_ - (tail_ & (max_size_ - 1))); + + if (data != NULL) + { + memcpy(data, buf_ + (tail_ & (max_size_ - 1)), l * sizeof(T)); + memcpy(data + l, buf_, (len - l) * sizeof(T)); + } + tail_ += len; + return len; + } + + void put(T item) + { + put(&item, 1); + } + + T get() + { + T item; + get(&item, 1); + return item; + } + + void reset() + { + std::unique_lock lock(mutex_); + head_ = tail_ = 0; + } + + inline bool empty() + { + return head_ == tail_; + } + + inline bool full() + { + return size() == capacity(); + } + + inline size_t capacity() const + { + return max_size_; + } + + size_t size() + { + return (head_ - tail_); + } + + void print_buffer() + { + std::unique_lock lock(mutex_); + size_t t = tail_; + int i = 0; + while (t < head_) + { + printf("%d => %d\n", i++, (int)buf_[t++&(max_size_-1)]); + } + } + +private: + uint32_t next_power_of_2 (uint32_t x) + { + uint32_t power = 1; + while(power < x) + { + power <<= 1; + } + return power; + } + +private: + std::mutex mutex_; + std::condition_variable cond_var_; + + T* buf_; + size_t head_ = 0; + size_t tail_ = 0; + size_t max_size_; + bool override_write_; + bool block_read_; +}; + +#endif \ No newline at end of file diff --git a/examples/cpp_api/async_sample_process/main.cpp b/examples/cpp_api/async_sample_process/main.cpp new file mode 100644 index 0000000..1bebc2b --- /dev/null +++ b/examples/cpp_api/async_sample_process/main.cpp @@ -0,0 +1,235 @@ +#include +#include +#include +#include +#include + +#include // CPP API for CaribouLite +#include "circular_buffer.hpp" // for circular sample buffer + +#define SAMPLE_RATE (4000000) +#define SAMPLE_RATE_CLOSEST (4194304) +#define MAX_FIFO_SECONDS (2) +#define MAX_FIFO_SIZE (SAMPLE_RATE_CLOSEST * MAX_FIFO_SECONDS) +#define TIME_BETWEEN_EPOCHS (5) +#define TIME_OF_SAMPLING (1) +#define RX_CHUNK_SAMPLES (8192) + +// ========================================================================================== +// The Application context +// ========================================================================================== + +typedef enum +{ + app_state_setup = 0, + app_state_sampling = 1, + app_state_sleaping = 2, +} appState_en; + +typedef struct +{ + // device + CaribouLite* cl; + CaribouLiteRadio* radio; + + // operational parameters + bool running; + float freq; + float gain; + size_t num_samples_read_so_far; + size_t epoch; + appState_en state; + bool requested_to_quit; + + // buffers & threads + circular_buffer> rx_fifo; + thread *dsp_thread; +} appContext_st; + +static appContext_st app = {0}; + +// ========================================================================================== +// General printing and detection of the board +// ========================================================================================== +void printInfo(CaribouLite& cl) +{ + std::cout << "Initialized CaribouLite: " << cl.IsInitialized() << std::endl; + std::cout << "API Versions: " << cl.GetApiVersion() << std::endl; + std::cout << "Hardware Serial Number: " << std::hex << cl.GetHwSerialNumber() << std::endl; + std::cout << "System Type: " << cl.GetSystemVersionStr() << std::endl; + std::cout << "Hardware Unique ID: " << cl.GetHwGuid() << std::endl; +} + +// Detect boards +void detectBoard() +{ + CaribouLite::SysVersion ver; + std::string name; + std::string guid; + + if (CaribouLite::DetectBoard(&ver, name, guid)) + { + std::cout << "Detected Version: " << CaribouLite::GetSystemVersionStr(ver) << ", Name: " << name << ", GUID: " << guid << std::endl; + } + else + { + std::cout << "Undetected CaribouLite!" << std::endl; + } +} + +// Print radio information +void printRadioInformation(CaribouLiteRadio* radio) +{ + std::cout << "Radio Name: " << radio->GetRadioName() << " MtuSize: " << std::dec << radio->GetNativeMtuSample() << " Samples" << std::endl; + + std::vector range = radio->GetFrequencyRange(); + std::cout << "Frequency Regions:" << std::endl; + for (int i = 0; i < range.size(); i++) + { + std::cout << " " << i << ": " << range[i] << std::endl; + } +} + +// ========================================================================================== +// DSP Thread - The thread that processes data whenever it is available and its +// helper sub-functions +// ========================================================================================== + +// Helper DSP function example: calculate the RSSI +float RSSI(const std::complex* signal, size_t num_of_samples) +{ + if (num_of_samples == 0) + { + return 0.0f; + } + + float sum_of_squares = 0.0f; + for (size_t i = 0; i < num_of_samples && i < num_of_samples; ++i) + { + float vrms = std::norm(signal[i]); + sum_of_squares += vrms * vrms / 100.0; + } + + float mean_of_squares = sum_of_squares / num_of_samples; + + // Convert RMS value to dBm + return 10 * log10(mean_of_squares); +} + +// Consumer thread +void dataConsumerThread(appContext_st* app) +{ + std::cout << "Data consumer thread started" << std::endl; + std::complex local_dsp_buffer[RX_CHUNK_SAMPLES * 4]; + + + while (app->running) + { + // get the number of elements in the fifo + size_t num_lements = app.rx_fifo.size(); + if (num_lements == 0) + { + std::this_thread::sleep_for(std::chrono::milliseconds(50)) + continue; + } + + app.rx_fifo.get(local_dsp_buffer, (num_lements>(RX_CHUNK_SAMPLES*4)) ? (RX_CHUNK_SAMPLES * 4) : num_lements); + } + + std::cout << "Data consumer thread exitting" << std::endl; +} + +// ========================================================================================== +// Asynchronous API for receiving data and managing data flow in RX +// ========================================================================================== +// Rx Callback (async) +void receivedSamples(CaribouLiteRadio* radio, const std::complex* samples, CaribouLiteMeta* sync, size_t num_samples) +{ + for (int i = 0; i < 6; i ++) + { + std::cout << "[" << samples[i].real() << ", " << samples[i].imag() << "]"; + } + std::cout << std::endl; + + // push the received samples in the fifo + app.rx_fifo.put(samples, num_samples); +} + + +// Main entry +int main () +{ + // try detecting the board before getting the instance + detectBoard(); + CaribouLite &cl = CaribouLite::GetInstance(); + printInfo(cl); + + // get the radios + CaribouLiteRadio *s1g = cl.GetRadioChannel(CaribouLiteRadio::RadioType::S1G); + printRadioInformation(s1g); + + // create the application context + app.cl = &cl; + app.radio = s1g; + app.freq = 900000000; + app.gain = 69; + app.rx_fifo = new circular_buffer>(MAX_FIFO_SIZE); + app.num_samples_read_so_far = 0; + app.state = app_state_sampling; + app.epoch = 0; + app.requested_to_quit = false; + app.running = true; + app.dsp_thread = new std::thread(dataConsumerThread, &app); + + // time management + while (1) + { + switch(app.state) + { + //---------------------------------------------- + case app_state_setup: + // an example periodic radio setup stage + app.radio->SetRxGain(app.gain); + app.radio->SetFrequency(app.freq); + app.num_samples_read_so_far = 0; + + // and now go directly to the next sampling stage + app.state = app_state_sampling; + break; + + //---------------------------------------------- + case app_state_sampling: + // start receiving + app.radio->StartReceiving(receivedSamples, RX_CHUNK_SAMPLES); + std::this_thread::sleep_for(std::chrono::milliseconds(TIME_OF_SAMPLING * 1000)); + + // stop receiving + app.radio->StopReceiving(); + app.state = app_state_sleeping; + break; + + //---------------------------------------------- + case app_state_sleeping: + std::this_thread::sleep_for(std::chrono::milliseconds(TIME_BETWEEN_EPOCHS * 1000)); + app.epoch ++; + + // either go the next epoch or quit the program + // this is an example flow but other possibilities exist + if (!app.requested_to_quit) app.state = app_state_setup; + else break; + break; + + //---------------------------------------------- + default: + break; + } + } + + // cleanup - done by the creator + app.running = false; + app.dsp_thread->join(); + delete app.dsp_thread; + delete app.rx_fifo; + + return 0; +} diff --git a/examples/cpp_api/sync_rx_api/main.cpp b/examples/cpp_api/sync_rx_api/main.cpp index 267ecc0..c0a8128 100644 --- a/examples/cpp_api/sync_rx_api/main.cpp +++ b/examples/cpp_api/sync_rx_api/main.cpp @@ -128,7 +128,6 @@ int main () { std::cout << "Radio: " << hif->GetRadioName() << " Received " << std::dec << ret << " samples" << "RSSI: " << RSSI(samples, ret) << " dBm" << std::endl; - std::cout << "Radio: " << s1g->GetRadioName() << " Received " << std::dec << ret << " samples" << std::endl; } } diff --git a/examples/cpp_api/sync_tx_api/CMakeLists.txt b/examples/cpp_api/sync_tx_api/CMakeLists.txt new file mode 100644 index 0000000..7562635 --- /dev/null +++ b/examples/cpp_api/sync_tx_api/CMakeLists.txt @@ -0,0 +1,15 @@ +cmake_minimum_required(VERSION 3.2) +project(test_app) + +# Find the package using pkg-config +find_package(PkgConfig REQUIRED) +pkg_check_modules(CARIBOULITE REQUIRED cariboulite) + +# Add the executable +add_executable(test_app main.cpp) + +# Include directories from the cariboulite package +target_include_directories(test_app PRIVATE ${CARIBOULITE_INCLUDE_DIRS}) + +# Link against the cariboulite library +target_link_libraries(test_app PRIVATE ${CARIBOULITE_LIBRARIES} -lcariboulite) diff --git a/examples/cpp_api/sync_tx_api/main.cpp b/examples/cpp_api/sync_tx_api/main.cpp new file mode 100644 index 0000000..877062b --- /dev/null +++ b/examples/cpp_api/sync_tx_api/main.cpp @@ -0,0 +1,141 @@ +#include +#include +#include +#include +#include +#include + +// Print Board Information +void printInfo(CaribouLite& cl) +{ + std::cout << "Initialized CaribouLite: " << cl.IsInitialized() << std::endl; + std::cout << "API Versions: " << cl.GetApiVersion() << std::endl; + std::cout << "Hardware Serial Number: " << std::hex << cl.GetHwSerialNumber() << std::endl; + std::cout << "System Type: " << cl.GetSystemVersionStr() << std::endl; + std::cout << "Hardware Unique ID: " << cl.GetHwGuid() << std::endl; +} + +// Detect the board before instantiating it +void detectBoard() +{ + CaribouLite::SysVersion ver; + std::string name; + std::string guid; + + if (CaribouLite::DetectBoard(&ver, name, guid)) + { + std::cout << "Detected Version: " << CaribouLite::GetSystemVersionStr(ver) << ", Name: " << name << ", GUID: " << guid << std::endl; + } + else + { + std::cout << "Undetected CaribouLite!" << std::endl; + } +} + + +// Rx Callback (async) +void receivedSamples(CaribouLiteRadio* radio, const std::complex* samples, CaribouLiteMeta* sync, size_t num_samples) +{ + std::cout << "Radio: " << radio->GetRadioName() << " Received " << std::dec << num_samples << " samples" << std::endl; +} + +// Tx buffer generation +void generateCwWave(float freq, float sample_rate, std::complex* samples, size_t num_samples) +{ + // angular frequency + float omega = 2.0f * M_PI * freq; + + for (int i = 0; i < num_samples; ++i) + { + float t = (float)(i) / sample_rate; + float I = cos(omega * t); + float Q = sin(omega * t); + samples[i] = std::complex(I, Q); + } +} + +// Main entry +int main () +{ + // try detecting the board before getting the instance + detectBoard(); + + // get driver instance - use "CaribouLite&" rather than "CaribouLite" (ref) + CaribouLite &cl = CaribouLite::GetInstance(); + + // print the info after connecting + printInfo(cl); + + // get the radios + CaribouLiteRadio *s1g = cl.GetRadioChannel(CaribouLiteRadio::RadioType::S1G); + CaribouLiteRadio *hif = cl.GetRadioChannel(CaribouLiteRadio::RadioType::HiF); + + // write radio information + std::cout << "First Radio Name: " << s1g->GetRadioName() << " MtuSize: " << std::dec << s1g->GetNativeMtuSample() << " Samples" << std::endl; + std::cout << "First Radio Name: " << hif->GetRadioName() << " MtuSize: " << std::dec << hif->GetNativeMtuSample() << " Samples" << std::endl; + + std::vector range_s1g = s1g->GetFrequencyRange(); + std::vector range_hif = hif->GetFrequencyRange(); + std::cout << "S1G Frequency Regions:" << std::endl; + for (int i = 0; i < range_s1g.size(); i++) + { + std::cout << " " << i << ": " << range_s1g[i] << std::endl; + } + + std::cout << "HiF Frequency Regions:" << std::endl; + for (int i = 0; i < range_hif.size(); i++) + { + std::cout << " " << i << ": " << range_hif[i] << std::endl; + } + + /********************************************************************************/ + /* TRANSMITTING CW */ + /********************************************************************************/ + /*try + { + s1g->SetFrequency(900000000); + } + catch (...) + { + std::cout << "The specified freq couldn't be used" << std::endl; + } + s1g->SetTxPower(0); + s1g->SetTxBandwidth(1e6); + s1g->SetTxSampleRate(4e6); + s1g->StartTransmittingCw(); + + std::this_thread::sleep_for(std::chrono::milliseconds(5000)); + s1g->StopTransmitting();*/ + + /********************************************************************************/ + /* TRANSMITTING */ + /********************************************************************************/ + std::complex* samples = new std::complex[s1g->GetNativeMtuSample()]; + generateCwWave(500e3, 4e6, samples, s1g->GetNativeMtuSample()); + + try + { + s1g->SetFrequency(900000000); + } + catch (...) + { + std::cout << "The specified freq couldn't be used" << std::endl; + } + s1g->SetTxPower(0); + s1g->SetTxBandwidth(1e6); + s1g->SetTxSampleRate(4e6); + s1g->StartTransmitting(); + + for (int i = 0; i < 18; i++) + { + printf("buffer #%d\n", i); + s1g->WriteSamples(samples, s1g->GetNativeMtuSample()); + } + std::this_thread::sleep_for(std::chrono::milliseconds(10000)); + + s1g->StopTransmitting(); + + delete [] samples; + + return 0; +} diff --git a/firmware/Makefile b/firmware/Makefile index 6a2c314..e9dbb96 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -5,7 +5,7 @@ pcf_file = ./io.pcf top.bin: yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v #nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc - nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 1 --timing-allow-fail + nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 5 --timing-allow-fail #nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui icepack $(filename).asc $(filename).bin diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index 789e2d4..d76d608 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -17,14 +17,14 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-03-14 - * Time: 23:08:06 + * Date: 2024-03-15 + * Time: 03:49:31 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 6, - .tm_min = 8, - .tm_hour = 23, - .tm_mday = 14, + .tm_sec = 31, + .tm_min = 49, + .tm_hour = 3, + .tm_mday = 15, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ }; @@ -38,384 +38,384 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, @@ -469,697 +468,698 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAD, 0xB0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x41, 0xDB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xFE, 0x2D, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8D, 0x0D, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/firmware/lvds_tx.v b/firmware/lvds_tx.v index ff21be2..a5d9586 100644 --- a/firmware/lvds_tx.v +++ b/firmware/lvds_tx.v @@ -1,15 +1,15 @@ module lvds_tx ( - input i_rst_b, - input i_ddr_clk, + input i_rst_b, + input i_ddr_clk, output reg[1:0] o_ddr_data, - input i_fifo_empty, - output o_fifo_read_clk, + input i_fifo_empty, + output o_fifo_read_clk, output o_fifo_pull, - input [31:0] i_fifo_data, + input [31:0] i_fifo_data, input [3:0] i_sample_gap, - input i_tx_state, - input i_sync_input, + input i_tx_state, + input i_sync_input, input i_debug_lb, output o_tx_state_bit, output o_sync_state_bit, @@ -17,28 +17,29 @@ module lvds_tx ( // STATES and PARAMS localparam - tx_state_sync = 1'b0, - tx_state_tx = 1'b1; + tx_state_sync = 1'b0, + tx_state_tx = 1'b1; localparam sync_duration_frames = 4'd10; // at least 2.5usec localparam zero_frame = 32'b00000000_00000000_00000000_00000000; localparam lb_frame = 32'b10000100_00000011_01110000_01001000; - // Internal Registers + + // Internal Registers reg [3:0] r_sync_count; wire frame_pull_clock; wire frame_assign_clock; reg r_state; reg [3:0] r_phase_count; - reg [31:0] r_fifo_data; + reg [31:0] r_fifo_data; reg r_pulled; reg r_schedule_zero_frame; - // Initial conditions - initial begin + // Initial conditions + initial begin r_phase_count = 4'd15; r_fifo_data <= zero_frame; - end + end - assign o_fifo_read_clk = i_ddr_clk; + assign o_fifo_read_clk = i_ddr_clk; assign o_tx_state_bit = r_state; assign o_sync_state_bit = 1'b0; assign o_fifo_pull = r_pulled; @@ -52,15 +53,17 @@ module lvds_tx ( r_phase_count <= r_phase_count - 1; end end + // SYNC AND MANAGEMENT - always @(posedge i_ddr_clk) begin - if (i_rst_b == 1'b0) begin + always @(posedge i_ddr_clk) + begin + if (i_rst_b == 1'b0) begin r_state <= tx_state_sync; r_pulled <= 1'b0; r_fifo_data <= zero_frame; r_sync_count <= sync_duration_frames; r_schedule_zero_frame <= 1'b0; - end else begin + end else begin case (r_state) //---------------------------------------------- tx_state_sync: @@ -83,14 +86,15 @@ module lvds_tx ( r_state <= tx_state_sync; r_fifo_data <= zero_frame; end - end else begin + end else begin r_sync_count <= r_sync_count - 1; r_schedule_zero_frame <= 1'b1; //r_fifo_data <= zero_frame; r_state <= tx_state_sync; - end + end end end + //---------------------------------------------- tx_state_tx: begin @@ -106,7 +110,7 @@ module lvds_tx ( r_sync_count <= sync_duration_frames; r_fifo_data <= zero_frame; r_state <= tx_state_sync; - end else begin + end else begin r_fifo_data <= i_fifo_data; if (i_sample_gap > 0) begin r_sync_count <= i_sample_gap; @@ -115,11 +119,11 @@ module lvds_tx ( r_state <= tx_state_tx; end end + r_pulled <= 1'b0; - end + end end endcase + end end - end - endmodule diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v index dba0505..8428534 100644 --- a/firmware/smi_ctrl.v +++ b/firmware/smi_ctrl.v @@ -171,7 +171,7 @@ module smi_ctrl tx_state_third = 2'b10, tx_state_fourth = 2'b11; - reg [4:0] int_cnt_tx; + reg [12:0] int_cnt_tx; reg [31:0] r_fifo_pushed_data; reg [1:0] tx_reg_state; reg modem_tx_ctrl; @@ -194,7 +194,11 @@ module smi_ctrl r_fifo_pushed_data <= 32'h00000000; modem_tx_ctrl <= 1'b0; cond_tx_ctrl <= 1'b0; - //cnt <= 0; + + // DEBUG + int_cnt_tx <= 0; + // END_DEBUG + end else begin case (tx_reg_state) //---------------------------------------------- @@ -247,10 +251,11 @@ module smi_ctrl begin if (i_smi_data_in[7] == 1'b0) begin o_tx_fifo_pushed_data <= {r_fifo_pushed_data[31:8], i_smi_data_in[6:0], 1'b0}; + //o_tx_fifo_pushed_data <= {i_smi_data_in[6:0], 1'b0, r_fifo_pushed_data[15:8], r_fifo_pushed_data[23:16], r_fifo_pushed_data[31:24]}; - //o_tx_fifo_pushed_data <= {2'b10, cnt, 1'b1, 2'b01, 13'h3F, 1'b0}; - //o_tx_fifo_pushed_data <= {cnt, cnt, 6'b111111}; - //cnt <= cnt + 1024; + o_tx_fifo_pushed_data <= {2'b10, int_cnt_tx, 1'b1, 2'b01, 13'h3F, 1'b0}; + int_cnt_tx <= int_cnt_tx + 512; + w_fifo_push_trigger <= 1'b1; o_cond_tx <= cond_tx_ctrl; end else begin diff --git a/firmware/top.asc b/firmware/top.asc index cd69eb1..e5d1897 100644 --- a/firmware/top.asc +++ b/firmware/top.asc @@ -50,7 +50,7 @@ 000000000000000000 000000000000000000 000000000000000000 -000000000000010000 +000000000000000000 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rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 863 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 864 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 865 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 866 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 867 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 899 rx_fifo.wr_addr[7] +.sym 906 rx_fifo.wr_addr[0] +.sym 908 rx_fifo.wr_addr[4] +.sym 940 lvds_clock .sym 944 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 972 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 974 $PACKER_GND_NET -.sym 976 w_rx_09_fifo_data[3] -.sym 980 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 1000 rx_fifo.wr_addr[6] -.sym 1054 o_iq_tx_clk_p$SB_IO_OUT +.sym 959 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 974 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 975 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 976 rx_fifo.rd_addr_gray_wr_r[6] +.sym 977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 978 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] +.sym 979 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.sym 980 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 981 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] +.sym 1007 $PACKER_VCC_NET +.sym 1042 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1051 $PACKER_VCC_NET +.sym 1054 w_lvds_rx_09_d0 +.sym 1055 $PACKER_VCC_NET .sym 1061 $PACKER_GND_NET .sym 1062 $PACKER_GND_NET .sym 1066 $PACKER_VCC_NET .sym 1067 $PACKER_VCC_NET .sym 1069 $PACKER_VCC_NET -.sym 1071 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1072 $PACKER_GND_NET -.sym 1076 $PACKER_VCC_NET -.sym 1080 $PACKER_GND_NET -.sym 1084 $PACKER_VCC_NET +.sym 1071 io_pmod[0]$SB_IO_IN +.sym 1076 $PACKER_GND_NET +.sym 1077 $PACKER_GND_NET +.sym 1078 $PACKER_VCC_NET +.sym 1084 io_pmod[0]$SB_IO_IN .sym 1085 $PACKER_VCC_NET -.sym 1088 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 1090 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 1091 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 1094 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 1095 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 1128 i_rst_b$SB_IO_IN +.sym 1086 $PACKER_VCC_NET +.sym 1088 rx_fifo.rd_addr_gray_wr_r[4] +.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 1090 rx_fifo.rd_addr_gray_wr[4] +.sym 1091 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 1092 rx_fifo.rd_addr_gray_wr_r[2] +.sym 1093 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] +.sym 1094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 1095 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 1116 $PACKER_VCC_NET +.sym 1121 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 1141 io_pmod[0]$SB_IO_IN +.sym 1142 $PACKER_VCC_NET .sym 1173 w_lvds_rx_09_d0 .sym 1174 w_lvds_rx_09_d1 .sym 1183 $PACKER_VCC_NET -.sym 1184 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1191 $PACKER_VCC_NET -.sym 1203 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 1204 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 1205 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 1206 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 1207 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 1209 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 1234 w_lvds_rx_09_d0 -.sym 1246 w_lvds_rx_09_d1 -.sym 1248 $PACKER_VCC_NET -.sym 1259 $PACKER_VCC_NET -.sym 1287 o_iq_tx_clk_p$SB_IO_OUT +.sym 1184 lvds_clock_$glb_clk +.sym 1199 $PACKER_VCC_NET +.sym 1202 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 1203 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 1204 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 1206 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 1208 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 1209 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] +.sym 1222 rx_fifo.rd_addr_gray_wr_r[8] +.sym 1235 $PACKER_GND_NET +.sym 1241 i_rst_b$SB_IO_IN +.sym 1242 w_lvds_rx_09_d0 +.sym 1244 w_lvds_rx_09_d1 +.sym 1256 $PACKER_VCC_NET +.sym 1271 w_lvds_rx_09_d1 +.sym 1279 $PACKER_GND_NET +.sym 1287 lvds_clock .sym 1297 $PACKER_VCC_NET -.sym 1310 $PACKER_VCC_NET -.sym 1317 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 1318 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 1319 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 1320 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 1321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 1305 $PACKER_VCC_NET +.sym 1316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 1317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 1318 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 1319 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] +.sym 1320 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 1321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] .sym 1322 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 1323 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 1349 w_lvds_rx_09_d0 -.sym 1350 $PACKER_VCC_NET -.sym 1393 w_lvds_rx_09_d1 +.sym 1323 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 1324 lvds_clock +.sym 1336 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 1348 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 1360 rx_fifo.rd_addr_gray_wr_r[9] +.sym 1362 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] .sym 1401 w_lvds_rx_24_d0 .sym 1402 w_lvds_rx_24_d1 .sym 1411 $PACKER_VCC_NET -.sym 1412 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 1424 $PACKER_VCC_NET -.sym 1431 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 1432 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 1435 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 1436 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 1437 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 1464 w_lvds_rx_24_d1 -.sym 1470 w_lvds_rx_24_d0 -.sym 1499 $PACKER_VCC_NET -.sym 1560 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 1883 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 1885 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 1911 w_smi_data_direction -.sym 1941 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 1946 w_rx_09_fifo_data[19] -.sym 1954 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2063 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 2064 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 2066 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 2067 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 2068 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 2070 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 2104 smi_ctrl_ins.int_cnt_rx[4] -.sym 2115 w_rx_09_fifo_data[29] -.sym 2140 w_rx_24_fifo_data[26] -.sym 2144 w_rx_24_fifo_data[24] -.sym 2163 w_rx_24_fifo_data[22] -.sym 2165 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2166 w_rx_09_fifo_data[23] -.sym 2167 w_rx_09_fifo_data[22] -.sym 2168 w_rx_09_fifo_data[25] -.sym 2172 w_rx_09_fifo_data[21] -.sym 2176 w_rx_09_fifo_data[19] -.sym 2182 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2183 w_rx_09_fifo_data[27] -.sym 2187 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2188 w_rx_09_fifo_data[23] -.sym 2192 w_rx_24_fifo_data[22] -.sym 2193 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2194 w_rx_09_fifo_data[22] -.sym 2204 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2206 w_rx_09_fifo_data[27] -.sym 2210 w_rx_09_fifo_data[19] -.sym 2211 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2221 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2223 w_rx_09_fifo_data[21] -.sym 2228 w_rx_09_fifo_data[25] -.sym 2230 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 1412 lvds_clock_$glb_clk +.sym 1416 $PACKER_VCC_NET +.sym 1430 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 1433 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E +.sym 1434 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 1435 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 1436 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 1462 w_lvds_rx_24_d0 +.sym 1463 w_lvds_rx_09_d0 +.sym 1464 $PACKER_VCC_NET +.sym 1474 w_lvds_rx_24_d1 +.sym 1545 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 1546 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 1547 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] +.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 1549 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] +.sym 1550 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 1551 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 1690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 1894 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 1945 w_rx_09_fifo_data[5] +.sym 1951 w_rx_24_fifo_data[15] +.sym 2063 rx_fifo.mem_q.0.3_WDATA_1 +.sym 2064 rx_fifo.mem_q.0.3_WDATA_2 +.sym 2065 w_rx_09_fifo_data[10] +.sym 2066 rx_fifo.mem_q.0.3_WDATA_3 +.sym 2067 w_rx_09_fifo_data[12] +.sym 2068 w_rx_09_fifo_data[18] +.sym 2069 w_rx_09_fifo_data[14] +.sym 2070 w_rx_09_fifo_data[16] +.sym 2081 $PACKER_VCC_NET +.sym 2120 rx_fifo.mem_q.0.2_WDATA +.sym 2123 rx_fifo.mem_q.0.2_WDATA_1 +.sym 2124 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2125 rx_fifo.mem_i.0.0_WDATA_1 +.sym 2128 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2129 w_rx_24_fifo_data[14] +.sym 2143 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2155 w_rx_09_fifo_data[11] +.sym 2156 w_rx_09_fifo_data[13] +.sym 2159 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2169 w_rx_09_fifo_data[15] +.sym 2172 w_rx_24_fifo_data[15] +.sym 2180 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2186 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2187 w_rx_24_fifo_data[15] +.sym 2188 w_rx_09_fifo_data[15] +.sym 2193 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2194 w_rx_09_fifo_data[13] +.sym 2210 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2212 w_rx_09_fifo_data[11] +.sym 2227 w_rx_09_fifo_data[15] +.sym 2229 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] .sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2232 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2232 lvds_clock_$glb_clk .sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2234 w_smi_data_output[2] -.sym 2235 w_smi_data_output[3] -.sym 2236 w_smi_data_output[1] -.sym 2237 rx_fifo.mem_i.0.0_WDATA -.sym 2238 w_smi_data_output[0] -.sym 2239 w_smi_data_output[6] -.sym 2240 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 2241 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 2246 w_rx_09_fifo_data[25] -.sym 2251 w_rx_24_fifo_data[22] -.sym 2256 w_rx_09_fifo_data[21] -.sym 2259 rx_fifo.mem_i.0.1_WDATA_3 -.sym 2268 rx_fifo.mem_i.0.2_WDATA_2 -.sym 2272 w_rx_24_fifo_data[22] -.sym 2277 w_rx_09_fifo_data[14] -.sym 2290 w_rx_09_fifo_data[26] -.sym 2291 w_rx_09_fifo_data[28] -.sym 2292 w_rx_09_fifo_data[24] -.sym 2294 w_rx_09_fifo_data[20] -.sym 2295 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2298 w_rx_09_fifo_data[29] -.sym 2299 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2303 w_rx_24_fifo_data[24] -.sym 2307 w_rx_24_fifo_data[26] -.sym 2310 w_rx_09_fifo_data[22] -.sym 2320 w_rx_09_fifo_data[29] -.sym 2323 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2326 w_rx_09_fifo_data[26] -.sym 2328 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2329 w_rx_24_fifo_data[26] -.sym 2333 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2334 w_rx_24_fifo_data[24] -.sym 2335 w_rx_09_fifo_data[24] -.sym 2338 w_rx_09_fifo_data[24] -.sym 2340 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2345 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2347 w_rx_09_fifo_data[26] -.sym 2350 w_rx_09_fifo_data[22] -.sym 2352 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2357 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2358 w_rx_09_fifo_data[28] -.sym 2362 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2364 w_rx_09_fifo_data[20] +.sym 2234 w_rx_09_fifo_data[20] +.sym 2235 rx_fifo.mem_i.0.0_WDATA_3 +.sym 2236 w_rx_09_fifo_data[26] +.sym 2237 rx_fifo.mem_q.0.2_WDATA_3 +.sym 2238 w_rx_09_fifo_data[28] +.sym 2239 w_rx_09_fifo_data[22] +.sym 2240 w_rx_09_fifo_data[24] +.sym 2241 rx_fifo.mem_i.0.0_WDATA_2 +.sym 2246 rx_fifo.mem_q.0.3_WDATA +.sym 2258 w_rx_09_fifo_data[10] +.sym 2260 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2262 w_rx_09_fifo_data[7] +.sym 2264 rx_fifo.wr_addr[0] +.sym 2265 rx_fifo.wr_addr[4] +.sym 2267 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2268 rx_fifo.wr_addr[6] +.sym 2270 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2271 w_rx_09_fifo_data[6] +.sym 2275 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 2287 w_rx_24_fifo_data[9] +.sym 2291 w_rx_09_fifo_data[5] +.sym 2292 w_rx_09_fifo_data[9] +.sym 2294 w_rx_09_fifo_data[17] +.sym 2296 w_rx_24_fifo_data[17] +.sym 2301 w_rx_09_fifo_data[7] +.sym 2302 w_rx_24_fifo_data[11] +.sym 2304 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2306 w_rx_09_fifo_data[11] +.sym 2308 w_rx_09_fifo_data[6] +.sym 2313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2321 w_rx_09_fifo_data[9] +.sym 2322 w_rx_24_fifo_data[9] +.sym 2323 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2326 w_rx_09_fifo_data[17] +.sym 2327 w_rx_24_fifo_data[17] +.sym 2328 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2333 w_rx_09_fifo_data[6] +.sym 2335 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2338 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2340 w_rx_09_fifo_data[9] +.sym 2345 w_rx_09_fifo_data[17] +.sym 2347 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2350 w_rx_09_fifo_data[7] +.sym 2352 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2358 w_rx_09_fifo_data[5] +.sym 2359 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2362 w_rx_09_fifo_data[11] +.sym 2364 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2365 w_rx_24_fifo_data[11] .sym 2366 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2367 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2367 lvds_clock_$glb_clk .sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2369 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 2370 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 2371 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 2372 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 2373 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 2374 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 2375 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 2376 rx_fifo.mem_i.0.0_WDATA_1 -.sym 2378 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2379 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2381 w_rx_09_fifo_data[31] -.sym 2386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 2388 w_smi_data_output[2] -.sym 2391 w_rx_09_fifo_data[28] -.sym 2392 w_smi_data_output[1] -.sym 2393 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 2394 w_rx_24_fifo_data[17] -.sym 2399 rx_fifo.rd_addr[8] -.sym 2403 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2404 w_rx_24_fifo_data[19] -.sym 2405 w_rx_09_fifo_data[15] -.sym 2406 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2412 w_rx_24_fifo_data[14] -.sym 2423 w_rx_24_fifo_data[16] -.sym 2425 w_rx_09_fifo_data[17] -.sym 2427 w_rx_24_fifo_data[20] -.sym 2433 w_rx_24_fifo_data[18] -.sym 2435 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2442 w_rx_09_fifo_data[16] -.sym 2443 w_rx_09_fifo_data[18] -.sym 2445 w_rx_09_fifo_data[20] -.sym 2450 w_rx_09_fifo_data[15] -.sym 2451 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2452 w_rx_09_fifo_data[14] -.sym 2455 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2456 w_rx_09_fifo_data[17] -.sym 2462 w_rx_09_fifo_data[16] -.sym 2463 w_rx_24_fifo_data[16] -.sym 2464 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2467 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2468 w_rx_09_fifo_data[18] -.sym 2469 w_rx_24_fifo_data[18] -.sym 2473 w_rx_09_fifo_data[15] -.sym 2474 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2480 w_rx_09_fifo_data[14] -.sym 2481 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2486 w_rx_09_fifo_data[16] -.sym 2488 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2492 w_rx_24_fifo_data[20] -.sym 2493 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2494 w_rx_09_fifo_data[20] -.sym 2499 w_rx_09_fifo_data[18] -.sym 2500 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2501 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2502 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2504 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 2505 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 2506 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 2507 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 2508 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 2509 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 2525 rx_fifo.rd_addr[2] -.sym 2526 rx_fifo.rd_addr[8] -.sym 2527 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2530 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 2531 rx_fifo.mem_q.0.3_WDATA_2 -.sym 2536 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 2538 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2541 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2551 w_rx_09_fifo_data[10] -.sym 2561 w_rx_24_fifo_data[24] -.sym 2564 w_rx_24_fifo_data[22] -.sym 2568 w_rx_24_fifo_data[18] -.sym 2574 w_rx_24_fifo_data[16] -.sym 2578 w_rx_24_fifo_data[20] -.sym 2579 w_rx_24_fifo_data[14] -.sym 2584 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2585 o_iq_tx_clk_p$SB_IO_OUT -.sym 2586 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2597 w_rx_24_fifo_data[14] -.sym 2599 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2602 w_rx_24_fifo_data[24] -.sym 2604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2610 w_rx_24_fifo_data[16] -.sym 2611 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2617 w_rx_24_fifo_data[22] -.sym 2621 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2623 w_rx_24_fifo_data[18] -.sym 2627 o_iq_tx_clk_p$SB_IO_OUT -.sym 2632 w_rx_24_fifo_data[20] -.sym 2635 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 2370 w_rx_24_fifo_data[18] +.sym 2371 rx_fifo.mem_q.0.2_WDATA_2 +.sym 2372 w_rx_24_fifo_data[10] +.sym 2373 w_rx_24_fifo_data[8] +.sym 2374 w_rx_24_fifo_data[14] +.sym 2375 w_rx_24_fifo_data[16] +.sym 2376 w_rx_24_fifo_data[12] +.sym 2386 rx_fifo.mem_i.0.0_WDATA_2 +.sym 2393 w_rx_09_fifo_data[26] +.sym 2395 w_rx_24_fifo_data[13] +.sym 2396 w_rx_24_fifo_data[26] +.sym 2398 w_rx_09_fifo_data[19] +.sym 2400 rx_fifo.mem_q.0.1_WDATA_1 +.sym 2402 rx_fifo.mem_q.0.1_WDATA +.sym 2424 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2426 w_rx_09_fifo_data[19] +.sym 2429 w_rx_24_fifo_data[7] +.sym 2431 w_rx_24_fifo_data[17] +.sym 2435 w_rx_24_fifo_data[13] +.sym 2437 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2438 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2440 w_rx_24_fifo_data[15] +.sym 2445 w_rx_24_fifo_data[11] +.sym 2446 w_rx_24_fifo_data[9] +.sym 2450 w_rx_24_fifo_data[19] +.sym 2455 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2456 w_rx_24_fifo_data[7] +.sym 2462 w_rx_24_fifo_data[15] +.sym 2464 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2467 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2469 w_rx_24_fifo_data[13] +.sym 2479 w_rx_24_fifo_data[17] +.sym 2481 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2485 w_rx_24_fifo_data[11] +.sym 2488 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2491 w_rx_09_fifo_data[19] +.sym 2493 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2494 w_rx_24_fifo_data[19] +.sym 2498 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2499 w_rx_24_fifo_data[9] +.sym 2501 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2502 lvds_clock_$glb_clk +.sym 2503 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2504 rx_fifo.mem_q.0.1_WDATA_3 +.sym 2505 rx_fifo.mem_i.0.2_WDATA_2 +.sym 2506 w_rx_24_fifo_data[6] +.sym 2507 rx_fifo.mem_i.0.2_WDATA_1 +.sym 2508 rx_fifo.mem_q.0.1_WDATA_2 +.sym 2509 w_rx_24_fifo_data[27] +.sym 2510 w_rx_24_fifo_data[4] +.sym 2511 w_rx_24_fifo_data[20] +.sym 2520 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2526 rx_fifo.rd_addr[0] +.sym 2530 rx_fifo.wr_addr[6] +.sym 2531 w_rx_09_fifo_data[28] +.sym 2533 rx_fifo.wr_addr[9] +.sym 2535 w_rx_09_fifo_data[20] +.sym 2537 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2538 w_rx_09_fifo_data[4] +.sym 2540 w_rx_09_fifo_data[5] +.sym 2541 rx_fifo.mem_i.0.1_WDATA_1 +.sym 2548 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2558 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 2560 w_rx_24_fifo_data[5] +.sym 2561 i_rst_b$SB_IO_IN +.sym 2568 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2569 w_rx_24_fifo_data[19] +.sym 2570 w_rx_09_fifo_data[7] +.sym 2572 w_rx_24_fifo_data[7] +.sym 2577 w_rx_09_fifo_data[5] +.sym 2578 w_rx_24_fifo_data[21] +.sym 2581 w_rx_24_fifo_data[23] +.sym 2585 w_rx_24_fifo_data[3] +.sym 2587 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2588 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2590 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2591 w_rx_24_fifo_data[21] +.sym 2596 w_rx_24_fifo_data[5] +.sym 2598 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2599 w_rx_09_fifo_data[5] +.sym 2602 w_rx_09_fifo_data[7] +.sym 2603 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2604 w_rx_24_fifo_data[7] +.sym 2608 w_rx_24_fifo_data[3] +.sym 2609 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2615 w_rx_24_fifo_data[23] +.sym 2622 w_rx_24_fifo_data[19] +.sym 2623 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2627 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 2628 i_rst_b$SB_IO_IN +.sym 2632 w_rx_24_fifo_data[5] +.sym 2635 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 2636 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2637 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2637 lvds_clock_$glb_clk .sym 2638 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2639 w_rx_24_fifo_data[17] -.sym 2640 w_rx_24_fifo_data[11] -.sym 2641 rx_fifo.mem_q.0.2_WDATA -.sym 2642 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2643 w_rx_24_fifo_data[15] -.sym 2644 w_rx_24_fifo_data[19] -.sym 2645 w_rx_24_fifo_data[13] -.sym 2646 rx_fifo.mem_q.0.2_WDATA_1 -.sym 2650 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 2652 rx_fifo.wr_addr[8] -.sym 2654 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 2661 rx_fifo.mem_q.0.1_WDATA_2 -.sym 2668 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2684 rx_fifo.mem_q.0.1_WDATA_2 -.sym 2695 w_rx_24_fifo_data[14] -.sym 2700 w_rx_09_fifo_data[11] -.sym 2703 w_rx_09_fifo_data[14] -.sym 2705 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2709 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2710 w_rx_09_fifo_data[10] -.sym 2713 w_rx_09_fifo_data[12] -.sym 2718 w_rx_09_fifo_data[13] -.sym 2721 w_rx_09_fifo_data[9] -.sym 2725 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2727 w_rx_09_fifo_data[9] -.sym 2739 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2740 w_rx_09_fifo_data[11] -.sym 2744 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2745 w_rx_09_fifo_data[12] -.sym 2756 w_rx_09_fifo_data[10] -.sym 2758 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2761 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2764 w_rx_09_fifo_data[13] -.sym 2767 w_rx_24_fifo_data[14] -.sym 2768 w_rx_09_fifo_data[14] -.sym 2769 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] +.sym 2639 w_rx_24_fifo_data[29] +.sym 2640 rx_fifo.mem_i.0.1_WDATA_2 +.sym 2641 w_rx_24_fifo_data[22] +.sym 2642 rx_fifo.mem_i.0.1_WDATA_3 +.sym 2643 w_rx_24_fifo_data[3] +.sym 2644 w_rx_24_fifo_data[31] +.sym 2645 w_rx_24_fifo_data[2] +.sym 2646 w_rx_24_fifo_data[30] +.sym 2658 $PACKER_VCC_NET +.sym 2665 rx_fifo.wr_addr[4] +.sym 2666 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 2667 rx_fifo.wr_addr[6] +.sym 2672 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2673 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2683 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2692 w_rx_24_fifo_data[23] +.sym 2697 w_rx_24_fifo_data[27] +.sym 2704 w_rx_09_fifo_data[19] +.sym 2705 w_rx_24_fifo_data[21] +.sym 2706 w_rx_09_fifo_data[21] +.sym 2707 w_rx_09_fifo_data[27] +.sym 2711 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2717 w_rx_09_fifo_data[25] +.sym 2718 w_rx_09_fifo_data[23] +.sym 2720 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2722 w_rx_09_fifo_data[4] +.sym 2726 w_rx_09_fifo_data[4] +.sym 2728 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2731 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2733 w_rx_09_fifo_data[23] +.sym 2738 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2740 w_rx_09_fifo_data[21] +.sym 2743 w_rx_09_fifo_data[23] +.sym 2744 w_rx_24_fifo_data[23] +.sym 2745 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2750 w_rx_09_fifo_data[21] +.sym 2751 w_rx_24_fifo_data[21] +.sym 2752 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2755 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 2757 w_rx_24_fifo_data[27] +.sym 2758 w_rx_09_fifo_data[27] +.sym 2762 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2764 w_rx_09_fifo_data[19] +.sym 2768 w_rx_09_fifo_data[25] +.sym 2769 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] .sym 2771 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2772 lvds_clock_$glb_clk .sym 2773 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2774 rx_fifo.mem_q.0.1_WDATA_1 -.sym 2775 w_rx_09_fifo_data[7] -.sym 2776 rx_fifo.mem_q.0.3_WDATA_3 -.sym 2777 rx_fifo.mem_q.0.3_WDATA -.sym 2778 w_rx_09_fifo_data[5] -.sym 2779 w_rx_09_fifo_data[9] -.sym 2780 rx_fifo.mem_q.0.3_WDATA_1 -.sym 2781 rx_fifo.mem_q.0.1_WDATA -.sym 2790 rx_fifo.rd_addr[7] -.sym 2800 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2803 rx_fifo.mem_q.0.2_WDATA_3 -.sym 2805 w_rx_24_fifo_data[4] -.sym 2807 rx_fifo.mem_q.0.2_WDATA_2 -.sym 2809 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 2811 rx_fifo.rd_addr_gray_wr[0] -.sym 2814 rx_fifo.rd_addr[9] -.sym 2832 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2833 w_rx_24_fifo_data[4] -.sym 2836 w_rx_24_fifo_data[6] -.sym 2837 w_rx_24_fifo_data[10] -.sym 2838 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2839 w_rx_24_fifo_data[7] -.sym 2840 w_rx_24_fifo_data[12] -.sym 2841 w_rx_09_fifo_data[6] -.sym 2842 w_rx_24_fifo_data[8] -.sym 2847 w_rx_24_fifo_data[5] -.sym 2852 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2860 w_rx_24_fifo_data[6] -.sym 2861 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2863 w_rx_09_fifo_data[6] -.sym 2867 w_rx_24_fifo_data[4] -.sym 2869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2872 w_rx_24_fifo_data[8] -.sym 2874 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2879 w_rx_24_fifo_data[12] -.sym 2881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2884 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2886 w_rx_24_fifo_data[5] -.sym 2891 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2892 w_rx_24_fifo_data[10] -.sym 2896 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2899 w_rx_24_fifo_data[7] -.sym 2903 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2905 w_rx_24_fifo_data[6] -.sym 2906 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 2907 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 2908 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2909 rx_fifo.mem_q.0.1_WDATA_3 -.sym 2910 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 2911 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 2914 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 2916 w_rx_fifo_full -.sym 2926 rx_fifo.wr_addr[5] -.sym 2927 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2930 rx_fifo.wr_addr[9] -.sym 2933 w_rx_24_fifo_data[5] -.sym 2935 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 2937 w_rx_09_fifo_data[3] -.sym 2938 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 2942 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 2943 rx_fifo.rd_addr[8] -.sym 2944 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 2950 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2964 w_rx_24_fifo_data[10] -.sym 2965 w_rx_09_fifo_data[2] -.sym 2967 w_rx_09_fifo_data[10] -.sym 2969 w_rx_24_fifo_data[8] -.sym 2970 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 2971 w_rx_09_fifo_data[8] -.sym 2974 w_rx_09_fifo_data[4] -.sym 2987 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 2992 w_rx_09_fifo_data[6] -.sym 2995 w_rx_09_fifo_data[8] -.sym 2996 w_rx_24_fifo_data[8] -.sym 2998 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 3002 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3003 w_rx_09_fifo_data[6] -.sym 3008 w_rx_09_fifo_data[10] -.sym 3009 w_rx_24_fifo_data[10] -.sym 3010 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 3019 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3022 w_rx_09_fifo_data[2] -.sym 3026 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3028 w_rx_09_fifo_data[8] -.sym 3031 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3034 w_rx_09_fifo_data[4] -.sym 3041 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 3042 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3043 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 3044 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 3045 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 3047 w_rx_24_fifo_data[4] -.sym 3048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 3049 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] -.sym 3050 w_rx_24_fifo_data[5] -.sym 3051 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 3052 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 3056 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 3059 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 3061 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 3062 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3066 w_rx_09_fifo_data[4] -.sym 3067 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 3068 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 3069 w_rx_24_fifo_data[2] -.sym 3070 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 3072 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 3074 $PACKER_VCC_NET -.sym 3075 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 3077 rx_fifo.wr_addr[1] -.sym 3078 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3097 rx_fifo.rd_addr[9] -.sym 3110 rx_fifo.rd_addr_gray_wr[0] -.sym 3121 rx_fifo.rd_addr_gray_wr[9] -.sym 3130 rx_fifo.rd_addr[9] -.sym 3149 rx_fifo.rd_addr_gray_wr[0] -.sym 3167 rx_fifo.rd_addr_gray_wr[9] -.sym 3177 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3179 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 3180 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 3181 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 3183 rx_fifo.mem_q.0.0_WDATA -.sym 3184 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 3185 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 3186 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 3193 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 3195 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 3196 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 3197 $PACKER_VCC_NET -.sym 3200 $PACKER_VCC_NET -.sym 3201 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 3202 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 3203 w_rx_09_fifo_data[2] -.sym 3205 w_rx_24_fifo_data[3] -.sym 3208 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 3212 w_rx_09_fifo_data[1] -.sym 3215 $PACKER_VCC_NET -.sym 3221 $PACKER_VCC_NET -.sym 3226 $PACKER_VCC_NET -.sym 3234 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3235 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3248 w_rx_09_fifo_data[1] -.sym 3261 i_rst_b$SB_IO_IN -.sym 3277 w_rx_09_fifo_data[1] -.sym 3279 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3301 i_rst_b$SB_IO_IN -.sym 3302 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3311 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 3312 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3313 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 3314 w_rx_24_fifo_data[2] -.sym 3316 rx_fifo.mem_q.0.0_WDATA_3 -.sym 3318 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 3319 rx_fifo.mem_q.0.0_WDATA_2 -.sym 3320 rx_fifo.mem_q.0.0_WDATA_1 -.sym 3321 w_rx_24_fifo_data[3] -.sym 3333 rx_fifo.rd_addr[9] -.sym 3335 rx_fifo.rd_addr_gray_wr[0] -.sym 3346 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 3348 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3349 w_rx_24_fifo_data[0] -.sym 3369 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 3370 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3371 w_lvds_rx_09_d0 -.sym 3372 w_lvds_rx_09_d1 -.sym 3376 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3378 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3382 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3385 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3388 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3400 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 3401 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3402 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3406 w_lvds_rx_09_d1 -.sym 3409 w_lvds_rx_09_d0 -.sym 3412 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3414 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3418 w_lvds_rx_09_d1 -.sym 3419 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3420 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3421 w_lvds_rx_09_d0 -.sym 3431 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 3436 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3437 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3438 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3439 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 3443 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3444 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3445 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3446 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.sym 3447 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 3448 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3449 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 3450 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 3453 w_rx_09_fifo_data[1] -.sym 3454 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3455 w_rx_09_fifo_data[0] -.sym 3467 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3469 rx_fifo.wr_addr[5] -.sym 3474 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 3475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3487 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 3504 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 3506 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 3507 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3509 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 3512 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3514 $PACKER_VCC_NET -.sym 3517 $PACKER_VCC_NET -.sym 3518 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 3527 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 3529 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3531 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 3534 $nextpnr_ICESTORM_LC_1$O -.sym 3537 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 3540 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 3541 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3542 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 3543 $PACKER_VCC_NET -.sym 3544 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 3547 $PACKER_VCC_NET -.sym 3548 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3549 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 3550 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 3554 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 3555 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 3556 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 3559 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 3565 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3566 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 3567 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 3568 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 3579 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 3580 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 3581 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3582 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2774 rx_fifo.mem_q.0.0_WDATA +.sym 2776 rx_fifo.mem_i.0.3_WDATA_2 +.sym 2777 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 2778 rx_fifo.mem_i.0.1_WDATA +.sym 2779 rx_fifo.mem_i.0.3_WDATA +.sym 2780 rx_fifo.mem_i.0.3_WDATA_1 +.sym 2781 rx_fifo.mem_q.0.0_WDATA_2 +.sym 2788 rx_fifo.mem_i.0.2_WDATA +.sym 2789 w_rx_24_fifo_data[1] +.sym 2792 rx_fifo.rd_addr[8] +.sym 2795 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 2797 w_rx_24_fifo_data[28] +.sym 2799 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2800 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 2803 rx_fifo.wr_addr[0] +.sym 2805 rx_fifo.wr_addr[4] +.sym 2807 rx_fifo.wr_addr[6] +.sym 2808 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 2810 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 2829 w_rx_09_fifo_data[2] +.sym 2836 w_rx_09_fifo_data[29] +.sym 2837 w_rx_09_fifo_data[28] +.sym 2838 w_rx_09_fifo_data[3] +.sym 2842 w_rx_09_fifo_data[27] +.sym 2844 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2851 w_rx_09_fifo_data[0] +.sym 2854 w_rx_09_fifo_data[1] +.sym 2862 w_rx_09_fifo_data[29] +.sym 2863 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2866 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2869 w_rx_09_fifo_data[27] +.sym 2873 w_rx_09_fifo_data[0] +.sym 2875 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2879 w_rx_09_fifo_data[1] +.sym 2880 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2885 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2887 w_rx_09_fifo_data[28] +.sym 2891 w_rx_09_fifo_data[2] +.sym 2892 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2896 w_rx_09_fifo_data[3] +.sym 2899 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2906 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 2907 lvds_clock_$glb_clk +.sym 2908 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2909 rx_fifo.wr_addr[5] +.sym 2910 rx_fifo.wr_addr[3] +.sym 2911 rx_fifo.mem_q.0.0_WDATA_1 +.sym 2912 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 2913 rx_fifo.wr_addr[2] +.sym 2914 rx_fifo.wr_addr[1] +.sym 2915 rx_fifo.wr_addr_gray[3] +.sym 2916 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 2922 rx_fifo.wr_addr[6] +.sym 2932 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2935 rx_fifo.wr_addr[7] +.sym 2937 w_rx_09_fifo_data[0] +.sym 2940 w_rx_09_fifo_data[1] +.sym 2945 rx_fifo.wr_addr[6] +.sym 2949 rx_fifo.rd_addr_gray_wr_r[3] +.sym 2950 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 2970 rx_fifo.wr_addr[0] +.sym 2973 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 2974 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 2990 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 2992 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 2993 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 2998 rx_fifo.wr_addr[0] +.sym 3001 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3008 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3026 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3032 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3041 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 3042 lvds_clock_$glb_clk +.sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3045 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 3046 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 3047 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 3048 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3049 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 3050 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3051 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3055 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3061 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 3064 rx_fifo.mem_i.0.1_WDATA_1 +.sym 3065 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 3067 w_rx_24_fifo_data[1] +.sym 3069 rx_fifo.wr_addr[6] +.sym 3072 rx_fifo.wr_addr[2] +.sym 3073 rx_fifo.wr_addr[9] +.sym 3075 rx_fifo.wr_addr[7] +.sym 3076 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3077 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3079 rx_fifo.rd_addr_gray_wr_r[3] +.sym 3083 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.sym 3088 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3090 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3098 rx_fifo.wr_addr[3] +.sym 3099 rx_fifo.wr_addr[6] +.sym 3101 rx_fifo.wr_addr[2] +.sym 3102 rx_fifo.wr_addr[7] +.sym 3105 rx_fifo.wr_addr[5] +.sym 3106 rx_fifo.wr_addr[4] +.sym 3110 rx_fifo.wr_addr[1] +.sym 3117 rx_fifo.wr_addr[8] +.sym 3129 $nextpnr_ICESTORM_LC_6$O +.sym 3132 rx_fifo.wr_addr[1] +.sym 3135 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 +.sym 3137 rx_fifo.wr_addr[2] +.sym 3139 rx_fifo.wr_addr[1] +.sym 3141 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 +.sym 3143 rx_fifo.wr_addr[3] +.sym 3145 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 +.sym 3147 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 3149 rx_fifo.wr_addr[4] +.sym 3151 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 +.sym 3153 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 3155 rx_fifo.wr_addr[5] +.sym 3157 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 3161 rx_fifo.wr_addr[6] +.sym 3163 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 3167 rx_fifo.wr_addr[7] +.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 3173 rx_fifo.wr_addr[8] +.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 3179 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 3184 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 3186 rx_fifo.wr_addr_gray_rd[9] +.sym 3194 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 3202 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 3203 rx_fifo.wr_addr[8] +.sym 3207 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3209 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 3212 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 3213 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3215 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3221 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3226 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 3232 rx_fifo.rd_addr_gray_wr_r[3] +.sym 3233 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 3234 rx_fifo.rd_addr_gray_wr_r[6] +.sym 3236 rx_fifo.rd_addr_gray_wr_r[2] +.sym 3237 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 3238 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3239 rx_fifo.rd_addr_gray_wr[6] +.sym 3240 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3241 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 3242 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 3243 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 3244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 3245 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 3246 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3247 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3250 rx_fifo.wr_addr[9] +.sym 3260 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3263 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] +.sym 3267 rx_fifo.wr_addr[9] +.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 3271 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 3272 rx_fifo.rd_addr_gray_wr_r[2] +.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 3278 rx_fifo.rd_addr_gray_wr[6] +.sym 3283 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 3285 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3286 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] +.sym 3289 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 3290 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 3292 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 3297 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3298 rx_fifo.rd_addr_gray_wr_r[6] +.sym 3301 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 3307 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 3308 rx_fifo.rd_addr_gray_wr_r[3] +.sym 3310 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 3312 lvds_clock_$glb_clk +.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] +.sym 3315 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 3316 rx_fifo.wr_addr[9] +.sym 3317 rx_fifo.wr_addr_gray[7] +.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 3320 rx_fifo.wr_addr[8] +.sym 3321 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 3331 rx_fifo.wr_addr_gray_rd[9] +.sym 3332 rx_fifo.rd_addr_gray_wr_r[6] +.sym 3333 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 3335 rx_fifo.rd_addr_gray_wr[6] +.sym 3339 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3340 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 3343 rx_fifo.wr_addr[8] +.sym 3346 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3348 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 3350 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 3359 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3361 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 3367 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3368 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3369 rx_fifo.rd_addr_gray_wr_r[6] +.sym 3370 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 3372 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3375 rx_fifo.rd_addr_gray[4] +.sym 3377 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3378 rx_fifo.rd_addr_gray_wr[2] +.sym 3379 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] +.sym 3380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 3381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3383 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3385 rx_fifo.rd_addr_gray_wr[4] +.sym 3393 i_rst_b$SB_IO_IN +.sym 3397 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3402 rx_fifo.rd_addr_gray_wr[4] +.sym 3406 i_rst_b$SB_IO_IN +.sym 3408 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 3413 rx_fifo.rd_addr_gray[4] +.sym 3420 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3421 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 3424 rx_fifo.rd_addr_gray_wr[2] +.sym 3430 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 3432 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] +.sym 3436 rx_fifo.rd_addr_gray_wr_r[6] +.sym 3437 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3438 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3439 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3442 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3443 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3445 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3447 lvds_clock_$glb_clk +.sym 3449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 3450 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 3451 rx_fifo.mem_q.0.0_WDATA_3 +.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 3453 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 3454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 3455 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3456 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 3457 rx_fifo.rd_addr_gray[4] +.sym 3462 rx_fifo.rd_addr_gray_wr_r[9] +.sym 3466 rx_fifo.rd_addr_gray_wr[2] +.sym 3468 rx_fifo.rd_addr_gray_wr_r[3] +.sym 3471 rx_fifo.rd_addr_gray_wr_r[2] +.sym 3472 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3476 w_rx_09_fifo_data[0] +.sym 3477 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3480 w_rx_09_fifo_data[1] +.sym 3481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3485 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3486 w_lvds_rx_09_d1 +.sym 3493 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3502 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] +.sym 3503 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3504 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3505 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3506 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3507 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] +.sym 3509 rx_fifo.rd_addr_gray_wr_r[9] +.sym 3510 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3512 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.sym 3513 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3514 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3517 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 3519 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3522 w_lvds_rx_09_d0 +.sym 3523 w_lvds_rx_09_d1 +.sym 3524 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3526 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3533 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] +.sym 3536 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3541 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3542 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3547 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3548 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3549 w_lvds_rx_09_d0 +.sym 3550 w_lvds_rx_09_d1 +.sym 3559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3560 rx_fifo.rd_addr_gray_wr_r[9] +.sym 3562 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] +.sym 3566 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] +.sym 3567 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.sym 3568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] +.sym 3571 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3574 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 3577 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 3578 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 3579 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 3580 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 3581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3582 lvds_clock_$glb_clk .sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3587 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 3589 w_rx_24_fifo_data[0] -.sym 3591 w_rx_24_fifo_data[1] -.sym 3597 w_rx_09_fifo_data[0] -.sym 3614 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3638 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3642 w_lvds_rx_24_d1 -.sym 3643 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3644 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] +.sym 3584 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3585 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3587 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 3588 w_rx_fifo_full +.sym 3591 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 3592 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3597 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 3599 rx_fifo.rd_addr_gray_wr_r[8] +.sym 3600 w_rx_data[0] +.sym 3601 w_rx_24_fifo_data[0] +.sym 3608 $PACKER_VCC_NET +.sym 3609 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3611 $PACKER_VCC_NET +.sym 3614 rx_fifo.rd_addr_gray_wr_r[3] +.sym 3617 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3619 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3637 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3638 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3639 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3641 w_lvds_rx_09_d0 +.sym 3643 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 3645 w_lvds_rx_24_d0 -.sym 3646 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3647 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 3648 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 3652 $PACKER_VCC_NET -.sym 3656 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 3657 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 3658 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3662 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 3664 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 3669 $nextpnr_ICESTORM_LC_0$O -.sym 3671 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 3675 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 3676 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3677 $PACKER_VCC_NET -.sym 3678 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 3679 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 3682 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3683 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 3684 $PACKER_VCC_NET -.sym 3685 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 3689 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 3694 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 3695 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3696 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3697 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3700 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3701 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 3702 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 3703 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 3706 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3707 w_lvds_rx_24_d1 -.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3646 w_lvds_rx_24_d1 +.sym 3649 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3651 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3653 w_lvds_rx_09_d1 +.sym 3654 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3655 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 3661 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3665 w_rx_fifo_full +.sym 3671 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3673 rx_fifo.rd_addr_gray_wr_r[4] +.sym 3676 w_lvds_rx_24_d0 +.sym 3677 w_lvds_rx_24_d1 +.sym 3682 w_lvds_rx_09_d1 +.sym 3684 w_lvds_rx_09_d0 +.sym 3688 w_rx_fifo_full +.sym 3689 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3690 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3694 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3696 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3697 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3700 w_lvds_rx_24_d0 +.sym 3701 w_lvds_rx_24_d1 +.sym 3702 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3706 w_lvds_rx_24_d1 +.sym 3707 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 3709 w_lvds_rx_24_d0 -.sym 3715 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 3716 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.sym 3717 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3712 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3713 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3716 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 3717 lvds_clock_$glb_clk .sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3719 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 3720 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 3725 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3774 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3777 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3778 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3783 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3788 w_lvds_rx_24_d0 -.sym 3789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3793 w_lvds_rx_24_d1 -.sym 3801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3817 w_lvds_rx_24_d0 -.sym 3820 w_lvds_rx_24_d1 -.sym 3835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3836 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3838 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3847 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3848 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 3849 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3850 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3720 w_rx_09_fifo_data[0] +.sym 3721 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 3722 w_rx_09_fifo_data[1] +.sym 3733 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3740 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3744 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 3747 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3751 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3752 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 3773 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3774 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.sym 3776 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3778 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3780 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3784 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3785 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3792 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3801 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 3808 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3823 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3824 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 3825 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3826 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3830 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3831 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3836 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3838 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3842 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 3843 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 3851 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3852 lvds_clock_$glb_clk .sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3860 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 4238 w_rx_fifo_pulled_data[24] -.sym 4242 w_rx_fifo_pulled_data[26] -.sym 4256 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 4259 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 4261 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 4300 w_rx_fifo_pulled_data[26] -.sym 4304 w_rx_fifo_pulled_data[25] -.sym 4336 w_rx_fifo_pulled_data[25] -.sym 4349 w_rx_fifo_pulled_data[26] -.sym 4358 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 4359 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4360 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4366 w_rx_fifo_pulled_data[25] -.sym 4370 w_rx_fifo_pulled_data[27] -.sym 4383 rx_fifo.mem_i.0.2_WDATA_2 -.sym 4384 rx_fifo.mem_i.0.1_WDATA_3 -.sym 4398 rx_fifo.wr_addr[0] -.sym 4402 rx_fifo.wr_addr[5] -.sym 4406 $PACKER_VCC_NET -.sym 4408 rx_fifo.rd_addr[4] -.sym 4410 smi_ctrl_ins.int_cnt_rx[3] -.sym 4414 rx_fifo.rd_addr[5] -.sym 4415 rx_fifo.rd_addr[3] -.sym 4418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 4422 w_rx_fifo_pulled_data[17] -.sym 4425 rx_fifo.mem_i.0.0_WDATA_3 -.sym 4427 w_smi_data_output[3] -.sym 4430 smi_ctrl_ins.int_cnt_rx[4] -.sym 4431 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 4443 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 4451 w_rx_fifo_pulled_data[24] -.sym 4452 w_rx_fifo_pulled_data[17] -.sym 4454 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 4455 smi_ctrl_ins.int_cnt_rx[4] -.sym 4456 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 4463 w_rx_fifo_pulled_data[18] -.sym 4465 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 4467 smi_ctrl_ins.int_cnt_rx[3] -.sym 4471 w_rx_fifo_pulled_data[27] -.sym 4475 smi_ctrl_ins.int_cnt_rx[3] -.sym 4476 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 4477 smi_ctrl_ins.int_cnt_rx[4] -.sym 4478 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 4481 w_rx_fifo_pulled_data[18] -.sym 4494 w_rx_fifo_pulled_data[27] -.sym 4499 w_rx_fifo_pulled_data[24] -.sym 4505 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 4506 smi_ctrl_ins.int_cnt_rx[4] -.sym 4507 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 4508 smi_ctrl_ins.int_cnt_rx[3] -.sym 4517 w_rx_fifo_pulled_data[17] -.sym 4521 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 4522 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4523 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4525 w_rx_fifo_pulled_data[16] -.sym 4529 w_rx_fifo_pulled_data[18] -.sym 4540 rx_fifo.rd_addr[7] -.sym 4541 rx_fifo.rd_addr[9] -.sym 4542 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4543 rx_fifo.rd_addr[6] -.sym 4545 rx_fifo.rd_addr[8] -.sym 4549 rx_fifo.rd_addr[0] -.sym 4551 rx_fifo.rd_addr[2] -.sym 4552 w_rx_fifo_pulled_data[8] -.sym 4554 rx_fifo.rd_addr[4] -.sym 4555 w_rx_fifo_pulled_data[10] -.sym 4558 rx_fifo.rd_addr[1] -.sym 4559 smi_ctrl_ins.int_cnt_rx[3] -.sym 4565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 4566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 4567 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 4568 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 4569 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 4570 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 4571 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 4572 smi_ctrl_ins.int_cnt_rx[3] -.sym 4573 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 4576 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 4577 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 4578 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 4579 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 4580 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 4583 i_rst_b$SB_IO_IN -.sym 4587 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 4588 w_rx_24_fifo_data[19] -.sym 4589 w_rx_09_fifo_data[19] -.sym 4592 smi_ctrl_ins.int_cnt_rx[4] -.sym 4596 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4598 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 4601 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 4605 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 4607 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 4610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 4611 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 4616 w_rx_09_fifo_data[19] -.sym 4618 w_rx_24_fifo_data[19] -.sym 4619 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 4624 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 4628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 4630 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 4634 smi_ctrl_ins.int_cnt_rx[4] -.sym 4635 smi_ctrl_ins.int_cnt_rx[3] -.sym 4636 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 4637 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 4640 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 4641 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 4642 smi_ctrl_ins.int_cnt_rx[3] -.sym 4643 smi_ctrl_ins.int_cnt_rx[4] -.sym 4644 i_rst_b$SB_IO_IN -.sym 4645 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4648 w_rx_fifo_pulled_data[17] -.sym 4652 w_rx_fifo_pulled_data[19] -.sym 4657 w_rx_fifo_full -.sym 4661 w_rx_09_fifo_data[29] -.sym 4662 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4663 rx_fifo.mem_i.0.3_WDATA_1 -.sym 4664 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 4665 rx_fifo.wr_addr[3] -.sym 4668 smi_ctrl_ins.int_cnt_rx[4] -.sym 4669 w_smi_data_output[0] -.sym 4671 rx_fifo.wr_addr[0] -.sym 4673 rx_fifo.rd_addr[9] -.sym 4675 rx_fifo.mem_q.0.2_WDATA -.sym 4677 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4678 rx_fifo.wr_addr[5] -.sym 4680 rx_fifo.wr_addr[0] -.sym 4681 rx_fifo.wr_addr[5] -.sym 4682 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4689 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 4692 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 4693 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 4697 w_rx_fifo_pulled_data[16] -.sym 4698 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 4699 w_rx_09_fifo_data[17] -.sym 4700 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4704 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 4707 smi_ctrl_ins.int_cnt_rx[4] -.sym 4708 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 4709 w_rx_fifo_pulled_data[19] -.sym 4710 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 4712 w_rx_24_fifo_data[17] -.sym 4713 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 4716 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 4718 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 4719 smi_ctrl_ins.int_cnt_rx[3] -.sym 4721 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 4722 smi_ctrl_ins.int_cnt_rx[4] -.sym 4723 smi_ctrl_ins.int_cnt_rx[3] -.sym 4724 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 4727 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 4728 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 4729 smi_ctrl_ins.int_cnt_rx[4] -.sym 4730 smi_ctrl_ins.int_cnt_rx[3] -.sym 4733 smi_ctrl_ins.int_cnt_rx[3] -.sym 4734 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 4735 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 4736 smi_ctrl_ins.int_cnt_rx[4] -.sym 4741 w_rx_fifo_pulled_data[19] -.sym 4747 w_rx_fifo_pulled_data[16] -.sym 4751 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 4752 smi_ctrl_ins.int_cnt_rx[3] -.sym 4753 smi_ctrl_ins.int_cnt_rx[4] -.sym 4754 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 4757 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 4758 smi_ctrl_ins.int_cnt_rx[4] -.sym 4759 smi_ctrl_ins.int_cnt_rx[3] -.sym 4760 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 4763 w_rx_24_fifo_data[17] -.sym 4764 w_rx_09_fifo_data[17] -.sym 4765 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4767 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 4768 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4769 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4771 w_rx_fifo_pulled_data[4] -.sym 4775 w_rx_fifo_pulled_data[6] -.sym 4783 rx_fifo.rd_addr[6] -.sym 4788 rx_fifo.rd_addr[3] -.sym 4790 rx_fifo.rd_addr[7] -.sym 4795 $PACKER_VCC_NET -.sym 4796 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 4799 i_rst_b$SB_IO_IN -.sym 4803 rx_fifo.rd_addr[3] -.sym 4804 rx_fifo.rd_addr[5] -.sym 4805 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 4824 w_rx_fifo_pulled_data[8] -.sym 4825 w_rx_fifo_pulled_data[10] -.sym 4832 w_rx_fifo_pulled_data[6] -.sym 4834 w_rx_fifo_pulled_data[13] -.sym 4838 w_rx_fifo_pulled_data[3] -.sym 4842 w_rx_fifo_pulled_data[15] -.sym 4845 w_rx_fifo_pulled_data[13] -.sym 4853 w_rx_fifo_pulled_data[8] -.sym 4859 w_rx_fifo_pulled_data[10] -.sym 4865 w_rx_fifo_pulled_data[15] -.sym 4868 w_rx_fifo_pulled_data[3] -.sym 4874 w_rx_fifo_pulled_data[6] -.sym 4890 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 4891 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4892 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4894 w_rx_fifo_pulled_data[5] -.sym 4898 w_rx_fifo_pulled_data[7] -.sym 4907 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 4908 rx_fifo.rd_addr[1] -.sym 4912 rx_fifo.rd_addr[0] -.sym 4914 rx_fifo.rd_addr[2] -.sym 4915 rx_fifo.wr_addr[3] -.sym 4917 rx_fifo.mem_q.0.1_WDATA_3 -.sym 4920 w_rx_fifo_pulled_data[13] -.sym 4924 w_rx_fifo_pulled_data[3] -.sym 4927 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 4928 w_rx_fifo_pulled_data[15] -.sym 4934 w_rx_09_fifo_data[11] -.sym 4935 w_rx_24_fifo_data[11] -.sym 4937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4938 w_rx_24_fifo_data[15] -.sym 4939 w_rx_09_fifo_data[9] -.sym 4940 w_rx_24_fifo_data[13] -.sym 4942 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 4943 w_rx_24_fifo_data[11] -.sym 4952 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4956 w_rx_24_fifo_data[9] -.sym 4958 w_rx_24_fifo_data[17] -.sym 4959 i_rst_b$SB_IO_IN -.sym 4961 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 4967 w_rx_24_fifo_data[15] -.sym 4968 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4973 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4976 w_rx_24_fifo_data[9] -.sym 4979 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 4980 w_rx_24_fifo_data[11] -.sym 4981 w_rx_09_fifo_data[11] -.sym 4986 i_rst_b$SB_IO_IN -.sym 4987 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 4993 w_rx_24_fifo_data[13] -.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 4999 w_rx_24_fifo_data[17] -.sym 5003 w_rx_24_fifo_data[11] -.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5010 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5011 w_rx_09_fifo_data[9] -.sym 5012 w_rx_24_fifo_data[9] +.sym 3855 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 3856 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 3857 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 3858 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 3859 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 3860 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 3861 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 3883 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3897 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 3913 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 3916 $PACKER_VCC_NET +.sym 3917 $PACKER_VCC_NET +.sym 3918 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] +.sym 3919 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3921 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3922 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 3925 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 3932 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 3933 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 3934 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 3936 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] +.sym 3937 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 3939 $nextpnr_ICESTORM_LC_0$O +.sym 3941 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 3945 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 +.sym 3946 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3947 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] +.sym 3948 $PACKER_VCC_NET +.sym 3949 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 3952 $PACKER_VCC_NET +.sym 3953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3954 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 3955 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 +.sym 3959 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 3964 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 3965 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3966 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 3967 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 3970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 3971 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 3972 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 3973 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 3978 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 3983 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] +.sym 3984 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 3986 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 3987 lvds_clock_$glb_clk +.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 3989 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 3993 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 4209 o_shdn_tx_lna$SB_IO_OUT +.sym 4238 w_rx_fifo_pulled_data[12] +.sym 4242 w_rx_fifo_pulled_data[14] +.sym 4366 w_rx_fifo_pulled_data[13] +.sym 4370 w_rx_fifo_pulled_data[15] +.sym 4373 rx_fifo.wr_addr[9] +.sym 4375 rx_fifo.wr_addr[1] +.sym 4376 rx_fifo.wr_addr[9] +.sym 4377 rx_fifo.wr_addr[0] +.sym 4380 rx_fifo.wr_addr[4] +.sym 4383 rx_fifo.wr_addr[6] +.sym 4413 rx_fifo.rd_addr[0] +.sym 4416 w_rx_09_fifo_data[28] +.sym 4420 rx_fifo.wr_addr[2] +.sym 4421 rx_fifo.wr_addr[8] +.sym 4422 rx_fifo.wr_addr[7] +.sym 4424 rx_fifo.mem_q.0.2_WDATA_2 +.sym 4426 rx_fifo.wr_addr[1] +.sym 4428 rx_fifo.wr_addr[5] +.sym 4429 rx_fifo.wr_addr[0] +.sym 4431 rx_fifo.wr_addr[4] +.sym 4444 w_rx_09_fifo_data[10] +.sym 4446 w_rx_09_fifo_data[13] +.sym 4449 w_rx_09_fifo_data[16] +.sym 4450 w_rx_24_fifo_data[13] +.sym 4460 w_rx_09_fifo_data[8] +.sym 4462 w_rx_09_fifo_data[12] +.sym 4463 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4464 w_rx_09_fifo_data[14] +.sym 4465 w_rx_24_fifo_data[12] +.sym 4468 w_rx_24_fifo_data[14] +.sym 4473 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4475 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4476 w_rx_24_fifo_data[13] +.sym 4477 w_rx_09_fifo_data[13] +.sym 4481 w_rx_24_fifo_data[14] +.sym 4482 w_rx_09_fifo_data[14] +.sym 4484 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4487 w_rx_09_fifo_data[8] +.sym 4490 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4494 w_rx_09_fifo_data[12] +.sym 4495 w_rx_24_fifo_data[12] +.sym 4496 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4499 w_rx_09_fifo_data[10] +.sym 4502 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4505 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4507 w_rx_09_fifo_data[16] +.sym 4511 w_rx_09_fifo_data[12] +.sym 4514 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4517 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4518 w_rx_09_fifo_data[14] +.sym 4521 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 4522 lvds_clock_$glb_clk +.sym 4523 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4525 w_rx_fifo_pulled_data[8] +.sym 4529 w_rx_fifo_pulled_data[10] +.sym 4546 w_rx_24_fifo_data[13] +.sym 4547 $PACKER_VCC_NET +.sym 4548 rx_fifo.wr_addr[8] +.sym 4551 w_rx_24_fifo_data[12] +.sym 4552 w_rx_09_fifo_data[24] +.sym 4555 rx_fifo.wr_addr[3] +.sym 4559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 4565 w_rx_09_fifo_data[20] +.sym 4566 w_rx_24_fifo_data[18] +.sym 4567 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4569 w_rx_24_fifo_data[8] +.sym 4570 w_rx_09_fifo_data[22] +.sym 4571 w_rx_24_fifo_data[16] +.sym 4572 w_rx_09_fifo_data[16] +.sym 4575 w_rx_09_fifo_data[8] +.sym 4578 w_rx_09_fifo_data[18] +.sym 4579 w_rx_09_fifo_data[24] +.sym 4581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4583 w_rx_09_fifo_data[26] +.sym 4598 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4600 w_rx_09_fifo_data[18] +.sym 4605 w_rx_24_fifo_data[16] +.sym 4606 w_rx_09_fifo_data[16] +.sym 4607 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4611 w_rx_09_fifo_data[24] +.sym 4612 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4617 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4618 w_rx_09_fifo_data[8] +.sym 4619 w_rx_24_fifo_data[8] +.sym 4622 w_rx_09_fifo_data[26] +.sym 4624 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4629 w_rx_09_fifo_data[20] +.sym 4631 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4636 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 4637 w_rx_09_fifo_data[22] +.sym 4640 w_rx_24_fifo_data[18] +.sym 4641 w_rx_09_fifo_data[18] +.sym 4643 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4644 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 4645 lvds_clock_$glb_clk +.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4648 w_rx_fifo_pulled_data[9] +.sym 4652 w_rx_fifo_pulled_data[11] +.sym 4659 w_rx_09_fifo_data[20] +.sym 4660 $PACKER_VCC_NET +.sym 4663 rx_fifo.mem_i.0.0_WDATA_3 +.sym 4664 rx_fifo.wr_addr[6] +.sym 4665 rx_fifo.wr_addr[9] +.sym 4669 w_rx_09_fifo_data[28] +.sym 4678 w_rx_09_fifo_data[22] +.sym 4691 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4692 w_rx_09_fifo_data[10] +.sym 4693 w_rx_24_fifo_data[14] +.sym 4698 w_rx_24_fifo_data[6] +.sym 4699 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4703 w_rx_24_fifo_data[12] +.sym 4707 w_rx_24_fifo_data[10] +.sym 4709 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4710 w_rx_24_fifo_data[16] +.sym 4716 w_rx_24_fifo_data[8] +.sym 4727 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4730 w_rx_24_fifo_data[16] +.sym 4733 w_rx_09_fifo_data[10] +.sym 4734 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4736 w_rx_24_fifo_data[10] +.sym 4739 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4741 w_rx_24_fifo_data[8] +.sym 4746 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4748 w_rx_24_fifo_data[6] +.sym 4751 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4754 w_rx_24_fifo_data[12] +.sym 4758 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4760 w_rx_24_fifo_data[14] +.sym 4763 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4765 w_rx_24_fifo_data[10] +.sym 4767 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4768 lvds_clock_$glb_clk +.sym 4769 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4771 w_rx_fifo_pulled_data[24] +.sym 4775 w_rx_fifo_pulled_data[26] +.sym 4782 rx_fifo.mem_i.0.0_WDATA_1 +.sym 4783 rx_fifo.rd_addr[3] +.sym 4784 rx_fifo.wr_addr[6] +.sym 4785 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4786 rx_fifo.mem_q.0.2_WDATA +.sym 4787 rx_fifo.wr_addr[4] +.sym 4788 rx_fifo.mem_q.0.2_WDATA_1 +.sym 4789 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 4791 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 4792 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 4794 rx_fifo.mem_q.0.0_WDATA +.sym 4796 rx_fifo.rd_addr[0] +.sym 4798 w_rx_09_fifo_data[28] +.sym 4812 w_rx_24_fifo_data[18] +.sym 4815 w_rx_09_fifo_data[26] +.sym 4817 w_rx_24_fifo_data[4] +.sym 4818 w_rx_24_fifo_data[26] +.sym 4822 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4823 w_rx_24_fifo_data[25] +.sym 4825 w_rx_24_fifo_data[2] +.sym 4827 w_rx_09_fifo_data[6] +.sym 4829 w_rx_24_fifo_data[6] +.sym 4830 w_rx_09_fifo_data[4] +.sym 4835 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4836 w_rx_09_fifo_data[25] +.sym 4841 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4844 w_rx_24_fifo_data[4] +.sym 4845 w_rx_09_fifo_data[4] +.sym 4847 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4850 w_rx_24_fifo_data[26] +.sym 4852 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4853 w_rx_09_fifo_data[26] +.sym 4857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4858 w_rx_24_fifo_data[4] +.sym 4862 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4863 w_rx_09_fifo_data[25] +.sym 4864 w_rx_24_fifo_data[25] +.sym 4868 w_rx_09_fifo_data[6] +.sym 4869 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4870 w_rx_24_fifo_data[6] +.sym 4874 w_rx_24_fifo_data[25] +.sym 4876 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4883 w_rx_24_fifo_data[2] +.sym 4886 w_rx_24_fifo_data[18] +.sym 4888 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4890 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4891 lvds_clock_$glb_clk +.sym 4892 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4894 w_rx_fifo_pulled_data[25] +.sym 4898 w_rx_fifo_pulled_data[27] +.sym 4905 rx_fifo.mem_q.0.1_WDATA_3 +.sym 4906 rx_fifo.wr_addr[6] +.sym 4909 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 4911 rx_fifo.wr_addr[0] +.sym 4913 rx_fifo.wr_addr[4] +.sym 4915 rx_fifo.mem_q.0.1_WDATA_2 +.sym 4917 rx_fifo.wr_addr[5] +.sym 4918 rx_fifo.mem_i.0.3_WDATA_1 +.sym 4919 rx_fifo.wr_addr[8] +.sym 4920 rx_fifo.wr_addr[7] +.sym 4922 rx_fifo.wr_addr[9] +.sym 4923 w_rx_24_fifo_data[0] +.sym 4925 rx_fifo.wr_addr[2] +.sym 4926 rx_fifo.wr_addr[0] +.sym 4927 rx_fifo.wr_addr[1] +.sym 4928 rx_fifo.wr_addr[4] +.sym 4936 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 4937 w_rx_09_fifo_data[20] +.sym 4939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4940 w_rx_24_fifo_data[1] +.sym 4941 w_rx_24_fifo_data[20] +.sym 4944 w_rx_24_fifo_data[22] +.sym 4946 w_rx_24_fifo_data[28] +.sym 4947 w_rx_24_fifo_data[27] +.sym 4948 w_rx_09_fifo_data[22] +.sym 4949 w_rx_24_fifo_data[0] +.sym 4950 w_rx_24_fifo_data[29] +.sym 4961 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4967 w_rx_24_fifo_data[27] +.sym 4970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4973 w_rx_09_fifo_data[22] +.sym 4975 w_rx_24_fifo_data[22] +.sym 4976 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4982 w_rx_24_fifo_data[20] +.sym 4985 w_rx_24_fifo_data[20] +.sym 4986 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 4987 w_rx_09_fifo_data[20] +.sym 4993 w_rx_24_fifo_data[1] +.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 4999 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 5000 w_rx_24_fifo_data[29] +.sym 5003 w_rx_24_fifo_data[0] +.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 5009 w_rx_24_fifo_data[28] +.sym 5011 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5014 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5014 lvds_clock_$glb_clk .sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5017 w_rx_fifo_pulled_data[12] -.sym 5021 w_rx_fifo_pulled_data[14] -.sym 5030 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5031 rx_fifo.rd_addr[8] -.sym 5032 rx_fifo.rd_addr[1] -.sym 5033 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5035 rx_fifo.rd_addr[4] -.sym 5038 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 5039 rx_fifo.rd_addr[9] -.sym 5041 rx_fifo.rd_addr[0] -.sym 5043 w_rx_fifo_pulled_data[8] -.sym 5049 rx_fifo.rd_addr[2] -.sym 5050 rx_fifo.rd_addr[4] -.sym 5051 w_rx_fifo_pulled_data[10] -.sym 5058 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5061 w_rx_24_fifo_data[15] -.sym 5062 w_rx_24_fifo_data[12] -.sym 5066 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5069 w_rx_24_fifo_data[7] -.sym 5071 w_rx_24_fifo_data[13] -.sym 5073 w_rx_09_fifo_data[3] -.sym 5074 w_rx_09_fifo_data[7] -.sym 5077 w_rx_24_fifo_data[5] -.sym 5083 w_rx_09_fifo_data[13] -.sym 5085 w_rx_09_fifo_data[5] -.sym 5086 w_rx_09_fifo_data[12] -.sym 5087 w_rx_09_fifo_data[15] -.sym 5090 w_rx_24_fifo_data[5] -.sym 5091 w_rx_09_fifo_data[5] -.sym 5092 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5096 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5098 w_rx_09_fifo_data[5] -.sym 5102 w_rx_09_fifo_data[12] -.sym 5104 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5105 w_rx_24_fifo_data[12] -.sym 5109 w_rx_24_fifo_data[15] -.sym 5110 w_rx_09_fifo_data[15] -.sym 5111 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5115 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5116 w_rx_09_fifo_data[3] -.sym 5120 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5122 w_rx_09_fifo_data[7] -.sym 5126 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5127 w_rx_24_fifo_data[13] -.sym 5129 w_rx_09_fifo_data[13] -.sym 5132 w_rx_09_fifo_data[7] -.sym 5134 w_rx_24_fifo_data[7] -.sym 5135 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5136 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 5137 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5138 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5140 w_rx_fifo_pulled_data[13] -.sym 5144 w_rx_fifo_pulled_data[15] +.sym 5017 w_rx_fifo_pulled_data[20] +.sym 5021 w_rx_fifo_pulled_data[22] +.sym 5028 rx_fifo.mem_q.0.1_WDATA_1 +.sym 5031 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 5032 w_rx_24_fifo_data[26] +.sym 5033 rx_fifo.wr_addr[7] +.sym 5034 w_rx_24_fifo_data[22] +.sym 5036 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5038 rx_fifo.mem_q.0.1_WDATA +.sym 5040 rx_fifo.wr_addr[8] +.sym 5041 rx_fifo.wr_addr_gray[3] +.sym 5043 i_rst_b$SB_IO_IN +.sym 5047 rx_fifo.wr_addr[3] +.sym 5051 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5057 w_rx_24_fifo_data[29] +.sym 5058 w_rx_09_fifo_data[29] +.sym 5060 w_rx_09_fifo_data[3] +.sym 5061 w_rx_24_fifo_data[3] +.sym 5062 w_rx_24_fifo_data[31] +.sym 5063 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5064 w_rx_24_fifo_data[30] +.sym 5065 w_rx_09_fifo_data[31] +.sym 5067 w_rx_09_fifo_data[2] +.sym 5069 w_rx_09_fifo_data[30] +.sym 5071 w_rx_24_fifo_data[2] +.sym 5082 w_rx_fifo_pulled_data[20] +.sym 5084 rx_fifo.mem_i.0.1_WDATA +.sym 5090 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5092 w_rx_24_fifo_data[3] +.sym 5093 w_rx_09_fifo_data[3] +.sym 5102 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5103 w_rx_09_fifo_data[30] +.sym 5105 w_rx_24_fifo_data[30] +.sym 5109 w_rx_fifo_pulled_data[20] +.sym 5116 rx_fifo.mem_i.0.1_WDATA +.sym 5120 w_rx_09_fifo_data[31] +.sym 5122 w_rx_24_fifo_data[31] +.sym 5123 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5126 w_rx_24_fifo_data[29] +.sym 5127 w_rx_09_fifo_data[29] +.sym 5128 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5132 w_rx_24_fifo_data[2] +.sym 5134 w_rx_09_fifo_data[2] +.sym 5135 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5140 w_rx_fifo_pulled_data[21] +.sym 5144 w_rx_fifo_pulled_data[23] +.sym 5149 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 5152 $PACKER_VCC_NET -.sym 5154 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 5155 rx_fifo.wr_addr[1] -.sym 5156 rx_fifo.wr_addr[3] -.sym 5159 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5161 rx_fifo.mem_q.0.3_WDATA_2 -.sym 5162 rx_fifo.wr_addr[0] -.sym 5164 rx_fifo.wr_addr[5] -.sym 5165 rx_fifo.rd_addr[9] -.sym 5166 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5168 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5169 w_rx_fifo_pulled_data[14] -.sym 5170 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 5171 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5172 rx_fifo.mem_q.0.2_WDATA -.sym 5173 rx_fifo.mem_q.0.2_WDATA_1 -.sym 5180 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 5181 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5182 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 5184 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 5185 w_rx_09_fifo_data[4] -.sym 5186 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 5187 w_rx_fifo_full -.sym 5190 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 5191 w_rx_24_fifo_data[4] -.sym 5192 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 5193 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5194 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 5195 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5196 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 5197 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 5202 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5210 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5213 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5215 w_rx_24_fifo_data[4] -.sym 5216 w_rx_09_fifo_data[4] -.sym 5219 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 5220 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 5221 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 5225 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5226 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5227 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5228 w_rx_fifo_full -.sym 5243 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5244 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5245 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 5246 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 5255 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 5256 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 5257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 5258 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 5260 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5153 rx_fifo.mem_i.0.3_WDATA +.sym 5157 rx_fifo.mem_i.0.3_WDATA_2 +.sym 5158 rx_fifo.wr_addr[6] +.sym 5159 rx_fifo.wr_addr[7] +.sym 5161 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 5162 rx_fifo.wr_addr[9] +.sym 5163 rx_fifo.wr_addr[2] +.sym 5174 rx_fifo.mem_q.0.0_WDATA_2 +.sym 5182 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5183 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5184 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5189 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5190 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 5191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5192 w_rx_24_fifo_data[1] +.sym 5194 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5199 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5202 w_rx_09_fifo_data[1] +.sym 5203 i_rst_b$SB_IO_IN +.sym 5214 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5222 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5226 w_rx_24_fifo_data[1] +.sym 5227 w_rx_09_fifo_data[1] +.sym 5228 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5232 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5234 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5240 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 5244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5250 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5255 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5257 i_rst_b$SB_IO_IN +.sym 5259 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5260 lvds_clock_$glb_clk .sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5263 w_rx_fifo_pulled_data[8] -.sym 5267 w_rx_fifo_pulled_data[10] -.sym 5275 rx_fifo.rd_addr[6] -.sym 5276 rx_fifo.rd_addr[1] -.sym 5279 rx_fifo.rd_addr[5] -.sym 5280 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5281 rx_fifo.rd_addr[7] -.sym 5285 rx_fifo.rd_addr[3] -.sym 5288 $PACKER_VCC_NET -.sym 5290 rx_fifo.rd_addr[5] -.sym 5291 $PACKER_VCC_NET -.sym 5292 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5294 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 5295 rx_fifo.rd_addr[3] -.sym 5296 rx_fifo.wr_addr[7] -.sym 5303 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 5305 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 5306 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 5309 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5310 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 5312 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5314 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5315 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 5316 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 5317 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 5319 rx_fifo.wr_addr[1] -.sym 5320 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 5327 w_rx_24_fifo_data[2] -.sym 5328 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 5330 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 5331 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5332 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] -.sym 5333 w_rx_24_fifo_data[3] -.sym 5334 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5336 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5337 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5338 rx_fifo.wr_addr[1] -.sym 5339 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5342 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 5343 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5344 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 5345 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] -.sym 5356 w_rx_24_fifo_data[2] -.sym 5357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 5361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 5362 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 5363 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 5366 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5367 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 5368 rx_fifo.rd_addr_gray_wr_r[9] -.sym 5369 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 5373 w_rx_24_fifo_data[3] -.sym 5374 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5378 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5379 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 5381 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 5382 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5383 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5384 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5386 w_rx_fifo_pulled_data[9] -.sym 5390 w_rx_fifo_pulled_data[11] -.sym 5393 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 5396 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 5401 rx_fifo.mem_q.0.2_WDATA_2 -.sym 5403 rx_fifo.mem_q.0.2_WDATA_3 +.sym 5263 w_rx_fifo_pulled_data[0] +.sym 5267 w_rx_fifo_pulled_data[2] +.sym 5274 rx_fifo.wr_addr[5] +.sym 5275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 5276 rx_fifo.wr_addr[1] +.sym 5278 rx_fifo.wr_addr[3] +.sym 5279 rx_fifo.rd_addr[3] +.sym 5282 rx_fifo.wr_addr[8] +.sym 5284 rx_fifo.wr_addr[2] +.sym 5285 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 5286 rx_fifo.mem_q.0.0_WDATA +.sym 5287 rx_fifo.mem_q.0.0_WDATA_1 +.sym 5288 rx_fifo.rd_addr[0] +.sym 5292 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5293 rx_fifo.wr_addr[1] +.sym 5296 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5303 rx_fifo.wr_addr[5] +.sym 5307 rx_fifo.wr_addr[2] +.sym 5312 rx_fifo.wr_addr[3] +.sym 5316 rx_fifo.wr_addr[1] +.sym 5319 rx_fifo.wr_addr[0] +.sym 5320 rx_fifo.wr_addr[4] +.sym 5321 rx_fifo.wr_addr[6] +.sym 5327 rx_fifo.wr_addr[0] +.sym 5332 rx_fifo.wr_addr[7] +.sym 5335 $nextpnr_ICESTORM_LC_4$O +.sym 5337 rx_fifo.wr_addr[0] +.sym 5341 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5343 rx_fifo.wr_addr[1] +.sym 5345 rx_fifo.wr_addr[0] +.sym 5347 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5350 rx_fifo.wr_addr[2] +.sym 5351 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5355 rx_fifo.wr_addr[3] +.sym 5357 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5359 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5361 rx_fifo.wr_addr[4] +.sym 5363 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5365 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5367 rx_fifo.wr_addr[5] +.sym 5369 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5371 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 5374 rx_fifo.wr_addr[6] +.sym 5375 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 5377 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5379 rx_fifo.wr_addr[7] +.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 5386 w_rx_fifo_pulled_data[1] +.sym 5390 w_rx_fifo_pulled_data[3] +.sym 5399 rx_fifo.wr_addr[0] +.sym 5401 rx_fifo.rd_addr[9] +.sym 5402 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5403 rx_fifo.wr_addr[8] .sym 5405 rx_fifo.wr_addr[4] -.sym 5411 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 5412 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 5420 w_rx_fifo_pulled_data[3] -.sym 5428 w_rx_09_fifo_data[3] -.sym 5433 w_rx_24_fifo_data[3] -.sym 5438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5441 w_rx_fifo_pulled_data[14] -.sym 5443 w_rx_fifo_pulled_data[0] -.sym 5447 w_rx_fifo_pulled_data[11] -.sym 5451 w_rx_fifo_pulled_data[9] -.sym 5452 w_rx_fifo_pulled_data[1] -.sym 5455 w_rx_fifo_pulled_data[2] -.sym 5462 w_rx_fifo_pulled_data[0] -.sym 5465 w_rx_fifo_pulled_data[11] -.sym 5473 w_rx_fifo_pulled_data[14] -.sym 5483 w_rx_09_fifo_data[3] -.sym 5484 w_rx_24_fifo_data[3] -.sym 5486 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5489 w_rx_fifo_pulled_data[1] -.sym 5497 w_rx_fifo_pulled_data[9] -.sym 5504 w_rx_fifo_pulled_data[2] -.sym 5505 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 5506 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 5507 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5509 w_rx_fifo_pulled_data[0] -.sym 5513 w_rx_fifo_pulled_data[2] -.sym 5522 rx_fifo.rd_addr[1] -.sym 5523 rx_fifo.rd_addr[8] -.sym 5526 rx_fifo.rd_addr[7] -.sym 5531 rx_fifo.rd_addr[6] -.sym 5533 rx_fifo.rd_addr[4] -.sym 5537 rx_fifo.mem_q.0.0_WDATA -.sym 5538 w_rx_fifo_pulled_data[1] -.sym 5539 rx_fifo.rd_addr[5] -.sym 5541 rx_fifo.rd_addr[0] -.sym 5542 rx_fifo.rd_addr[2] -.sym 5550 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5553 w_rx_09_fifo_data[1] -.sym 5554 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5555 w_rx_09_fifo_data[0] -.sym 5557 w_rx_24_fifo_data[2] -.sym 5558 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5559 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5560 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5561 w_rx_09_fifo_data[2] -.sym 5565 w_lvds_rx_09_d0 -.sym 5567 w_lvds_rx_09_d1 -.sym 5571 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5572 w_rx_24_fifo_data[1] -.sym 5575 w_rx_24_fifo_data[0] -.sym 5584 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5585 w_rx_24_fifo_data[0] -.sym 5594 w_rx_09_fifo_data[0] -.sym 5595 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5597 w_rx_24_fifo_data[0] -.sym 5606 w_lvds_rx_09_d0 -.sym 5607 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5608 w_lvds_rx_09_d1 -.sym 5609 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5612 w_rx_24_fifo_data[2] -.sym 5613 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5614 w_rx_09_fifo_data[2] -.sym 5618 w_rx_09_fifo_data[1] -.sym 5619 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 5621 w_rx_24_fifo_data[1] -.sym 5625 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5626 w_rx_24_fifo_data[1] -.sym 5628 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5629 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5630 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5632 w_rx_fifo_pulled_data[1] -.sym 5636 w_rx_fifo_pulled_data[3] -.sym 5644 rx_fifo.wr_addr[3] -.sym 5649 rx_fifo.wr_addr[0] -.sym 5651 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 5653 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 5656 rx_fifo.rd_addr[8] -.sym 5657 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 5658 w_rx_24_fifo_data[1] -.sym 5659 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5674 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5675 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 5685 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 5687 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5689 w_lvds_rx_09_d0 -.sym 5695 w_lvds_rx_09_d1 -.sym 5698 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5701 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5707 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 5712 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5713 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5730 w_lvds_rx_09_d0 -.sym 5735 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 5737 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 5738 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5741 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5743 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 5744 w_lvds_rx_09_d1 -.sym 5751 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 5752 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5763 o_shdn_tx_lna$SB_IO_OUT -.sym 5764 o_shdn_tx_lna$SB_IO_OUT -.sym 5767 rx_fifo.rd_addr[7] -.sym 5770 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5771 rx_fifo.rd_addr[1] -.sym 5772 rx_fifo.rd_addr[9] -.sym 5774 rx_fifo.rd_addr[2] -.sym 5775 rx_fifo.rd_addr[3] -.sym 5776 w_rx_09_fifo_data[2] -.sym 5777 rx_fifo.rd_addr[6] -.sym 5779 $PACKER_VCC_NET -.sym 5806 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5808 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5811 w_lvds_rx_24_d0 -.sym 5812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5813 w_lvds_rx_24_d1 -.sym 5819 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5846 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5847 w_lvds_rx_24_d1 -.sym 5848 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5849 w_lvds_rx_24_d0 -.sym 5858 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5859 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5860 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5861 w_lvds_rx_24_d1 -.sym 5873 w_lvds_rx_24_d0 -.sym 5874 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 5875 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5908 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 5909 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 5920 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 5924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5927 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5929 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5936 w_rx_fifo_full -.sym 5939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5951 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 5953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5957 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5958 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 5960 w_rx_fifo_full -.sym 5989 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5990 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5997 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 5998 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6056 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 6058 w_rx_fifo_full -.sym 6068 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 6110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 6113 w_rx_fifo_full -.sym 6120 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E -.sym 6121 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5407 rx_fifo.wr_addr[6] +.sym 5410 rx_fifo.wr_addr[8] +.sym 5411 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5412 rx_fifo.rd_addr_gray_wr_r[1] +.sym 5413 rx_fifo.mem_q.0.0_WDATA_3 +.sym 5414 w_rx_24_fifo_data[0] +.sym 5415 rx_fifo.wr_addr[7] +.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5418 rx_fifo.wr_addr[9] +.sym 5419 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5421 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5427 rx_fifo.rd_addr_gray_wr_r[6] +.sym 5428 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 5430 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5431 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5432 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5433 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5435 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5436 rx_fifo.wr_addr[9] +.sym 5437 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5440 rx_fifo.wr_addr[8] +.sym 5441 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5454 rx_fifo.rd_addr_gray_wr_r[2] +.sym 5458 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5460 rx_fifo.wr_addr[8] +.sym 5462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 5467 rx_fifo.wr_addr[9] +.sym 5468 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 5471 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5473 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5474 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5478 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 5479 rx_fifo.rd_addr_gray_wr_r[2] +.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5483 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5485 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 5491 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5496 rx_fifo.rd_addr_gray_wr_r[6] +.sym 5497 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5501 rx_fifo.wr_addr[9] +.sym 5506 r_counter_$glb_clk +.sym 5522 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 5524 $PACKER_VCC_NET +.sym 5526 io_pmod[0]$SB_IO_IN +.sym 5533 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5536 rx_fifo.wr_addr[8] +.sym 5537 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 5539 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 5540 w_rx_fifo_full +.sym 5550 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5551 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 5554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 5557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 5560 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 5561 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5562 rx_fifo.wr_addr[2] +.sym 5563 rx_fifo.wr_addr[1] +.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5567 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5568 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5571 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5572 rx_fifo.rd_addr_gray_wr_r[1] +.sym 5582 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5583 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 5584 rx_fifo.wr_addr[2] +.sym 5585 rx_fifo.rd_addr_gray_wr_r[1] +.sym 5588 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 5590 rx_fifo.rd_addr_gray_wr_r[1] +.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5602 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 5607 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5608 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5609 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5612 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5613 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5614 rx_fifo.wr_addr[1] +.sym 5615 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5624 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 5627 rx_fifo.rd_addr_gray_wr_r[0] +.sym 5628 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5629 lvds_clock_$glb_clk +.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5645 rx_fifo.rd_addr_gray_wr_r[8] +.sym 5647 $PACKER_VCC_NET +.sym 5649 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5652 $PACKER_VCC_NET +.sym 5653 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5658 rx_fifo.wr_addr_gray[7] +.sym 5673 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 5675 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5676 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 5677 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5679 w_rx_data[0] +.sym 5680 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 5681 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 5682 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5683 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 5685 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 5686 w_rx_24_fifo_data[0] +.sym 5687 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5689 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5690 w_rx_09_fifo_data[0] +.sym 5691 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] +.sym 5692 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5694 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5699 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 5700 w_rx_fifo_full +.sym 5702 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 5703 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5705 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 5706 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 5707 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 5711 w_rx_fifo_full +.sym 5712 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 5714 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 5717 w_rx_09_fifo_data[0] +.sym 5719 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5720 w_rx_24_fifo_data[0] +.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 5732 w_rx_data[0] +.sym 5735 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 5737 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 5743 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 5744 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 5747 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 5748 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] +.sym 5751 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 5752 r_counter_$glb_clk +.sym 5753 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5766 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 5769 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 5776 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5780 rx_fifo.rd_addr_gray_wr_r[9] +.sym 5783 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 5784 w_lvds_rx_09_d1 +.sym 5789 w_lvds_rx_09_d0 +.sym 5795 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 5798 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 5800 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5802 w_lvds_rx_09_d1 +.sym 5803 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 5806 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 5810 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5811 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5812 w_lvds_rx_09_d0 +.sym 5816 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5817 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 5818 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 5819 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5821 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5824 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 5826 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5828 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5829 w_lvds_rx_09_d0 +.sym 5830 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 5831 w_lvds_rx_09_d1 +.sym 5834 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5836 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5846 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 5847 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 5848 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 5849 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5852 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 5853 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 5854 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 5855 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 5871 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5872 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5875 lvds_clock_$glb_clk +.sym 5876 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5886 rx_fifo.wr_addr[1] +.sym 5889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 5892 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5906 w_rx_fifo_full +.sym 5910 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5923 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5927 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5929 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5941 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 5944 w_lvds_rx_09_d1 +.sym 5949 w_lvds_rx_09_d0 +.sym 5957 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 5958 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 5959 w_lvds_rx_09_d1 +.sym 5960 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 5966 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 5970 w_lvds_rx_09_d0 +.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce +.sym 5998 lvds_clock_$glb_clk +.sym 6017 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 6043 $PACKER_VCC_NET +.sym 6045 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 6050 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 6051 $PACKER_VCC_NET +.sym 6052 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6059 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 6061 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6068 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E +.sym 6070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6071 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 6073 $nextpnr_ICESTORM_LC_7$O +.sym 6076 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 6079 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 6080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 6081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 6082 $PACKER_VCC_NET +.sym 6083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 6086 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 6087 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 6088 $PACKER_VCC_NET +.sym 6089 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 6094 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6098 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6104 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 6105 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6107 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 6110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 6112 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 6113 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 6120 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E +.sym 6121 lvds_clock_$glb_clk .sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 6139 rx_fifo.rd_addr_gray_wr_r[3] +.sym 6165 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6166 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 6168 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 6176 w_rx_fifo_full +.sym 6177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 6197 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 6200 w_rx_fifo_full +.sym 6222 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 6223 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 6243 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.sym 6244 lvds_clock_$glb_clk +.sym 6245 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 6257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 6258 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E .sym 6294 o_shdn_tx_lna$SB_IO_OUT .sym 6314 o_shdn_tx_lna$SB_IO_OUT -.sym 6359 $PACKER_VCC_NET -.sym 6381 w_smi_data_output[3] -.sym 6387 rx_fifo.wr_addr[0] -.sym 6388 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6381 w_smi_data_output[6] .sym 6389 rx_fifo.wr_addr[9] -.sym 6390 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6394 rx_fifo.wr_addr[7] -.sym 6395 rx_fifo.mem_i.0.2_WDATA_2 -.sym 6398 rx_fifo.wr_addr[5] -.sym 6399 rx_fifo.wr_addr[8] -.sym 6401 rx_fifo.wr_addr[6] +.sym 6391 rx_fifo.wr_addr[0] +.sym 6392 rx_fifo.wr_addr[4] +.sym 6395 rx_fifo.wr_addr[6] +.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6400 rx_fifo.wr_addr[3] .sym 6404 rx_fifo.wr_addr[1] .sym 6406 $PACKER_VCC_NET -.sym 6407 rx_fifo.wr_addr[3] -.sym 6408 rx_fifo.wr_addr[4] -.sym 6413 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6422 rx_fifo.mem_i.0.1_WDATA_1 -.sym 6423 w_rx_24_fifo_data[23] -.sym 6424 rx_fifo.mem_i.0.1_WDATA -.sym 6425 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6426 w_rx_24_fifo_data[27] -.sym 6427 rx_fifo.mem_i.0.2_WDATA -.sym 6428 w_rx_24_fifo_data[25] -.sym 6429 w_rx_24_fifo_data[29] -.sym 6438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6408 rx_fifo.wr_addr[8] +.sym 6409 rx_fifo.wr_addr[7] +.sym 6411 rx_fifo.mem_q.0.3_WDATA_2 +.sym 6413 rx_fifo.mem_q.0.3_WDATA_3 +.sym 6414 rx_fifo.wr_addr[5] +.sym 6415 rx_fifo.wr_addr[2] +.sym 6422 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 6424 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 6438 rx_fifo.wr_addr[2] .sym 6439 rx_fifo.wr_addr[3] .sym 6441 rx_fifo.wr_addr[4] .sym 6442 rx_fifo.wr_addr[5] @@ -5918,96 +6150,91 @@ .sym 6446 rx_fifo.wr_addr[9] .sym 6447 rx_fifo.wr_addr[1] .sym 6448 rx_fifo.wr_addr[0] -.sym 6449 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6450 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6452 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6456 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6449 lvds_clock_$glb_clk +.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6452 rx_fifo.mem_q.0.3_WDATA_3 +.sym 6456 rx_fifo.mem_q.0.3_WDATA_2 .sym 6459 $PACKER_VCC_NET -.sym 6481 rx_fifo.wr_addr[3] -.sym 6482 rx_fifo.wr_addr[4] -.sym 6493 rx_fifo.wr_addr[7] -.sym 6495 w_smi_data_output[6] -.sym 6496 rx_fifo.wr_addr[9] -.sym 6497 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6500 rx_fifo.wr_addr[9] -.sym 6501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6503 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6504 rx_fifo.wr_addr[1] -.sym 6506 $PACKER_VCC_NET -.sym 6507 $PACKER_VCC_NET -.sym 6508 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 6512 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 6519 rx_fifo.wr_addr[8] -.sym 6521 rx_fifo.wr_addr[6] -.sym 6528 rx_fifo.rd_addr[6] -.sym 6530 rx_fifo.rd_addr[8] -.sym 6533 rx_fifo.rd_addr[3] -.sym 6535 rx_fifo.rd_addr[7] -.sym 6538 rx_fifo.rd_addr[5] -.sym 6541 $PACKER_VCC_NET +.sym 6469 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6472 rx_fifo.wr_addr[3] +.sym 6478 $PACKER_VCC_NET +.sym 6493 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6497 rx_fifo.rd_addr[6] +.sym 6500 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6505 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6506 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6508 w_rx_fifo_pulled_data[9] +.sym 6511 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 6512 rx_fifo.rd_addr[3] +.sym 6514 w_smi_data_output[1] +.sym 6515 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6517 w_rx_fifo_pulled_data[11] +.sym 6528 rx_fifo.mem_q.0.3_WDATA_1 +.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6531 rx_fifo.rd_addr[0] +.sym 6532 $PACKER_VCC_NET +.sym 6537 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6540 rx_fifo.rd_addr[3] +.sym 6541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 6542 rx_fifo.rd_addr[9] -.sym 6543 rx_fifo.rd_addr[4] -.sym 6546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 6549 rx_fifo.rd_addr[0] -.sym 6550 rx_fifo.rd_addr[1] -.sym 6555 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6557 rx_fifo.mem_i.0.2_WDATA -.sym 6559 rx_fifo.rd_addr[2] -.sym 6560 rx_fifo.mem_i.0.3_WDATA -.sym 6561 w_rx_24_fifo_data[28] -.sym 6562 w_rx_24_fifo_data[30] -.sym 6563 rx_fifo.mem_i.0.3_WDATA_3 -.sym 6564 w_rx_24_fifo_data[21] -.sym 6565 rx_fifo.mem_i.0.3_WDATA_1 -.sym 6566 w_rx_24_fifo_data[31] -.sym 6567 rx_fifo.mem_i.0.3_WDATA_2 -.sym 6576 rx_fifo.rd_addr[2] +.sym 6544 rx_fifo.mem_q.0.3_WDATA +.sym 6549 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6553 rx_fifo.rd_addr[6] +.sym 6555 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6557 rx_fifo.rd_addr[8] +.sym 6558 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6560 tx_fifo.rd_addr_gray[1] +.sym 6561 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 6562 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 6564 tx_fifo.rd_addr_gray[4] +.sym 6565 tx_fifo.rd_addr_gray[2] +.sym 6566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 6576 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 6577 rx_fifo.rd_addr[3] -.sym 6579 rx_fifo.rd_addr[4] -.sym 6580 rx_fifo.rd_addr[5] +.sym 6579 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 6581 rx_fifo.rd_addr[6] -.sym 6582 rx_fifo.rd_addr[7] +.sym 6582 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 6583 rx_fifo.rd_addr[8] .sym 6584 rx_fifo.rd_addr[9] -.sym 6585 rx_fifo.rd_addr[1] +.sym 6585 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 6586 rx_fifo.rd_addr[0] .sym 6587 r_counter_$glb_clk -.sym 6588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6589 $PACKER_VCC_NET -.sym 6593 rx_fifo.mem_i.0.2_WDATA -.sym 6597 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6602 w_rx_09_fifo_data[23] -.sym 6604 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 6610 rx_fifo.mem_i.0.1_WDATA_2 -.sym 6611 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 6613 rx_fifo.mem_i.0.1_WDATA -.sym 6616 w_rx_24_fifo_data[26] -.sym 6617 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 6619 rx_fifo.wr_addr[6] -.sym 6620 rx_fifo.wr_addr[6] -.sym 6622 rx_fifo.wr_addr[8] -.sym 6631 rx_fifo.wr_addr[3] -.sym 6632 rx_fifo.wr_addr[8] -.sym 6634 rx_fifo.wr_addr[6] -.sym 6638 rx_fifo.wr_addr[7] -.sym 6639 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6641 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6644 rx_fifo.wr_addr[9] -.sym 6645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6648 rx_fifo.wr_addr[1] -.sym 6650 $PACKER_VCC_NET -.sym 6651 rx_fifo.wr_addr[0] -.sym 6652 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6657 rx_fifo.wr_addr[4] -.sym 6660 rx_fifo.wr_addr[5] -.sym 6663 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 6665 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 6666 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 6667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 6668 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 6669 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 6678 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6593 rx_fifo.mem_q.0.3_WDATA +.sym 6597 rx_fifo.mem_q.0.3_WDATA_1 +.sym 6605 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 6607 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 6614 $PACKER_VCC_NET +.sym 6616 w_rx_fifo_pulled_data[10] +.sym 6618 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 6623 rx_fifo.rd_addr[8] +.sym 6624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 6625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 6630 rx_fifo.mem_q.0.2_WDATA_2 +.sym 6631 rx_fifo.wr_addr[9] +.sym 6632 rx_fifo.wr_addr[1] +.sym 6634 $PACKER_VCC_NET +.sym 6635 rx_fifo.wr_addr[0] +.sym 6636 rx_fifo.wr_addr[6] +.sym 6637 rx_fifo.wr_addr[7] +.sym 6641 rx_fifo.mem_q.0.2_WDATA_3 +.sym 6642 rx_fifo.wr_addr[5] +.sym 6643 rx_fifo.wr_addr[2] +.sym 6645 rx_fifo.wr_addr[4] +.sym 6648 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6655 rx_fifo.wr_addr[8] +.sym 6660 rx_fifo.wr_addr[3] +.sym 6662 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 6663 tx_fifo.rd_addr_gray_wr_r[0] +.sym 6664 tx_fifo.rd_addr_gray_wr[9] +.sym 6665 tx_fifo.rd_addr_gray_wr[0] +.sym 6666 tx_fifo.rd_addr_gray_wr[8] +.sym 6667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 6668 tx_fifo.rd_addr_gray_wr[1] +.sym 6669 tx_fifo.rd_addr_gray_wr_r[1] +.sym 6678 rx_fifo.wr_addr[2] .sym 6679 rx_fifo.wr_addr[3] .sym 6681 rx_fifo.wr_addr[4] .sym 6682 rx_fifo.wr_addr[5] @@ -6017,92 +6244,81 @@ .sym 6686 rx_fifo.wr_addr[9] .sym 6687 rx_fifo.wr_addr[1] .sym 6688 rx_fifo.wr_addr[0] -.sym 6689 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6690 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6692 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6696 rx_fifo.mem_i.0.0_WDATA_2 +.sym 6689 lvds_clock_$glb_clk +.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6692 rx_fifo.mem_q.0.2_WDATA_3 +.sym 6696 rx_fifo.mem_q.0.2_WDATA_2 .sym 6699 $PACKER_VCC_NET -.sym 6706 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6707 smi_ctrl_ins.int_cnt_rx[3] -.sym 6709 rx_fifo.mem_i.0.3_WDATA_2 +.sym 6705 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 6709 w_tx_fifo_pull .sym 6710 i_rst_b$SB_IO_IN -.sym 6713 w_rx_09_fifo_data[30] -.sym 6714 rx_fifo.rd_addr[3] -.sym 6715 rx_fifo.rd_addr[4] -.sym 6718 rx_fifo.wr_addr[4] -.sym 6719 w_rx_24_fifo_data[19] -.sym 6721 rx_fifo.wr_addr[3] -.sym 6723 rx_fifo.wr_addr[4] -.sym 6724 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 6726 w_rx_fifo_pulled_data[7] -.sym 6733 rx_fifo.rd_addr[3] -.sym 6734 rx_fifo.rd_addr[4] -.sym 6735 rx_fifo.rd_addr[7] -.sym 6736 rx_fifo.rd_addr[6] -.sym 6737 rx_fifo.rd_addr[0] -.sym 6738 rx_fifo.rd_addr[1] -.sym 6743 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 6747 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6748 rx_fifo.rd_addr[8] -.sym 6751 rx_fifo.rd_addr[9] -.sym 6759 rx_fifo.mem_i.0.0_WDATA -.sym 6761 $PACKER_VCC_NET -.sym 6762 rx_fifo.rd_addr[5] -.sym 6763 rx_fifo.rd_addr[2] -.sym 6765 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 6766 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 6767 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 6768 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 6769 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 6770 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 6771 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 6780 rx_fifo.rd_addr[2] +.sym 6719 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 6720 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6727 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6732 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 6734 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6737 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6741 rx_fifo.mem_q.0.2_WDATA_1 +.sym 6744 rx_fifo.rd_addr[3] +.sym 6747 rx_fifo.mem_q.0.2_WDATA +.sym 6750 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6752 $PACKER_VCC_NET +.sym 6753 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6755 rx_fifo.rd_addr[9] +.sym 6756 rx_fifo.rd_addr[0] +.sym 6757 rx_fifo.rd_addr[6] +.sym 6759 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6761 rx_fifo.rd_addr[8] +.sym 6764 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 6767 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 6770 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 6771 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 6780 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 6781 rx_fifo.rd_addr[3] -.sym 6783 rx_fifo.rd_addr[4] -.sym 6784 rx_fifo.rd_addr[5] +.sym 6783 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6784 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 6785 rx_fifo.rd_addr[6] -.sym 6786 rx_fifo.rd_addr[7] +.sym 6786 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 6787 rx_fifo.rd_addr[8] .sym 6788 rx_fifo.rd_addr[9] -.sym 6789 rx_fifo.rd_addr[1] +.sym 6789 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 6790 rx_fifo.rd_addr[0] .sym 6791 r_counter_$glb_clk -.sym 6792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6793 $PACKER_VCC_NET -.sym 6797 rx_fifo.mem_i.0.0_WDATA -.sym 6801 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6809 smi_ctrl_ins.int_cnt_rx[4] -.sym 6813 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 6819 rx_fifo.wr_addr[7] -.sym 6820 rx_fifo.wr_addr[9] -.sym 6822 smi_ctrl_ins.int_cnt_rx[3] -.sym 6823 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6824 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6825 w_rx_fifo_pulled_data[5] -.sym 6829 rx_fifo.wr_addr[1] -.sym 6837 rx_fifo.wr_addr[9] -.sym 6838 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6839 rx_fifo.wr_addr[3] -.sym 6842 rx_fifo.wr_addr[7] -.sym 6846 rx_fifo.wr_addr[0] -.sym 6848 rx_fifo.wr_addr[5] -.sym 6849 rx_fifo.wr_addr[6] -.sym 6850 rx_fifo.mem_q.0.1_WDATA_2 -.sym 6852 rx_fifo.wr_addr[1] -.sym 6854 rx_fifo.mem_q.0.1_WDATA_3 -.sym 6856 rx_fifo.wr_addr[4] -.sym 6859 rx_fifo.wr_addr[8] -.sym 6861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] +.sym 6797 rx_fifo.mem_q.0.2_WDATA +.sym 6801 rx_fifo.mem_q.0.2_WDATA_1 +.sym 6814 rx_fifo.wr_addr[5] +.sym 6816 rx_fifo.wr_addr[8] +.sym 6817 rx_fifo.wr_addr[2] +.sym 6819 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6821 rx_fifo.rd_addr[9] +.sym 6823 rx_fifo.rd_addr[6] +.sym 6824 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 6825 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6827 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6835 rx_fifo.wr_addr[0] +.sym 6836 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6838 rx_fifo.wr_addr[6] +.sym 6840 rx_fifo.wr_addr[8] +.sym 6843 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6845 rx_fifo.wr_addr[4] +.sym 6848 rx_fifo.wr_addr[3] +.sym 6851 rx_fifo.wr_addr[9] +.sym 6854 rx_fifo.wr_addr[2] +.sym 6856 rx_fifo.wr_addr[1] +.sym 6857 rx_fifo.wr_addr[7] +.sym 6861 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6862 rx_fifo.wr_addr[5] .sym 6863 $PACKER_VCC_NET -.sym 6866 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 6867 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6868 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 6869 rx_fifo.wr_addr_gray_rd[0] -.sym 6870 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 6871 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 6872 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 6873 rx_fifo.wr_addr_gray_rd[5] -.sym 6882 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 6867 w_rx_24_fifo_data[24] +.sym 6871 w_rx_24_fifo_data[26] +.sym 6872 w_rx_24_fifo_data[28] +.sym 6882 rx_fifo.wr_addr[2] .sym 6883 rx_fifo.wr_addr[3] .sym 6885 rx_fifo.wr_addr[4] .sym 6886 rx_fifo.wr_addr[5] @@ -6112,99 +6328,86 @@ .sym 6890 rx_fifo.wr_addr[9] .sym 6891 rx_fifo.wr_addr[1] .sym 6892 rx_fifo.wr_addr[0] -.sym 6893 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 6894 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 6896 rx_fifo.mem_q.0.1_WDATA_3 -.sym 6900 rx_fifo.mem_q.0.1_WDATA_2 +.sym 6893 lvds_clock_$glb_clk +.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6896 rx_fifo.mem_i.0.2_WDATA_3 +.sym 6900 rx_fifo.mem_i.0.2_WDATA_2 .sym 6903 $PACKER_VCC_NET -.sym 6908 rx_fifo.rd_addr[0] -.sym 6912 rx_fifo.rd_addr[2] -.sym 6915 smi_ctrl_ins.int_cnt_rx[3] -.sym 6916 rx_fifo.rd_addr[1] -.sym 6917 rx_fifo.rd_addr[4] -.sym 6920 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 6922 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 6923 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 6924 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 6925 rx_fifo.wr_addr[6] -.sym 6928 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 6929 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 6930 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 6931 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 6936 rx_fifo.rd_addr[4] -.sym 6938 rx_fifo.rd_addr[6] -.sym 6941 rx_fifo.rd_addr[3] -.sym 6942 rx_fifo.rd_addr[8] -.sym 6948 rx_fifo.rd_addr[9] -.sym 6949 $PACKER_VCC_NET -.sym 6950 rx_fifo.rd_addr[5] -.sym 6951 rx_fifo.rd_addr[1] -.sym 6952 rx_fifo.mem_q.0.1_WDATA_1 -.sym 6957 rx_fifo.rd_addr[0] -.sym 6962 rx_fifo.rd_addr[7] -.sym 6963 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 6965 rx_fifo.rd_addr[2] -.sym 6967 rx_fifo.mem_q.0.1_WDATA -.sym 6968 rx_fifo.wr_addr[7] -.sym 6969 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 6970 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 6971 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 6972 rx_fifo.wr_addr_gray[5] -.sym 6973 rx_fifo.wr_addr[1] -.sym 6974 rx_fifo.wr_addr_gray[0] -.sym 6975 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 6984 rx_fifo.rd_addr[2] +.sym 6910 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 6911 w_rx_09_fifo_data[24] +.sym 6913 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 6915 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 6916 rx_fifo.wr_addr[8] +.sym 6920 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6922 rx_fifo.rd_addr[9] +.sym 6923 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 6925 rx_fifo.rd_addr[3] +.sym 6927 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 6928 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 6930 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6931 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 6936 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6938 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 6939 rx_fifo.rd_addr[9] +.sym 6942 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6947 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 6954 rx_fifo.mem_i.0.2_WDATA +.sym 6956 rx_fifo.rd_addr[8] +.sym 6959 rx_fifo.rd_addr[0] +.sym 6960 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6961 rx_fifo.rd_addr[6] +.sym 6963 rx_fifo.mem_i.0.2_WDATA_1 +.sym 6964 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6965 $PACKER_VCC_NET +.sym 6966 rx_fifo.rd_addr[3] +.sym 6968 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 6969 rx_fifo.mem_i.0.3_WDATA_3 +.sym 6970 rx_fifo.rd_addr[6] +.sym 6971 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 6972 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 6973 rx_fifo.rd_addr_gray[3] +.sym 6974 rx_fifo.rd_addr[3] +.sym 6975 rx_fifo.rd_addr[0] +.sym 6984 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 6985 rx_fifo.rd_addr[3] -.sym 6987 rx_fifo.rd_addr[4] -.sym 6988 rx_fifo.rd_addr[5] +.sym 6987 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 6988 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 6989 rx_fifo.rd_addr[6] -.sym 6990 rx_fifo.rd_addr[7] +.sym 6990 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 6991 rx_fifo.rd_addr[8] .sym 6992 rx_fifo.rd_addr[9] -.sym 6993 rx_fifo.rd_addr[1] +.sym 6993 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 6994 rx_fifo.rd_addr[0] .sym 6995 r_counter_$glb_clk -.sym 6996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 6997 $PACKER_VCC_NET -.sym 7001 rx_fifo.mem_q.0.1_WDATA -.sym 7005 rx_fifo.mem_q.0.1_WDATA_1 -.sym 7010 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 7012 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 7013 rx_fifo.wr_addr_gray_rd[0] -.sym 7014 rx_fifo.rd_addr[6] -.sym 7018 rx_fifo.wr_addr[5] -.sym 7020 rx_fifo.wr_addr[0] -.sym 7023 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 7027 rx_fifo.wr_addr[6] -.sym 7028 i_rst_b$SB_IO_IN -.sym 7029 rx_fifo.wr_addr[8] -.sym 7030 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 7031 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 7033 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 7040 rx_fifo.mem_q.0.3_WDATA_3 +.sym 7001 rx_fifo.mem_i.0.2_WDATA +.sym 7005 rx_fifo.mem_i.0.2_WDATA_1 +.sym 7023 rx_fifo.rd_addr[8] +.sym 7029 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 7031 $PACKER_VCC_NET +.sym 7038 rx_fifo.wr_addr[6] .sym 7042 $PACKER_VCC_NET +.sym 7043 rx_fifo.wr_addr[0] .sym 7044 rx_fifo.wr_addr[8] -.sym 7049 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7050 rx_fifo.wr_addr[0] -.sym 7051 rx_fifo.mem_q.0.3_WDATA_2 -.sym 7052 rx_fifo.wr_addr[3] -.sym 7056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7057 rx_fifo.wr_addr[5] -.sym 7060 rx_fifo.wr_addr[4] -.sym 7061 rx_fifo.wr_addr[9] -.sym 7062 rx_fifo.wr_addr[7] -.sym 7063 rx_fifo.wr_addr[6] +.sym 7045 rx_fifo.wr_addr[7] +.sym 7050 rx_fifo.wr_addr[9] +.sym 7053 rx_fifo.wr_addr[4] +.sym 7055 rx_fifo.wr_addr[3] +.sym 7056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 7058 rx_fifo.wr_addr[2] +.sym 7062 rx_fifo.wr_addr[5] +.sym 7063 rx_fifo.mem_i.0.1_WDATA_2 +.sym 7065 rx_fifo.mem_i.0.1_WDATA_3 .sym 7067 rx_fifo.wr_addr[1] -.sym 7070 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 7071 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 7072 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 7073 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 7074 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 7075 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 7076 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 7077 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 7086 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 7071 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 7072 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 7074 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 7077 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 7086 rx_fifo.wr_addr[2] .sym 7087 rx_fifo.wr_addr[3] .sym 7089 rx_fifo.wr_addr[4] .sym 7090 rx_fifo.wr_addr[5] @@ -6214,98 +6417,94 @@ .sym 7094 rx_fifo.wr_addr[9] .sym 7095 rx_fifo.wr_addr[1] .sym 7096 rx_fifo.wr_addr[0] -.sym 7097 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7098 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7100 rx_fifo.mem_q.0.3_WDATA_3 -.sym 7104 rx_fifo.mem_q.0.3_WDATA_2 +.sym 7097 lvds_clock_$glb_clk +.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 7100 rx_fifo.mem_i.0.1_WDATA_3 +.sym 7104 rx_fifo.mem_i.0.1_WDATA_2 .sym 7107 $PACKER_VCC_NET -.sym 7109 $PACKER_VCC_NET -.sym 7114 $PACKER_VCC_NET -.sym 7115 rx_fifo.rd_addr[5] -.sym 7117 $PACKER_VCC_NET -.sym 7119 rx_fifo.wr_addr[7] -.sym 7121 $PACKER_VCC_NET -.sym 7123 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7124 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7125 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 7126 rx_fifo.wr_addr[4] -.sym 7128 rx_fifo.wr_addr[3] -.sym 7129 rx_fifo.rd_addr_gray_wr_r[8] -.sym 7131 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 7132 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 7134 rx_fifo.wr_addr[0] -.sym 7144 rx_fifo.rd_addr[6] -.sym 7145 rx_fifo.rd_addr[0] -.sym 7146 rx_fifo.rd_addr[4] -.sym 7148 rx_fifo.rd_addr[7] -.sym 7151 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 7152 rx_fifo.rd_addr[3] -.sym 7153 rx_fifo.rd_addr[2] -.sym 7154 rx_fifo.rd_addr[5] -.sym 7155 rx_fifo.rd_addr[1] -.sym 7159 rx_fifo.rd_addr[9] -.sym 7162 rx_fifo.mem_q.0.3_WDATA_1 -.sym 7165 rx_fifo.rd_addr[8] -.sym 7167 rx_fifo.mem_q.0.3_WDATA +.sym 7112 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 7114 w_rx_fifo_pulled_data[22] +.sym 7115 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 7117 rx_fifo.rd_addr[0] +.sym 7119 w_rx_09_fifo_data[28] +.sym 7123 rx_fifo.rd_addr[6] +.sym 7124 rx_fifo.rd_addr[6] +.sym 7127 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 7128 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 7130 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 7134 w_rx_fifo_pulled_data[3] +.sym 7135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7140 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 7142 rx_fifo.rd_addr[6] +.sym 7144 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 7147 rx_fifo.rd_addr[0] +.sym 7148 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 7151 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 7152 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 7154 rx_fifo.rd_addr[3] +.sym 7156 rx_fifo.rd_addr[8] +.sym 7158 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7160 rx_fifo.mem_i.0.1_WDATA +.sym 7161 rx_fifo.rd_addr[9] +.sym 7162 rx_fifo.mem_i.0.1_WDATA_1 .sym 7169 $PACKER_VCC_NET -.sym 7172 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 7173 rx_fifo.rd_addr[8] -.sym 7174 rx_fifo.wr_addr[6] -.sym 7175 rx_fifo.wr_addr[8] -.sym 7176 rx_fifo.wr_addr_gray[2] -.sym 7177 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 7178 rx_fifo.wr_addr_gray[4] -.sym 7179 rx_fifo.wr_addr[4] -.sym 7188 rx_fifo.rd_addr[2] +.sym 7172 rx_fifo.rd_addr[8] +.sym 7173 rx_fifo.rd_addr_gray[6] +.sym 7174 rx_fifo.rd_addr_gray[8] +.sym 7175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] +.sym 7176 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.sym 7177 rx_fifo.rd_addr[9] +.sym 7178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] +.sym 7179 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] +.sym 7188 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 7189 rx_fifo.rd_addr[3] -.sym 7191 rx_fifo.rd_addr[4] -.sym 7192 rx_fifo.rd_addr[5] +.sym 7191 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 7192 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 7193 rx_fifo.rd_addr[6] -.sym 7194 rx_fifo.rd_addr[7] +.sym 7194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 7195 rx_fifo.rd_addr[8] .sym 7196 rx_fifo.rd_addr[9] -.sym 7197 rx_fifo.rd_addr[1] +.sym 7197 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 7198 rx_fifo.rd_addr[0] .sym 7199 r_counter_$glb_clk -.sym 7200 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 7201 $PACKER_VCC_NET -.sym 7205 rx_fifo.mem_q.0.3_WDATA -.sym 7209 rx_fifo.mem_q.0.3_WDATA_1 -.sym 7216 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 7218 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 7226 rx_fifo.rd_addr_gray_wr_r[6] -.sym 7227 rx_fifo.wr_addr[9] -.sym 7228 rx_fifo.rd_addr_gray_wr_r[7] -.sym 7230 $PACKER_VCC_NET -.sym 7231 rx_fifo.wr_addr[1] -.sym 7232 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7233 rx_fifo.rd_addr[4] -.sym 7235 $PACKER_VCC_NET -.sym 7236 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 7237 rx_fifo.wr_addr[1] -.sym 7246 rx_fifo.wr_addr[1] -.sym 7247 rx_fifo.wr_addr[5] -.sym 7250 rx_fifo.wr_addr[9] -.sym 7251 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7253 rx_fifo.wr_addr[8] -.sym 7255 $PACKER_VCC_NET -.sym 7257 rx_fifo.mem_q.0.2_WDATA_2 -.sym 7260 rx_fifo.wr_addr[6] -.sym 7261 rx_fifo.wr_addr[7] -.sym 7262 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7266 rx_fifo.wr_addr[3] -.sym 7269 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7272 rx_fifo.wr_addr[0] -.sym 7273 rx_fifo.wr_addr[4] -.sym 7274 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 7275 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 7276 rx_fifo.rd_addr_gray_wr_r[8] -.sym 7277 rx_fifo.rd_addr_gray_wr[7] -.sym 7278 rx_fifo.rd_addr_gray_wr[6] -.sym 7279 rx_fifo.rd_addr_gray_wr[0] -.sym 7280 rx_fifo.rd_addr_gray_wr_r[6] -.sym 7281 rx_fifo.rd_addr_gray_wr_r[7] -.sym 7290 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 7205 rx_fifo.mem_i.0.1_WDATA +.sym 7209 rx_fifo.mem_i.0.1_WDATA_1 +.sym 7210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 7215 rx_fifo.wr_addr[4] +.sym 7216 w_rx_fifo_pulled_data[23] +.sym 7220 rx_fifo.wr_addr[0] +.sym 7222 rx_fifo.mem_i.0.3_WDATA_1 +.sym 7227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 7228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 7229 rx_fifo.rd_addr[9] +.sym 7231 rx_fifo.rd_addr_gray[3] +.sym 7233 w_rx_fifo_pulled_data[1] +.sym 7236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 7244 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 7246 rx_fifo.wr_addr[2] +.sym 7249 rx_fifo.wr_addr[0] +.sym 7251 rx_fifo.wr_addr[8] +.sym 7253 rx_fifo.wr_addr[4] +.sym 7255 rx_fifo.wr_addr[6] +.sym 7257 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7258 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7259 rx_fifo.wr_addr[3] +.sym 7262 $PACKER_VCC_NET +.sym 7263 rx_fifo.wr_addr[9] +.sym 7266 rx_fifo.wr_addr[5] +.sym 7268 rx_fifo.wr_addr[7] +.sym 7271 rx_fifo.wr_addr[1] +.sym 7274 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 7275 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] +.sym 7276 rx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 7277 rx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 7278 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] +.sym 7279 rx_fifo.rd_addr_gray_wr[6] +.sym 7280 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +.sym 7281 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] +.sym 7290 rx_fifo.wr_addr[2] .sym 7291 rx_fifo.wr_addr[3] .sym 7293 rx_fifo.wr_addr[4] .sym 7294 rx_fifo.wr_addr[5] @@ -6315,4093 +6514,3807 @@ .sym 7298 rx_fifo.wr_addr[9] .sym 7299 rx_fifo.wr_addr[1] .sym 7300 rx_fifo.wr_addr[0] -.sym 7301 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7302 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7304 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7308 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7301 lvds_clock_$glb_clk +.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 7304 rx_fifo.mem_q.0.0_WDATA_3 +.sym 7308 rx_fifo.mem_q.0.0_WDATA_2 .sym 7311 $PACKER_VCC_NET -.sym 7316 rx_fifo.rd_addr[5] -.sym 7319 rx_fifo.wr_addr[8] -.sym 7321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 7324 rx_fifo.rd_addr[4] -.sym 7327 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 7328 rx_fifo.wr_addr[6] -.sym 7329 w_rx_09_fifo_data[2] -.sym 7330 rx_fifo.wr_addr[8] -.sym 7335 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 7337 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7338 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 7339 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7344 rx_fifo.mem_q.0.2_WDATA -.sym 7345 rx_fifo.rd_addr[7] -.sym 7346 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 7348 rx_fifo.rd_addr[6] -.sym 7349 rx_fifo.rd_addr[3] -.sym 7350 rx_fifo.rd_addr[8] -.sym 7352 rx_fifo.rd_addr[5] -.sym 7354 rx_fifo.rd_addr[9] -.sym 7355 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7359 rx_fifo.rd_addr[1] -.sym 7365 rx_fifo.rd_addr[0] -.sym 7366 rx_fifo.rd_addr[2] -.sym 7371 rx_fifo.rd_addr[4] -.sym 7373 $PACKER_VCC_NET -.sym 7376 rx_fifo.wr_addr[9] -.sym 7377 rx_fifo.wr_addr_gray[3] -.sym 7378 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 7379 rx_fifo.wr_addr_gray[8] -.sym 7380 rx_fifo.wr_addr_gray[1] -.sym 7381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 7382 rx_fifo.wr_addr_gray[6] -.sym 7383 rx_fifo.wr_addr_gray[7] -.sym 7392 rx_fifo.rd_addr[2] +.sym 7316 rx_fifo.wr_addr_gray[3] +.sym 7320 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 7323 rx_fifo.rd_addr[8] +.sym 7327 i_rst_b$SB_IO_IN +.sym 7330 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 7331 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 7334 rx_fifo.rd_addr[9] +.sym 7335 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 7336 rx_fifo.rd_addr_gray_wr_r[9] +.sym 7338 rx_fifo.rd_addr[3] +.sym 7344 rx_fifo.rd_addr[8] +.sym 7346 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 7348 rx_fifo.mem_q.0.0_WDATA +.sym 7349 rx_fifo.rd_addr[9] +.sym 7353 rx_fifo.rd_addr[6] +.sym 7355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 7357 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7358 rx_fifo.rd_addr[0] +.sym 7359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 7362 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7363 rx_fifo.rd_addr[3] +.sym 7364 $PACKER_VCC_NET +.sym 7365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 7374 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 7376 rx_fifo.rd_addr_gray_wr[8] +.sym 7377 rx_fifo.rd_addr_gray_wr_r[8] +.sym 7378 rx_fifo.rd_addr_gray_wr_r[9] +.sym 7379 rx_fifo.rd_addr_gray_wr[2] +.sym 7380 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 7381 rx_fifo.rd_addr_gray_wr[9] +.sym 7382 rx_fifo.rd_addr_gray_wr_r[5] +.sym 7383 rx_fifo.rd_addr_gray_wr[5] +.sym 7392 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 7393 rx_fifo.rd_addr[3] -.sym 7395 rx_fifo.rd_addr[4] -.sym 7396 rx_fifo.rd_addr[5] +.sym 7395 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 7396 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 7397 rx_fifo.rd_addr[6] -.sym 7398 rx_fifo.rd_addr[7] +.sym 7398 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 7399 rx_fifo.rd_addr[8] .sym 7400 rx_fifo.rd_addr[9] -.sym 7401 rx_fifo.rd_addr[1] +.sym 7401 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 7402 rx_fifo.rd_addr[0] .sym 7403 r_counter_$glb_clk -.sym 7404 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 7405 $PACKER_VCC_NET -.sym 7409 rx_fifo.mem_q.0.2_WDATA -.sym 7413 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7420 rx_fifo.rd_addr[9] -.sym 7421 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 7422 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 7424 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 7425 i_rst_b$SB_IO_IN -.sym 7426 rx_fifo.rd_addr[8] -.sym 7429 rx_fifo.rd_addr_gray_wr_r[8] -.sym 7433 rx_fifo.rd_addr_gray_wr[8] -.sym 7435 i_rst_b$SB_IO_IN -.sym 7447 rx_fifo.wr_addr[0] -.sym 7448 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7449 rx_fifo.wr_addr[7] -.sym 7450 $PACKER_VCC_NET -.sym 7455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7458 rx_fifo.wr_addr[3] -.sym 7459 rx_fifo.mem_q.0.0_WDATA_2 -.sym 7464 rx_fifo.wr_addr[1] -.sym 7466 rx_fifo.wr_addr[6] -.sym 7468 rx_fifo.wr_addr[8] -.sym 7470 rx_fifo.wr_addr[9] -.sym 7473 rx_fifo.wr_addr[4] -.sym 7476 rx_fifo.wr_addr[5] -.sym 7478 w_rx_09_fifo_data[2] -.sym 7494 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 7495 rx_fifo.wr_addr[3] -.sym 7497 rx_fifo.wr_addr[4] -.sym 7498 rx_fifo.wr_addr[5] -.sym 7499 rx_fifo.wr_addr[6] -.sym 7500 rx_fifo.wr_addr[7] -.sym 7501 rx_fifo.wr_addr[8] -.sym 7502 rx_fifo.wr_addr[9] -.sym 7503 rx_fifo.wr_addr[1] -.sym 7504 rx_fifo.wr_addr[0] -.sym 7505 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 7506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 7508 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7512 rx_fifo.mem_q.0.0_WDATA_2 -.sym 7515 $PACKER_VCC_NET -.sym 7539 rx_fifo.wr_addr[4] -.sym 7549 rx_fifo.rd_addr[9] -.sym 7550 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 7551 rx_fifo.rd_addr[5] -.sym 7552 rx_fifo.rd_addr[6] -.sym 7553 rx_fifo.rd_addr[0] -.sym 7554 rx_fifo.rd_addr[1] -.sym 7557 rx_fifo.mem_q.0.0_WDATA -.sym 7558 rx_fifo.rd_addr[3] -.sym 7559 rx_fifo.rd_addr[2] -.sym 7560 rx_fifo.rd_addr[7] -.sym 7561 rx_fifo.rd_addr[4] -.sym 7564 rx_fifo.rd_addr[8] -.sym 7570 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7577 $PACKER_VCC_NET -.sym 7596 rx_fifo.rd_addr[2] -.sym 7597 rx_fifo.rd_addr[3] -.sym 7599 rx_fifo.rd_addr[4] -.sym 7600 rx_fifo.rd_addr[5] -.sym 7601 rx_fifo.rd_addr[6] -.sym 7602 rx_fifo.rd_addr[7] -.sym 7603 rx_fifo.rd_addr[8] -.sym 7604 rx_fifo.rd_addr[9] -.sym 7605 rx_fifo.rd_addr[1] -.sym 7606 rx_fifo.rd_addr[0] -.sym 7607 r_counter_$glb_clk -.sym 7608 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 7609 $PACKER_VCC_NET -.sym 7613 rx_fifo.mem_q.0.0_WDATA -.sym 7617 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7746 o_shdn_rx_lna$SB_IO_OUT -.sym 7838 i_rst_b$SB_IO_IN +.sym 7409 rx_fifo.mem_q.0.0_WDATA +.sym 7413 rx_fifo.mem_q.0.0_WDATA_1 +.sym 7415 w_ioc[1] +.sym 7422 i_rst_b$SB_IO_IN +.sym 7430 $PACKER_VCC_NET +.sym 7431 w_lvds_rx_24_d0 +.sym 7433 w_lvds_rx_24_d1 +.sym 7437 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 7441 $PACKER_VCC_NET +.sym 7479 w_rx_24_fifo_data[1] +.sym 7480 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 7481 w_rx_24_fifo_data[0] +.sym 7528 i_rst_b$SB_IO_IN +.sym 7531 rx_fifo.rd_addr_gray_wr_r[9] +.sym 7532 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 7535 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 7541 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 7542 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 7543 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7580 rx_fifo.wr_addr_gray[5] +.sym 7581 rx_fifo.wr_addr_gray[4] +.sym 7582 rx_fifo.wr_addr_gray[6] +.sym 7583 rx_fifo.wr_addr_gray[2] +.sym 7584 rx_fifo.wr_addr_gray[1] +.sym 7585 rx_fifo.wr_addr_gray[8] +.sym 7587 rx_fifo.wr_addr_gray[0] +.sym 7624 rx_fifo.rd_addr_gray_wr_r[0] +.sym 7625 w_rx_24_fifo_data[0] +.sym 7626 rx_fifo.rd_addr_gray_wr_r[1] +.sym 7627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 7629 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 7633 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 7636 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 7639 rx_fifo.rd_addr_gray[3] +.sym 7641 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 7682 rx_fifo.wr_addr_gray_rd[7] +.sym 7683 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 7684 rx_fifo.wr_addr_gray_rd[4] +.sym 7686 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 7688 rx_fifo.wr_addr_gray_rd[6] +.sym 7689 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 7724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 7730 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 7732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 7787 rx_fifo.rd_addr_gray_wr[3] +.sym 7789 rx_fifo.rd_addr_gray_wr_r[3] +.sym 7830 rx_fifo.wr_addr_gray[7] +.sym 8043 o_shdn_rx_lna$SB_IO_OUT .sym 8093 w_smi_data_output[6] .sym 8095 w_smi_data_direction .sym 8099 $PACKER_VCC_NET -.sym 8104 w_smi_data_output[6] -.sym 8114 w_smi_data_direction -.sym 8115 $PACKER_VCC_NET -.sym 8119 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 8121 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 8122 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 8123 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 8125 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 8133 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 8134 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8139 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8141 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8246 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 8247 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 8248 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 8250 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 8251 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 8252 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 8253 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8255 tx_fifo.wr_addr[5] -.sym 8261 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 8265 w_rx_fifo_pulled_data[22] -.sym 8277 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 8289 $PACKER_VCC_NET -.sym 8290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8292 smi_ctrl_ins.int_cnt_rx[3] -.sym 8297 w_smi_data_output[1] -.sym 8298 w_rx_fifo_pulled_data[28] -.sym 8299 w_smi_data_output[2] -.sym 8306 rx_fifo.mem_i.0.3_WDATA -.sym 8310 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 8324 w_rx_24_fifo_data[23] -.sym 8325 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 8335 w_rx_24_fifo_data[21] -.sym 8336 w_rx_09_fifo_data[23] -.sym 8337 w_rx_09_fifo_data[27] -.sym 8338 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8343 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8344 w_rx_09_fifo_data[21] -.sym 8351 w_rx_24_fifo_data[27] -.sym 8352 w_rx_09_fifo_data[25] -.sym 8353 w_rx_24_fifo_data[25] -.sym 8356 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8357 w_rx_09_fifo_data[21] -.sym 8359 w_rx_24_fifo_data[21] -.sym 8363 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8364 w_rx_24_fifo_data[21] -.sym 8368 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8369 w_rx_24_fifo_data[23] -.sym 8370 w_rx_09_fifo_data[23] -.sym 8374 w_rx_24_fifo_data[25] -.sym 8375 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8377 w_rx_09_fifo_data[25] -.sym 8380 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8383 w_rx_24_fifo_data[25] -.sym 8386 w_rx_09_fifo_data[27] -.sym 8387 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8388 w_rx_24_fifo_data[27] -.sym 8393 w_rx_24_fifo_data[23] -.sym 8394 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8398 w_rx_24_fifo_data[27] -.sym 8399 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8402 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 8403 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8404 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 8405 rx_fifo.rd_addr[3] -.sym 8406 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 8407 rx_fifo.rd_addr_gray[1] -.sym 8408 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 8409 rx_fifo.rd_addr_gray[4] -.sym 8410 rx_fifo.rd_addr_gray[2] -.sym 8411 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 8416 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 8417 rx_fifo.mem_i.0.1_WDATA_1 -.sym 8425 w_rx_09_fifo_data[27] -.sym 8431 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 8435 i_rst_b$SB_IO_IN -.sym 8436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 8439 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8440 rx_fifo.wr_addr[8] -.sym 8454 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8455 w_rx_24_fifo_data[28] -.sym 8456 w_rx_09_fifo_data[30] -.sym 8460 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8461 w_rx_24_fifo_data[29] -.sym 8464 w_rx_24_fifo_data[30] -.sym 8465 w_rx_24_fifo_data[26] -.sym 8467 w_rx_09_fifo_data[28] -.sym 8469 w_rx_24_fifo_data[19] -.sym 8472 w_rx_09_fifo_data[29] -.sym 8473 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 8475 w_rx_09_fifo_data[31] -.sym 8476 w_rx_24_fifo_data[31] -.sym 8480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8481 w_rx_09_fifo_data[31] -.sym 8482 w_rx_24_fifo_data[31] -.sym 8485 w_rx_24_fifo_data[26] -.sym 8487 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8492 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8493 w_rx_24_fifo_data[28] -.sym 8497 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8498 w_rx_24_fifo_data[28] -.sym 8499 w_rx_09_fifo_data[28] -.sym 8504 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8506 w_rx_24_fifo_data[19] -.sym 8509 w_rx_09_fifo_data[29] -.sym 8511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8512 w_rx_24_fifo_data[29] -.sym 8516 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 8517 w_rx_24_fifo_data[29] -.sym 8521 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8522 w_rx_24_fifo_data[30] -.sym 8523 w_rx_09_fifo_data[30] -.sym 8525 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 8526 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 8527 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 8528 w_smi_data_output[4] -.sym 8529 w_smi_data_output[7] -.sym 8530 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 8531 w_smi_data_output[5] -.sym 8532 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 8533 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 8534 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 8535 smi_ctrl_ins.w_fifo_pull_trigger -.sym 8540 rx_fifo.wr_addr[7] -.sym 8542 rx_fifo.wr_addr[1] -.sym 8543 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 8545 smi_ctrl_ins.int_cnt_rx[4] -.sym 8547 smi_ctrl_ins.int_cnt_rx[3] -.sym 8548 rx_fifo.mem_i.0.3_WDATA_3 -.sym 8554 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 8556 rx_fifo.rd_addr_gray[6] -.sym 8560 rx_fifo.rd_addr[7] -.sym 8562 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 8573 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 8575 smi_ctrl_ins.int_cnt_rx[4] -.sym 8580 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8583 smi_ctrl_ins.int_cnt_rx[4] -.sym 8584 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 8588 w_rx_fifo_pulled_data[7] -.sym 8591 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8593 smi_ctrl_ins.int_cnt_rx[3] -.sym 8594 w_rx_fifo_pulled_data[4] -.sym 8596 w_rx_fifo_pulled_data[5] -.sym 8599 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8600 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 8608 smi_ctrl_ins.int_cnt_rx[3] -.sym 8609 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8610 smi_ctrl_ins.int_cnt_rx[4] -.sym 8611 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 8623 w_rx_fifo_pulled_data[5] -.sym 8626 smi_ctrl_ins.int_cnt_rx[4] -.sym 8627 smi_ctrl_ins.int_cnt_rx[3] -.sym 8628 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8629 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8632 smi_ctrl_ins.int_cnt_rx[4] -.sym 8633 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 8634 smi_ctrl_ins.int_cnt_rx[3] -.sym 8635 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 8639 w_rx_fifo_pulled_data[7] -.sym 8645 w_rx_fifo_pulled_data[4] -.sym 8648 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8651 rx_fifo.rd_addr_gray[6] -.sym 8652 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 8653 rx_fifo.rd_addr[7] -.sym 8654 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 8655 rx_fifo.rd_addr[0] -.sym 8656 rx_fifo.rd_addr[2] -.sym 8657 rx_fifo.rd_addr_gray[3] -.sym 8658 rx_fifo.rd_addr[1] -.sym 8662 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 8664 $PACKER_VCC_NET -.sym 8665 smi_ctrl_ins.int_cnt_rx[4] -.sym 8667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 8672 $PACKER_VCC_NET -.sym 8673 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 8675 rx_fifo.wr_addr[9] -.sym 8676 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 8677 rx_fifo.wr_addr[5] -.sym 8679 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 8682 smi_ctrl_ins.int_cnt_rx[3] -.sym 8683 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 8684 rx_fifo.rd_addr_gray_wr_r[6] -.sym 8685 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 8701 rx_fifo.wr_addr[6] -.sym 8703 rx_fifo.wr_addr[4] -.sym 8708 rx_fifo.wr_addr[0] -.sym 8710 rx_fifo.wr_addr[1] -.sym 8711 rx_fifo.wr_addr[3] -.sym 8712 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 8716 rx_fifo.wr_addr[7] -.sym 8723 rx_fifo.wr_addr[5] -.sym 8724 $nextpnr_ICESTORM_LC_7$O -.sym 8727 rx_fifo.wr_addr[0] -.sym 8730 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 8732 rx_fifo.wr_addr[1] -.sym 8734 rx_fifo.wr_addr[0] -.sym 8736 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 8739 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 8740 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 8742 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 8745 rx_fifo.wr_addr[3] -.sym 8746 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 8748 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 8751 rx_fifo.wr_addr[4] -.sym 8752 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 8754 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 8756 rx_fifo.wr_addr[5] -.sym 8758 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 8760 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 8763 rx_fifo.wr_addr[6] -.sym 8764 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 8766 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 8769 rx_fifo.wr_addr[7] -.sym 8770 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 8774 rx_fifo.wr_addr[0] -.sym 8775 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] -.sym 8776 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 8777 rx_fifo.wr_addr[3] -.sym 8778 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 8779 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 8780 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 8781 rx_fifo.wr_addr[5] -.sym 8790 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 8794 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8797 rx_fifo.wr_addr[6] -.sym 8799 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 8800 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 8801 rx_fifo.rd_addr[8] -.sym 8804 rx_fifo.rd_addr[2] -.sym 8805 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 8806 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 8808 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 8809 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 8810 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 8817 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 8818 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8819 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8820 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 8821 rx_fifo.wr_addr_gray[0] -.sym 8827 rx_fifo.wr_addr_gray[5] -.sym 8828 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8829 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8830 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8834 rx_fifo.wr_addr[8] -.sym 8835 rx_fifo.wr_addr[9] -.sym 8844 rx_fifo.rd_addr_gray_wr_r[6] -.sym 8846 rx_fifo.wr_addr_gray_rd[5] -.sym 8847 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 8849 rx_fifo.wr_addr[8] -.sym 8851 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 8855 rx_fifo.wr_addr[9] -.sym 8857 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 8861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 8862 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 8863 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8869 rx_fifo.wr_addr_gray[0] -.sym 8872 rx_fifo.rd_addr_gray_wr_r[6] -.sym 8873 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8874 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8881 rx_fifo.wr_addr_gray_rd[5] -.sym 8884 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8886 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8890 rx_fifo.wr_addr_gray[5] -.sym 8895 r_counter_$glb_clk -.sym 8898 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 8899 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 8900 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 8901 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 8902 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 8903 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 8904 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 8909 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 8912 rx_fifo.wr_addr[3] -.sym 8913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8916 rx_fifo.wr_addr[0] -.sym 8922 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 8923 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 8925 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 8926 i_rst_b$SB_IO_IN -.sym 8927 rx_fifo.wr_addr[8] -.sym 8929 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 8930 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 8931 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 8939 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 8940 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 8942 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 8944 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 8945 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 8946 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 8948 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 8950 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 8951 rx_fifo.wr_addr[1] -.sym 8952 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8955 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 8957 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 8963 rx_fifo.rd_addr_gray_wr_r[8] -.sym 8964 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 8965 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 8974 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8977 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 8978 rx_fifo.rd_addr_gray_wr_r[8] -.sym 8979 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 8980 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 8986 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 8989 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 8990 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 8991 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 8992 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 8998 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9003 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 9009 rx_fifo.wr_addr[1] -.sym 9013 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9015 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 9017 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9018 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 8110 w_smi_data_direction +.sym 8112 $PACKER_VCC_NET +.sym 8117 w_smi_data_output[6] +.sym 8118 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 8119 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 8120 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 8121 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] +.sym 8122 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 8123 tx_fifo.rd_addr[0] +.sym 8124 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 8125 tx_fifo.rd_addr[2] +.sym 8150 w_smi_data_direction +.sym 8153 w_smi_data_output[1] +.sym 8247 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 8248 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8249 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 8250 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 8251 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 8252 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 8253 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 8260 $PACKER_VCC_NET +.sym 8263 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8265 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 8272 $PACKER_VCC_NET +.sym 8276 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8290 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8296 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 8298 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 8302 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 8309 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 8312 tx_fifo.rd_addr[9] +.sym 8325 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 8326 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] +.sym 8329 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 8332 w_rx_fifo_pulled_data[13] +.sym 8336 w_rx_fifo_pulled_data[15] +.sym 8340 w_rx_fifo_pulled_data[12] +.sym 8342 w_rx_fifo_pulled_data[11] +.sym 8344 w_rx_fifo_pulled_data[14] +.sym 8348 w_rx_fifo_pulled_data[8] +.sym 8350 w_rx_fifo_pulled_data[9] +.sym 8353 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 8359 w_rx_fifo_pulled_data[14] +.sym 8362 w_rx_fifo_pulled_data[12] +.sym 8368 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 8369 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] +.sym 8370 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 8371 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 8375 w_rx_fifo_pulled_data[13] +.sym 8380 w_rx_fifo_pulled_data[9] +.sym 8387 w_rx_fifo_pulled_data[8] +.sym 8393 w_rx_fifo_pulled_data[11] +.sym 8401 w_rx_fifo_pulled_data[15] +.sym 8402 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 8403 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8407 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 8408 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 8409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 8410 tx_fifo.rd_addr_gray_wr[2] +.sym 8411 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 8412 tx_fifo.rd_addr_gray_wr[4] +.sym 8415 rx_fifo.rd_addr[9] +.sym 8432 tx_fifo.rd_addr_gray_wr_r[1] +.sym 8438 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 8439 tx_fifo.rd_addr[1] +.sym 8448 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 8452 w_tx_fifo_pull +.sym 8453 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 8455 i_rst_b$SB_IO_IN +.sym 8457 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8462 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 8464 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 8468 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 8472 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 8479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 8486 i_rst_b$SB_IO_IN +.sym 8488 w_tx_fifo_pull +.sym 8491 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 8493 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 8506 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 8510 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 8518 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 8525 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8526 lvds_clock_$glb_clk +.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8528 tx_fifo.rd_addr_gray[8] +.sym 8529 tx_fifo.rd_addr_gray[0] +.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 8531 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 8533 tx_fifo.rd_addr[9] +.sym 8534 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 8535 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8540 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 8544 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8545 tx_fifo.rd_addr_gray_wr[4] +.sym 8557 smi_ctrl_ins.int_cnt_rx[4] +.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 8563 smi_ctrl_ins.int_cnt_rx[3] +.sym 8569 tx_fifo.rd_addr_gray[1] +.sym 8573 tx_fifo.rd_addr_gray_wr[8] +.sym 8586 tx_fifo.rd_addr_gray[0] +.sym 8587 tx_fifo.rd_addr_gray_wr[9] +.sym 8591 tx_fifo.rd_addr_gray_wr[1] +.sym 8593 tx_fifo.rd_addr_gray[8] +.sym 8596 tx_fifo.rd_addr_gray_wr[0] +.sym 8598 tx_fifo.rd_addr[9] +.sym 8604 tx_fifo.rd_addr_gray_wr[8] +.sym 8609 tx_fifo.rd_addr_gray_wr[0] +.sym 8616 tx_fifo.rd_addr[9] +.sym 8620 tx_fifo.rd_addr_gray[0] +.sym 8627 tx_fifo.rd_addr_gray[8] +.sym 8635 tx_fifo.rd_addr_gray_wr[9] +.sym 8640 tx_fifo.rd_addr_gray[1] +.sym 8647 tx_fifo.rd_addr_gray_wr[1] +.sym 8649 r_counter_$glb_clk +.sym 8651 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 8652 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 8653 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 8654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 8655 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 8656 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 8657 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 8658 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 8663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 8665 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 8667 tx_fifo.rd_addr_gray_wr_r[0] +.sym 8668 rx_fifo.rd_addr[9] +.sym 8669 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8671 w_smi_data_output[1] +.sym 8672 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 8677 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 8682 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 8686 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 8693 w_rx_24_fifo_data[24] +.sym 8696 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 8697 w_rx_fifo_pulled_data[26] +.sym 8698 w_rx_09_fifo_data[24] +.sym 8701 w_rx_fifo_pulled_data[24] +.sym 8703 w_rx_fifo_pulled_data[10] +.sym 8705 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 8709 w_rx_fifo_pulled_data[25] +.sym 8710 smi_ctrl_ins.int_cnt_rx[4] +.sym 8713 smi_ctrl_ins.int_cnt_rx[3] +.sym 8715 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 8716 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 8721 w_rx_fifo_pulled_data[27] +.sym 8723 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 8725 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 8726 smi_ctrl_ins.int_cnt_rx[3] +.sym 8727 smi_ctrl_ins.int_cnt_rx[4] +.sym 8728 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 8732 w_rx_fifo_pulled_data[27] +.sym 8740 w_rx_fifo_pulled_data[25] +.sym 8743 w_rx_24_fifo_data[24] +.sym 8744 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 8746 w_rx_09_fifo_data[24] +.sym 8749 w_rx_fifo_pulled_data[10] +.sym 8758 w_rx_fifo_pulled_data[24] +.sym 8764 w_rx_fifo_pulled_data[26] +.sym 8767 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 8768 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 8769 smi_ctrl_ins.int_cnt_rx[3] +.sym 8770 smi_ctrl_ins.int_cnt_rx[4] +.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8776 smi_ctrl_ins.int_cnt_rx[4] +.sym 8779 smi_ctrl_ins.int_cnt_rx[3] +.sym 8786 io_pmod[0]$SB_IO_IN +.sym 8787 $PACKER_VCC_NET +.sym 8790 w_rx_fifo_pulled_data[6] +.sym 8792 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 8798 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 8801 rx_fifo.rd_addr[0] +.sym 8802 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 8803 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 8806 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 8807 rx_fifo.rd_addr[6] +.sym 8808 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 8809 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 8828 w_rx_24_fifo_data[26] +.sym 8832 w_rx_24_fifo_data[24] +.sym 8837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 8842 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8843 w_rx_24_fifo_data[22] +.sym 8854 w_rx_24_fifo_data[22] +.sym 8855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 8878 w_rx_24_fifo_data[24] +.sym 8879 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 8884 w_rx_24_fifo_data[26] +.sym 8886 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 8894 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 8895 lvds_clock_$glb_clk +.sym 8896 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 8898 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 8899 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 8911 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 8913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 8920 smi_ctrl_ins.int_cnt_rx[4] +.sym 8943 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 8944 w_rx_24_fifo_data[28] +.sym 8946 w_rx_09_fifo_data[28] +.sym 8949 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 8955 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 8956 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 8959 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 8961 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 8965 rx_fifo.rd_addr[3] +.sym 8968 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 8969 rx_fifo.rd_addr[0] +.sym 8972 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 8977 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 8978 w_rx_24_fifo_data[28] +.sym 8979 w_rx_09_fifo_data[28] +.sym 8984 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 8989 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 8996 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 9002 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 9009 rx_fifo.rd_addr[3] +.sym 9014 rx_fifo.rd_addr[0] +.sym 9017 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9018 r_counter_$glb_clk .sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9020 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 9021 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] -.sym 9022 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 9023 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 9024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] -.sym 9025 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 9026 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 9027 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] -.sym 9032 rx_fifo.rd_addr[4] -.sym 9034 rx_fifo.wr_addr[1] -.sym 9036 $PACKER_VCC_NET -.sym 9039 $PACKER_VCC_NET -.sym 9045 rx_fifo.rd_addr[7] -.sym 9046 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 9047 rx_fifo.wr_addr[4] -.sym 9048 rx_fifo.rd_addr_gray[6] -.sym 9052 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9053 rx_fifo.wr_addr[6] -.sym 9054 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 9062 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9063 i_rst_b$SB_IO_IN -.sym 9064 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9065 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9066 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 9067 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 9068 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 9069 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9070 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 9072 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 9074 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 9075 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 9076 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 9077 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 9078 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 9081 rx_fifo.rd_addr_gray_wr_r[6] -.sym 9082 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 9083 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9086 w_rx_fifo_pulled_data[12] -.sym 9089 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 9091 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 9095 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 9096 i_rst_b$SB_IO_IN -.sym 9100 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 9101 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 9103 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 9106 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 9107 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 9108 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9109 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 9114 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9115 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9120 w_rx_fifo_pulled_data[12] -.sym 9124 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 9125 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9126 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9127 rx_fifo.rd_addr_gray_wr_r[6] -.sym 9130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 9131 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 9132 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 9133 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 9136 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 9138 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9023 rx_fifo.rd_addr[3] +.sym 9024 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 9026 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 9032 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 9034 rx_fifo.rd_addr_gray[3] +.sym 9036 rx_fifo.mem_i.0.3_WDATA_3 +.sym 9045 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9047 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9048 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 9049 rx_fifo.rd_addr[8] +.sym 9052 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 9054 w_rx_24_fifo_data[1] +.sym 9065 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 9068 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 9070 w_rx_fifo_pulled_data[21] +.sym 9074 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 9075 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 9080 w_rx_fifo_pulled_data[3] +.sym 9082 w_rx_fifo_pulled_data[2] +.sym 9086 w_rx_fifo_pulled_data[0] +.sym 9088 w_rx_fifo_pulled_data[1] +.sym 9095 w_rx_fifo_pulled_data[3] +.sym 9100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 9102 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 9108 w_rx_fifo_pulled_data[1] +.sym 9120 w_rx_fifo_pulled_data[0] +.sym 9126 w_rx_fifo_pulled_data[2] +.sym 9130 w_rx_fifo_pulled_data[21] +.sym 9137 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 9139 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] .sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce .sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9143 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 9144 rx_fifo.wr_addr_gray_rd[4] -.sym 9147 rx_fifo.wr_addr_gray_rd[2] -.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] -.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] -.sym 9150 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 9155 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9157 w_rx_data[5] -.sym 9166 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 9167 rx_fifo.wr_addr[9] -.sym 9168 rx_fifo.rd_addr_gray_wr_r[6] -.sym 9170 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9171 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 9172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 9173 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 9174 rx_fifo.wr_addr[5] -.sym 9188 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9190 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 9192 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9193 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9195 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9196 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 9200 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9207 rx_fifo.rd_addr[8] -.sym 9211 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9212 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9217 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 9219 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9223 rx_fifo.rd_addr[8] -.sym 9230 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9236 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9243 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9244 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9247 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9249 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 9250 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 9255 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9260 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9263 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9264 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 9143 rx_fifo.wr_addr_gray_rd[3] +.sym 9144 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] +.sym 9147 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9149 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] +.sym 9150 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 9156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9158 rx_fifo.rd_addr[3] +.sym 9163 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 9165 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 9166 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9167 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9169 rx_fifo.rd_addr[9] +.sym 9171 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 9175 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9176 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 9178 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 9185 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 9186 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9187 rx_fifo.rd_addr[3] +.sym 9189 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 9190 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9192 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9194 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 9202 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 9206 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 9207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 9213 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9215 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] +.sym 9218 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 9225 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 9229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 9235 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9236 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] +.sym 9237 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9238 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9242 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9243 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 9248 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 9253 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 9254 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 9255 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 9256 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 9259 rx_fifo.rd_addr[3] +.sym 9260 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 9262 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9264 r_counter_$glb_clk .sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9266 rx_fifo.rd_addr_gray[0] -.sym 9267 rx_fifo.rd_addr[9] -.sym 9268 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9269 rx_fifo.rd_addr_gray[7] -.sym 9270 rx_fifo.rd_addr_gray[8] -.sym 9273 rx_fifo.rd_addr[8] -.sym 9280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 9282 rx_fifo.rd_addr_gray_wr[8] -.sym 9285 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 9291 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 9292 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 9297 rx_fifo.rd_addr[8] -.sym 9300 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 9307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 9309 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9312 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 9317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9318 rx_fifo.rd_addr_gray_wr[7] -.sym 9320 rx_fifo.rd_addr_gray[6] -.sym 9321 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9322 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9323 rx_fifo.rd_addr_gray[0] -.sym 9325 rx_fifo.rd_addr_gray_wr_r[8] -.sym 9327 rx_fifo.rd_addr_gray_wr[6] -.sym 9333 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9334 rx_fifo.rd_addr_gray[7] -.sym 9338 rx_fifo.rd_addr_gray_wr[8] -.sym 9340 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9341 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 9342 rx_fifo.rd_addr_gray_wr_r[8] -.sym 9343 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9346 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9347 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 9348 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9349 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9354 rx_fifo.rd_addr_gray_wr[8] -.sym 9361 rx_fifo.rd_addr_gray[7] -.sym 9364 rx_fifo.rd_addr_gray[6] -.sym 9371 rx_fifo.rd_addr_gray[0] -.sym 9376 rx_fifo.rd_addr_gray_wr[6] -.sym 9383 rx_fifo.rd_addr_gray_wr[7] -.sym 9387 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9389 rx_fifo.wr_addr_gray_rd[6] -.sym 9390 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 9391 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 9392 rx_fifo.wr_addr_gray_rd[9] -.sym 9393 rx_fifo.wr_addr_gray_rd[1] -.sym 9394 rx_fifo.wr_addr_gray_rd[3] -.sym 9395 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 9396 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 9413 i_rst_b$SB_IO_IN -.sym 9416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 9421 rx_fifo.wr_addr[9] -.sym 9435 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9436 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9440 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9441 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9445 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9448 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9456 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9457 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9459 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9461 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9472 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9475 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9477 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9482 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9484 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9487 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 9494 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9495 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9505 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9509 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 9510 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9511 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9512 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 9513 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 9517 rx_fifo.wr_addr_gray_rd[8] -.sym 9518 rx_fifo.wr_addr_gray_rd[7] -.sym 9573 w_rx_09_fifo_data[0] -.sym 9581 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 9588 w_rx_09_fifo_data[0] -.sym 9589 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 9632 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 9633 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 9634 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 9635 rx_fifo.rd_addr_gray_wr[4] -.sym 9636 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 9642 rx_fifo.rd_addr_gray_wr[1] -.sym 9649 $PACKER_VCC_NET -.sym 9650 o_shdn_rx_lna$SB_IO_OUT -.sym 9667 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 9773 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 9905 i_rst_b$SB_IO_IN -.sym 10010 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 10155 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 10162 o_shdn_rx_lna$SB_IO_OUT +.sym 9266 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 9268 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 9271 rx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 9272 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 9273 rx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 9280 $PACKER_VCC_NET +.sym 9283 $PACKER_VCC_NET +.sym 9287 $PACKER_VCC_NET +.sym 9291 rx_fifo.rd_addr_gray[8] +.sym 9292 w_rx_24_fifo_data[1] +.sym 9293 w_rx_data[0] +.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 9297 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9299 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9307 rx_fifo.rd_addr[8] +.sym 9308 rx_fifo.rd_addr[6] +.sym 9311 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] +.sym 9312 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 9313 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 9314 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] +.sym 9315 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 9316 rx_fifo.rd_addr_gray[6] +.sym 9317 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9318 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] +.sym 9319 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.sym 9320 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 9322 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 9323 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 9325 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 9327 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9329 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 9332 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] +.sym 9335 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9337 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 9342 rx_fifo.rd_addr[8] +.sym 9346 rx_fifo.rd_addr[6] +.sym 9347 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 9348 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 9349 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 9352 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] +.sym 9354 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] +.sym 9355 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] +.sym 9358 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 9359 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] +.sym 9360 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 9361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 9364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 9365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 9366 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 9367 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +.sym 9373 rx_fifo.rd_addr_gray[6] +.sym 9377 rx_fifo.rd_addr[6] +.sym 9378 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 9382 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.sym 9383 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 9384 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9385 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 9387 lvds_clock_$glb_clk +.sym 9389 rx_fifo.rd_addr_gray[4] +.sym 9393 rx_fifo.rd_addr_gray[1] +.sym 9394 rx_fifo.rd_addr_gray[7] +.sym 9395 rx_fifo.rd_addr_gray[5] +.sym 9396 rx_fifo.rd_addr_gray[2] +.sym 9405 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 9407 w_load +.sym 9408 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9410 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 9411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 9417 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9418 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 9420 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 9421 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 9422 rx_fifo.wr_addr_gray_rd[2] +.sym 9423 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 9424 rx_fifo.wr_addr_gray_rd[5] +.sym 9441 rx_fifo.rd_addr[9] +.sym 9443 rx_fifo.rd_addr_gray_wr[9] +.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 9451 rx_fifo.rd_addr_gray[8] +.sym 9453 rx_fifo.rd_addr_gray_wr[5] +.sym 9454 rx_fifo.rd_addr_gray_wr[8] +.sym 9459 rx_fifo.rd_addr_gray_wr_r[2] +.sym 9460 rx_fifo.rd_addr_gray[5] +.sym 9461 rx_fifo.rd_addr_gray[2] +.sym 9466 rx_fifo.rd_addr_gray[8] +.sym 9469 rx_fifo.rd_addr_gray_wr[8] +.sym 9477 rx_fifo.rd_addr_gray_wr[9] +.sym 9484 rx_fifo.rd_addr_gray[2] +.sym 9487 rx_fifo.rd_addr_gray_wr_r[2] +.sym 9488 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 9490 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 9494 rx_fifo.rd_addr[9] +.sym 9500 rx_fifo.rd_addr_gray_wr[5] +.sym 9505 rx_fifo.rd_addr_gray[5] +.sym 9510 lvds_clock_$glb_clk +.sym 9512 rx_fifo.rd_addr_gray_wr_r[7] +.sym 9513 rx_fifo.rd_addr_gray_wr_r[0] +.sym 9515 rx_fifo.rd_addr_gray_wr[0] +.sym 9516 rx_fifo.rd_addr_gray_wr[1] +.sym 9517 rx_fifo.rd_addr_gray_wr_r[1] +.sym 9519 rx_fifo.rd_addr_gray_wr[7] +.sym 9525 $PACKER_GND_NET +.sym 9530 $PACKER_GND_NET +.sym 9538 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9540 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 9541 rx_fifo.rd_addr_gray[0] +.sym 9543 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 9544 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 9546 w_rx_24_fifo_data[1] +.sym 9547 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9557 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9558 w_lvds_rx_24_d0 +.sym 9561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9562 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9564 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 9565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 9567 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 9568 w_lvds_rx_24_d1 +.sym 9572 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 9592 w_lvds_rx_24_d0 +.sym 9598 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9599 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 9606 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 9607 w_lvds_rx_24_d1 +.sym 9632 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 9633 lvds_clock_$glb_clk +.sym 9635 rx_fifo.wr_addr_gray_rd[8] +.sym 9636 rx_fifo.wr_addr_gray_rd[0] +.sym 9637 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 9638 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 9639 rx_fifo.wr_addr_gray_rd[2] +.sym 9640 rx_fifo.wr_addr_gray_rd[5] +.sym 9642 rx_fifo.wr_addr_gray_rd[1] +.sym 9669 rx_fifo.rd_addr_gray_wr_r[3] +.sym 9679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9681 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9683 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9685 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 9688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9689 rx_fifo.wr_addr[1] +.sym 9693 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 9695 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 9703 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9707 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9712 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9715 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9722 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 9727 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 9729 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 9740 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9741 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 9752 rx_fifo.wr_addr[1] +.sym 9755 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9756 lvds_clock_$glb_clk +.sym 9757 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 9760 rx_fifo.rd_addr_gray[0] +.sym 9801 rx_fifo.wr_addr_gray[6] +.sym 9805 rx_fifo.wr_addr_gray_rd[6] +.sym 9807 rx_fifo.wr_addr_gray_rd[7] +.sym 9808 rx_fifo.wr_addr_gray[4] +.sym 9809 rx_fifo.wr_addr_gray_rd[4] +.sym 9814 rx_fifo.wr_addr_gray[7] +.sym 9834 rx_fifo.wr_addr_gray[7] +.sym 9839 rx_fifo.wr_addr_gray_rd[6] +.sym 9846 rx_fifo.wr_addr_gray[4] +.sym 9859 rx_fifo.wr_addr_gray_rd[4] +.sym 9870 rx_fifo.wr_addr_gray[6] +.sym 9876 rx_fifo.wr_addr_gray_rd[7] +.sym 9879 r_counter_$glb_clk +.sym 9926 rx_fifo.rd_addr_gray[3] +.sym 9949 rx_fifo.rd_addr_gray_wr[3] +.sym 9976 rx_fifo.rd_addr_gray[3] +.sym 9988 rx_fifo.rd_addr_gray_wr[3] +.sym 10002 lvds_clock_$glb_clk +.sym 10004 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10018 o_shdn_rx_lna$SB_IO_OUT .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10196 o_shdn_rx_lna$SB_IO_OUT -.sym 10197 i_rst_b$SB_IO_IN +.sym 10185 o_shdn_rx_lna$SB_IO_OUT .sym 10201 w_smi_data_output[2] .sym 10203 w_smi_data_direction .sym 10204 w_smi_data_output[1] .sym 10206 w_smi_data_direction .sym 10207 $PACKER_VCC_NET -.sym 10210 w_smi_data_direction -.sym 10211 w_smi_data_output[1] .sym 10212 $PACKER_VCC_NET -.sym 10218 w_smi_data_direction -.sym 10221 w_smi_data_output[2] -.sym 10227 tx_fifo.wr_addr_gray_rd[6] -.sym 10228 tx_fifo.wr_addr_gray_rd[2] -.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 10232 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 10233 tx_fifo.wr_addr_gray_rd[5] -.sym 10236 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 10245 w_rx_data[0] -.sym 10248 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 10249 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 10250 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 10258 w_smi_data_direction -.sym 10259 $PACKER_VCC_NET -.sym 10260 w_smi_data_input[7] -.sym 10268 w_rx_fifo_pulled_data[22] -.sym 10269 w_rx_fifo_pulled_data[20] -.sym 10275 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10284 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10289 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 10290 w_rx_fifo_pulled_data[23] -.sym 10292 w_rx_fifo_pulled_data[21] -.sym 10297 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 10309 w_rx_fifo_pulled_data[20] -.sym 10319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10320 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10321 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 10322 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 10325 w_rx_fifo_pulled_data[22] -.sym 10334 w_rx_fifo_pulled_data[23] -.sym 10345 w_rx_fifo_pulled_data[21] -.sym 10347 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 10348 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10214 w_smi_data_direction +.sym 10217 w_smi_data_output[1] +.sym 10222 w_smi_data_direction +.sym 10225 w_smi_data_output[2] +.sym 10226 tx_fifo.rd_addr[1] +.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 10231 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 10233 w_smi_data_output[2] +.sym 10270 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10271 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10272 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10277 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 10278 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 10283 tx_fifo.rd_addr[2] +.sym 10295 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10297 tx_fifo.rd_addr[0] +.sym 10301 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10304 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10308 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 10310 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10313 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10319 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 10320 tx_fifo.rd_addr[2] +.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10334 tx_fifo.rd_addr[0] +.sym 10338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10346 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10348 lvds_clock_$glb_clk .sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 10352 w_smi_data_input[7] -.sym 10354 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10355 tx_fifo.wr_addr_gray_rd[4] -.sym 10356 tx_fifo.wr_addr_gray_rd[3] -.sym 10357 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 10358 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 10359 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 10361 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 10363 w_rx_fifo_pulled_data[20] -.sym 10365 rx_fifo.rd_addr_gray[1] -.sym 10369 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 10371 rx_fifo.wr_addr[8] -.sym 10383 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 10384 w_rx_fifo_pulled_data[23] -.sym 10386 w_rx_fifo_pulled_data[21] -.sym 10389 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 10391 w_rx_fifo_pulled_data[29] -.sym 10392 w_rx_fifo_pulled_data[31] -.sym 10394 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 10396 rx_fifo.rd_addr[3] -.sym 10402 w_rx_fifo_pulled_data[30] -.sym 10403 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 10404 w_smi_data_output[0] -.sym 10407 smi_ctrl_ins.int_cnt_rx[4] -.sym 10408 tx_fifo.wr_addr_gray_rd[2] -.sym 10410 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10414 rx_fifo.rd_addr[3] -.sym 10419 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10423 w_smi_data_direction -.sym 10425 w_smi_data_output[7] -.sym 10435 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10437 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10439 smi_ctrl_ins.int_cnt_rx[3] -.sym 10440 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 10444 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10446 w_rx_fifo_pulled_data[28] -.sym 10447 w_rx_fifo_pulled_data[31] -.sym 10448 w_rx_fifo_pulled_data[29] -.sym 10449 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10456 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 10458 w_rx_fifo_pulled_data[30] -.sym 10461 smi_ctrl_ins.int_cnt_rx[4] -.sym 10464 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 10465 smi_ctrl_ins.int_cnt_rx[3] -.sym 10466 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 10467 smi_ctrl_ins.int_cnt_rx[4] -.sym 10473 w_rx_fifo_pulled_data[28] -.sym 10476 w_rx_fifo_pulled_data[30] -.sym 10491 w_rx_fifo_pulled_data[29] -.sym 10494 smi_ctrl_ins.int_cnt_rx[3] -.sym 10495 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10496 smi_ctrl_ins.int_cnt_rx[4] -.sym 10497 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10502 w_rx_fifo_pulled_data[31] -.sym 10506 smi_ctrl_ins.int_cnt_rx[4] -.sym 10507 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10508 smi_ctrl_ins.int_cnt_rx[3] -.sym 10509 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10510 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 10511 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10515 tx_fifo.wr_addr_gray_rd[9] -.sym 10516 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10518 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 10519 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 10520 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 10523 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 10529 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10530 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10536 rx_fifo.rd_addr[7] -.sym 10537 rx_fifo.rd_addr_gray[4] -.sym 10539 rx_fifo.rd_addr_gray[2] -.sym 10544 w_smi_data_output[7] -.sym 10554 smi_ctrl_ins.int_cnt_rx[3] -.sym 10560 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 10565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 10566 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 10568 smi_ctrl_ins.int_cnt_rx[4] -.sym 10569 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 10571 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 10574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 10576 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 10579 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10581 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 10582 i_rst_b$SB_IO_IN -.sym 10589 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 10594 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10596 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 10599 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 10605 i_rst_b$SB_IO_IN -.sym 10606 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 10611 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 10617 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 10623 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 10624 smi_ctrl_ins.int_cnt_rx[4] -.sym 10625 smi_ctrl_ins.int_cnt_rx[3] -.sym 10626 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 10633 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 10354 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 10355 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 10356 tx_fifo.empty_o_SB_LUT4_I1_O[3] +.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 10358 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 10359 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10360 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 10361 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 10368 $PACKER_VCC_NET +.sym 10370 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 10372 $PACKER_VCC_NET +.sym 10373 tx_fifo.rd_addr[1] +.sym 10379 w_smi_data_output[0] +.sym 10392 $PACKER_VCC_NET +.sym 10396 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10405 tx_fifo.empty_o_SB_LUT4_I1_O[3] +.sym 10409 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 10411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10412 w_smi_data_input[7] +.sym 10414 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 10423 w_smi_data_output[7] +.sym 10436 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 10439 tx_fifo.rd_addr[1] +.sym 10440 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 10441 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 10444 tx_fifo.rd_addr[0] +.sym 10445 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 10446 tx_fifo.rd_addr[2] +.sym 10453 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 10463 $nextpnr_ICESTORM_LC_5$O +.sym 10466 tx_fifo.rd_addr[0] +.sym 10469 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10472 tx_fifo.rd_addr[1] +.sym 10473 tx_fifo.rd_addr[0] +.sym 10475 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10478 tx_fifo.rd_addr[2] +.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10481 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10484 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 10485 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10487 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 10489 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 10491 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 10493 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 +.sym 10496 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 10497 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 10499 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10502 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 10503 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 +.sym 10505 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10507 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 10513 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 10514 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 10515 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 10516 tx_fifo.empty_o_SB_LUT4_I1_O[2] +.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 10518 w_tx_fifo_empty +.sym 10519 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 10537 w_smi_data_output[0] +.sym 10538 tx_fifo.rd_addr[1] +.sym 10540 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 10543 w_smi_data_output[7] +.sym 10546 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 10548 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 10549 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10554 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 10557 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 10558 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10560 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 10561 tx_fifo.rd_addr[9] +.sym 10564 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 10565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 10566 tx_fifo.rd_addr_gray[4] +.sym 10567 tx_fifo.rd_addr_gray[2] +.sym 10568 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 10569 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10571 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 10577 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10581 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 10584 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10586 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10589 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10590 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10593 tx_fifo.rd_addr[9] +.sym 10596 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 10600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 10601 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 10605 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 10606 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10607 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 10608 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 10611 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 10612 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10614 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 10618 tx_fifo.rd_addr_gray[2] +.sym 10623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 10624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 10625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 10626 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 10629 tx_fifo.rd_addr_gray[4] .sym 10634 r_counter_$glb_clk -.sym 10635 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10636 smi_ctrl_ins.r_fifo_pull_1 -.sym 10637 smi_ctrl_ins.r_fifo_pull -.sym 10638 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] -.sym 10639 smi_ctrl_ins.r_fifo_push -.sym 10640 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 10641 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 10642 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 10643 smi_ctrl_ins.r_fifo_push_1 -.sym 10648 smi_ctrl_ins.int_cnt_rx[3] -.sym 10649 rx_fifo.wr_addr[9] -.sym 10650 w_rx_fifo_pulled_data[28] -.sym 10653 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 10655 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 10658 rx_fifo.wr_addr[5] -.sym 10659 $PACKER_VCC_NET -.sym 10660 rx_fifo.wr_addr[0] -.sym 10661 rx_fifo.rd_addr_gray[3] -.sym 10662 rx_fifo.rd_addr[9] -.sym 10663 rx_fifo.rd_addr[1] -.sym 10664 rx_fifo.rd_addr[6] -.sym 10665 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10666 rx_fifo.wr_addr[3] -.sym 10667 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 10669 rx_fifo.rd_addr[7] -.sym 10670 w_rx_fifo_empty -.sym 10671 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 10677 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 10678 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 10679 i_rst_b$SB_IO_IN -.sym 10680 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10682 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 10686 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 10687 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 10688 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10689 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 10690 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 10691 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 10692 smi_ctrl_ins.int_cnt_rx[4] -.sym 10695 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] -.sym 10696 smi_ctrl_ins.int_cnt_rx[3] -.sym 10697 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 10699 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10700 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 10702 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 10704 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 10706 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 10707 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 10717 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10719 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10722 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10723 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 10724 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 10725 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 10729 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 10734 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 10735 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 10736 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] -.sym 10737 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 10740 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10741 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 10742 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 10743 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 10746 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 10747 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 10748 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 10749 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 10754 smi_ctrl_ins.int_cnt_rx[3] -.sym 10755 smi_ctrl_ins.int_cnt_rx[4] -.sym 10756 i_rst_b$SB_IO_IN -.sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 10759 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 10760 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] -.sym 10761 w_tx_fifo_full -.sym 10762 w_rx_fifo_empty -.sym 10763 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] -.sym 10764 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.sym 10765 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10766 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] -.sym 10771 w_smi_data_output[4] -.sym 10773 smi_ctrl_ins.w_fifo_push_trigger -.sym 10774 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 10777 rx_fifo.mem_i.0.3_WDATA -.sym 10779 w_smi_data_output[5] -.sym 10783 rx_fifo.rd_addr[3] -.sym 10785 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 10786 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 10788 rx_fifo.wr_addr[0] -.sym 10789 rx_fifo.rd_addr[1] -.sym 10790 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 10793 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 10794 rx_fifo.wr_addr[3] -.sym 10804 rx_fifo.rd_addr[0] -.sym 10805 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 10806 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 10812 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 10817 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 10818 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 10822 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10823 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10825 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 10826 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10829 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 10830 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 10836 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 10839 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10841 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 10848 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10851 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 10852 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 10853 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 10854 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 10859 rx_fifo.rd_addr[0] -.sym 10865 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10871 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 10878 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 10879 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 10880 r_counter_$glb_clk +.sym 10636 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 10637 w_smi_data_output[7] +.sym 10638 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 10639 w_smi_data_output[3] +.sym 10640 w_smi_data_output[2] +.sym 10641 w_smi_data_output[6] +.sym 10642 w_smi_data_output[0] +.sym 10643 w_smi_data_output[1] +.sym 10650 tx_fifo.rd_addr_gray_wr[2] +.sym 10656 rx_fifo.mem_i.0.0_WDATA_2 +.sym 10661 w_rx_fifo_pulled_data[18] +.sym 10664 smi_ctrl_ins.int_cnt_rx[4] +.sym 10666 w_rx_fifo_pulled_data[19] +.sym 10667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 10669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10670 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10677 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 10678 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 10679 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 10680 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 10685 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10686 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 10687 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 10690 tx_fifo.rd_addr[9] +.sym 10691 tx_fifo.rd_addr[1] +.sym 10695 smi_ctrl_ins.int_cnt_rx[3] +.sym 10696 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10703 smi_ctrl_ins.int_cnt_rx[3] +.sym 10704 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10705 smi_ctrl_ins.int_cnt_rx[4] +.sym 10708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10713 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 10716 tx_fifo.rd_addr[1] +.sym 10722 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 10723 smi_ctrl_ins.int_cnt_rx[3] +.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 10725 smi_ctrl_ins.int_cnt_rx[4] +.sym 10729 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 10730 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 10735 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 10736 smi_ctrl_ins.int_cnt_rx[3] +.sym 10737 smi_ctrl_ins.int_cnt_rx[4] +.sym 10743 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 10746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10747 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10748 tx_fifo.rd_addr[9] +.sym 10749 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10754 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 10756 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 10757 lvds_clock_$glb_clk +.sym 10758 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10759 tx_fifo.wr_addr_gray_rd[7] +.sym 10760 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 10761 tx_fifo.wr_addr_gray_rd[8] +.sym 10762 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 10763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 10764 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 10765 tx_fifo.wr_addr_gray_rd[1] +.sym 10766 tx_fifo.wr_addr_gray_rd[5] +.sym 10772 rx_fifo.rd_addr[6] +.sym 10775 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 10776 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 10780 rx_fifo.rd_addr[0] +.sym 10782 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 10783 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10793 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 10801 w_rx_fifo_pulled_data[4] +.sym 10802 smi_ctrl_ins.int_cnt_rx[4] +.sym 10805 smi_ctrl_ins.int_cnt_rx[3] +.sym 10806 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 10807 w_rx_fifo_pulled_data[6] +.sym 10808 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 10809 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 10810 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 10813 smi_ctrl_ins.int_cnt_rx[3] +.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10821 w_rx_fifo_pulled_data[18] +.sym 10826 w_rx_fifo_pulled_data[19] +.sym 10828 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10830 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 10836 w_rx_fifo_pulled_data[6] +.sym 10839 smi_ctrl_ins.int_cnt_rx[3] +.sym 10840 smi_ctrl_ins.int_cnt_rx[4] +.sym 10841 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 10842 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 10848 w_rx_fifo_pulled_data[19] +.sym 10851 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 10852 smi_ctrl_ins.int_cnt_rx[4] +.sym 10853 smi_ctrl_ins.int_cnt_rx[3] +.sym 10854 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 10857 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10858 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10859 smi_ctrl_ins.int_cnt_rx[4] +.sym 10860 smi_ctrl_ins.int_cnt_rx[3] +.sym 10865 w_rx_fifo_pulled_data[18] +.sym 10870 w_rx_fifo_pulled_data[4] +.sym 10875 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 10876 smi_ctrl_ins.int_cnt_rx[4] +.sym 10877 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 10878 smi_ctrl_ins.int_cnt_rx[3] +.sym 10879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 10880 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10883 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 10884 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 10885 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 10886 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 10887 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10888 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 10889 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10895 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 10900 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 10901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 10906 rx_fifo.rd_addr[6] -.sym 10907 rx_fifo.rd_addr[7] -.sym 10908 rx_fifo.rd_addr[5] -.sym 10909 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 10911 rx_fifo.rd_addr[3] -.sym 10912 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.sym 10913 rx_fifo.rd_addr[2] -.sym 10915 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 10916 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] -.sym 10917 rx_fifo.rd_addr[1] -.sym 10923 rx_fifo.wr_addr[0] -.sym 10924 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] -.sym 10925 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 10928 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 10930 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10932 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] -.sym 10936 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 10939 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 10942 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10943 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10944 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 10945 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 10946 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10951 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 10952 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10953 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10958 rx_fifo.wr_addr[0] -.sym 10962 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10963 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 10964 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 10969 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10970 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10974 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10980 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] -.sym 10981 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] -.sym 10982 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 10983 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 10987 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 10988 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 10993 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10994 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10995 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11001 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11002 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 11003 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 10883 tx_fifo.wr_addr_gray_rd[0] +.sym 10885 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 10886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 10888 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 10891 w_rx_fifo_pulled_data[4] +.sym 10898 $PACKER_VCC_NET +.sym 10899 o_smi_read_req$SB_IO_OUT +.sym 10904 tx_fifo.rd_addr_gray_wr_r[1] +.sym 10908 smi_ctrl_ins.int_cnt_rx[3] +.sym 10910 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 10912 rx_fifo.rd_addr[3] +.sym 10916 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 10941 smi_ctrl_ins.int_cnt_rx[4] +.sym 10952 smi_ctrl_ins.int_cnt_rx[3] +.sym 10968 smi_ctrl_ins.int_cnt_rx[3] +.sym 10970 smi_ctrl_ins.int_cnt_rx[4] +.sym 10989 smi_ctrl_ins.int_cnt_rx[3] +.sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 11004 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11005 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11006 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11007 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] -.sym 11008 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 11009 rx_fifo.rd_addr[4] -.sym 11010 rx_fifo.rd_addr_gray[5] -.sym 11011 rx_fifo.rd_addr[6] -.sym 11012 rx_fifo.rd_addr[5] -.sym 11021 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 11029 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 11030 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11032 rx_fifo.wr_addr[3] -.sym 11036 rx_fifo.wr_addr[4] -.sym 11037 rx_fifo.rd_addr_gray[4] -.sym 11039 rx_fifo.rd_addr_gray[2] -.sym 11040 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 11046 rx_fifo.wr_addr[7] -.sym 11049 rx_fifo.wr_addr[3] -.sym 11056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 11059 rx_fifo.wr_addr[1] -.sym 11061 rx_fifo.wr_addr[5] -.sym 11069 rx_fifo.wr_addr[8] -.sym 11075 rx_fifo.wr_addr[6] -.sym 11077 rx_fifo.wr_addr[4] -.sym 11078 $nextpnr_ICESTORM_LC_5$O -.sym 11081 rx_fifo.wr_addr[1] -.sym 11084 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 11087 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 11088 rx_fifo.wr_addr[1] -.sym 11090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11092 rx_fifo.wr_addr[3] -.sym 11094 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 11096 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 11098 rx_fifo.wr_addr[4] -.sym 11100 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11102 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 11105 rx_fifo.wr_addr[5] -.sym 11106 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 11108 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 11110 rx_fifo.wr_addr[6] -.sym 11112 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 11114 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11117 rx_fifo.wr_addr[7] -.sym 11118 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 11120 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 11123 rx_fifo.wr_addr[8] -.sym 11124 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11128 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 11129 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 11130 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] -.sym 11131 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] -.sym 11132 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 11133 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] -.sym 11134 rx_fifo.rd_addr_gray_wr[5] -.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] -.sym 11147 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11149 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11153 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] -.sym 11154 rx_fifo.rd_addr[9] -.sym 11155 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 11156 rx_fifo.rd_addr[4] -.sym 11157 rx_fifo.rd_addr[7] -.sym 11160 rx_fifo.rd_addr[6] -.sym 11161 rx_fifo.rd_addr_gray[3] -.sym 11163 rx_fifo.rd_addr[1] -.sym 11164 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 11170 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 11171 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 11173 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 11176 w_rx_data[5] -.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11178 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11180 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 11182 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 11183 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 11187 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 11188 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 11189 w_rx_data[0] -.sym 11190 rx_fifo.rd_addr_gray_wr_r[6] -.sym 11191 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 11192 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] -.sym 11193 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11197 rx_fifo.wr_addr[9] -.sym 11199 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 11203 rx_fifo.wr_addr[9] -.sym 11205 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 11208 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] -.sym 11209 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 11210 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 11211 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 11215 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11220 w_rx_data[5] -.sym 11226 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 11227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 11228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 11229 rx_fifo.rd_addr_gray_wr_r[6] -.sym 11235 w_rx_data[0] -.sym 11238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 11239 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11240 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 11244 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 11246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 11247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 11248 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 11010 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 11011 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 11019 smi_ctrl_ins.int_cnt_rx[3] +.sym 11023 smi_ctrl_ins.int_cnt_rx[4] +.sym 11024 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 11028 rx_fifo.rd_addr[8] +.sym 11030 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 11038 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 11048 rx_fifo.rd_addr[6] +.sym 11049 rx_fifo.rd_addr[3] +.sym 11054 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 11056 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 11057 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11058 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 11060 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 11061 rx_fifo.rd_addr[0] +.sym 11078 $nextpnr_ICESTORM_LC_8$O +.sym 11081 rx_fifo.rd_addr[0] +.sym 11084 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11086 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11088 rx_fifo.rd_addr[0] +.sym 11090 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 11092 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 11094 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 11096 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 11099 rx_fifo.rd_addr[3] +.sym 11100 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 11104 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 11106 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 11111 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 11117 rx_fifo.rd_addr[6] +.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11123 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 11128 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11132 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 11144 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 11146 rx_fifo.wr_addr[6] +.sym 11147 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11154 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 11157 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11163 rx_fifo.wr_addr_gray_rd[1] +.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11170 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 11172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11179 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11181 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 11190 rx_fifo.rd_addr[9] +.sym 11193 rx_fifo.rd_addr[8] +.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11203 rx_fifo.rd_addr[8] +.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11208 rx_fifo.rd_addr[9] +.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 11222 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 11227 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 11228 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 11239 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 11244 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 11246 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 11249 r_counter_$glb_clk .sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11251 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11252 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 11253 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 11254 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 11255 rx_fifo.rd_addr_gray_wr[3] -.sym 11256 rx_fifo.rd_addr_gray_wr[8] -.sym 11257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 11258 rx_fifo.rd_addr_gray_wr[2] -.sym 11269 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 11271 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11274 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 11275 rx_fifo.wr_addr[3] -.sym 11276 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 11277 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 11278 rx_fifo.rd_addr[8] -.sym 11279 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 11280 rx_fifo.wr_addr[0] -.sym 11282 rx_fifo.rd_addr[9] -.sym 11286 rx_fifo.rd_addr[1] -.sym 11297 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] -.sym 11298 rx_fifo.wr_addr_gray[4] -.sym 11301 rx_fifo.wr_addr_gray_rd[4] -.sym 11303 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 11304 rx_fifo.wr_addr_gray[2] -.sym 11305 rx_fifo.rd_addr[7] -.sym 11307 rx_fifo.rd_addr[8] -.sym 11312 rx_fifo.wr_addr_gray_rd[2] -.sym 11313 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 11320 rx_fifo.rd_addr[6] -.sym 11325 rx_fifo.wr_addr_gray_rd[4] -.sym 11332 rx_fifo.wr_addr_gray[4] -.sym 11352 rx_fifo.wr_addr_gray[2] -.sym 11357 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 11358 rx_fifo.rd_addr[8] -.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 11362 rx_fifo.rd_addr[6] -.sym 11363 rx_fifo.rd_addr[7] -.sym 11364 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] -.sym 11370 rx_fifo.wr_addr_gray_rd[2] +.sym 11251 w_rx_fifo_empty +.sym 11256 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 11258 rx_fifo.empty_o_SB_LUT4_I0_I3[3] +.sym 11265 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 11266 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11267 rx_fifo.rd_addr[6] +.sym 11269 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11270 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 11271 rx_fifo.rd_addr[3] +.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11273 w_rx_data[0] +.sym 11278 rx_fifo.rd_addr[3] +.sym 11280 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 11292 rx_fifo.wr_addr_gray_rd[2] +.sym 11293 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 11295 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11296 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 11298 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] +.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11304 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 11306 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 11308 rx_fifo.wr_addr_gray[3] +.sym 11312 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11315 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 11316 rx_fifo.wr_addr_gray_rd[3] +.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11318 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 11319 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] +.sym 11322 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] +.sym 11325 rx_fifo.wr_addr_gray[3] +.sym 11331 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 11332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 11333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] +.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 11340 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11343 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 11344 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11349 rx_fifo.wr_addr_gray_rd[2] +.sym 11357 rx_fifo.wr_addr_gray_rd[3] +.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11364 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] +.sym 11369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] .sym 11372 r_counter_$glb_clk -.sym 11377 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 11380 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.sym 11381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11389 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 11390 rx_fifo.wr_addr[9] -.sym 11392 $PACKER_VCC_NET -.sym 11397 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 11399 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 11400 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 11401 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 11402 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 11403 rx_fifo.rd_addr[6] -.sym 11404 rx_fifo.rd_addr[3] -.sym 11405 rx_fifo.rd_addr[2] -.sym 11406 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11407 rx_fifo.rd_addr[7] -.sym 11408 rx_fifo.rd_addr[9] -.sym 11409 rx_fifo.rd_addr[1] -.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11417 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11423 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11426 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 11436 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 11441 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 11444 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11446 rx_fifo.rd_addr[1] -.sym 11448 rx_fifo.rd_addr[1] -.sym 11457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 11460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11461 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 11466 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 11473 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 11491 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 11494 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11374 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 11375 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] +.sym 11376 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] +.sym 11377 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 11378 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] +.sym 11379 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 11380 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 11392 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 11396 rx_fifo.wr_addr_gray_rd[2] +.sym 11407 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 11415 w_rx_fifo_empty +.sym 11417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11418 rx_fifo.wr_addr_gray_rd[9] +.sym 11420 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 11422 rx_fifo.empty_o_SB_LUT4_I0_I3[3] +.sym 11425 rx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 11426 rx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 11427 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11428 rx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 11431 rx_fifo.rd_addr[8] +.sym 11432 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 11433 rx_fifo.wr_addr_gray_rd[1] +.sym 11434 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11438 rx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11441 i_rst_b$SB_IO_IN +.sym 11442 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 11444 rx_fifo.rd_addr[9] +.sym 11446 rx_fifo.wr_addr_gray_rd[5] +.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 11451 i_rst_b$SB_IO_IN +.sym 11455 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11457 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 11460 rx_fifo.wr_addr_gray_rd[5] +.sym 11468 rx_fifo.wr_addr_gray_rd[9] +.sym 11472 rx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 11473 rx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 11474 rx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 11475 rx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11478 rx_fifo.empty_o_SB_LUT4_I0_I3[3] +.sym 11479 w_rx_fifo_empty +.sym 11480 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 11481 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 11484 rx_fifo.wr_addr_gray_rd[1] +.sym 11490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 11491 rx_fifo.rd_addr[9] +.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 11493 rx_fifo.rd_addr[8] .sym 11495 r_counter_$glb_clk -.sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11497 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 11499 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11500 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 11505 w_rx_data[0] -.sym 11513 rx_fifo.rd_addr[9] -.sym 11516 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 11521 rx_fifo.rd_addr_gray_wr[4] -.sym 11527 w_rx_data[4] -.sym 11528 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 11529 rx_fifo.rd_addr_gray[4] -.sym 11532 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 11542 rx_fifo.wr_addr_gray[1] -.sym 11543 rx_fifo.wr_addr_gray_rd[3] -.sym 11544 rx_fifo.wr_addr_gray[6] -.sym 11546 rx_fifo.wr_addr[9] -.sym 11547 rx_fifo.wr_addr_gray[3] -.sym 11557 rx_fifo.wr_addr_gray_rd[9] -.sym 11558 rx_fifo.wr_addr_gray_rd[1] -.sym 11562 rx_fifo.wr_addr_gray_rd[6] -.sym 11571 rx_fifo.wr_addr_gray[6] -.sym 11579 rx_fifo.wr_addr_gray_rd[6] -.sym 11584 rx_fifo.wr_addr_gray_rd[3] -.sym 11589 rx_fifo.wr_addr[9] -.sym 11597 rx_fifo.wr_addr_gray[1] -.sym 11604 rx_fifo.wr_addr_gray[3] -.sym 11607 rx_fifo.wr_addr_gray_rd[1] -.sym 11613 rx_fifo.wr_addr_gray_rd[9] +.sym 11497 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 11498 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] +.sym 11499 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 11500 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11501 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 11502 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11503 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 11504 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 11509 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11510 w_cs[0] +.sym 11514 rx_fifo.wr_addr_gray_rd[9] +.sym 11516 w_rx_data[1] +.sym 11517 w_rx_data[4] +.sym 11522 w_rx_fifo_empty +.sym 11530 w_rx_data[3] +.sym 11540 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11541 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 11548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 11550 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11574 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 11598 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 11604 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 11610 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 11614 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 11618 r_counter_$glb_clk -.sym 11620 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 11623 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 11624 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] -.sym 11626 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] -.sym 11627 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] -.sym 11632 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 11636 o_led0_SB_LUT4_I1_O[1] -.sym 11648 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 11667 rx_fifo.wr_addr_gray_rd[7] -.sym 11682 rx_fifo.wr_addr_gray_rd[8] -.sym 11688 rx_fifo.wr_addr_gray[8] -.sym 11692 rx_fifo.wr_addr_gray[7] -.sym 11696 rx_fifo.wr_addr_gray_rd[7] -.sym 11702 rx_fifo.wr_addr_gray_rd[8] -.sym 11727 rx_fifo.wr_addr_gray[8] -.sym 11730 rx_fifo.wr_addr_gray[7] -.sym 11741 r_counter_$glb_clk -.sym 11743 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 11744 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 11745 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 11747 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 11748 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 11749 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 11750 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 11778 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 11801 rx_fifo.rd_addr_gray[4] -.sym 11808 rx_fifo.rd_addr_gray[1] -.sym 11815 rx_fifo.rd_addr_gray_wr[1] -.sym 11820 rx_fifo.rd_addr_gray[4] -.sym 11826 rx_fifo.rd_addr_gray_wr[1] -.sym 11861 rx_fifo.rd_addr_gray[1] -.sym 11864 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 11866 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 11867 w_tx_data_io[7] -.sym 11870 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 11873 w_tx_data_io[5] -.sym 11989 i_button_SB_LUT4_I0_O[2] -.sym 11990 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 11992 io_ctrl_ins.pmod_dir_state[6] -.sym 11994 io_ctrl_ins.pmod_dir_state[7] -.sym 11995 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 11996 io_ctrl_ins.pmod_dir_state[5] -.sym 12001 i_button_SB_LUT4_I0_O[1] -.sym 12126 i_config[2]$SB_IO_IN -.sym 12128 o_led1_SB_LUT4_I1_I3[3] -.sym 12130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 12181 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 12225 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] +.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 11620 w_tx_data_smi[1] +.sym 11622 w_tx_data_smi[2] +.sym 11624 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 11625 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0] +.sym 11635 w_ioc[1] +.sym 11636 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 11642 w_cs[0] +.sym 11643 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 11645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 11646 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11647 rx_fifo.wr_addr_gray_rd[1] +.sym 11653 w_ioc[0] +.sym 11672 rx_fifo.rd_addr_gray_wr[0] +.sym 11673 rx_fifo.rd_addr_gray[1] +.sym 11674 rx_fifo.rd_addr_gray[7] +.sym 11681 rx_fifo.rd_addr_gray_wr[1] +.sym 11684 rx_fifo.rd_addr_gray_wr[7] +.sym 11689 rx_fifo.rd_addr_gray[0] +.sym 11695 rx_fifo.rd_addr_gray_wr[7] +.sym 11703 rx_fifo.rd_addr_gray_wr[0] +.sym 11714 rx_fifo.rd_addr_gray[0] +.sym 11721 rx_fifo.rd_addr_gray[1] +.sym 11725 rx_fifo.rd_addr_gray_wr[1] +.sym 11739 rx_fifo.rd_addr_gray[7] +.sym 11741 lvds_clock_$glb_clk +.sym 11746 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 11747 o_led0_SB_LUT4_I1_O[1] +.sym 11748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 11750 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 11751 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 11773 o_shdn_rx_lna$SB_IO_OUT +.sym 11784 rx_fifo.wr_addr_gray_rd[8] +.sym 11792 rx_fifo.wr_addr_gray[5] +.sym 11795 rx_fifo.wr_addr_gray[2] +.sym 11796 rx_fifo.wr_addr_gray[1] +.sym 11797 rx_fifo.wr_addr_gray[8] +.sym 11799 rx_fifo.wr_addr_gray[0] +.sym 11801 rx_fifo.wr_addr_gray_rd[0] +.sym 11817 rx_fifo.wr_addr_gray[8] +.sym 11826 rx_fifo.wr_addr_gray[0] +.sym 11831 rx_fifo.wr_addr_gray_rd[8] +.sym 11835 rx_fifo.wr_addr_gray_rd[0] +.sym 11843 rx_fifo.wr_addr_gray[2] +.sym 11849 rx_fifo.wr_addr_gray[5] +.sym 11861 rx_fifo.wr_addr_gray[1] +.sym 11864 r_counter_$glb_clk +.sym 11866 io_ctrl_ins.o_pmod[0] +.sym 11868 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 11869 io_ctrl_ins.o_pmod[3] +.sym 11870 io_ctrl_ins.o_pmod[2] +.sym 11871 o_led1_SB_LUT4_I1_O[2] +.sym 11872 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 11873 io_ctrl_ins.o_pmod[1] +.sym 11881 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 11883 w_load +.sym 11885 w_fetch +.sym 11896 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 11912 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11918 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11955 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 11986 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 11987 r_counter_$glb_clk +.sym 11988 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 11990 o_led0_SB_LUT4_I1_O[0] +.sym 11992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 11993 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 11995 o_led1_SB_LUT4_I1_O[0] +.sym 11996 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 12001 o_shdn_tx_lna$SB_IO_OUT +.sym 12006 w_rx_data[1] +.sym 12023 w_rx_data[3] +.sym 12125 w_rx_data[1] +.sym 12127 w_rx_data[3] +.sym 12133 w_rx_data[4] +.sym 12183 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 12187 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 12305 i_rst_b$SB_IO_IN +.sym 12307 o_shdn_tx_lna$SB_IO_OUT .sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E .sym 12310 w_smi_data_output[0] .sym 12312 w_smi_data_direction .sym 12313 w_smi_data_output[7] .sym 12315 w_smi_data_direction .sym 12316 $PACKER_VCC_NET -.sym 12319 w_smi_data_output[0] -.sym 12320 w_smi_data_output[7] -.sym 12322 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12323 w_smi_data_direction -.sym 12326 w_smi_data_direction +.sym 12320 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 12321 w_smi_data_direction +.sym 12326 w_smi_data_output[7] +.sym 12328 w_smi_data_output[0] +.sym 12329 w_smi_data_direction .sym 12332 $PACKER_VCC_NET -.sym 12335 tx_fifo.wr_addr[0] -.sym 12336 tx_fifo.wr_addr_gray[5] -.sym 12337 tx_fifo.wr_addr_gray[2] -.sym 12338 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 12339 tx_fifo.wr_addr_gray[3] -.sym 12341 tx_fifo.wr_addr_gray[6] -.sym 12342 tx_fifo.wr_addr[5] +.sym 12335 tx_fifo.wr_addr_gray_rd[2] +.sym 12336 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 12337 w_smi_data_direction +.sym 12338 tx_fifo.wr_addr_gray_rd[3] +.sym 12339 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12340 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 12341 tx_fifo.wr_addr_gray_rd[6] +.sym 12342 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 12368 $PACKER_VCC_NET .sym 12369 w_smi_data_input[7] -.sym 12384 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 12399 tx_fifo.wr_addr_gray[6] -.sym 12402 tx_fifo.wr_addr_gray[5] -.sym 12403 tx_fifo.wr_addr_gray[2] -.sym 12408 tx_fifo.wr_addr_gray_rd[5] -.sym 12417 tx_fifo.wr_addr_gray[6] -.sym 12423 tx_fifo.wr_addr_gray[2] -.sym 12436 tx_fifo.wr_addr_gray_rd[5] -.sym 12449 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 12453 tx_fifo.wr_addr_gray[5] -.sym 12457 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12463 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12465 tx_fifo.wr_addr[9] -.sym 12466 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12467 tx_fifo.wr_addr_gray[4] -.sym 12468 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12469 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 12470 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 12474 rx_fifo.rd_addr[6] -.sym 12476 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 12479 w_smi_data_direction -.sym 12480 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 12481 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12482 tx_fifo.wr_addr[0] -.sym 12485 rx_fifo.mem_i.0.1_WDATA_3 -.sym 12486 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12507 i_rst_b$SB_IO_IN -.sym 12515 $PACKER_VCC_NET -.sym 12520 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 12523 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 12524 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 12528 smi_ctrl_ins.int_cnt_rx[4] -.sym 12541 tx_fifo.wr_addr_gray_rd[6] -.sym 12543 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12544 tx_fifo.wr_addr_gray[3] -.sym 12546 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12553 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12555 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 12557 tx_fifo.wr_addr_gray_rd[4] -.sym 12559 smi_ctrl_ins.int_cnt_rx[4] -.sym 12560 tx_fifo.wr_addr_gray[4] -.sym 12562 i_rst_b$SB_IO_IN -.sym 12564 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12567 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12568 smi_ctrl_ins.int_cnt_rx[3] -.sym 12573 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12574 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12575 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12582 tx_fifo.wr_addr_gray[4] -.sym 12587 tx_fifo.wr_addr_gray[3] -.sym 12591 smi_ctrl_ins.int_cnt_rx[4] -.sym 12592 i_rst_b$SB_IO_IN -.sym 12593 smi_ctrl_ins.int_cnt_rx[3] -.sym 12598 tx_fifo.wr_addr_gray_rd[6] -.sym 12604 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12606 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 12617 tx_fifo.wr_addr_gray_rd[4] -.sym 12620 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12623 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 12624 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 12625 smi_ctrl_ins.int_cnt_rx[4] -.sym 12626 smi_ctrl_ins.int_cnt_rx[3] -.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 12629 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -.sym 12634 rx_fifo.wr_addr[3] -.sym 12635 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 12636 w_rx_fifo_pulled_data[23] -.sym 12639 rx_fifo.rd_addr[9] -.sym 12640 w_rx_fifo_pulled_data[29] -.sym 12641 w_rx_fifo_pulled_data[21] -.sym 12642 rx_fifo.wr_addr[0] -.sym 12643 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12644 w_rx_fifo_pulled_data[31] -.sym 12645 tx_fifo.wr_addr[9] -.sym 12647 smi_ctrl_ins.int_cnt_rx[3] -.sym 12649 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 12651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 12653 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 12654 tx_fifo.wr_addr_gray_rd[1] -.sym 12655 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12657 smi_ctrl_ins.r_fifo_push -.sym 12665 tx_fifo.wr_addr[9] -.sym 12673 tx_fifo.wr_addr_gray_rd[3] -.sym 12675 tx_fifo.wr_addr_gray_rd[2] -.sym 12680 tx_fifo.wr_addr_gray_rd[1] -.sym 12681 tx_fifo.wr_addr_gray_rd[9] -.sym 12708 tx_fifo.wr_addr[9] -.sym 12716 tx_fifo.wr_addr_gray_rd[3] -.sym 12726 tx_fifo.wr_addr_gray_rd[2] -.sym 12735 tx_fifo.wr_addr_gray_rd[1] -.sym 12739 tx_fifo.wr_addr_gray_rd[9] -.sym 12743 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 12745 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 12746 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] -.sym 12747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 12748 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 12749 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] -.sym 12750 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12751 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12752 tx_fifo.rd_addr_gray_wr[1] -.sym 12757 rx_fifo.rd_addr[1] -.sym 12758 w_rx_fifo_pulled_data[30] -.sym 12759 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12760 smi_ctrl_ins.int_cnt_rx[4] -.sym 12763 rx_fifo.wr_addr[0] -.sym 12764 rx_fifo.mem_i.0.3_WDATA_1 -.sym 12765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12769 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 12771 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 12772 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12773 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 12774 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 12775 smi_ctrl_ins.r_fifo_push_1 -.sym 12776 rx_fifo.wr_addr[5] -.sym 12778 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 12779 rx_fifo.wr_addr_gray_rd[0] -.sym 12780 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 12786 smi_ctrl_ins.r_fifo_pull_1 -.sym 12789 w_rx_fifo_empty -.sym 12793 smi_ctrl_ins.w_fifo_push_trigger -.sym 12795 smi_ctrl_ins.r_fifo_pull -.sym 12797 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 12801 smi_ctrl_ins.w_fifo_pull_trigger -.sym 12802 rx_fifo.rd_addr[3] -.sym 12807 rx_fifo.rd_addr[2] -.sym 12809 rx_fifo.rd_addr[1] -.sym 12812 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 12813 smi_ctrl_ins.r_fifo_push -.sym 12814 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 12815 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12821 smi_ctrl_ins.r_fifo_pull -.sym 12826 smi_ctrl_ins.w_fifo_pull_trigger -.sym 12832 rx_fifo.rd_addr[1] -.sym 12833 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12839 smi_ctrl_ins.w_fifo_push_trigger -.sym 12843 smi_ctrl_ins.r_fifo_pull -.sym 12844 w_rx_fifo_empty -.sym 12845 smi_ctrl_ins.r_fifo_pull_1 -.sym 12849 rx_fifo.rd_addr[2] -.sym 12850 rx_fifo.rd_addr[3] -.sym 12851 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 12857 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 12858 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 12864 smi_ctrl_ins.r_fifo_push -.sym 12866 r_counter_$glb_clk -.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12868 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 12869 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 12871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 12872 tx_fifo.wr_addr_gray[1] -.sym 12873 tx_fifo.wr_addr_gray[0] +.sym 12385 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 12389 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 12394 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 12397 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12398 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 12404 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12405 w_smi_data_output[2] +.sym 12406 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 12407 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 12411 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 12418 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 12434 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12435 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 12436 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 12437 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 12440 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 12447 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 12454 w_smi_data_output[2] +.sym 12456 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12457 lvds_clock_$glb_clk +.sym 12458 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 12464 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 12465 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 12466 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 12467 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 12468 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 12469 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 12470 w_tx_fifo_pull +.sym 12475 tx_fifo.rd_addr[1] +.sym 12481 w_smi_data_input[7] +.sym 12492 w_smi_data_output[4] +.sym 12498 w_smi_data_output[6] +.sym 12507 w_tx_fifo_pull +.sym 12509 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 12512 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 12513 i_rst_b_SB_LUT4_I3_O +.sym 12516 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 12524 w_smi_data_output[3] +.sym 12525 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12526 w_smi_data_output[2] +.sym 12527 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 12540 tx_fifo.rd_addr[1] +.sym 12541 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 12544 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12545 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12546 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 12547 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 12549 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 12553 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 12554 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 12555 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 12557 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 12558 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 12563 tx_fifo.rd_addr[2] +.sym 12564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 12565 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 12566 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 12567 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 12568 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 12570 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 12571 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 12573 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 12574 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 12575 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 12576 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 12579 tx_fifo.rd_addr[2] +.sym 12580 tx_fifo.rd_addr[1] +.sym 12581 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 12585 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12586 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 12587 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 12594 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 12598 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 12603 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 12604 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 12605 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 12609 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 12611 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 12612 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12615 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 12616 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 12617 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 12618 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 12623 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 12624 tx_fifo.wr_addr_gray_rd[9] +.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 12626 i_rst_b_SB_LUT4_I3_O +.sym 12627 tx_fifo.wr_addr_gray_rd[4] +.sym 12628 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12639 $PACKER_VCC_NET +.sym 12645 $PACKER_VCC_NET +.sym 12648 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 12649 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 12650 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 12652 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 12654 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 12666 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12667 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 12669 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 12670 w_tx_fifo_pull +.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12672 tx_fifo.empty_o_SB_LUT4_I1_O[3] +.sym 12673 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12675 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 12676 w_tx_fifo_empty +.sym 12677 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12678 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 12682 tx_fifo.empty_o_SB_LUT4_I1_O[2] +.sym 12685 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12686 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12687 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12688 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 12689 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 12690 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 12692 tx_fifo.rd_addr[9] +.sym 12694 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 12696 tx_fifo.empty_o_SB_LUT4_I1_O[3] +.sym 12697 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 12698 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 12699 tx_fifo.empty_o_SB_LUT4_I1_O[2] +.sym 12702 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 12703 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12704 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12705 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12708 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 12709 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 12710 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12711 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 12714 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12715 tx_fifo.rd_addr[9] +.sym 12716 w_tx_fifo_pull +.sym 12717 w_tx_fifo_empty +.sym 12722 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12726 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12727 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12728 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12729 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12732 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12733 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 12735 w_tx_fifo_pull +.sym 12738 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 12739 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 12741 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 12743 lvds_clock_$glb_clk +.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 12745 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 12747 tx_fifo.rd_addr_gray[3] +.sym 12748 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 12749 tx_fifo.rd_addr_gray[6] +.sym 12750 tx_fifo.rd_addr_gray[5] +.sym 12751 tx_fifo.rd_addr_gray[7] +.sym 12752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 12758 $PACKER_VCC_NET +.sym 12762 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12763 w_smi_data_output[5] +.sym 12764 rx_fifo.mem_i.0.0_WDATA_3 +.sym 12769 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 12770 tx_fifo.wr_addr_gray_rd[1] +.sym 12771 w_smi_data_output[6] +.sym 12772 i_rst_b$SB_IO_IN +.sym 12773 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12774 w_smi_data_output[4] +.sym 12775 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 12777 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12778 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 12779 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 12788 i_rst_b$SB_IO_IN +.sym 12793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12794 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 12795 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 12796 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 12797 smi_ctrl_ins.int_cnt_rx[3] +.sym 12798 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 12799 tx_fifo.rd_addr[1] +.sym 12801 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 12802 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 12805 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 12806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 12807 smi_ctrl_ins.int_cnt_rx[4] +.sym 12808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 12809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 12810 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 12811 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 12812 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 12813 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 12816 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 12817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 12819 smi_ctrl_ins.int_cnt_rx[3] +.sym 12820 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 12821 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 12822 smi_ctrl_ins.int_cnt_rx[4] +.sym 12826 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 12828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 12831 tx_fifo.rd_addr[1] +.sym 12832 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 12833 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 12834 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 12837 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 12838 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 12843 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 12845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 12849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 12851 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 12856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 12858 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 12861 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 12862 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 12865 i_rst_b$SB_IO_IN +.sym 12866 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 12868 tx_fifo.wr_addr_gray[8] +.sym 12869 tx_fifo.wr_addr_gray[5] +.sym 12870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 12871 tx_fifo.wr_addr_gray[1] +.sym 12872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 12873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] .sym 12874 tx_fifo.wr_addr_gray[7] -.sym 12875 tx_fifo.wr_addr_gray[8] -.sym 12880 rx_fifo.rd_addr[7] -.sym 12881 rx_fifo.rd_addr[6] -.sym 12882 rx_fifo.rd_addr[3] -.sym 12887 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12890 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 12891 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 12896 rx_fifo.wr_addr[7] -.sym 12898 $PACKER_VCC_NET -.sym 12900 rx_fifo.rd_addr[4] -.sym 12901 rx_fifo.rd_addr[3] +.sym 12875 tx_fifo.wr_addr_gray[0] +.sym 12880 rx_fifo.mem_i.0.0_WDATA_1 +.sym 12881 rx_fifo.wr_addr[6] +.sym 12883 rx_fifo.wr_addr[4] +.sym 12885 smi_ctrl_ins.int_cnt_rx[3] +.sym 12886 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 12889 rx_fifo.rd_addr[3] +.sym 12890 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 12895 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] .sym 12903 i_rst_b$SB_IO_IN -.sym 12910 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12912 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 12913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 12914 rx_fifo.rd_addr[2] -.sym 12915 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12916 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 12918 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 12919 w_tx_fifo_full -.sym 12920 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 12921 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12922 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 12923 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 12924 rx_fifo.rd_addr[1] -.sym 12925 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12927 smi_ctrl_ins.r_fifo_push -.sym 12928 w_rx_fifo_empty -.sym 12929 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] -.sym 12930 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12931 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 12932 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12935 smi_ctrl_ins.r_fifo_push_1 -.sym 12936 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 12939 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 12940 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 12942 smi_ctrl_ins.r_fifo_push -.sym 12943 w_tx_fifo_full -.sym 12945 smi_ctrl_ins.r_fifo_push_1 -.sym 12948 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 12949 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 12950 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 12954 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12955 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12956 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12957 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12960 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 12961 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 12962 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 12963 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 12967 rx_fifo.rd_addr[2] -.sym 12968 rx_fifo.rd_addr[1] -.sym 12969 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12972 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 12973 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 12974 rx_fifo.rd_addr[2] -.sym 12975 rx_fifo.rd_addr[1] -.sym 12978 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 12980 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 12984 w_rx_fifo_empty -.sym 12985 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 12986 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 12987 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] -.sym 12989 r_counter_$glb_clk -.sym 12990 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12991 tx_fifo.wr_addr_gray_rd[8] -.sym 12992 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 12994 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 12995 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 12997 tx_fifo.wr_addr_gray_rd[7] -.sym 12998 tx_fifo.wr_addr_gray_rd[0] -.sym 13003 tx_fifo.wr_addr[1] -.sym 13006 rx_fifo.wr_addr[4] -.sym 13007 rx_fifo.rd_addr[1] -.sym 13008 rx_fifo.rd_addr[2] -.sym 13009 w_tx_fifo_full -.sym 13010 rx_fifo.rd_addr[0] -.sym 13012 rx_fifo.wr_addr[3] -.sym 13016 w_tx_fifo_full -.sym 13018 w_rx_fifo_empty -.sym 13036 rx_fifo.rd_addr[3] -.sym 13038 rx_fifo.rd_addr[6] -.sym 13039 rx_fifo.rd_addr[5] -.sym 13044 rx_fifo.rd_addr[4] -.sym 13052 rx_fifo.rd_addr[0] -.sym 13053 rx_fifo.rd_addr[2] -.sym 13058 rx_fifo.rd_addr[7] -.sym 13063 rx_fifo.rd_addr[1] -.sym 13064 $nextpnr_ICESTORM_LC_4$O -.sym 13067 rx_fifo.rd_addr[0] -.sym 13070 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 13072 rx_fifo.rd_addr[1] -.sym 13074 rx_fifo.rd_addr[0] -.sym 13076 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 13078 rx_fifo.rd_addr[2] -.sym 13080 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 13082 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 13084 rx_fifo.rd_addr[3] -.sym 13086 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 13088 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 13090 rx_fifo.rd_addr[4] -.sym 13092 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 13094 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 13097 rx_fifo.rd_addr[5] -.sym 13098 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 13100 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 13103 rx_fifo.rd_addr[6] -.sym 13104 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 13106 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 13109 rx_fifo.rd_addr[7] -.sym 13110 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 13114 w_tx_data_smi[2] -.sym 13116 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 13117 w_tx_data_smi[1] -.sym 13119 w_tx_data_smi[0] -.sym 13120 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 12909 tx_fifo.wr_addr_gray_rd[7] +.sym 12916 tx_fifo.wr_addr_gray_rd[5] +.sym 12925 tx_fifo.wr_addr_gray[8] +.sym 12927 smi_ctrl_ins.int_cnt_rx[4] +.sym 12929 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 12930 smi_ctrl_ins.int_cnt_rx[3] +.sym 12934 tx_fifo.wr_addr_gray[5] +.sym 12935 tx_fifo.wr_addr_gray_rd[8] +.sym 12936 tx_fifo.wr_addr_gray[1] +.sym 12937 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12939 tx_fifo.wr_addr_gray[7] +.sym 12945 tx_fifo.wr_addr_gray[7] +.sym 12948 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12949 smi_ctrl_ins.int_cnt_rx[4] +.sym 12950 smi_ctrl_ins.int_cnt_rx[3] +.sym 12951 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 12954 tx_fifo.wr_addr_gray[8] +.sym 12960 tx_fifo.wr_addr_gray_rd[8] +.sym 12966 tx_fifo.wr_addr_gray_rd[7] +.sym 12972 tx_fifo.wr_addr_gray_rd[5] +.sym 12978 tx_fifo.wr_addr_gray[1] +.sym 12987 tx_fifo.wr_addr_gray[5] +.sym 12989 lvds_clock_$glb_clk +.sym 12991 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12993 w_smi_data_output[4] +.sym 12996 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 12998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 13003 rx_fifo.wr_addr[0] +.sym 13004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 13008 rx_fifo.mem_q.0.1_WDATA_3 +.sym 13009 rx_fifo.mem_q.0.1_WDATA_2 +.sym 13010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 13011 rx_fifo.wr_addr[4] +.sym 13014 rx_fifo.wr_addr[6] +.sym 13021 w_rx_fifo_pulled_data[31] +.sym 13026 w_rx_fifo_pulled_data[23] +.sym 13034 smi_ctrl_ins.int_cnt_rx[4] +.sym 13037 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 13039 tx_fifo.wr_addr_gray[0] +.sym 13042 smi_ctrl_ins.int_cnt_rx[4] +.sym 13045 smi_ctrl_ins.int_cnt_rx[3] +.sym 13046 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 13049 tx_fifo.wr_addr_gray_rd[0] +.sym 13056 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 13057 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 13063 i_rst_b$SB_IO_IN +.sym 13071 tx_fifo.wr_addr_gray[0] +.sym 13083 tx_fifo.wr_addr_gray_rd[0] +.sym 13089 smi_ctrl_ins.int_cnt_rx[3] +.sym 13090 smi_ctrl_ins.int_cnt_rx[4] +.sym 13091 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 13092 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 13101 i_rst_b$SB_IO_IN +.sym 13102 smi_ctrl_ins.int_cnt_rx[4] +.sym 13103 smi_ctrl_ins.int_cnt_rx[3] +.sym 13107 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 13108 smi_ctrl_ins.int_cnt_rx[4] +.sym 13109 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 13110 smi_ctrl_ins.int_cnt_rx[3] +.sym 13112 lvds_clock_$glb_clk +.sym 13114 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 13115 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 13117 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 13118 smi_ctrl_ins.r_fifo_pulled_data[29] .sym 13122 io_pmod[7]$SB_IO_IN .sym 13125 io_pmod[7]$SB_IO_IN -.sym 13129 w_rx_fifo_empty -.sym 13131 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 13138 rx_fifo.rd_addr[4] -.sym 13142 o_led0_SB_LUT4_I1_O[1] -.sym 13144 rx_fifo.rd_addr[5] -.sym 13150 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 13155 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 13157 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] -.sym 13159 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 13160 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] -.sym 13161 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 13162 rx_fifo.rd_addr[8] -.sym 13166 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 13167 rx_fifo.rd_addr[4] -.sym 13168 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 13169 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] -.sym 13172 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 13177 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13184 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] -.sym 13185 rx_fifo.rd_addr[9] -.sym 13186 rx_fifo.rd_addr[5] -.sym 13187 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 13189 rx_fifo.rd_addr[8] -.sym 13191 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 13196 rx_fifo.rd_addr[9] -.sym 13197 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 13200 rx_fifo.rd_addr[5] -.sym 13201 rx_fifo.rd_addr[4] -.sym 13202 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 13203 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 13206 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] -.sym 13207 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] -.sym 13208 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] -.sym 13209 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] -.sym 13214 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 13219 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13224 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 13231 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 13234 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 13235 r_counter_$glb_clk +.sym 13128 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 13129 rx_fifo.mem_q.0.1_WDATA +.sym 13130 w_rx_fifo_pulled_data[19] +.sym 13131 rx_fifo.wr_addr[7] +.sym 13133 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 13134 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 13135 w_rx_fifo_pulled_data[18] +.sym 13136 rx_fifo.mem_q.0.1_WDATA_1 +.sym 13138 w_rx_fifo_empty +.sym 13141 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13142 rx_fifo.rd_addr[8] +.sym 13145 i_rst_b$SB_IO_IN +.sym 13147 i_rst_b$SB_IO_IN +.sym 13178 w_rx_fifo_pulled_data[22] +.sym 13186 w_rx_fifo_pulled_data[23] +.sym 13218 w_rx_fifo_pulled_data[22] +.sym 13226 w_rx_fifo_pulled_data[23] +.sym 13234 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 13235 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13237 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 13238 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13243 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 13244 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 13251 $PACKER_VCC_NET -.sym 13252 rx_fifo.rd_addr[9] -.sym 13253 rx_fifo.wr_addr[1] -.sym 13258 rx_fifo.rd_addr[8] -.sym 13259 rx_fifo.rd_addr[4] -.sym 13262 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 13266 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 13269 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 13270 rx_fifo.rd_addr[6] -.sym 13279 rx_fifo.rd_addr[6] -.sym 13280 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 13281 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13282 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 13283 rx_fifo.rd_addr_gray[5] -.sym 13284 rx_fifo.rd_addr[2] -.sym 13285 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.sym 13286 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 13288 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13289 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13290 rx_fifo.rd_addr[4] -.sym 13292 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13293 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] -.sym 13294 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 13296 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] -.sym 13297 rx_fifo.rd_addr[9] -.sym 13298 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 13299 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.sym 13301 rx_fifo.rd_addr[8] -.sym 13302 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 13304 rx_fifo.rd_addr[5] -.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] -.sym 13309 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 13312 rx_fifo.rd_addr[6] -.sym 13313 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 13317 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13320 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 13323 rx_fifo.rd_addr[2] -.sym 13324 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 13325 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 13326 rx_fifo.rd_addr[4] -.sym 13329 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 13330 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] -.sym 13331 rx_fifo.rd_addr[5] -.sym 13336 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 13337 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 13341 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.sym 13342 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] -.sym 13343 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.sym 13344 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] -.sym 13348 rx_fifo.rd_addr_gray[5] -.sym 13353 rx_fifo.rd_addr[9] -.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13355 rx_fifo.rd_addr[8] -.sym 13356 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 13358 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13361 w_rx_data[4] -.sym 13362 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13363 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13364 w_rx_data[5] -.sym 13365 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13366 w_rx_data[7] -.sym 13367 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13373 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 13376 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 13377 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13382 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13385 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.sym 13386 io_pmod[6]$SB_IO_IN -.sym 13389 rx_fifo.rd_addr[3] -.sym 13390 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 13391 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13395 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13402 rx_fifo.rd_addr_gray_wr[4] -.sym 13405 rx_fifo.rd_addr_gray_wr[3] -.sym 13408 rx_fifo.rd_addr_gray_wr[2] -.sym 13412 rx_fifo.rd_addr_gray[2] -.sym 13414 rx_fifo.rd_addr_gray[3] -.sym 13415 rx_fifo.rd_addr_gray_wr[5] -.sym 13418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] -.sym 13421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] -.sym 13429 rx_fifo.rd_addr_gray[8] -.sym 13436 rx_fifo.rd_addr_gray_wr[3] -.sym 13442 rx_fifo.rd_addr_gray_wr[5] -.sym 13446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] -.sym 13449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] -.sym 13454 rx_fifo.rd_addr_gray_wr[4] -.sym 13460 rx_fifo.rd_addr_gray[3] -.sym 13464 rx_fifo.rd_addr_gray[8] -.sym 13471 rx_fifo.rd_addr_gray_wr[2] -.sym 13477 rx_fifo.rd_addr_gray[2] -.sym 13481 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 13483 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13484 spi_if_ins.state_if[0] -.sym 13485 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13486 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13487 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13488 spi_if_ins.state_if[1] -.sym 13489 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13490 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13496 rx_fifo.rd_addr_gray_wr[4] -.sym 13500 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13504 w_rx_data[4] -.sym 13507 w_rx_data[2] -.sym 13508 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13510 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13511 w_rx_data[5] -.sym 13512 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 13514 i_glob_clock$SB_IO_IN -.sym 13515 w_rx_data[7] -.sym 13516 w_rx_data[1] -.sym 13517 w_rx_data[6] -.sym 13518 w_rx_data[3] -.sym 13527 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 13529 rx_fifo.rd_addr[4] -.sym 13532 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13542 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 13546 io_pmod[6]$SB_IO_IN -.sym 13547 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13549 rx_fifo.rd_addr[3] -.sym 13551 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 13554 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13577 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13593 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 13594 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 13595 rx_fifo.rd_addr[3] -.sym 13596 rx_fifo.rd_addr[4] -.sym 13599 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13600 io_pmod[6]$SB_IO_IN -.sym 13601 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13603 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 13604 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13237 w_rx_data[0] +.sym 13240 w_rx_data[5] +.sym 13242 w_rx_data[2] +.sym 13243 i_rst_b$SB_IO_IN +.sym 13249 rx_fifo.wr_addr[9] +.sym 13251 rx_fifo.mem_i.0.3_WDATA +.sym 13253 rx_fifo.rd_addr[3] +.sym 13255 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 13256 $PACKER_VCC_NET +.sym 13257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 13258 rx_fifo.mem_i.0.3_WDATA_2 +.sym 13259 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 13260 rx_fifo.wr_addr[7] +.sym 13261 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13266 w_rx_fifo_empty +.sym 13269 w_tx_fifo_full +.sym 13270 w_rx_data[0] +.sym 13271 i_rst_b$SB_IO_IN +.sym 13289 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 13294 w_rx_data[0] +.sym 13299 w_rx_data[2] +.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 13312 w_rx_data[2] +.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 13337 w_rx_data[0] +.sym 13353 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 13357 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 13358 r_counter_$glb_clk +.sym 13359 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13361 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13362 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 13363 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 13364 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] +.sym 13365 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 13368 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 13372 rx_fifo.wr_addr[5] +.sym 13373 rx_fifo.wr_addr[1] +.sym 13374 rx_fifo.wr_addr[3] +.sym 13376 rx_fifo.wr_addr[8] +.sym 13382 rx_fifo.wr_addr[2] +.sym 13383 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 13385 w_fetch +.sym 13388 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 13390 w_rx_data[2] +.sym 13408 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 13410 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 13413 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 13414 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13416 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 13419 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 13420 rx_fifo.rd_addr[3] +.sym 13421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 13422 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 13427 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 13429 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 13434 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 13435 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 13436 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 13437 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 13464 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 13465 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 13466 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 13467 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 13476 rx_fifo.rd_addr[3] +.sym 13477 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 13478 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 13481 r_counter_$glb_clk +.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 13483 w_cs[3] +.sym 13484 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 13485 w_cs[1] +.sym 13486 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 13487 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 13488 w_cs[2] +.sym 13495 w_rx_fifo_empty +.sym 13499 w_rx_data[3] +.sym 13500 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 13502 rx_fifo.rd_addr[9] +.sym 13509 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 13511 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] +.sym 13513 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 13524 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13526 w_ioc[0] +.sym 13527 w_rx_data[4] +.sym 13528 w_cs[0] +.sym 13530 w_ioc[1] +.sym 13532 w_rx_data[1] +.sym 13534 w_ioc[1] +.sym 13540 w_rx_data[0] +.sym 13542 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 13543 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 13545 w_fetch +.sym 13550 w_rx_data[2] +.sym 13552 w_load +.sym 13557 w_ioc[1] +.sym 13559 w_ioc[0] +.sym 13560 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 13565 w_rx_data[1] +.sym 13571 w_rx_data[0] +.sym 13575 w_fetch +.sym 13576 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13577 w_load +.sym 13578 w_cs[0] +.sym 13582 w_rx_data[2] +.sym 13587 w_ioc[1] +.sym 13589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 13590 w_ioc[0] +.sym 13594 w_rx_data[4] +.sym 13603 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 13604 r_counter_$glb_clk .sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13607 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 13609 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13610 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13611 o_led0_SB_LUT4_I1_O[1] -.sym 13612 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 13618 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13625 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 13631 i_rst_b$SB_IO_IN -.sym 13632 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13633 o_led0_SB_LUT4_I1_O[1] -.sym 13636 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13639 w_rx_data[4] -.sym 13641 w_fetch -.sym 13648 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 13655 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13658 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 13663 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13667 rx_fifo.rd_addr[6] -.sym 13670 io_pmod[7]$SB_IO_IN -.sym 13671 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 13674 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 13676 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13678 rx_fifo.rd_addr[8] -.sym 13680 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 13682 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13693 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13694 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13695 io_pmod[7]$SB_IO_IN -.sym 13698 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 13699 rx_fifo.rd_addr[8] -.sym 13700 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 13701 rx_fifo.rd_addr[6] -.sym 13726 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 13727 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13606 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] +.sym 13607 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 13608 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 13609 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13610 r_tx_data[0] +.sym 13611 r_tx_data[2] +.sym 13612 r_tx_data[1] +.sym 13613 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 13619 io_pmod[0]$SB_IO_IN +.sym 13620 w_ioc[1] +.sym 13621 $PACKER_VCC_NET +.sym 13622 w_ioc[0] +.sym 13626 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 13628 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13630 w_cs[1] +.sym 13631 w_tx_data_io[2] +.sym 13632 i_rst_b$SB_IO_IN +.sym 13633 w_load +.sym 13634 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 13636 w_cs[2] +.sym 13637 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 13639 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13647 w_tx_data_smi[1] +.sym 13648 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 13649 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13651 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] +.sym 13652 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13653 w_ioc[1] +.sym 13654 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13655 w_fetch +.sym 13656 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] +.sym 13657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] +.sym 13659 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13660 w_cs[0] +.sym 13661 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 13662 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 13666 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13668 w_ioc[0] +.sym 13674 w_tx_data_io[1] +.sym 13680 w_tx_data_smi[1] +.sym 13681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 13682 w_tx_data_io[1] +.sym 13683 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 13686 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13687 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] +.sym 13694 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] +.sym 13695 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13698 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13705 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 13707 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] +.sym 13710 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 13712 w_fetch +.sym 13713 w_cs[0] +.sym 13716 w_ioc[1] +.sym 13717 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13718 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 13719 w_ioc[0] +.sym 13722 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13724 w_ioc[0] +.sym 13725 w_ioc[1] +.sym 13726 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13727 r_counter_$glb_clk .sym 13728 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13729 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] -.sym 13730 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13731 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 13732 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 13734 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13735 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 13736 o_led1_SB_LUT4_I1_I2[2] -.sym 13744 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E -.sym 13748 w_fetch -.sym 13755 o_rx_h_tx_l$SB_IO_OUT -.sym 13756 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 13757 i_rst_b$SB_IO_IN -.sym 13758 o_rx_h_tx_l_b$SB_IO_OUT -.sym 13762 w_rx_data[1] -.sym 13779 w_rx_data[2] -.sym 13780 w_rx_data[4] -.sym 13781 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 13786 w_rx_data[1] -.sym 13787 w_rx_data[7] -.sym 13788 w_rx_data[3] -.sym 13789 w_rx_data[6] -.sym 13806 w_rx_data[4] -.sym 13823 w_rx_data[6] -.sym 13828 w_rx_data[7] -.sym 13836 w_rx_data[3] -.sym 13841 w_rx_data[1] -.sym 13846 w_rx_data[2] -.sym 13849 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E +.sym 13729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 13730 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 13731 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 13732 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 13733 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 13735 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13743 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 13744 $PACKER_VCC_NET +.sym 13747 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13753 w_ioc[1] +.sym 13757 w_tx_fifo_full +.sym 13758 w_rx_data[0] +.sym 13759 io_ctrl_ins.o_pmod[3] +.sym 13760 w_tx_data_io[1] +.sym 13761 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13762 i_rst_b$SB_IO_IN +.sym 13763 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 13770 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 13774 o_led0_SB_LUT4_I1_O[1] +.sym 13775 w_tx_fifo_full +.sym 13781 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13783 w_rx_fifo_empty +.sym 13789 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 13804 w_tx_fifo_full +.sym 13817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 13830 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 13836 w_rx_fifo_empty +.sym 13849 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E .sym 13850 r_counter_$glb_clk -.sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13852 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 13853 io_ctrl_ins.pmod_dir_state[1] -.sym 13854 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 13856 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 13858 o_led1_SB_LUT4_I1_I3[1] -.sym 13867 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.sym 13878 spi_if_ins.w_rx_data[6] -.sym 13880 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 13881 i_rst_b$SB_IO_IN -.sym 13882 w_cs[2] -.sym 13884 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 13885 spi_if_ins.w_rx_data[5] -.sym 13886 o_led1_SB_LUT4_I1_I2[2] -.sym 13887 o_tr_vc1$SB_IO_OUT -.sym 13895 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13897 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13898 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13899 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] -.sym 13901 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13904 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13906 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] -.sym 13908 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] -.sym 13920 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13926 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13927 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13932 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13933 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] -.sym 13940 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13941 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13950 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 13951 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13956 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13959 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] -.sym 13963 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 13965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13968 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 13971 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] -.sym 13972 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13973 r_counter_$glb_clk +.sym 13851 o_led0_SB_LUT4_I1_O[1] +.sym 13852 w_tx_data_io[2] +.sym 13853 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 13854 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 13855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 13856 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 13857 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 13858 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 13859 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 13867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 13874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 13877 i_rst_b$SB_IO_IN +.sym 13878 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 13881 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 13882 w_rx_data[2] +.sym 13887 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 13897 o_led0_SB_LUT4_I1_O[1] +.sym 13898 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 13901 w_fetch +.sym 13902 w_cs[1] +.sym 13904 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13906 w_ioc[0] +.sym 13907 w_load +.sym 13909 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13913 w_ioc[1] +.sym 13920 io_pmod[7]$SB_IO_IN +.sym 13921 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13922 i_rst_b$SB_IO_IN +.sym 13944 w_load +.sym 13945 w_cs[1] +.sym 13946 w_fetch +.sym 13947 i_rst_b$SB_IO_IN +.sym 13950 w_ioc[1] +.sym 13952 w_ioc[0] +.sym 13953 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 13956 w_load +.sym 13957 o_led0_SB_LUT4_I1_O[1] +.sym 13958 w_fetch +.sym 13959 w_cs[1] +.sym 13968 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 13969 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 13971 io_pmod[7]$SB_IO_IN +.sym 13972 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13973 lvds_clock_$glb_clk .sym 13974 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13975 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 13976 w_cs[2] -.sym 13977 w_cs[3] -.sym 13979 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 13980 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 13982 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 14003 w_rx_data[7] -.sym 14004 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 14006 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 14007 i_glob_clock$SB_IO_IN -.sym 14008 w_rx_data[5] -.sym 14017 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 14022 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 14024 i_button_SB_LUT4_I0_O[2] -.sym 14026 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 14027 o_rx_h_tx_l$SB_IO_OUT -.sym 14028 o_rx_h_tx_l_b$SB_IO_OUT -.sym 14029 i_button_SB_LUT4_I0_O[1] -.sym 14043 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 14047 o_tr_vc1$SB_IO_OUT -.sym 14049 i_button_SB_LUT4_I0_O[1] -.sym 14050 o_rx_h_tx_l_b$SB_IO_OUT -.sym 14051 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 14055 i_button_SB_LUT4_I0_O[2] -.sym 14056 o_rx_h_tx_l$SB_IO_OUT -.sym 14058 i_button_SB_LUT4_I0_O[1] -.sym 14076 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 14092 o_tr_vc1$SB_IO_OUT -.sym 14093 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 14094 i_button_SB_LUT4_I0_O[1] -.sym 14095 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 13975 o_led0_SB_LUT4_I1_O[2] +.sym 13976 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 13978 w_tx_data_io[1] +.sym 13979 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 13980 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 13981 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 13982 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 13992 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 13995 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 14000 w_rx_data[0] +.sym 14002 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 14016 w_ioc[0] +.sym 14018 o_shdn_rx_lna$SB_IO_OUT +.sym 14019 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 14021 o_shdn_tx_lna$SB_IO_OUT +.sym 14022 w_rx_data[1] +.sym 14023 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 14028 w_rx_data[0] +.sym 14031 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 14034 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 14039 io_ctrl_ins.o_pmod[1] +.sym 14042 w_rx_data[2] +.sym 14044 io_ctrl_ins.o_pmod[2] +.sym 14046 w_rx_data[3] +.sym 14052 w_rx_data[0] +.sym 14061 w_ioc[0] +.sym 14062 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 14063 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 14069 w_rx_data[3] +.sym 14074 w_rx_data[2] +.sym 14079 io_ctrl_ins.o_pmod[1] +.sym 14080 w_ioc[0] +.sym 14081 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 14082 o_shdn_rx_lna$SB_IO_OUT +.sym 14085 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 14086 o_shdn_tx_lna$SB_IO_OUT +.sym 14087 w_ioc[0] +.sym 14088 io_ctrl_ins.o_pmod[2] +.sym 14092 w_rx_data[1] +.sym 14095 io_ctrl_ins.pmod_state_SB_DFFE_Q_E .sym 14096 r_counter_$glb_clk -.sym 14099 r_tx_data[2] -.sym 14100 r_tx_data[5] -.sym 14101 r_tx_data[7] -.sym 14102 r_tx_data[6] -.sym 14104 r_tx_data[4] -.sym 14105 r_tx_data[1] -.sym 14113 w_tx_data_io[1] +.sym 14098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] +.sym 14099 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 14100 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 14101 w_smi_data_direction +.sym 14102 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 14105 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 14111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 14119 i_config[0]$SB_IO_IN +.sym 14121 o_led0_SB_LUT4_I1_O[3] .sym 14123 i_rst_b$SB_IO_IN -.sym 14124 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 14129 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 14141 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 14146 i_config[2]$SB_IO_IN -.sym 14147 w_rx_data[6] -.sym 14150 io_ctrl_ins.pmod_dir_state[6] -.sym 14152 io_ctrl_ins.pmod_dir_state[7] -.sym 14154 o_led1_SB_LUT4_I1_I3[3] -.sym 14158 o_led1_SB_LUT4_I1_I2[2] -.sym 14160 i_button$SB_IO_IN -.sym 14163 w_rx_data[7] -.sym 14167 i_config[3]$SB_IO_IN -.sym 14168 w_rx_data[5] -.sym 14170 io_ctrl_ins.pmod_dir_state[5] -.sym 14172 io_ctrl_ins.pmod_dir_state[7] -.sym 14173 i_button$SB_IO_IN -.sym 14174 o_led1_SB_LUT4_I1_I3[3] -.sym 14175 o_led1_SB_LUT4_I1_I2[2] -.sym 14178 i_config[2]$SB_IO_IN -.sym 14179 io_ctrl_ins.pmod_dir_state[5] -.sym 14180 o_led1_SB_LUT4_I1_I2[2] -.sym 14181 o_led1_SB_LUT4_I1_I3[3] -.sym 14192 w_rx_data[6] -.sym 14202 w_rx_data[7] -.sym 14208 o_led1_SB_LUT4_I1_I3[3] -.sym 14209 i_config[3]$SB_IO_IN -.sym 14210 io_ctrl_ins.pmod_dir_state[6] -.sym 14211 o_led1_SB_LUT4_I1_I2[2] -.sym 14217 w_rx_data[5] -.sym 14218 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 14141 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E +.sym 14145 w_rx_data[3] +.sym 14149 w_rx_data[4] +.sym 14151 w_rx_data[1] +.sym 14154 w_rx_data[2] +.sym 14160 w_rx_data[0] +.sym 14178 w_rx_data[0] +.sym 14190 w_rx_data[4] +.sym 14196 w_rx_data[3] +.sym 14209 w_rx_data[1] +.sym 14217 w_rx_data[2] +.sym 14218 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E .sym 14219 r_counter_$glb_clk -.sym 14221 r_counter -.sym 14225 i_config[3]$SB_IO_IN -.sym 14226 i_button$SB_IO_IN -.sym 14235 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 14237 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 14243 w_rx_data[6] +.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14223 r_counter +.sym 14236 w_smi_data_direction +.sym 14237 o_shdn_rx_lna$SB_IO_OUT +.sym 14239 o_tr_vc1$SB_IO_OUT +.sym 14241 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 14243 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 14248 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] .sym 14249 i_rst_b$SB_IO_IN -.sym 14251 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O .sym 14344 i_rst_b$SB_IO_IN -.sym 14373 i_rst_b$SB_IO_IN -.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14412 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14418 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14359 i_glob_clock$SB_IO_IN +.sym 14365 i_rst_b$SB_IO_IN +.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14406 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14418 i_rst_b_SB_LUT4_I3_O .sym 14419 w_smi_data_output[3] .sym 14421 w_smi_data_direction .sym 14425 $PACKER_VCC_NET -.sym 14430 $PACKER_VCC_NET -.sym 14436 w_smi_data_direction -.sym 14439 w_smi_data_output[3] -.sym 14442 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14445 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14446 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14447 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 14448 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14449 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14450 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14451 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14455 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14430 w_smi_data_output[3] +.sym 14436 i_rst_b_SB_LUT4_I3_O +.sym 14438 w_smi_data_direction +.sym 14441 $PACKER_VCC_NET +.sym 14445 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 14454 w_smi_data_direction +.sym 14456 i_rst_b_SB_LUT4_I3_O +.sym 14457 smi_ctrl_ins.r_fifo_pulled_data[20] .sym 14474 i_rst_b$SB_IO_IN -.sym 14479 w_smi_data_output[3] -.sym 14486 tx_fifo.wr_addr[0] -.sym 14489 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14490 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14492 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 14495 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14496 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14498 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 14500 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14507 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 14513 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14521 tx_fifo.wr_addr[0] -.sym 14528 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14534 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14537 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14539 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 14546 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 14555 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 14557 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14561 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14565 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14566 r_counter_$glb_clk -.sym 14567 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14568 i_smi_swe_srw$SB_IO_IN -.sym 14572 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14573 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 14574 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 14575 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 14576 tx_fifo.rd_addr[1] -.sym 14577 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 14578 tx_fifo.rd_addr[0] -.sym 14579 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 14584 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 14588 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14592 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 14600 tx_fifo.rd_addr[7] -.sym 14601 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 14603 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 14606 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14617 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 14620 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 14621 tx_fifo.wr_addr[5] -.sym 14624 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14626 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14627 tx_fifo.rd_addr[1] -.sym 14629 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14631 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14632 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 14636 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 14638 smi_ctrl_ins.int_cnt_rx[4] -.sym 14651 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 14653 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14654 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14655 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14657 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 14658 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14659 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14660 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 14661 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 14664 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14665 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14668 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 14680 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14682 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14684 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 14689 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14690 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 14691 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14696 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 14701 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 14702 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 14713 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14714 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 14715 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14720 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14721 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14726 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 14727 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14728 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14729 r_counter_$glb_clk +.sym 14478 w_smi_data_output[4] +.sym 14489 tx_fifo.wr_addr_gray_rd[3] +.sym 14504 tx_fifo.wr_addr_gray[6] +.sym 14505 tx_fifo.wr_addr_gray[2] +.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 14510 tx_fifo.wr_addr_gray_rd[2] +.sym 14512 w_smi_data_direction +.sym 14513 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14514 tx_fifo.wr_addr_gray[3] +.sym 14516 tx_fifo.wr_addr_gray_rd[6] +.sym 14522 tx_fifo.wr_addr_gray[2] +.sym 14526 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14528 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 14534 w_smi_data_direction +.sym 14537 tx_fifo.wr_addr_gray[3] +.sym 14546 tx_fifo.wr_addr_gray_rd[3] +.sym 14551 tx_fifo.wr_addr_gray_rd[2] +.sym 14557 tx_fifo.wr_addr_gray[6] +.sym 14561 tx_fifo.wr_addr_gray_rd[6] +.sym 14566 lvds_clock_$glb_clk +.sym 14568 $io_pmod[3]$iobuf_i +.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14573 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14574 tx_fifo.wr_addr_gray[6] +.sym 14575 tx_fifo.wr_addr_gray[2] +.sym 14576 tx_fifo.wr_addr_gray[3] +.sym 14577 tx_fifo.wr_addr_gray[4] +.sym 14578 tx_fifo.wr_addr[9] +.sym 14579 tx_fifo.wr_addr[1] +.sym 14602 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 14613 $io_pmod[3]$iobuf_i +.sym 14614 w_smi_data_direction +.sym 14624 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 14627 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 14629 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14634 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 14636 tx_fifo.rd_addr_gray_wr_r[0] +.sym 14637 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 14638 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 14651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14652 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14653 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 14655 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 14656 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 14657 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 14658 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14661 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 14662 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 14663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 14666 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14671 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 14673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 14676 i_rst_b_SB_LUT4_I3_O +.sym 14678 w_tx_fifo_empty +.sym 14682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 14688 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14690 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14694 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 14695 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 14696 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 14697 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 14701 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 14703 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 14707 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 14712 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 14713 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 14715 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 14718 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 14719 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 14720 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 14721 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 14727 w_tx_fifo_empty +.sym 14728 i_rst_b_SB_LUT4_I3_O +.sym 14729 lvds_clock_$glb_clk .sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14731 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] -.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14733 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 14734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14735 w_tx_fifo_empty -.sym 14736 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 14737 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14738 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 14742 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 14745 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 14746 rx_fifo.wr_addr[5] -.sym 14749 tx_fifo.wr_addr[9] -.sym 14750 rx_fifo.mem_i.0.1_WDATA -.sym 14751 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 14753 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 14754 rx_fifo.mem_i.0.1_WDATA_2 -.sym 14758 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14759 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 14760 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 14761 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 14765 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 14766 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 14773 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14774 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14776 smi_ctrl_ins.int_cnt_rx[3] -.sym 14777 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 14778 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 14780 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 14784 tx_fifo.rd_addr[1] -.sym 14785 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 14786 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 14787 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 14788 tx_fifo.rd_addr[2] -.sym 14791 smi_ctrl_ins.int_cnt_rx[4] -.sym 14795 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14813 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 14814 tx_fifo.rd_addr[2] -.sym 14817 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 14818 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14819 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 14820 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 14823 smi_ctrl_ins.int_cnt_rx[4] -.sym 14824 smi_ctrl_ins.int_cnt_rx[3] -.sym 14831 smi_ctrl_ins.int_cnt_rx[3] -.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 14842 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14844 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 14847 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 14848 tx_fifo.rd_addr[2] -.sym 14849 tx_fifo.rd_addr[1] -.sym 14852 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14854 tx_fifo.rd_addr[2] -.sym 14855 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 14856 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 14857 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 14858 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 14859 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 14860 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] -.sym 14861 tx_fifo.rd_addr_gray[1] -.sym 14862 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 14865 w_tx_data_smi[2] -.sym 14868 i_rst_b$SB_IO_IN -.sym 14869 rx_fifo.rd_addr[3] -.sym 14870 rx_fifo.rd_addr[4] -.sym 14871 rx_fifo.mem_i.0.3_WDATA_2 -.sym 14873 rx_fifo.wr_addr[7] -.sym 14874 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 14876 smi_ctrl_ins.int_cnt_rx[3] -.sym 14878 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 14879 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 14880 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14881 tx_fifo.rd_addr[8] -.sym 14882 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 14885 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 14886 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 14888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 14896 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14897 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 14898 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 14899 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14902 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -.sym 14903 tx_fifo.rd_addr[1] -.sym 14904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 14906 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14909 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 14914 rx_fifo.wr_addr_gray_rd[0] -.sym 14917 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 14918 tx_fifo.rd_addr_gray[1] -.sym 14919 tx_fifo.rd_addr[2] -.sym 14922 i_rst_b$SB_IO_IN -.sym 14925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 14926 tx_fifo.rd_addr_gray_wr[1] -.sym 14928 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 14929 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 14934 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -.sym 14935 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 14936 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 14937 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 14940 i_rst_b$SB_IO_IN -.sym 14942 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 14949 tx_fifo.rd_addr_gray_wr[1] -.sym 14952 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 14953 tx_fifo.rd_addr[2] -.sym 14955 tx_fifo.rd_addr[1] -.sym 14958 rx_fifo.wr_addr_gray_rd[0] -.sym 14964 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14965 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14966 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14967 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14970 tx_fifo.rd_addr_gray[1] -.sym 14975 r_counter_$glb_clk -.sym 14977 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] -.sym 14978 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 14979 tx_fifo.wr_addr_gray_rd[1] -.sym 14980 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 14981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 14983 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] -.sym 14984 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] -.sym 14989 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 14993 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 14995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 14997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 14998 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 15001 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 15004 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15005 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 15007 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 15008 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 15012 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 15018 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 15019 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 15020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 15022 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 15023 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 15025 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 15027 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 15030 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 15031 tx_fifo.wr_addr[1] -.sym 15035 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 15037 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 15038 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 15040 tx_fifo.rd_addr[9] -.sym 15043 tx_fifo.rd_addr[8] -.sym 15051 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 15053 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 15054 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 15057 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 15060 tx_fifo.rd_addr[8] -.sym 15069 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 15070 tx_fifo.rd_addr[8] -.sym 15071 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 15072 tx_fifo.rd_addr[9] -.sym 15075 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 15084 tx_fifo.wr_addr[1] -.sym 15088 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 15090 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 15094 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 15095 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 14732 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 14734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.sym 14737 w_smi_data_output[5] +.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14748 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 14750 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 14752 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 14758 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 14763 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 14764 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 14765 tx_fifo.wr_addr[1] +.sym 14766 $PACKER_VCC_NET +.sym 14777 tx_fifo.wr_addr_gray[4] +.sym 14786 tx_fifo.wr_addr[9] +.sym 14792 i_rst_b$SB_IO_IN +.sym 14793 tx_fifo.wr_addr_gray_rd[4] +.sym 14798 tx_fifo.wr_addr_gray_rd[9] +.sym 14801 tx_fifo.wr_addr_gray_rd[1] +.sym 14803 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14814 tx_fifo.wr_addr_gray_rd[1] +.sym 14820 tx_fifo.wr_addr[9] +.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14829 i_rst_b$SB_IO_IN +.sym 14837 tx_fifo.wr_addr_gray[4] +.sym 14842 tx_fifo.wr_addr_gray_rd[4] +.sym 14849 tx_fifo.wr_addr_gray_rd[9] +.sym 14852 lvds_clock_$glb_clk +.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 14855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 14857 tx_fifo.rd_addr_gray_wr[5] +.sym 14858 tx_fifo.rd_addr_gray_wr[7] +.sym 14859 tx_fifo.rd_addr_gray_wr[3] +.sym 14860 tx_fifo.rd_addr_gray_wr[6] +.sym 14861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 14866 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 14874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 14875 i_rst_b$SB_IO_IN +.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 14881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 14886 smi_ctrl_ins.int_cnt_rx[4] +.sym 14895 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 14897 smi_ctrl_ins.int_cnt_rx[4] +.sym 14899 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 14902 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 14904 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 14906 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14909 smi_ctrl_ins.int_cnt_rx[3] +.sym 14911 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 14912 smi_ctrl_ins.int_cnt_rx[4] +.sym 14913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14915 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 14918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 14922 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 14923 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 14925 tx_fifo.wr_addr[1] +.sym 14926 tx_fifo.rd_addr_gray_wr_r[0] +.sym 14928 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 14929 smi_ctrl_ins.int_cnt_rx[3] +.sym 14930 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 14931 smi_ctrl_ins.int_cnt_rx[4] +.sym 14940 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 14946 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 14947 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 14948 smi_ctrl_ins.int_cnt_rx[3] +.sym 14949 smi_ctrl_ins.int_cnt_rx[4] +.sym 14955 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 14959 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 14966 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 14970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 14971 tx_fifo.rd_addr_gray_wr_r[0] +.sym 14972 tx_fifo.wr_addr[1] +.sym 14973 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 14974 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 14975 lvds_clock_$glb_clk +.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] +.sym 14980 o_smi_read_req$SB_IO_OUT +.sym 14981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 14988 w_rx_data[0] +.sym 14989 rx_fifo.wr_addr[2] +.sym 14997 rx_fifo.wr_addr[5] +.sym 14999 rx_fifo.wr_addr[8] +.sym 15001 w_smi_data_direction +.sym 15003 w_rx_fifo_pulled_data[28] +.sym 15004 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 15008 w_smi_data_direction +.sym 15010 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 15011 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 15020 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 15026 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15028 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 15029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 15030 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 15036 w_tx_fifo_full +.sym 15037 tx_fifo.wr_addr[1] +.sym 15038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 15041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 15042 tx_fifo.rd_addr_gray_wr_r[1] +.sym 15044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 15047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 15052 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15054 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 15057 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15064 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 15065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 15066 tx_fifo.rd_addr_gray_wr_r[1] +.sym 15072 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 15075 w_tx_fifo_full +.sym 15076 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 15078 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 15081 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 15082 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 15083 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 15087 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 15090 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 15093 tx_fifo.wr_addr[1] +.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 15098 r_counter_$glb_clk .sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15100 tx_fifo.rd_addr_gray[3] -.sym 15101 tx_fifo.rd_addr[8] -.sym 15102 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 15103 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 15104 tx_fifo.rd_addr_gray[0] -.sym 15105 tx_fifo.rd_addr_gray[8] -.sym 15106 tx_fifo.rd_addr[9] -.sym 15107 tx_fifo.rd_addr_gray[7] +.sym 15100 smi_ctrl_ins.r_fifo_pull_1 +.sym 15101 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 15102 w_tx_fifo_full +.sym 15103 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 15104 smi_ctrl_ins.r_fifo_pull +.sym 15106 smi_ctrl_ins.r_fifo_push_1 +.sym 15107 smi_ctrl_ins.r_fifo_push .sym 15108 i_rst_b$SB_IO_IN .sym 15111 i_rst_b$SB_IO_IN -.sym 15112 rx_fifo.rd_addr[0] -.sym 15113 tx_fifo.rd_addr[7] -.sym 15114 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 15118 tx_fifo.rd_addr_gray_wr[0] -.sym 15121 rx_fifo.rd_addr[5] -.sym 15122 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 15123 tx_fifo.wr_addr_gray_rd[1] -.sym 15124 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15130 $PACKER_VCC_NET -.sym 15133 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 15146 tx_fifo.wr_addr_gray[0] -.sym 15147 tx_fifo.wr_addr_gray[7] -.sym 15148 tx_fifo.wr_addr_gray[8] -.sym 15163 tx_fifo.wr_addr_gray_rd[7] -.sym 15164 tx_fifo.wr_addr_gray_rd[0] -.sym 15165 tx_fifo.wr_addr_gray_rd[8] -.sym 15177 tx_fifo.wr_addr_gray[8] -.sym 15182 tx_fifo.wr_addr_gray_rd[8] -.sym 15194 tx_fifo.wr_addr_gray_rd[0] -.sym 15200 tx_fifo.wr_addr_gray_rd[7] -.sym 15212 tx_fifo.wr_addr_gray[7] -.sym 15218 tx_fifo.wr_addr_gray[0] -.sym 15221 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 15224 $PACKER_VCC_NET -.sym 15225 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 15226 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15227 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 15228 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 15230 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15233 w_tx_data_smi[1] -.sym 15241 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 15242 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 15251 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 15253 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 15254 spi_if_ins.w_rx_data[4] -.sym 15257 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15258 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15270 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 15275 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15277 w_tx_fifo_full -.sym 15279 w_rx_fifo_empty -.sym 15284 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 15285 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15286 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 15293 o_led0_SB_LUT4_I1_O[1] -.sym 15299 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 15309 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 15312 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15316 w_tx_fifo_full -.sym 15330 w_rx_fifo_empty -.sym 15334 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15335 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 15343 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15344 r_counter_$glb_clk -.sym 15345 o_led0_SB_LUT4_I1_O[1] -.sym 15346 w_load -.sym 15347 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] -.sym 15348 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15349 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15350 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 15351 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 15352 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 15361 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15362 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 15367 $PACKER_VCC_NET -.sym 15369 io_pmod[6]$SB_IO_IN -.sym 15370 w_rx_data[0] -.sym 15372 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15375 spi_if_ins.spi.r_tx_byte[0] -.sym 15377 w_tx_data_smi[0] -.sym 15379 w_load -.sym 15388 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 15389 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15396 w_rx_data[0] -.sym 15397 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 15400 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15402 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15405 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 15406 i_rst_b$SB_IO_IN -.sym 15411 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 15421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 15423 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 15426 i_rst_b$SB_IO_IN -.sym 15427 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15456 w_rx_data[0] -.sym 15463 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15464 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 15465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15466 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.sym 15113 w_rx_fifo_empty +.sym 15114 rx_fifo.rd_addr[8] +.sym 15116 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 15118 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 15120 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 15121 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 15122 i_rst_b$SB_IO_IN +.sym 15123 rx_fifo.wr_addr[8] +.sym 15126 w_rx_fifo_pulled_data[29] +.sym 15135 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 15144 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 15145 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 15146 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 15152 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 15159 smi_ctrl_ins.int_cnt_rx[3] +.sym 15162 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 15167 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 15168 i_rst_b$SB_IO_IN +.sym 15169 smi_ctrl_ins.int_cnt_rx[4] +.sym 15175 smi_ctrl_ins.int_cnt_rx[4] +.sym 15176 smi_ctrl_ins.int_cnt_rx[3] +.sym 15187 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 15189 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 15204 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 15205 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 15206 smi_ctrl_ins.int_cnt_rx[4] +.sym 15207 smi_ctrl_ins.int_cnt_rx[3] +.sym 15216 smi_ctrl_ins.int_cnt_rx[4] +.sym 15217 smi_ctrl_ins.int_cnt_rx[3] +.sym 15218 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 15219 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 15220 i_rst_b$SB_IO_IN +.sym 15221 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 15223 spi_if_ins.w_rx_data[1] +.sym 15225 spi_if_ins.w_rx_data[2] +.sym 15226 spi_if_ins.w_rx_data[4] +.sym 15228 spi_if_ins.w_rx_data[5] +.sym 15229 spi_if_ins.w_rx_data[6] +.sym 15230 spi_if_ins.w_rx_data[0] +.sym 15233 w_smi_data_direction +.sym 15241 w_rx_fifo_empty +.sym 15244 smi_ctrl_ins.w_fifo_push_trigger +.sym 15246 w_tx_fifo_full +.sym 15252 w_rx_data[0] +.sym 15253 $PACKER_VCC_NET +.sym 15256 spi_if_ins.w_rx_data[1] +.sym 15258 w_rx_data[5] +.sym 15266 w_rx_fifo_pulled_data[31] +.sym 15275 w_rx_fifo_pulled_data[28] +.sym 15279 w_rx_fifo_pulled_data[30] +.sym 15286 w_rx_fifo_pulled_data[29] +.sym 15297 w_rx_fifo_pulled_data[30] +.sym 15306 w_rx_fifo_pulled_data[31] +.sym 15318 w_rx_fifo_pulled_data[28] +.sym 15321 w_rx_fifo_pulled_data[29] +.sym 15343 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15346 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 15347 spi_if_ins.w_rx_data[3] +.sym 15348 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 15350 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 15351 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 15352 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15353 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 15357 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 15358 rx_fifo.rd_addr[6] +.sym 15361 rx_fifo.rd_addr[0] +.sym 15362 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 15367 w_rx_fifo_pulled_data[30] +.sym 15370 spi_if_ins.w_rx_data[2] +.sym 15372 w_rx_data[2] +.sym 15376 spi_if_ins.w_rx_data[5] +.sym 15378 spi_if_ins.w_rx_data[6] +.sym 15380 spi_if_ins.w_rx_data[0] +.sym 15381 spi_if_ins.w_rx_data[3] +.sym 15392 spi_if_ins.w_rx_data[5] +.sym 15394 spi_if_ins.w_rx_data[0] +.sym 15397 spi_if_ins.w_rx_data[2] +.sym 15398 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15414 i_rst_b$SB_IO_IN +.sym 15421 spi_if_ins.w_rx_data[0] +.sym 15440 spi_if_ins.w_rx_data[5] +.sym 15452 spi_if_ins.w_rx_data[2] +.sym 15456 i_rst_b$SB_IO_IN +.sym 15466 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 15467 r_counter_$glb_clk -.sym 15468 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15470 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] -.sym 15471 w_ioc[2] -.sym 15472 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 15474 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] -.sym 15476 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] -.sym 15481 i_glob_clock$SB_IO_IN -.sym 15482 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15486 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 15493 spi_if_ins.spi.r_tx_byte[1] -.sym 15494 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 15495 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15496 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15497 spi_if_ins.r_tx_byte[2] -.sym 15499 spi_if_ins.r_tx_byte[3] -.sym 15502 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15503 w_rx_data[4] -.sym 15504 spi_if_ins.r_tx_byte[0] -.sym 15510 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15511 spi_if_ins.state_if[0] -.sym 15513 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15515 spi_if_ins.state_if[1] -.sym 15517 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15518 spi_if_ins.w_rx_data[5] -.sym 15521 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15524 spi_if_ins.w_rx_data[4] -.sym 15525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15528 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15534 i_rst_b$SB_IO_IN -.sym 15537 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15544 spi_if_ins.state_if[0] -.sym 15546 spi_if_ins.state_if[1] -.sym 15551 spi_if_ins.w_rx_data[4] -.sym 15555 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15556 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15557 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15561 spi_if_ins.state_if[1] -.sym 15562 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15563 spi_if_ins.state_if[0] -.sym 15570 spi_if_ins.w_rx_data[5] -.sym 15573 i_rst_b$SB_IO_IN -.sym 15574 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15576 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15581 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15585 spi_if_ins.state_if[1] -.sym 15587 spi_if_ins.state_if[0] -.sym 15588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15589 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 15470 w_rx_data[4] +.sym 15471 w_rx_data[7] +.sym 15472 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15473 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15474 w_rx_data[3] +.sym 15475 w_rx_data[1] +.sym 15476 w_rx_data[6] +.sym 15481 rx_fifo.wr_addr[0] +.sym 15482 rx_fifo.wr_addr[4] +.sym 15485 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 15486 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 15489 rx_fifo.mem_i.0.3_WDATA_1 +.sym 15490 w_rx_fifo_pulled_data[31] +.sym 15494 spi_if_ins.w_rx_data[1] +.sym 15495 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 15496 w_rx_data[5] +.sym 15500 w_rx_data[2] +.sym 15504 w_smi_data_direction +.sym 15513 w_rx_data[5] +.sym 15521 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 15528 w_rx_data[7] +.sym 15533 w_rx_data[6] +.sym 15538 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15539 w_rx_data[3] +.sym 15550 w_rx_data[7] +.sym 15558 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15563 w_rx_data[6] +.sym 15569 w_rx_data[3] +.sym 15575 w_rx_data[5] +.sym 15589 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O .sym 15590 r_counter_$glb_clk -.sym 15592 spi_if_ins.spi.r_tx_byte[2] -.sym 15593 spi_if_ins.spi.r_tx_byte[5] -.sym 15594 spi_if_ins.spi.r_tx_byte[0] -.sym 15595 spi_if_ins.spi.r_tx_byte[4] -.sym 15596 spi_if_ins.spi.r_tx_byte[3] -.sym 15597 spi_if_ins.spi.r_tx_byte[6] -.sym 15598 spi_if_ins.spi.r_tx_byte[1] -.sym 15599 spi_if_ins.spi.r_tx_byte[7] -.sym 15600 spi_if_ins.w_rx_data[5] -.sym 15604 i_rst_b$SB_IO_IN -.sym 15608 w_rx_data[4] -.sym 15610 w_fetch -.sym 15613 rx_fifo.wr_addr[8] -.sym 15616 w_ioc[2] -.sym 15617 w_load -.sym 15618 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15621 w_rx_data[5] -.sym 15622 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15625 w_rx_data[7] -.sym 15627 $PACKER_VCC_NET -.sym 15633 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15635 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15636 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15640 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15641 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 15642 spi_if_ins.state_if[0] -.sym 15644 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 15646 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15648 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15654 spi_if_ins.state_if[1] -.sym 15656 i_rst_b$SB_IO_IN -.sym 15659 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15660 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 15662 i_rst_b$SB_IO_IN -.sym 15664 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15666 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15667 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15668 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15672 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 15678 spi_if_ins.state_if[0] -.sym 15679 spi_if_ins.state_if[1] -.sym 15680 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15686 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15690 i_rst_b$SB_IO_IN -.sym 15691 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15692 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15696 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 15698 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15699 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15702 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15703 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 15704 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 15705 i_rst_b$SB_IO_IN -.sym 15709 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 15712 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 15591 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15592 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 15593 w_ioc[1] +.sym 15594 w_cs[0] +.sym 15595 w_ioc[4] +.sym 15596 w_ioc[3] +.sym 15597 w_ioc[0] +.sym 15598 w_ioc[2] +.sym 15599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 15605 w_rx_data[1] +.sym 15606 $PACKER_VCC_NET +.sym 15607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 15608 w_load +.sym 15609 i_rst_b$SB_IO_IN +.sym 15614 rx_fifo.rd_addr[8] +.sym 15621 i_glob_clock$SB_IO_IN +.sym 15622 w_rx_data[3] +.sym 15624 w_rx_data[1] +.sym 15627 w_ioc[1] +.sym 15635 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 15644 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15646 w_cs[2] +.sym 15648 spi_if_ins.w_rx_data[5] +.sym 15650 spi_if_ins.w_rx_data[6] +.sym 15651 w_cs[1] +.sym 15653 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15657 w_cs[3] +.sym 15659 w_cs[0] +.sym 15666 spi_if_ins.w_rx_data[5] +.sym 15667 spi_if_ins.w_rx_data[6] +.sym 15672 w_cs[3] +.sym 15673 w_cs[2] +.sym 15674 w_cs[0] +.sym 15675 w_cs[1] +.sym 15678 spi_if_ins.w_rx_data[5] +.sym 15681 spi_if_ins.w_rx_data[6] +.sym 15684 spi_if_ins.w_rx_data[6] +.sym 15687 spi_if_ins.w_rx_data[5] +.sym 15692 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15696 spi_if_ins.w_rx_data[6] +.sym 15697 spi_if_ins.w_rx_data[5] +.sym 15712 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 15713 r_counter_$glb_clk -.sym 15714 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15715 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 15716 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 15717 io_ctrl_ins.rf_pin_state[2] -.sym 15718 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] -.sym 15719 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 15720 io_ctrl_ins.rf_pin_state[7] -.sym 15722 io_ctrl_ins.rf_pin_state[5] -.sym 15731 w_rx_data[1] -.sym 15737 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15739 spi_if_ins.w_rx_data[4] -.sym 15741 spi_if_ins.w_rx_data[3] -.sym 15742 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15746 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 15747 spi_if_ins.w_rx_data[6] -.sym 15750 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 15758 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 15759 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 15763 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 15764 w_fetch -.sym 15769 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 15771 w_cs[2] -.sym 15774 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15777 w_load -.sym 15778 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15782 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15783 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 15786 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15787 o_led1_SB_LUT4_I1_I2[1] -.sym 15795 w_load -.sym 15796 o_led1_SB_LUT4_I1_I2[1] -.sym 15797 w_fetch -.sym 15798 w_cs[2] -.sym 15807 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15808 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 15809 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15810 w_cs[2] -.sym 15813 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15814 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15815 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15816 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 15819 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15820 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15821 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15825 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 15828 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 15835 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 15836 r_counter_$glb_clk -.sym 15837 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15838 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 15839 w_tx_data_io[2] -.sym 15840 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15841 o_led1_SB_LUT4_I1_I3[3] -.sym 15842 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] -.sym 15843 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 15844 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15845 o_led1_SB_LUT4_I1_I2[1] -.sym 15850 o_led1_SB_LUT4_I1_O[0] -.sym 15852 o_led0_SB_LUT4_I1_O[1] -.sym 15854 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 15856 i_rst_b$SB_IO_IN -.sym 15857 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15859 w_cs[2] -.sym 15860 spi_if_ins.w_rx_data[5] -.sym 15861 spi_if_ins.w_rx_data[6] -.sym 15863 o_led1_SB_LUT4_I1_I3[1] -.sym 15865 w_tx_data_smi[0] -.sym 15868 o_led1_SB_LUT4_I1_I2[2] -.sym 15869 w_cs[1] -.sym 15871 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 15872 w_load -.sym 15873 w_tx_data_io[2] -.sym 15879 w_rx_data[2] -.sym 15881 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 15885 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 15886 w_fetch -.sym 15887 w_load -.sym 15890 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15892 i_rst_b$SB_IO_IN -.sym 15894 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15897 w_cs[0] -.sym 15905 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15909 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15914 w_rx_data[2] -.sym 15918 w_fetch -.sym 15919 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 15921 w_cs[0] -.sym 15924 i_rst_b$SB_IO_IN -.sym 15927 w_fetch -.sym 15930 w_fetch -.sym 15931 w_cs[0] -.sym 15932 w_load -.sym 15943 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15944 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15945 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15948 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15949 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15950 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15951 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15954 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 15955 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 15956 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 15957 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15958 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 15714 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 15716 spi_if_ins.r_tx_byte[2] +.sym 15717 spi_if_ins.r_tx_byte[1] +.sym 15718 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 15719 spi_if_ins.r_tx_byte[0] +.sym 15720 spi_if_ins.r_tx_byte[7] +.sym 15721 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 15722 spi_if_ins.r_tx_byte[6] +.sym 15734 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 15736 w_ioc[1] +.sym 15740 w_cs[1] +.sym 15743 w_fetch +.sym 15744 w_rx_data[0] +.sym 15745 w_ioc[0] +.sym 15746 w_cs[2] +.sym 15749 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 15750 w_rx_data[5] +.sym 15756 w_cs[3] +.sym 15757 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] +.sym 15758 w_cs[1] +.sym 15759 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 15760 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 15761 w_cs[2] +.sym 15764 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 15765 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 15766 w_cs[0] +.sym 15767 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15769 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 15772 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] +.sym 15773 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 15774 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 15775 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 15776 i_rst_b$SB_IO_IN +.sym 15777 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0] +.sym 15778 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 15780 w_tx_data_io[2] +.sym 15781 i_glob_clock$SB_IO_IN +.sym 15782 w_tx_data_smi[2] +.sym 15783 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 15787 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 15789 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 15790 w_tx_data_io[2] +.sym 15791 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15792 w_tx_data_smi[2] +.sym 15795 w_cs[2] +.sym 15796 w_cs[3] +.sym 15797 w_cs[0] +.sym 15798 w_cs[1] +.sym 15801 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 15803 i_rst_b$SB_IO_IN +.sym 15807 w_cs[0] +.sym 15808 w_cs[3] +.sym 15809 w_cs[2] +.sym 15810 w_cs[1] +.sym 15813 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 15814 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 15815 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 15816 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 15819 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] +.sym 15820 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] +.sym 15821 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 15822 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 15825 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 15826 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 15828 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 15831 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0] +.sym 15832 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 15833 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 15834 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 15835 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 15836 i_glob_clock$SB_IO_IN +.sym 15838 r_tx_data[6] +.sym 15839 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 15840 r_tx_data[3] +.sym 15841 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 15842 r_tx_data[5] +.sym 15843 r_tx_data[7] +.sym 15844 r_tx_data[4] +.sym 15845 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] +.sym 15850 w_fetch +.sym 15855 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 15865 w_ioc[1] +.sym 15870 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 15872 w_rx_data[2] +.sym 15873 w_ioc[0] +.sym 15881 w_cs[2] +.sym 15884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] +.sym 15886 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 15887 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 15890 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 15892 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 15894 w_load +.sym 15896 o_led1_SB_LUT4_I1_I2[3] +.sym 15897 w_ioc[1] +.sym 15898 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 15903 w_fetch +.sym 15906 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 15909 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 15910 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15912 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15914 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 15920 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] +.sym 15921 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15924 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15926 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 15930 o_led1_SB_LUT4_I1_I2[3] +.sym 15931 w_cs[2] +.sym 15932 w_fetch +.sym 15933 w_load +.sym 15936 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15937 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 15943 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 15944 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 15948 w_ioc[1] +.sym 15949 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 15950 w_cs[2] +.sym 15951 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O .sym 15959 r_counter_$glb_clk -.sym 15961 w_ioc[3] -.sym 15962 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 15963 w_cs[0] -.sym 15964 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15965 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 15966 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15968 w_ioc[4] -.sym 15976 w_rx_data[6] -.sym 15978 w_rx_data[1] -.sym 15980 w_rx_data[3] -.sym 15981 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15983 w_rx_data[2] -.sym 15987 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 15988 spi_if_ins.r_tx_byte[2] -.sym 15989 spi_if_ins.w_rx_data[6] -.sym 15990 spi_if_ins.r_tx_byte[3] -.sym 15992 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15994 spi_if_ins.w_rx_data[5] -.sym 15996 spi_if_ins.r_tx_byte[0] -.sym 16002 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 16004 w_cs[3] -.sym 16009 o_led1_SB_LUT4_I1_I2[1] -.sym 16010 w_rx_data[4] -.sym 16011 w_cs[2] -.sym 16012 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 16015 w_rx_data[1] -.sym 16017 o_led1_SB_LUT4_I1_I2[2] -.sym 16020 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 16021 w_cs[1] -.sym 16028 w_cs[0] -.sym 16029 w_cs[1] -.sym 16035 o_led1_SB_LUT4_I1_I2[2] -.sym 16036 o_led1_SB_LUT4_I1_I2[1] -.sym 16037 w_cs[1] -.sym 16038 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 16042 w_rx_data[1] -.sym 16047 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 16059 w_cs[3] -.sym 16060 w_cs[1] -.sym 16061 w_cs[2] -.sym 16062 w_cs[0] -.sym 16074 w_rx_data[4] -.sym 16081 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15961 io_ctrl_ins.pmod_dir_state[5] +.sym 15962 o_led1_SB_LUT4_I1_I2[3] +.sym 15963 io_ctrl_ins.pmod_dir_state[6] +.sym 15964 o_led1_SB_LUT4_I1_I2[2] +.sym 15965 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 15967 io_ctrl_ins.pmod_dir_state[3] +.sym 15968 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 15978 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 15984 lvds_clock +.sym 15987 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 15991 w_smi_data_direction +.sym 15992 w_rx_data[2] +.sym 15996 w_rx_data[5] +.sym 16004 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 16006 o_led0_SB_LUT4_I1_O[1] +.sym 16008 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 16009 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16011 w_cs[1] +.sym 16012 w_load +.sym 16013 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 16014 w_ioc[1] +.sym 16015 w_fetch +.sym 16016 w_cs[2] +.sym 16017 w_ioc[0] +.sym 16020 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 16021 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 16022 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 16024 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 16025 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 16029 o_led1_SB_LUT4_I1_I2[2] +.sym 16032 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 16033 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 16035 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 16036 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 16037 o_led0_SB_LUT4_I1_O[1] +.sym 16041 w_load +.sym 16042 o_led1_SB_LUT4_I1_I2[2] +.sym 16043 w_cs[2] +.sym 16044 w_fetch +.sym 16047 o_led1_SB_LUT4_I1_I2[2] +.sym 16049 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 16050 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 16053 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 16054 w_ioc[0] +.sym 16055 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16059 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 16060 w_ioc[1] +.sym 16061 w_ioc[0] +.sym 16062 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 16066 w_ioc[0] +.sym 16067 w_ioc[1] +.sym 16068 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 16071 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 16072 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16073 w_cs[1] +.sym 16074 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 16077 w_ioc[1] +.sym 16078 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 16081 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E .sym 16082 r_counter_$glb_clk -.sym 16084 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16085 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16086 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 16087 w_cs[1] -.sym 16088 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16089 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16096 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.sym 16097 o_led1$SB_IO_OUT -.sym 16100 io_ctrl_ins.pmod_dir_state[1] -.sym 16103 i_rst_b$SB_IO_IN -.sym 16106 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 16111 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16113 i_glob_clock$SB_IO_IN -.sym 16129 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 16130 spi_if_ins.w_rx_data[5] -.sym 16131 w_tx_data_io[1] -.sym 16134 w_tx_data_io[7] -.sym 16137 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 16138 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 16139 spi_if_ins.w_rx_data[6] -.sym 16140 w_tx_data_io[5] -.sym 16142 w_tx_data_smi[1] -.sym 16143 w_tx_data_io[2] -.sym 16144 w_tx_data_smi[2] -.sym 16145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16149 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16152 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 16153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16158 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16159 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16160 w_tx_data_io[5] -.sym 16164 spi_if_ins.w_rx_data[5] -.sym 16166 spi_if_ins.w_rx_data[6] -.sym 16171 spi_if_ins.w_rx_data[5] -.sym 16173 spi_if_ins.w_rx_data[6] -.sym 16182 w_tx_data_io[7] -.sym 16183 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16185 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16188 w_tx_data_smi[1] -.sym 16189 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 16190 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16191 w_tx_data_io[1] -.sym 16200 w_tx_data_smi[2] -.sym 16201 w_tx_data_io[2] -.sym 16202 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 16203 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16204 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 16083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 16084 i_config_SB_LUT4_I0_1_O[1] +.sym 16085 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 16086 i_config_SB_LUT4_I0_1_O[3] +.sym 16087 w_tx_data_io[7] +.sym 16088 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 16089 w_tx_data_io[5] +.sym 16090 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 16091 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 16098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.sym 16109 w_rx_data[1] +.sym 16119 w_rx_data[3] +.sym 16125 o_led1_SB_LUT4_I1_O[3] +.sym 16126 o_led1_SB_LUT4_I1_I2[3] +.sym 16127 i_config[0]$SB_IO_IN +.sym 16128 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 16129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 16130 o_led1_SB_LUT4_I1_O[2] +.sym 16132 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16133 io_ctrl_ins.o_pmod[0] +.sym 16134 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 16136 o_led1_SB_LUT4_I1_I2[2] +.sym 16137 o_led0_SB_LUT4_I1_O[3] +.sym 16139 io_ctrl_ins.pmod_dir_state[3] +.sym 16140 io_ctrl_ins.o_pmod[3] +.sym 16141 o_led0_SB_LUT4_I1_O[2] +.sym 16142 o_led0_SB_LUT4_I1_O[0] +.sym 16143 w_ioc[0] +.sym 16145 o_led0_SB_LUT4_I1_O[1] +.sym 16146 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 16149 o_tr_vc2$SB_IO_OUT +.sym 16150 io_ctrl_ins.mixer_en_state +.sym 16152 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 16153 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16155 o_led1_SB_LUT4_I1_O[0] +.sym 16158 io_ctrl_ins.mixer_en_state +.sym 16159 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16160 w_ioc[0] +.sym 16161 io_ctrl_ins.o_pmod[0] +.sym 16164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 16165 io_ctrl_ins.o_pmod[3] +.sym 16166 o_tr_vc2$SB_IO_OUT +.sym 16167 w_ioc[0] +.sym 16176 o_led1_SB_LUT4_I1_O[0] +.sym 16177 o_led1_SB_LUT4_I1_O[3] +.sym 16178 o_led1_SB_LUT4_I1_O[2] +.sym 16179 o_led0_SB_LUT4_I1_O[1] +.sym 16182 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 16183 o_led1_SB_LUT4_I1_I2[3] +.sym 16184 i_config[0]$SB_IO_IN +.sym 16185 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 16188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16189 o_led1_SB_LUT4_I1_I2[2] +.sym 16190 io_ctrl_ins.pmod_dir_state[3] +.sym 16191 o_led0_SB_LUT4_I1_O[1] +.sym 16195 o_led1_SB_LUT4_I1_I2[3] +.sym 16197 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 16200 o_led0_SB_LUT4_I1_O[0] +.sym 16201 o_led0_SB_LUT4_I1_O[1] +.sym 16202 o_led0_SB_LUT4_I1_O[3] +.sym 16203 o_led0_SB_LUT4_I1_O[2] +.sym 16204 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 16205 r_counter_$glb_clk -.sym 16206 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 16207 spi_if_ins.r_tx_byte[5] -.sym 16208 spi_if_ins.r_tx_byte[2] -.sym 16209 spi_if_ins.r_tx_byte[3] -.sym 16210 spi_if_ins.r_tx_byte[6] -.sym 16211 spi_if_ins.r_tx_byte[4] -.sym 16212 spi_if_ins.r_tx_byte[0] -.sym 16213 spi_if_ins.r_tx_byte[7] -.sym 16214 spi_if_ins.r_tx_byte[1] -.sym 16221 i_rst_b$SB_IO_IN -.sym 16222 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16223 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 16224 o_rx_h_tx_l$SB_IO_OUT -.sym 16228 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16248 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16249 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 16251 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 16252 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 16253 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 16255 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 16256 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 16257 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 16259 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 16260 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16261 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16263 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 16266 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16268 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 16271 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16272 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 16273 i_glob_clock$SB_IO_IN -.sym 16276 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 16287 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16288 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 16289 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 16290 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 16293 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16294 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 16296 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 16300 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 16301 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 16302 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16305 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 16306 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16307 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16308 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 16317 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 16318 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 16319 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16320 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16323 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16325 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 16326 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 16327 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16328 i_glob_clock$SB_IO_IN -.sym 16343 spi_if_ins.r_tx_byte[7] -.sym 16344 o_tr_vc1$SB_IO_OUT -.sym 16345 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 16371 r_counter -.sym 16380 i_glob_clock$SB_IO_IN -.sym 16393 i_button$SB_IO_IN -.sym 16395 i_config[3]$SB_IO_IN -.sym 16406 r_counter -.sym 16429 i_config[3]$SB_IO_IN -.sym 16437 i_button$SB_IO_IN +.sym 16206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 16207 o_tr_vc2$SB_IO_OUT +.sym 16208 io_ctrl_ins.mixer_en_state +.sym 16209 o_shdn_tx_lna$SB_IO_OUT +.sym 16210 o_tr_vc1_b$SB_IO_OUT +.sym 16211 o_rx_h_tx_l$SB_IO_OUT +.sym 16212 o_shdn_rx_lna$SB_IO_OUT +.sym 16213 o_tr_vc1$SB_IO_OUT +.sym 16214 o_rx_h_tx_l_b$SB_IO_OUT +.sym 16219 o_led1_SB_LUT4_I1_O[3] +.sym 16228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 16232 o_rx_h_tx_l$SB_IO_OUT +.sym 16240 i_config[3]$SB_IO_IN +.sym 16249 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 16250 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 16251 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 16252 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16254 o_led1_SB_LUT4_I1_O[0] +.sym 16257 o_led0_SB_LUT4_I1_O[0] +.sym 16263 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 16264 i_rst_b$SB_IO_IN +.sym 16267 w_rx_data[0] +.sym 16272 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] +.sym 16281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 16283 o_led0_SB_LUT4_I1_O[0] +.sym 16288 o_led1_SB_LUT4_I1_O[0] +.sym 16290 o_led0_SB_LUT4_I1_O[0] +.sym 16293 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 16294 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 16295 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16296 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 16299 w_rx_data[0] +.sym 16305 i_rst_b$SB_IO_IN +.sym 16306 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] +.sym 16307 o_led1_SB_LUT4_I1_O[0] +.sym 16323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 16324 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 16325 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 16326 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 16327 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 16328 r_counter_$glb_clk +.sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16330 io_ctrl_ins.rf_pin_state[4] +.sym 16331 io_ctrl_ins.rf_pin_state[7] +.sym 16332 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 16333 io_ctrl_ins.rf_pin_state[5] +.sym 16334 io_ctrl_ins.rf_pin_state[1] +.sym 16335 io_ctrl_ins.rf_pin_state[6] +.sym 16336 io_ctrl_ins.rf_pin_state[3] +.sym 16337 io_ctrl_ins.rf_pin_state[2] +.sym 16338 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 16344 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 16347 o_rx_h_tx_l_b$SB_IO_OUT +.sym 16354 i_button$SB_IO_IN +.sym 16371 i_glob_clock$SB_IO_IN +.sym 16389 r_counter +.sym 16418 r_counter .sym 16451 i_glob_clock$SB_IO_IN .sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN +.sym 16457 w_rx_data[0] +.sym 16480 w_rx_data[2] +.sym 16484 w_rx_data[5] .sym 16497 r_counter -.sym 16515 r_counter -.sym 16523 i_rst_b$SB_IO_IN -.sym 16554 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 16555 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 16556 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16557 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16558 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 16559 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16560 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 16564 tx_fifo.rd_addr[1] -.sym 16567 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16585 i_smi_swe_srw$SB_IO_IN -.sym 16599 tx_fifo.rd_addr[1] -.sym 16601 tx_fifo.rd_addr[0] -.sym 16602 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 16607 tx_fifo.rd_addr[7] -.sym 16609 tx_fifo.rd_addr[0] -.sym 16615 tx_fifo.rd_addr[2] -.sym 16616 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 16620 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 16621 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 16627 $nextpnr_ICESTORM_LC_6$O -.sym 16629 tx_fifo.rd_addr[0] -.sym 16633 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16635 tx_fifo.rd_addr[1] -.sym 16637 tx_fifo.rd_addr[0] -.sym 16639 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 16642 tx_fifo.rd_addr[2] -.sym 16643 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16645 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 16648 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 16649 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 16651 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 16654 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 16655 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 16657 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16660 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 16661 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 16663 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 16665 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 16667 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16672 tx_fifo.rd_addr[7] -.sym 16673 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 16681 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 16682 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16683 tx_fifo.wr_addr[1] -.sym 16684 tx_fifo.wr_addr[3] -.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16686 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 16687 tx_fifo.wr_addr[4] -.sym 16688 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 16697 w_rx_fifo_pulled_data[22] -.sym 16698 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 16700 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 16702 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 16707 $PACKER_VCC_NET -.sym 16710 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 16712 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16715 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 16721 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 16723 w_smi_data_direction -.sym 16728 $PACKER_VCC_NET -.sym 16729 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 16730 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16731 tx_fifo.rd_addr[9] -.sym 16735 tx_fifo.rd_addr[2] -.sym 16736 w_smi_data_output[4] -.sym 16740 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16741 tx_fifo.wr_addr[7] -.sym 16743 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 16744 tx_fifo.wr_addr[8] -.sym 16747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16750 $PACKER_VCC_NET -.sym 16753 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16760 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 16761 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16762 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 16764 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 16767 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16768 tx_fifo.rd_addr[8] -.sym 16769 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 16770 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16774 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 16776 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 16787 tx_fifo.rd_addr[9] -.sym 16788 tx_fifo.rd_addr[0] -.sym 16790 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 16792 tx_fifo.rd_addr[8] -.sym 16794 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16798 tx_fifo.rd_addr[9] -.sym 16800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 16803 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 16805 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 16810 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 16812 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 16817 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 16830 tx_fifo.rd_addr[0] -.sym 16836 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 16837 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 16838 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16517 r_counter +.sym 16554 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 16555 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 16556 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 16557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 16558 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 16559 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 16560 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 16577 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 16585 w_smi_data_direction +.sym 16596 tx_fifo.wr_addr[4] +.sym 16610 tx_fifo.wr_addr[1] +.sym 16612 tx_fifo.wr_addr[5] +.sym 16614 tx_fifo.wr_addr[6] +.sym 16623 tx_fifo.wr_addr[3] +.sym 16624 tx_fifo.wr_addr[7] +.sym 16625 tx_fifo.wr_addr[2] +.sym 16626 tx_fifo.wr_addr[0] +.sym 16627 $nextpnr_ICESTORM_LC_3$O +.sym 16630 tx_fifo.wr_addr[0] +.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16635 tx_fifo.wr_addr[1] +.sym 16637 tx_fifo.wr_addr[0] +.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16641 tx_fifo.wr_addr[2] +.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 16645 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 16648 tx_fifo.wr_addr[3] +.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 16653 tx_fifo.wr_addr[4] +.sym 16655 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 16660 tx_fifo.wr_addr[5] +.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16665 tx_fifo.wr_addr[6] +.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 16669 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16671 tx_fifo.wr_addr[7] +.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 16681 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 16682 tx_fifo.wr_addr[5] +.sym 16683 tx_fifo.wr_addr[8] +.sym 16684 tx_fifo.wr_addr[6] +.sym 16685 tx_fifo.wr_addr[3] +.sym 16686 tx_fifo.wr_addr[7] +.sym 16687 tx_fifo.wr_addr[2] +.sym 16688 tx_fifo.wr_addr[0] +.sym 16694 tx_fifo.wr_addr[4] +.sym 16697 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 16703 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 16733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 16735 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 16736 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 16742 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 16744 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 16753 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 16765 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 16767 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 16769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 16770 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 16772 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 16775 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16776 tx_fifo.wr_addr[8] +.sym 16780 tx_fifo.wr_addr[9] +.sym 16783 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 16790 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 16793 tx_fifo.wr_addr[8] +.sym 16794 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 16798 tx_fifo.wr_addr[9] +.sym 16800 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 16812 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 16815 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 16823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 16828 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16833 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 16838 r_counter_$glb_clk .sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16841 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16852 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 16853 tx_fifo.rd_addr[7] -.sym 16856 tx_fifo.rd_addr[8] -.sym 16857 rx_fifo.mem_i.0.1_WDATA_1 -.sym 16860 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 16861 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16864 tx_fifo.wr_addr[6] -.sym 16865 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 16867 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 16868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 16870 $PACKER_VCC_NET -.sym 16871 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16874 rx_fifo.wr_addr[9] -.sym 16875 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 16881 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 16882 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 16883 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 16884 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 16886 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 16887 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 16890 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 16891 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 16892 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 16893 tx_fifo.rd_addr[1] -.sym 16894 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 16895 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 16896 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16897 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 16899 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 16900 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 16901 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 16902 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 16903 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 16905 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16907 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 16908 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 16909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16911 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 16912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16914 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 16915 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 16916 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 16917 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 16920 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 16921 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16922 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 16923 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 16926 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 16927 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 16928 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 16929 tx_fifo.rd_addr[1] -.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16933 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 16934 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 16935 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 16938 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 16939 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 16940 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 16941 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 16944 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 16946 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 16947 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 16951 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 16952 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 16953 tx_fifo.rd_addr_gray_wr_r[8] -.sym 16956 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 16957 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 16961 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 16962 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16963 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 16964 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] -.sym 16965 tx_fifo.wr_addr[7] -.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 16967 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -.sym 16968 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] -.sym 16969 tx_fifo.wr_addr[6] -.sym 16970 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] -.sym 16974 spi_if_ins.r_tx_byte[5] -.sym 16975 rx_fifo.wr_addr[7] -.sym 16976 tx_fifo.wr_addr[5] -.sym 16977 rx_fifo.wr_addr[1] -.sym 16985 w_tx_fifo_empty -.sym 16986 rx_fifo.mem_i.0.3_WDATA_3 -.sym 16987 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 16992 w_tx_fifo_empty -.sym 16994 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 16995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 17004 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] -.sym 17005 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] -.sym 17006 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17008 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 17009 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 17010 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] -.sym 17011 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 17012 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] -.sym 17013 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 17014 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 17015 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 17017 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 17018 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 17019 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 17021 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17022 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 17023 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 17026 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] -.sym 17030 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 17033 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 17037 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 17043 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] -.sym 17044 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] -.sym 17045 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] -.sym 17046 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] -.sym 17051 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 17055 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 17056 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] -.sym 17057 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 17064 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 17067 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 17068 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 17069 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 17070 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 17073 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 17074 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17075 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 17076 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 17082 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 17083 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17084 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 17085 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17086 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 17087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 17088 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17089 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 17090 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 17091 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 17092 tx_fifo.rd_addr_gray_wr[0] -.sym 17093 tx_fifo.rd_addr_gray_wr[7] -.sym 17096 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 17099 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 17102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17103 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 17104 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 17110 o_smi_read_req$SB_IO_OUT -.sym 17111 tx_fifo.rd_addr[9] -.sym 17112 $PACKER_VCC_NET -.sym 17113 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17121 w_smi_data_direction -.sym 17127 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 17128 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 17129 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 17130 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 17131 tx_fifo.rd_addr[7] -.sym 17132 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 17133 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17135 w_tx_fifo_pull -.sym 17137 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 17138 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 17139 tx_fifo.wr_addr_gray[1] -.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 17141 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17142 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 17143 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 17145 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 17146 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 17147 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 17150 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] -.sym 17151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 17152 w_tx_fifo_empty -.sym 17154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 17155 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] -.sym 17160 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 17161 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 17162 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 17163 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 17166 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17167 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 17169 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 17173 tx_fifo.wr_addr_gray[1] -.sym 17178 w_tx_fifo_pull -.sym 17179 w_tx_fifo_empty -.sym 17180 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 17181 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 17186 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 17187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 17196 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 17197 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] -.sym 17198 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 17199 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] -.sym 17202 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 17203 tx_fifo.rd_addr[7] -.sym 17204 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 17205 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 17207 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 17210 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17211 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17212 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17214 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17215 o_smi_read_req$SB_IO_OUT -.sym 17217 w_tx_fifo_pull -.sym 17222 o_miso_$_TBUF__Y_E -.sym 17225 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 17228 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 17230 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17232 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17233 w_load -.sym 17237 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17239 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17250 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 17252 w_tx_fifo_pull -.sym 17253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 17254 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17255 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 17259 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 17260 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 17261 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 17268 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17271 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 17274 tx_fifo.rd_addr[1] -.sym 17280 tx_fifo.rd_addr[9] -.sym 17286 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 17290 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 17295 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17296 tx_fifo.rd_addr[9] -.sym 17297 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 17298 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 17301 tx_fifo.rd_addr[1] -.sym 17302 w_tx_fifo_pull -.sym 17303 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 17308 tx_fifo.rd_addr[1] -.sym 17316 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 17320 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 17325 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 17326 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 17329 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 17330 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] +.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 16845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 16846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 16850 w_rx_data[3] +.sym 16851 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 16857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 16872 tx_fifo.wr_addr[2] +.sym 16875 $PACKER_VCC_NET +.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 16882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 16883 i_rst_b$SB_IO_IN +.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16890 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16891 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 16892 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 16894 tx_fifo.rd_addr_gray_wr_r[0] +.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 16903 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 16904 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 16905 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 16907 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 16910 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 16933 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 16934 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 16945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 16946 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 16947 tx_fifo.rd_addr_gray_wr_r[0] +.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 16952 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 16956 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 16958 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 16959 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 16960 i_rst_b$SB_IO_IN +.sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 16964 spi_if_ins.spi.r_rx_bit_count[1] +.sym 16965 spi_if_ins.spi.r_rx_bit_count[2] +.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] +.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] +.sym 16969 spi_if_ins.spi.r_rx_bit_count[0] +.sym 16970 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.sym 16973 w_ioc[0] +.sym 16975 $io_pmod[3]$iobuf_i +.sym 16979 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 16983 tx_fifo.rd_addr_gray_wr[4] +.sym 16984 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 16985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 16988 i_ss$SB_IO_IN +.sym 16990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 16993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 16994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.sym 17009 tx_fifo.rd_addr_gray[5] +.sym 17012 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17014 tx_fifo.rd_addr_gray[3] +.sym 17016 tx_fifo.rd_addr_gray[6] +.sym 17017 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 17018 tx_fifo.rd_addr_gray[7] +.sym 17026 tx_fifo.rd_addr_gray_wr[6] +.sym 17032 tx_fifo.rd_addr_gray_wr[7] +.sym 17033 tx_fifo.rd_addr_gray_wr[3] +.sym 17037 tx_fifo.rd_addr_gray_wr[6] +.sym 17043 tx_fifo.rd_addr_gray_wr[7] +.sym 17049 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 17052 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 17055 tx_fifo.rd_addr_gray[5] +.sym 17062 tx_fifo.rd_addr_gray[7] +.sym 17069 tx_fifo.rd_addr_gray[3] +.sym 17074 tx_fifo.rd_addr_gray[6] +.sym 17080 tx_fifo.rd_addr_gray_wr[3] +.sym 17084 r_counter_$glb_clk +.sym 17088 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 17089 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 17091 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 17092 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 17096 w_rx_data[6] +.sym 17100 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 17101 rx_fifo.rd_addr[9] +.sym 17105 i_sck$SB_IO_IN +.sym 17106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 17109 i_ss$SB_IO_IN +.sym 17129 w_tx_fifo_full +.sym 17130 tx_fifo.rd_addr_gray_wr[5] +.sym 17131 w_rx_fifo_empty +.sym 17132 i_rst_b$SB_IO_IN +.sym 17134 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.sym 17138 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] +.sym 17144 tx_fifo.wr_addr[2] +.sym 17151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] +.sym 17154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.sym 17156 tx_fifo.rd_addr_gray_wr_r[1] +.sym 17157 w_smi_data_direction +.sym 17160 tx_fifo.rd_addr_gray_wr_r[1] +.sym 17161 tx_fifo.wr_addr[2] +.sym 17162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 17179 w_rx_fifo_empty +.sym 17180 w_smi_data_direction +.sym 17181 w_tx_fifo_full +.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.sym 17186 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] +.sym 17187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] +.sym 17190 tx_fifo.rd_addr_gray_wr[5] +.sym 17204 i_rst_b$SB_IO_IN +.sym 17205 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 17207 r_counter_$glb_clk +.sym 17210 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17212 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17225 w_rx_fifo_pulled_data[6] +.sym 17227 io_pmod[0]$SB_IO_IN +.sym 17232 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 17234 i_mosi$SB_IO_IN +.sym 17251 w_rx_fifo_empty +.sym 17252 smi_ctrl_ins.w_fifo_push_trigger +.sym 17255 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 17256 smi_ctrl_ins.r_fifo_push_1 +.sym 17257 smi_ctrl_ins.r_fifo_push +.sym 17258 smi_ctrl_ins.w_fifo_pull_trigger +.sym 17260 w_tx_fifo_full +.sym 17262 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 17265 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 17270 smi_ctrl_ins.r_fifo_pull +.sym 17274 smi_ctrl_ins.r_fifo_pull_1 +.sym 17279 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 17285 smi_ctrl_ins.r_fifo_pull +.sym 17289 w_rx_fifo_empty +.sym 17291 smi_ctrl_ins.r_fifo_pull_1 +.sym 17292 smi_ctrl_ins.r_fifo_pull +.sym 17295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 17296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 17297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 17298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 17301 w_tx_fifo_full +.sym 17302 smi_ctrl_ins.r_fifo_push_1 +.sym 17303 smi_ctrl_ins.r_fifo_push +.sym 17310 smi_ctrl_ins.w_fifo_pull_trigger +.sym 17320 smi_ctrl_ins.r_fifo_push +.sym 17328 smi_ctrl_ins.w_fifo_push_trigger +.sym 17330 r_counter_$glb_clk .sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17332 tx_fifo.rd_addr_gray_wr_r[8] -.sym 17333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 17334 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17335 tx_fifo.rd_addr_gray_wr[8] -.sym 17336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17337 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17338 tx_fifo.rd_addr_gray_wr[3] -.sym 17339 tx_fifo.rd_addr_gray_wr[9] -.sym 17342 spi_if_ins.r_tx_byte[6] -.sym 17346 w_tx_fifo_pull -.sym 17355 i_ss$SB_IO_IN -.sym 17365 rx_fifo.wr_addr[9] -.sym 17366 $PACKER_VCC_NET -.sym 17367 spi_if_ins.w_rx_data[0] -.sym 17375 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17377 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17378 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 17382 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17385 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17388 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17391 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17395 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17398 $PACKER_VCC_NET -.sym 17405 $nextpnr_ICESTORM_LC_9$O -.sym 17408 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17411 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 17413 $PACKER_VCC_NET -.sym 17414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17418 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17420 $PACKER_VCC_NET -.sym 17421 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 17424 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 17425 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17430 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17432 $PACKER_VCC_NET -.sym 17433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17436 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17439 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17451 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17332 spi_if_ins.spi.r_rx_byte[5] +.sym 17333 spi_if_ins.spi.r_rx_byte[1] +.sym 17334 spi_if_ins.spi.r_rx_byte[7] +.sym 17335 spi_if_ins.spi.r_rx_byte[0] +.sym 17336 spi_if_ins.spi.r_rx_byte[2] +.sym 17337 spi_if_ins.spi.r_rx_byte[6] +.sym 17338 spi_if_ins.spi.r_rx_byte[4] +.sym 17339 spi_if_ins.spi.r_rx_byte[3] +.sym 17342 w_rx_data[4] +.sym 17347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17348 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 17351 i_ss$SB_IO_IN +.sym 17358 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17359 $PACKER_VCC_NET +.sym 17364 i_rst_b$SB_IO_IN +.sym 17384 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17390 spi_if_ins.spi.r_rx_byte[1] +.sym 17397 spi_if_ins.spi.r_rx_byte[5] +.sym 17400 spi_if_ins.spi.r_rx_byte[0] +.sym 17401 spi_if_ins.spi.r_rx_byte[2] +.sym 17402 spi_if_ins.spi.r_rx_byte[6] +.sym 17403 spi_if_ins.spi.r_rx_byte[4] +.sym 17407 spi_if_ins.spi.r_rx_byte[1] +.sym 17419 spi_if_ins.spi.r_rx_byte[2] +.sym 17426 spi_if_ins.spi.r_rx_byte[4] +.sym 17436 spi_if_ins.spi.r_rx_byte[5] +.sym 17444 spi_if_ins.spi.r_rx_byte[6] +.sym 17449 spi_if_ins.spi.r_rx_byte[0] +.sym 17452 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 17453 r_counter_$glb_clk -.sym 17454 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17458 spi_if_ins.r_tx_data_valid -.sym 17460 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17461 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17462 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17471 $PACKER_VCC_NET -.sym 17478 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17479 w_fetch -.sym 17487 w_load -.sym 17490 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17497 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 17498 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17500 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] -.sym 17505 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] -.sym 17506 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17508 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] -.sym 17511 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17516 spi_if_ins.spi.r_tx_byte[1] -.sym 17519 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 17521 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] -.sym 17523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 17524 spi_if_ins.spi.r_tx_byte[0] -.sym 17527 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17536 spi_if_ins.spi.r_tx_byte[1] -.sym 17537 spi_if_ins.spi.r_tx_byte[0] -.sym 17538 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17542 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 17549 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17553 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 17555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17556 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] -.sym 17562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] -.sym 17566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] -.sym 17572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] -.sym 17573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 17574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 17575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 17455 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 17456 spi_if_ins.state_if[0] +.sym 17457 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17458 spi_if_ins.state_if[1] +.sym 17459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 17460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 17461 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 17462 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17466 w_rx_data[7] +.sym 17467 spi_if_ins.w_rx_data[1] +.sym 17468 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 17469 w_rx_fifo_pulled_data[28] +.sym 17470 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 17472 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 17473 i_sck$SB_IO_IN +.sym 17474 rx_fifo.mem_i.0.3_WDATA_3 +.sym 17475 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17478 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 17480 w_rx_data[1] +.sym 17481 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17482 spi_if_ins.w_rx_data[4] +.sym 17485 $PACKER_VCC_NET +.sym 17486 w_rx_data[4] +.sym 17488 w_rx_data[7] +.sym 17490 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 17503 spi_if_ins.spi.r_rx_byte[3] +.sym 17504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 17506 spi_if_ins.spi.r_rx_byte[7] +.sym 17507 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17510 i_rst_b$SB_IO_IN +.sym 17512 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 17515 spi_if_ins.state_if[1] +.sym 17518 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17519 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17521 spi_if_ins.state_if[0] +.sym 17522 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17527 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17531 spi_if_ins.state_if[0] +.sym 17532 spi_if_ins.state_if[1] +.sym 17537 spi_if_ins.spi.r_rx_byte[3] +.sym 17542 spi_if_ins.spi.r_rx_byte[7] +.sym 17553 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17554 i_rst_b$SB_IO_IN +.sym 17555 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 17559 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 17560 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17561 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17566 i_rst_b$SB_IO_IN +.sym 17567 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17568 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 17571 spi_if_ins.state_if[1] +.sym 17573 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17574 spi_if_ins.state_if[0] +.sym 17575 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 17576 r_counter_$glb_clk -.sym 17577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17583 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17584 w_fetch -.sym 17585 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 17586 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 17590 w_load -.sym 17591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17592 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 17599 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 17601 i_ss$SB_IO_IN -.sym 17604 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 17607 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 17609 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 17610 spi_if_ins.r_tx_byte[4] -.sym 17619 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17620 spi_if_ins.spi.r_tx_byte[5] -.sym 17622 spi_if_ins.spi.r_tx_byte[4] -.sym 17624 spi_if_ins.spi.r_tx_byte[6] -.sym 17626 spi_if_ins.w_rx_data[2] -.sym 17627 spi_if_ins.spi.r_tx_byte[2] -.sym 17628 spi_if_ins.w_rx_data[1] -.sym 17630 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 17631 spi_if_ins.spi.r_tx_byte[3] -.sym 17632 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 17634 spi_if_ins.spi.r_tx_byte[7] -.sym 17637 spi_if_ins.w_rx_data[0] -.sym 17642 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17650 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17653 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17654 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17659 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17660 spi_if_ins.spi.r_tx_byte[6] -.sym 17661 spi_if_ins.spi.r_tx_byte[7] -.sym 17665 spi_if_ins.w_rx_data[2] -.sym 17673 spi_if_ins.w_rx_data[0] -.sym 17676 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17678 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 17683 spi_if_ins.w_rx_data[1] -.sym 17688 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17689 spi_if_ins.spi.r_tx_byte[5] -.sym 17691 spi_if_ins.spi.r_tx_byte[4] -.sym 17694 spi_if_ins.spi.r_tx_byte[3] -.sym 17695 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17696 spi_if_ins.spi.r_tx_byte[2] -.sym 17698 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17579 $PACKER_VCC_NET +.sym 17580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 17581 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 17583 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 17584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 17585 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17590 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 17592 w_rx_fifo_pulled_data[29] +.sym 17596 i_glob_clock$SB_IO_IN +.sym 17600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 17601 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 17604 w_rx_data[3] +.sym 17605 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 17606 w_rx_data[1] +.sym 17607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 17609 w_ioc[1] +.sym 17611 w_cs[0] +.sym 17612 w_rx_data[4] +.sym 17620 spi_if_ins.w_rx_data[3] +.sym 17621 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17623 spi_if_ins.w_rx_data[6] +.sym 17627 spi_if_ins.w_rx_data[1] +.sym 17629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17630 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17633 i_rst_b$SB_IO_IN +.sym 17634 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17642 spi_if_ins.w_rx_data[4] +.sym 17646 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17652 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17654 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17658 spi_if_ins.w_rx_data[4] +.sym 17666 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 17670 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17671 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17676 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 17677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17678 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17679 i_rst_b$SB_IO_IN +.sym 17682 spi_if_ins.w_rx_data[3] +.sym 17691 spi_if_ins.w_rx_data[1] +.sym 17697 spi_if_ins.w_rx_data[6] +.sym 17698 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 17699 r_counter_$glb_clk -.sym 17702 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 17705 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 17710 spi_if_ins.w_rx_data[1] -.sym 17712 spi_if_ins.r_tx_byte[7] -.sym 17714 spi_if_ins.w_rx_data[4] -.sym 17718 spi_if_ins.w_rx_data[3] -.sym 17720 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 17721 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17722 spi_if_ins.w_rx_data[2] -.sym 17724 spi_if_ins.w_rx_data[6] -.sym 17728 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17729 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 17730 w_load -.sym 17732 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 17733 w_fetch -.sym 17734 io_ctrl_ins.rf_pin_state[2] -.sym 17743 spi_if_ins.r_tx_byte[1] -.sym 17749 spi_if_ins.r_tx_byte[0] -.sym 17750 spi_if_ins.r_tx_byte[2] -.sym 17752 spi_if_ins.r_tx_byte[3] -.sym 17753 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17755 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17761 spi_if_ins.r_tx_byte[5] -.sym 17765 spi_if_ins.r_tx_byte[7] -.sym 17767 spi_if_ins.r_tx_byte[6] -.sym 17770 spi_if_ins.r_tx_byte[4] -.sym 17778 spi_if_ins.r_tx_byte[2] -.sym 17781 spi_if_ins.r_tx_byte[5] -.sym 17788 spi_if_ins.r_tx_byte[0] -.sym 17795 spi_if_ins.r_tx_byte[4] -.sym 17802 spi_if_ins.r_tx_byte[3] -.sym 17806 spi_if_ins.r_tx_byte[6] -.sym 17812 spi_if_ins.r_tx_byte[1] -.sym 17819 spi_if_ins.r_tx_byte[7] -.sym 17821 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 17701 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 17702 spi_if_ins.spi.r_tx_byte[7] +.sym 17703 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 17704 spi_if_ins.spi.r_tx_byte[5] +.sym 17705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 17706 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 17707 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 17708 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 17713 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 17714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17719 w_rx_data[0] +.sym 17720 w_fetch +.sym 17721 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 17722 $PACKER_VCC_NET +.sym 17724 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17732 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17735 spi_if_ins.spi.r_tx_bit_count[0] +.sym 17736 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17743 spi_if_ins.w_rx_data[2] +.sym 17744 spi_if_ins.w_rx_data[3] +.sym 17745 spi_if_ins.w_rx_data[0] +.sym 17746 w_ioc[3] +.sym 17752 spi_if_ins.w_rx_data[4] +.sym 17753 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 17755 spi_if_ins.w_rx_data[1] +.sym 17760 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17769 w_ioc[4] +.sym 17772 w_ioc[2] +.sym 17775 w_ioc[4] +.sym 17777 w_ioc[3] +.sym 17778 w_ioc[2] +.sym 17782 spi_if_ins.w_rx_data[1] +.sym 17789 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 17795 spi_if_ins.w_rx_data[4] +.sym 17799 spi_if_ins.w_rx_data[3] +.sym 17807 spi_if_ins.w_rx_data[0] +.sym 17812 spi_if_ins.w_rx_data[2] +.sym 17817 w_ioc[2] +.sym 17818 w_ioc[3] +.sym 17820 w_ioc[4] +.sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E .sym 17822 r_counter_$glb_clk -.sym 17823 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17824 o_led0_SB_LUT4_I1_O[0] -.sym 17825 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 17826 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 17827 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E -.sym 17828 o_led1_SB_LUT4_I1_O[0] -.sym 17830 o_led1_SB_LUT4_I1_I2[0] -.sym 17831 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 17833 spi_if_ins.r_tx_byte[1] -.sym 17834 spi_if_ins.r_tx_byte[1] -.sym 17837 w_rx_data[0] -.sym 17850 io_ctrl_ins.rf_pin_state[7] -.sym 17854 io_ctrl_ins.rf_pin_state[5] -.sym 17855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 17857 spi_if_ins.w_rx_data[5] -.sym 17865 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 17866 w_rx_data[5] -.sym 17867 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 17869 w_rx_data[2] -.sym 17870 w_rx_data[7] -.sym 17871 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 17874 i_rst_b$SB_IO_IN -.sym 17875 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 17876 io_pmod[2]$SB_IO_IN -.sym 17877 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 17883 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 17884 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 17888 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17891 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 17892 w_cs[1] -.sym 17898 i_rst_b$SB_IO_IN -.sym 17900 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 17901 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 17904 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 17905 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 17906 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 17907 w_cs[1] -.sym 17910 w_rx_data[2] -.sym 17916 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 17918 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 17919 io_pmod[2]$SB_IO_IN -.sym 17924 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 17925 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 17930 w_rx_data[7] -.sym 17940 w_rx_data[5] -.sym 17944 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 17824 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 17825 spi_if_ins.spi.r_tx_byte[6] +.sym 17826 spi_if_ins.spi.r_tx_byte[2] +.sym 17827 spi_if_ins.spi.r_tx_byte[0] +.sym 17828 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 17829 spi_if_ins.spi.r_tx_byte[1] +.sym 17830 spi_if_ins.spi.r_tx_byte[4] +.sym 17831 spi_if_ins.spi.r_tx_byte[3] +.sym 17837 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 17838 w_ioc[0] +.sym 17840 w_ioc[1] +.sym 17842 w_load +.sym 17848 spi_if_ins.r_tx_byte[5] +.sym 17849 w_fetch +.sym 17850 w_load +.sym 17855 w_ioc[0] +.sym 17856 i_rst_b$SB_IO_IN +.sym 17859 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 17869 r_tx_data[0] +.sym 17870 r_tx_data[2] +.sym 17871 r_tx_data[1] +.sym 17873 r_tx_data[6] +.sym 17875 w_cs[0] +.sym 17878 r_tx_data[7] +.sym 17883 w_cs[1] +.sym 17889 w_cs[3] +.sym 17892 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17894 w_cs[2] +.sym 17904 r_tx_data[2] +.sym 17910 r_tx_data[1] +.sym 17916 w_cs[3] +.sym 17917 w_cs[1] +.sym 17918 w_cs[0] +.sym 17919 w_cs[2] +.sym 17922 r_tx_data[0] +.sym 17931 r_tx_data[7] +.sym 17934 w_cs[2] +.sym 17935 w_cs[3] +.sym 17936 w_cs[1] +.sym 17937 w_cs[0] +.sym 17942 r_tx_data[6] +.sym 17944 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O .sym 17945 r_counter_$glb_clk -.sym 17947 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 17948 w_tx_data_io[1] -.sym 17949 w_tx_data_io[0] -.sym 17950 o_led1_SB_LUT4_I1_O[2] -.sym 17951 i_button_SB_LUT4_I0_O[1] -.sym 17952 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 17953 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 17954 o_led0_SB_LUT4_I1_O[3] -.sym 17960 o_led1_SB_LUT4_I1_I2[0] -.sym 17962 w_rx_data[4] -.sym 17963 spi_if_ins.w_rx_data[5] -.sym 17964 io_pmod[2]$SB_IO_IN -.sym 17965 w_rx_data[2] -.sym 17966 spi_if_ins.w_rx_data[6] -.sym 17967 w_rx_data[1] -.sym 17969 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 17970 io_pmod_SB_DFFE_Q_E -.sym 17971 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 17972 i_button_SB_LUT4_I0_O[1] -.sym 17973 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 17975 w_load -.sym 17976 w_fetch -.sym 17977 w_cs[1] -.sym 17978 w_rx_data[3] -.sym 17979 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 17988 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] -.sym 17989 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 17990 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 17991 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] -.sym 17995 w_ioc[4] -.sym 17996 w_ioc[3] -.sym 17997 w_ioc[2] -.sym 17999 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18000 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18001 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 18002 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 18003 o_shdn_tx_lna$SB_IO_OUT -.sym 18007 o_led1_SB_LUT4_I1_I3[3] -.sym 18008 i_button_SB_LUT4_I0_O[1] -.sym 18009 o_led0_SB_LUT4_I1_O[1] -.sym 18015 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 18016 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] -.sym 18018 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 18022 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 18023 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18024 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 18027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] -.sym 18028 i_button_SB_LUT4_I0_O[1] -.sym 18029 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] -.sym 18030 o_shdn_tx_lna$SB_IO_OUT -.sym 18034 w_ioc[4] -.sym 18035 w_ioc[2] -.sym 18036 w_ioc[3] -.sym 18039 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 18041 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 18042 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18045 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] -.sym 18046 o_led0_SB_LUT4_I1_O[1] -.sym 18047 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 18048 o_led1_SB_LUT4_I1_I3[3] -.sym 18051 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 18053 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 18054 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18058 w_ioc[3] -.sym 18059 w_ioc[2] -.sym 18060 w_ioc[4] -.sym 18063 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 18065 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 18066 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18067 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 18068 r_counter_$glb_clk -.sym 18069 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 18070 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18071 o_led1_SB_DFFER_Q_E -.sym 18073 o_led1_SB_LUT4_I1_O[3] -.sym 18074 w_smi_data_direction -.sym 18076 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 18077 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 18085 o_shdn_rx_lna$SB_IO_OUT -.sym 18087 o_led0_SB_LUT4_I1_O[2] -.sym 18088 i_glob_clock$SB_IO_IN -.sym 18091 o_shdn_tx_lna$SB_IO_OUT -.sym 18096 io_pmod[1]$SB_IO_IN -.sym 18097 o_led1_SB_LUT4_I1_I3[3] -.sym 18098 i_button_SB_LUT4_I0_O[1] -.sym 18100 o_led0_SB_LUT4_I1_O[1] -.sym 18101 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 18102 spi_if_ins.r_tx_byte[4] -.sym 18104 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 18105 o_led1_SB_LUT4_I1_I2[1] -.sym 18112 spi_if_ins.w_rx_data[4] -.sym 18113 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 18114 o_led1_SB_LUT4_I1_I3[3] -.sym 18115 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 18117 w_load -.sym 18120 spi_if_ins.w_rx_data[6] -.sym 18121 w_tx_data_io[0] -.sym 18122 spi_if_ins.w_rx_data[3] -.sym 18123 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18126 w_tx_data_smi[0] -.sym 18127 spi_if_ins.w_rx_data[5] -.sym 18128 w_cs[2] -.sym 18136 w_fetch -.sym 18138 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 18144 spi_if_ins.w_rx_data[3] -.sym 18150 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18151 w_tx_data_smi[0] -.sym 18152 w_tx_data_io[0] -.sym 18153 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 18156 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 18163 spi_if_ins.w_rx_data[6] -.sym 18165 spi_if_ins.w_rx_data[5] -.sym 18168 w_load -.sym 18169 w_cs[2] -.sym 18170 w_fetch -.sym 18171 o_led1_SB_LUT4_I1_I3[3] -.sym 18177 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 18188 spi_if_ins.w_rx_data[4] -.sym 18190 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 17949 spi_if_ins.r_tx_byte[4] +.sym 17952 spi_if_ins.r_tx_byte[3] +.sym 17953 spi_if_ins.r_tx_byte[5] +.sym 17960 $PACKER_GND_NET +.sym 17961 spi_if_ins.r_tx_byte[7] +.sym 17964 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 17969 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 17972 i_glob_clock$SB_IO_IN +.sym 17973 w_rx_data[1] +.sym 17975 i_config[2]$SB_IO_IN +.sym 17976 w_rx_data[7] +.sym 17977 w_tx_data_io[7] +.sym 17978 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 17981 w_tx_data_io[5] +.sym 17988 i_glob_clock$SB_IO_IN +.sym 17989 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 17993 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 17995 w_tx_data_io[7] +.sym 17996 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 17997 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 17998 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 17999 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 18000 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18005 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 18006 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 18007 w_tx_data_io[5] +.sym 18009 w_fetch +.sym 18011 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 18013 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18015 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18016 i_rst_b$SB_IO_IN +.sym 18018 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 18019 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] +.sym 18021 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18022 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 18023 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18024 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 18028 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18029 w_tx_data_io[7] +.sym 18030 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 18033 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18034 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 18035 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18036 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 18039 w_fetch +.sym 18041 i_rst_b$SB_IO_IN +.sym 18045 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] +.sym 18047 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18048 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18052 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 18053 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 18054 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18057 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 18058 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 18059 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18060 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 18064 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 18065 w_tx_data_io[5] +.sym 18066 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 18067 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.sym 18068 i_glob_clock$SB_IO_IN +.sym 18072 o_led1_SB_DFFER_Q_E +.sym 18073 io_ctrl_ins.pmod_dir_state[0] +.sym 18075 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18094 o_tr_vc2$SB_IO_OUT +.sym 18097 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 18100 w_rx_data[4] +.sym 18103 w_rx_data[1] +.sym 18104 w_rx_data[3] +.sym 18114 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 18115 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18117 w_rx_data[2] +.sym 18119 w_cs[1] +.sym 18121 w_rx_data[5] +.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 18125 w_ioc[0] +.sym 18126 w_ioc[1] +.sym 18128 o_led1_SB_LUT4_I1_I2[3] +.sym 18129 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18137 w_rx_data[3] +.sym 18141 w_rx_data[6] +.sym 18145 w_rx_data[5] +.sym 18150 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 18152 w_ioc[0] +.sym 18153 w_ioc[1] +.sym 18157 w_rx_data[6] +.sym 18162 w_ioc[0] +.sym 18163 w_ioc[1] +.sym 18164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 18168 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 18169 o_led1_SB_LUT4_I1_I2[3] +.sym 18170 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18171 w_cs[1] +.sym 18181 w_rx_data[3] +.sym 18189 w_rx_data[2] +.sym 18190 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 18191 r_counter_$glb_clk -.sym 18194 r_tx_data[3] -.sym 18197 i_config_SB_LUT4_I0_2_O[3] -.sym 18199 i_config_SB_LUT4_I0_2_O[2] -.sym 18200 r_tx_data[0] -.sym 18201 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 18205 w_rx_data[0] -.sym 18209 io_ctrl_ins.pmod_dir_state[3] -.sym 18212 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18214 o_led1_SB_DFFER_Q_E -.sym 18235 w_cs[2] -.sym 18236 w_cs[3] -.sym 18237 w_cs[1] -.sym 18239 spi_if_ins.w_rx_data[5] -.sym 18241 i_rst_b$SB_IO_IN -.sym 18242 spi_if_ins.w_rx_data[6] -.sym 18243 w_cs[2] -.sym 18244 w_cs[0] -.sym 18245 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 18252 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 18261 w_cs[1] -.sym 18263 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 18267 w_cs[3] -.sym 18268 w_cs[0] -.sym 18269 w_cs[2] -.sym 18270 w_cs[1] -.sym 18274 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 18275 i_rst_b$SB_IO_IN -.sym 18279 w_cs[3] -.sym 18280 w_cs[1] -.sym 18281 w_cs[2] -.sym 18282 w_cs[0] -.sym 18285 spi_if_ins.w_rx_data[6] -.sym 18287 spi_if_ins.w_rx_data[5] -.sym 18291 w_cs[1] -.sym 18292 w_cs[2] -.sym 18293 w_cs[3] -.sym 18294 w_cs[0] -.sym 18297 w_cs[0] -.sym 18298 w_cs[2] -.sym 18299 w_cs[1] -.sym 18300 w_cs[3] -.sym 18313 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 18193 o_led1_SB_LUT4_I1_I2[1] +.sym 18194 io_ctrl_ins.pmod_dir_state[7] +.sym 18195 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 18196 i_config_SB_LUT4_I0_1_O[2] +.sym 18197 o_led1_SB_LUT4_I1_O[3] +.sym 18199 o_led0_SB_LUT4_I1_O[3] +.sym 18200 io_ctrl_ins.pmod_dir_state[1] +.sym 18205 w_cs[1] +.sym 18211 w_rx_data[0] +.sym 18212 o_rx_h_tx_l$SB_IO_OUT +.sym 18216 o_led1_SB_DFFER_Q_E +.sym 18234 io_ctrl_ins.pmod_dir_state[5] +.sym 18235 o_led1_SB_LUT4_I1_I2[3] +.sym 18236 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18237 o_led1_SB_LUT4_I1_I2[2] +.sym 18238 o_rx_h_tx_l$SB_IO_OUT +.sym 18240 o_tr_vc1$SB_IO_OUT +.sym 18242 i_config_SB_LUT4_I0_1_O[1] +.sym 18244 io_ctrl_ins.pmod_dir_state[6] +.sym 18246 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 18247 i_config[2]$SB_IO_IN +.sym 18248 i_button$SB_IO_IN +.sym 18249 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18251 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 18252 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 18254 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18256 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 18259 io_ctrl_ins.pmod_dir_state[7] +.sym 18260 w_ioc[0] +.sym 18263 i_config[3]$SB_IO_IN +.sym 18265 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 18268 w_ioc[0] +.sym 18269 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 18273 i_config_SB_LUT4_I0_1_O[1] +.sym 18274 io_ctrl_ins.pmod_dir_state[7] +.sym 18275 o_led1_SB_LUT4_I1_I2[2] +.sym 18276 o_rx_h_tx_l$SB_IO_OUT +.sym 18279 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18280 o_led1_SB_LUT4_I1_I2[3] +.sym 18281 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18285 i_button$SB_IO_IN +.sym 18286 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18287 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 18291 io_ctrl_ins.pmod_dir_state[5] +.sym 18292 i_config_SB_LUT4_I0_1_O[1] +.sym 18293 o_tr_vc1$SB_IO_OUT +.sym 18294 o_led1_SB_LUT4_I1_I2[2] +.sym 18298 i_config[2]$SB_IO_IN +.sym 18299 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 18300 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18303 i_config[3]$SB_IO_IN +.sym 18304 o_led1_SB_LUT4_I1_I2[2] +.sym 18305 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 18306 io_ctrl_ins.pmod_dir_state[6] +.sym 18310 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 18311 i_config_SB_LUT4_I0_1_O[1] +.sym 18312 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18313 io_ctrl_ins.o_data_out_SB_DFFE_Q_E .sym 18314 r_counter_$glb_clk -.sym 18315 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 18320 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 18336 o_led1_SB_LUT4_I1_I3[1] -.sym 18337 o_led1_SB_LUT4_I1_I2[2] -.sym 18338 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 18358 r_tx_data[2] -.sym 18359 r_tx_data[5] -.sym 18360 r_tx_data[7] -.sym 18361 r_tx_data[6] -.sym 18363 r_tx_data[4] -.sym 18364 r_tx_data[0] -.sym 18366 r_tx_data[3] -.sym 18368 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 18372 r_tx_data[1] -.sym 18392 r_tx_data[5] -.sym 18396 r_tx_data[2] -.sym 18402 r_tx_data[3] -.sym 18411 r_tx_data[6] -.sym 18414 r_tx_data[4] -.sym 18420 r_tx_data[0] -.sym 18429 r_tx_data[7] -.sym 18433 r_tx_data[1] -.sym 18436 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 18317 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 18318 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 18328 o_led0$SB_IO_OUT +.sym 18331 o_led1$SB_IO_OUT +.sym 18336 i_button$SB_IO_IN +.sym 18340 i_rst_b$SB_IO_IN +.sym 18341 i_config[1]$SB_IO_IN +.sym 18345 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18347 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 18358 io_ctrl_ins.rf_pin_state[7] +.sym 18359 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18360 io_ctrl_ins.rf_pin_state[5] +.sym 18361 io_ctrl_ins.rf_pin_state[1] +.sym 18364 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18365 io_ctrl_ins.rf_pin_state[4] +.sym 18366 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18367 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 18368 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18370 io_ctrl_ins.rf_pin_state[6] +.sym 18371 io_ctrl_ins.rf_pin_state[3] +.sym 18372 io_ctrl_ins.rf_pin_state[2] +.sym 18379 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18381 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18387 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18390 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18391 io_ctrl_ins.rf_pin_state[3] +.sym 18392 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18393 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18396 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18398 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18399 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18402 io_ctrl_ins.rf_pin_state[2] +.sym 18403 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 18404 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18409 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18410 io_ctrl_ins.rf_pin_state[4] +.sym 18411 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18414 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18415 io_ctrl_ins.rf_pin_state[7] +.sym 18417 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18421 io_ctrl_ins.rf_pin_state[1] +.sym 18422 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 18423 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18426 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18428 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18429 io_ctrl_ins.rf_pin_state[5] +.sym 18432 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18433 io_ctrl_ins.rf_pin_state[6] +.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 18436 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E .sym 18437 r_counter_$glb_clk -.sym 18453 o_tr_vc1_b$SB_IO_OUT -.sym 18467 i_config[1]$SB_IO_IN +.sym 18453 o_shdn_rx_lna$SB_IO_OUT +.sym 18459 o_tr_vc1_b$SB_IO_OUT +.sym 18464 o_shdn_tx_lna$SB_IO_OUT +.sym 18471 i_config[2]$SB_IO_IN +.sym 18480 w_rx_data[1] +.sym 18482 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 18483 w_rx_data[0] +.sym 18490 w_rx_data[3] +.sym 18503 w_rx_data[5] +.sym 18505 w_rx_data[6] +.sym 18507 w_rx_data[2] +.sym 18509 w_rx_data[4] +.sym 18511 w_rx_data[7] +.sym 18515 w_rx_data[4] +.sym 18522 w_rx_data[7] +.sym 18528 w_rx_data[0] +.sym 18533 w_rx_data[5] +.sym 18539 w_rx_data[1] +.sym 18546 w_rx_data[6] +.sym 18552 w_rx_data[3] +.sym 18556 w_rx_data[2] +.sym 18559 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.sym 18560 r_counter_$glb_clk .sym 18562 i_config[1]$SB_IO_IN .sym 18564 i_config[2]$SB_IO_IN -.sym 18587 i_config[2]$SB_IO_IN .sym 18636 w_smi_data_output[4] .sym 18638 w_smi_data_direction .sym 18642 $PACKER_VCC_NET -.sym 18647 $PACKER_VCC_NET -.sym 18653 w_smi_data_direction -.sym 18658 w_smi_data_output[4] -.sym 18662 w_rx_fifo_pulled_data[20] -.sym 18666 w_rx_fifo_pulled_data[22] -.sym 18691 w_smi_data_direction -.sym 18694 $PACKER_VCC_NET -.sym 18695 w_smi_data_input[7] -.sym 18696 w_smi_data_output[5] -.sym 18704 tx_fifo.wr_addr[6] -.sym 18705 tx_fifo.wr_addr[1] -.sym 18709 tx_fifo.wr_addr[4] -.sym 18713 tx_fifo.wr_addr[5] -.sym 18714 tx_fifo.wr_addr[3] -.sym 18715 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 18719 tx_fifo.wr_addr[0] -.sym 18727 tx_fifo.wr_addr[0] -.sym 18728 tx_fifo.wr_addr[7] -.sym 18735 $nextpnr_ICESTORM_LC_3$O -.sym 18737 tx_fifo.wr_addr[0] -.sym 18741 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 18743 tx_fifo.wr_addr[1] -.sym 18745 tx_fifo.wr_addr[0] -.sym 18747 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 18749 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 18751 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 18753 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18755 tx_fifo.wr_addr[3] -.sym 18757 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 18759 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 18762 tx_fifo.wr_addr[4] -.sym 18763 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18765 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 18768 tx_fifo.wr_addr[5] -.sym 18769 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 18771 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18773 tx_fifo.wr_addr[6] -.sym 18775 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 18777 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18779 tx_fifo.wr_addr[7] -.sym 18781 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 18647 w_smi_data_output[4] +.sym 18655 $PACKER_VCC_NET +.sym 18657 w_smi_data_direction +.sym 18679 $PACKER_VCC_NET +.sym 18695 i_mosi$SB_IO_IN +.sym 18706 tx_fifo.wr_addr[6] +.sym 18707 tx_fifo.wr_addr[4] +.sym 18708 tx_fifo.wr_addr[7] +.sym 18712 tx_fifo.wr_addr[5] +.sym 18713 tx_fifo.wr_addr[8] +.sym 18715 tx_fifo.wr_addr[3] +.sym 18717 tx_fifo.wr_addr[2] +.sym 18726 tx_fifo.wr_addr[1] +.sym 18734 tx_fifo.wr_addr[1] +.sym 18735 $nextpnr_ICESTORM_LC_1$O +.sym 18737 tx_fifo.wr_addr[1] +.sym 18741 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 18744 tx_fifo.wr_addr[2] +.sym 18745 tx_fifo.wr_addr[1] +.sym 18747 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18749 tx_fifo.wr_addr[3] +.sym 18751 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 18753 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 18755 tx_fifo.wr_addr[4] +.sym 18757 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 18759 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18762 tx_fifo.wr_addr[5] +.sym 18763 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 18765 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 18768 tx_fifo.wr_addr[6] +.sym 18769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 18771 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 18773 tx_fifo.wr_addr[7] +.sym 18775 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 18777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 +.sym 18780 tx_fifo.wr_addr[8] +.sym 18781 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18790 w_rx_fifo_pulled_data[21] -.sym 18794 w_rx_fifo_pulled_data[23] -.sym 18801 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 18802 tx_fifo.wr_addr[6] -.sym 18804 rx_fifo.wr_addr[9] -.sym 18805 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18806 rx_fifo.wr_addr[8] -.sym 18807 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 18809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 18810 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 18812 $PACKER_VCC_NET -.sym 18814 rx_fifo.wr_addr[4] -.sym 18818 rx_fifo.wr_addr[0] -.sym 18824 rx_fifo.wr_addr[3] -.sym 18831 i_sck$SB_IO_IN -.sym 18832 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 18833 rx_fifo.rd_addr[8] -.sym 18837 rx_fifo.rd_addr[1] -.sym 18841 rx_fifo.wr_addr[1] -.sym 18843 rx_fifo.rd_addr[6] -.sym 18844 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 18845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18846 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 18850 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 18851 tx_fifo.wr_addr[8] -.sym 18852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18853 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18855 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 18859 w_smi_data_direction -.sym 18861 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18867 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 18872 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18873 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 18876 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 18877 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 18878 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 18879 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 18880 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18889 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 18891 tx_fifo.wr_addr[8] -.sym 18894 tx_fifo.wr_addr[9] -.sym 18898 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 18901 tx_fifo.wr_addr[8] -.sym 18902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18905 tx_fifo.wr_addr[9] -.sym 18908 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 18912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18918 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 18924 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 18929 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 18930 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18931 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 18938 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 18941 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18944 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 18818 $PACKER_VCC_NET +.sym 18831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 18835 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 18838 $PACKER_VCC_NET +.sym 18841 w_smi_data_output[5] +.sym 18842 w_smi_data_direction +.sym 18843 rx_fifo.wr_addr[6] +.sym 18844 w_smi_data_input[7] +.sym 18848 i_smi_soe_se$SB_IO_IN +.sym 18849 rx_fifo.wr_addr[1] +.sym 18850 rx_fifo.wr_addr[3] +.sym 18853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 18854 rx_fifo.wr_addr[4] +.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 18861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 +.sym 18868 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 18872 tx_fifo.wr_addr[9] +.sym 18874 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18881 tx_fifo.wr_addr[0] +.sym 18884 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18885 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 18887 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 18888 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 18889 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 18899 tx_fifo.wr_addr[9] +.sym 18902 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 +.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 18914 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 18931 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 18937 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 18942 tx_fifo.wr_addr[0] +.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 18946 r_counter_$glb_clk .sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 18949 w_rx_fifo_pulled_data[28] -.sym 18953 w_rx_fifo_pulled_data[30] -.sym 18960 rx_fifo.rd_addr[7] -.sym 18962 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 18964 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 18968 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 18970 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 18973 tx_fifo.wr_addr[1] -.sym 18974 rx_fifo.rd_addr[2] -.sym 18975 rx_fifo.rd_addr[1] -.sym 18976 rx_fifo.wr_addr[4] -.sym 18978 rx_fifo.wr_addr[3] -.sym 18981 w_smi_data_direction -.sym 18982 rx_fifo.rd_addr[0] -.sym 18983 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 18991 tx_fifo.wr_addr[1] -.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 18995 tx_fifo.wr_addr[6] -.sym 18999 tx_fifo.wr_addr[7] -.sym 19000 tx_fifo.wr_addr[3] -.sym 19001 tx_fifo.wr_addr[5] -.sym 19003 tx_fifo.wr_addr[4] -.sym 19016 tx_fifo.wr_addr[8] -.sym 19021 $nextpnr_ICESTORM_LC_8$O -.sym 19024 tx_fifo.wr_addr[1] -.sym 19027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 19031 tx_fifo.wr_addr[1] -.sym 19033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19036 tx_fifo.wr_addr[3] -.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19042 tx_fifo.wr_addr[4] -.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19045 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19047 tx_fifo.wr_addr[5] -.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19051 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19053 tx_fifo.wr_addr[6] -.sym 19055 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19057 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 19059 tx_fifo.wr_addr[7] -.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 19063 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 19065 tx_fifo.wr_addr[8] -.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 19072 w_rx_fifo_pulled_data[29] -.sym 19076 w_rx_fifo_pulled_data[31] -.sym 19082 w_fetch -.sym 19084 o_smi_read_req$SB_IO_OUT -.sym 19089 rx_fifo.wr_addr[5] -.sym 19090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 19092 w_rx_fifo_pulled_data[28] -.sym 19093 $PACKER_VCC_NET -.sym 19094 rx_fifo.wr_addr[9] -.sym 19098 w_rx_fifo_pulled_data[31] -.sym 19103 tx_fifo.wr_addr[9] -.sym 19104 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19106 w_rx_fifo_pulled_data[29] -.sym 19107 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 19113 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 19114 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19115 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19116 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19117 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 19119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19121 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 19122 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 19124 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 19125 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19126 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19128 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19129 tx_fifo.wr_addr[9] -.sym 19130 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 19132 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -.sym 19137 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] -.sym 19146 tx_fifo.wr_addr[9] -.sym 19148 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 19151 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19153 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19157 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19166 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19169 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 19170 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 19172 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19175 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 19176 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] -.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19178 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19183 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19187 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 19188 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19189 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19190 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -.sym 19191 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 19192 r_counter_$glb_clk -.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19206 rx_fifo.mem_i.0.3_WDATA -.sym 19212 tx_fifo.wr_addr[8] -.sym 19214 w_smi_data_output[5] -.sym 19215 smi_ctrl_ins.w_fifo_push_trigger -.sym 19221 rx_fifo.wr_addr[1] -.sym 19222 rx_fifo.rd_addr[9] -.sym 19223 i_sck$SB_IO_IN -.sym 19224 rx_fifo.rd_addr[8] -.sym 19227 rx_fifo.rd_addr[4] -.sym 19229 rx_fifo.mem_i.0.3_WDATA_1 -.sym 19235 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19238 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 19239 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 19240 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] -.sym 19243 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 19245 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19246 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 19247 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 19249 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19250 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] -.sym 19251 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19252 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 19253 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19255 tx_fifo.rd_addr_gray[0] -.sym 19256 tx_fifo.rd_addr_gray_wr[3] -.sym 19258 tx_fifo.rd_addr_gray[7] -.sym 19259 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19264 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19268 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] -.sym 19269 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] -.sym 19274 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 19275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19276 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19277 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19283 tx_fifo.rd_addr_gray_wr[3] -.sym 19286 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19287 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19288 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19289 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19292 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19293 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 19294 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 19299 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 19300 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 19301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 19304 tx_fifo.rd_addr_gray[0] -.sym 19310 tx_fifo.rd_addr_gray[7] -.sym 19315 r_counter_$glb_clk -.sym 19328 w_smi_data_direction -.sym 19331 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 19339 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 19342 tx_fifo.rd_addr_gray_wr[3] -.sym 19350 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19352 tx_fifo.rd_addr_gray_wr[7] -.sym 19362 i_ss$SB_IO_IN -.sym 19363 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19367 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19368 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19380 w_rx_fifo_empty -.sym 19382 w_smi_data_direction -.sym 19383 i_sck$SB_IO_IN -.sym 19386 w_tx_fifo_full -.sym 19387 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19390 $nextpnr_ICESTORM_LC_2$O -.sym 19392 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19396 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 19398 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19400 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19404 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19406 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 19409 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19410 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19411 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19412 i_ss$SB_IO_IN -.sym 19423 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19427 w_rx_fifo_empty -.sym 19428 w_tx_fifo_full -.sym 19430 w_smi_data_direction -.sym 19438 i_sck$SB_IO_IN -.sym 19439 i_ss$SB_IO_IN -.sym 19464 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19468 w_smi_data_direction -.sym 19472 w_tx_fifo_full -.sym 19482 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19483 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19486 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19488 tx_fifo.rd_addr_gray_wr[9] -.sym 19492 tx_fifo.rd_addr_gray_wr[8] -.sym 19494 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19502 tx_fifo.rd_addr_gray[8] -.sym 19503 tx_fifo.rd_addr[9] -.sym 19505 tx_fifo.rd_addr_gray[3] -.sym 19512 tx_fifo.rd_addr_gray_wr[7] -.sym 19514 tx_fifo.rd_addr_gray_wr[8] -.sym 19523 tx_fifo.rd_addr_gray_wr[7] -.sym 19529 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19532 tx_fifo.rd_addr_gray[8] -.sym 19539 tx_fifo.rd_addr_gray_wr[9] -.sym 19545 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19546 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19547 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19551 tx_fifo.rd_addr_gray[3] -.sym 19559 tx_fifo.rd_addr[9] -.sym 19561 r_counter_$glb_clk -.sym 19582 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19595 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 19615 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 19616 i_ss$SB_IO_IN -.sym 19618 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 19621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 19631 spi_if_ins.r_tx_data_valid -.sym 19633 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 19669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 19675 spi_if_ins.r_tx_data_valid -.sym 19676 i_ss$SB_IO_IN -.sym 19681 i_ss$SB_IO_IN -.sym 19682 spi_if_ins.r_tx_data_valid -.sym 19683 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 18949 w_rx_fifo_pulled_data[16] +.sym 18953 w_rx_fifo_pulled_data[18] +.sym 18960 i_ss$SB_IO_IN +.sym 18964 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 18973 rx_fifo.wr_addr[0] +.sym 18976 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 18977 w_smi_data_input[7] +.sym 18978 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 18990 tx_fifo.rd_addr_gray_wr[2] +.sym 18992 tx_fifo.rd_addr_gray_wr[4] +.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 18997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 18998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 19002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 19004 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 19005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 19008 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 19012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] +.sym 19015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 19017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 19018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 19020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 19023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 19024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 19031 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 19049 tx_fifo.rd_addr_gray_wr[4] +.sym 19052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 19055 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] +.sym 19058 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 19060 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 19061 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 19064 tx_fifo.rd_addr_gray_wr[2] +.sym 19069 r_counter_$glb_clk +.sym 19072 w_rx_fifo_pulled_data[17] +.sym 19076 w_rx_fifo_pulled_data[19] +.sym 19084 tx_fifo.rd_addr_gray_wr[2] +.sym 19091 rx_fifo.mem_i.0.0_WDATA_2 +.sym 19097 rx_fifo.wr_addr[7] +.sym 19098 w_rx_fifo_pulled_data[19] +.sym 19101 w_rx_fifo_pulled_data[18] +.sym 19103 $PACKER_VCC_NET +.sym 19106 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19112 i_sck$SB_IO_IN +.sym 19116 i_ss$SB_IO_IN +.sym 19117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 19118 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 19119 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 19120 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 19121 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 19134 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19137 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19138 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] +.sym 19144 $nextpnr_ICESTORM_LC_2$O +.sym 19147 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19150 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 19152 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19154 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19158 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19160 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 19163 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 19165 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] +.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 19178 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 19183 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 19188 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 19189 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 19192 i_sck$SB_IO_IN +.sym 19193 i_ss$SB_IO_IN +.sym 19195 w_rx_fifo_pulled_data[4] +.sym 19199 w_rx_fifo_pulled_data[6] +.sym 19206 i_mosi$SB_IO_IN +.sym 19207 rx_fifo.rd_addr[6] +.sym 19211 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 19213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 19215 rx_fifo.rd_addr[0] +.sym 19219 rx_fifo.wr_addr[9] +.sym 19221 rx_fifo.rd_addr[3] +.sym 19223 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 19224 $PACKER_VCC_NET +.sym 19225 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19226 $PACKER_VCC_NET +.sym 19227 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 19228 w_smi_data_direction +.sym 19244 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19245 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19248 i_ss$SB_IO_IN +.sym 19249 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19260 w_rx_fifo_pulled_data[5] +.sym 19264 w_rx_fifo_pulled_data[7] +.sym 19280 w_rx_fifo_pulled_data[7] +.sym 19286 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19287 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19288 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19298 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19299 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19300 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19301 i_ss$SB_IO_IN +.sym 19304 w_rx_fifo_pulled_data[5] +.sym 19314 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 19315 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 19316 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 19318 w_rx_fifo_pulled_data[5] +.sym 19322 w_rx_fifo_pulled_data[7] +.sym 19337 o_smi_read_req$SB_IO_OUT +.sym 19341 rx_fifo.wr_addr[1] +.sym 19342 rx_fifo.wr_addr[5] +.sym 19343 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 19344 rx_fifo.wr_addr[8] +.sym 19345 i_smi_soe_se$SB_IO_IN +.sym 19346 rx_fifo.wr_addr[3] +.sym 19347 rx_fifo.wr_addr[1] +.sym 19350 rx_fifo.wr_addr[2] +.sym 19352 rx_fifo.wr_addr[3] +.sym 19359 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19366 i_ss$SB_IO_IN +.sym 19369 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19397 i_ss$SB_IO_IN +.sym 19400 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19411 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19438 r_counter_$glb_clk +.sym 19441 w_rx_fifo_pulled_data[28] +.sym 19445 w_rx_fifo_pulled_data[30] +.sym 19452 $PACKER_VCC_NET +.sym 19459 rx_fifo.rd_addr[8] +.sym 19463 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19464 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 19466 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 19467 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19468 rx_fifo.rd_addr[9] +.sym 19472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 19473 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 19481 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19483 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19485 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19486 i_mosi$SB_IO_IN +.sym 19487 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19489 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19490 i_sck$SB_IO_IN +.sym 19493 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19495 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19508 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19517 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19522 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19528 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19532 i_mosi$SB_IO_IN +.sym 19541 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19545 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19550 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19557 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19560 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19561 i_sck$SB_IO_IN +.sym 19564 w_rx_fifo_pulled_data[29] +.sym 19568 w_rx_fifo_pulled_data[31] +.sym 19575 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19579 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19581 rx_fifo.wr_addr[6] +.sym 19585 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19594 $PACKER_VCC_NET +.sym 19598 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 19604 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 19606 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 19608 i_rst_b$SB_IO_IN +.sym 19611 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 19612 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 19613 spi_if_ins.state_if[0] +.sym 19615 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 19617 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19618 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19623 spi_if_ins.state_if[1] +.sym 19625 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19627 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 19631 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 19632 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 19638 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19640 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19645 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 19649 spi_if_ins.state_if[0] +.sym 19650 spi_if_ins.state_if[1] +.sym 19655 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 19657 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19658 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 19661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 19663 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 19664 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19667 spi_if_ins.state_if[1] +.sym 19668 spi_if_ins.state_if[0] +.sym 19669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 19673 i_rst_b$SB_IO_IN +.sym 19674 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 19675 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19676 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 19679 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 19683 spi_if_ins.state_if_SB_DFFESR_Q_E .sym 19684 r_counter_$glb_clk -.sym 19685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19714 w_fetch -.sym 19731 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 19735 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19740 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 19742 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 19745 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 19748 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19749 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 19751 i_rst_b$SB_IO_IN -.sym 19791 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 19797 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19802 i_rst_b$SB_IO_IN -.sym 19803 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 19804 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 19805 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 19806 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 19685 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 19698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 19700 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 19702 rx_fifo.rd_addr[6] +.sym 19704 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 19706 rx_fifo.rd_addr[3] +.sym 19710 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 19719 w_smi_data_direction +.sym 19720 $PACKER_VCC_NET +.sym 19721 rx_fifo.mem_i.0.3_WDATA +.sym 19729 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 19730 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19731 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19732 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 19734 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19740 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19742 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 19746 i_rst_b$SB_IO_IN +.sym 19750 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 19752 $PACKER_VCC_NET +.sym 19753 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 19754 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 19756 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19757 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19759 $nextpnr_ICESTORM_LC_9$O +.sym 19761 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19765 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 19767 $PACKER_VCC_NET +.sym 19768 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19773 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 19774 $PACKER_VCC_NET +.sym 19775 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 19778 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 19779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 19780 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 19781 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 19784 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 19785 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 19787 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 19791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 19792 i_rst_b$SB_IO_IN +.sym 19796 $PACKER_VCC_NET +.sym 19797 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19799 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19804 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19806 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 19807 r_counter_$glb_clk -.sym 19808 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 19823 spi_if_ins.w_rx_data[0] -.sym 19831 spi_if_ins.w_rx_data[5] -.sym 19834 o_led1_SB_LUT4_I1_I2[0] -.sym 19838 o_led0_SB_LUT4_I1_O[0] -.sym 19840 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 19850 w_rx_data[2] -.sym 19861 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 19862 w_rx_data[0] -.sym 19890 w_rx_data[2] -.sym 19910 w_rx_data[0] -.sym 19929 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19821 w_fetch +.sym 19826 w_load +.sym 19835 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19836 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 19837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19838 i_glob_clock$SB_IO_IN +.sym 19852 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 19854 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 19856 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19857 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19858 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 19859 spi_if_ins.spi.r_tx_byte[6] +.sym 19860 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 19861 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19862 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 19863 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19864 spi_if_ins.spi.r_tx_byte[4] +.sym 19865 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 19868 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 19869 spi_if_ins.spi.r_tx_byte[5] +.sym 19870 spi_if_ins.r_tx_byte[5] +.sym 19871 spi_if_ins.r_tx_byte[7] +.sym 19872 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 19874 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 19875 spi_if_ins.spi.r_tx_byte[7] +.sym 19883 spi_if_ins.spi.r_tx_byte[7] +.sym 19884 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19885 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19886 spi_if_ins.spi.r_tx_byte[5] +.sym 19889 spi_if_ins.r_tx_byte[7] +.sym 19895 spi_if_ins.spi.r_tx_byte[6] +.sym 19896 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19897 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19898 spi_if_ins.spi.r_tx_byte[4] +.sym 19904 spi_if_ins.r_tx_byte[5] +.sym 19907 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 19908 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 19909 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 19910 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 19913 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 19914 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19916 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 19920 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 19921 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19922 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19925 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 19926 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 19928 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 19929 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 19930 r_counter_$glb_clk -.sym 19931 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19944 w_rx_data[3] -.sym 19948 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 19954 w_rx_data[2] -.sym 19956 io_pmod[3]$SB_IO_IN -.sym 19958 o_led0$SB_IO_OUT -.sym 19960 o_led1_SB_LUT4_I1_I2[0] -.sym 19962 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 19964 w_smi_data_direction -.sym 19966 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 19974 w_rx_data[2] -.sym 19976 w_rx_data[1] -.sym 19977 i_button_SB_LUT4_I0_O[1] -.sym 19979 w_rx_data[4] -.sym 19982 w_load -.sym 19985 w_fetch -.sym 19991 w_cs[1] -.sym 19992 w_rx_data[3] -.sym 19995 w_rx_data[0] -.sym 19999 o_led0_SB_LUT4_I1_O[1] -.sym 20000 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E -.sym 20001 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20006 w_rx_data[0] -.sym 20014 w_rx_data[3] -.sym 20018 i_button_SB_LUT4_I0_O[1] -.sym 20019 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20024 w_fetch -.sym 20025 w_load -.sym 20026 o_led0_SB_LUT4_I1_O[1] -.sym 20027 w_cs[1] -.sym 20031 w_rx_data[1] -.sym 20044 w_rx_data[4] -.sym 20050 w_rx_data[2] -.sym 20052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E +.sym 19931 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19944 i_glob_clock$SB_IO_IN +.sym 19946 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 19954 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 19974 spi_if_ins.r_tx_byte[2] +.sym 19975 spi_if_ins.r_tx_byte[4] +.sym 19978 spi_if_ins.r_tx_byte[3] +.sym 19980 spi_if_ins.r_tx_byte[6] +.sym 19983 spi_if_ins.r_tx_byte[1] +.sym 19984 spi_if_ins.spi.r_tx_byte[0] +.sym 19985 spi_if_ins.r_tx_byte[0] +.sym 19986 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 19987 spi_if_ins.spi.r_tx_bit_count[0] +.sym 19999 spi_if_ins.spi.r_tx_byte[2] +.sym 20000 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 20002 spi_if_ins.spi.r_tx_byte[1] +.sym 20004 spi_if_ins.spi.r_tx_byte[3] +.sym 20006 spi_if_ins.spi.r_tx_byte[0] +.sym 20008 spi_if_ins.spi.r_tx_byte[1] +.sym 20009 spi_if_ins.spi.r_tx_bit_count[0] +.sym 20014 spi_if_ins.r_tx_byte[6] +.sym 20019 spi_if_ins.r_tx_byte[2] +.sym 20026 spi_if_ins.r_tx_byte[0] +.sym 20031 spi_if_ins.spi.r_tx_byte[2] +.sym 20032 spi_if_ins.spi.r_tx_byte[3] +.sym 20033 spi_if_ins.spi.r_tx_bit_count[0] +.sym 20038 spi_if_ins.r_tx_byte[1] +.sym 20042 spi_if_ins.r_tx_byte[4] +.sym 20048 spi_if_ins.r_tx_byte[3] +.sym 20052 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 20053 r_counter_$glb_clk -.sym 20054 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 20067 o_led0_SB_LUT4_I1_O[0] -.sym 20069 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 20071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 20078 io_pmod[1]$SB_IO_IN -.sym 20080 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 20081 w_rx_data[0] -.sym 20084 i_config[0]$SB_IO_IN -.sym 20088 o_led1_SB_LUT4_I1_I2[0] -.sym 20089 w_tx_data_io[1] -.sym 20096 o_led0_SB_LUT4_I1_O[0] -.sym 20097 io_ctrl_ins.pmod_dir_state[0] -.sym 20098 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20099 o_led1_SB_LUT4_I1_O[3] -.sym 20100 o_led1_SB_LUT4_I1_O[0] -.sym 20101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 20102 o_shdn_rx_lna$SB_IO_OUT -.sym 20103 o_led1_SB_LUT4_I1_I2[1] -.sym 20105 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 20106 o_tr_vc2$SB_IO_OUT -.sym 20107 o_led1_SB_LUT4_I1_I3[3] -.sym 20109 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20110 o_led0_SB_LUT4_I1_O[2] -.sym 20111 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20114 o_led0_SB_LUT4_I1_O[1] -.sym 20115 o_led1_SB_LUT4_I1_O[2] -.sym 20116 io_pmod[3]$SB_IO_IN -.sym 20117 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20118 o_led0$SB_IO_OUT -.sym 20122 o_led0_SB_LUT4_I1_O[1] -.sym 20123 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 20124 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20126 io_pmod[1]$SB_IO_IN -.sym 20127 o_led0_SB_LUT4_I1_O[3] -.sym 20130 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 20132 o_led1_SB_LUT4_I1_I2[1] -.sym 20135 o_led1_SB_LUT4_I1_O[2] -.sym 20136 o_led0_SB_LUT4_I1_O[1] -.sym 20137 o_led1_SB_LUT4_I1_O[3] -.sym 20138 o_led1_SB_LUT4_I1_O[0] -.sym 20141 o_led0_SB_LUT4_I1_O[3] -.sym 20142 o_led0_SB_LUT4_I1_O[2] -.sym 20143 o_led0_SB_LUT4_I1_O[0] -.sym 20144 o_led0_SB_LUT4_I1_O[1] -.sym 20147 io_pmod[1]$SB_IO_IN -.sym 20148 o_shdn_rx_lna$SB_IO_OUT -.sym 20149 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20150 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20153 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20154 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20159 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 20160 io_pmod[3]$SB_IO_IN -.sym 20161 o_tr_vc2$SB_IO_OUT -.sym 20162 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20165 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 20166 o_led0_SB_LUT4_I1_O[1] -.sym 20167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 20168 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 20171 o_led1_SB_LUT4_I1_I2[1] -.sym 20172 o_led0$SB_IO_OUT -.sym 20173 io_ctrl_ins.pmod_dir_state[0] -.sym 20174 o_led1_SB_LUT4_I1_I3[3] -.sym 20175 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20054 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 20075 o_tr_vc2$SB_IO_OUT +.sym 20098 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 20100 r_tx_data[5] +.sym 20102 r_tx_data[4] +.sym 20106 r_tx_data[3] +.sym 20141 r_tx_data[4] +.sym 20159 r_tx_data[3] +.sym 20167 r_tx_data[5] +.sym 20175 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O .sym 20176 r_counter_$glb_clk -.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20187 io_ctrl_ins.pmod_dir_state[0] -.sym 20190 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 20192 o_tr_vc2$SB_IO_OUT -.sym 20198 o_shdn_rx_lna$SB_IO_OUT -.sym 20200 io_ctrl_ins.rf_pin_state[2] -.sym 20206 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20210 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20211 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 20219 w_load -.sym 20224 w_rx_data[0] -.sym 20226 io_ctrl_ins.pmod_dir_state[3] -.sym 20230 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 20233 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20236 o_led1$SB_IO_OUT -.sym 20237 io_ctrl_ins.pmod_dir_state[1] -.sym 20238 w_cs[1] -.sym 20239 w_fetch -.sym 20240 i_rst_b$SB_IO_IN -.sym 20242 o_led1_SB_LUT4_I1_I2[1] -.sym 20244 i_config[0]$SB_IO_IN -.sym 20246 o_led1_SB_LUT4_I1_I3[3] -.sym 20252 o_led1_SB_LUT4_I1_I3[3] -.sym 20255 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20258 w_cs[1] -.sym 20259 w_load -.sym 20260 o_led1_SB_LUT4_I1_I2[1] -.sym 20261 w_fetch -.sym 20270 o_led1$SB_IO_OUT -.sym 20271 io_ctrl_ins.pmod_dir_state[1] -.sym 20272 o_led1_SB_LUT4_I1_I2[1] -.sym 20273 o_led1_SB_LUT4_I1_I3[3] -.sym 20277 w_rx_data[0] -.sym 20288 w_fetch -.sym 20289 i_rst_b$SB_IO_IN -.sym 20290 w_load -.sym 20291 w_cs[1] -.sym 20294 io_ctrl_ins.pmod_dir_state[3] -.sym 20295 i_config[0]$SB_IO_IN -.sym 20296 o_led1_SB_LUT4_I1_I2[1] -.sym 20297 o_led1_SB_LUT4_I1_I3[3] -.sym 20298 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 20206 w_smi_data_direction +.sym 20220 w_rx_data[0] +.sym 20221 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20222 o_led1_SB_LUT4_I1_I2[2] +.sym 20224 w_cs[1] +.sym 20227 w_fetch +.sym 20228 o_led1_SB_LUT4_I1_I2[3] +.sym 20230 w_load +.sym 20246 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20264 w_load +.sym 20265 w_cs[1] +.sym 20266 o_led1_SB_LUT4_I1_I2[3] +.sym 20267 w_fetch +.sym 20270 w_rx_data[0] +.sym 20283 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20284 o_led1_SB_LUT4_I1_I2[2] +.sym 20298 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O .sym 20299 r_counter_$glb_clk -.sym 20300 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 20314 io_ctrl_ins.rf_pin_state[5] -.sym 20318 io_ctrl_ins.rf_pin_state[7] -.sym 20342 i_glob_clock$SB_IO_IN -.sym 20344 i_config[1]$SB_IO_IN -.sym 20345 o_led1_SB_LUT4_I1_I3[1] -.sym 20346 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 20347 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 20349 o_led1_SB_LUT4_I1_I3[3] -.sym 20350 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 20352 o_led1_SB_LUT4_I1_I2[2] -.sym 20353 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 20355 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 20357 o_led1_SB_LUT4_I1_I2[1] -.sym 20358 o_led1_SB_LUT4_I1_I2[0] -.sym 20367 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 20368 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 20371 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 20381 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 20382 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 20383 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 20384 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 20399 o_led1_SB_LUT4_I1_I2[1] -.sym 20400 o_led1_SB_LUT4_I1_I2[2] -.sym 20401 o_led1_SB_LUT4_I1_I2[0] -.sym 20411 o_led1_SB_LUT4_I1_I2[1] -.sym 20412 o_led1_SB_LUT4_I1_I3[3] -.sym 20413 i_config[1]$SB_IO_IN -.sym 20414 o_led1_SB_LUT4_I1_I3[1] -.sym 20417 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 20418 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 20419 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 20420 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 20421 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 20422 i_glob_clock$SB_IO_IN -.sym 20436 i_glob_clock$SB_IO_IN -.sym 20438 i_config[1]$SB_IO_IN -.sym 20451 o_led1$SB_IO_OUT -.sym 20476 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 20477 i_config_SB_LUT4_I0_2_O[3] -.sym 20478 i_button_SB_LUT4_I0_O[1] -.sym 20479 i_config_SB_LUT4_I0_2_O[2] -.sym 20480 o_tr_vc1_b$SB_IO_OUT -.sym 20522 i_button_SB_LUT4_I0_O[1] -.sym 20523 i_config_SB_LUT4_I0_2_O[3] -.sym 20524 o_tr_vc1_b$SB_IO_OUT -.sym 20525 i_config_SB_LUT4_I0_2_O[2] -.sym 20544 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20315 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20326 i_glob_clock$SB_IO_IN +.sym 20344 w_rx_data[4] +.sym 20347 w_rx_data[1] +.sym 20348 o_led1$SB_IO_OUT +.sym 20353 io_ctrl_ins.pmod_dir_state[0] +.sym 20354 w_rx_data[7] +.sym 20355 o_led0$SB_IO_OUT +.sym 20357 io_ctrl_ins.pmod_dir_state[1] +.sym 20358 o_led1_SB_LUT4_I1_I2[1] +.sym 20359 o_led1_SB_LUT4_I1_I2[3] +.sym 20361 o_led1_SB_LUT4_I1_I2[2] +.sym 20362 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 20369 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20371 i_config[1]$SB_IO_IN +.sym 20377 w_rx_data[4] +.sym 20381 w_rx_data[7] +.sym 20389 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 20393 o_led1_SB_LUT4_I1_I2[3] +.sym 20394 i_config[1]$SB_IO_IN +.sym 20395 o_led1_SB_LUT4_I1_I2[2] +.sym 20396 o_led1_SB_LUT4_I1_I2[1] +.sym 20399 io_ctrl_ins.pmod_dir_state[1] +.sym 20400 o_led1_SB_LUT4_I1_I2[3] +.sym 20401 o_led1$SB_IO_OUT +.sym 20402 o_led1_SB_LUT4_I1_I2[2] +.sym 20411 o_led0$SB_IO_OUT +.sym 20412 o_led1_SB_LUT4_I1_I2[2] +.sym 20413 io_ctrl_ins.pmod_dir_state[0] +.sym 20414 o_led1_SB_LUT4_I1_I2[3] +.sym 20417 w_rx_data[1] +.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.sym 20422 r_counter_$glb_clk +.sym 20448 o_led1$SB_IO_OUT +.sym 20468 i_config_SB_LUT4_I0_1_O[2] +.sym 20476 o_tr_vc1_b$SB_IO_OUT +.sym 20481 i_config_SB_LUT4_I0_1_O[1] +.sym 20483 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 20485 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20491 i_config_SB_LUT4_I0_1_O[3] +.sym 20504 i_config_SB_LUT4_I0_1_O[2] +.sym 20505 i_config_SB_LUT4_I0_1_O[1] +.sym 20506 i_config_SB_LUT4_I0_1_O[3] +.sym 20507 o_tr_vc1_b$SB_IO_OUT +.sym 20510 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20512 i_config_SB_LUT4_I0_1_O[1] +.sym 20544 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] .sym 20545 r_counter_$glb_clk -.sym 20569 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] .sym 20571 i_config[0]$SB_IO_IN .sym 20672 i_config[0]$SB_IO_IN .sym 20748 w_smi_data_output[5] .sym 20750 w_smi_data_direction .sym 20751 $PACKER_VCC_NET -.sym 20754 w_smi_data_direction -.sym 20759 $PACKER_VCC_NET -.sym 20761 w_smi_data_output[5] -.sym 20771 tx_fifo.rd_addr_gray_wr[4] -.sym 20773 i_smi_soe_se$SB_IO_IN -.sym 20774 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 20782 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 20786 rx_fifo.wr_addr[6] -.sym 20802 i_sck$SB_IO_IN -.sym 20804 w_smi_data_input[7] -.sym 20810 rx_fifo.mem_i.0.1_WDATA_3 -.sym 20812 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 20813 rx_fifo.wr_addr[3] -.sym 20814 $PACKER_VCC_NET -.sym 20815 rx_fifo.wr_addr[0] -.sym 20816 rx_fifo.wr_addr[8] -.sym 20819 rx_fifo.wr_addr[4] -.sym 20824 rx_fifo.wr_addr[9] -.sym 20826 rx_fifo.wr_addr[6] -.sym 20828 rx_fifo.wr_addr[1] -.sym 20829 rx_fifo.wr_addr[7] -.sym 20830 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 20832 rx_fifo.mem_i.0.1_WDATA_2 -.sym 20840 rx_fifo.wr_addr[5] +.sym 20764 w_smi_data_output[5] +.sym 20765 w_smi_data_direction +.sym 20767 $PACKER_VCC_NET +.sym 20772 tx_fifo.wr_addr[4] .sym 20844 i_mosi$SB_IO_IN -.sym 20847 tx_fifo.rd_addr_gray[2] -.sym 20848 tx_fifo.rd_addr[7] -.sym 20849 tx_fifo.rd_addr_gray[6] -.sym 20850 tx_fifo.rd_addr_gray[4] -.sym 20851 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 20852 tx_fifo.rd_addr_gray[5] -.sym 20862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 20863 rx_fifo.wr_addr[3] -.sym 20865 rx_fifo.wr_addr[4] -.sym 20866 rx_fifo.wr_addr[5] -.sym 20867 rx_fifo.wr_addr[6] -.sym 20868 rx_fifo.wr_addr[7] -.sym 20869 rx_fifo.wr_addr[8] -.sym 20870 rx_fifo.wr_addr[9] -.sym 20871 rx_fifo.wr_addr[1] -.sym 20872 rx_fifo.wr_addr[0] -.sym 20873 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 20874 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 20876 rx_fifo.mem_i.0.1_WDATA_3 -.sym 20880 rx_fifo.mem_i.0.1_WDATA_2 -.sym 20883 $PACKER_VCC_NET -.sym 20898 rx_fifo.mem_i.0.1_WDATA_3 -.sym 20906 rx_fifo.mem_i.0.1_WDATA_2 -.sym 20915 rx_fifo.wr_addr[5] -.sym 20918 $PACKER_VCC_NET -.sym 20922 rx_fifo.rd_addr[3] -.sym 20926 rx_fifo.rd_addr[4] -.sym 20928 o_miso_$_TBUF__Y_E -.sym 20929 rx_fifo.wr_addr[7] -.sym 20932 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 20933 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 20938 int_miso -.sym 20939 i_mosi$SB_IO_IN -.sym 20942 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 20957 rx_fifo.rd_addr[7] -.sym 20958 rx_fifo.rd_addr[8] -.sym 20963 rx_fifo.rd_addr[1] -.sym 20966 rx_fifo.rd_addr[9] -.sym 20968 rx_fifo.mem_i.0.1_WDATA -.sym 20970 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 20972 $PACKER_VCC_NET -.sym 20974 rx_fifo.rd_addr[2] -.sym 20976 rx_fifo.rd_addr[3] -.sym 20977 rx_fifo.rd_addr[6] -.sym 20978 rx_fifo.rd_addr[5] -.sym 20979 rx_fifo.mem_i.0.1_WDATA_1 -.sym 20981 rx_fifo.rd_addr[4] -.sym 20982 rx_fifo.rd_addr[0] -.sym 20984 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 20985 tx_fifo.rd_addr_gray_wr[6] -.sym 20986 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 20987 tx_fifo.rd_addr_gray_wr[2] -.sym 20989 tx_fifo.rd_addr_gray_wr[5] -.sym 20991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 21000 rx_fifo.rd_addr[2] -.sym 21001 rx_fifo.rd_addr[3] -.sym 21003 rx_fifo.rd_addr[4] -.sym 21004 rx_fifo.rd_addr[5] -.sym 21005 rx_fifo.rd_addr[6] -.sym 21006 rx_fifo.rd_addr[7] -.sym 21007 rx_fifo.rd_addr[8] -.sym 21008 rx_fifo.rd_addr[9] -.sym 21009 rx_fifo.rd_addr[1] -.sym 21010 rx_fifo.rd_addr[0] -.sym 21011 r_counter_$glb_clk -.sym 21012 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 21013 $PACKER_VCC_NET -.sym 21017 rx_fifo.mem_i.0.1_WDATA -.sym 21021 rx_fifo.mem_i.0.1_WDATA_1 -.sym 21028 w_rx_fifo_pulled_data[23] -.sym 21030 w_rx_fifo_pulled_data[21] -.sym 21032 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 21034 rx_fifo.rd_addr[9] -.sym 21038 tx_fifo.rd_addr[7] -.sym 21039 rx_fifo.rd_addr[0] -.sym 21044 rx_fifo.rd_addr[5] -.sym 21046 rx_fifo.wr_addr[8] -.sym 21054 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 21055 rx_fifo.wr_addr[5] -.sym 21056 rx_fifo.wr_addr[8] -.sym 21062 rx_fifo.wr_addr[0] -.sym 21066 rx_fifo.wr_addr[9] -.sym 21067 $PACKER_VCC_NET -.sym 21072 rx_fifo.wr_addr[1] -.sym 21074 rx_fifo.wr_addr[6] -.sym 21076 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21077 rx_fifo.wr_addr[3] -.sym 21078 rx_fifo.wr_addr[7] -.sym 21079 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21081 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 21083 rx_fifo.wr_addr[4] -.sym 21090 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 21091 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 21092 tx_fifo.wr_addr[8] -.sym 21102 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] +.sym 20931 rx_fifo.wr_addr[5] +.sym 20938 rx_fifo.wr_addr[2] +.sym 20940 rx_fifo.wr_addr[8] +.sym 20942 o_miso_$_TBUF__Y_E +.sym 20989 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 20990 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 21040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 21041 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 21043 rx_fifo.rd_addr[8] +.sym 21046 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21047 i_rst_b$SB_IO_IN +.sym 21056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21058 rx_fifo.wr_addr[6] +.sym 21060 rx_fifo.wr_addr[4] +.sym 21062 rx_fifo.wr_addr[9] +.sym 21063 rx_fifo.wr_addr[1] +.sym 21064 rx_fifo.wr_addr[3] +.sym 21065 rx_fifo.mem_i.0.0_WDATA_2 +.sym 21067 rx_fifo.mem_i.0.0_WDATA_3 +.sym 21074 $PACKER_VCC_NET +.sym 21075 rx_fifo.wr_addr[5] +.sym 21078 rx_fifo.wr_addr[0] +.sym 21081 rx_fifo.wr_addr[2] +.sym 21083 rx_fifo.wr_addr[8] +.sym 21084 rx_fifo.wr_addr[7] +.sym 21086 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 21087 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 21088 smi_ctrl_ins.tx_reg_state[1] +.sym 21089 smi_ctrl_ins.tx_reg_state[2] +.sym 21090 smi_ctrl_ins.tx_reg_state[3] +.sym 21091 o_miso_$_TBUF__Y_E +.sym 21092 smi_ctrl_ins.tx_reg_state[0] +.sym 21093 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 21102 rx_fifo.wr_addr[2] .sym 21103 rx_fifo.wr_addr[3] .sym 21105 rx_fifo.wr_addr[4] .sym 21106 rx_fifo.wr_addr[5] @@ -10411,2459 +10324,2237 @@ .sym 21110 rx_fifo.wr_addr[9] .sym 21111 rx_fifo.wr_addr[1] .sym 21112 rx_fifo.wr_addr[0] -.sym 21113 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 21114 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 21116 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21120 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21113 lvds_clock_$glb_clk +.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21116 rx_fifo.mem_i.0.0_WDATA_3 +.sym 21120 rx_fifo.mem_i.0.0_WDATA_2 .sym 21123 $PACKER_VCC_NET -.sym 21128 rx_fifo.wr_addr[0] -.sym 21130 w_rx_fifo_pulled_data[30] -.sym 21139 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 21140 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 21141 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 21128 rx_fifo.wr_addr[9] +.sym 21135 rx_fifo.mem_i.0.0_WDATA_3 +.sym 21140 smi_ctrl_ins.swe_and_reset +.sym 21146 smi_ctrl_ins.w_fifo_push_trigger +.sym 21148 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 21149 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 21156 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21158 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 21160 rx_fifo.rd_addr[6] -.sym 21162 rx_fifo.rd_addr[2] -.sym 21164 rx_fifo.rd_addr[7] -.sym 21166 rx_fifo.rd_addr[3] -.sym 21167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 21169 rx_fifo.mem_i.0.3_WDATA -.sym 21171 rx_fifo.rd_addr[1] -.sym 21174 rx_fifo.rd_addr[8] +.sym 21162 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21163 rx_fifo.rd_addr[3] +.sym 21164 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 21166 rx_fifo.rd_addr[0] +.sym 21167 rx_fifo.mem_i.0.0_WDATA_1 +.sym 21171 rx_fifo.mem_i.0.0_WDATA +.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21175 rx_fifo.rd_addr[9] .sym 21176 $PACKER_VCC_NET -.sym 21177 rx_fifo.rd_addr[0] -.sym 21180 rx_fifo.rd_addr[9] -.sym 21182 rx_fifo.rd_addr[5] -.sym 21185 rx_fifo.rd_addr[4] -.sym 21187 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21188 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 21189 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 21191 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 21192 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 21193 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 21204 rx_fifo.rd_addr[2] +.sym 21177 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 21181 rx_fifo.rd_addr[8] +.sym 21189 smi_ctrl_ins.w_fifo_push_trigger +.sym 21194 smi_ctrl_ins.swe_and_reset +.sym 21204 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] .sym 21205 rx_fifo.rd_addr[3] -.sym 21207 rx_fifo.rd_addr[4] -.sym 21208 rx_fifo.rd_addr[5] +.sym 21207 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21208 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] .sym 21209 rx_fifo.rd_addr[6] -.sym 21210 rx_fifo.rd_addr[7] +.sym 21210 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] .sym 21211 rx_fifo.rd_addr[8] .sym 21212 rx_fifo.rd_addr[9] -.sym 21213 rx_fifo.rd_addr[1] +.sym 21213 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] .sym 21214 rx_fifo.rd_addr[0] .sym 21215 r_counter_$glb_clk -.sym 21216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] +.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] .sym 21217 $PACKER_VCC_NET -.sym 21221 rx_fifo.mem_i.0.3_WDATA -.sym 21225 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21231 tx_fifo.wr_addr[8] -.sym 21232 rx_fifo.rd_addr[3] -.sym 21233 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 21236 rx_fifo.rd_addr[6] -.sym 21238 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 21239 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 21240 rx_fifo.rd_addr[7] -.sym 21242 $PACKER_VCC_NET -.sym 21251 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 21296 spi_if_ins.spi.r_rx_done -.sym 21332 tx_fifo.wr_addr[1] -.sym 21333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 21341 w_tx_fifo_full -.sym 21345 i_mosi$SB_IO_IN -.sym 21346 int_miso -.sym 21350 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 21352 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 21398 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 21399 int_miso -.sym 21442 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 21446 rx_fifo.wr_addr[8] -.sym 21494 spi_if_ins.spi.r_rx_byte[0] -.sym 21495 spi_if_ins.spi.r_rx_byte[1] -.sym 21496 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 21497 spi_if_ins.spi.r_rx_byte[2] -.sym 21499 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 21501 spi_if_ins.spi.r_rx_byte[5] -.sym 21596 spi_if_ins.w_rx_data[5] -.sym 21597 spi_if_ins.w_rx_data[0] -.sym 21598 spi_if_ins.w_rx_data[4] -.sym 21599 spi_if_ins.w_rx_data[3] -.sym 21600 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 21601 spi_if_ins.w_rx_data[2] -.sym 21602 spi_if_ins.w_rx_data[6] -.sym 21603 spi_if_ins.w_rx_data[1] -.sym 21651 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 21653 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 21655 spi_if_ins.w_rx_data[6] -.sym 21656 spi_if_ins.r_tx_byte[7] -.sym 21658 w_rx_data[0] -.sym 21659 spi_if_ins.w_rx_data[5] -.sym 21698 w_rx_data[2] -.sym 21699 w_rx_data[1] -.sym 21700 w_rx_data[0] -.sym 21702 w_rx_data[3] -.sym 21741 io_pmod[3]$SB_IO_IN -.sym 21753 w_rx_data[3] -.sym 21761 w_rx_data[2] -.sym 21763 w_rx_data[1] -.sym 21800 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] -.sym 21801 io_ctrl_ins.rf_pin_state[1] -.sym 21804 io_ctrl_ins.rf_pin_state[4] -.sym 21806 io_pmod_SB_DFFE_Q_E -.sym 21807 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] -.sym 21853 w_rx_data[0] -.sym 21854 i_rst_b$SB_IO_IN -.sym 21855 io_ctrl_ins.rf_pin_state[4] -.sym 21858 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 21860 w_rx_data[4] -.sym 21902 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 21903 o_tr_vc2$SB_IO_OUT -.sym 21905 o_led0_SB_LUT4_I1_O[2] -.sym 21906 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 21907 o_shdn_tx_lna$SB_IO_OUT -.sym 21909 o_shdn_rx_lna$SB_IO_OUT -.sym 21951 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 21958 o_rx_h_tx_l$SB_IO_OUT -.sym 21966 o_rx_h_tx_l_b$SB_IO_OUT -.sym 21967 o_tr_vc2$SB_IO_OUT -.sym 22004 io_ctrl_ins.mixer_en_state -.sym 22005 o_tr_vc1$SB_IO_OUT -.sym 22007 o_rx_h_tx_l_b$SB_IO_OUT -.sym 22008 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 22009 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 22010 o_tr_vc1_b$SB_IO_OUT -.sym 22011 o_rx_h_tx_l$SB_IO_OUT -.sym 22046 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 22048 o_led0_SB_LUT4_I1_O[0] -.sym 22054 o_led1_SB_LUT4_I1_I2[0] -.sym 22059 w_rx_data[0] -.sym 22062 o_led1_SB_LUT4_I1_O[0] -.sym 22064 spi_if_ins.r_tx_byte[7] -.sym 22069 o_tr_vc1$SB_IO_OUT -.sym 22107 io_ctrl_ins.rf_pin_state[0] -.sym 22111 io_ctrl_ins.rf_pin_state[6] -.sym 22150 o_led0$SB_IO_OUT -.sym 22151 o_led1_SB_LUT4_I1_I2[0] -.sym 22153 o_rx_h_tx_l$SB_IO_OUT -.sym 22155 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 22157 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 22158 o_led1$SB_IO_OUT -.sym 22164 w_rx_data[6] -.sym 22167 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 22208 w_rx_data[6] -.sym 22258 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 22262 i_rst_b$SB_IO_IN -.sym 22268 o_led0$SB_IO_OUT -.sym 22359 w_rx_data[6] +.sym 21221 rx_fifo.mem_i.0.0_WDATA +.sym 21225 rx_fifo.mem_i.0.0_WDATA_1 +.sym 21235 rx_fifo.mem_i.0.0_WDATA_1 +.sym 21238 w_smi_data_input[7] +.sym 21239 rx_fifo.rd_addr[3] +.sym 21249 rx_fifo.rd_addr[6] +.sym 21251 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21252 rx_fifo.rd_addr[0] +.sym 21260 rx_fifo.wr_addr[4] +.sym 21261 rx_fifo.wr_addr[0] +.sym 21262 $PACKER_VCC_NET +.sym 21264 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21267 rx_fifo.wr_addr[6] +.sym 21272 rx_fifo.wr_addr[7] +.sym 21273 rx_fifo.mem_q.0.1_WDATA_2 +.sym 21275 rx_fifo.wr_addr[3] +.sym 21276 rx_fifo.wr_addr[1] +.sym 21278 rx_fifo.wr_addr[8] +.sym 21279 rx_fifo.wr_addr[5] +.sym 21282 rx_fifo.wr_addr[9] +.sym 21285 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21287 rx_fifo.wr_addr[2] +.sym 21290 spi_if_ins.spi.r_rx_done +.sym 21306 rx_fifo.wr_addr[2] +.sym 21307 rx_fifo.wr_addr[3] +.sym 21309 rx_fifo.wr_addr[4] +.sym 21310 rx_fifo.wr_addr[5] +.sym 21311 rx_fifo.wr_addr[6] +.sym 21312 rx_fifo.wr_addr[7] +.sym 21313 rx_fifo.wr_addr[8] +.sym 21314 rx_fifo.wr_addr[9] +.sym 21315 rx_fifo.wr_addr[1] +.sym 21316 rx_fifo.wr_addr[0] +.sym 21317 lvds_clock_$glb_clk +.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21320 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21324 rx_fifo.mem_q.0.1_WDATA_2 +.sym 21327 $PACKER_VCC_NET +.sym 21334 w_smi_data_input[7] +.sym 21336 rx_fifo.wr_addr[4] +.sym 21337 rx_fifo.wr_addr[0] +.sym 21340 rx_fifo.mem_q.0.1_WDATA_3 +.sym 21341 rx_fifo.mem_q.0.1_WDATA_2 +.sym 21343 rx_fifo.wr_addr[6] +.sym 21344 rx_fifo.wr_addr[4] +.sym 21345 rx_fifo.wr_addr[0] +.sym 21351 o_miso_$_TBUF__Y_E +.sym 21360 rx_fifo.rd_addr[8] +.sym 21361 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 21362 rx_fifo.mem_q.0.1_WDATA +.sym 21365 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 21367 rx_fifo.rd_addr[3] +.sym 21369 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21371 rx_fifo.mem_q.0.1_WDATA_1 +.sym 21373 $PACKER_VCC_NET +.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21380 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 21384 rx_fifo.rd_addr[9] +.sym 21387 rx_fifo.rd_addr[6] +.sym 21389 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21390 rx_fifo.rd_addr[0] +.sym 21392 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 21394 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 21395 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 21396 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 21397 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 21398 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 21399 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 21408 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 21409 rx_fifo.rd_addr[3] +.sym 21411 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21412 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 21413 rx_fifo.rd_addr[6] +.sym 21414 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 21415 rx_fifo.rd_addr[8] +.sym 21416 rx_fifo.rd_addr[9] +.sym 21417 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21418 rx_fifo.rd_addr[0] +.sym 21419 r_counter_$glb_clk +.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21421 $PACKER_VCC_NET +.sym 21425 rx_fifo.mem_q.0.1_WDATA +.sym 21429 rx_fifo.mem_q.0.1_WDATA_1 +.sym 21435 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21436 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 21437 rx_fifo.mem_q.0.1_WDATA_1 +.sym 21438 rx_fifo.mem_q.0.1_WDATA +.sym 21446 $PACKER_VCC_NET +.sym 21448 i_rst_b$SB_IO_IN +.sym 21452 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 21455 rx_fifo.rd_addr[8] +.sym 21463 rx_fifo.wr_addr[7] +.sym 21464 rx_fifo.wr_addr[1] +.sym 21466 $PACKER_VCC_NET +.sym 21467 rx_fifo.wr_addr[5] +.sym 21469 rx_fifo.wr_addr[3] +.sym 21470 rx_fifo.wr_addr[9] +.sym 21471 rx_fifo.wr_addr[6] +.sym 21473 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21475 rx_fifo.wr_addr[2] +.sym 21477 rx_fifo.wr_addr[8] +.sym 21482 rx_fifo.wr_addr[4] +.sym 21483 rx_fifo.wr_addr[0] +.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21491 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21494 smi_ctrl_ins.soe_and_reset +.sym 21495 spi_if_ins.r_tx_data_valid +.sym 21496 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 21497 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 21498 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 21510 rx_fifo.wr_addr[2] +.sym 21511 rx_fifo.wr_addr[3] +.sym 21513 rx_fifo.wr_addr[4] +.sym 21514 rx_fifo.wr_addr[5] +.sym 21515 rx_fifo.wr_addr[6] +.sym 21516 rx_fifo.wr_addr[7] +.sym 21517 rx_fifo.wr_addr[8] +.sym 21518 rx_fifo.wr_addr[9] +.sym 21519 rx_fifo.wr_addr[1] +.sym 21520 rx_fifo.wr_addr[0] +.sym 21521 lvds_clock_$glb_clk +.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 21524 rx_fifo.mem_i.0.3_WDATA_3 +.sym 21528 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21531 $PACKER_VCC_NET +.sym 21536 rx_fifo.wr_addr[9] +.sym 21541 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21542 $PACKER_VCC_NET +.sym 21547 rx_fifo.wr_addr[7] +.sym 21567 rx_fifo.rd_addr[3] +.sym 21571 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 21572 rx_fifo.rd_addr[9] +.sym 21573 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21579 rx_fifo.rd_addr[6] +.sym 21580 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 21582 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21584 $PACKER_VCC_NET +.sym 21589 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21591 rx_fifo.mem_i.0.3_WDATA_1 +.sym 21592 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 21593 rx_fifo.rd_addr[8] +.sym 21594 rx_fifo.rd_addr[0] +.sym 21595 rx_fifo.mem_i.0.3_WDATA +.sym 21600 w_fetch +.sym 21601 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 21602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 21612 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 21613 rx_fifo.rd_addr[3] +.sym 21615 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 21616 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 21617 rx_fifo.rd_addr[6] +.sym 21618 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 21619 rx_fifo.rd_addr[8] +.sym 21620 rx_fifo.rd_addr[9] +.sym 21621 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 21622 rx_fifo.rd_addr[0] +.sym 21623 r_counter_$glb_clk +.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 21625 $PACKER_VCC_NET +.sym 21629 rx_fifo.mem_i.0.3_WDATA +.sym 21633 rx_fifo.mem_i.0.3_WDATA_1 +.sym 21641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 21644 i_glob_clock$SB_IO_IN +.sym 21645 i_smi_soe_se$SB_IO_IN +.sym 21647 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 21649 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 21651 w_fetch +.sym 21658 io_pmod[6]$SB_IO_IN +.sym 21660 rx_fifo.rd_addr[0] +.sym 21698 int_miso +.sym 21744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 21745 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 21750 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 21754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 21758 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 21802 $PACKER_GND_NET +.sym 21807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 21843 io_pmod[0]$SB_IO_IN +.sym 21861 w_rx_data[1] +.sym 21953 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 22005 o_led1$SB_IO_OUT +.sym 22010 o_led0$SB_IO_OUT +.sym 22157 o_led1$SB_IO_OUT +.sym 22361 o_tr_vc1$SB_IO_OUT .sym 22487 o_led1$SB_IO_OUT -.sym 22498 o_led1$SB_IO_OUT +.sym 22505 o_led1$SB_IO_OUT .sym 22517 int_miso .sym 22519 o_miso_$_TBUF__Y_E -.sym 22536 o_miso_$_TBUF__Y_E +.sym 22533 o_miso_$_TBUF__Y_E .sym 22537 int_miso -.sym 22588 tx_fifo.rd_addr_gray[4] -.sym 22609 tx_fifo.rd_addr_gray_wr[4] -.sym 22612 i_smi_soe_se$SB_IO_IN -.sym 22624 tx_fifo.rd_addr_gray[4] -.sym 22635 i_smi_soe_se$SB_IO_IN -.sym 22643 tx_fifo.rd_addr_gray_wr[4] +.sym 22554 i_mosi$SB_IO_IN +.sym 22561 int_miso +.sym 22565 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 22576 i_ss$SB_IO_IN +.sym 22595 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 22605 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 22632 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 22663 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 22664 r_counter_$glb_clk +.sym 22665 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN -.sym 22671 smi_ctrl_ins.soe_and_reset -.sym 22675 smi_ctrl_ins.swe_and_reset +.sym 22687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 22707 i_ss$SB_IO_IN -.sym 22710 smi_ctrl_ins.swe_and_reset -.sym 22712 i_smi_swe_srw$SB_IO_IN .sym 22720 i_sck$SB_IO_IN -.sym 22724 i_ss$SB_IO_IN -.sym 22726 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 22727 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] .sym 22729 i_sck$SB_IO_IN -.sym 22730 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 22734 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 22736 smi_ctrl_ins.soe_and_reset -.sym 22753 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 22756 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 22766 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 22769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 22771 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 22773 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 22774 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 22788 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 22795 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 22798 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 22799 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 22806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 22812 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 22816 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 22826 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 22827 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 22828 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 22829 o_miso_$_TBUF__Y_E -.sym 22830 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 22831 smi_ctrl_ins.tx_reg_state[3] -.sym 22832 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 22833 smi_ctrl_ins.tx_reg_state[2] -.sym 22834 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 22835 smi_ctrl_ins.tx_reg_state[0] -.sym 22836 smi_ctrl_ins.tx_reg_state[1] -.sym 22849 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 22855 i_rst_b_SB_LUT4_I3_O -.sym 22859 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 22861 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 22862 o_miso_$_TBUF__Y_E -.sym 22871 tx_fifo.rd_addr_gray[2] -.sym 22873 tx_fifo.rd_addr_gray_wr[2] -.sym 22881 tx_fifo.rd_addr_gray[6] -.sym 22884 tx_fifo.rd_addr_gray[5] -.sym 22895 tx_fifo.rd_addr_gray_wr[6] -.sym 22899 tx_fifo.rd_addr_gray_wr[5] -.sym 22906 tx_fifo.rd_addr_gray_wr[2] -.sym 22912 tx_fifo.rd_addr_gray[6] -.sym 22917 tx_fifo.rd_addr_gray_wr[6] -.sym 22923 tx_fifo.rd_addr_gray[2] -.sym 22935 tx_fifo.rd_addr_gray[5] -.sym 22946 tx_fifo.rd_addr_gray_wr[5] -.sym 22950 r_counter_$glb_clk -.sym 22957 smi_ctrl_ins.w_fifo_push_trigger -.sym 22963 spi_if_ins.w_rx_data[6] -.sym 22964 w_smi_data_input[7] -.sym 22966 i_rst_b$SB_IO_IN -.sym 22971 o_miso_$_TBUF__Y_E -.sym 22976 smi_ctrl_ins.swe_and_reset -.sym 22977 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 22980 w_tx_fifo_pull -.sym 22984 i_ss$SB_IO_IN -.sym 22994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 22995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 23003 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 23004 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 23008 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 23013 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 23018 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 23019 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 23050 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 23053 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 23056 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 23057 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 23058 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 23059 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 23064 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 23072 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O -.sym 23073 r_counter_$glb_clk -.sym 23074 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23075 w_tx_fifo_pull -.sym 23087 w_smi_data_input[7] -.sym 23098 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 23099 w_tx_fifo_empty -.sym 23101 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 22733 i_ss$SB_IO_IN +.sym 22879 w_rx_fifo_pulled_data[16] +.sym 22887 w_rx_fifo_pulled_data[17] +.sym 22934 w_rx_fifo_pulled_data[16] +.sym 22940 w_rx_fifo_pulled_data[17] +.sym 22949 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce +.sym 22950 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 22980 i_ss$SB_IO_IN +.sym 22996 w_smi_data_input[7] +.sym 22998 i_rst_b$SB_IO_IN +.sym 23000 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 23002 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 23004 w_smi_data_input[7] +.sym 23005 smi_ctrl_ins.tx_reg_state[3] +.sym 23006 i_rst_b$SB_IO_IN +.sym 23010 i_ss$SB_IO_IN +.sym 23015 smi_ctrl_ins.tx_reg_state[0] +.sym 23018 smi_ctrl_ins.swe_and_reset +.sym 23019 smi_ctrl_ins.tx_reg_state[1] +.sym 23020 smi_ctrl_ins.tx_reg_state[2] +.sym 23026 i_rst_b$SB_IO_IN +.sym 23028 smi_ctrl_ins.tx_reg_state[0] +.sym 23029 smi_ctrl_ins.tx_reg_state[3] +.sym 23032 i_rst_b$SB_IO_IN +.sym 23033 w_smi_data_input[7] +.sym 23034 smi_ctrl_ins.tx_reg_state[3] +.sym 23035 smi_ctrl_ins.tx_reg_state[0] +.sym 23038 smi_ctrl_ins.tx_reg_state[2] +.sym 23040 w_smi_data_input[7] +.sym 23041 i_rst_b$SB_IO_IN +.sym 23044 w_smi_data_input[7] +.sym 23045 smi_ctrl_ins.tx_reg_state[0] +.sym 23047 i_rst_b$SB_IO_IN +.sym 23050 w_smi_data_input[7] +.sym 23052 i_rst_b$SB_IO_IN +.sym 23053 smi_ctrl_ins.tx_reg_state[1] +.sym 23056 i_ss$SB_IO_IN +.sym 23062 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 23063 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 23068 smi_ctrl_ins.tx_reg_state[1] +.sym 23069 w_smi_data_input[7] +.sym 23071 smi_ctrl_ins.tx_reg_state[2] +.sym 23073 smi_ctrl_ins.swe_and_reset +.sym 23099 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23103 $io_pmod[3]$iobuf_i .sym 23104 i_sck$SB_IO_IN +.sym 23108 i_sck$SB_IO_IN .sym 23116 i_rst_b$SB_IO_IN -.sym 23118 w_tx_fifo_full -.sym 23120 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23121 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 23124 tx_fifo.rd_addr_gray_wr[0] -.sym 23128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23129 tx_fifo.wr_addr[1] -.sym 23132 w_tx_fifo_pull -.sym 23133 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 23137 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 23143 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 23144 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23149 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 23150 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 23152 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 23156 tx_fifo.wr_addr[1] -.sym 23157 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23158 w_tx_fifo_full -.sym 23167 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 23168 tx_fifo.wr_addr[1] -.sym 23169 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 23170 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 23176 tx_fifo.rd_addr_gray_wr[0] -.sym 23180 i_rst_b$SB_IO_IN -.sym 23182 w_tx_fifo_pull -.sym 23196 r_counter_$glb_clk -.sym 23210 tx_fifo.rd_addr_gray_wr[0] -.sym 23222 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23227 i_ss$SB_IO_IN -.sym 23228 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23229 smi_ctrl_ins.soe_and_reset -.sym 23230 i_ss$SB_IO_IN -.sym 23231 i_sck$SB_IO_IN -.sym 23233 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 23243 i_ss$SB_IO_IN -.sym 23244 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23250 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23129 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 23131 w_smi_data_input[7] +.sym 23132 i_smi_swe_srw$rename$0 +.sym 23141 smi_ctrl_ins.swe_and_reset +.sym 23158 w_smi_data_input[7] +.sym 23185 i_rst_b$SB_IO_IN +.sym 23187 i_smi_swe_srw$rename$0 +.sym 23196 smi_ctrl_ins.swe_and_reset +.sym 23197 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 23198 i_smi_swe_srw$rename$0 +.sym 23199 smi_ctrl_ins.swe_and_reset +.sym 23200 spi_if_ins.spi.r2_rx_done +.sym 23201 spi_if_ins.spi.r3_rx_done +.sym 23204 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23226 i_ss$SB_IO_IN +.sym 23246 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23252 i_ss$SB_IO_IN +.sym 23257 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E .sym 23264 i_sck$SB_IO_IN -.sym 23311 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23273 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] .sym 23318 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E .sym 23319 i_sck$SB_IO_IN .sym 23320 i_ss$SB_IO_IN -.sym 23321 spi_if_ins.spi.r3_rx_done -.sym 23323 spi_if_ins.spi.SCKr[0] -.sym 23324 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23325 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23326 spi_if_ins.spi.r2_rx_done -.sym 23327 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23346 i_rst_b_SB_LUT4_I3_O -.sym 23352 o_miso_$_TBUF__Y_E -.sym 23369 spi_if_ins.r_tx_byte[7] -.sym 23373 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 23374 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 23382 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23388 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23389 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23392 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23393 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 23431 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 23432 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 23434 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 23438 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 23439 spi_if_ins.r_tx_byte[7] -.sym 23440 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23441 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 23442 r_counter_$glb_clk -.sym 23444 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23445 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23446 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23447 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23448 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 23449 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23450 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23465 spi_if_ins.r_tx_byte[7] +.sym 23328 spi_if_ins.spi.SCKr[0] +.sym 23347 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23354 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23365 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23369 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23373 o_miso_$_TBUF__Y_E +.sym 23375 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23376 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23378 i_sck$SB_IO_IN +.sym 23382 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23386 i_mosi$SB_IO_IN +.sym 23388 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23396 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23410 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 23415 i_mosi$SB_IO_IN +.sym 23421 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 23425 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 23432 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 23440 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 23441 o_miso_$_TBUF__Y_E +.sym 23442 i_sck$SB_IO_IN +.sym 23445 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23451 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23455 o_led0$SB_IO_OUT .sym 23467 io_pmod[6]$SB_IO_IN -.sym 23470 w_rx_data[1] -.sym 23478 io_pmod_SB_DFFE_Q_E -.sym 23487 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23493 i_mosi$SB_IO_IN -.sym 23497 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23501 i_sck$SB_IO_IN -.sym 23502 i_ss$SB_IO_IN -.sym 23508 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23509 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23511 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23512 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23521 i_mosi$SB_IO_IN -.sym 23524 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23533 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23538 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23548 i_ss$SB_IO_IN -.sym 23550 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23561 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23565 i_sck$SB_IO_IN -.sym 23567 i_rst_b_SB_LUT4_I3_O -.sym 23568 spi_if_ins.spi.r_rx_byte[7] -.sym 23569 spi_if_ins.spi.r_rx_byte[4] -.sym 23571 spi_if_ins.spi.r_rx_byte[3] -.sym 23573 spi_if_ins.spi.r_rx_byte[6] -.sym 23579 i_mosi$SB_IO_IN -.sym 23581 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23590 i_glob_clock$SB_IO_IN -.sym 23591 $io_pmod[3]$iobuf_i -.sym 23593 io_pmod_SB_DFFE_Q_E -.sym 23595 spi_if_ins.w_rx_data[6] -.sym 23596 w_rx_data[2] -.sym 23598 w_rx_data[1] -.sym 23599 spi_if_ins.w_rx_data[5] -.sym 23609 spi_if_ins.spi.r_rx_byte[1] -.sym 23610 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23615 spi_if_ins.spi.r_rx_byte[5] -.sym 23616 spi_if_ins.spi.r_rx_byte[0] -.sym 23619 spi_if_ins.spi.r_rx_byte[2] -.sym 23633 spi_if_ins.spi.r_rx_byte[7] -.sym 23634 spi_if_ins.spi.r_rx_byte[4] -.sym 23636 spi_if_ins.spi.r_rx_byte[3] -.sym 23638 spi_if_ins.spi.r_rx_byte[6] -.sym 23642 spi_if_ins.spi.r_rx_byte[5] -.sym 23649 spi_if_ins.spi.r_rx_byte[0] -.sym 23656 spi_if_ins.spi.r_rx_byte[4] -.sym 23659 spi_if_ins.spi.r_rx_byte[3] -.sym 23665 spi_if_ins.spi.r_rx_byte[7] -.sym 23672 spi_if_ins.spi.r_rx_byte[2] -.sym 23678 spi_if_ins.spi.r_rx_byte[6] -.sym 23683 spi_if_ins.spi.r_rx_byte[1] -.sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23468 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 23473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23478 w_load +.sym 23487 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 23489 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23491 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 23493 i_smi_soe_se$SB_IO_IN +.sym 23498 i_ss$SB_IO_IN +.sym 23499 i_rst_b$SB_IO_IN +.sym 23502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23510 spi_if_ins.r_tx_data_valid +.sym 23511 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23519 i_smi_soe_se$SB_IO_IN +.sym 23521 i_rst_b$SB_IO_IN +.sym 23525 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 23530 i_ss$SB_IO_IN +.sym 23532 spi_if_ins.r_tx_data_valid +.sym 23537 spi_if_ins.r_tx_data_valid +.sym 23539 i_ss$SB_IO_IN +.sym 23543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23544 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23564 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 23565 r_counter_$glb_clk +.sym 23566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23569 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 23570 w_load +.sym 23579 smi_ctrl_ins.soe_and_reset +.sym 23587 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 23592 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23594 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 23602 spi_if_ins.r_tx_byte[7] +.sym 23613 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23614 i_rst_b$SB_IO_IN +.sym 23619 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 23634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 23635 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23637 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 23665 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23671 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23677 i_rst_b$SB_IO_IN +.sym 23678 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23679 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 23680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 23687 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .sym 23688 r_counter_$glb_clk -.sym 23696 $io_pmod[3]$iobuf_i +.sym 23689 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 23703 $PACKER_VCC_NET +.sym 23705 w_load .sym 23710 i_rst_b$SB_IO_IN -.sym 23719 i_glob_clock$SB_IO_IN -.sym 23720 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23732 spi_if_ins.w_rx_data[0] -.sym 23734 spi_if_ins.w_rx_data[3] -.sym 23736 spi_if_ins.w_rx_data[2] -.sym 23738 spi_if_ins.w_rx_data[1] -.sym 23742 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 23767 spi_if_ins.w_rx_data[2] -.sym 23770 spi_if_ins.w_rx_data[1] -.sym 23777 spi_if_ins.w_rx_data[0] -.sym 23789 spi_if_ins.w_rx_data[3] -.sym 23810 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23714 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 23733 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 23752 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23755 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 23762 spi_if_ins.r_tx_byte[7] +.sym 23765 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23766 spi_if_ins.r_tx_byte[7] +.sym 23767 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 23810 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] .sym 23811 r_counter_$glb_clk -.sym 23816 $io_pmod[2]$iobuf_i -.sym 23818 $io_pmod[1]$iobuf_i -.sym 23819 $io_pmod[0]$iobuf_i -.sym 23828 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 23829 w_rx_data[1] -.sym 23838 w_rx_data[0] -.sym 23842 w_rx_data[3] -.sym 23844 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 23845 io_ctrl_ins.pmod_dir_state[3] -.sym 23847 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 23854 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 23855 w_rx_data[1] -.sym 23862 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 23866 w_rx_data[3] -.sym 23870 o_led0_SB_LUT4_I1_O[0] -.sym 23871 i_rst_b$SB_IO_IN -.sym 23872 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 23874 o_led1_SB_LUT4_I1_I2[0] -.sym 23880 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 23883 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 23885 w_rx_data[4] -.sym 23887 o_led1_SB_LUT4_I1_I2[0] -.sym 23888 i_rst_b$SB_IO_IN -.sym 23889 o_led0_SB_LUT4_I1_O[0] -.sym 23890 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 23893 w_rx_data[1] -.sym 23911 w_rx_data[4] -.sym 23923 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 23924 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 23925 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 23931 w_rx_data[3] -.sym 23933 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 23934 r_counter_$glb_clk -.sym 23938 io_ctrl_ins.pmod_dir_state[3] -.sym 23943 io_ctrl_ins.pmod_dir_state[0] -.sym 23967 o_tr_vc1$SB_IO_OUT -.sym 23968 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 23969 io_pmod_SB_DFFE_Q_E -.sym 23970 w_rx_data[1] -.sym 23977 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] -.sym 23979 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 23982 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 23984 o_led0_SB_LUT4_I1_O[0] -.sym 23985 io_ctrl_ins.mixer_en_state -.sym 23986 io_ctrl_ins.rf_pin_state[1] -.sym 23988 o_led1_SB_LUT4_I1_I2[0] -.sym 23989 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 23990 io_pmod[0]$SB_IO_IN -.sym 23992 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] -.sym 23993 io_ctrl_ins.rf_pin_state[2] -.sym 23997 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 24001 o_led1_SB_LUT4_I1_O[0] -.sym 24007 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 24010 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] -.sym 24013 o_led1_SB_LUT4_I1_O[0] -.sym 24016 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24017 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] -.sym 24018 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24019 o_led1_SB_LUT4_I1_I2[0] -.sym 24028 io_ctrl_ins.mixer_en_state -.sym 24029 io_pmod[0]$SB_IO_IN -.sym 24030 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 24031 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 24035 o_led0_SB_LUT4_I1_O[0] -.sym 24037 o_led1_SB_LUT4_I1_O[0] -.sym 24040 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24041 o_led1_SB_LUT4_I1_I2[0] -.sym 24042 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24043 io_ctrl_ins.rf_pin_state[2] -.sym 24052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24054 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24055 io_ctrl_ins.rf_pin_state[1] -.sym 24056 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 24057 r_counter_$glb_clk -.sym 24059 o_led1$SB_IO_OUT -.sym 24060 o_led0$SB_IO_OUT -.sym 24078 io_pmod[0]$SB_IO_IN -.sym 24083 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 24087 o_tr_vc1_b$SB_IO_OUT -.sym 24100 io_ctrl_ins.rf_pin_state[4] -.sym 24102 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24105 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 24106 o_led1_SB_LUT4_I1_I2[0] -.sym 24108 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24109 io_ctrl_ins.rf_pin_state[0] -.sym 24111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 24112 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24113 io_ctrl_ins.rf_pin_state[6] -.sym 24119 io_ctrl_ins.rf_pin_state[7] -.sym 24125 io_ctrl_ins.rf_pin_state[5] -.sym 24128 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 24133 o_led1_SB_LUT4_I1_I2[0] -.sym 24134 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24135 io_ctrl_ins.rf_pin_state[0] -.sym 24136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24139 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24140 io_ctrl_ins.rf_pin_state[5] -.sym 24141 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 24142 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24151 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 24152 io_ctrl_ins.rf_pin_state[6] -.sym 24153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24157 o_led1_SB_LUT4_I1_I2[0] -.sym 24159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24163 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24164 o_led1_SB_LUT4_I1_I2[0] -.sym 24165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24166 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 24169 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24170 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 24171 io_ctrl_ins.rf_pin_state[4] -.sym 24172 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 24175 io_ctrl_ins.rf_pin_state[7] -.sym 24177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 24178 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 23839 o_led1_SB_DFFER_Q_E +.sym 23845 w_rx_data[0] +.sym 23855 io_pmod[6]$SB_IO_IN +.sym 23856 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 23874 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 23884 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 23929 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 23930 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 23931 io_pmod[6]$SB_IO_IN +.sym 23933 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 23934 lvds_clock_$glb_clk +.sym 23935 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 23942 $io_pmod[0]$iobuf_i +.sym 23954 $PACKER_GND_NET +.sym 23961 o_led0$SB_IO_OUT +.sym 23967 o_led1$SB_IO_OUT +.sym 24071 lvds_clock +.sym 24111 o_led1_SB_DFFER_Q_E +.sym 24114 w_rx_data[1] +.sym 24117 w_rx_data[0] +.sym 24139 w_rx_data[1] +.sym 24172 w_rx_data[0] +.sym 24179 o_led1_SB_DFFER_Q_E .sym 24180 r_counter_$glb_clk -.sym 24184 o_rx_h_tx_l_b$SB_IO_OUT -.sym 24197 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.sym 24201 o_led1$SB_IO_OUT -.sym 24203 o_led0$SB_IO_OUT -.sym 24228 w_rx_data[0] -.sym 24231 w_rx_data[6] -.sym 24234 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 24264 w_rx_data[0] -.sym 24288 w_rx_data[6] -.sym 24302 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 24303 r_counter_$glb_clk -.sym 24323 o_tr_vc2$SB_IO_OUT -.sym 24357 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 24362 spi_if_ins.w_rx_data[6] -.sym 24379 spi_if_ins.w_rx_data[6] -.sym 24425 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 24426 r_counter_$glb_clk +.sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 24443 o_rx_h_tx_l_b$SB_IO_OUT .sym 24596 o_led0$SB_IO_OUT -.sym 24620 o_led0$SB_IO_OUT -.sym 24621 i_rst_b$SB_IO_IN -.sym 24656 smi_ctrl_ins.swe_and_reset +.sym 24609 o_led0$SB_IO_OUT .sym 24659 i_sck$SB_IO_IN -.sym 24856 i_smi_swe_srw$SB_IO_IN -.sym 24861 i_rst_b$SB_IO_IN -.sym 24871 i_smi_soe_se$SB_IO_IN -.sym 24893 i_smi_soe_se$SB_IO_IN -.sym 24894 i_rst_b$SB_IO_IN -.sym 24916 i_smi_swe_srw$SB_IO_IN -.sym 24918 i_rst_b$SB_IO_IN -.sym 24943 i_rst_b$SB_IO_IN -.sym 25011 smi_ctrl_ins.tx_reg_state[2] -.sym 25012 w_smi_data_input[7] -.sym 25013 smi_ctrl_ins.tx_reg_state[0] -.sym 25014 i_rst_b$SB_IO_IN -.sym 25017 smi_ctrl_ins.tx_reg_state[3] -.sym 25019 i_ss$SB_IO_IN -.sym 25020 w_smi_data_input[7] -.sym 25022 i_rst_b$SB_IO_IN -.sym 25024 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 25026 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 25032 smi_ctrl_ins.swe_and_reset -.sym 25038 smi_ctrl_ins.tx_reg_state[1] -.sym 25041 i_ss$SB_IO_IN -.sym 25047 smi_ctrl_ins.tx_reg_state[1] -.sym 25048 w_smi_data_input[7] -.sym 25049 smi_ctrl_ins.tx_reg_state[2] -.sym 25052 smi_ctrl_ins.tx_reg_state[1] -.sym 25054 w_smi_data_input[7] -.sym 25055 i_rst_b$SB_IO_IN -.sym 25058 smi_ctrl_ins.tx_reg_state[3] -.sym 25059 i_rst_b$SB_IO_IN -.sym 25060 w_smi_data_input[7] -.sym 25061 smi_ctrl_ins.tx_reg_state[0] -.sym 25065 w_smi_data_input[7] -.sym 25066 smi_ctrl_ins.tx_reg_state[0] -.sym 25067 i_rst_b$SB_IO_IN -.sym 25071 i_rst_b$SB_IO_IN -.sym 25072 smi_ctrl_ins.tx_reg_state[3] -.sym 25073 smi_ctrl_ins.tx_reg_state[0] -.sym 25077 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 25079 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 25083 smi_ctrl_ins.tx_reg_state[2] -.sym 25084 i_rst_b$SB_IO_IN -.sym 25085 w_smi_data_input[7] -.sym 25087 smi_ctrl_ins.swe_and_reset -.sym 25167 w_smi_data_input[7] -.sym 25175 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 25187 smi_ctrl_ins.swe_and_reset -.sym 25225 w_smi_data_input[7] -.sym 25242 smi_ctrl_ins.swe_and_reset -.sym 25243 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 25328 i_rst_b_SB_LUT4_I3_O -.sym 25334 w_tx_fifo_empty -.sym 25353 w_tx_fifo_empty -.sym 25396 i_rst_b_SB_LUT4_I3_O -.sym 25397 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -.sym 25398 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 25401 io_pmod[7]$SB_IO_IN -.sym 25554 io_pmod[3]$SB_IO_IN +.sym 25408 io_pmod[0]$SB_IO_IN +.sym 25480 spi_if_ins.spi.r_rx_done +.sym 25496 i_smi_swe_srw$rename$0 +.sym 25498 spi_if_ins.spi.r2_rx_done +.sym 25499 spi_if_ins.spi.r3_rx_done +.sym 25502 smi_ctrl_ins.swe_and_reset +.sym 25508 i_smi_swe_srw$rename$0 +.sym 25511 smi_ctrl_ins.swe_and_reset +.sym 25518 spi_if_ins.spi.r_rx_done +.sym 25523 spi_if_ins.spi.r2_rx_done +.sym 25543 spi_if_ins.spi.r3_rx_done +.sym 25544 spi_if_ins.spi.r2_rx_done +.sym 25552 r_counter_$glb_clk +.sym 25554 i_smi_swe_srw$rename$0 .sym 25556 io_pmod[6]$SB_IO_IN -.sym 25641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 25643 spi_if_ins.spi.r3_rx_done -.sym 25648 spi_if_ins.spi.r2_rx_done -.sym 25649 spi_if_ins.spi.r_rx_done -.sym 25653 spi_if_ins.spi.SCKr[0] .sym 25655 i_sck$SB_IO_IN -.sym 25661 spi_if_ins.spi.r2_rx_done -.sym 25675 i_sck$SB_IO_IN -.sym 25680 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 25684 spi_if_ins.spi.r3_rx_done -.sym 25687 spi_if_ins.spi.r2_rx_done -.sym 25693 spi_if_ins.spi.r_rx_done -.sym 25699 spi_if_ins.spi.SCKr[0] +.sym 25702 i_sck$SB_IO_IN .sym 25707 r_counter_$glb_clk .sym 25711 i_glob_clock$SB_IO_IN -.sym 25725 $io_pmod[3]$iobuf_i -.sym 25782 i_sck$SB_IO_IN -.sym 25784 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 25785 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 25787 i_mosi$SB_IO_IN -.sym 25791 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 25793 o_miso_$_TBUF__Y_E -.sym 25796 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25806 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 25811 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 25817 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 25821 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 25828 i_mosi$SB_IO_IN -.sym 25836 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 25840 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25846 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 25854 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 25861 o_miso_$_TBUF__Y_E -.sym 25862 i_sck$SB_IO_IN +.sym 25724 $io_pmod[3]$iobuf_i +.sym 25797 spi_if_ins.spi.SCKr[0] +.sym 25813 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 25822 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 25858 spi_if_ins.spi.SCKr[0] +.sym 25862 r_counter_$glb_clk .sym 25878 i_glob_clock$SB_IO_IN -.sym 25880 smi_ctrl_ins.soe_and_reset -.sym 25938 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 25941 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 25943 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25948 i_rst_b$SB_IO_IN -.sym 25950 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 25953 i_sck$SB_IO_IN -.sym 25955 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 25970 i_rst_b$SB_IO_IN -.sym 25979 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 25982 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 25995 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 26006 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 26016 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 26017 i_sck$SB_IO_IN -.sym 26103 io_pmod_SB_DFFE_Q_E -.sym 26104 w_rx_data[3] -.sym 26164 w_rx_data[3] -.sym 26171 io_pmod_SB_DFFE_Q_E -.sym 26172 r_counter_$glb_clk -.sym 26174 io_pmod[2]$SB_IO_IN -.sym 26176 io_pmod[1]$SB_IO_IN -.sym 26258 io_pmod_SB_DFFE_Q_E -.sym 26263 w_rx_data[2] -.sym 26264 w_rx_data[1] -.sym 26265 w_rx_data[0] -.sym 26299 w_rx_data[2] -.sym 26312 w_rx_data[1] -.sym 26316 w_rx_data[0] -.sym 26326 io_pmod_SB_DFFE_Q_E -.sym 26327 r_counter_$glb_clk +.sym 25950 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 25957 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 25963 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 25964 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 25984 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 25990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26016 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 26017 r_counter_$glb_clk +.sym 26018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .sym 26329 io_pmod[0]$SB_IO_IN -.sym 26337 io_pmod[2]$SB_IO_IN -.sym 26407 w_rx_data[0] -.sym 26411 w_rx_data[3] -.sym 26413 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 26447 w_rx_data[3] -.sym 26479 w_rx_data[0] -.sym 26481 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 26482 r_counter_$glb_clk -.sym 26557 w_rx_data[0] -.sym 26563 w_rx_data[1] -.sym 26568 o_led1_SB_DFFER_Q_E -.sym 26592 w_rx_data[1] -.sym 26597 w_rx_data[0] -.sym 26636 o_led1_SB_DFFER_Q_E -.sym 26637 r_counter_$glb_clk -.sym 26638 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26648 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 26652 o_led1_SB_DFFER_Q_E -.sym 26731 o_rx_h_tx_l_b$SB_IO_OUT -.sym 26760 o_rx_h_tx_l_b$SB_IO_OUT -.sym 26810 o_tr_vc1$SB_IO_OUT -.sym 26960 o_tr_vc1_b$SB_IO_OUT -.sym 27275 i_rst_b$SB_IO_IN +.sym 26347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.sym 26410 lvds_clock +.sym 26472 lvds_clock +.sym 26488 lvds_clock +.sym 26648 o_rx_h_tx_l$SB_IO_OUT +.sym 26968 o_tr_vc1_b$SB_IO_OUT +.sym 27248 o_smi_read_req$SB_IO_OUT .sym 27283 o_smi_read_req$SB_IO_OUT -.sym 27301 o_smi_read_req$SB_IO_OUT -.sym 27365 io_pmod[3]$SB_IO_IN -.sym 27395 i_rst_b$SB_IO_IN +.sym 27292 o_smi_read_req$SB_IO_OUT +.sym 27365 io_pmod[0]$SB_IO_IN .sym 27397 i_glob_clock$SB_IO_IN .sym 27400 $io_pmod[3]$iobuf_i -.sym 27415 $io_pmod[3]$iobuf_i +.sym 27422 $io_pmod[3]$iobuf_i .sym 27429 smi_ctrl_ins.soe_and_reset -.sym 27453 smi_ctrl_ins.soe_and_reset -.sym 27459 i_rst_b_SB_LUT4_I3_O -.sym 27477 i_rst_b_SB_LUT4_I3_O -.sym 27514 i_rst_b$SB_IO_IN -.sym 27516 i_glob_clock$SB_IO_IN -.sym 27519 $io_pmod[2]$iobuf_i -.sym 27522 $io_pmod[1]$iobuf_i -.sym 27533 $io_pmod[1]$iobuf_i -.sym 27539 $io_pmod[2]$iobuf_i +.sym 27444 smi_ctrl_ins.soe_and_reset +.sym 27457 lvds_clock +.sym 27459 lvds_clock +.sym 27483 lvds_clock +.sym 27485 io_pmod[0]$SB_IO_IN +.sym 27514 io_pmod[0]$SB_IO_IN +.sym 27519 $PACKER_GND_NET +.sym 27522 $PACKER_GND_NET +.sym 27529 $PACKER_GND_NET +.sym 27537 $PACKER_GND_NET +.sym 27545 o_tr_vc1$SB_IO_OUT +.sym 27547 o_tr_vc2$SB_IO_OUT .sym 27549 $io_pmod[0]$iobuf_i .sym 27564 $io_pmod[0]$iobuf_i .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27591 o_rx_h_tx_l$SB_IO_OUT +.sym 27589 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27615 o_tr_vc2$SB_IO_OUT -.sym 27620 o_tr_vc1$SB_IO_OUT +.sym 27621 o_tr_vc2$SB_IO_OUT +.sym 27627 o_tr_vc1$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27642 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27643 o_tr_vc1_b$SB_IO_OUT -.sym 27716 w_rx_09_fifo_data[23] -.sym 27717 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27719 w_rx_09_fifo_data[22] -.sym 27720 w_rx_24_fifo_data[22] -.sym 27721 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27728 w_rx_09_fifo_data[27] -.sym 27729 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27732 w_rx_09_fifo_data[19] -.sym 27733 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27740 w_rx_09_fifo_data[21] -.sym 27741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27744 w_rx_09_fifo_data[25] -.sym 27745 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27748 w_rx_09_fifo_data[29] -.sym 27749 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27751 w_rx_09_fifo_data[26] -.sym 27752 w_rx_24_fifo_data[26] -.sym 27753 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27755 w_rx_09_fifo_data[24] -.sym 27756 w_rx_24_fifo_data[24] -.sym 27757 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27760 w_rx_09_fifo_data[24] -.sym 27761 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27764 w_rx_09_fifo_data[26] -.sym 27765 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27768 w_rx_09_fifo_data[22] -.sym 27769 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27772 w_rx_09_fifo_data[28] -.sym 27773 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27776 w_rx_09_fifo_data[20] -.sym 27777 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27780 w_rx_09_fifo_data[17] -.sym 27781 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27783 w_rx_24_fifo_data[16] -.sym 27784 w_rx_09_fifo_data[16] -.sym 27785 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27787 w_rx_09_fifo_data[18] -.sym 27788 w_rx_24_fifo_data[18] -.sym 27789 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27792 w_rx_09_fifo_data[15] -.sym 27793 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27796 w_rx_09_fifo_data[14] -.sym 27797 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27800 w_rx_09_fifo_data[16] -.sym 27801 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27803 w_rx_09_fifo_data[20] -.sym 27804 w_rx_24_fifo_data[20] -.sym 27805 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27808 w_rx_09_fifo_data[18] -.sym 27809 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27816 w_rx_24_fifo_data[14] -.sym 27817 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27820 w_rx_24_fifo_data[24] -.sym 27821 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27824 w_rx_24_fifo_data[16] -.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27828 w_rx_24_fifo_data[22] -.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27832 w_rx_24_fifo_data[18] -.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27837 o_iq_tx_clk_p$SB_IO_OUT -.sym 27840 w_rx_24_fifo_data[20] -.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27844 w_rx_09_fifo_data[9] -.sym 27845 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27852 w_rx_09_fifo_data[11] -.sym 27853 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27856 w_rx_09_fifo_data[12] -.sym 27857 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27864 w_rx_09_fifo_data[10] -.sym 27865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27868 w_rx_09_fifo_data[13] -.sym 27869 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27871 w_rx_09_fifo_data[14] -.sym 27872 w_rx_24_fifo_data[14] -.sym 27873 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27875 w_rx_09_fifo_data[6] -.sym 27876 w_rx_24_fifo_data[6] -.sym 27877 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27880 w_rx_24_fifo_data[4] -.sym 27881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27884 w_rx_24_fifo_data[8] -.sym 27885 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27888 w_rx_24_fifo_data[12] -.sym 27889 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27892 w_rx_24_fifo_data[5] -.sym 27893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27896 w_rx_24_fifo_data[10] -.sym 27897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27900 w_rx_24_fifo_data[7] -.sym 27901 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27904 w_rx_24_fifo_data[6] -.sym 27905 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 27907 w_rx_24_fifo_data[8] -.sym 27908 w_rx_09_fifo_data[8] -.sym 27909 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27912 w_rx_09_fifo_data[6] -.sym 27913 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27915 w_rx_09_fifo_data[10] -.sym 27916 w_rx_24_fifo_data[10] -.sym 27917 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 27924 w_rx_09_fifo_data[2] -.sym 27925 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27928 w_rx_09_fifo_data[8] -.sym 27929 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27932 w_rx_09_fifo_data[4] -.sym 27933 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27938 rx_fifo.rd_addr[9] -.sym 27950 rx_fifo.rd_addr_gray_wr[0] -.sym 27962 rx_fifo.rd_addr_gray_wr[9] -.sym 27980 w_rx_09_fifo_data[1] -.sym 27981 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 27996 i_rst_b$SB_IO_IN -.sym 27997 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 28003 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28004 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] -.sym 28005 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28008 w_lvds_rx_09_d0 -.sym 28009 w_lvds_rx_09_d1 -.sym 28012 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28013 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 28014 w_lvds_rx_09_d0 -.sym 28015 w_lvds_rx_09_d1 -.sym 28016 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28017 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28022 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.sym 28026 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28027 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28028 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28029 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28031 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28032 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28033 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28035 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 28038 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28039 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.sym 28040 $PACKER_VCC_NET -.sym 28041 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -.sym 28042 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28043 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28044 $PACKER_VCC_NET -.sym 28045 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 -.sym 28047 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28048 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28049 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28053 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28054 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28055 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] -.sym 28056 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] -.sym 28057 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28064 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28065 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.sym 28067 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 28070 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28071 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.sym 28072 $PACKER_VCC_NET -.sym 28073 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] -.sym 28074 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28075 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 28076 $PACKER_VCC_NET -.sym 28077 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 -.sym 28081 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28082 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28083 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28084 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28085 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28086 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 28087 rx_fifo.full_o_SB_LUT4_I1_I3[0] -.sym 28088 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] -.sym 28089 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 27641 o_tr_vc1_b$SB_IO_OUT +.sym 27646 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27715 w_rx_24_fifo_data[15] +.sym 27716 w_rx_09_fifo_data[15] +.sym 27717 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27720 w_rx_09_fifo_data[13] +.sym 27721 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27732 w_rx_09_fifo_data[11] +.sym 27733 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27744 w_rx_09_fifo_data[15] +.sym 27745 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27747 w_rx_09_fifo_data[9] +.sym 27748 w_rx_24_fifo_data[9] +.sym 27749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27751 w_rx_09_fifo_data[17] +.sym 27752 w_rx_24_fifo_data[17] +.sym 27753 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27756 w_rx_09_fifo_data[6] +.sym 27757 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27760 w_rx_09_fifo_data[9] +.sym 27761 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27764 w_rx_09_fifo_data[17] +.sym 27765 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27768 w_rx_09_fifo_data[7] +.sym 27769 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27772 w_rx_09_fifo_data[5] +.sym 27773 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27775 w_rx_09_fifo_data[11] +.sym 27776 w_rx_24_fifo_data[11] +.sym 27777 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27780 w_rx_24_fifo_data[7] +.sym 27781 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27784 w_rx_24_fifo_data[15] +.sym 27785 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27788 w_rx_24_fifo_data[13] +.sym 27789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27796 w_rx_24_fifo_data[17] +.sym 27797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27800 w_rx_24_fifo_data[11] +.sym 27801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27803 w_rx_24_fifo_data[19] +.sym 27804 w_rx_09_fifo_data[19] +.sym 27805 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27808 w_rx_24_fifo_data[9] +.sym 27809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27812 w_rx_24_fifo_data[21] +.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27815 w_rx_24_fifo_data[5] +.sym 27816 w_rx_09_fifo_data[5] +.sym 27817 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27819 w_rx_24_fifo_data[7] +.sym 27820 w_rx_09_fifo_data[7] +.sym 27821 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27824 w_rx_24_fifo_data[3] +.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27828 w_rx_24_fifo_data[23] +.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27832 w_rx_24_fifo_data[19] +.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27836 i_rst_b$SB_IO_IN +.sym 27837 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.sym 27840 w_rx_24_fifo_data[5] +.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 27844 w_rx_09_fifo_data[4] +.sym 27845 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27848 w_rx_09_fifo_data[23] +.sym 27849 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27852 w_rx_09_fifo_data[21] +.sym 27853 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27855 w_rx_24_fifo_data[23] +.sym 27856 w_rx_09_fifo_data[23] +.sym 27857 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27859 w_rx_09_fifo_data[21] +.sym 27860 w_rx_24_fifo_data[21] +.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27863 w_rx_09_fifo_data[27] +.sym 27864 w_rx_24_fifo_data[27] +.sym 27865 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 27868 w_rx_09_fifo_data[19] +.sym 27869 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27872 w_rx_09_fifo_data[25] +.sym 27873 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27876 w_rx_09_fifo_data[29] +.sym 27877 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27880 w_rx_09_fifo_data[27] +.sym 27881 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27884 w_rx_09_fifo_data[0] +.sym 27885 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27888 w_rx_09_fifo_data[1] +.sym 27889 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27892 w_rx_09_fifo_data[28] +.sym 27893 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27896 w_rx_09_fifo_data[2] +.sym 27897 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27900 w_rx_09_fifo_data[3] +.sym 27901 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27909 rx_fifo.wr_addr[0] +.sym 27910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 27914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 27933 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 27939 rx_fifo.wr_addr[1] +.sym 27944 rx_fifo.wr_addr[2] +.sym 27945 rx_fifo.wr_addr[1] +.sym 27948 rx_fifo.wr_addr[3] +.sym 27949 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 +.sym 27952 rx_fifo.wr_addr[4] +.sym 27953 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 +.sym 27956 rx_fifo.wr_addr[5] +.sym 27957 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 +.sym 27960 rx_fifo.wr_addr[6] +.sym 27961 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 +.sym 27964 rx_fifo.wr_addr[7] +.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 27968 rx_fifo.wr_addr[8] +.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 27972 rx_fifo.wr_addr[9] +.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 27975 rx_fifo.rd_addr_gray_wr_r[2] +.sym 27976 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.sym 27977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 27978 rx_fifo.rd_addr_gray_wr[6] +.sym 27982 rx_fifo.rd_addr_gray_wr_r[4] +.sym 27983 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 27984 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 27985 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] +.sym 27986 rx_fifo.rd_addr_gray_wr_r[5] +.sym 27987 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.sym 27988 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 27989 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 27991 rx_fifo.rd_addr_gray_wr_r[6] +.sym 27992 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 27993 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 27996 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 27997 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 27999 rx_fifo.rd_addr_gray_wr_r[3] +.sym 28000 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.sym 28001 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.sym 28002 rx_fifo.rd_addr_gray_wr[4] +.sym 28008 i_rst_b$SB_IO_IN +.sym 28009 w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.sym 28010 rx_fifo.rd_addr_gray[4] +.sym 28016 rx_fifo.rd_addr_gray_wr_r[5] +.sym 28017 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 28018 rx_fifo.rd_addr_gray_wr[2] +.sym 28024 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] +.sym 28025 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 28026 rx_fifo.rd_addr_gray_wr_r[6] +.sym 28027 rx_fifo.rd_addr_gray_wr_r[4] +.sym 28028 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28029 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28031 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28032 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28033 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28034 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28040 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28041 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28042 w_lvds_rx_09_d0 +.sym 28043 w_lvds_rx_09_d1 +.sym 28044 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28045 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28051 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28052 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28054 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.sym 28055 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] +.sym 28056 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] +.sym 28057 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] +.sym 28060 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28061 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.sym 28062 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 28063 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28064 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28065 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28068 rx_fifo.rd_addr_gray_wr_r[4] +.sym 28069 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28072 w_lvds_rx_24_d1 +.sym 28073 w_lvds_rx_24_d0 +.sym 28076 w_lvds_rx_09_d0 +.sym 28077 w_lvds_rx_09_d1 +.sym 28079 w_rx_fifo_full +.sym 28080 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28081 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28083 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28084 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28085 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28086 w_lvds_rx_24_d1 +.sym 28087 w_lvds_rx_24_d0 +.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28089 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q .sym 28090 w_lvds_rx_24_d1 .sym 28091 w_lvds_rx_24_d0 .sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28097 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] -.sym 28104 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28105 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28108 w_lvds_rx_24_d1 -.sym 28109 w_lvds_rx_24_d0 -.sym 28119 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28120 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28121 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28122 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28126 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28127 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28128 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28129 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28210 w_rx_fifo_pulled_data[25] -.sym 28218 w_rx_fifo_pulled_data[26] -.sym 28226 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 28227 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 28228 smi_ctrl_ins.int_cnt_rx[4] -.sym 28229 smi_ctrl_ins.int_cnt_rx[3] -.sym 28230 w_rx_fifo_pulled_data[18] -.sym 28238 w_rx_fifo_pulled_data[27] -.sym 28242 w_rx_fifo_pulled_data[24] -.sym 28246 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 28247 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 28248 smi_ctrl_ins.int_cnt_rx[4] -.sym 28249 smi_ctrl_ins.int_cnt_rx[3] -.sym 28254 w_rx_fifo_pulled_data[17] -.sym 28260 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 28261 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 28264 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 28265 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 28268 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 28269 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 28271 w_rx_24_fifo_data[19] -.sym 28272 w_rx_09_fifo_data[19] -.sym 28273 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28276 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 28277 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 28280 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 28281 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 28282 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 28283 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 28284 smi_ctrl_ins.int_cnt_rx[4] -.sym 28285 smi_ctrl_ins.int_cnt_rx[3] -.sym 28286 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 28287 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 28288 smi_ctrl_ins.int_cnt_rx[4] -.sym 28289 smi_ctrl_ins.int_cnt_rx[3] -.sym 28290 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 28291 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 28292 smi_ctrl_ins.int_cnt_rx[4] -.sym 28293 smi_ctrl_ins.int_cnt_rx[3] -.sym 28294 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 28295 smi_ctrl_ins.int_cnt_rx[4] -.sym 28296 smi_ctrl_ins.int_cnt_rx[3] -.sym 28297 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 28298 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 28299 smi_ctrl_ins.int_cnt_rx[4] -.sym 28300 smi_ctrl_ins.int_cnt_rx[3] -.sym 28301 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 28302 w_rx_fifo_pulled_data[19] -.sym 28306 w_rx_fifo_pulled_data[16] -.sym 28310 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 28311 smi_ctrl_ins.int_cnt_rx[4] -.sym 28312 smi_ctrl_ins.int_cnt_rx[3] -.sym 28313 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 28314 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 28315 smi_ctrl_ins.int_cnt_rx[4] -.sym 28316 smi_ctrl_ins.int_cnt_rx[3] -.sym 28317 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 28319 w_rx_09_fifo_data[17] -.sym 28320 w_rx_24_fifo_data[17] -.sym 28321 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28322 w_rx_fifo_pulled_data[13] -.sym 28326 w_rx_fifo_pulled_data[8] -.sym 28330 w_rx_fifo_pulled_data[10] -.sym 28334 w_rx_fifo_pulled_data[15] -.sym 28338 w_rx_fifo_pulled_data[3] -.sym 28342 w_rx_fifo_pulled_data[6] -.sym 28356 w_rx_24_fifo_data[15] -.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28360 w_rx_24_fifo_data[9] -.sym 28361 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28363 w_rx_09_fifo_data[11] -.sym 28364 w_rx_24_fifo_data[11] -.sym 28365 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28368 i_rst_b$SB_IO_IN -.sym 28369 w_lvds_rx_24_d1_SB_LUT4_I0_O[1] -.sym 28372 w_rx_24_fifo_data[13] -.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28376 w_rx_24_fifo_data[17] -.sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28380 w_rx_24_fifo_data[11] -.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28383 w_rx_09_fifo_data[9] -.sym 28384 w_rx_24_fifo_data[9] -.sym 28385 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28387 w_rx_09_fifo_data[5] -.sym 28388 w_rx_24_fifo_data[5] -.sym 28389 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28392 w_rx_09_fifo_data[5] -.sym 28393 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28395 w_rx_24_fifo_data[12] -.sym 28396 w_rx_09_fifo_data[12] -.sym 28397 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28399 w_rx_24_fifo_data[15] -.sym 28400 w_rx_09_fifo_data[15] -.sym 28401 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28404 w_rx_09_fifo_data[3] -.sym 28405 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28408 w_rx_09_fifo_data[7] -.sym 28409 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28411 w_rx_24_fifo_data[13] -.sym 28412 w_rx_09_fifo_data[13] -.sym 28413 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28415 w_rx_09_fifo_data[7] -.sym 28416 w_rx_24_fifo_data[7] -.sym 28417 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28419 w_rx_24_fifo_data[4] -.sym 28420 w_rx_09_fifo_data[4] -.sym 28421 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28423 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 28424 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 28425 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 28426 w_rx_fifo_full -.sym 28427 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28428 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 28429 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28438 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28439 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28440 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 28441 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 28446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 28447 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 28448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 28449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 28450 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28451 rx_fifo.wr_addr[1] -.sym 28452 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28453 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 28455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 28456 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 28457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] -.sym 28464 w_rx_24_fifo_data[2] -.sym 28465 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 28467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 28468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 28469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 28470 rx_fifo.rd_addr_gray_wr_r[9] -.sym 28471 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28472 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 28473 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.sym 28476 w_rx_24_fifo_data[3] -.sym 28477 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28479 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] -.sym 28480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28481 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] -.sym 28482 w_rx_fifo_pulled_data[0] -.sym 28486 w_rx_fifo_pulled_data[11] -.sym 28490 w_rx_fifo_pulled_data[14] -.sym 28499 w_rx_09_fifo_data[3] -.sym 28500 w_rx_24_fifo_data[3] -.sym 28501 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28502 w_rx_fifo_pulled_data[1] -.sym 28506 w_rx_fifo_pulled_data[9] -.sym 28510 w_rx_fifo_pulled_data[2] -.sym 28516 w_rx_24_fifo_data[0] -.sym 28517 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28523 w_rx_09_fifo_data[0] -.sym 28524 w_rx_24_fifo_data[0] -.sym 28525 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28530 w_lvds_rx_09_d0 -.sym 28531 w_lvds_rx_09_d1 -.sym 28532 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28533 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28535 w_rx_24_fifo_data[2] -.sym 28536 w_rx_09_fifo_data[2] -.sym 28537 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28539 w_rx_24_fifo_data[1] -.sym 28540 w_rx_09_fifo_data[1] -.sym 28541 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28544 w_rx_24_fifo_data[1] -.sym 28545 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28549 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] -.sym 28552 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28553 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28562 w_lvds_rx_09_d0 -.sym 28567 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28568 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 28569 w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -.sym 28571 w_lvds_rx_09_d1 -.sym 28572 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28573 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 28590 w_lvds_rx_24_d1 -.sym 28591 w_lvds_rx_24_d0 -.sym 28592 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28593 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28598 w_lvds_rx_24_d1 -.sym 28599 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28600 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28601 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28609 w_lvds_rx_24_d0 -.sym 28612 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28613 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28615 w_rx_fifo_full -.sym 28616 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] -.sym 28617 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28636 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 28637 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28668 w_rx_fifo_full -.sym 28669 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 28739 w_rx_09_fifo_data[21] -.sym 28740 w_rx_24_fifo_data[21] -.sym 28741 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28744 w_rx_24_fifo_data[21] -.sym 28745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28747 w_rx_09_fifo_data[23] -.sym 28748 w_rx_24_fifo_data[23] -.sym 28749 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28751 w_rx_24_fifo_data[25] -.sym 28752 w_rx_09_fifo_data[25] -.sym 28753 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28756 w_rx_24_fifo_data[25] -.sym 28757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28759 w_rx_09_fifo_data[27] -.sym 28760 w_rx_24_fifo_data[27] -.sym 28761 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28764 w_rx_24_fifo_data[23] -.sym 28765 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28768 w_rx_24_fifo_data[27] -.sym 28769 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28771 w_rx_09_fifo_data[31] -.sym 28772 w_rx_24_fifo_data[31] -.sym 28773 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28776 w_rx_24_fifo_data[26] -.sym 28777 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28780 w_rx_24_fifo_data[28] -.sym 28781 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28783 w_rx_24_fifo_data[28] -.sym 28784 w_rx_09_fifo_data[28] -.sym 28785 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28788 w_rx_24_fifo_data[19] -.sym 28789 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28791 w_rx_09_fifo_data[29] -.sym 28792 w_rx_24_fifo_data[29] -.sym 28793 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28796 w_rx_24_fifo_data[29] -.sym 28797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28799 w_rx_09_fifo_data[30] -.sym 28800 w_rx_24_fifo_data[30] -.sym 28801 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 28806 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 28807 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 28808 smi_ctrl_ins.int_cnt_rx[4] -.sym 28809 smi_ctrl_ins.int_cnt_rx[3] -.sym 28814 w_rx_fifo_pulled_data[5] -.sym 28818 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 28819 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 28820 smi_ctrl_ins.int_cnt_rx[4] -.sym 28821 smi_ctrl_ins.int_cnt_rx[3] -.sym 28822 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 28823 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 28824 smi_ctrl_ins.int_cnt_rx[4] -.sym 28825 smi_ctrl_ins.int_cnt_rx[3] -.sym 28826 w_rx_fifo_pulled_data[7] -.sym 28830 w_rx_fifo_pulled_data[4] -.sym 28835 rx_fifo.wr_addr[0] -.sym 28840 rx_fifo.wr_addr[1] -.sym 28841 rx_fifo.wr_addr[0] -.sym 28844 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 28845 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 28848 rx_fifo.wr_addr[3] -.sym 28849 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 28852 rx_fifo.wr_addr[4] -.sym 28853 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 28856 rx_fifo.wr_addr[5] -.sym 28857 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28860 rx_fifo.wr_addr[6] -.sym 28861 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28864 rx_fifo.wr_addr[7] -.sym 28865 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 28868 rx_fifo.wr_addr[8] -.sym 28869 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 28872 rx_fifo.wr_addr[9] -.sym 28873 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 28875 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 28876 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28877 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28878 rx_fifo.wr_addr_gray[0] -.sym 28883 rx_fifo.rd_addr_gray_wr_r[6] -.sym 28884 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28885 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28886 rx_fifo.wr_addr_gray_rd[5] -.sym 28892 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28893 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 28894 rx_fifo.wr_addr_gray[5] -.sym 28898 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28902 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28903 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28904 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28905 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 28906 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28910 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -.sym 28911 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 28912 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 28913 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 28914 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 28918 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 28925 rx_fifo.wr_addr[1] -.sym 28928 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 28929 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 28932 i_rst_b$SB_IO_IN -.sym 28933 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -.sym 28935 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -.sym 28936 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 28937 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 28938 rx_fifo.rd_addr_gray_wr_r[7] -.sym 28939 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 28940 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 28941 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 28944 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28945 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28946 w_rx_fifo_pulled_data[12] -.sym 28950 rx_fifo.rd_addr_gray_wr_r[6] -.sym 28951 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 28952 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28953 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 28954 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 28955 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 28956 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 28957 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 28960 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 28961 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28964 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 28965 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28969 rx_fifo.rd_addr[8] -.sym 28970 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28974 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28980 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28981 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 28984 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 28985 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28986 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28990 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28994 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28995 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 28996 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28997 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28998 rx_fifo.rd_addr_gray_wr_r[7] -.sym 28999 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29000 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 29001 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 29002 rx_fifo.rd_addr_gray_wr[8] -.sym 29006 rx_fifo.rd_addr_gray[7] -.sym 29010 rx_fifo.rd_addr_gray[6] -.sym 29014 rx_fifo.rd_addr_gray[0] -.sym 29018 rx_fifo.rd_addr_gray_wr[6] -.sym 29022 rx_fifo.rd_addr_gray_wr[7] -.sym 29026 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29030 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29040 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29041 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29042 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29048 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29049 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29050 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 29054 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29060 w_rx_09_fifo_data[0] -.sym 29061 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29222 w_rx_fifo_pulled_data[20] -.sym 29230 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29231 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29232 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29233 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29234 w_rx_fifo_pulled_data[22] -.sym 29238 w_rx_fifo_pulled_data[23] -.sym 29246 w_rx_fifo_pulled_data[21] -.sym 29250 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 29251 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 29252 smi_ctrl_ins.int_cnt_rx[4] -.sym 29253 smi_ctrl_ins.int_cnt_rx[3] -.sym 29254 w_rx_fifo_pulled_data[28] -.sym 29258 w_rx_fifo_pulled_data[30] -.sym 29266 w_rx_fifo_pulled_data[29] -.sym 29270 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 29271 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 29272 smi_ctrl_ins.int_cnt_rx[4] -.sym 29273 smi_ctrl_ins.int_cnt_rx[3] -.sym 29274 w_rx_fifo_pulled_data[31] -.sym 29278 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 29279 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 29280 smi_ctrl_ins.int_cnt_rx[4] -.sym 29281 smi_ctrl_ins.int_cnt_rx[3] -.sym 29282 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29288 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29289 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29290 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 29296 i_rst_b$SB_IO_IN -.sym 29297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 29298 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 29302 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29306 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 29307 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 29308 smi_ctrl_ins.int_cnt_rx[4] -.sym 29309 smi_ctrl_ins.int_cnt_rx[3] -.sym 29316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 29320 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 29321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 29322 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 29323 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 29324 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 29325 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 29328 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 29330 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 29331 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] -.sym 29332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -.sym 29333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 29334 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 29335 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 29336 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 29337 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 29338 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 29339 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 29340 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 29341 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 29344 smi_ctrl_ins.int_cnt_rx[4] -.sym 29345 smi_ctrl_ins.int_cnt_rx[3] -.sym 29346 rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.sym 29352 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29353 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 29354 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 29358 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29359 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 29360 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 29361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 29365 rx_fifo.rd_addr[0] -.sym 29366 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29370 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] -.sym 29374 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29381 rx_fifo.wr_addr[0] -.sym 29383 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 29384 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29385 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29388 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29389 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29390 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29394 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 29395 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] -.sym 29396 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] -.sym 29397 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 29400 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 29401 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29403 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 29404 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29405 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29406 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29411 rx_fifo.wr_addr[1] -.sym 29416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -.sym 29417 rx_fifo.wr_addr[1] -.sym 29420 rx_fifo.wr_addr[3] -.sym 29421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 -.sym 29424 rx_fifo.wr_addr[4] -.sym 29425 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29428 rx_fifo.wr_addr[5] -.sym 29429 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 29432 rx_fifo.wr_addr[6] -.sym 29433 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 29436 rx_fifo.wr_addr[7] -.sym 29437 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 29440 rx_fifo.wr_addr[8] -.sym 29441 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29444 rx_fifo.wr_addr[9] -.sym 29445 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 -.sym 29446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -.sym 29447 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 29448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.sym 29449 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] -.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29453 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 29454 w_rx_data[5] -.sym 29458 rx_fifo.rd_addr_gray_wr_r[6] -.sym 29459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -.sym 29460 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 29461 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 29462 w_rx_data[0] -.sym 29467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 29468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 29469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.sym 29471 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 29472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 29473 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.sym 29474 rx_fifo.wr_addr_gray_rd[4] -.sym 29478 rx_fifo.wr_addr_gray[4] -.sym 29490 rx_fifo.wr_addr_gray[2] -.sym 29496 rx_fifo.rd_addr[8] -.sym 29497 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 29498 rx_fifo.rd_addr[7] -.sym 29499 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 29500 rx_fifo.rd_addr[6] -.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] -.sym 29502 rx_fifo.wr_addr_gray_rd[2] -.sym 29509 rx_fifo.rd_addr[1] -.sym 29510 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.sym 29516 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -.sym 29517 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29518 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.sym 29522 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.sym 29538 rx_fifo.wr_addr_gray[6] -.sym 29542 rx_fifo.wr_addr_gray_rd[6] -.sym 29546 rx_fifo.wr_addr_gray_rd[3] -.sym 29550 rx_fifo.wr_addr[9] -.sym 29554 rx_fifo.wr_addr_gray[1] -.sym 29558 rx_fifo.wr_addr_gray[3] -.sym 29562 rx_fifo.wr_addr_gray_rd[1] -.sym 29566 rx_fifo.wr_addr_gray_rd[9] -.sym 29570 rx_fifo.wr_addr_gray_rd[7] -.sym 29574 rx_fifo.wr_addr_gray_rd[8] -.sym 29590 rx_fifo.wr_addr_gray[8] -.sym 29594 rx_fifo.wr_addr_gray[7] -.sym 29602 rx_fifo.rd_addr_gray[4] -.sym 29606 rx_fifo.rd_addr_gray_wr[1] -.sym 29630 rx_fifo.rd_addr_gray[1] -.sym 29725 w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -.sym 29734 tx_fifo.wr_addr_gray[6] -.sym 29738 tx_fifo.wr_addr_gray[2] -.sym 29746 tx_fifo.wr_addr_gray_rd[5] -.sym 29757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 29758 tx_fifo.wr_addr_gray[5] -.sym 29762 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29763 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29764 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29766 tx_fifo.wr_addr_gray[4] -.sym 29770 tx_fifo.wr_addr_gray[3] -.sym 29775 i_rst_b$SB_IO_IN -.sym 29776 smi_ctrl_ins.int_cnt_rx[4] -.sym 29777 smi_ctrl_ins.int_cnt_rx[3] -.sym 29778 tx_fifo.wr_addr_gray_rd[6] -.sym 29784 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 29785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 29790 tx_fifo.wr_addr_gray_rd[4] -.sym 29802 tx_fifo.wr_addr[9] -.sym 29806 tx_fifo.wr_addr_gray_rd[3] -.sym 29814 tx_fifo.wr_addr_gray_rd[2] -.sym 29818 tx_fifo.wr_addr_gray_rd[1] -.sym 29822 tx_fifo.wr_addr_gray_rd[9] -.sym 29826 smi_ctrl_ins.r_fifo_pull -.sym 29830 smi_ctrl_ins.w_fifo_pull_trigger -.sym 29836 rx_fifo.rd_addr[1] -.sym 29837 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 29838 smi_ctrl_ins.w_fifo_push_trigger -.sym 29843 w_rx_fifo_empty -.sym 29844 smi_ctrl_ins.r_fifo_pull_1 -.sym 29845 smi_ctrl_ins.r_fifo_pull -.sym 29847 rx_fifo.rd_addr[3] -.sym 29848 rx_fifo.rd_addr[2] -.sym 29849 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 29852 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29853 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] -.sym 29854 smi_ctrl_ins.r_fifo_push -.sym 29859 w_tx_fifo_full -.sym 29860 smi_ctrl_ins.r_fifo_push_1 -.sym 29861 smi_ctrl_ins.r_fifo_push -.sym 29863 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 29864 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29865 rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -.sym 29866 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 29867 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 29868 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 29869 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 29870 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 29871 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 29872 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 29873 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 29875 rx_fifo.rd_addr[2] -.sym 29876 rx_fifo.rd_addr[1] -.sym 29877 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29878 rx_fifo.rd_addr[2] -.sym 29879 rx_fifo.rd_addr[1] -.sym 29880 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] -.sym 29881 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 29884 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29885 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 29886 w_rx_fifo_empty -.sym 29887 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] -.sym 29888 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] -.sym 29889 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] -.sym 29891 rx_fifo.rd_addr[0] -.sym 29896 rx_fifo.rd_addr[1] -.sym 29897 rx_fifo.rd_addr[0] -.sym 29900 rx_fifo.rd_addr[2] -.sym 29901 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 29904 rx_fifo.rd_addr[3] -.sym 29905 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 29908 rx_fifo.rd_addr[4] -.sym 29909 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29912 rx_fifo.rd_addr[5] -.sym 29913 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29916 rx_fifo.rd_addr[6] -.sym 29917 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 29920 rx_fifo.rd_addr[7] -.sym 29921 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29924 rx_fifo.rd_addr[8] -.sym 29925 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 29928 rx_fifo.rd_addr[9] -.sym 29929 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 29930 rx_fifo.rd_addr[5] -.sym 29931 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 29932 rx_fifo.rd_addr[4] -.sym 29933 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 29934 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] -.sym 29935 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] -.sym 29936 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] -.sym 29937 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] -.sym 29938 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 29942 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29946 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29950 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29956 rx_fifo.rd_addr[6] -.sym 29957 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 29958 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29959 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 29960 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 29962 rx_fifo.rd_addr[4] -.sym 29963 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 29964 rx_fifo.rd_addr[2] -.sym 29965 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -.sym 29967 rx_fifo.rd_addr[5] -.sym 29968 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] -.sym 29969 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] -.sym 29972 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 29973 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29974 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] -.sym 29975 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.sym 29976 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] -.sym 29977 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.sym 29978 rx_fifo.rd_addr_gray[5] -.sym 29982 rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -.sym 29983 rx_fifo.rd_addr[9] -.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29985 rx_fifo.rd_addr[8] -.sym 29986 rx_fifo.rd_addr_gray_wr[3] -.sym 29990 rx_fifo.rd_addr_gray_wr[5] -.sym 29996 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] -.sym 29997 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] -.sym 29998 rx_fifo.rd_addr_gray_wr[4] -.sym 30002 rx_fifo.rd_addr_gray[3] -.sym 30006 rx_fifo.rd_addr_gray[8] -.sym 30010 rx_fifo.rd_addr_gray_wr[2] -.sym 30014 rx_fifo.rd_addr_gray[2] -.sym 30033 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 30042 rx_fifo.rd_addr[4] -.sym 30043 rx_fifo.rd_addr[3] -.sym 30044 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] -.sym 30045 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.sym 30047 io_pmod[6]$SB_IO_IN -.sym 30048 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30049 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30052 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 30053 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30059 io_pmod[7]$SB_IO_IN -.sym 30060 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30061 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30062 rx_fifo.rd_addr[8] -.sym 30063 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -.sym 30064 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] -.sym 30065 rx_fifo.rd_addr[6] -.sym 30082 w_rx_data[4] -.sym 30094 w_rx_data[6] -.sym 30098 w_rx_data[7] -.sym 30102 w_rx_data[3] -.sym 30106 w_rx_data[1] -.sym 30110 w_rx_data[2] -.sym 30116 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30117 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30120 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] -.sym 30121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30124 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30125 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30136 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] -.sym 30137 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30140 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30144 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] -.sym 30145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30147 o_rx_h_tx_l_b$SB_IO_OUT -.sym 30148 i_button_SB_LUT4_I0_O[1] -.sym 30149 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 30151 o_rx_h_tx_l$SB_IO_OUT -.sym 30152 i_button_SB_LUT4_I0_O[1] -.sym 30153 i_button_SB_LUT4_I0_O[2] -.sym 30165 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 30175 o_tr_vc1$SB_IO_OUT -.sym 30176 i_button_SB_LUT4_I0_O[1] -.sym 30177 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 30178 i_button$SB_IO_IN -.sym 30179 io_ctrl_ins.pmod_dir_state[7] -.sym 30180 o_led1_SB_LUT4_I1_I3[3] -.sym 30181 o_led1_SB_LUT4_I1_I2[2] -.sym 30182 i_config[2]$SB_IO_IN -.sym 30183 io_ctrl_ins.pmod_dir_state[5] -.sym 30184 o_led1_SB_LUT4_I1_I3[3] -.sym 30185 o_led1_SB_LUT4_I1_I2[2] -.sym 30190 w_rx_data[6] -.sym 30198 w_rx_data[7] -.sym 30202 i_config[3]$SB_IO_IN -.sym 30203 io_ctrl_ins.pmod_dir_state[6] -.sym 30204 o_led1_SB_LUT4_I1_I3[3] -.sym 30205 o_led1_SB_LUT4_I1_I2[2] -.sym 30206 w_rx_data[5] -.sym 30245 tx_fifo.wr_addr[0] -.sym 30246 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30250 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 30256 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 30257 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30258 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 30268 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30269 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 30270 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 30276 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 30277 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 30279 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 30280 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30281 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30282 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 30295 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 30296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30297 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30300 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30301 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30304 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30305 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 30312 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 30313 tx_fifo.rd_addr[2] -.sym 30314 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 30315 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 30316 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 30317 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 30320 smi_ctrl_ins.int_cnt_rx[4] -.sym 30321 smi_ctrl_ins.int_cnt_rx[3] -.sym 30325 smi_ctrl_ins.int_cnt_rx[3] -.sym 30330 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30331 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 30332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 30335 tx_fifo.rd_addr[2] -.sym 30336 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 30337 tx_fifo.rd_addr[1] -.sym 30340 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 30341 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 30342 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 30343 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 30344 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -.sym 30345 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.sym 30348 i_rst_b$SB_IO_IN -.sym 30349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 30350 tx_fifo.rd_addr_gray_wr[1] -.sym 30355 tx_fifo.rd_addr[2] -.sym 30356 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 30357 tx_fifo.rd_addr[1] -.sym 30358 rx_fifo.wr_addr_gray_rd[0] -.sym 30362 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 30363 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 30364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30366 tx_fifo.rd_addr_gray[1] -.sym 30371 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 30372 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 30373 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 30376 tx_fifo.rd_addr[8] -.sym 30377 tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -.sym 30382 tx_fifo.rd_addr[9] -.sym 30383 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 30384 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 30385 tx_fifo.rd_addr[8] -.sym 30386 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30393 tx_fifo.wr_addr[1] -.sym 30396 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 30397 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 30400 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 30401 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 30402 tx_fifo.wr_addr_gray[8] -.sym 30406 tx_fifo.wr_addr_gray_rd[8] -.sym 30414 tx_fifo.wr_addr_gray_rd[0] -.sym 30418 tx_fifo.wr_addr_gray_rd[7] -.sym 30426 tx_fifo.wr_addr_gray[7] -.sym 30430 tx_fifo.wr_addr_gray[0] -.sym 30434 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] -.sym 30444 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.sym 30445 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30446 w_tx_fifo_full -.sym 30454 w_rx_fifo_empty -.sym 30460 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30461 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 30468 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] -.sym 30469 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] -.sym 30472 i_rst_b$SB_IO_IN -.sym 30473 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30490 w_rx_data[0] -.sym 30495 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30496 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30497 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30500 spi_if_ins.state_if[1] -.sym 30501 spi_if_ins.state_if[0] -.sym 30502 spi_if_ins.w_rx_data[4] -.sym 30507 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30508 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30509 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30511 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30512 spi_if_ins.state_if[1] -.sym 30513 spi_if_ins.state_if[0] -.sym 30514 spi_if_ins.w_rx_data[5] -.sym 30518 i_rst_b$SB_IO_IN -.sym 30519 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30521 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30522 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 30527 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30528 spi_if_ins.state_if[1] -.sym 30529 spi_if_ins.state_if[0] -.sym 30531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30532 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30533 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30534 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 30539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30540 spi_if_ins.state_if[1] -.sym 30541 spi_if_ins.state_if[0] -.sym 30544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30547 i_rst_b$SB_IO_IN -.sym 30548 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30549 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30551 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 30552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30553 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 30554 i_rst_b$SB_IO_IN -.sym 30555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 30556 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30557 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30558 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30566 w_cs[2] -.sym 30567 w_fetch -.sym 30568 w_load -.sym 30569 o_led1_SB_LUT4_I1_I2[1] -.sym 30574 w_cs[2] -.sym 30575 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30576 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 30577 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 30578 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30579 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30580 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 30581 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 30583 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30584 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30585 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 30588 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30589 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30594 w_rx_data[2] -.sym 30599 w_fetch -.sym 30600 w_cs[0] -.sym 30601 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 30604 i_rst_b$SB_IO_IN -.sym 30605 w_fetch -.sym 30607 w_fetch -.sym 30608 w_load -.sym 30609 w_cs[0] -.sym 30615 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30616 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30617 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 30618 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30619 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30620 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 30621 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 30622 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 30623 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30624 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 30625 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 30626 w_cs[1] -.sym 30627 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 30628 o_led1_SB_LUT4_I1_I2[1] -.sym 30629 o_led1_SB_LUT4_I1_I2[2] -.sym 30630 w_rx_data[1] -.sym 30637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 30642 w_cs[3] -.sym 30643 w_cs[2] -.sym 30644 w_cs[1] -.sym 30645 w_cs[0] -.sym 30650 w_rx_data[4] -.sym 30659 w_tx_data_io[5] -.sym 30660 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30661 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 30664 spi_if_ins.w_rx_data[6] -.sym 30665 spi_if_ins.w_rx_data[5] -.sym 30668 spi_if_ins.w_rx_data[6] -.sym 30669 spi_if_ins.w_rx_data[5] -.sym 30675 w_tx_data_io[7] -.sym 30676 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30677 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 30678 w_tx_data_smi[1] -.sym 30679 w_tx_data_io[1] -.sym 30680 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 30681 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30686 w_tx_data_io[2] -.sym 30687 w_tx_data_smi[2] -.sym 30688 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 30689 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30694 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 30695 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30696 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 30697 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 30699 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 30700 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30701 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 30703 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 30704 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30705 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 30706 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 30707 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 30708 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30709 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30714 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 30715 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 30716 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30717 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30719 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 30720 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30721 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 30725 r_counter -.sym 30741 i_config[3]$SB_IO_IN -.sym 30745 i_button$SB_IO_IN -.sym 30755 tx_fifo.rd_addr[0] -.sym 30760 tx_fifo.rd_addr[1] -.sym 30761 tx_fifo.rd_addr[0] -.sym 30764 tx_fifo.rd_addr[2] -.sym 30765 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30768 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 30769 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 -.sym 30772 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 30773 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 -.sym 30776 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 30777 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 30780 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 30781 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30784 tx_fifo.rd_addr[7] -.sym 30785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 30788 tx_fifo.rd_addr[8] -.sym 30789 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30792 tx_fifo.rd_addr[9] -.sym 30793 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 -.sym 30795 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 30796 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 30800 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 30801 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 30802 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 30813 tx_fifo.rd_addr[0] -.sym 30814 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30818 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 30819 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 30820 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 30821 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 30822 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30823 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 30824 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 30825 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] -.sym 30826 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 30827 tx_fifo.rd_addr[1] -.sym 30828 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 30829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30830 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30831 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.sym 30832 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.sym 30833 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.sym 30834 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 30835 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 30836 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 30837 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 30839 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 30840 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 30841 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 30843 tx_fifo.rd_addr_gray_wr_r[8] -.sym 30844 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 30845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 30848 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30849 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30850 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -.sym 30854 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] -.sym 30855 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] -.sym 30856 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] -.sym 30857 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] -.sym 30858 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.sym 30863 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] -.sym 30864 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] -.sym 30865 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 30866 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 30871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 30872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -.sym 30873 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 30874 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] -.sym 30875 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 30876 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -.sym 30877 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 30878 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 30882 tx_fifo.empty_o_SB_LUT4_I0_O[0] -.sym 30883 tx_fifo.empty_o_SB_LUT4_I0_O[1] -.sym 30884 tx_fifo.empty_o_SB_LUT4_I0_O[2] -.sym 30885 tx_fifo.empty_o_SB_LUT4_I0_O[3] -.sym 30887 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 30888 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 30889 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30890 tx_fifo.wr_addr_gray[1] -.sym 30894 w_tx_fifo_empty -.sym 30895 w_tx_fifo_pull -.sym 30896 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 30897 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 30901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] -.sym 30906 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -.sym 30907 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -.sym 30908 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] -.sym 30909 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] -.sym 30910 tx_fifo.rd_addr[7] -.sym 30911 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -.sym 30912 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -.sym 30913 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.sym 30914 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 30918 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30922 tx_fifo.rd_addr[9] -.sym 30923 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] -.sym 30924 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 30925 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30927 w_tx_fifo_pull -.sym 30928 tx_fifo.rd_addr[1] -.sym 30929 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] -.sym 30933 tx_fifo.rd_addr[1] -.sym 30934 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.sym 30938 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.sym 30944 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30945 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.sym 30947 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30951 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 30952 $PACKER_VCC_NET -.sym 30955 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 30956 $PACKER_VCC_NET -.sym 30957 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 30959 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 30960 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 30961 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 30963 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 30964 $PACKER_VCC_NET -.sym 30965 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30967 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 30968 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 30969 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30977 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30978 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30983 spi_if_ins.spi.r_tx_byte[1] -.sym 30984 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30985 spi_if_ins.spi.r_tx_byte[0] -.sym 30989 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 30993 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30994 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30995 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30996 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30998 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 30999 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 31000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] -.sym 31001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] -.sym 31005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31006 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -.sym 31007 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -.sym 31008 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] -.sym 31009 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28096 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28097 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28100 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 28101 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28110 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28111 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28112 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28113 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28115 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28116 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28117 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28118 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28119 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28120 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28121 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28123 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28124 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28125 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.sym 28131 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 28134 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28135 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] +.sym 28136 $PACKER_VCC_NET +.sym 28137 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.sym 28138 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28139 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 28140 $PACKER_VCC_NET +.sym 28141 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 +.sym 28145 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 28146 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 28147 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 28148 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 28149 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28150 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 28151 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 +.sym 28152 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.sym 28153 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28157 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 +.sym 28160 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28161 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] +.sym 28227 w_rx_24_fifo_data[13] +.sym 28228 w_rx_09_fifo_data[13] +.sym 28229 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28231 w_rx_09_fifo_data[14] +.sym 28232 w_rx_24_fifo_data[14] +.sym 28233 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28236 w_rx_09_fifo_data[8] +.sym 28237 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28239 w_rx_09_fifo_data[12] +.sym 28240 w_rx_24_fifo_data[12] +.sym 28241 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28244 w_rx_09_fifo_data[10] +.sym 28245 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28248 w_rx_09_fifo_data[16] +.sym 28249 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28252 w_rx_09_fifo_data[12] +.sym 28253 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28256 w_rx_09_fifo_data[14] +.sym 28257 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28260 w_rx_09_fifo_data[18] +.sym 28261 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28263 w_rx_09_fifo_data[16] +.sym 28264 w_rx_24_fifo_data[16] +.sym 28265 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28268 w_rx_09_fifo_data[24] +.sym 28269 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28271 w_rx_09_fifo_data[8] +.sym 28272 w_rx_24_fifo_data[8] +.sym 28273 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28276 w_rx_09_fifo_data[26] +.sym 28277 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28280 w_rx_09_fifo_data[20] +.sym 28281 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28284 w_rx_09_fifo_data[22] +.sym 28285 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28287 w_rx_09_fifo_data[18] +.sym 28288 w_rx_24_fifo_data[18] +.sym 28289 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28296 w_rx_24_fifo_data[16] +.sym 28297 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28299 w_rx_09_fifo_data[10] +.sym 28300 w_rx_24_fifo_data[10] +.sym 28301 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28304 w_rx_24_fifo_data[8] +.sym 28305 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28308 w_rx_24_fifo_data[6] +.sym 28309 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28312 w_rx_24_fifo_data[12] +.sym 28313 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28316 w_rx_24_fifo_data[14] +.sym 28317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28320 w_rx_24_fifo_data[10] +.sym 28321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28323 w_rx_24_fifo_data[4] +.sym 28324 w_rx_09_fifo_data[4] +.sym 28325 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28327 w_rx_09_fifo_data[26] +.sym 28328 w_rx_24_fifo_data[26] +.sym 28329 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28332 w_rx_24_fifo_data[4] +.sym 28333 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28335 w_rx_24_fifo_data[25] +.sym 28336 w_rx_09_fifo_data[25] +.sym 28337 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28339 w_rx_09_fifo_data[6] +.sym 28340 w_rx_24_fifo_data[6] +.sym 28341 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28344 w_rx_24_fifo_data[25] +.sym 28345 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28348 w_rx_24_fifo_data[2] +.sym 28349 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28352 w_rx_24_fifo_data[18] +.sym 28353 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28356 w_rx_24_fifo_data[27] +.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28359 w_rx_09_fifo_data[22] +.sym 28360 w_rx_24_fifo_data[22] +.sym 28361 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28364 w_rx_24_fifo_data[20] +.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28367 w_rx_24_fifo_data[20] +.sym 28368 w_rx_09_fifo_data[20] +.sym 28369 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28372 w_rx_24_fifo_data[1] +.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28376 w_rx_24_fifo_data[29] +.sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28380 w_rx_24_fifo_data[0] +.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28384 w_rx_24_fifo_data[28] +.sym 28385 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28387 w_rx_24_fifo_data[3] +.sym 28388 w_rx_09_fifo_data[3] +.sym 28389 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28395 w_rx_24_fifo_data[30] +.sym 28396 w_rx_09_fifo_data[30] +.sym 28397 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28398 w_rx_fifo_pulled_data[20] +.sym 28405 rx_fifo.mem_i.0.1_WDATA +.sym 28407 w_rx_24_fifo_data[31] +.sym 28408 w_rx_09_fifo_data[31] +.sym 28409 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28411 w_rx_24_fifo_data[29] +.sym 28412 w_rx_09_fifo_data[29] +.sym 28413 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28415 w_rx_09_fifo_data[2] +.sym 28416 w_rx_24_fifo_data[2] +.sym 28417 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28418 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28422 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28427 w_rx_09_fifo_data[1] +.sym 28428 w_rx_24_fifo_data[1] +.sym 28429 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28432 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28433 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28434 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 28438 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 28442 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 28448 i_rst_b$SB_IO_IN +.sym 28449 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 28451 rx_fifo.wr_addr[0] +.sym 28456 rx_fifo.wr_addr[1] +.sym 28457 rx_fifo.wr_addr[0] +.sym 28460 rx_fifo.wr_addr[2] +.sym 28461 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28464 rx_fifo.wr_addr[3] +.sym 28465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28468 rx_fifo.wr_addr[4] +.sym 28469 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28472 rx_fifo.wr_addr[5] +.sym 28473 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28476 rx_fifo.wr_addr[6] +.sym 28477 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 28480 rx_fifo.wr_addr[7] +.sym 28481 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 28484 rx_fifo.wr_addr[8] +.sym 28485 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 28488 rx_fifo.wr_addr[9] +.sym 28489 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 28491 rx_fifo.rd_addr_gray_wr_r[3] +.sym 28492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28495 rx_fifo.rd_addr_gray_wr_r[2] +.sym 28496 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28500 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 28501 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 28504 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28505 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28507 rx_fifo.rd_addr_gray_wr_r[6] +.sym 28508 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28509 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28510 rx_fifo.wr_addr[9] +.sym 28514 rx_fifo.wr_addr[2] +.sym 28515 rx_fifo.rd_addr_gray_wr_r[1] +.sym 28516 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.sym 28518 rx_fifo.rd_addr_gray_wr_r[1] +.sym 28519 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 28520 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 28522 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28526 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 28530 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28531 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28532 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28533 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28534 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28535 rx_fifo.wr_addr[1] +.sym 28536 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28537 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28538 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28542 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28543 rx_fifo.rd_addr_gray_wr_r[0] +.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28547 rx_fifo.full_o_SB_LUT4_I0_O[0] +.sym 28548 rx_fifo.full_o_SB_LUT4_I0_O[1] +.sym 28549 rx_fifo.full_o_SB_LUT4_I0_O[2] +.sym 28550 w_rx_fifo_full +.sym 28551 rx_fifo.rd_addr_gray_wr_r[9] +.sym 28552 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.sym 28553 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 28555 w_rx_24_fifo_data[0] +.sym 28556 w_rx_09_fifo_data[0] +.sym 28557 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] +.sym 28559 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.sym 28560 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.sym 28562 w_rx_data[0] +.sym 28568 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.sym 28569 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 28572 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 28573 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 28575 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] +.sym 28576 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28577 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] +.sym 28578 w_lvds_rx_09_d0 +.sym 28579 w_lvds_rx_09_d1 +.sym 28580 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28581 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28584 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.sym 28585 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28590 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28591 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.sym 28592 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.sym 28593 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.sym 28594 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.sym 28595 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.sym 28596 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.sym 28597 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.sym 28608 rx_fifo.rd_addr_gray_wr_r[3] +.sym 28609 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 28614 w_lvds_rx_09_d1 +.sym 28615 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 28616 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28617 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28621 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.sym 28622 w_lvds_rx_09_d0 +.sym 28643 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28646 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28647 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.sym 28648 $PACKER_VCC_NET +.sym 28649 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] +.sym 28650 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28651 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 28652 $PACKER_VCC_NET +.sym 28653 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 +.sym 28657 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28660 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28661 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28662 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 28663 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28664 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] +.sym 28665 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28666 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.sym 28667 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28668 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] +.sym 28669 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.sym 28673 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] +.sym 28676 w_rx_fifo_full +.sym 28677 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 28692 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.sym 28693 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28738 w_rx_fifo_pulled_data[14] +.sym 28742 w_rx_fifo_pulled_data[12] +.sym 28746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 28747 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 28748 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 28749 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] +.sym 28750 w_rx_fifo_pulled_data[13] +.sym 28754 w_rx_fifo_pulled_data[9] +.sym 28758 w_rx_fifo_pulled_data[8] +.sym 28762 w_rx_fifo_pulled_data[11] +.sym 28766 w_rx_fifo_pulled_data[15] +.sym 28770 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 28776 i_rst_b$SB_IO_IN +.sym 28777 w_tx_fifo_pull +.sym 28780 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 28781 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 28786 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 28790 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 28794 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 28802 tx_fifo.rd_addr_gray_wr[8] +.sym 28806 tx_fifo.rd_addr_gray_wr[0] +.sym 28810 tx_fifo.rd_addr[9] +.sym 28814 tx_fifo.rd_addr_gray[0] +.sym 28818 tx_fifo.rd_addr_gray[8] +.sym 28822 tx_fifo.rd_addr_gray_wr[9] +.sym 28826 tx_fifo.rd_addr_gray[1] +.sym 28830 tx_fifo.rd_addr_gray_wr[1] +.sym 28834 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 28835 smi_ctrl_ins.int_cnt_rx[4] +.sym 28836 smi_ctrl_ins.int_cnt_rx[3] +.sym 28837 smi_ctrl_ins.r_fifo_pulled_data[1] +.sym 28838 w_rx_fifo_pulled_data[27] +.sym 28842 w_rx_fifo_pulled_data[25] +.sym 28847 w_rx_24_fifo_data[24] +.sym 28848 w_rx_09_fifo_data[24] +.sym 28849 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28850 w_rx_fifo_pulled_data[10] +.sym 28854 w_rx_fifo_pulled_data[24] +.sym 28858 w_rx_fifo_pulled_data[26] +.sym 28862 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 28863 smi_ctrl_ins.int_cnt_rx[4] +.sym 28864 smi_ctrl_ins.int_cnt_rx[3] +.sym 28865 smi_ctrl_ins.r_fifo_pulled_data[2] +.sym 28872 w_rx_24_fifo_data[22] +.sym 28873 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28888 w_rx_24_fifo_data[24] +.sym 28889 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28892 w_rx_24_fifo_data[26] +.sym 28893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 28898 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 28903 w_rx_24_fifo_data[28] +.sym 28904 w_rx_09_fifo_data[28] +.sym 28905 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 28906 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 28910 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 28914 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 28918 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 28925 rx_fifo.rd_addr[3] +.sym 28929 rx_fifo.rd_addr[0] +.sym 28930 w_rx_fifo_pulled_data[3] +.sym 28936 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 28937 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 28938 w_rx_fifo_pulled_data[1] +.sym 28946 w_rx_fifo_pulled_data[0] +.sym 28950 w_rx_fifo_pulled_data[2] +.sym 28954 w_rx_fifo_pulled_data[21] +.sym 28960 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 28961 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 28962 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 28966 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 28970 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 28974 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 28975 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 28976 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 28977 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] +.sym 28978 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 28979 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 28980 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 28982 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 28986 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 28987 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 28988 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 28989 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 28991 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 28993 rx_fifo.rd_addr[3] +.sym 28996 rx_fifo.rd_addr[8] +.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 28998 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 28999 rx_fifo.rd_addr[6] +.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 29001 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 29003 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] +.sym 29004 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] +.sym 29005 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] +.sym 29006 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 29007 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 29008 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 29009 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] +.sym 29010 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 29011 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 29012 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +.sym 29013 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.sym 29014 rx_fifo.rd_addr_gray[6] +.sym 29020 rx_fifo.rd_addr[6] +.sym 29021 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 29022 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 29023 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 29024 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 29025 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.sym 29026 rx_fifo.rd_addr_gray[8] +.sym 29030 rx_fifo.rd_addr_gray_wr[8] +.sym 29034 rx_fifo.rd_addr_gray_wr[9] +.sym 29038 rx_fifo.rd_addr_gray[2] +.sym 29043 rx_fifo.rd_addr_gray_wr_r[2] +.sym 29044 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 29045 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29046 rx_fifo.rd_addr[9] +.sym 29050 rx_fifo.rd_addr_gray_wr[5] +.sym 29054 rx_fifo.rd_addr_gray[5] +.sym 29065 w_lvds_rx_24_d0 +.sym 29066 rx_fifo.rd_addr_gray_wr_r[8] +.sym 29067 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29071 w_lvds_rx_24_d1 +.sym 29072 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 29073 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.sym 29090 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29094 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 29098 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 29104 rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.sym 29105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29106 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 29112 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29113 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29121 rx_fifo.wr_addr[1] +.sym 29122 rx_fifo.wr_addr_gray[7] +.sym 29126 rx_fifo.wr_addr_gray_rd[6] +.sym 29130 rx_fifo.wr_addr_gray[4] +.sym 29138 rx_fifo.wr_addr_gray_rd[4] +.sym 29146 rx_fifo.wr_addr_gray[6] +.sym 29150 rx_fifo.wr_addr_gray_rd[7] +.sym 29166 rx_fifo.rd_addr_gray[3] +.sym 29174 rx_fifo.rd_addr_gray_wr[3] +.sym 29220 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29221 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29224 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 29225 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29226 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29232 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 29233 tx_fifo.rd_addr[2] +.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29241 tx_fifo.rd_addr[0] +.sym 29242 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29251 tx_fifo.rd_addr[0] +.sym 29256 tx_fifo.rd_addr[1] +.sym 29257 tx_fifo.rd_addr[0] +.sym 29260 tx_fifo.rd_addr[2] +.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29264 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 29265 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29268 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 29272 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29273 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29276 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29277 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 +.sym 29280 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29284 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29285 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29288 tx_fifo.rd_addr[9] +.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29292 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 29293 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29294 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29295 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 29296 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 29297 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29299 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 29300 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.sym 29301 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 29302 tx_fifo.rd_addr_gray[2] +.sym 29306 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 29307 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 29308 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 29309 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 29310 tx_fifo.rd_addr_gray[4] +.sym 29314 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.sym 29321 tx_fifo.rd_addr[1] +.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 29323 smi_ctrl_ins.int_cnt_rx[4] +.sym 29324 smi_ctrl_ins.int_cnt_rx[3] +.sym 29325 smi_ctrl_ins.r_fifo_pulled_data[0] +.sym 29328 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29329 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[6] +.sym 29332 smi_ctrl_ins.int_cnt_rx[4] +.sym 29333 smi_ctrl_ins.int_cnt_rx[3] +.sym 29334 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29338 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29339 tx_fifo.rd_addr[9] +.sym 29340 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29341 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.sym 29342 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29346 w_rx_fifo_pulled_data[6] +.sym 29350 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 29351 smi_ctrl_ins.r_fifo_pulled_data[4] +.sym 29352 smi_ctrl_ins.int_cnt_rx[4] +.sym 29353 smi_ctrl_ins.int_cnt_rx[3] +.sym 29354 w_rx_fifo_pulled_data[19] +.sym 29358 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 29359 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 29360 smi_ctrl_ins.int_cnt_rx[4] +.sym 29361 smi_ctrl_ins.int_cnt_rx[3] +.sym 29362 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 29363 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 29364 smi_ctrl_ins.int_cnt_rx[4] +.sym 29365 smi_ctrl_ins.int_cnt_rx[3] +.sym 29366 w_rx_fifo_pulled_data[18] +.sym 29370 w_rx_fifo_pulled_data[4] +.sym 29374 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 29375 smi_ctrl_ins.int_cnt_rx[4] +.sym 29376 smi_ctrl_ins.int_cnt_rx[3] +.sym 29377 smi_ctrl_ins.r_fifo_pulled_data[3] +.sym 29388 smi_ctrl_ins.int_cnt_rx[4] +.sym 29389 smi_ctrl_ins.int_cnt_rx[3] +.sym 29401 smi_ctrl_ins.int_cnt_rx[3] +.sym 29411 rx_fifo.rd_addr[0] +.sym 29416 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 29417 rx_fifo.rd_addr[0] +.sym 29420 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 29421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 29424 rx_fifo.rd_addr[3] +.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 +.sym 29428 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +.sym 29429 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 29432 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 29436 rx_fifo.rd_addr[6] +.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 29440 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 29444 rx_fifo.rd_addr[8] +.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29448 rx_fifo.rd_addr[9] +.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 29450 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 29460 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.sym 29461 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] +.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] +.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 29472 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29474 rx_fifo.wr_addr_gray[3] +.sym 29479 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 29480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] +.sym 29481 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.sym 29484 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29485 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 29486 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29488 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 29490 rx_fifo.wr_addr_gray_rd[2] +.sym 29494 rx_fifo.wr_addr_gray_rd[3] +.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 29499 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29502 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] +.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] +.sym 29508 i_rst_b$SB_IO_IN +.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29512 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 29513 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 29514 rx_fifo.wr_addr_gray_rd[5] +.sym 29518 rx_fifo.wr_addr_gray_rd[9] +.sym 29522 rx_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 29523 rx_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 29524 rx_fifo.empty_o_SB_LUT4_I0_O[2] +.sym 29525 rx_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 29526 w_rx_fifo_empty +.sym 29527 rx_fifo.empty_o_SB_LUT4_I0_I3[1] +.sym 29528 rx_fifo.empty_o_SB_LUT4_I0_I3[2] +.sym 29529 rx_fifo.empty_o_SB_LUT4_I0_I3[3] +.sym 29530 rx_fifo.wr_addr_gray_rd[1] +.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 29535 rx_fifo.rd_addr[9] +.sym 29536 rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] +.sym 29537 rx_fifo.rd_addr[8] +.sym 29538 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.sym 29558 rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 29562 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 29566 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.sym 29570 rx_fifo.rd_addr_gray_wr[7] +.sym 29574 rx_fifo.rd_addr_gray_wr[0] +.sym 29582 rx_fifo.rd_addr_gray[0] +.sym 29586 rx_fifo.rd_addr_gray[1] +.sym 29590 rx_fifo.rd_addr_gray_wr[1] +.sym 29598 rx_fifo.rd_addr_gray[7] +.sym 29602 rx_fifo.wr_addr_gray[8] +.sym 29606 rx_fifo.wr_addr_gray[0] +.sym 29610 rx_fifo.wr_addr_gray_rd[8] +.sym 29614 rx_fifo.wr_addr_gray_rd[0] +.sym 29618 rx_fifo.wr_addr_gray[2] +.sym 29622 rx_fifo.wr_addr_gray[5] +.sym 29630 rx_fifo.wr_addr_gray[1] +.sym 29645 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.sym 29701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q +.sym 29730 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 29734 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 29746 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 29747 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 29748 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 29749 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 29750 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29756 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 29761 w_smi_data_output[2] +.sym 29762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 29763 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29764 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 29765 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 29767 tx_fifo.rd_addr[2] +.sym 29768 tx_fifo.rd_addr[1] +.sym 29769 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 29771 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 29772 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 29773 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] +.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 29779 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] +.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 29782 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] +.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +.sym 29784 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.sym 29785 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 29787 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29788 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29789 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +.sym 29790 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 29791 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 29792 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 29793 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 29794 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 29795 tx_fifo.empty_o_SB_LUT4_I1_O[1] +.sym 29796 tx_fifo.empty_o_SB_LUT4_I1_O[2] +.sym 29797 tx_fifo.empty_o_SB_LUT4_I1_O[3] +.sym 29798 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29799 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29800 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] +.sym 29801 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 29802 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 29803 tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29804 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.sym 29805 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 29806 w_tx_fifo_pull +.sym 29807 w_tx_fifo_empty +.sym 29808 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29809 tx_fifo.rd_addr[9] +.sym 29812 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] +.sym 29813 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29814 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29815 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29816 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 29817 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 29819 w_tx_fifo_pull +.sym 29820 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29821 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29823 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.sym 29824 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.sym 29825 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.sym 29826 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 29827 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 29828 smi_ctrl_ins.int_cnt_rx[4] +.sym 29829 smi_ctrl_ins.int_cnt_rx[3] +.sym 29832 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.sym 29833 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.sym 29834 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 29835 tx_fifo.rd_addr[1] +.sym 29836 tx_fifo.empty_o_SB_LUT4_I1_O[0] +.sym 29837 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.sym 29840 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.sym 29841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.sym 29844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.sym 29845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.sym 29848 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 29849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.sym 29852 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.sym 29853 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.sym 29856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.sym 29857 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.sym 29858 tx_fifo.wr_addr_gray[7] +.sym 29862 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 29863 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 29864 smi_ctrl_ins.int_cnt_rx[4] +.sym 29865 smi_ctrl_ins.int_cnt_rx[3] +.sym 29866 tx_fifo.wr_addr_gray[8] +.sym 29870 tx_fifo.wr_addr_gray_rd[8] +.sym 29874 tx_fifo.wr_addr_gray_rd[7] +.sym 29878 tx_fifo.wr_addr_gray_rd[5] +.sym 29882 tx_fifo.wr_addr_gray[1] +.sym 29886 tx_fifo.wr_addr_gray[5] +.sym 29894 tx_fifo.wr_addr_gray[0] +.sym 29902 tx_fifo.wr_addr_gray_rd[0] +.sym 29906 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 29907 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 29908 smi_ctrl_ins.int_cnt_rx[4] +.sym 29909 smi_ctrl_ins.int_cnt_rx[3] +.sym 29915 i_rst_b$SB_IO_IN +.sym 29916 smi_ctrl_ins.int_cnt_rx[4] +.sym 29917 smi_ctrl_ins.int_cnt_rx[3] +.sym 29918 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 29919 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 29920 smi_ctrl_ins.int_cnt_rx[4] +.sym 29921 smi_ctrl_ins.int_cnt_rx[3] +.sym 29942 w_rx_fifo_pulled_data[22] +.sym 29946 w_rx_fifo_pulled_data[23] +.sym 29954 w_rx_data[2] +.sym 29960 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 29970 w_rx_data[0] +.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.sym 29986 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.sym 29987 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.sym 29988 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.sym 29989 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.sym 30006 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 30007 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.sym 30008 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.sym 30009 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.sym 30015 rx_fifo.rd_addr[3] +.sym 30016 rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.sym 30017 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.sym 30019 w_ioc[1] +.sym 30020 w_ioc[0] +.sym 30021 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 30022 w_rx_data[1] +.sym 30026 w_rx_data[0] +.sym 30030 w_cs[0] +.sym 30031 w_load +.sym 30032 w_fetch +.sym 30033 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 30034 w_rx_data[2] +.sym 30039 w_ioc[1] +.sym 30040 w_ioc[0] +.sym 30041 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.sym 30042 w_rx_data[4] +.sym 30050 w_tx_data_smi[1] +.sym 30051 w_tx_data_io[1] +.sym 30052 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 30053 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30056 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] +.sym 30057 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30060 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] +.sym 30061 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30065 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.sym 30068 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] +.sym 30069 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30071 w_cs[0] +.sym 30072 w_fetch +.sym 30073 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.sym 30074 w_ioc[1] +.sym 30075 w_ioc[0] +.sym 30076 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 30077 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30079 w_ioc[1] +.sym 30080 w_ioc[0] +.sym 30081 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 30082 w_tx_fifo_full +.sym 30090 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] +.sym 30101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 30102 w_rx_fifo_empty +.sym 30126 i_rst_b$SB_IO_IN +.sym 30127 w_cs[1] +.sym 30128 w_load +.sym 30129 w_fetch +.sym 30131 w_ioc[1] +.sym 30132 w_ioc[0] +.sym 30133 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30134 w_cs[1] +.sym 30135 w_load +.sym 30136 w_fetch +.sym 30137 o_led0_SB_LUT4_I1_O[1] +.sym 30143 io_pmod[7]$SB_IO_IN +.sym 30144 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] +.sym 30145 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 30146 w_rx_data[0] +.sym 30155 w_ioc[0] +.sym 30156 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 30157 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30158 w_rx_data[3] +.sym 30162 w_rx_data[2] +.sym 30166 o_shdn_rx_lna$SB_IO_OUT +.sym 30167 w_ioc[0] +.sym 30168 io_ctrl_ins.o_pmod[1] +.sym 30169 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30170 o_shdn_tx_lna$SB_IO_OUT +.sym 30171 w_ioc[0] +.sym 30172 io_ctrl_ins.o_pmod[2] +.sym 30173 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30174 w_rx_data[1] +.sym 30182 w_rx_data[0] +.sym 30190 w_rx_data[4] +.sym 30194 w_rx_data[3] +.sym 30202 w_rx_data[1] +.sym 30206 w_rx_data[2] +.sym 30242 tx_fifo.wr_addr_gray[2] +.sym 30248 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 30249 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 30253 w_smi_data_direction +.sym 30254 tx_fifo.wr_addr_gray[3] +.sym 30258 tx_fifo.wr_addr_gray_rd[3] +.sym 30262 tx_fifo.wr_addr_gray_rd[2] +.sym 30266 tx_fifo.wr_addr_gray[6] +.sym 30270 tx_fifo.wr_addr_gray_rd[6] +.sym 30275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 30280 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30281 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 30282 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 30283 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 30284 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30285 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 30288 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 30289 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 30291 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 30295 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 30296 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 30297 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 30298 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 30299 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 30300 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 30301 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 30305 w_tx_fifo_empty +.sym 30310 tx_fifo.wr_addr_gray_rd[1] +.sym 30314 tx_fifo.wr_addr[9] +.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.sym 30325 i_rst_b$SB_IO_IN +.sym 30326 tx_fifo.wr_addr_gray[4] +.sym 30330 tx_fifo.wr_addr_gray_rd[4] +.sym 30334 tx_fifo.wr_addr_gray_rd[9] +.sym 30338 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 30339 smi_ctrl_ins.r_fifo_pulled_data[5] +.sym 30340 smi_ctrl_ins.int_cnt_rx[4] +.sym 30341 smi_ctrl_ins.int_cnt_rx[3] +.sym 30346 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.sym 30350 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 30351 smi_ctrl_ins.r_fifo_pulled_data[7] +.sym 30352 smi_ctrl_ins.int_cnt_rx[4] +.sym 30353 smi_ctrl_ins.int_cnt_rx[3] +.sym 30354 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 30358 tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] +.sym 30362 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] +.sym 30366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 30367 tx_fifo.wr_addr[1] +.sym 30368 tx_fifo.rd_addr_gray_wr_r[0] +.sym 30369 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30372 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30373 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30378 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 30379 tx_fifo.rd_addr_gray_wr_r[1] +.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30382 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30387 w_tx_fifo_full +.sym 30388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 30389 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.sym 30392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] +.sym 30393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] +.sym 30396 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 30397 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30401 tx_fifo.wr_addr[1] +.sym 30404 smi_ctrl_ins.int_cnt_rx[4] +.sym 30405 smi_ctrl_ins.int_cnt_rx[3] +.sym 30412 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 30413 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.sym 30422 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 30423 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 30424 smi_ctrl_ins.int_cnt_rx[4] +.sym 30425 smi_ctrl_ins.int_cnt_rx[3] +.sym 30430 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 30431 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 30432 smi_ctrl_ins.int_cnt_rx[4] +.sym 30433 smi_ctrl_ins.int_cnt_rx[3] +.sym 30434 w_rx_fifo_pulled_data[30] +.sym 30438 w_rx_fifo_pulled_data[31] +.sym 30446 w_rx_fifo_pulled_data[28] +.sym 30450 w_rx_fifo_pulled_data[29] +.sym 30466 spi_if_ins.w_rx_data[0] +.sym 30478 spi_if_ins.w_rx_data[5] +.sym 30486 spi_if_ins.w_rx_data[2] +.sym 30493 i_rst_b$SB_IO_IN +.sym 30502 w_rx_data[7] +.sym 30509 spi_if_ins.o_ioc_SB_DFFE_Q_E +.sym 30510 w_rx_data[6] +.sym 30514 w_rx_data[3] +.sym 30518 w_rx_data[5] +.sym 30532 spi_if_ins.w_rx_data[6] +.sym 30533 spi_if_ins.w_rx_data[5] +.sym 30534 w_cs[3] +.sym 30535 w_cs[2] +.sym 30536 w_cs[1] +.sym 30537 w_cs[0] +.sym 30540 spi_if_ins.w_rx_data[6] +.sym 30541 spi_if_ins.w_rx_data[5] +.sym 30544 spi_if_ins.w_rx_data[6] +.sym 30545 spi_if_ins.w_rx_data[5] +.sym 30549 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 30552 spi_if_ins.w_rx_data[6] +.sym 30553 spi_if_ins.w_rx_data[5] +.sym 30562 w_tx_data_smi[2] +.sym 30563 w_tx_data_io[2] +.sym 30564 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 30565 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30566 w_cs[3] +.sym 30567 w_cs[2] +.sym 30568 w_cs[1] +.sym 30569 w_cs[0] +.sym 30572 i_rst_b$SB_IO_IN +.sym 30573 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 30574 w_cs[3] +.sym 30575 w_cs[2] +.sym 30576 w_cs[1] +.sym 30577 w_cs[0] +.sym 30578 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] +.sym 30579 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30580 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 30581 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.sym 30582 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] +.sym 30583 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30584 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 30585 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] +.sym 30587 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 30588 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 30589 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.sym 30590 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0] +.sym 30591 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 30592 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 30593 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 30596 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 30597 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30600 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] +.sym 30601 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30604 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +.sym 30605 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30606 w_cs[2] +.sym 30607 w_load +.sym 30608 w_fetch +.sym 30609 o_led1_SB_LUT4_I1_I2[3] +.sym 30612 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 30613 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30616 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] +.sym 30617 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.sym 30618 w_cs[2] +.sym 30619 w_ioc[1] +.sym 30620 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 30621 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30627 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 30628 o_led0_SB_LUT4_I1_O[1] +.sym 30629 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] +.sym 30630 w_cs[2] +.sym 30631 w_load +.sym 30632 w_fetch +.sym 30633 o_led1_SB_LUT4_I1_I2[2] +.sym 30635 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +.sym 30636 o_led1_SB_LUT4_I1_I2[2] +.sym 30637 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] +.sym 30639 w_ioc[0] +.sym 30640 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30641 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30642 w_ioc[1] +.sym 30643 w_ioc[0] +.sym 30644 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 30645 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30647 w_ioc[1] +.sym 30648 w_ioc[0] +.sym 30649 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.sym 30650 w_cs[1] +.sym 30651 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 30652 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 30653 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30656 w_ioc[1] +.sym 30657 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.sym 30658 w_ioc[0] +.sym 30659 io_ctrl_ins.o_pmod[0] +.sym 30660 io_ctrl_ins.mixer_en_state +.sym 30661 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30662 o_tr_vc2$SB_IO_OUT +.sym 30663 w_ioc[0] +.sym 30664 io_ctrl_ins.o_pmod[3] +.sym 30665 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 30670 o_led1_SB_LUT4_I1_O[0] +.sym 30671 o_led0_SB_LUT4_I1_O[1] +.sym 30672 o_led1_SB_LUT4_I1_O[2] +.sym 30673 o_led1_SB_LUT4_I1_O[3] +.sym 30674 i_config[0]$SB_IO_IN +.sym 30675 o_led1_SB_LUT4_I1_I2[3] +.sym 30676 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.sym 30677 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.sym 30678 io_ctrl_ins.pmod_dir_state[3] +.sym 30679 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 30680 o_led1_SB_LUT4_I1_I2[2] +.sym 30681 o_led0_SB_LUT4_I1_O[1] +.sym 30684 o_led1_SB_LUT4_I1_I2[3] +.sym 30685 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.sym 30686 o_led0_SB_LUT4_I1_O[0] +.sym 30687 o_led0_SB_LUT4_I1_O[1] +.sym 30688 o_led0_SB_LUT4_I1_O[2] +.sym 30689 o_led0_SB_LUT4_I1_O[3] +.sym 30691 o_led0_SB_LUT4_I1_O[0] +.sym 30692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 30693 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 30696 o_led0_SB_LUT4_I1_O[0] +.sym 30697 o_led1_SB_LUT4_I1_O[0] +.sym 30698 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 30699 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 30700 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 30701 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 30702 w_rx_data[0] +.sym 30707 i_rst_b$SB_IO_IN +.sym 30708 o_led1_SB_LUT4_I1_O[0] +.sym 30709 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] +.sym 30718 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 30719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] +.sym 30720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 30721 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 30733 r_counter +.sym 30755 tx_fifo.wr_addr[0] +.sym 30760 tx_fifo.wr_addr[1] +.sym 30761 tx_fifo.wr_addr[0] +.sym 30764 tx_fifo.wr_addr[2] +.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 30768 tx_fifo.wr_addr[3] +.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30772 tx_fifo.wr_addr[4] +.sym 30773 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 +.sym 30776 tx_fifo.wr_addr[5] +.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 +.sym 30780 tx_fifo.wr_addr[6] +.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 +.sym 30784 tx_fifo.wr_addr[7] +.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 30788 tx_fifo.wr_addr[8] +.sym 30789 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 30792 tx_fifo.wr_addr[9] +.sym 30793 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 +.sym 30796 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 30798 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 30808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 30810 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.sym 30823 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.sym 30824 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 30832 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30833 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.sym 30838 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 30839 tx_fifo.rd_addr_gray_wr_r[0] +.sym 30840 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 30841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.sym 30846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 30847 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 30849 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.sym 30850 tx_fifo.rd_addr_gray_wr[6] +.sym 30854 tx_fifo.rd_addr_gray_wr[7] +.sym 30860 tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 30862 tx_fifo.rd_addr_gray[5] +.sym 30866 tx_fifo.rd_addr_gray[7] +.sym 30870 tx_fifo.rd_addr_gray[3] +.sym 30874 tx_fifo.rd_addr_gray[6] +.sym 30878 tx_fifo.rd_addr_gray_wr[3] +.sym 30883 tx_fifo.wr_addr[2] +.sym 30884 tx_fifo.rd_addr_gray_wr_r[1] +.sym 30885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 30895 w_tx_fifo_full +.sym 30896 w_rx_fifo_empty +.sym 30897 w_smi_data_direction +.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] +.sym 30899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] +.sym 30901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.sym 30902 tx_fifo.rd_addr_gray_wr[5] +.sym 30912 i_rst_b$SB_IO_IN +.sym 30913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.sym 30914 smi_ctrl_ins.r_fifo_pull +.sym 30919 w_rx_fifo_empty +.sym 30920 smi_ctrl_ins.r_fifo_pull_1 +.sym 30921 smi_ctrl_ins.r_fifo_pull +.sym 30922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 30923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 30924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 30925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 30927 w_tx_fifo_full +.sym 30928 smi_ctrl_ins.r_fifo_push +.sym 30929 smi_ctrl_ins.r_fifo_push_1 +.sym 30930 smi_ctrl_ins.w_fifo_pull_trigger +.sym 30938 smi_ctrl_ins.r_fifo_push +.sym 30942 smi_ctrl_ins.w_fifo_push_trigger +.sym 30946 spi_if_ins.spi.r_rx_byte[1] +.sym 30954 spi_if_ins.spi.r_rx_byte[2] +.sym 30958 spi_if_ins.spi.r_rx_byte[4] +.sym 30966 spi_if_ins.spi.r_rx_byte[5] +.sym 30970 spi_if_ins.spi.r_rx_byte[6] +.sym 30974 spi_if_ins.spi.r_rx_byte[0] +.sym 30979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30980 spi_if_ins.state_if[1] +.sym 30981 spi_if_ins.state_if[0] +.sym 30982 spi_if_ins.spi.r_rx_byte[3] +.sym 30986 spi_if_ins.spi.r_rx_byte[7] +.sym 30995 i_rst_b$SB_IO_IN +.sym 30996 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30997 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 30999 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31001 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 31003 i_rst_b$SB_IO_IN +.sym 31004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 31007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31008 spi_if_ins.state_if[1] +.sym 31009 spi_if_ins.state_if[0] +.sym 31011 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] .sym 31012 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] .sym 31013 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31015 spi_if_ins.spi.r_tx_byte[7] -.sym 31016 spi_if_ins.spi.r_tx_byte[6] -.sym 31017 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31018 spi_if_ins.w_rx_data[2] -.sym 31022 spi_if_ins.w_rx_data[0] -.sym 31027 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 31014 spi_if_ins.w_rx_data[4] +.sym 31018 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 31024 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31025 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31026 i_rst_b$SB_IO_IN +.sym 31027 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] .sym 31028 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] .sym 31029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31030 spi_if_ins.w_rx_data[1] -.sym 31035 spi_if_ins.spi.r_tx_byte[5] -.sym 31036 spi_if_ins.spi.r_tx_byte[4] -.sym 31037 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31039 spi_if_ins.spi.r_tx_byte[3] -.sym 31040 spi_if_ins.spi.r_tx_byte[2] -.sym 31041 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31042 spi_if_ins.r_tx_byte[2] -.sym 31046 spi_if_ins.r_tx_byte[5] -.sym 31050 spi_if_ins.r_tx_byte[0] -.sym 31054 spi_if_ins.r_tx_byte[4] -.sym 31058 spi_if_ins.r_tx_byte[3] -.sym 31062 spi_if_ins.r_tx_byte[6] -.sym 31066 spi_if_ins.r_tx_byte[1] -.sym 31070 spi_if_ins.r_tx_byte[7] -.sym 31075 i_rst_b$SB_IO_IN -.sym 31076 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 31077 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 31078 w_cs[1] -.sym 31079 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.sym 31080 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 31081 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31082 w_rx_data[2] -.sym 31087 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31088 io_pmod[2]$SB_IO_IN -.sym 31089 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31092 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 31093 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.sym 31094 w_rx_data[7] -.sym 31102 w_rx_data[5] -.sym 31107 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 31108 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31109 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.sym 31110 o_shdn_tx_lna$SB_IO_OUT -.sym 31111 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] -.sym 31112 i_button_SB_LUT4_I0_O[1] -.sym 31113 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] -.sym 31115 w_ioc[4] -.sym 31116 w_ioc[3] -.sym 31117 w_ioc[2] -.sym 31119 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 31120 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31121 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 31122 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] -.sym 31123 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 31124 o_led1_SB_LUT4_I1_I3[3] -.sym 31125 o_led0_SB_LUT4_I1_O[1] -.sym 31127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31128 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 31129 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31131 w_ioc[4] -.sym 31132 w_ioc[3] -.sym 31133 w_ioc[2] -.sym 31135 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] -.sym 31136 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31137 o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.sym 31138 spi_if_ins.w_rx_data[3] -.sym 31142 w_tx_data_smi[0] -.sym 31143 w_tx_data_io[0] -.sym 31144 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] -.sym 31145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31146 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 31152 spi_if_ins.w_rx_data[6] -.sym 31153 spi_if_ins.w_rx_data[5] -.sym 31154 w_cs[2] -.sym 31155 w_fetch -.sym 31156 w_load -.sym 31157 o_led1_SB_LUT4_I1_I3[3] -.sym 31161 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 31166 spi_if_ins.w_rx_data[4] -.sym 31170 w_cs[3] -.sym 31171 w_cs[2] -.sym 31172 w_cs[1] -.sym 31173 w_cs[0] -.sym 31176 i_rst_b$SB_IO_IN -.sym 31177 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 31178 w_cs[3] -.sym 31179 w_cs[2] -.sym 31180 w_cs[1] -.sym 31181 w_cs[0] -.sym 31184 spi_if_ins.w_rx_data[6] -.sym 31185 spi_if_ins.w_rx_data[5] -.sym 31186 w_cs[3] -.sym 31187 w_cs[2] -.sym 31188 w_cs[1] -.sym 31189 w_cs[0] -.sym 31190 w_cs[3] -.sym 31191 w_cs[2] -.sym 31192 w_cs[1] -.sym 31193 w_cs[0] -.sym 31202 r_tx_data[5] -.sym 31206 r_tx_data[2] -.sym 31210 r_tx_data[3] -.sym 31214 r_tx_data[6] -.sym 31218 r_tx_data[4] -.sym 31222 r_tx_data[0] -.sym 31226 r_tx_data[7] -.sym 31230 r_tx_data[1] -.sym 31267 tx_fifo.wr_addr[0] -.sym 31272 tx_fifo.wr_addr[1] -.sym 31273 tx_fifo.wr_addr[0] -.sym 31276 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 31277 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 31280 tx_fifo.wr_addr[3] -.sym 31281 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 31284 tx_fifo.wr_addr[4] -.sym 31285 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 31288 tx_fifo.wr_addr[5] -.sym 31289 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 -.sym 31292 tx_fifo.wr_addr[6] -.sym 31293 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 31296 tx_fifo.wr_addr[7] -.sym 31297 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31300 tx_fifo.wr_addr[8] -.sym 31301 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 31304 tx_fifo.wr_addr[9] -.sym 31305 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 31306 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 31319 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 31320 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31321 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -.sym 31328 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.sym 31329 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31331 tx_fifo.wr_addr[1] -.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -.sym 31337 tx_fifo.wr_addr[1] -.sym 31340 tx_fifo.wr_addr[3] -.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31344 tx_fifo.wr_addr[4] -.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31348 tx_fifo.wr_addr[5] -.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31352 tx_fifo.wr_addr[6] -.sym 31353 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31356 tx_fifo.wr_addr[7] -.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31360 tx_fifo.wr_addr[8] -.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 31364 tx_fifo.wr_addr[9] -.sym 31365 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 31367 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31368 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31369 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31370 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -.sym 31375 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31379 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -.sym 31380 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.sym 31381 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31382 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -.sym 31383 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31385 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] -.sym 31386 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31390 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -.sym 31391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31393 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -.sym 31396 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] -.sym 31397 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] -.sym 31398 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31399 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31400 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31401 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31402 tx_fifo.rd_addr_gray_wr[3] -.sym 31406 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31407 tx_fifo.rd_addr_gray_wr_r[8] -.sym 31408 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31409 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31410 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31411 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31412 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31413 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 31414 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] -.sym 31415 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.sym 31416 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] -.sym 31417 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] -.sym 31418 tx_fifo.rd_addr_gray[0] -.sym 31422 tx_fifo.rd_addr_gray[7] -.sym 31427 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31432 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31433 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31436 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31437 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 31438 i_ss$SB_IO_IN -.sym 31439 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31440 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31441 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31449 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31451 w_rx_fifo_empty -.sym 31452 w_tx_fifo_full -.sym 31453 w_smi_data_direction -.sym 31458 tx_fifo.rd_addr_gray_wr[8] -.sym 31462 tx_fifo.rd_addr_gray_wr[7] -.sym 31466 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 31470 tx_fifo.rd_addr_gray[8] -.sym 31474 tx_fifo.rd_addr_gray_wr[9] -.sym 31479 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31480 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31481 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31482 tx_fifo.rd_addr_gray[3] -.sym 31486 tx_fifo.rd_addr[9] -.sym 31502 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -.sym 31513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 31516 i_ss$SB_IO_IN -.sym 31517 spi_if_ins.r_tx_data_valid -.sym 31520 i_ss$SB_IO_IN -.sym 31521 spi_if_ins.r_tx_data_valid -.sym 31545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 31546 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31550 i_rst_b$SB_IO_IN -.sym 31551 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 31553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 31558 w_rx_data[2] -.sym 31570 w_rx_data[0] -.sym 31586 w_rx_data[0] -.sym 31590 w_rx_data[3] -.sym 31596 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 31597 i_button_SB_LUT4_I0_O[1] -.sym 31598 w_cs[1] -.sym 31599 w_fetch -.sym 31600 w_load -.sym 31601 o_led0_SB_LUT4_I1_O[1] -.sym 31602 w_rx_data[1] -.sym 31610 w_rx_data[4] -.sym 31614 w_rx_data[2] -.sym 31620 o_led1_SB_LUT4_I1_I2[1] -.sym 31621 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.sym 31622 o_led1_SB_LUT4_I1_O[0] -.sym 31623 o_led0_SB_LUT4_I1_O[1] -.sym 31624 o_led1_SB_LUT4_I1_O[2] -.sym 31625 o_led1_SB_LUT4_I1_O[3] -.sym 31626 o_led0_SB_LUT4_I1_O[0] -.sym 31627 o_led0_SB_LUT4_I1_O[1] -.sym 31628 o_led0_SB_LUT4_I1_O[2] -.sym 31629 o_led0_SB_LUT4_I1_O[3] -.sym 31630 o_shdn_rx_lna$SB_IO_OUT -.sym 31631 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31632 io_pmod[1]$SB_IO_IN -.sym 31633 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31636 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31638 o_tr_vc2$SB_IO_OUT -.sym 31639 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31640 io_pmod[3]$SB_IO_IN -.sym 31641 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 31642 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 31643 o_led0_SB_LUT4_I1_O[1] -.sym 31644 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] -.sym 31645 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] -.sym 31646 io_ctrl_ins.pmod_dir_state[0] -.sym 31647 o_led0$SB_IO_OUT -.sym 31648 o_led1_SB_LUT4_I1_I2[1] -.sym 31649 o_led1_SB_LUT4_I1_I3[3] -.sym 31652 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 31653 o_led1_SB_LUT4_I1_I3[3] -.sym 31654 w_cs[1] -.sym 31655 w_fetch -.sym 31656 w_load -.sym 31657 o_led1_SB_LUT4_I1_I2[1] -.sym 31662 io_ctrl_ins.pmod_dir_state[1] -.sym 31663 o_led1$SB_IO_OUT -.sym 31664 o_led1_SB_LUT4_I1_I2[1] -.sym 31665 o_led1_SB_LUT4_I1_I3[3] -.sym 31666 w_rx_data[0] -.sym 31674 i_rst_b$SB_IO_IN -.sym 31675 w_cs[1] -.sym 31676 w_fetch -.sym 31677 w_load -.sym 31678 i_config[0]$SB_IO_IN -.sym 31679 io_ctrl_ins.pmod_dir_state[3] -.sym 31680 o_led1_SB_LUT4_I1_I2[1] -.sym 31681 o_led1_SB_LUT4_I1_I3[3] -.sym 31686 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 31687 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 31688 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31689 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31699 o_led1_SB_LUT4_I1_I2[0] -.sym 31700 o_led1_SB_LUT4_I1_I2[1] -.sym 31701 o_led1_SB_LUT4_I1_I2[2] -.sym 31706 i_config[1]$SB_IO_IN -.sym 31707 o_led1_SB_LUT4_I1_I3[1] -.sym 31708 o_led1_SB_LUT4_I1_I2[1] -.sym 31709 o_led1_SB_LUT4_I1_I3[3] -.sym 31710 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] -.sym 31711 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31712 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] -.sym 31713 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] -.sym 31730 o_tr_vc1_b$SB_IO_OUT -.sym 31731 i_button_SB_LUT4_I0_O[1] -.sym 31732 i_config_SB_LUT4_I0_2_O[2] -.sym 31733 i_config_SB_LUT4_I0_2_O[3] -.sym 31782 tx_fifo.rd_addr_gray[4] -.sym 31793 i_smi_soe_se$SB_IO_IN -.sym 31794 tx_fifo.rd_addr_gray_wr[4] -.sym 31814 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 31818 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31824 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 31825 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31826 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 31830 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] -.sym 31834 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 31842 tx_fifo.rd_addr_gray_wr[2] -.sym 31846 tx_fifo.rd_addr_gray[6] -.sym 31850 tx_fifo.rd_addr_gray_wr[6] -.sym 31854 tx_fifo.rd_addr_gray[2] -.sym 31862 tx_fifo.rd_addr_gray[5] -.sym 31870 tx_fifo.rd_addr_gray_wr[5] -.sym 31892 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31893 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] -.sym 31894 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -.sym 31896 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 31897 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 31898 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.sym 31907 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 31908 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 31909 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 31911 w_tx_fifo_full -.sym 31912 tx_fifo.wr_addr[1] -.sym 31913 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31919 tx_fifo.wr_addr[1] -.sym 31920 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] -.sym 31922 tx_fifo.rd_addr_gray_wr[0] -.sym 31928 i_rst_b$SB_IO_IN -.sym 31929 w_tx_fifo_pull -.sym 31962 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 31995 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 31996 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31997 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31998 spi_if_ins.r_tx_byte[7] -.sym 31999 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 32001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 32002 i_mosi$SB_IO_IN -.sym 32006 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32013 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 32014 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 32024 i_ss$SB_IO_IN -.sym 32025 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32030 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 32034 spi_if_ins.spi.r_rx_byte[5] -.sym 32038 spi_if_ins.spi.r_rx_byte[0] -.sym 32042 spi_if_ins.spi.r_rx_byte[4] -.sym 32046 spi_if_ins.spi.r_rx_byte[3] -.sym 32050 spi_if_ins.spi.r_rx_byte[7] -.sym 32054 spi_if_ins.spi.r_rx_byte[2] -.sym 32058 spi_if_ins.spi.r_rx_byte[6] -.sym 32062 spi_if_ins.spi.r_rx_byte[1] -.sym 32066 spi_if_ins.w_rx_data[2] -.sym 32070 spi_if_ins.w_rx_data[1] -.sym 32074 spi_if_ins.w_rx_data[0] -.sym 32082 spi_if_ins.w_rx_data[3] -.sym 32098 i_rst_b$SB_IO_IN -.sym 32099 o_led0_SB_LUT4_I1_O[0] -.sym 32100 o_led1_SB_LUT4_I1_I2[0] -.sym 32101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32102 w_rx_data[1] -.sym 32114 w_rx_data[4] -.sym 32123 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 32124 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 32125 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 32126 w_rx_data[3] -.sym 32132 o_led1_SB_LUT4_I1_O[0] -.sym 32133 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] -.sym 32134 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] -.sym 32135 o_led1_SB_LUT4_I1_I2[0] -.sym 32136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32137 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 32143 io_pmod[0]$SB_IO_IN -.sym 32144 io_ctrl_ins.mixer_en_state -.sym 32145 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] -.sym 32148 o_led1_SB_LUT4_I1_O[0] -.sym 32149 o_led0_SB_LUT4_I1_O[0] -.sym 32150 io_ctrl_ins.rf_pin_state[2] -.sym 32151 o_led1_SB_LUT4_I1_I2[0] -.sym 32152 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32159 io_ctrl_ins.rf_pin_state[1] -.sym 32160 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32161 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32162 io_ctrl_ins.rf_pin_state[0] -.sym 32163 o_led1_SB_LUT4_I1_I2[0] -.sym 32164 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32166 io_ctrl_ins.rf_pin_state[5] -.sym 32167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32168 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 32169 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32175 io_ctrl_ins.rf_pin_state[6] -.sym 32176 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 32180 o_led1_SB_LUT4_I1_I2[0] -.sym 32181 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 32182 o_led1_SB_LUT4_I1_I2[0] -.sym 32183 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] -.sym 32184 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32185 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32186 io_ctrl_ins.rf_pin_state[4] -.sym 32187 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] -.sym 32188 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 32189 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32191 io_ctrl_ins.rf_pin_state[7] -.sym 32192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.sym 32193 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 32198 w_rx_data[0] -.sym 32214 w_rx_data[6] -.sym 32226 spi_if_ins.w_rx_data[6] -.sym 32328 i_smi_soe_se$SB_IO_IN -.sym 32329 i_rst_b$SB_IO_IN -.sym 32344 i_smi_swe_srw$SB_IO_IN -.sym 32345 i_rst_b$SB_IO_IN -.sym 32357 i_ss$SB_IO_IN -.sym 32359 w_smi_data_input[7] -.sym 32360 smi_ctrl_ins.tx_reg_state[2] -.sym 32361 smi_ctrl_ins.tx_reg_state[1] -.sym 32363 i_rst_b$SB_IO_IN -.sym 32364 w_smi_data_input[7] -.sym 32365 smi_ctrl_ins.tx_reg_state[1] -.sym 32366 i_rst_b$SB_IO_IN -.sym 32367 w_smi_data_input[7] -.sym 32368 smi_ctrl_ins.tx_reg_state[3] -.sym 32369 smi_ctrl_ins.tx_reg_state[0] -.sym 32371 i_rst_b$SB_IO_IN -.sym 32372 w_smi_data_input[7] -.sym 32373 smi_ctrl_ins.tx_reg_state[0] -.sym 32375 i_rst_b$SB_IO_IN -.sym 32376 smi_ctrl_ins.tx_reg_state[3] -.sym 32377 smi_ctrl_ins.tx_reg_state[0] -.sym 32380 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 32381 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 32383 i_rst_b$SB_IO_IN -.sym 32384 w_smi_data_input[7] -.sym 32385 smi_ctrl_ins.tx_reg_state[2] -.sym 32409 w_smi_data_input[7] -.sym 32421 w_tx_fifo_empty -.sym 32482 spi_if_ins.spi.r2_rx_done -.sym 32490 i_sck$SB_IO_IN -.sym 32494 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 32500 spi_if_ins.spi.r3_rx_done -.sym 32501 spi_if_ins.spi.r2_rx_done -.sym 32502 spi_if_ins.spi.r_rx_done -.sym 32506 spi_if_ins.spi.SCKr[0] -.sym 32514 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32518 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 32522 i_mosi$SB_IO_IN -.sym 32526 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32530 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32534 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32538 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 32549 i_rst_b$SB_IO_IN -.sym 32550 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 32554 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32562 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32570 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32602 w_rx_data[3] -.sym 32622 w_rx_data[2] -.sym 32630 w_rx_data[1] -.sym 32634 w_rx_data[0] -.sym 32650 w_rx_data[3] -.sym 32670 w_rx_data[0] -.sym 32674 w_rx_data[1] -.sym 32678 w_rx_data[0] -.sym 32717 o_rx_h_tx_l_b$SB_IO_OUT +.sym 31030 spi_if_ins.w_rx_data[3] +.sym 31034 spi_if_ins.w_rx_data[1] +.sym 31038 spi_if_ins.w_rx_data[6] +.sym 31043 w_ioc[4] +.sym 31044 w_ioc[3] +.sym 31045 w_ioc[2] +.sym 31046 spi_if_ins.w_rx_data[1] +.sym 31050 sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.sym 31054 spi_if_ins.w_rx_data[4] +.sym 31058 spi_if_ins.w_rx_data[3] +.sym 31062 spi_if_ins.w_rx_data[0] +.sym 31066 spi_if_ins.w_rx_data[2] +.sym 31071 w_ioc[4] +.sym 31072 w_ioc[3] +.sym 31073 w_ioc[2] +.sym 31078 r_tx_data[2] +.sym 31082 r_tx_data[1] +.sym 31086 w_cs[3] +.sym 31087 w_cs[2] +.sym 31088 w_cs[1] +.sym 31089 w_cs[0] +.sym 31090 r_tx_data[0] +.sym 31094 r_tx_data[7] +.sym 31098 w_cs[3] +.sym 31099 w_cs[2] +.sym 31100 w_cs[1] +.sym 31101 w_cs[0] +.sym 31102 r_tx_data[6] +.sym 31106 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.sym 31107 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] +.sym 31108 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31111 w_tx_data_io[7] +.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31113 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 31114 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.sym 31115 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] +.sym 31116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31117 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31120 i_rst_b$SB_IO_IN +.sym 31121 w_fetch +.sym 31123 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31125 spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] +.sym 31127 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 31128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31129 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.sym 31130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.sym 31131 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] +.sym 31132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.sym 31133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31135 w_tx_data_io[5] +.sym 31136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.sym 31137 r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +.sym 31138 w_rx_data[5] +.sym 31143 w_ioc[1] +.sym 31144 w_ioc[0] +.sym 31145 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 31146 w_rx_data[6] +.sym 31151 w_ioc[1] +.sym 31152 w_ioc[0] +.sym 31153 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +.sym 31154 w_cs[1] +.sym 31155 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.sym 31156 o_led1_SB_LUT4_I1_I2[3] +.sym 31157 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 31162 w_rx_data[3] +.sym 31166 w_rx_data[2] +.sym 31172 w_ioc[0] +.sym 31173 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +.sym 31174 o_rx_h_tx_l$SB_IO_OUT +.sym 31175 io_ctrl_ins.pmod_dir_state[7] +.sym 31176 o_led1_SB_LUT4_I1_I2[2] +.sym 31177 i_config_SB_LUT4_I0_1_O[1] +.sym 31179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31180 o_led1_SB_LUT4_I1_I2[3] +.sym 31181 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 31183 i_button$SB_IO_IN +.sym 31184 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 31185 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 31186 o_tr_vc1$SB_IO_OUT +.sym 31187 io_ctrl_ins.pmod_dir_state[5] +.sym 31188 o_led1_SB_LUT4_I1_I2[2] +.sym 31189 i_config_SB_LUT4_I0_1_O[1] +.sym 31191 i_config[2]$SB_IO_IN +.sym 31192 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 31193 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 31194 i_config[3]$SB_IO_IN +.sym 31195 io_ctrl_ins.pmod_dir_state[6] +.sym 31196 o_led1_SB_LUT4_I1_I2[2] +.sym 31197 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +.sym 31199 o_rx_h_tx_l_b$SB_IO_OUT +.sym 31200 i_config_SB_LUT4_I0_1_O[1] +.sym 31201 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.sym 31202 io_ctrl_ins.rf_pin_state[3] +.sym 31203 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31204 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 31205 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] +.sym 31207 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 31209 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31210 io_ctrl_ins.rf_pin_state[2] +.sym 31211 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] +.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 31213 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31215 io_ctrl_ins.rf_pin_state[4] +.sym 31216 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31217 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31219 io_ctrl_ins.rf_pin_state[7] +.sym 31220 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31221 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31223 io_ctrl_ins.rf_pin_state[1] +.sym 31224 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] +.sym 31225 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31227 io_ctrl_ins.rf_pin_state[5] +.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31229 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31231 io_ctrl_ins.rf_pin_state[6] +.sym 31232 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31234 w_rx_data[4] +.sym 31238 w_rx_data[7] +.sym 31242 w_rx_data[0] +.sym 31246 w_rx_data[5] +.sym 31250 w_rx_data[1] +.sym 31254 w_rx_data[6] +.sym 31258 w_rx_data[3] +.sym 31262 w_rx_data[2] +.sym 31267 tx_fifo.wr_addr[1] +.sym 31272 tx_fifo.wr_addr[2] +.sym 31273 tx_fifo.wr_addr[1] +.sym 31276 tx_fifo.wr_addr[3] +.sym 31277 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI +.sym 31280 tx_fifo.wr_addr[4] +.sym 31281 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI +.sym 31284 tx_fifo.wr_addr[5] +.sym 31285 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 +.sym 31288 tx_fifo.wr_addr[6] +.sym 31289 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO +.sym 31292 tx_fifo.wr_addr[7] +.sym 31293 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 31296 tx_fifo.wr_addr[8] +.sym 31297 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO +.sym 31300 tx_fifo.wr_addr[9] +.sym 31301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 +.sym 31302 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] +.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.sym 31329 tx_fifo.wr_addr[0] +.sym 31331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.sym 31332 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 31334 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 31346 tx_fifo.rd_addr_gray_wr[4] +.sym 31352 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] +.sym 31353 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 31354 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.sym 31355 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.sym 31356 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 31357 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.sym 31358 tx_fifo.rd_addr_gray_wr[2] +.sym 31363 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31368 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31369 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31372 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31373 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 +.sym 31376 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 31383 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] +.sym 31389 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31390 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +.sym 31391 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.sym 31402 w_rx_fifo_pulled_data[7] +.sym 31407 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31408 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31409 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31414 i_ss$SB_IO_IN +.sym 31415 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31416 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31417 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31418 w_rx_fifo_pulled_data[5] +.sym 31432 i_ss$SB_IO_IN +.sym 31433 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31438 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 31458 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 31462 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31466 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 31470 i_mosi$SB_IO_IN +.sym 31474 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31478 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 31482 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 31486 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 31492 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31493 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 31494 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 31500 spi_if_ins.state_if[1] +.sym 31501 spi_if_ins.state_if[0] +.sym 31503 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.sym 31504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 31505 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 31507 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31508 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 31509 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 31511 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31512 spi_if_ins.state_if[1] +.sym 31513 spi_if_ins.state_if[0] +.sym 31514 i_rst_b$SB_IO_IN +.sym 31515 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 31516 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 31517 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 31518 spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.sym 31523 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31528 $PACKER_VCC_NET +.sym 31531 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 31532 $PACKER_VCC_NET +.sym 31533 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 +.sym 31534 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 31535 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31537 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 31539 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 31540 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 31541 spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 31544 i_rst_b$SB_IO_IN +.sym 31545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 31547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31548 $PACKER_VCC_NET +.sym 31549 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31553 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31554 spi_if_ins.spi.r_tx_byte[7] +.sym 31555 spi_if_ins.spi.r_tx_byte[5] +.sym 31556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31557 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31558 spi_if_ins.r_tx_byte[7] +.sym 31562 spi_if_ins.spi.r_tx_byte[6] +.sym 31563 spi_if_ins.spi.r_tx_byte[4] +.sym 31564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31565 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31566 spi_if_ins.r_tx_byte[5] +.sym 31570 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 31571 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.sym 31572 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.sym 31573 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.sym 31575 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31576 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.sym 31577 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 31579 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.sym 31580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31581 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.sym 31584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.sym 31585 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.sym 31587 spi_if_ins.spi.r_tx_byte[1] +.sym 31588 spi_if_ins.spi.r_tx_byte[0] +.sym 31589 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31590 spi_if_ins.r_tx_byte[6] +.sym 31594 spi_if_ins.r_tx_byte[2] +.sym 31598 spi_if_ins.r_tx_byte[0] +.sym 31603 spi_if_ins.spi.r_tx_byte[3] +.sym 31604 spi_if_ins.spi.r_tx_byte[2] +.sym 31605 spi_if_ins.spi.r_tx_bit_count[0] +.sym 31606 spi_if_ins.r_tx_byte[1] +.sym 31610 spi_if_ins.r_tx_byte[4] +.sym 31614 spi_if_ins.r_tx_byte[3] +.sym 31626 r_tx_data[4] +.sym 31638 r_tx_data[3] +.sym 31642 r_tx_data[5] +.sym 31658 w_cs[1] +.sym 31659 w_load +.sym 31660 w_fetch +.sym 31661 o_led1_SB_LUT4_I1_I2[3] +.sym 31662 w_rx_data[0] +.sym 31672 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31673 o_led1_SB_LUT4_I1_I2[2] +.sym 31682 w_rx_data[4] +.sym 31686 w_rx_data[7] +.sym 31693 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 31694 i_config[1]$SB_IO_IN +.sym 31695 o_led1_SB_LUT4_I1_I2[1] +.sym 31696 o_led1_SB_LUT4_I1_I2[2] +.sym 31697 o_led1_SB_LUT4_I1_I2[3] +.sym 31698 io_ctrl_ins.pmod_dir_state[1] +.sym 31699 o_led1$SB_IO_OUT +.sym 31700 o_led1_SB_LUT4_I1_I2[2] +.sym 31701 o_led1_SB_LUT4_I1_I2[3] +.sym 31706 io_ctrl_ins.pmod_dir_state[0] +.sym 31707 o_led0$SB_IO_OUT +.sym 31708 o_led1_SB_LUT4_I1_I2[2] +.sym 31709 o_led1_SB_LUT4_I1_I2[3] +.sym 31710 w_rx_data[1] +.sym 31718 o_tr_vc1_b$SB_IO_OUT +.sym 31719 i_config_SB_LUT4_I0_1_O[1] +.sym 31720 i_config_SB_LUT4_I0_1_O[2] +.sym 31721 i_config_SB_LUT4_I0_1_O[3] +.sym 31724 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31725 i_config_SB_LUT4_I0_1_O[1] +.sym 31786 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +.sym 31862 w_rx_fifo_pulled_data[16] +.sym 31866 w_rx_fifo_pulled_data[17] +.sym 31875 i_rst_b$SB_IO_IN +.sym 31876 smi_ctrl_ins.tx_reg_state[3] +.sym 31877 smi_ctrl_ins.tx_reg_state[0] +.sym 31878 i_rst_b$SB_IO_IN +.sym 31879 w_smi_data_input[7] +.sym 31880 smi_ctrl_ins.tx_reg_state[3] +.sym 31881 smi_ctrl_ins.tx_reg_state[0] +.sym 31883 i_rst_b$SB_IO_IN +.sym 31884 w_smi_data_input[7] +.sym 31885 smi_ctrl_ins.tx_reg_state[2] +.sym 31887 i_rst_b$SB_IO_IN +.sym 31888 w_smi_data_input[7] +.sym 31889 smi_ctrl_ins.tx_reg_state[0] +.sym 31891 i_rst_b$SB_IO_IN +.sym 31892 w_smi_data_input[7] +.sym 31893 smi_ctrl_ins.tx_reg_state[1] +.sym 31897 i_ss$SB_IO_IN +.sym 31900 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.sym 31901 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.sym 31903 w_smi_data_input[7] +.sym 31904 smi_ctrl_ins.tx_reg_state[2] +.sym 31905 smi_ctrl_ins.tx_reg_state[1] +.sym 31913 w_smi_data_input[7] +.sym 31932 i_smi_swe_srw$rename$0 +.sym 31933 i_rst_b$SB_IO_IN +.sym 31938 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31970 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 31978 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31982 i_mosi$SB_IO_IN +.sym 31986 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 31990 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 31994 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31998 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 32004 i_smi_soe_se$SB_IO_IN +.sym 32005 i_rst_b$SB_IO_IN +.sym 32006 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 32012 i_ss$SB_IO_IN +.sym 32013 spi_if_ins.r_tx_data_valid +.sym 32016 i_ss$SB_IO_IN +.sym 32017 spi_if_ins.r_tx_data_valid +.sym 32019 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 32020 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 32021 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32050 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32057 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 32058 i_rst_b$SB_IO_IN +.sym 32059 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 32060 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.sym 32061 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 32067 spi_if_ins.r_tx_byte[7] +.sym 32068 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32069 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 32127 io_pmod[6]$SB_IO_IN +.sym 32128 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] +.sym 32129 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] +.sym 32166 w_rx_data[1] +.sym 32186 w_rx_data[0] +.sym 32453 i_smi_swe_srw$rename$0 +.sym 32457 smi_ctrl_ins.swe_and_reset +.sym 32458 spi_if_ins.spi.r_rx_done +.sym 32462 spi_if_ins.spi.r2_rx_done +.sym 32476 spi_if_ins.spi.r3_rx_done +.sym 32477 spi_if_ins.spi.r2_rx_done +.sym 32510 i_sck$SB_IO_IN +.sym 32518 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 32542 spi_if_ins.spi.SCKr[0] +.sym 32557 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] +.sym 32558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32669 lvds_clock diff --git a/firmware/top.bin b/firmware/top.bin index a4bf763..605814c 100644 Binary files a/firmware/top.bin and b/firmware/top.bin differ diff --git a/firmware/top.blif b/firmware/top.blif index 29e9832..bf08b39 100644 --- a/firmware/top.blif +++ b/firmware/top.blif @@ -7,27 +7,23 @@ .names $true 1 .names $undef -.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=i_button_SB_LUT4_I0_O[2] +.gate SB_LUT4 I0=$false I1=i_button I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=i_config_SB_LUT4_I0_1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[1] I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=i_config_SB_LUT4_I0_2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=i_config_SB_LUT4_I0_2_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=i_config_SB_LUT4_I0_1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I2[2] O=i_config_SB_LUT4_I0_2_O[3] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=i_config_SB_LUT4_I0_1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110000000000 @@ -50,337 +46,497 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.lna_rx_shutdown_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000111111001100 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.lna_tx_shutdown_state +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001110101010 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.mixer_en_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_pmod[0] I2=io_ctrl_ins.mixer_en_state I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=o_led0_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110010000000000 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001011111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110110011111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod[2] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=o_led1_SB_LUT4_I1_I3[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101111100010011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E Q=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111111111 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000100000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000101010101010 -.gate SB_LUT4 I0=$false I1=$false I2=o_led1_SB_LUT4_I1_I2[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000010001000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000100010000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[7] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[4] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.rx_h_b_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011111100 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.rx_h_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111100001100 -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001100000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=i_config_SB_LUT4_I0_2_O[1] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_1_b_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=i_config_SB_LUT4_I0_2_O[1] I2=i_config_SB_LUT4_I0_2_O[2] I3=i_config_SB_LUT4_I0_2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111110001111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_1_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000001110101010 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=i_config_SB_LUT4_I0_2_O[1] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O Q=io_ctrl_ins.tr_vc_2_state -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[3] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1011100000000000 -.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.pmod_dir_state[3] I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[3] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[2] +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[1] +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_pmod_SB_DFFE_Q_E Q=io_pmod[0] +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=io_pmod_SB_DFFE_Q_E +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=i_config_SB_LUT4_I0_2_O[1] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_fetch_cmd I3=spi_if_ins.o_load_cmd O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000001100 +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.param LUT_INIT 0000000000001000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100111111111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011110010101010 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=io_ctrl_ins.pmod_state[0] I2=io_ctrl_ins.mixer_en_state I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led0_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110010000000000 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=i_config[0] I1=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100011111111 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111001100000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001011111111 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 +.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=i_config[2] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000010001000 +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I2=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000100010000000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000010000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011111100 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=i_config_SB_LUT4_I0_1_O[1] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100001100 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001100000000000 +.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[4] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011111100 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=i_config_SB_LUT4_I0_1_O[1] I2=i_config_SB_LUT4_I0_1_O[2] I3=i_config_SB_LUT4_I0_1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111110001111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[5] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100001100 +.gate SB_LUT4 I0=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000111000000000 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_config_SB_LUT4_I0_1_O[1] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010100111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011110010101010 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_2_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[3] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011100000000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101111100010011 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=io_pmod[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:288.7-293.4" +.attr src "top.v:293.7-298.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_24_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:273.7-279.4" +.attr src "top.v:278.7-284.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=lvds_clock PACKAGE_PIN=i_iq_rx_clk_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:255.7-258.4" +.attr src "top.v:260.7-263.4" .param IO_STANDARD "SB_LVDS_INPUT" .param PIN_TYPE 000001 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=lvds_clock PACKAGE_PIN=o_iq_tx_n +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=io_pmod[0] PACKAGE_PIN=o_iq_tx_clk_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:314.5-319.4" +.attr src "top.v:339.5-342.4" +.param IO_STANDARD "SB_LVCMOS" +.param PIN_TYPE 011001 +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=lvds_clock PACKAGE_PIN=o_iq_tx_clk_p +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:330.5-333.4" +.param IO_STANDARD "SB_LVCMOS" +.param PIN_TYPE 011001 +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_n +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:319.5-324.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=lvds_clock PACKAGE_PIN=o_iq_tx_p +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=io_pmod[0] PACKAGE_PIN=o_iq_tx_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:303.5-308.4" +.attr src "top.v:308.5-313.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100010000010 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000010 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D +.param LUT_INIT 0111001101010000 +.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I2=$true I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001000101000 +.gate SB_CARRY CI=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 CO=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I1=$true +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101000011011101 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111100001111 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=io_pmod[7] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000010 +.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101010101010 +.gate SB_LUT4 I0=$false I1=io_pmod[7] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] O=lvds_rx_09_inst.i_sync_input +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=sys_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0111011100100000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010011010101111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.i_cs I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000110000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -390,74 +546,74 @@ .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -467,127 +623,127 @@ .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -600,25 +756,25 @@ .gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111111110000 .gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011111100001111 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 @@ -626,28 +782,18 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000000010 -.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D +.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100010101010101 -.gate SB_LUT4 I0=$false I1=io_pmod[6] I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_24_inst.i_sync_input +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000000110011 +.gate SB_LUT4 I0=$false I1=io_pmod[6] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100111111000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -657,74 +803,74 @@ .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -734,127 +880,127 @@ .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 .gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 @@ -870,32 +1016,72 @@ .param LUT_INIT 0000000011111111 .gate SB_DFFNESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_tx.v:56.3-123.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.attr src "lvds_tx.v:58.5-128.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.empty_o O=lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[0] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011000000 -.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.param LUT_INIT 1100110000001100 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[6] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000010000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.param LUT_INIT 1001000000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[8] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010101000010101 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr[6] I2=tx_fifo.wr_addr_gray_rd_r[6] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[1] I3=tx_fifo.wr_addr_gray_rd_r[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[8] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011101010100011 +.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001100111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[6] I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[5] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000001001000001 @@ -903,191 +1089,212 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=o_iq_tx_clk_n -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led0 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led0_SB_LUT4_I1_O[3] +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led0_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 +.param LUT_INIT 0001001101011111 .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I2[1] O=o_led1_SB_DFFER_Q_E +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[1] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_LUT4_I1_O[3] +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=o_led1_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010011010101111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I3[3] +.param LUT_INIT 0001001101011111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=o_led1_SB_LUT4_I1_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 -.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_pmod[1] I3=io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_O[2] +.gate SB_LUT4 I0=io_ctrl_ins.lna_rx_shutdown_state I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] O=o_led1_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1011100000000000 .gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso .attr src "top.v:150.19-150.43" -.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o I2=tx_fifo.full_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=rx_fifo.empty_o I3=smi_ctrl_ins.r_dir O=o_smi_read_req .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011001100001111 +.param LUT_INIT 0000111100110011 .gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] O=r_tx_data_SB_DFFE_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_4_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] O=r_tx_data_SB_DFFE_Q_5_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001011111111 +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[2] I1=io_ctrl_ins.o_data_out[2] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001001101011111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001001101011111 .gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_7_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:224.3-238.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D +.attr src "top.v:229.3-243.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] O=r_tx_data_SB_DFFE_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111001011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_DFFER_Q_D[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[0] I1=io_ctrl_ins.o_data_out[0] I2=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000100 +.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000000111111 .gate SB_DFFSS C=r_counter D=rx_fifo.empty_o_SB_DFFSS_Q_D Q=rx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:20.59-20.105" -.gate SB_LUT4 I0=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] I1=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] I2=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] I3=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D +.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110101010101010 +.param LUT_INIT 1110110011001100 +.gate SB_LUT4 I0=rx_fifo.empty_o I1=rx_fifo.wr_addr_gray_rd_r[0] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.empty_o_SB_LUT4_I0_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000010000010 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.empty_o_SB_LUT4_I0_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110011101111110 +.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001101001 +.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.rd_addr[6] I2=rx_fifo.wr_addr_gray_rd_r[6] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010011010111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr[5] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] O=rx_fifo.empty_o_SB_LUT4_I0_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011111001 +.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010000111100 +.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr[1] I3=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001101111 +.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000000110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr[3] O=rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 .gate SB_DFFSR C=lvds_clock D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" @@ -1111,65 +1318,11 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[8] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001010111110 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[7] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[2] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0] +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000001001 @@ -1177,78 +1330,82 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_O +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111001101010000 -.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101000011011101 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100010000010 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] I2=$true I3=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001000101000 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1] I1=$true -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O E=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O Q=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0] I1=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] I2=rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=rx_fifo.full_o_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101000011011101 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010101000101010 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O CO=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 I0=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I1=$true +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100010000010 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D E=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_I3_O Q=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q I1=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[2] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I3 O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001000101000 +.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I2[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" @@ -1274,23 +1431,23 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE +.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_1 +.param LUT_INIT 1100111111000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[16] I2=lvds_rx_09_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.0_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 @@ -1315,22 +1472,22 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[20] I2=lvds_rx_09_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[23] I2=lvds_rx_09_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.1_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 +.param LUT_INIT 1100110011110000 .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" @@ -1352,19 +1509,19 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[24] I2=lvds_rx_09_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.2_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 @@ -1389,22 +1546,22 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[29] I2=lvds_rx_24_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[30] I2=lvds_rx_09_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[28] I2=lvds_rx_09_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[31] I2=lvds_rx_09_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_i.0.3_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" @@ -1426,22 +1583,22 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[0] I2=lvds_rx_24_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[1] I2=lvds_rx_24_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[2] I2=lvds_rx_24_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[3] I2=lvds_rx_09_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.0_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" @@ -1463,22 +1620,22 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[5] I2=lvds_rx_09_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[4] I2=lvds_rx_09_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[7] I2=lvds_rx_09_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.1_WDATA +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 .gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" @@ -1500,19 +1657,19 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[8] I2=lvds_rx_24_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA_3 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.2_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 @@ -1537,166 +1694,162 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_1 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_1 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_2 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_2 .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[12] I2=lvds_rx_09_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_3 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA_3 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] O=rx_fifo.mem_q.0.3_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[3] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[4] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[7] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[5] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010001011110011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[1] +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[4] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.empty_o I1=rx_fifo.wr_addr_gray_rd_r[0] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000010000010 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[2] I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111100 -.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.param LUT_INIT 1000000001000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110101101000001 -.gate SB_LUT4 I0=rx_fifo.rd_addr[5] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[3] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111110101000001 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011001111 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110011101111110 -.gate SB_LUT4 I0=rx_fifo.rd_addr[2] I1=rx_fifo.rd_addr[1] I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001101111 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.rd_addr[3] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011101101 -.gate SB_LUT4 I0=rx_fifo.rd_addr[8] I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.wr_addr_gray_rd_r[6] I3=rx_fifo.rd_addr[6] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110000000000110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.wr_addr_gray_rd_r[5] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[1] +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[2] +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[5] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100110010000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=rx_fifo.empty_o_SB_LUT4_I0_O[0] I1=rx_fifo.empty_o_SB_LUT4_I0_O[1] I2=rx_fifo.empty_o_SB_LUT4_I0_O[2] I3=rx_fifo.empty_o_SB_LUT4_I0_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.wr_addr_gray_rd_r[7] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[3] +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[1] I1=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[4] I1=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1001000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[7] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.wr_addr_gray_rd_r[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000001000000001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[1] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -1704,89 +1857,31 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] O=rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001001 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[7] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[6] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[5] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111101000101 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O @@ -1796,20 +1891,6 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] I2=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000010000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[8] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" @@ -1879,97 +1960,131 @@ .gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[5] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[4] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 I0=$false I1=rx_fifo.wr_addr[3] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[2] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000010010 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[6] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[7] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[8] I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111100 +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[5] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000001100 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[2] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[3] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[1] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[8] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[7] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[5] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 .gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -1997,6 +2112,34 @@ .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[1] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -2044,11 +2187,11 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000011101011 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 @@ -2070,18 +2213,18 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 .gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O @@ -2172,23 +2315,23 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[1] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] +.gate SB_DFFESS C=r_counter D=rx_fifo.empty_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_ioc[1] I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[2] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000000011 .gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7] .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" @@ -2312,10 +2455,10 @@ .gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I2[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 +.param LUT_INIT 0000100000000000 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "smi_ctrl.v:154.5-163.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" @@ -2428,80 +2571,124 @@ .attr src "smi_ctrl.v:124.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_push Q=smi_ctrl_ins.r_fifo_push_1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push_1 I3=smi_ctrl_ins.r_fifo_push O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] +.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push I3=smi_ctrl_ins.r_fifo_push_1 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O +.param LUT_INIT 0000000000110000 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr[2] I2=tx_fifo.rd_addr_gray_wr_r[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr[2] I2=tx_fifo.rd_addr_gray_wr_r[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011110000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001010111110 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.param LUT_INIT 0011001101011010 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[4] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2] -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[5] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010000000000000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000100000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0010100000111100 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[5] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[7] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 I0=$false I1=tx_fifo.wr_addr[8] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001010111110 +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2] +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000001111011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_push_trigger Q=smi_ctrl_ins.r_fifo_push R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:266.5-275.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.attr src "smi_ctrl.v:271.5-280.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" .gate SB_LUT4 I0=$false I1=$false I2=i_smi_soe_se I3=i_rst_b O=smi_ctrl_ins.soe_and_reset .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" @@ -2555,7 +2742,7 @@ .param LUT_INIT 0000111100000000 .gate SB_DFFNSR C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D Q=smi_ctrl_ins.w_fifo_push_trigger R=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:189.5-264.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" +.attr src "smi_ctrl.v:189.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.i_smi_data_in[7] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" @@ -2564,44 +2751,44 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011001100111111 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:503.5-508.4" +.attr src "top.v:526.5-531.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:512.5-517.4" +.attr src "top.v:535.5-540.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:521.5-526.4" +.attr src "top.v:544.5-549.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:530.5-535.4" +.attr src "top.v:553.5-558.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:539.5-544.4" +.attr src "top.v:562.5-567.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:548.5-553.4" +.attr src "top.v:571.5-576.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:557.5-562.4" +.attr src "top.v:580.5-585.4" .param PIN_TYPE 101001 .param PULLUP 0 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:566.5-571.4" +.attr src "top.v:589.5-594.4" .param PIN_TYPE 101001 .param PULLUP 0 .gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D @@ -2615,10 +2802,17 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1111111011101000 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000100 +.param LUT_INIT 0000000000010111 +.gate SB_DFFER C=r_counter D=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O Q=spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I0_1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" @@ -2626,41 +2820,6 @@ .gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000010111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000010000 .gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_cs_SB_LUT4_I0_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 @@ -2701,7 +2860,7 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1010100000100000 @@ -2731,54 +2890,42 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011000000 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=spi_if_ins.o_load_cmd I3=sys_ctrl_ins.i_cs O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[7] +.gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[7] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[6] +.gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[6] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[5] +.gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[5] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[4] +.gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[4] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[3] +.gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[2] +.gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[1] +.gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[0] +.gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.r_tx_byte[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0101011100000000 @@ -2845,31 +2992,31 @@ .gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.o_spi_miso .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=spi_if_ins.r_tx_byte[7] I1=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D +.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011001111 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000100010001011 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.param LUT_INIT 1010100011111101 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[7] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000101000101 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.param LUT_INIT 0101001100000000 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[6] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010101000001000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[7] I2=spi_if_ins.spi.r_tx_byte[6] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +.param LUT_INIT 0000000001010011 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_byte[0] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_byte[4] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011001100001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_byte[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 @@ -3017,32 +3164,16 @@ .gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] O=spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100000000 .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" @@ -3050,7 +3181,31 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] O=spi_if_ins.state_if_SB_DFFESR_Q_E +.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I3=spi_if_ins.state_if_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000011110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_D[2] I3=spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=spi_if_ins.state_if_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0101010111011111 @@ -3061,14 +3216,6 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] O=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111011100100000 .gate SB_DFFNSS C=lvds_clock D=tx_fifo.empty_o_SB_DFFNSS_Q_D Q=tx_fifo.empty_o S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:84.2-92.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:18.59-18.105" @@ -3076,195 +3223,135 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1110101010101010 -.gate SB_LUT4 I0=tx_fifo.empty_o I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.empty_o_SB_LUT4_I0_O[1] +.gate SB_LUT4 I0=lvds_tx_inst.r_pulled I1=tx_fifo.empty_o I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_gray[9] O=tx_fifo.empty_o_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000100010 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.empty_o_SB_LUT4_I0_O[0] +.param LUT_INIT 0100010000000100 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.empty_o_SB_LUT4_I1_O[1] I2=tx_fifo.empty_o_SB_LUT4_I1_O[2] I3=tx_fifo.empty_o_SB_LUT4_I1_O[3] O=tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1101110100001101 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr[6] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O[2] +.param LUT_INIT 0000000010010000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.empty_o_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.empty_o_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr[6] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010010111110 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[7] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111110101000001 -.gate SB_LUT4 I0=tx_fifo.rd_addr[5] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001011 -.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100101101111 -.gate SB_LUT4 I0=tx_fifo.rd_addr[3] I1=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001110 -.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_I0_O[0] I1=tx_fifo.empty_o_SB_LUT4_I0_O[1] I2=tx_fifo.empty_o_SB_LUT4_I0_O[2] I3=tx_fifo.empty_o_SB_LUT4_I0_O[3] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[2] I3=tx_fifo.rd_addr[2] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=tx_fifo.rd_addr[8] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100010101011100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 .gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:57.2-65.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.wr_addr[1] I3=tx_fifo.rd_addr_gray_wr_r[0] O=tx_fifo.full_o_SB_LUT4_I1_O[0] +.param LUT_INIT 1110101011000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o_SB_LUT4_I1_O[0] I2=tx_fifo.full_o_SB_LUT4_I1_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.full_o_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010101000010101 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.param LUT_INIT 1100110000001100 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010001011110011 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[7] I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000001001000001 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[5] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[6] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[4] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[3] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.empty_o_SB_LUT4_I1_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[7] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[8] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[5] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[1] +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[4] .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[3] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[2] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[1] +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.empty_o_SB_LUT4_I1_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O @@ -3274,59 +3361,43 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[7] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010001011110011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.param LUT_INIT 1100111101000101 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:67.2-76.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" .gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O @@ -3336,30 +3407,6 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111101000101 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[8] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[7] -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:73.15-73.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" @@ -3420,95 +3467,87 @@ .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:52.2-55.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[5] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[2] +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[6] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[1] +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[5] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[4] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[3] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[1] +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1000001001000001 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 @@ -3516,91 +3555,99 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 1100111101000101 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000001101001 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000000100011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:41.2-49.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 .gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] +.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] .attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" @@ -3661,84 +3708,15 @@ .gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0] .attr module_not_derived 00000000000000000000000000000001 .attr src "complex_fifo.v:79.2-82.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] +.gate SB_LUT4 I0=w_lvds_rx_09_d0 I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] O=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000011111101 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I2=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000111100000011 .gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d0_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[0] E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] O=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I2=$true I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100010000010 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010101000101010 -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2] I2=$true I3=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001000101000 -.gate SB_CARRY CI=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 CO=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1] I1=$true -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[0] I1=w_lvds_rx_09_d0_SB_LUT4_I2_O[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101000111011101 -.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] O=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] +.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q O=w_lvds_rx_24_d1_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0000000011111101 @@ -3746,29 +3724,69 @@ .attr module_not_derived 00000000000000000000000000000001 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000011110000 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] +.names tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] +.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0] +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[0] 1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1] +.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] 1 1 -.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] 1 1 -.names io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2] +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.names i_rst_b io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_2_D[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[2] +1 1 +.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +1 1 +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] 1 1 .names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[3] +1 1 +.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +1 1 +.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +1 1 +.names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[0] +1 1 +.names lvds_tx_inst.r_pulled tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I1[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_I2[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] 1 1 .names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0] 1 1 @@ -3776,439 +3794,379 @@ 1 1 .names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0] +.names io_ctrl_ins.rf_pin_state[0] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1] +.names i_rst_b w_lvds_rx_09_d0_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] +.names rx_fifo.rd_addr[7] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O[1] -1 1 -.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] -1 1 -.names tx_fifo.rd_addr[6] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1] -1 1 -.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0] -1 1 -.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O[1] -1 1 -.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] -1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[1] -1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[2] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1] 1 1 .names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] 1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[3] +.names tx_fifo.rd_addr[4] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] 1 1 -.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.names tx_fifo.wr_addr_gray_rd_r[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] 1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.names tx_fifo.rd_addr[3] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[1] 1 1 .names i_rst_b w_lvds_rx_24_d1_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_ioc[0] io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[0] +.names io_ctrl_ins.o_data_out[5] spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] 1 1 -.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[0] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q[1] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[1] +.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[2] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3[2] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[0] +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] 1 1 -.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] 1 1 -.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[1] +1 1 +.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[0] +1 1 +.names smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[2] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[3] +1 1 +.names rx_fifo.wr_addr[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[0] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[1] +1 1 +.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O[2] +1 1 +.names rx_fifo.rd_addr[5] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0] +1 1 +.names rx_fifo.rd_addr[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[1] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3[2] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +1 1 +.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[0] +1 1 +.names $true rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[2] +1 1 +.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I3_O rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O[3] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] +1 1 +.names rx_fifo.empty_o rx_fifo.empty_o_SB_LUT4_I0_I3[0] +1 1 +.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.empty_o_SB_LUT4_I0_I3[1] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.empty_o_SB_LUT4_I0_I3[2] +1 1 +.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0] +1 1 +.names $true lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] 1 1 .names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] 1 1 .names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] 1 1 -.names i_config[1] o_led1_SB_LUT4_I1_I3[0] +.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[0] 1 1 -.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I3[1] +.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O[1] 1 1 -.names o_led1_SB_LUT4_I1_I2[1] o_led1_SB_LUT4_I1_I3[2] +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] -1 1 -.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] -1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[2] o_led1_SB_LUT4_I1_I2[0] -1 1 -.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0] -1 1 -.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1] -1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] -1 1 -.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] 1 1 .names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] 1 1 .names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0[0] o_led1_SB_LUT4_I1_O[0] +.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[0] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] o_led1_SB_LUT4_I1_O[1] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[1] 1 1 -.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.rd_addr_SB_DFFESR_Q_2_D[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] 1 1 -.names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] +.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] 1 1 -.names spi_if_ins.o_ioc[1] o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[0] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] 1 1 -.names spi_if_ins.o_ioc[0] o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[1] +.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] 1 1 -.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] 1 1 -.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] -1 1 -.names io_ctrl_ins.lna_tx_shutdown_state io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[0] -1 1 -.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1[2] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1] -1 1 -.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -1 1 -.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[0] -1 1 -.names o_led1_SB_LUT4_I1_I3[3] io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2] -1 1 -.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_SB_DFFNESR_Q_D[0] -1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_D[1] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[0] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[0] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[3] -1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[0] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I1_I3[1] -1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3[2] -1 1 -.names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] -1 1 -.names o_led1_SB_LUT4_I1_I2[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] -1 1 -.names io_pmod[6] lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[0] -1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[1] -1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3[2] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -1 1 -.names i_rst_b io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[0] -1 1 -.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3[0] -1 1 -.names lvds_rx_24_inst.o_fifo_data[29] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[0] -1 1 -.names $true w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[2] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I3 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] -1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I1[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[2] -1 1 -.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[0] -1 1 -.names sys_ctrl_ins.i_cs sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[0] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I2[2] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[1] w_lvds_rx_09_d0_SB_LUT4_I0_O[0] -1 1 -.names w_lvds_rx_09_d0_SB_LUT4_I2_O[3] w_lvds_rx_09_d0_SB_LUT4_I0_O[2] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led0_SB_LUT4_I1_O[0] -1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] o_led0_SB_LUT4_I1_O[1] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[1] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3[2] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] 1 1 .names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2[2] +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[1] +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] 1 1 -.names rx_fifo.wr_addr[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[0] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[1] -1 1 -.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_3_I3[2] -1 1 -.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[0] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[1] -1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3[2] -1 1 -.names io_ctrl_ins.i_cs io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[0] -1 1 -.names o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2] -1 1 -.names io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[3] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -1 1 -.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] -1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2[1] -1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0] -1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2[1] -1 1 -.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] -1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] -1 1 -.names tx_fifo.wr_addr[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1] -1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2[1] -1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2[1] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -1 1 -.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D[2] rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[0] -1 1 -.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[2] -1 1 -.names rx_fifo.rd_addr_gray_SB_DFFESR_Q_D[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_D_SB_LUT4_I3_I1[3] -1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] rx_fifo.rd_addr_SB_DFFESR_Q_D[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] -1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_I3_O[0] -1 1 -.names rx_fifo.rd_addr[4] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0] -1 1 -.names rx_fifo.rd_addr[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1] -1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2] -1 1 -.names io_ctrl_ins.tr_vc_1_b_state i_config_SB_LUT4_I0_2_O[0] +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] 1 1 .names io_ctrl_ins.rf_pin_state[7] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[9] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[0] +.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 -.names tx_fifo.rd_addr[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[1] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[2] +.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] 1 1 -.names rx_fifo.rd_addr[5] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3[0] +.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] 1 1 -.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.names rx_fifo.rd_addr[2] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.names rx_fifo.rd_addr[1] rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[0] +.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] 1 1 -.names $true rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[2] +.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3] +.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.rd_addr[2] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led1_SB_LUT4_I1_O[0] 1 1 -.names rx_fifo.rd_addr[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led1_SB_LUT4_I1_O[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.names tx_fifo.rd_addr[5] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] 1 1 -.names io_ctrl_ins.rx_h_state i_button_SB_LUT4_I0_O[0] +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] 1 1 -.names i_config_SB_LUT4_I0_2_O[1] i_button_SB_LUT4_I0_O[1] +.names tx_fifo.rd_addr[4] tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] +.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_I1_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I2_O[2] rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[2] +.names i_button io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[0] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +1 1 +.names io_ctrl_ins.rf_pin_state[5] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O[0] +1 1 +.names io_pmod[6] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q[0] 1 1 .names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0] 1 1 -.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] +.names i_config_SB_LUT4_I0_1_O[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] 1 1 -.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[0] +.names tx_fifo.rd_addr[8] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.names tx_fifo.wr_addr_gray_rd_r[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] 1 1 -.names rx_fifo.empty_o rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[0] +.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[1] +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2[1] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_I3[2] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_I3_O[0] +.names tx_fifo.rd_addr[7] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.names tx_fifo.rd_addr[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1] +.names tx_fifo.wr_addr_gray_rd_r[6] lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] 1 1 -.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[0] +.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] 1 1 -.names i_config_SB_LUT4_I0_2_O[1] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1] +.names tx_fifo.rd_addr_gray_wr_r[8] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_6_D[1] +.names i_config[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I1_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1] 1 1 -.names rx_fifo.rd_addr[7] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[0] +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[1] +.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.rd_addr[6] rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_O_I3[2] +.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +1 1 +.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[1] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2[2] +1 1 +.names io_pmod[7] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] +1 1 +.names spi_if_ins.o_ioc[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0] +1 1 +.names sys_ctrl_ins.i_cs lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.o_load_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[1] +1 1 +.names spi_if_ins.o_fetch_cmd lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +1 1 +.names io_ctrl_ins.tr_vc_1_b_state i_config_SB_LUT4_I0_1_O[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[0] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[1] +1 1 +.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3[2] +1 1 +.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O[0] +1 1 +.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[0] +1 1 +.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I2[3] +1 1 +.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] +1 1 +.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_D[0] +1 1 +.names spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O[0] spi_if_ins.state_if_SB_DFFESR_Q_D[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[0] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[1] +1 1 +.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[2] +1 1 +.names i_config[1] o_led1_SB_LUT4_I1_I2[0] +1 1 +.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I2[1] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] o_led1_SB_LUT4_I1_I2[3] +1 1 +.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0] +1 1 +.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I2_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_I3_O[1] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[0] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +1 1 +.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] o_led0_SB_LUT4_I1_O[0] +1 1 +.names io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1] o_led0_SB_LUT4_I1_O[1] +1 1 +.names i_config[0] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[0] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I2_1_O[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[1] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_ioc[1] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.o_ioc[0] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3[3] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[2] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] +1 1 +.names tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[1] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_5_D_SB_LUT4_O_I0[2] +1 1 +.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +1 1 +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[0] +1 1 +.names rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I1[2] rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I1[1] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] +1 1 +.names lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[1] +1 1 +.names rx_fifo.rd_addr_SB_DFFESR_Q_2_D[0] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +1 1 +.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_1_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] +1 1 +.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] 1 1 .names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1] 1 1 @@ -4226,6 +4184,14 @@ 1 1 .names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13] 1 1 +.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13] +1 1 .names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1] 1 1 .names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5] @@ -4242,22 +4208,6 @@ 1 1 .names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13] 1 1 -.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] -1 1 -.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1] -1 1 -.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5] -1 1 -.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9] -1 1 -.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13] -1 1 .names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1] 1 1 .names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5] @@ -4274,7 +4224,15 @@ 1 1 .names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.names smi_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0] +1 1 +.names io_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +1 1 +.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] 1 1 .names spi_if_ins.spi.o_spi_miso int_miso 1 1 @@ -4334,13 +4292,13 @@ 1 1 .names $false io_ctrl_ins.o_mixer_fm 1 1 -.names io_pmod[0] io_ctrl_ins.o_pmod[0] +.names io_ctrl_ins.pmod_state[0] io_ctrl_ins.o_pmod[0] 1 1 -.names io_pmod[1] io_ctrl_ins.o_pmod[1] +.names io_ctrl_ins.pmod_state[1] io_ctrl_ins.o_pmod[1] 1 1 -.names io_pmod[2] io_ctrl_ins.o_pmod[2] +.names io_ctrl_ins.pmod_state[2] io_ctrl_ins.o_pmod[2] 1 1 -.names io_pmod[3] io_ctrl_ins.o_pmod[3] +.names io_ctrl_ins.pmod_state[3] io_ctrl_ins.o_pmod[3] 1 1 .names io_ctrl_ins.rx_h_state io_ctrl_ins.o_rx_h_tx_l 1 1 @@ -4356,13 +4314,11 @@ 1 1 .names io_ctrl_ins.tr_vc_2_state io_ctrl_ins.o_tr_vc2 1 1 -.names io_pmod[0] io_ctrl_ins.pmod_state[0] +.names $false io_pmod[1] 1 1 -.names io_pmod[1] io_ctrl_ins.pmod_state[1] +.names $false io_pmod[2] 1 1 -.names io_pmod[2] io_ctrl_ins.pmod_state[2] -1 1 -.names io_pmod[3] io_ctrl_ins.pmod_state[3] +.names i_smi_swe_srw io_pmod[3] 1 1 .names lvds_clock lvds_clock_buf 1 1 @@ -4476,8 +4432,6 @@ 1 1 .names $false lvds_tx_inst.r_state 1 1 -.names lvds_clock o_iq_tx_clk_p -1 1 .names $undef o_mixer_en 1 1 .names $undef o_mixer_fm @@ -4612,6 +4566,20 @@ 1 1 .names rx_fifo.rd_data_o[31] smi_ctrl_ins.i_rx_fifo_pulled_data[31] 1 1 +.names w_smi_data_input[0] smi_ctrl_ins.i_smi_data_in[0] +1 1 +.names w_smi_data_input[1] smi_ctrl_ins.i_smi_data_in[1] +1 1 +.names w_smi_data_input[2] smi_ctrl_ins.i_smi_data_in[2] +1 1 +.names w_smi_data_input[3] smi_ctrl_ins.i_smi_data_in[3] +1 1 +.names w_smi_data_input[4] smi_ctrl_ins.i_smi_data_in[4] +1 1 +.names w_smi_data_input[5] smi_ctrl_ins.i_smi_data_in[5] +1 1 +.names w_smi_data_input[6] smi_ctrl_ins.i_smi_data_in[6] +1 1 .names i_smi_soe_se smi_ctrl_ins.i_smi_soe_se 1 1 .names i_smi_swe_srw smi_ctrl_ins.i_smi_swe_srw @@ -4628,6 +4596,32 @@ 1 1 .names $false smi_ctrl_ins.int_cnt_rx[2] 1 1 +.names $false smi_ctrl_ins.int_cnt_tx[0] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[1] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[2] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[3] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[4] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[5] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[6] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[7] +1 1 +.names $false smi_ctrl_ins.int_cnt_tx[8] +1 1 +.names $undef smi_ctrl_ins.int_cnt_tx[9] +1 1 +.names $undef smi_ctrl_ins.int_cnt_tx[10] +1 1 +.names $undef smi_ctrl_ins.int_cnt_tx[11] +1 1 +.names $undef smi_ctrl_ins.int_cnt_tx[12] +1 1 .names $false smi_ctrl_ins.o_data_out[3] 1 1 .names $false smi_ctrl_ins.o_data_out[4] @@ -4656,19 +4650,19 @@ 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[6] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[7] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[7] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[8] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[8] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[9] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[9] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[10] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[10] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[11] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[11] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[12] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[12] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[13] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[13] 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[14] 1 1 @@ -4676,23 +4670,23 @@ 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[16] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[17] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[17] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[18] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[18] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[19] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[19] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[20] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[20] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[21] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[21] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[22] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[22] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[23] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[23] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[24] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[24] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[25] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[25] 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[26] 1 1 @@ -4706,70 +4700,6 @@ 1 1 .names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[31] 1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[0] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[1] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[2] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[3] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[4] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[5] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[6] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[7] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[8] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[9] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[10] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[11] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[12] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[13] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[14] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[15] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[16] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[17] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[18] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[19] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[20] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[21] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[22] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[23] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[24] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[25] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[26] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[27] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[28] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[29] -1 1 -.names $false smi_ctrl_ins.r_fifo_pushed_data[30] -1 1 -.names $undef smi_ctrl_ins.r_fifo_pushed_data[31] -1 1 .names r_tx_data[0] spi_if_ins.i_data_out[0] 1 1 .names r_tx_data[1] spi_if_ins.i_data_out[1] @@ -4922,19 +4852,19 @@ 1 1 .names $undef tx_fifo.wr_data_i[6] 1 1 -.names $undef tx_fifo.wr_data_i[7] +.names $false tx_fifo.wr_data_i[7] 1 1 -.names $undef tx_fifo.wr_data_i[8] +.names $false tx_fifo.wr_data_i[8] 1 1 -.names $undef tx_fifo.wr_data_i[9] +.names $false tx_fifo.wr_data_i[9] 1 1 -.names $undef tx_fifo.wr_data_i[10] +.names $false tx_fifo.wr_data_i[10] 1 1 -.names $undef tx_fifo.wr_data_i[11] +.names $false tx_fifo.wr_data_i[11] 1 1 -.names $undef tx_fifo.wr_data_i[12] +.names $false tx_fifo.wr_data_i[12] 1 1 -.names $undef tx_fifo.wr_data_i[13] +.names $false tx_fifo.wr_data_i[13] 1 1 .names $undef tx_fifo.wr_data_i[14] 1 1 @@ -4942,23 +4872,23 @@ 1 1 .names $undef tx_fifo.wr_data_i[16] 1 1 -.names $undef tx_fifo.wr_data_i[17] +.names $false tx_fifo.wr_data_i[17] 1 1 -.names $undef tx_fifo.wr_data_i[18] +.names $false tx_fifo.wr_data_i[18] 1 1 -.names $undef tx_fifo.wr_data_i[19] +.names $false tx_fifo.wr_data_i[19] 1 1 -.names $undef tx_fifo.wr_data_i[20] +.names $false tx_fifo.wr_data_i[20] 1 1 -.names $undef tx_fifo.wr_data_i[21] +.names $false tx_fifo.wr_data_i[21] 1 1 -.names $undef tx_fifo.wr_data_i[22] +.names $false tx_fifo.wr_data_i[22] 1 1 -.names $undef tx_fifo.wr_data_i[23] +.names $false tx_fifo.wr_data_i[23] 1 1 -.names $undef tx_fifo.wr_data_i[24] +.names $false tx_fifo.wr_data_i[24] 1 1 -.names $undef tx_fifo.wr_data_i[25] +.names $false tx_fifo.wr_data_i[25] 1 1 .names $undef tx_fifo.wr_data_i[26] 1 1 @@ -5236,20 +5166,6 @@ 1 1 .names smi_ctrl_ins.r_dir w_smi_data_direction 1 1 -.names smi_ctrl_ins.i_smi_data_in[0] w_smi_data_input[0] -1 1 -.names smi_ctrl_ins.i_smi_data_in[1] w_smi_data_input[1] -1 1 -.names smi_ctrl_ins.i_smi_data_in[2] w_smi_data_input[2] -1 1 -.names smi_ctrl_ins.i_smi_data_in[3] w_smi_data_input[3] -1 1 -.names smi_ctrl_ins.i_smi_data_in[4] w_smi_data_input[4] -1 1 -.names smi_ctrl_ins.i_smi_data_in[5] w_smi_data_input[5] -1 1 -.names smi_ctrl_ins.i_smi_data_in[6] w_smi_data_input[6] -1 1 .names smi_ctrl_ins.i_smi_data_in[7] w_smi_data_input[7] 1 1 .names smi_ctrl_ins.o_smi_data_out[0] w_smi_data_output[0] @@ -5306,19 +5222,19 @@ 1 1 .names $undef w_tx_fifo_data[6] 1 1 -.names $undef w_tx_fifo_data[7] +.names $false w_tx_fifo_data[7] 1 1 -.names $undef w_tx_fifo_data[8] +.names $false w_tx_fifo_data[8] 1 1 -.names $undef w_tx_fifo_data[9] +.names $false w_tx_fifo_data[9] 1 1 -.names $undef w_tx_fifo_data[10] +.names $false w_tx_fifo_data[10] 1 1 -.names $undef w_tx_fifo_data[11] +.names $false w_tx_fifo_data[11] 1 1 -.names $undef w_tx_fifo_data[12] +.names $false w_tx_fifo_data[12] 1 1 -.names $undef w_tx_fifo_data[13] +.names $false w_tx_fifo_data[13] 1 1 .names $undef w_tx_fifo_data[14] 1 1 @@ -5326,23 +5242,23 @@ 1 1 .names $undef w_tx_fifo_data[16] 1 1 -.names $undef w_tx_fifo_data[17] +.names $false w_tx_fifo_data[17] 1 1 -.names $undef w_tx_fifo_data[18] +.names $false w_tx_fifo_data[18] 1 1 -.names $undef w_tx_fifo_data[19] +.names $false w_tx_fifo_data[19] 1 1 -.names $undef w_tx_fifo_data[20] +.names $false w_tx_fifo_data[20] 1 1 -.names $undef w_tx_fifo_data[21] +.names $false w_tx_fifo_data[21] 1 1 -.names $undef w_tx_fifo_data[22] +.names $false w_tx_fifo_data[22] 1 1 -.names $undef w_tx_fifo_data[23] +.names $false w_tx_fifo_data[23] 1 1 -.names $undef w_tx_fifo_data[24] +.names $false w_tx_fifo_data[24] 1 1 -.names $undef w_tx_fifo_data[25] +.names $false w_tx_fifo_data[25] 1 1 .names $undef w_tx_fifo_data[26] 1 1 diff --git a/firmware/top.json b/firmware/top.json index 97da5f3..f891558 100644 --- a/firmware/top.json +++ b/firmware/top.json @@ -21,7 +21,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -404,7 +404,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8333": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8346": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -428,7 +428,7 @@ "Y": [ 78 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8334": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8347": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -452,7 +452,7 @@ "Y": [ 79 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8335": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8348": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -476,7 +476,7 @@ "Y": [ 80 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8336": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8349": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -819,28 +819,28 @@ } }, "netnames": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8333_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661$8346_Y": { "hide_name": 1, "bits": [ 78 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1661.33-1661.44" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8334_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663$8347_Y": { "hide_name": 1, "bits": [ 79 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1663.34-1663.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8335_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669$8348_Y": { "hide_name": 1, "bits": [ 80 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1669.34-1669.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8336_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1673$8349_Y": { "hide_name": 1, "bits": [ 81 ], "attributes": { @@ -952,7 +952,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1022,7 +1022,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1092,7 +1092,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1162,7 +1162,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1232,7 +1232,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1302,7 +1302,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1372,7 +1372,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -1442,7 +1442,7 @@ } }, "cells": { - "$specify$8458": { + "$specify$8471": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -11211,7 +11211,7 @@ "attributes": { "hdlname": "top", "top": "00000000000000000000000000000001", - "src": "top.v:9.1-579.10" + "src": "top.v:9.1-602.10" }, "ports": { "i_glob_clock": { @@ -11296,35 +11296,35 @@ }, "io_pmod": { "direction": "inout", - "bits": [ 23, 24, 25, 26, 27, 28, 29, 30 ] + "bits": [ 23, "0", "0", 24, 25, 26, 27, 28 ] }, "o_led0": { "direction": "output", - "bits": [ 31 ] + "bits": [ 29 ] }, "o_led1": { "direction": "output", - "bits": [ 32 ] + "bits": [ 30 ] }, "i_smi_a2": { "direction": "input", - "bits": [ 33 ] + "bits": [ 31 ] }, "i_smi_a3": { "direction": "input", - "bits": [ 34 ] + "bits": [ 32 ] }, "i_smi_soe_se": { "direction": "input", - "bits": [ 35 ] + "bits": [ 33 ] }, "i_smi_swe_srw": { "direction": "input", - "bits": [ 36 ] + "bits": [ 24 ] }, "io_smi_data": { "direction": "inout", - "bits": [ 37, 38, 39, 40, 41, 42, 43, 44 ] + "bits": [ 34, 35, 36, 37, 38, 39, 40, 41 ] }, "o_smi_write_req": { "direction": "output", @@ -11332,35 +11332,35 @@ }, "o_smi_read_req": { "direction": "output", - "bits": [ 45 ] + "bits": [ 42 ] }, "i_mosi": { "direction": "input", - "bits": [ 46 ] + "bits": [ 43 ] }, "i_sck": { "direction": "input", - "bits": [ 47 ] + "bits": [ 44 ] }, "i_ss": { "direction": "input", - "bits": [ 48 ] + "bits": [ 45 ] }, "o_miso": { "direction": "output", - "bits": [ 49 ] + "bits": [ 46 ] } }, "cells": { - "i_button_SB_LUT4_I0": { + "i_button_SB_LUT4_I1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0001010100111111" + "LUT_INIT": "1100000011111111" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" }, "port_directions": { "I0": "input", @@ -11370,11 +11370,11 @@ "O": "output" }, "connections": { - "I0": [ 22 ], - "I1": [ 50 ], - "I2": [ 51 ], - "I3": [ 52 ], - "O": [ 53 ] + "I0": [ "0" ], + "I1": [ 22 ], + "I2": [ 47 ], + "I3": [ 48 ], + "O": [ 49 ] } }, "i_config_SB_LUT4_I0": { @@ -11396,10 +11396,10 @@ }, "connections": { "I0": [ 21 ], - "I1": [ 54 ], + "I1": [ 50 ], "I2": [ 51 ], - "I3": [ 52 ], - "O": [ 55 ] + "I3": [ 47 ], + "O": [ 52 ] } }, "i_config_SB_LUT4_I0_1": { @@ -11419,40 +11419,15 @@ "I3": "input", "O": "output" }, - "connections": { - "I0": [ 20 ], - "I1": [ 56 ], - "I2": [ 51 ], - "I3": [ 52 ], - "O": [ 57 ] - } - }, - "i_config_SB_LUT4_I0_2": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0001001101011111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, "connections": { "I0": [ 19 ], - "I1": [ 58 ], - "I2": [ 59 ], - "I3": [ 51 ], - "O": [ 60 ] + "I1": [ 53 ], + "I2": [ 51 ], + "I3": [ 54 ], + "O": [ 55 ] } }, - "i_config_SB_LUT4_I0_2_O_SB_LUT4_O": { + "i_config_SB_LUT4_I0_1_O_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -11472,12 +11447,12 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 61 ], - "I3": [ 62 ], - "O": [ 63 ] + "I2": [ 56 ], + "I3": [ 57 ], + "O": [ 58 ] } }, - "i_config_SB_LUT4_I0_2_O_SB_LUT4_O_1": { + "i_config_SB_LUT4_I0_1_O_SB_LUT4_O_1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -11496,10 +11471,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 64 ], - "I2": [ 59 ], - "I3": [ 52 ], - "O": [ 65 ] + "I1": [ 59 ], + "I2": [ 54 ], + "I3": [ 47 ], + "O": [ 60 ] } }, "i_rst_b_SB_LUT4_I1": { @@ -11522,9 +11497,9 @@ "connections": { "I0": [ "0" ], "I1": [ 3 ], - "I2": [ 66 ], - "I3": [ 67 ], - "O": [ 68 ] + "I2": [ 61 ], + "I3": [ 62 ], + "O": [ 63 ] } }, "i_rst_b_SB_LUT4_I3": { @@ -11549,7 +11524,7 @@ "I1": [ "0" ], "I2": [ "0" ], "I3": [ 3 ], - "O": [ 69 ] + "O": [ 64 ] } }, "i_ss_SB_LUT4_I3": { @@ -11573,8 +11548,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 48 ], - "O": [ 70 ] + "I3": [ 45 ], + "O": [ 65 ] } }, "io_ctrl_ins.i_cs_SB_DFFESR_Q": { @@ -11594,11 +11569,11 @@ "R": "input" }, "connections": { - "C": [ 71 ], - "D": [ 72 ], - "E": [ 73 ], - "Q": [ 74 ], - "R": [ 75 ] + "C": [ 66 ], + "D": [ 67 ], + "E": [ 68 ], + "Q": [ 69 ], + "R": [ 70 ] } }, "io_ctrl_ins.i_cs_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -11621,9 +11596,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 76 ], - "I3": [ 77 ], - "O": [ 72 ] + "I2": [ 71 ], + "I3": [ 72 ], + "O": [ 67 ] } }, "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q": { @@ -11642,9 +11617,9 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - "D": [ 78 ], - "E": [ 79 ], + "C": [ 66 ], + "D": [ 73 ], + "E": [ 74 ], "Q": [ 9 ] } }, @@ -11667,10 +11642,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 80 ], - "I2": [ 81 ], - "I3": [ 82 ], - "O": [ 78 ] + "I1": [ 75 ], + "I2": [ 76 ], + "I3": [ 77 ], + "O": [ 73 ] } }, "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q": { @@ -11689,9 +11664,9 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - "D": [ 83 ], - "E": [ 79 ], + "C": [ 66 ], + "D": [ 78 ], + "E": [ 74 ], "Q": [ 10 ] } }, @@ -11713,13 +11688,308 @@ "O": "output" }, "connections": { - "I0": [ 84 ], - "I1": [ 64 ], - "I2": [ 81 ], - "I3": [ 82 ], + "I0": [ 79 ], + "I1": [ 59 ], + "I2": [ 76 ], + "I3": [ 77 ], + "O": [ 78 ] + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1011100000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": 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] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9": { @@ -15234,11 +16262,11 @@ "R": "input" }, "connections": { - "C": [ 13 ], - "D": [ 235 ], - "E": [ 174 ], - "Q": [ 184 ], - "R": [ 176 ] + "C": [ 157 ], + "D": [ 271 ], + "E": [ 211 ], + "Q": [ 220 ], + "R": [ 182 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D_SB_LUT4_O": { @@ -15261,9 +16289,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 233 ], - "I3": [ 165 ], - "O": [ 235 ] + "I2": [ 269 ], + "I3": [ 170 ], + "O": [ 271 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -15286,9 +16314,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 236 ], - "I3": [ 165 ], - "O": [ 173 ] + "I2": [ 272 ], + "I3": [ 170 ], + "O": [ 210 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q": { @@ -15307,10 +16335,10 @@ "Q": "output" }, "connections": { - "C": [ 13 ], - "D": [ 157 ], - "E": [ 174 ], - "Q": [ 201 ] + "C": [ 157 ], + "D": [ 158 ], + "E": [ 211 ], + "Q": [ 237 ] } }, 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], + "O": [ 274 ] } }, - "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q_SB_LUT4_I1": { + "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q_SB_LUT4_I2": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100010101010101" + "LUT_INIT": "1111000000110011" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" }, "port_directions": { "I0": "input", @@ -15575,11 +16603,11 @@ "O": "output" }, "connections": { - "I0": [ 160 ], - "I1": [ 239 ], - "I2": [ 243 ], - "I3": [ 240 ], - "O": [ 248 ] + "I0": [ "0" ], + "I1": [ 161 ], + "I2": [ 275 ], + "I3": [ 284 ], + "O": [ 285 ] } }, "lvds_rx_24_inst.i_sync_input_SB_LUT4_O": { @@ -15601,83 +16629,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 29 ], - "I2": [ 249 ], - "I3": [ 250 ], - "O": [ 237 ] - } - }, - "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q": { - 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"I2": [ 518 ], + "I3": [ 516 ], + "O": [ 491 ] } }, "rx_fifo.mem_i.0.0_WDATA_1_SB_LUT4_O": { @@ -19894,10 +20887,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 192 ], - "I2": [ 270 ], - "I3": [ 476 ], - "O": [ 512 ] + "I1": [ 228 ], + "I2": [ 304 ], + "I3": [ 518 ], + "O": [ 562 ] } }, "rx_fifo.mem_i.0.0_WDATA_2_SB_LUT4_O": { @@ -19919,17 +20912,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 194 ], - "I2": [ 272 ], - "I3": [ 476 ], - "O": [ 511 ] + "I1": [ 230 ], + "I2": [ 306 ], + "I3": [ 518 ], + "O": [ 561 ] } }, "rx_fifo.mem_i.0.0_WDATA_3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -19944,10 +20937,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 268 ], - "I2": [ 190 ], - "I3": [ 476 ], - "O": [ 510 ] + "I1": [ 226 ], + "I2": [ 302 ], + "I3": [ 518 ], + "O": [ 560 ] } }, "rx_fifo.mem_i.0.0_WDATA_SB_LUT4_O": { @@ -19969,10 +20962,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 274 ], - "I2": [ 196 ], - "I3": [ 476 ], - "O": [ 513 ] + "I1": [ 308 ], + "I2": [ 232 ], + "I3": [ 518 ], + "O": [ 563 ] } }, "rx_fifo.mem_i.0.1": { @@ -20017,15 +21010,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], - "RCLK": [ 71 ], - "RCLKE": [ 488 ], - "RDATA": [ 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530 ], + "RADDR": [ 456, 455, 464, 463, 469, 468, 461, 459, 479, 533, "0" ], + "RCLK": [ 66 ], + "RCLKE": [ 534 ], + "RDATA": [ 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580 ], "RE": [ "1" ], - "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], - "WCLK": [ 13 ], - "WCLKE": [ 409 ], - "WDATA": [ "0", 531, "0", "0", "0", 532, "0", "0", "0", 533, "0", "0", "0", 534, "0", "0" ], + "WADDR": [ 551, 552, 553, 554, 555, 556, 557, 558, 512, 559, "0" ], + "WCLK": [ 157 ], + "WCLKE": [ 491 ], + "WDATA": [ "0", 581, "0", "0", "0", 582, "0", "0", "0", 583, "0", "0", "0", 584, "0", "0" ], "WE": [ "1" ] } }, @@ -20048,10 +21041,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 200 ], - "I2": [ 278 ], - "I3": [ 476 ], - "O": [ 533 ] + "I1": [ 236 ], + "I2": [ 312 ], + "I3": [ 518 ], + "O": [ 583 ] } }, "rx_fifo.mem_i.0.1_WDATA_2_SB_LUT4_O": { @@ -20073,17 +21066,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 205 ], - "I2": [ 283 ], - "I3": [ 476 ], - "O": [ 532 ] + "I1": [ 241 ], + "I2": [ 317 ], + "I3": [ 518 ], + "O": [ 582 ] } }, "rx_fifo.mem_i.0.1_WDATA_3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20098,17 +21091,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 198 ], - "I2": [ 276 ], - "I3": [ 476 ], - "O": [ 531 ] + "I1": [ 310 ], + "I2": [ 234 ], + "I3": [ 518 ], + "O": [ 581 ] } }, "rx_fifo.mem_i.0.1_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20123,10 +21116,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 207 ], - "I2": [ 285 ], - "I3": [ 476 ], - "O": [ 534 ] + "I1": [ 319 ], + "I2": [ 243 ], + "I3": [ 518 ], + "O": [ 584 ] } }, "rx_fifo.mem_i.0.2": { @@ -20171,15 +21164,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], - "RCLK": [ 71 ], - "RCLKE": [ 488 ], - "RDATA": [ 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550 ], + "RADDR": [ 456, 455, 464, 463, 469, 468, 461, 459, 479, 533, "0" ], + "RCLK": [ 66 ], + "RCLKE": [ 534 ], + "RDATA": [ 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600 ], "RE": [ "1" ], - "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], - "WCLK": [ 13 ], - "WCLKE": [ 409 ], - "WDATA": [ "0", 551, "0", "0", "0", 552, "0", "0", "0", 553, "0", "0", "0", 554, "0", "0" ], + "WADDR": [ 551, 552, 553, 554, 555, 556, 557, 558, 512, 559, "0" ], + "WCLK": [ 157 ], + "WCLKE": [ 491 ], + "WDATA": [ "0", 601, "0", "0", "0", 602, "0", "0", "0", 603, "0", "0", "0", 604, "0", "0" ], "WE": [ "1" ] } }, @@ -20202,10 +21195,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 289 ], - "I2": [ 211 ], - "I3": [ 476 ], - "O": [ 553 ] + "I1": [ 323 ], + "I2": [ 247 ], + "I3": [ 518 ], + "O": [ 603 ] } }, "rx_fifo.mem_i.0.2_WDATA_2_SB_LUT4_O": { @@ -20227,17 +21220,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 213 ], - "I2": [ 291 ], - "I3": [ 476 ], - "O": [ 552 ] + "I1": [ 249 ], + "I2": [ 325 ], + "I3": [ 518 ], + "O": [ 602 ] } }, "rx_fifo.mem_i.0.2_WDATA_3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20252,10 +21245,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 209 ], - "I2": [ 287 ], - "I3": [ 476 ], - "O": [ 551 ] + "I1": [ 321 ], + "I2": [ 245 ], + "I3": [ 518 ], + "O": [ 601 ] } }, "rx_fifo.mem_i.0.2_WDATA_SB_LUT4_O": { @@ -20277,10 +21270,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 215 ], - "I2": [ 293 ], - "I3": [ 476 ], - "O": [ 554 ] + "I1": [ 251 ], + "I2": [ 327 ], + "I3": [ 518 ], + "O": [ 604 ] } }, "rx_fifo.mem_i.0.3": { @@ -20325,15 +21318,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], - "RCLK": [ 71 ], - "RCLKE": [ 488 ], - "RDATA": [ 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570 ], + "RADDR": [ 456, 455, 464, 463, 469, 468, 461, 459, 479, 533, "0" ], + "RCLK": [ 66 ], + "RCLKE": [ 534 ], + "RDATA": [ 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 616, 617, 618, 619, 620 ], "RE": [ "1" ], - "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], - "WCLK": [ 13 ], - "WCLKE": [ 409 ], - "WDATA": [ "0", 571, "0", "0", "0", 572, "0", "0", "0", 573, "0", "0", "0", 574, "0", "0" ], + "WADDR": [ 551, 552, 553, 554, 555, 556, 557, 558, 512, 559, "0" ], + "WCLK": [ 157 ], + "WCLKE": [ 491 ], + "WDATA": [ "0", 621, "0", "0", "0", 622, "0", "0", "0", 623, "0", "0", "0", 624, "0", "0" ], "WE": [ "1" ] } }, @@ -20341,7 +21334,7 @@ "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20356,17 +21349,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 219 ], - "I2": [ 297 ], - "I3": [ 476 ], - "O": [ 573 ] + "I1": [ 331 ], + "I2": [ 255 ], + "I3": [ 518 ], + "O": [ 623 ] } }, "rx_fifo.mem_i.0.3_WDATA_2_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20381,10 +21374,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 221 ], - "I2": [ 299 ], - "I3": [ 476 ], - "O": [ 572 ] + "I1": [ 333 ], + "I2": [ 257 ], + "I3": [ 518 ], + "O": [ 622 ] } }, "rx_fifo.mem_i.0.3_WDATA_3_SB_LUT4_O": { @@ -20406,17 +21399,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 295 ], - "I2": [ 217 ], - "I3": [ 476 ], - "O": [ 571 ] + "I1": [ 329 ], + "I2": [ 253 ], + "I3": [ 518 ], + "O": [ 621 ] } }, "rx_fifo.mem_i.0.3_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20431,10 +21424,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 223 ], - "I2": [ 301 ], - "I3": [ 476 ], - "O": [ 574 ] + "I1": [ 335 ], + "I2": [ 259 ], + "I3": [ 518 ], + "O": [ 624 ] } }, "rx_fifo.mem_q.0.0": { @@ -20479,15 +21472,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], - "RCLK": [ 71 ], - "RCLKE": [ 488 ], - "RDATA": [ 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590 ], + "RADDR": [ 456, 455, 464, 463, 469, 468, 461, 459, 479, 533, "0" ], + "RCLK": [ 66 ], + "RCLKE": [ 534 ], + "RDATA": [ 625, 626, 627, 628, 629, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640 ], "RE": [ "1" ], - "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], - "WCLK": [ 13 ], - "WCLKE": [ 409 ], - "WDATA": [ "0", 591, "0", "0", "0", 592, "0", "0", "0", 593, "0", "0", "0", 594, "0", "0" ], + "WADDR": [ 551, 552, 553, 554, 555, 556, 557, 558, 512, 559, "0" ], + "WCLK": [ 157 ], + "WCLKE": [ 491 ], + "WDATA": [ "0", 641, "0", "0", "0", 642, "0", "0", "0", 643, "0", "0", "0", 644, "0", "0" ], "WE": [ "1" ] } }, @@ -20495,7 +21488,7 @@ "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1100110011110000" + "LUT_INIT": "1111000011001100" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20510,13 +21503,38 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 279 ], - "I2": [ 201 ], - "I3": [ 476 ], - "O": [ 593 ] + "I1": [ 237 ], + "I2": [ 313 ], + "I3": [ 518 ], + "O": [ 643 ] } }, "rx_fifo.mem_q.0.0_WDATA_2_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111000011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 212 ], + "I2": [ 288 ], + "I3": [ 518 ], + "O": [ 642 ] + } + }, + "rx_fifo.mem_q.0.0_WDATA_3_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { @@ -20535,42 +21553,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 254 ], - "I2": [ 175 ], - "I3": [ 476 ], - "O": [ 592 ] - } - }, - "rx_fifo.mem_q.0.0_WDATA_3_SB_LUT4_O": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "1111000011001100" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ 236 ], - "I2": [ 314 ], - "I3": [ 476 ], - "O": [ 591 ] + "I1": [ 348 ], + "I2": [ 272 ], + "I3": [ 518 ], + "O": [ 641 ] } }, "rx_fifo.mem_q.0.0_WDATA_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20585,10 +21578,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 178 ], - "I2": [ 256 ], - "I3": [ 476 ], - "O": [ 594 ] + "I1": [ 290 ], + "I2": [ 214 ], + "I3": [ 518 ], + "O": [ 644 ] } }, "rx_fifo.mem_q.0.1": { @@ -20633,15 +21626,15 @@ }, "connections": { "MASK": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], - "RADDR": [ 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, "0" ], - "RCLK": [ 71 ], - "RCLKE": [ 488 ], - "RDATA": [ 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610 ], + "RADDR": [ 456, 455, 464, 463, 469, 468, 461, 459, 479, 533, "0" ], + "RCLK": [ 66 ], + "RCLKE": [ 534 ], + "RDATA": [ 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660 ], "RE": [ "1" ], - "WADDR": [ 446, 440, 443, 447, 505, 506, 507, 508, 445, 509, "0" ], - "WCLK": [ 13 ], - "WCLKE": [ 409 ], - "WDATA": [ "0", 611, "0", "0", "0", 612, "0", "0", "0", 613, "0", "0", "0", 614, "0", "0" ], + "WADDR": [ 551, 552, 553, 554, 555, 556, 557, 558, 512, 559, "0" ], + "WCLK": [ 157 ], + "WCLKE": [ 491 ], + "WDATA": [ "0", 661, "0", "0", "0", 662, "0", "0", "0", 663, "0", "0", "0", 664, "0", "0" ], "WE": [ "1" ] } }, @@ -20649,7 +21642,7 @@ "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111000011001100" + "LUT_INIT": "1100110011110000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -20664,10 +21657,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 225 ], - "I2": [ 303 ], - "I3": [ 476 ], - "O": [ 613 ] + "I1": [ 337 ], + "I2": [ 261 ], + "I3": [ 518 ], + "O": [ 663 ] } }, "rx_fifo.mem_q.0.1_WDATA_2_SB_LUT4_O": { @@ -20689,10 +21682,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 227 ], - "I2": [ 305 ], - "I3": [ 476 ], - "O": [ 612 ] + "I1": [ 263 ], + "I2": [ 339 ], + "I3": [ 518 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[ 197 ], + "O": [ 411 ] } }, "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3": { @@ -28725,8 +29735,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ 3 ], - "I3": [ 924 ], - "O": [ 352 ] + "I3": [ 987 ], + "O": [ 405 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q": { @@ -28745,10 +29755,10 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - "D": [ 930 ], - "E": [ 931 ], - "Q": [ 134 ] + "C": [ 66 ], + "D": [ 988 ], + "E": [ 989 ], + "Q": [ 131 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_1": { @@ -28767,10 +29777,10 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - "D": [ 76 ], - "E": [ 931 ], - "Q": [ 136 ] + "C": [ 66 ], + "D": [ 71 ], + "E": [ 989 ], + "Q": [ 134 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_2": { @@ -28789,10 +29799,10 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - "D": [ 77 ], - "E": [ 931 ], - "Q": [ 137 ] + "C": [ 66 ], + "D": [ 72 ], + "E": [ 989 ], + "Q": [ 135 ] } }, "spi_if_ins.o_data_in_SB_DFFE_Q_3": { @@ -28811,10 +29821,10 @@ "Q": "output" }, "connections": { - "C": [ 71 ], - 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"bits": [ 31 ], "attributes": { "src": "top.v:75.11-75.19" } }, "i_smi_a3": { "hide_name": 0, - "bits": [ 34 ], + "bits": [ 32 ], "attributes": { "src": "top.v:76.11-76.19" } }, "i_smi_soe_se": { "hide_name": 0, - "bits": [ 35 ], + "bits": [ 33 ], "attributes": { "src": "top.v:78.11-78.23" } }, "i_smi_swe_srw": { "hide_name": 0, - "bits": [ 36 ], + "bits": [ 24 ], "attributes": { "src": "top.v:79.11-79.24" } }, "i_ss": { "hide_name": 0, - "bits": [ 48 ], + "bits": [ 45 ], "attributes": { "src": "top.v:87.12-87.16" } }, "int_miso": { "hide_name": 0, - "bits": [ 346 ], + "bits": [ 399 ], "attributes": { "src": "top.v:149.8-149.16" } @@ -36331,7 +36167,7 @@ }, "io_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 74 ], + "bits": [ 69 ], "attributes": { "hdlname": "io_ctrl_ins i_cs", "src": "io_ctrl.v:9.22-9.26" @@ -36339,13 +36175,13 @@ }, "io_ctrl_ins.i_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 72 ], + "bits": [ 67 ], "attributes": { } }, "io_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], + "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ], "attributes": { "hdlname": "io_ctrl_ins i_data_in", "src": "io_ctrl.v:7.22-7.31" @@ -36353,7 +36189,7 @@ }, "io_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 118 ], + "bits": [ 95 ], "attributes": { "hdlname": "io_ctrl_ins i_fetch_cmd", "src": "io_ctrl.v:10.22-10.33" @@ -36361,7 +36197,7 @@ }, "io_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 61, 106, 345, 344, 343 ], + "bits": [ 56, 97, 208, 207, 206 ], "attributes": { "hdlname": "io_ctrl_ins i_ioc", "src": "io_ctrl.v:6.22-6.27" @@ -36369,7 +36205,7 @@ }, "io_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 94 ], "attributes": { "hdlname": "io_ctrl_ins i_load_cmd", "src": "io_ctrl.v:11.22-11.32" @@ -36385,7 +36221,7 @@ }, "io_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "io_ctrl_ins i_sys_clk", "src": "io_ctrl.v:4.22-4.31" @@ -36393,7 +36229,7 @@ }, "io_ctrl_ins.led0_state": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 29 ], "attributes": { "hdlname": "io_ctrl_ins led0_state", "src": "io_ctrl.v:73.17-73.27" @@ -36401,7 +36237,7 @@ }, "io_ctrl_ins.led1_state": { "hide_name": 0, - "bits": [ 32 ], + "bits": [ 30 ], "attributes": { "hdlname": "io_ctrl_ins led1_state", "src": "io_ctrl.v:74.17-74.27" @@ -36417,7 +36253,7 @@ }, "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 78 ], + "bits": [ 73 ], "attributes": { } }, @@ -36431,13 +36267,61 @@ }, "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 83 ], + "bits": [ 78 ], "attributes": { } }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O": { + "hide_name": 0, + "bits": [ 82, 51, 81 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 86, 96, 83 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "defaultvalue": "1", + "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q": { + "hide_name": 0, + "bits": [ 101, 59, 76, 77 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q": { + "hide_name": 0, + "bits": [ 90, 88 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 3, 88, 93 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.mixer_en_state": { "hide_name": 0, - "bits": [ 86 ], + "bits": [ 100 ], "attributes": { "hdlname": "io_ctrl_ins mixer_en_state", "src": "io_ctrl.v:78.17-78.31" @@ -36445,13 +36329,13 @@ }, "io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 85 ], + "bits": [ 99 ], "attributes": { } }, "io_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 122, 91, 100, 94, 125, 132, 130, 128 ], + "bits": [ 119, 106, 114, 109, 129, 126, 124, 122 ], "attributes": { "hdlname": "io_ctrl_ins o_data_out", "src": "io_ctrl.v:8.22-8.32" @@ -36459,33 +36343,25 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 93 ], + "bits": [ 108 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 98 ], + "bits": [ 112 ], "attributes": { } }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D_SB_LUT4_O_I1": { - "hide_name": 0, - "bits": [ 10, 102, 63, 103 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E": { "hide_name": 0, - "bits": [ 99 ], + "bits": [ 113 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R": { "hide_name": 0, - "bits": [ 59, 101 ], + "bits": [ 54, 115 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36493,125 +36369,71 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 89 ], - "attributes": { - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0": { - "hide_name": 0, - "bits": [ 108, 114 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 112 ], - "attributes": { - "defaultvalue": "1", - "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_3_Q": { - "hide_name": 0, - "bits": [ 104, 105, 51, 95 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q": { - "hide_name": 0, - "bits": [ 3, 114, 64, 81 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_1_O": { - "hide_name": 0, - "bits": [ 146, 64, 81, 82 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_I3": { - "hide_name": 0, - "bits": [ 108, 120 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 79 ], + "bits": [ 104 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 92 ], + "bits": [ 107 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 121 ], + "bits": [ 118 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 126 ], + "bits": [ 123 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D": { "hide_name": 0, - "bits": [ 129 ], + "bits": [ 125 ], "attributes": { } }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D": { "hide_name": 0, - "bits": [ 131 ], + "bits": [ 128 ], "attributes": { } }, - "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E": { - "hide_name": 0, - "bits": [ 127 ], - "attributes": { - } - }, - "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1": { - "hide_name": 0, - "bits": [ 74, 133, 107, 62 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 106, 61, 90 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.o_data_out_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 124 ], + "bits": [ 49 ], "attributes": { } }, + "io_ctrl_ins.o_data_out_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + } + }, + "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1": { + "hide_name": 0, + "bits": [ 69, 130, 98, 57 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 97, 56, 105 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.o_led0": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 29 ], "attributes": { "hdlname": "io_ctrl_ins o_led0", "src": "io_ctrl.v:16.22-16.28" @@ -36619,7 +36441,7 @@ }, "io_ctrl_ins.o_led1": { "hide_name": 0, - "bits": [ 32 ], + "bits": [ 30 ], "attributes": { "hdlname": "io_ctrl_ins o_led1", "src": "io_ctrl.v:17.22-17.28" @@ -36643,7 +36465,7 @@ }, "io_ctrl_ins.o_pmod": { "hide_name": 0, - "bits": [ 23, 24, 25, 26 ], + "bits": [ 102, 142, 80, 141 ], "attributes": { "hdlname": "io_ctrl_ins o_pmod", "src": "io_ctrl.v:18.22-18.28" @@ -36707,7 +36529,7 @@ }, "io_ctrl_ins.pmod_dir_state": { "hide_name": 0, - "bits": [ 140, 139, 104, 138, 58, 56, 54, 50 ], + "bits": [ 139, 138, 82, 137, 53, 136, 50, 133 ], "attributes": { "hdlname": "io_ctrl_ins pmod_dir_state", "src": "io_ctrl.v:75.17-75.31" @@ -36715,15 +36537,41 @@ }, "io_ctrl_ins.pmod_state": { "hide_name": 0, - "bits": [ 23, 24, 25, 26 ], + "bits": [ 102, 142, 80, 141 ], "attributes": { "hdlname": "io_ctrl_ins pmod_state", "src": "io_ctrl.v:76.17-76.27" } }, + "io_ctrl_ins.pmod_state_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + } + }, + "io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 143, 51 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + } + }, + "io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + } + }, "io_ctrl_ins.rf_pin_state": { "hide_name": 0, - "bits": [ 87, 80, 84, 146, 145, 144, 143, 142 ], + "bits": [ 101, 75, 79, 149, 148, 147, 146, 145 ], "attributes": { "hdlname": "io_ctrl_ins rf_pin_state", "src": "io_ctrl.v:77.17-77.29" @@ -36739,13 +36587,13 @@ }, "io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 147 ], + "bits": [ 150 ], "attributes": { } }, "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3": { "hide_name": 0, - "bits": [ 5, 63, 55 ], + "bits": [ 5, 58, 52 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36761,13 +36609,27 @@ }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 149 ], + "bits": [ 152 ], "attributes": { } }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 142, 82, 148 ], + "bits": [ 145, 77, 151 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + } + }, + "io_ctrl_ins.rx_h_state_SB_LUT4_I0_O": { + "hide_name": 0, + "bits": [ 22, 47, 48 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36783,7 +36645,7 @@ }, "io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 150 ], + "bits": [ 153 ], "attributes": { } }, @@ -36797,21 +36659,21 @@ }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 152 ], + "bits": [ 155 ], "attributes": { } }, - "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2": { + "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 145, 81, 151, 82 ], + "bits": [ 147, 77, 154 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3": { + "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 6, 63, 57 ], + "bits": [ 20, 47, 127 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36827,13 +36689,13 @@ }, "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 153 ], + "bits": [ 156 ], "attributes": { } }, "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 81, 95, 96, 97 ], + "bits": [ 18, 54, 110, 111 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36841,69 +36703,35 @@ }, "io_pmod": { "hide_name": 0, - "bits": [ 23, 24, 25, 26, 27, 28, 29, 30 ], + "bits": [ 23, "0", "0", 24, 25, 26, 27, 28 ], "attributes": { "src": "top.v:43.17-43.24" } }, - "io_pmod_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 154 ], - "attributes": { - } - }, - "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 61, 155, 62 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O": { - "hide_name": 0, - "bits": [ 141 ], - "attributes": { - } - }, - "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 135 ], - "attributes": { - } - }, - "io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 61, 62 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_smi_data": { "hide_name": 0, - "bits": [ 37, 38, 39, 40, 41, 42, 43, 44 ], + "bits": [ 34, 35, 36, 37, 38, 39, 40, 41 ], "attributes": { "src": "top.v:80.17-80.28" } }, "lvds_clock": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { - "src": "top.v:248.8-248.18" + "src": "top.v:253.8-253.18" } }, "lvds_clock_buf": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { - "src": "top.v:249.8-249.22" + "src": "top.v:254.8-254.22" } }, "lvds_rx_09_inst.i_ddr_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_clk", "src": "lvds_rx.v:3.17-3.26" @@ -36911,7 +36739,7 @@ }, "lvds_rx_09_inst.i_ddr_data": { "hide_name": 0, - "bits": [ 158, 157 ], + "bits": [ 159, 158 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_data", "src": "lvds_rx.v:4.17-4.27" @@ -36919,7 +36747,7 @@ }, "lvds_rx_09_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 403 ], + "bits": [ 485 ], "attributes": { "hdlname": "lvds_rx_09_inst i_fifo_full", "src": "lvds_rx.v:6.23-6.34" @@ -36935,7 +36763,7 @@ }, "lvds_rx_09_inst.i_sync_input": { "hide_name": 0, - "bits": [ 161 ], + "bits": [ 162 ], "attributes": { "hdlname": "lvds_rx_09_inst i_sync_input", "src": "lvds_rx.v:10.23-10.35" @@ -36943,15 +36771,97 @@ }, "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 162 ], + "bits": [ 163, 165 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 166 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" } }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q": { + "hide_name": 0, + "bits": [ 175, 178, 173, 170 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I1": { + "hide_name": 0, + "bits": [ 170, 176, "1", 177 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_1_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:8.8-8.10" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_2_D": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_DFFER_Q_E": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "defaultvalue": "1", + "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D": { + "hide_name": 0, + "bits": [ 169, 167 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "lvds_rx.v:0.0-0.0|lvds_rx.v:43.7-82.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q": { + "hide_name": 0, + "bits": [ 168, 170, 181, 165 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 158, 163, 166 ], + "bits": [ 159, 164, 168, 165 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36959,7 +36869,7 @@ }, "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 30, 168, 169 ], + "bits": [ 28, 184, 185 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -36967,15 +36877,133 @@ }, "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 170 ], + "bits": [ 186 ], "attributes": { "defaultvalue": "1", "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" } }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q": { + "hide_name": 0, + "bits": [ 27, 189, 187 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 97, 56, 192 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "defaultvalue": "1", + "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_1_Q": { + "hide_name": 0, + "bits": [ 194, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q": { + "hide_name": 0, + "bits": [ 195, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q": { + "hide_name": 0, + "bits": [ 196, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q": { + "hide_name": 0, + "bits": [ 193, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + 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"hide_name": 0, + "bits": [ 200 ], + "attributes": { + "defaultvalue": "1", + "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_1_O": { + "hide_name": 0, + "bits": [ 56, 57 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 201, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 185, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "lvds_rx_09_inst.o_fifo_data": { "hide_name": 0, - "bits": [ 236, 201, 175, 178, 203, 225, 227, 229, 231, 233, 181, 184, 180, 183, 186, 188, 190, 192, 194, 196, 198, 200, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223 ], + "bits": [ 272, 237, 212, 214, 239, 261, 263, 265, 267, 269, 217, 220, 216, 219, 222, 224, 226, 228, 230, 232, 234, 236, 241, 243, 245, 247, 249, 251, 253, 255, 257, 259 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_data", "src": "lvds_rx.v:9.23-9.34" @@ -36983,199 +37011,199 @@ }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D": { "hide_name": 0, - "bits": [ 179 ], + "bits": [ 215 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D": { "hide_name": 0, - "bits": [ 182 ], + "bits": [ 218 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D": { "hide_name": 0, - "bits": [ 185 ], + "bits": [ 221 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D": { "hide_name": 0, - "bits": [ 187 ], + "bits": [ 223 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D": { "hide_name": 0, - "bits": [ 189 ], + "bits": [ 225 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D": { "hide_name": 0, - "bits": [ 191 ], + "bits": [ 227 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D": { "hide_name": 0, - "bits": [ 193 ], + "bits": [ 229 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D": { "hide_name": 0, - "bits": [ 195 ], + "bits": [ 231 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D": { "hide_name": 0, - "bits": [ 197 ], + "bits": [ 233 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D": { "hide_name": 0, - "bits": [ 199 ], + "bits": [ 235 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 177 ], + "bits": [ 213 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D": { "hide_name": 0, - "bits": [ 204 ], + "bits": [ 240 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D": { "hide_name": 0, - "bits": [ 206 ], + "bits": [ 242 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D": { "hide_name": 0, - "bits": [ 208 ], + "bits": [ 244 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D": { "hide_name": 0, - "bits": [ 210 ], + "bits": [ 246 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D": { "hide_name": 0, - "bits": [ 212 ], + "bits": [ 248 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D": { "hide_name": 0, - "bits": [ 214 ], + "bits": [ 250 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D": { "hide_name": 0, - "bits": [ 216 ], + "bits": [ 252 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D": { "hide_name": 0, - "bits": [ 218 ], + "bits": [ 254 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D": { "hide_name": 0, - "bits": [ 220 ], + "bits": [ 256 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D": { "hide_name": 0, - "bits": [ 222 ], + "bits": [ 258 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 202 ], + "bits": [ 238 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 224 ], + "bits": [ 260 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 226 ], + "bits": [ 262 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 228 ], + "bits": [ 264 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 230 ], + "bits": [ 266 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 232 ], + "bits": [ 268 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 234 ], + "bits": [ 270 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 235 ], + "bits": [ 271 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 173 ], + "bits": [ 210 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 176 ], + "bits": [ 182 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 167 ], + "bits": [ 183 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_write_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_write_clk", "src": "lvds_rx.v:7.23-7.39" @@ -37183,7 +37211,7 @@ }, "lvds_rx_24_inst.i_ddr_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { "hdlname": "lvds_rx_24_inst i_ddr_clk", "src": "lvds_rx.v:3.17-3.26" @@ -37191,7 +37219,7 @@ }, "lvds_rx_24_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 403 ], + "bits": [ 485 ], "attributes": { "hdlname": "lvds_rx_24_inst i_fifo_full", "src": "lvds_rx.v:6.23-6.34" @@ -37207,7 +37235,7 @@ }, "lvds_rx_24_inst.i_sync_input": { "hide_name": 0, - "bits": [ 237 ], + "bits": [ 273 ], "attributes": { "hdlname": "lvds_rx_24_inst i_sync_input", "src": "lvds_rx.v:10.23-10.35" @@ -37215,7 +37243,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E": { "hide_name": 0, - "bits": [ 238, 240 ], + "bits": [ 274, 276 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37223,7 +37251,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 241 ], + "bits": [ 277 ], "attributes": { "defaultvalue": "1", "src": "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37231,7 +37259,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q": { "hide_name": 0, - "bits": [ 297, 245 ], + "bits": [ 281 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37239,7 +37267,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D": { "hide_name": 0, - "bits": [ 244, 242 ], + "bits": [ 280, 278 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "lvds_rx.v:0.0-0.0|lvds_rx.v:43.7-82.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22" @@ -37247,7 +37275,7 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q": { "hide_name": 0, - "bits": [ 243, 245, 247 ], + "bits": [ 279, 281, 283 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37255,31 +37283,15 @@ }, "lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q": { "hide_name": 0, - "bits": [ 160, 239, 243, 240 ], + "bits": [ 161, 275, 284 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 29, 249, 250 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E": { - "hide_name": 0, - "bits": [ 171 ], - "attributes": { - "defaultvalue": "1", - "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, "lvds_rx_24_inst.o_fifo_data": { "hide_name": 0, - "bits": [ 314, 279, 254, 256, 281, 303, 305, 307, 309, 311, 259, 262, 258, 261, 264, 266, 268, 270, 272, 274, 276, 278, 283, 285, 287, 289, 291, 293, 295, 297, 299, 301 ], + "bits": [ 348, 313, 288, 290, 315, 337, 339, 341, 343, 345, 293, 296, 292, 295, 298, 300, 302, 304, 306, 308, 310, 312, 317, 319, 321, 323, 325, 327, 329, 331, 333, 335 ], "attributes": { "hdlname": "lvds_rx_24_inst o_fifo_data", "src": "lvds_rx.v:9.23-9.34" @@ -37287,205 +37299,205 @@ }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D": { "hide_name": 0, - "bits": [ 257 ], + "bits": [ 291 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D": { "hide_name": 0, - "bits": [ 260 ], + "bits": [ 294 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D": { "hide_name": 0, - "bits": [ 263 ], + "bits": [ 297 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D": { "hide_name": 0, - "bits": [ 265 ], + "bits": [ 299 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D": { "hide_name": 0, - "bits": [ 267 ], + "bits": [ 301 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D": { "hide_name": 0, - "bits": [ 269 ], + "bits": [ 303 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D": { "hide_name": 0, - "bits": [ 271 ], + "bits": [ 305 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D": { "hide_name": 0, - "bits": [ 273 ], + "bits": [ 307 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D": { "hide_name": 0, - "bits": [ 275 ], + "bits": [ 309 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D": { "hide_name": 0, - "bits": [ 277 ], + "bits": [ 311 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 255 ], + "bits": [ 289 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D": { "hide_name": 0, - "bits": [ 282 ], + "bits": [ 316 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D": { "hide_name": 0, - "bits": [ 284 ], + "bits": [ 318 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D": { "hide_name": 0, - "bits": [ 286 ], + "bits": [ 320 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D": { "hide_name": 0, - "bits": [ 288 ], + "bits": [ 322 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D": { "hide_name": 0, - "bits": [ 290 ], + "bits": [ 324 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D": { "hide_name": 0, - "bits": [ 292 ], + "bits": [ 326 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D": { "hide_name": 0, - "bits": [ 294 ], + "bits": [ 328 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D": { "hide_name": 0, - "bits": [ 296 ], + "bits": [ 330 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D": { "hide_name": 0, - "bits": [ 298 ], + "bits": [ 332 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D": { "hide_name": 0, - "bits": [ 300 ], + "bits": [ 334 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 280 ], + "bits": [ 314 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 302 ], + "bits": [ 336 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 304 ], + "bits": [ 338 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 306 ], + "bits": [ 340 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 308 ], + "bits": [ 342 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 310 ], + "bits": [ 344 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 312 ], + "bits": [ 346 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 313 ], + "bits": [ 347 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 252 ], + "bits": [ 286 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 246 ], + "bits": [ 282 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 248 ], + "bits": [ 285 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 315 ], + "bits": [ 349 ], "attributes": { } }, "lvds_rx_24_inst.o_fifo_write_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { "hdlname": "lvds_rx_24_inst o_fifo_write_clk", "src": "lvds_rx.v:7.23-7.39" @@ -37501,10 +37513,10 @@ }, "lvds_tx_inst.i_fifo_empty": { "hide_name": 0, - "bits": [ 318 ], + "bits": [ 352 ], "attributes": { "hdlname": "lvds_tx_inst i_fifo_empty", - "src": "lvds_tx.v:6.23-6.35" + "src": "lvds_tx.v:6.21-6.33" } }, "lvds_tx_inst.i_rst_b": { @@ -37512,7 +37524,7 @@ "bits": [ 3 ], "attributes": { "hdlname": "lvds_tx_inst i_rst_b", - "src": "lvds_tx.v:2.18-2.25" + "src": "lvds_tx.v:2.21-2.28" } }, "lvds_tx_inst.i_sample_gap": { @@ -37533,7 +37545,7 @@ }, "lvds_tx_inst.o_fifo_pull": { "hide_name": 0, - "bits": [ 317 ], + "bits": [ 351 ], "attributes": { "hdlname": "lvds_tx_inst o_fifo_pull", "src": "lvds_tx.v:8.21-8.32" @@ -37560,26 +37572,26 @@ "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], "attributes": { "hdlname": "lvds_tx_inst r_fifo_data", - "src": "lvds_tx.v:31.14-31.25" + "src": "lvds_tx.v:32.16-32.27" } }, "lvds_tx_inst.r_pulled": { "hide_name": 0, - "bits": [ 317 ], + "bits": [ 351 ], "attributes": { "hdlname": "lvds_tx_inst r_pulled", - "src": "lvds_tx.v:32.9-32.17" + "src": "lvds_tx.v:33.9-33.17" } }, "lvds_tx_inst.r_pulled_SB_DFFNESR_Q_D": { "hide_name": 0, - "bits": [ 316 ], + "bits": [ 350 ], "attributes": { } }, "lvds_tx_inst.r_pulled_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 321, 322, 323 ], + "bits": [ 356, 355, 357 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37587,7 +37599,47 @@ }, "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 329, 1028, 334, 324 ], + "bits": [ 363, 367, 358, 372 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 359, 360, 361, 362 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 374, 377, 368, 378 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2": { + "hide_name": 0, + "bits": [ 382, 383 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 385, 386, 387, 388 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 373, 374, 375, 376 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37595,7 +37647,7 @@ }, "lvds_tx_inst.r_pulled_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 341 ], + "bits": [ 397 ], "attributes": { } }, @@ -37604,7 +37656,7 @@ "bits": [ "0" ], "attributes": { "hdlname": "lvds_tx_inst r_state", - "src": "lvds_tx.v:29.9-29.16" + "src": "lvds_tx.v:30.9-30.16" } }, "o_iq_tx_clk_n": { @@ -37637,14 +37689,14 @@ }, "o_led0": { "hide_name": 0, - "bits": [ 31 ], + "bits": [ 29 ], "attributes": { "src": "top.v:44.12-44.18" } }, "o_led0_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 114, 95, 88, 123 ], + "bits": [ 90, 96, 103, 120 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37652,14 +37704,14 @@ }, "o_led1": { "hide_name": 0, - "bits": [ 32 ], + "bits": [ 30 ], "attributes": { "src": "top.v:45.12-45.18" } }, "o_led1_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 342 ], + "bits": [ 398 ], "attributes": { "defaultvalue": "1", "src": "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -37667,23 +37719,7 @@ }, "o_led1_SB_LUT4_I1_I2": { "hide_name": 0, - "bits": [ 64, 59, 52 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "o_led1_SB_LUT4_I1_I3": { - "hide_name": 0, - "bits": [ 19, 58, 59, 51 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "o_led1_SB_LUT4_I1_I3_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 106, 61, 156, 107 ], + "bits": [ 19, 53, 51, 54 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37691,7 +37727,7 @@ }, "o_led1_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 108, 95, 109, 110 ], + "bits": [ 88, 96, 116, 117 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37699,14 +37735,14 @@ }, "o_miso": { "hide_name": 0, - "bits": [ 49 ], + "bits": [ 46 ], "attributes": { "src": "top.v:88.12-88.18" } }, "o_miso_$_TBUF__Y_E": { "hide_name": 0, - "bits": [ 70 ], + "bits": [ 65 ], "attributes": { } }, @@ -37754,7 +37790,7 @@ }, "o_smi_read_req": { "hide_name": 0, - "bits": [ 45 ], + "bits": [ 42 ], "attributes": { "src": "top.v:82.12-82.26" } @@ -37789,33 +37825,33 @@ }, "r_counter": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "src": "top.v:95.14-95.23" } }, "r_counter_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 350 ], + "bits": [ 403 ], "attributes": { } }, "r_tx_data": { "hide_name": 0, - "bits": [ 388, 381, 377, 373, 369, 363, 355, 353 ], + "bits": [ 436, 431, 424, 421, 418, 414, 408, 406 ], "attributes": { "src": "top.v:100.14-100.23" } }, "r_tx_data_SB_DFFE_Q_1_D": { "hide_name": 0, - "bits": [ 354 ], + "bits": [ 407 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 130, 356, 357, 358 ], + "bits": [ 124, 409, 410, 411 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37823,47 +37859,25 @@ }, "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 359 ], + "bits": [ 412 ], "attributes": { } }, - "r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 361, 251 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "r_tx_data_SB_DFFE_Q_2_D": { "hide_name": 0, - "bits": [ 362 ], - "attributes": { - } - }, - "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1": { - "hide_name": 0, - "bits": [ 364, 357, 365 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { - "hide_name": 0, - "bits": [ 366 ], + "bits": [ 413 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_3_D": { "hide_name": 0, - "bits": [ 368 ], + "bits": [ 417 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 125, 370, 357, 358 ], + "bits": [ 129, 419, 410, 411 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37871,19 +37885,19 @@ }, "r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D": { "hide_name": 0, - "bits": [ 371 ], + "bits": [ 209 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_4_D": { "hide_name": 0, - "bits": [ 372 ], + "bits": [ 420 ], "attributes": { } }, "r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 94, 374, 357, 358 ], + "bits": [ 109, 422, 410, 411 ], "attributes": { "force_downto": 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], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1": { + "hide_name": 0, + "bits": [ 474, 475, 476 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3": { + "hide_name": 0, + "bits": [ 456, 478, 479, 482 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I1_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 456, 478, 479, 480 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -37999,7 +38075,7 @@ }, "rx_fifo.full_o": { "hide_name": 0, - "bits": [ 403 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738, 737, 736, 735, 459 ], "attributes": { "hdlname": "rx_fifo rd_addr_gray", "src": "complex_fifo.v:28.23-28.35" } }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D": { + "rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 684, 674, 662, 713 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D": { - "hide_name": 0, - "bits": [ 697, 715 ], + "bits": [ 460, 729, 716 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38729,37 +38701,13 @@ }, "rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 721 ], + "bits": [ 743 ], "attributes": { } }, - "rx_fifo.rd_addr_gray_SB_DFFESR_Q_D": { - "hide_name": 0, - "bits": [ 655, 704 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": 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453, 451, 449, 736, 433, 735, 437, 414, 426, 408 ], + "bits": [ 513, 508, 760, 759, 758, 757, 756, 496, 755, 490 ], "attributes": { "hdlname": "rx_fifo rd_addr_gray_wr_r", "src": "complex_fifo.v:30.23-30.40" @@ -38775,7 +38723,7 @@ }, "rx_fifo.rd_clk_i": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "rx_fifo rd_clk_i", "src": "complex_fifo.v:12.28-12.36" @@ -38783,7 +38731,7 @@ }, "rx_fifo.rd_data_o": { "hide_name": 0, - "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], + "bits": [ 626, 634, 630, 638, 646, 654, 650, 658, 666, 674, 670, 678, 686, 694, 690, 698, 536, 544, 540, 548, 566, 574, 570, 578, 586, 594, 590, 598, 606, 614, 610, 618 ], "attributes": { "hdlname": "rx_fifo rd_data_o", "src": "complex_fifo.v:14.32-14.41" @@ -38799,119 +38747,151 @@ }, "rx_fifo.wr_addr": { "hide_name": 0, - "bits": [ 509, 445, 446, 440, 443, 447, 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"bits": [ 792 ], "attributes": { } }, "rx_fifo.wr_addr_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 738, 737 ], + "bits": [ 762, 761 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38933,7 +38913,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 754 ], + "bits": [ 793 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38941,7 +38921,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, - "bits": [ 755 ], + "bits": [ 794 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38949,7 +38929,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 426, 737, 410, 756 ], + "bits": [ 755, 761, 492, 795 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38957,7 +38937,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 757 ], + "bits": [ 796 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -38965,7 +38945,7 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 758 ], + "bits": [ 797 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": 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+ "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 765, 764 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 739, 738 ], + "bits": [ 763, 762 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -38989,13 +39009,13 @@ }, "rx_fifo.wr_addr_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 514 ], + "bits": [ 564 ], "attributes": { } }, "rx_fifo.wr_addr_gray": { "hide_name": 0, - "bits": [ 774, 772, 771, 769, 767, 765, 763, 762, 761, 508 ], + "bits": [ 818, 816, 815, 813, 811, 809, 807, 806, 805, 558 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray", "src": "complex_fifo.v:24.23-24.35" @@ -39003,13 +39023,13 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 760 ], + "bits": [ 804 ], "attributes": { } }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": { "hide_name": 0, - "bits": [ 735, 764 ], + "bits": [ 757, 808 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39017,7 +39037,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 418, 419, 420, 421 ], + "bits": [ 500, 501, 502, 503 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39025,7 +39045,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 426, 766, 737, 410 ], + "bits": [ 755, 810, 761, 492 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39033,7 +39053,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 437, 433, 748, 759 ], + "bits": [ 756, 758, 802, 803 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39041,7 +39061,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D": { "hide_name": 0, - "bits": [ 736, 768 ], + "bits": [ 759, 812 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39049,7 +39069,7 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 414, 415, 416, 417 ], + "bits": [ 496, 497, 498, 499 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39057,19 +39077,19 @@ }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 770 ], + "bits": [ 814 ], "attributes": { } }, "rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 773 ], + "bits": [ 817 ], "attributes": { } }, "rx_fifo.wr_addr_gray_rd": { "hide_name": 0, - "bits": [ 784, 783, 782, 781, 780, 779, 778, 777, 776, 775 ], + "bits": [ 828, 827, 826, 825, 824, 823, 822, 821, 820, 819 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd", "src": "complex_fifo.v:25.23-25.38" @@ -39077,7 +39097,7 @@ }, "rx_fifo.wr_addr_gray_rd_r": { "hide_name": 0, - "bits": [ 677, 680, 670, 674, 673, 697, 684, 696, 690, 689 ], + "bits": [ 451, 478, 457, 483, 465, 481, 470, 473, 460, 458 ], "attributes": { "hdlname": "rx_fifo wr_addr_gray_rd_r", "src": "complex_fifo.v:26.23-26.40" @@ -39085,7 +39105,7 @@ }, "rx_fifo.wr_clk_i": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { "hdlname": "rx_fifo wr_clk_i", "src": "complex_fifo.v:7.28-7.36" @@ -39101,7 +39121,7 @@ }, "smi_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 477 ], + "bits": [ 441 ], "attributes": { "hdlname": "smi_ctrl_ins i_cs", "src": "smi_ctrl.v:9.25-9.29" @@ -39109,13 +39129,13 @@ }, "smi_ctrl_ins.i_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 785 ], + "bits": [ 829 ], "attributes": { } }, "smi_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], + "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ], "attributes": { "hdlname": "smi_ctrl_ins i_data_in", "src": "smi_ctrl.v:7.25-7.34" @@ -39123,7 +39143,7 @@ }, "smi_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 118 ], + "bits": [ 95 ], "attributes": { "hdlname": "smi_ctrl_ins i_fetch_cmd", "src": "smi_ctrl.v:10.25-10.36" @@ -39131,7 +39151,7 @@ }, "smi_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 61, 106, 345, 344, 343 ], + "bits": [ 56, 97, 208, 207, 206 ], "attributes": { "hdlname": "smi_ctrl_ins i_ioc", "src": "smi_ctrl.v:6.25-6.30" @@ -39139,7 +39159,7 @@ }, "smi_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 94 ], "attributes": { "hdlname": "smi_ctrl_ins i_load_cmd", "src": "smi_ctrl.v:11.25-11.35" @@ -39155,7 +39175,7 @@ }, "smi_ctrl_ins.i_rx_fifo_empty": { "hide_name": 0, - "bits": [ 347 ], + "bits": [ 401 ], "attributes": { "hdlname": "smi_ctrl_ins i_rx_fifo_empty", "src": "smi_ctrl.v:16.25-16.40" @@ -39163,7 +39183,7 @@ }, "smi_ctrl_ins.i_rx_fifo_pulled_data": { "hide_name": 0, - "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], + "bits": [ 626, 634, 630, 638, 646, 654, 650, 658, 666, 674, 670, 678, 686, 694, 690, 698, 536, 544, 540, 548, 566, 574, 570, 578, 586, 594, 590, 598, 606, 614, 610, 618 ], "attributes": { "hdlname": "smi_ctrl_ins i_rx_fifo_pulled_data", "src": "smi_ctrl.v:15.25-15.46" @@ -39171,7 +39191,7 @@ }, "smi_ctrl_ins.i_smi_data_in": { "hide_name": 0, - "bits": [ 914, 915, 916, 917, 918, 919, 920, 904 ], + "bits": [ 979, 980, 981, 982, 983, 984, 985, 969 ], "attributes": { "hdlname": "smi_ctrl_ins i_smi_data_in", "src": "smi_ctrl.v:27.25-27.38", @@ -39180,7 +39200,7 @@ }, "smi_ctrl_ins.i_smi_soe_se": { "hide_name": 0, - "bits": [ 35 ], + "bits": [ 33 ], "attributes": { "hdlname": "smi_ctrl_ins i_smi_soe_se", "src": "smi_ctrl.v:24.25-24.37" @@ -39188,7 +39208,7 @@ }, "smi_ctrl_ins.i_smi_swe_srw": { "hide_name": 0, - "bits": [ 36 ], + "bits": [ 24 ], "attributes": { "hdlname": "smi_ctrl_ins i_smi_swe_srw", "src": "smi_ctrl.v:25.25-25.38" @@ -39204,7 +39224,7 @@ }, "smi_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "smi_ctrl_ins i_sys_clk", "src": "smi_ctrl.v:4.25-4.34" @@ -39212,7 +39232,7 @@ }, "smi_ctrl_ins.i_tx_fifo_full": { "hide_name": 0, - "bits": [ 348 ], + "bits": [ 400 ], "attributes": { "hdlname": "smi_ctrl_ins i_tx_fifo_full", "src": "smi_ctrl.v:20.25-20.39" @@ -39220,7 +39240,7 @@ }, "smi_ctrl_ins.int_cnt_rx": { "hide_name": 0, - "bits": [ "0", "0", "0", 67, 66 ], + "bits": [ "0", "0", "0", 62, 61 ], "attributes": { "hdlname": "smi_ctrl_ins int_cnt_rx", "src": "smi_ctrl.v:110.15-110.25" @@ -39228,19 +39248,27 @@ }, "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D": { "hide_name": 0, - "bits": [ 788 ], + "bits": [ 832 ], "attributes": { } }, "smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D": { "hide_name": 0, - "bits": [ 787 ], + "bits": [ 831 ], "attributes": { } }, + "smi_ctrl_ins.int_cnt_tx": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x" ], + "attributes": { + "hdlname": "smi_ctrl_ins int_cnt_tx", + "src": "smi_ctrl.v:174.16-174.26" + } + }, "smi_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 392, 385, 790, "0", "0", "0", "0", "0" ], + "bits": [ 439, 434, 428, "0", "0", "0", "0", "0" ], "attributes": { "hdlname": "smi_ctrl_ins o_data_out", "src": "smi_ctrl.v:8.25-8.35" @@ -39248,13 +39276,21 @@ }, "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E": { "hide_name": 0, - "bits": [ 789 ], + "bits": [ 833 ], "attributes": { } }, + "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 97, 56, 198, 98 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "smi_ctrl_ins.o_dir": { "hide_name": 0, - "bits": [ 349 ], + "bits": [ 402 ], "attributes": { "hdlname": "smi_ctrl_ins o_dir", "src": "smi_ctrl.v:32.25-32.30" @@ -39262,7 +39298,7 @@ }, "smi_ctrl_ins.o_smi_data_out": { "hide_name": 0, - "bits": [ 842, 834, 826, 818, 810, 802, 794, 792 ], + "bits": [ 885, 877, 869, 861, 853, 845, 837, 835 ], "attributes": { "hdlname": "smi_ctrl_ins o_smi_data_out", "src": "smi_ctrl.v:26.25-26.39" @@ -39270,13 +39306,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D": { "hide_name": 0, - "bits": [ 793 ], + "bits": [ 836 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 795, 796 ], + "bits": [ 838, 839 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39284,13 +39320,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D": { "hide_name": 0, - "bits": [ 801 ], + "bits": [ 844 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 803, 804 ], + "bits": [ 846, 847 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39298,13 +39334,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D": { "hide_name": 0, - "bits": [ 809 ], + "bits": [ 852 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 811, 812 ], + "bits": [ 854, 855 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39312,13 +39348,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D": { "hide_name": 0, - "bits": [ 817 ], + "bits": [ 860 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 819, 820 ], + "bits": [ 862, 863 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39326,13 +39362,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D": { "hide_name": 0, - "bits": [ 825 ], + "bits": [ 868 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 827, 828 ], + "bits": [ 870, 871 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39340,13 +39376,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D": { "hide_name": 0, - "bits": [ 833 ], + "bits": [ 876 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 835, 836 ], + "bits": [ 878, 879 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39354,13 +39390,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D": { "hide_name": 0, - "bits": [ 841 ], + "bits": [ 884 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 843, 844 ], + "bits": [ 886, 887 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39368,13 +39404,13 @@ }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 791 ], + "bits": [ 834 ], "attributes": { } }, "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 849, 850 ], + "bits": [ 892, 893 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39382,7 +39418,7 @@ }, "smi_ctrl_ins.o_tx_fifo_clock": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "smi_ctrl_ins o_tx_fifo_clock", "src": "smi_ctrl.v:21.25-21.40" @@ -39390,7 +39426,7 @@ }, "smi_ctrl_ins.o_tx_fifo_pushed_data": { "hide_name": 0, - "bits": [ "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x" ], + "bits": [ "0", "x", "x", "x", "x", "x", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x", "0", "x" ], "attributes": { "hdlname": "smi_ctrl_ins o_tx_fifo_pushed_data", "src": "smi_ctrl.v:19.25-19.46" @@ -39398,7 +39434,7 @@ }, "smi_ctrl_ins.r_dir": { "hide_name": 0, - "bits": [ 349 ], + "bits": [ 402 ], "attributes": { "hdlname": "smi_ctrl_ins r_dir", "src": "smi_ctrl.v:116.9-116.14" @@ -39406,7 +39442,7 @@ }, "smi_ctrl_ins.r_dir_SB_DFFER_Q_E": { "hide_name": 0, - "bits": [ 855 ], + "bits": [ 898 ], "attributes": { "defaultvalue": "1", "src": "smi_ctrl.v:60.5-104.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" @@ -39414,7 +39450,7 @@ }, "smi_ctrl_ins.r_fifo_pull": { "hide_name": 0, - "bits": [ 856 ], + "bits": [ 899 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pull", "src": "smi_ctrl.v:112.9-112.20" @@ -39422,7 +39458,7 @@ }, "smi_ctrl_ins.r_fifo_pull_1": { "hide_name": 0, - "bits": [ 857 ], + "bits": [ 900 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pull_1", "src": "smi_ctrl.v:113.9-113.22" @@ -39430,7 +39466,7 @@ }, "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 488 ], + "bits": [ 534 ], "attributes": { "defaultvalue": "1", "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765|/usr/local/bin/../share/yosys/ice40/cells_sim.v:1490.16-1490.21" @@ -39438,13 +39474,13 @@ }, "smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I2_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 656 ], + "bits": [ 706 ], "attributes": { } }, "smi_ctrl_ins.r_fifo_pulled_data": { "hide_name": 0, - "bits": [ 846, 838, 830, 822, 814, 806, 798, 852, 845, 837, 829, 821, 813, 805, 797, 851, 848, 840, 832, 824, 816, 808, 800, 854, 847, 839, 831, 823, 815, 807, 799, 853 ], + "bits": [ 889, 881, 873, 865, 857, 849, 841, 895, 888, 880, 872, 864, 856, 848, 840, 894, 891, 883, 875, 867, 859, 851, 843, 897, 890, 882, 874, 866, 858, 850, 842, 896 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_pulled_data", "src": "smi_ctrl.v:117.16-117.34" @@ -39452,13 +39488,13 @@ }, "smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E": { "hide_name": 0, - "bits": [ 68 ], + "bits": [ 63 ], "attributes": { } }, "smi_ctrl_ins.r_fifo_push": { "hide_name": 0, - "bits": [ 859 ], + "bits": [ 902 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_push", "src": "smi_ctrl.v:179.9-179.20" @@ -39466,133 +39502,181 @@ }, "smi_ctrl_ins.r_fifo_push_1": { "hide_name": 0, - "bits": [ 860 ], + "bits": [ 903 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_push_1", "src": "smi_ctrl.v:180.9-180.22" } }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O": { + "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 863, 864, 861 ], + "bits": [ 3, 904 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O": { + "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 865, 870, 873, 877 ], + "bits": [ 908, 913, 918, 940 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3": { + "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3": { "hide_name": 0, - "bits": [ 866, 871, 872, 869 ], + "bits": [ 914, 915, 916, 917 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3": { + "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 879 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:61.24-61.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI": { - 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"smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D": { "hide_name": 0, - "bits": [ 902 ], + "bits": [ 967 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D": { "hide_name": 0, - "bits": [ 906 ], + "bits": [ 971 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D": { "hide_name": 0, - "bits": [ 908 ], + "bits": [ 973 ], "attributes": { } }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 909, 910 ], + "bits": [ 974, 975 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39641,13 +39725,13 @@ }, "smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D": { "hide_name": 0, - "bits": [ 900 ], + "bits": [ 965 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_pull_trigger": { "hide_name": 0, - "bits": [ 858 ], + "bits": [ 901 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_pull_trigger", "src": "smi_ctrl.v:114.10-114.29" @@ -39655,13 +39739,13 @@ }, "smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 911 ], + "bits": [ 976 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_push_trigger": { "hide_name": 0, - "bits": [ 898 ], + "bits": [ 963 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_push_trigger", "src": "smi_ctrl.v:181.10-181.29" @@ -39669,19 +39753,19 @@ }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D": { "hide_name": 0, - "bits": [ 912 ], + "bits": [ 977 ], "attributes": { } }, "smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R": { "hide_name": 0, - "bits": [ 913 ], + "bits": [ 978 ], "attributes": { } }, "spi_if_ins.i_data_out": { "hide_name": 0, - "bits": [ 388, 381, 377, 373, 369, 363, 355, 353 ], + "bits": [ 436, 431, 424, 421, 418, 414, 408, 406 ], "attributes": { "hdlname": "spi_if_ins i_data_out", "src": "spi_if.v:9.22-9.32" @@ -39697,7 +39781,7 @@ }, "spi_if_ins.i_spi_cs_b": { "hide_name": 0, - "bits": [ 48 ], + "bits": [ 45 ], "attributes": { "hdlname": "spi_if_ins i_spi_cs_b", "src": "spi_if.v:18.12-18.22" @@ -39705,7 +39789,7 @@ }, "spi_if_ins.i_spi_mosi": { "hide_name": 0, - "bits": [ 46 ], + "bits": [ 43 ], "attributes": { "hdlname": "spi_if_ins i_spi_mosi", "src": "spi_if.v:17.12-17.22" @@ -39713,7 +39797,7 @@ }, "spi_if_ins.i_spi_sck": { "hide_name": 0, - "bits": [ 47 ], + "bits": [ 44 ], "attributes": { "hdlname": "spi_if_ins i_spi_sck", "src": "spi_if.v:15.12-15.21" @@ -39721,7 +39805,7 @@ }, "spi_if_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "spi_if_ins i_sys_clk", "src": "spi_if.v:5.11-5.20" @@ -39729,7 +39813,7 @@ }, "spi_if_ins.o_cs": { "hide_name": 0, - "bits": [ 923, 74, 477, 922 ], + "bits": [ 197, 69, 441, 440 ], "attributes": { "hdlname": "spi_if_ins o_cs", "src": "spi_if.v:10.22-10.26" @@ -39737,67 +39821,21 @@ }, "spi_if_ins.o_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 921 ], + "bits": [ 986 ], "attributes": { } }, + "spi_if_ins.o_cs_SB_LUT4_I0_1_O": { + "hide_name": 0, + "bits": [ 415, 410, 416 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "spi_if_ins.o_cs_SB_LUT4_I0_3_O": { "hide_name": 0, - "bits": [ 378, 357, 367, 379 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D": { - "hide_name": 0, - "bits": [ 391, 384, 925, 375 ], - "attributes": { - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_1_I2": { - "hide_name": 0, - "bits": [ 927, 251 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_2_I2": { - "hide_name": 0, - "bits": [ 928, 251 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_3_I2": { - "hide_name": 0, - "bits": [ 929, 251 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 926, 251 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E": { - "hide_name": 0, - "bits": [ 360 ], - "attributes": { - "defaultvalue": "1", - "src": "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116|/usr/local/bin/../share/yosys/ice40/cells_sim.v:656.8-656.9" - } - }, - "spi_if_ins.o_cs_SB_LUT4_I0_4_O": { - "hide_name": 0, - "bits": [ 100, 790, 386, 358 ], + "bits": [ 126, 411, 426 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39805,7 +39843,7 @@ }, "spi_if_ins.o_cs_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 3, 924 ], + "bits": [ 3, 987 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39813,13 +39851,13 @@ }, "spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 352 ], + "bits": [ 405 ], "attributes": { } }, "spi_if_ins.o_data_in": { "hide_name": 0, - "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], + "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ], "attributes": { "hdlname": "spi_if_ins o_data_in", "src": "spi_if.v:8.22-8.31" @@ -39827,13 +39865,13 @@ }, "spi_if_ins.o_data_in_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 931 ], + "bits": [ 989 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd": { "hide_name": 0, - "bits": [ 118 ], + "bits": [ 95 ], "attributes": { "hdlname": "spi_if_ins o_fetch_cmd", "src": "spi_if.v:11.22-11.33" @@ -39841,7 +39879,7 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 945, 944, 937 ], + "bits": [ 1003, 1002, 995 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39849,13 +39887,13 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 938 ], + "bits": [ 996 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 3, 945, 946, 947 ], + "bits": [ 3, 1003, 1004, 1005 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39863,7 +39901,7 @@ }, "spi_if_ins.o_ioc": { "hide_name": 0, - "bits": [ 61, 106, 345, 344, 343 ], + "bits": [ 56, 97, 208, 207, 206 ], "attributes": { "hdlname": "spi_if_ins o_ioc", "src": "spi_if.v:7.22-7.27" @@ -39871,13 +39909,13 @@ }, "spi_if_ins.o_ioc_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 73 ], + "bits": [ 68 ], "attributes": { } }, "spi_if_ins.o_load_cmd": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 94 ], "attributes": { "hdlname": "spi_if_ins o_load_cmd", "src": "spi_if.v:12.22-12.32" @@ -39885,7 +39923,7 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 940, 941 ], + "bits": [ 998, 999 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39893,35 +39931,19 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 948 ], + "bits": [ 1006 ], "attributes": { } }, - "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 945, 940, 941, 950 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 949, 950, 951 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 939 ], + "bits": [ 997 ], "attributes": { } }, "spi_if_ins.o_spi_miso": { "hide_name": 0, - "bits": [ 346 ], + "bits": [ 399 ], "attributes": { "hdlname": "spi_if_ins o_spi_miso", "src": "spi_if.v:16.12-16.22" @@ -39929,21 +39951,15 @@ }, "spi_if_ins.r_tx_byte": { "hide_name": 0, - "bits": [ 960, 959, 958, 957, 956, 955, 954, 953 ], + "bits": [ 1018, 1017, 1016, 1015, 1014, 1013, 1012, 1011 ], "attributes": { "hdlname": "spi_if_ins r_tx_byte", "src": "spi_if.v:33.14-33.23" } }, - "spi_if_ins.r_tx_byte_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 952 ], - "attributes": { - } - }, "spi_if_ins.r_tx_data_valid": { "hide_name": 0, - "bits": [ 962 ], + "bits": [ 1020 ], "attributes": { "hdlname": "spi_if_ins r_tx_data_valid", "src": "spi_if.v:32.14-32.29" @@ -39951,19 +39967,19 @@ }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 961 ], + "bits": [ 1019 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 964 ], + "bits": [ 1022 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 969, 968, 963 ], + "bits": [ 1027, 1026, 1021 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -39971,7 +39987,7 @@ }, "spi_if_ins.spi.SCKr": { "hide_name": 0, - "bits": [ 970, 968, 969 ], + "bits": [ 1028, 1026, 1027 ], "attributes": { "hdlname": "spi_if_ins spi SCKr", "src": "spi_slave.v:61.13-61.17" @@ -39979,7 +39995,7 @@ }, "spi_if_ins.spi.i_spi_cs_b": { "hide_name": 0, - "bits": [ 48 ], + "bits": [ 45 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_cs_b", "src": "spi_slave.v:13.16-13.26" @@ -39987,7 +40003,7 @@ }, "spi_if_ins.spi.i_spi_mosi": { "hide_name": 0, - "bits": [ 46 ], + "bits": [ 43 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_mosi", "src": "spi_slave.v:12.16-12.26" @@ -39995,7 +40011,7 @@ }, "spi_if_ins.spi.i_spi_sck": { "hide_name": 0, - "bits": [ 47 ], + "bits": [ 44 ], "attributes": { "hdlname": "spi_if_ins spi i_spi_sck", "src": "spi_slave.v:10.16-10.25" @@ -40003,7 +40019,7 @@ }, "spi_if_ins.spi.i_sys_clk": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "spi_if_ins spi i_sys_clk", "src": "spi_slave.v:3.22-3.31" @@ -40011,7 +40027,7 @@ }, "spi_if_ins.spi.i_tx_byte": { "hide_name": 0, - "bits": [ 960, 959, 958, 957, 956, 955, 954, 953 ], + "bits": [ 1018, 1017, 1016, 1015, 1014, 1013, 1012, 1011 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_byte", "src": "spi_slave.v:7.22-7.31" @@ -40019,7 +40035,7 @@ }, "spi_if_ins.spi.i_tx_data_valid": { "hide_name": 0, - "bits": [ 962 ], + "bits": [ 1020 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_data_valid", "src": "spi_slave.v:6.22-6.37" @@ -40027,7 +40043,7 @@ }, "spi_if_ins.spi.o_rx_byte": { "hide_name": 0, - "bits": [ 936, 935, 934, 933, 932, 77, 76, 930 ], + "bits": [ 994, 993, 992, 991, 990, 72, 71, 988 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_byte", "src": "spi_slave.v:5.22-5.31" @@ -40035,7 +40051,7 @@ }, "spi_if_ins.spi.o_rx_data_valid": { "hide_name": 0, - "bits": [ 945 ], + "bits": [ 1003 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_data_valid", "src": "spi_slave.v:4.22-4.37" @@ -40043,7 +40059,7 @@ }, "spi_if_ins.spi.o_spi_miso": { "hide_name": 0, - "bits": [ 346 ], + "bits": [ 399 ], "attributes": { "hdlname": "spi_if_ins spi o_spi_miso", "src": "spi_slave.v:11.16-11.26" @@ -40051,29 +40067,29 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 980 ], + "bits": [ 1038 ], "attributes": { } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 953, 963, 981, 982 ], + "bits": [ 1011, 1021, 1039 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_1_I2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 983, 984, 987, 988 ], + "bits": [ 1040, 1041, 1042, 1043 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2": { "hide_name": 0, - "bits": [ 983, 984, 985, 986 ], + "bits": [ 1046, 1050, 1051 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40081,7 +40097,7 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 963, 965, 966 ], + "bits": [ 1021, 1023, 1024 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40089,7 +40105,7 @@ }, "spi_if_ins.spi.r2_rx_done": { "hide_name": 0, - "bits": [ 999 ], + "bits": [ 1057 ], "attributes": { "hdlname": "spi_if_ins spi r2_rx_done", "src": "spi_slave.v:21.7-21.17" @@ -40097,7 +40113,7 @@ }, "spi_if_ins.spi.r3_rx_done": { "hide_name": 0, - "bits": [ 1000 ], + "bits": [ 1058 ], "attributes": { "hdlname": "spi_if_ins spi r3_rx_done", "src": "spi_slave.v:22.7-22.17" @@ -40105,13 +40121,13 @@ }, "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 972 ], + "bits": [ 1030 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count": { "hide_name": 0, - "bits": [ 1005, 1004, 1002 ], + "bits": [ 1063, 1062, 1060 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_bit_count", "src": "spi_slave.v:16.13-16.27" @@ -40119,25 +40135,25 @@ }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D": { "hide_name": 0, - "bits": [ 1003 ], + "bits": [ 1061 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D": { "hide_name": 0, - "bits": [ 1006 ], + "bits": [ 1064 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 1001 ], + "bits": [ 1059 ], "attributes": { } }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1007 ], + "bits": [ 1065 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40145,7 +40161,7 @@ }, "spi_if_ins.spi.r_rx_byte": { "hide_name": 0, - "bits": [ 979, 978, 977, 976, 975, 974, 973, 971 ], + "bits": [ 1037, 1036, 1035, 1034, 1033, 1032, 1031, 1029 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_byte", "src": "spi_slave.v:19.13-19.22" @@ -40153,7 +40169,7 @@ }, "spi_if_ins.spi.r_rx_done": { "hide_name": 0, - "bits": [ 998 ], + "bits": [ 1056 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_done", "src": "spi_slave.v:20.7-20.16" @@ -40161,7 +40177,7 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 48, 1016 ], + "bits": [ 45, 1074 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40169,19 +40185,19 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1009 ], + "bits": [ 1067 ], "attributes": { } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 1017 ], + "bits": [ 1075 ], "attributes": { } }, "spi_if_ins.spi.r_temp_rx_byte": { "hide_name": 0, - "bits": [ 1015, 1014, 1013, 1012, 1011, 1010, 1008, "x" ], + "bits": [ 1073, 1072, 1071, 1070, 1069, 1068, 1066, "x" ], "attributes": { "hdlname": "spi_if_ins spi r_temp_rx_byte", "src": "spi_slave.v:18.13-18.27" @@ -40189,7 +40205,7 @@ }, "spi_if_ins.spi.r_tx_bit_count": { "hide_name": 0, - "bits": [ 991, 984, 983 ], + "bits": [ 1047, 1046, 1040 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_bit_count", "src": "spi_slave.v:17.13-17.27" @@ -40197,25 +40213,25 @@ }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 1018 ], + "bits": [ 1076 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D": { "hide_name": 0, - "bits": [ 1020 ], + "bits": [ 1078 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 1019 ], + "bits": [ 1077 ], "attributes": { } }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1021 ], + "bits": [ 1079 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40223,7 +40239,7 @@ }, "spi_if_ins.spi.r_tx_byte": { "hide_name": 0, - "bits": [ 995, 994, 997, 996, 993, 992, 990, 989 ], + "bits": [ 1053, 1052, 1055, 1054, 1049, 1045, 1048, 1044 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_byte", "src": "spi_slave.v:23.13-23.22" @@ -40231,13 +40247,13 @@ }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 967 ], + "bits": [ 1025 ], "attributes": { } }, "spi_if_ins.state_if": { "hide_name": 0, - "bits": [ 943, 942, 940 ], + "bits": [ 1001, 1000, 998 ], "attributes": { "hdlname": "spi_if_ins state_if", "src": "spi_if.v:29.14-29.22" @@ -40245,29 +40261,43 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 1024 ], + "bits": [ 1082 ], "attributes": { } }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 945, 946 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 3, 949, 1022 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "spi_if_ins.state_if_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 930, 946, 1025 ], + "bits": [ 988, 1004, 1083 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.state_if_SB_DFFESR_Q_D": { + "hide_name": 0, + "bits": [ 3, 1007, 1080 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1010 ], + "attributes": { + } + }, + "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1003, 1004 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1007, 1008, 1009 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40275,13 +40305,13 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 1023 ], + "bits": [ 1081 ], "attributes": { } }, "spi_if_ins.w_rx_data": { "hide_name": 0, - "bits": [ 936, 935, 934, 933, 932, 77, 76, 930 ], + "bits": [ 994, 993, 992, 991, 990, 72, 71, 988 ], "attributes": { "hdlname": "spi_if_ins w_rx_data", "src": "spi_if.v:31.14-31.23" @@ -40289,7 +40319,7 @@ }, "spi_if_ins.w_rx_data_valid": { "hide_name": 0, - "bits": [ 945 ], + "bits": [ 1003 ], "attributes": { "hdlname": "spi_if_ins w_rx_data_valid", "src": "spi_if.v:30.14-30.29" @@ -40297,7 +40327,7 @@ }, "sys_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 923 ], + "bits": [ 197 ], "attributes": { "hdlname": "sys_ctrl_ins i_cs", "src": "sys_ctrl.v:9.29-9.33" @@ -40305,21 +40335,13 @@ }, "sys_ctrl_ins.i_cs_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 75 ], + "bits": [ 70 ], "attributes": { } }, - "sys_ctrl_ins.i_cs_SB_LUT4_I2_I3": { - "hide_name": 0, - "bits": [ 118, 923, 1026 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "sys_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], + "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ], "attributes": { "hdlname": "sys_ctrl_ins i_data_in", "src": "sys_ctrl.v:7.29-7.38" @@ -40327,7 +40349,7 @@ }, "sys_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 118 ], + "bits": [ 95 ], "attributes": { "hdlname": "sys_ctrl_ins i_fetch_cmd", "src": "sys_ctrl.v:10.29-10.40" @@ -40335,7 +40357,7 @@ }, "sys_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 61, 106, 345, 344, 343 ], + "bits": [ 56, 97, 208, 207, 206 ], "attributes": { "hdlname": "sys_ctrl_ins i_ioc", "src": "sys_ctrl.v:6.29-6.34" @@ -40343,7 +40365,7 @@ }, "sys_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 94 ], "attributes": { "hdlname": "sys_ctrl_ins i_load_cmd", "src": "sys_ctrl.v:11.29-11.39" @@ -40359,7 +40381,7 @@ }, "sys_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "sys_ctrl_ins i_sys_clk", "src": "sys_ctrl.v:4.29-4.38" @@ -40399,7 +40421,7 @@ }, "tx_fifo.empty_o": { "hide_name": 0, - "bits": [ 318 ], + "bits": [ 352 ], "attributes": { "hdlname": "tx_fifo empty_o", "src": "complex_fifo.v:17.19-17.26" @@ -40407,53 +40429,21 @@ }, "tx_fifo.empty_o_SB_DFFNSS_Q_D": { "hide_name": 0, - "bits": [ 1027 ], + "bits": [ 1084 ], "attributes": { } }, - "tx_fifo.empty_o_SB_LUT4_I0_O": { + "tx_fifo.empty_o_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 1032, 1030, 1036, 1047 ], + "bits": [ 394, 1086, 1085, 1087 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3": { + "tx_fifo.empty_o_SB_LUT4_I1_O_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 1033, 1034, 1035 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_1_I3_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 1043, 1046, 1040, 1038 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3": { - "hide_name": 0, - "bits": [ 1043, 1044, 1045, 1046 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 325, 326, 327, 328 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_2_I3_SB_LUT4_I1_O_SB_LUT4_O_I3": { - "hide_name": 0, - "bits": [ 1049, 1050, 1051, 1052 ], + "bits": [ 390, 391, 385, 392 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40461,7 +40451,7 @@ }, "tx_fifo.full_o": { "hide_name": 0, - "bits": [ 348 ], + "bits": [ 400 ], "attributes": { "hdlname": "tx_fifo full_o", "src": "complex_fifo.v:16.19-16.25" @@ -40469,157 +40459,133 @@ }, "tx_fifo.full_o_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 1055 ], + "bits": [ 1089 ], "attributes": { } }, - "tx_fifo.full_o_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 1060, 1061, 1062 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 1056, 1057, 1058, 1059 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 1063, 1064 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3": { - "hide_name": 0, - "bits": [ 1071, 895, 875, 1072 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": 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"/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.rd_addr_SB_DFFNESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1108, 1097 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40627,49 +40593,37 @@ }, "tx_fifo.rd_addr_SB_DFFNESR_Q_8_D": { "hide_name": 0, - "bits": [ 1093 ], + "bits": [ 1109 ], "attributes": { } }, - "tx_fifo.rd_addr_SB_DFFNESR_Q_D": { - "hide_name": 0, - "bits": [ 1042, 1078, 1077 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "tx_fifo.rd_addr_gray": { "hide_name": 0, - "bits": [ 1107, 1105, 1104, 1103, 1102, 1100, 1099, 1097, 1095, 1031 ], + "bits": [ 1119, 1117, 1116, 1115, 1114, 1113, 1112, 1111, 1110, 384 ], "attributes": { "hdlname": "tx_fifo rd_addr_gray", "src": "complex_fifo.v:28.23-28.35" } }, - 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1127, 1126, 1125, 1124, 1123, 1122, 1121, 1120 ], "attributes": { "hdlname": "tx_fifo rd_addr_gray_wr", "src": "complex_fifo.v:29.23-29.38" @@ -40731,7 +40645,7 @@ }, "tx_fifo.rd_addr_gray_wr_r": { "hide_name": 0, - "bits": [ 871, 864, 1074, 1073, 1069, 897, 1071, 874, 867, 866 ], + "bits": [ 910, 907, 948, 944, 921, 919, 914, 926, 958, 909 ], "attributes": { "hdlname": "tx_fifo rd_addr_gray_wr_r", "src": "complex_fifo.v:30.23-30.40" @@ -40739,7 +40653,7 @@ }, "tx_fifo.rd_en_i": { "hide_name": 0, - "bits": [ 317 ], + "bits": [ 351 ], "attributes": { "hdlname": "tx_fifo rd_en_i", "src": "complex_fifo.v:13.28-13.35" @@ -40755,85 +40669,37 @@ }, "tx_fifo.wr_addr": { "hide_name": 0, - "bits": [ 1139, 892, 863, 891, 889, 887, 885, 883, 881, 878 ], + "bits": [ 1146, 942, 906, 961, 924, 949, 953, 955, 957, 962 ], "attributes": { "hdlname": "tx_fifo wr_addr", "src": "complex_fifo.v:23.23-23.30" } }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D": { + "tx_fifo.wr_addr_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 1069, 1125, 1124 ], + "bits": [ 1140, 1132 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_I3_O": { + "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 874, 1122, 1121, 1126 ], + "bits": [ 944, 1136, 1143, 1133 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3": { + "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1128 ], + "bits": [ 1137 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { - "hide_name": 0, - "bits": [ 1129 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 1071, 1123, 1122 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { - "hide_name": 0, - "bits": [ 1131 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 1133, 1125 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_6_D": { - "hide_name": 0, - "bits": [ 1074, 1134, 1133 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 1073, 1135, 1136, 1137 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": { + "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { "hide_name": 0, "bits": [ 1138 ], "attributes": { @@ -40841,17 +40707,73 @@ "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, - "tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO": { + "tx_fifo.wr_addr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 1132 ], + "bits": [ 1131, 1130 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_3_D": { + "hide_name": 0, + "bits": [ 1142, 1140 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1139 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" } }, + "tx_fifo.wr_addr_SB_DFFESR_Q_4_D": { + "hide_name": 0, + "bits": [ 1135, 1142 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 1141 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { + "hide_name": 0, + "bits": [ 1144 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { + "hide_name": 0, + "bits": [ 1145 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" + } + }, + "tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1134, 1135 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "tx_fifo.wr_addr_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 872, 1134 ], + "bits": [ 911, 1134 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40859,7 +40781,7 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 897, 864, 1140, 1141 ], + "bits": [ 919, 907, 1147, 1148 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40867,13 +40789,13 @@ }, "tx_fifo.wr_addr_SB_DFFESR_Q_8_D": { "hide_name": 0, - "bits": [ 1142 ], + "bits": [ 1149 ], "attributes": { } }, "tx_fifo.wr_addr_gray": { "hide_name": 0, - "bits": [ 1157, 1155, 1154, 1152, 1151, 1149, 1148, 1146, 1144, 878 ], + "bits": [ 1165, 1163, 1161, 1159, 1158, 1156, 1155, 1153, 1151, 962 ], "attributes": { "hdlname": "tx_fifo wr_addr_gray", "src": "complex_fifo.v:24.23-24.35" @@ -40881,31 +40803,31 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 1143 ], + "bits": [ 1150 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 1145 ], + "bits": [ 1152 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 1147 ], + "bits": [ 1154 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 1150 ], + "bits": [ 1157 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": { "hide_name": 0, - "bits": [ 1073, 1074, 1153, 1136 ], + "bits": [ 944, 948, 1160, 1143 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40913,7 +40835,15 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 1065, 1066, 1067, 1068 ], + "bits": [ 935, 936, 937, 938 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 926, 1131, 1130, 1162 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40921,13 +40851,13 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D": { "hide_name": 0, - "bits": [ 1156 ], + "bits": [ 1164 ], "attributes": { } }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 867, 1121, 1076 ], + "bits": [ 1130, 943 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -40935,7 +40865,7 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 1158 ], + "bits": [ 1166 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40943,15 +40873,7 @@ }, "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI": { "hide_name": 0, - "bits": [ 1127 ], - "attributes": { - "abc9_carry": "00000000000000000000000000000001", - "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" - } - }, - "tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI": { - "hide_name": 0, - "bits": [ 1130 ], + "bits": [ 1167 ], "attributes": { "abc9_carry": "00000000000000000000000000000001", "src": "complex_fifo.v:46.15-46.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11" @@ -40959,7 +40881,7 @@ }, "tx_fifo.wr_addr_gray_rd": { "hide_name": 0, - "bits": [ 1168, 1167, 1166, 1165, 1164, 1163, 1162, 1161, 1160, 1159 ], + "bits": [ 1177, 1176, 1175, 1174, 1173, 1172, 1171, 1170, 1169, 1168 ], "attributes": { "hdlname": "tx_fifo wr_addr_gray_rd", "src": "complex_fifo.v:25.23-25.38" @@ -40967,7 +40889,7 @@ }, "tx_fifo.wr_addr_gray_rd_r": { "hide_name": 0, - "bits": [ 320, 338, 1053, 1048, 1045, 337, 1033, 1042, 1054, 335 ], + "bits": [ 394, 381, 389, 386, 391, 393, 368, 375, 364, 353 ], "attributes": { "hdlname": "tx_fifo wr_addr_gray_rd_r", "src": "complex_fifo.v:26.23-26.40" @@ -40975,7 +40897,7 @@ }, "tx_fifo.wr_clk_i": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "hdlname": "tx_fifo wr_clk_i", "src": "complex_fifo.v:7.28-7.36" @@ -40983,7 +40905,7 @@ }, "tx_fifo.wr_data_i": { "hide_name": 0, - "bits": [ "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x" ], + "bits": [ "0", "x", "x", "x", "x", "x", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x", "0", "x" ], "attributes": { "hdlname": "tx_fifo wr_data_i", "src": "complex_fifo.v:9.32-9.41" @@ -41006,14 +40928,14 @@ }, "w_clock_sys": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { "src": "top.v:97.14-97.25" } }, "w_cs": { "hide_name": 0, - "bits": [ 923, 74, 477, 922 ], + "bits": [ 197, 69, 441, 440 ], "attributes": { "src": "top.v:101.14-101.18" } @@ -41027,35 +40949,35 @@ }, "w_fetch": { "hide_name": 0, - "bits": [ 118 ], + "bits": [ 95 ], "attributes": { "src": "top.v:102.14-102.21" } }, "w_ioc": { "hide_name": 0, - "bits": [ 61, 106, 345, 344, 343 ], + "bits": [ 56, 97, 208, 207, 206 ], "attributes": { "src": "top.v:98.14-98.19" } }, "w_load": { "hide_name": 0, - "bits": [ 119 ], + "bits": [ 94 ], "attributes": { "src": "top.v:103.14-103.20" } }, "w_lvds_rx_09_d0": { "hide_name": 0, - "bits": [ 157 ], + "bits": [ 158 ], "attributes": { - "src": "top.v:330.8-330.23" + "src": "top.v:353.8-353.23" } }, "w_lvds_rx_09_d0_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 165, 1169, 472 ], + "bits": [ 3, 1178 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41063,124 +40985,34 @@ }, "w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 174 ], + "bits": [ 211 ], "attributes": { } }, - "w_lvds_rx_09_d0_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 164, 165, 1171, 472 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - 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"top.v:331.8-331.23" + "src": "top.v:354.8-354.23" } }, "w_lvds_rx_24_d0": { "hide_name": 0, - "bits": [ 159 ], + "bits": [ 160 ], "attributes": { - "src": "top.v:332.8-332.23" + "src": "top.v:355.8-355.23" } }, "w_lvds_rx_24_d1": { "hide_name": 0, - "bits": [ 160 ], + "bits": [ 161 ], "attributes": { - "src": "top.v:333.8-333.23" + "src": "top.v:356.8-356.23" } }, "w_lvds_rx_24_d1_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 3, 1185 ], + "bits": [ 3, 1179 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -41188,7 +41020,7 @@ }, "w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 253 ], + "bits": [ 287 ], "attributes": { } }, @@ -41196,161 +41028,161 @@ "hide_name": 0, "bits": [ "0" ], "attributes": { - "src": "top.v:401.8-401.20" + "src": "top.v:424.8-424.20" } }, "w_lvds_tx_d1": { "hide_name": 0, "bits": [ "0" ], "attributes": { - "src": "top.v:402.8-402.20" + "src": "top.v:425.8-425.20" } }, "w_rx_09_fifo_data": { "hide_name": 0, - "bits": [ 236, 201, 175, 178, 203, 225, 227, 229, 231, 233, 181, 184, 180, 183, 186, 188, 190, 192, 194, 196, 198, 200, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223 ], + "bits": [ 272, 237, 212, 214, 239, 261, 263, 265, 267, 269, 217, 220, 216, 219, 222, 224, 226, 228, 230, 232, 234, 236, 241, 243, 245, 247, 249, 251, 253, 255, 257, 259 ], "attributes": { - "src": "top.v:338.15-338.32" + "src": "top.v:361.15-361.32" } }, "w_rx_09_fifo_write_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { - "src": "top.v:336.8-336.30" + "src": "top.v:359.8-359.30" } }, "w_rx_24_fifo_data": { "hide_name": 0, - "bits": [ 314, 279, 254, 256, 281, 303, 305, 307, 309, 311, 259, 262, 258, 261, 264, 266, 268, 270, 272, 274, 276, 278, 283, 285, 287, 289, 291, 293, 295, 297, 299, 301 ], + "bits": [ 348, 313, 288, 290, 315, 337, 339, 341, 343, 345, 293, 296, 292, 295, 298, 300, 302, 304, 306, 308, 310, 312, 317, 319, 321, 323, 325, 327, 329, 331, 333, 335 ], "attributes": { - "src": "top.v:342.15-342.32" + "src": "top.v:365.15-365.32" } }, "w_rx_24_fifo_write_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { - "src": "top.v:340.8-340.30" + "src": "top.v:363.8-363.30" } }, "w_rx_data": { "hide_name": 0, - "bits": [ 113, 111, 117, 116, 115, 137, 136, 134 ], + "bits": [ 89, 87, 84, 92, 91, 135, 134, 131 ], "attributes": { "src": "top.v:99.14-99.23" } }, "w_rx_fifo_empty": { "hide_name": 0, - "bits": [ 347 ], + "bits": [ 401 ], "attributes": { - "src": "top.v:378.8-378.23" + "src": "top.v:401.8-401.23" } }, "w_rx_fifo_full": { "hide_name": 0, - "bits": [ 403 ], + "bits": [ 485 ], "attributes": { - "src": "top.v:377.8-377.22" + "src": "top.v:400.8-400.22" } }, "w_rx_fifo_pulled_data": { "hide_name": 0, - "bits": [ 576, 584, 580, 588, 596, 604, 600, 608, 616, 624, 620, 628, 636, 644, 640, 648, 490, 498, 494, 502, 516, 524, 520, 528, 536, 544, 540, 548, 556, 564, 560, 568 ], + "bits": [ 626, 634, 630, 638, 646, 654, 650, 658, 666, 674, 670, 678, 686, 694, 690, 698, 536, 544, 540, 548, 566, 574, 570, 578, 586, 594, 590, 598, 606, 614, 610, 618 ], "attributes": { - "src": "top.v:376.15-376.36" + "src": "top.v:399.15-399.36" } }, "w_rx_fifo_write_clk": { "hide_name": 0, - "bits": [ 13 ], + "bits": [ 157 ], "attributes": { - "src": "top.v:372.8-372.27" + "src": "top.v:395.8-395.27" } }, "w_rx_sync_input_09": { "hide_name": 0, - "bits": [ 161 ], + "bits": [ 162 ], "attributes": { "src": "top.v:119.8-119.26" } }, "w_rx_sync_input_24": { "hide_name": 0, - "bits": [ 237 ], + "bits": [ 273 ], "attributes": { "src": "top.v:120.8-120.26" } }, "w_smi_data_direction": { "hide_name": 0, - "bits": [ 349 ], + "bits": [ 402 ], "attributes": { - "src": "top.v:451.8-451.28" + "src": "top.v:474.8-474.28" } }, "w_smi_data_input": { "hide_name": 0, - "bits": [ 914, 915, 916, 917, 918, 919, 920, 904 ], + "bits": [ 979, 980, 981, 982, 983, 984, 985, 969 ], "attributes": { - "src": "top.v:490.14-490.30", + "src": "top.v:513.14-513.30", "unused_bits": "0 1 2 3 4 5 6" } }, "w_smi_data_output": { "hide_name": 0, - "bits": [ 842, 834, 826, 818, 810, 802, 794, 792 ], + "bits": [ 885, 877, 869, 861, 853, 845, 837, 835 ], "attributes": { - "src": "top.v:489.14-489.31" + "src": "top.v:512.14-512.31" } }, "w_tx_data_io": { "hide_name": 0, - "bits": [ 122, 91, 100, 94, 125, 132, 130, 128 ], + "bits": [ 119, 106, 114, 109, 129, 126, 124, 122 ], "attributes": { "src": "top.v:106.14-106.26" } }, "w_tx_data_smi": { "hide_name": 0, - "bits": [ 392, 385, 790 ], + "bits": [ 439, 434, 428 ], "attributes": { } }, "w_tx_fifo_clock": { "hide_name": 0, - "bits": [ 71 ], + "bits": [ 66 ], "attributes": { - "src": "top.v:424.8-424.23" + "src": "top.v:447.8-447.23" } }, "w_tx_fifo_data": { "hide_name": 0, - "bits": [ "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "0", "x" ], + "bits": [ "0", "x", "x", "x", "x", "x", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x", "0", "x" ], "attributes": { - "src": "top.v:425.15-425.29" + "src": "top.v:448.15-448.29" } }, "w_tx_fifo_empty": { "hide_name": 0, - "bits": [ 318 ], + "bits": [ 352 ], "attributes": { - "src": "top.v:421.8-421.23" + "src": "top.v:444.8-444.23" } }, "w_tx_fifo_full": { "hide_name": 0, - "bits": [ 348 ], + "bits": [ 400 ], "attributes": { - "src": "top.v:420.8-420.22" + "src": "top.v:443.8-443.22" } }, "w_tx_fifo_pull": { "hide_name": 0, - "bits": [ 317 ], + "bits": [ 351 ], "attributes": { - "src": "top.v:426.8-426.22" + "src": "top.v:449.8-449.22" } } } diff --git a/firmware/top.v b/firmware/top.v index edce3e0..54680a5 100644 --- a/firmware/top.v +++ b/firmware/top.v @@ -199,7 +199,7 @@ module top ( .i_config(i_config), .o_led0 (o_led0), .o_led1 (o_led1), - .o_pmod (io_pmod[3:0]), + .o_pmod (/*io_pmod[3:0]*/), // Analog interfaces .o_mixer_fm(/*o_mixer_fm*/), @@ -213,6 +213,11 @@ module top ( .o_mixer_en(/*o_mixer_en*/) ); + assign io_pmod[0] = ~lvds_clock_buf; + assign io_pmod[1] = w_lvds_tx_d0; + assign io_pmod[2] = w_lvds_tx_d1; + assign io_pmod[3] = i_smi_swe_srw; + //========================================================================= // CONBINATORIAL ASSIGNMENTS //========================================================================= @@ -302,7 +307,7 @@ module top ( .IO_STANDARD("SB_LVCMOS"), ) iq_tx_p ( .PACKAGE_PIN(o_iq_tx_p), - .OUTPUT_CLK(lvds_clock_buf), + .OUTPUT_CLK(~lvds_clock_buf), .D_OUT_0(~w_lvds_tx_d0), .D_OUT_1(~w_lvds_tx_d1) ); @@ -313,16 +318,34 @@ module top ( .IO_STANDARD("SB_LVCMOS"), ) iq_tx_n ( .PACKAGE_PIN(o_iq_tx_n), - .OUTPUT_CLK(lvds_clock_buf), + .OUTPUT_CLK(~lvds_clock_buf), .D_OUT_0(w_lvds_tx_d0), .D_OUT_1(w_lvds_tx_d1) ); + // Non-inverting, P-side clock + SB_IO #( + .PIN_TYPE(6'b011001), + .IO_STANDARD("SB_LVCMOS") + ) iq_tx_clk_p ( + .PACKAGE_PIN(o_iq_tx_clk_p), + .D_OUT_0(lvds_clock_buf), + ); + + // Inverting, N-side clock + SB_IO #( + .PIN_TYPE(6'b011001), + .IO_STANDARD("SB_LVCMOS") + ) iq_tx_clk_n ( + .PACKAGE_PIN(o_iq_tx_clk_n), + .D_OUT_0(~lvds_clock_buf), + ); + // Logic on a clock signal is very bad - try to use a dedicated // SB_IO - assign o_iq_tx_clk_p = lvds_clock_buf; - assign o_iq_tx_clk_n = ~lvds_clock_buf; + //assign o_iq_tx_clk_p = lvds_clock_buf; + //assign o_iq_tx_clk_n = ~lvds_clock_buf; //========================================================================= // LVDS RX SIGNAL FROM MODEM diff --git a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h index a595825..13cd398 100644 --- a/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h +++ b/software/libcariboulite/src/caribou_smi/kernel/smi_stream_dev_gen.h @@ -17,27 +17,27 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-03-14 - * Time: 23:25:30 + * Date: 2024-03-15 + * Time: 00:30:30 */ struct tm smi_stream_dev_date_time = { .tm_sec = 30, - .tm_min = 25, - .tm_hour = 23, - .tm_mday = 14, + .tm_min = 30, + .tm_hour = 0, + .tm_mday = 15, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ }; /* * Data blob of variable smi_stream_dev: - * Size: 34888 bytes + * Size: 35136 bytes * Original filename: /home/pi/cariboulite/driver/build/smi_stream_dev.ko */ uint8_t smi_stream_dev[] = { 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xB7, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x28, 0x00, 0x27, 0x00, 0x3F, 0x23, 0x03, 0xD5, 0x00, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE1, 0x03, 0x00, 0x2A, 0x21, 0x00, 0x01, 0xCA, 0x01, 0x00, 0x00, 0xB5, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, @@ -59,49 +59,50 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x80, 0x52, 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC2, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xB9, 0xA9, 0x03, 0x41, 0x38, 0xD5, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, - 0x14, 0x00, 0x00, 0x90, 0xF3, 0x03, 0x02, 0xAA, 0xF5, 0x5B, 0x02, 0xA9, 0xF5, 0x03, 0x01, 0xAA, + 0x14, 0x00, 0x00, 0x90, 0xF5, 0x5B, 0x02, 0xA9, 0xF6, 0x03, 0x01, 0xAA, 0xF5, 0x03, 0x02, 0xAA, 0x80, 0x02, 0x40, 0xF9, 0x61, 0xCC, 0x42, 0xF9, 0xE1, 0x37, 0x00, 0xF9, 0x01, 0x00, 0x80, 0xD2, - 0xFF, 0x3F, 0x00, 0xB9, 0x00, 0x40, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x60, 0x08, 0x00, 0x35, - 0x83, 0x02, 0x40, 0xF9, 0x60, 0x00, 0x01, 0x91, 0x66, 0x40, 0x40, 0xB9, 0x02, 0x90, 0x40, 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0x02, 0x40, 0xF9, 0x00, 0xC0, 0x01, 0x91, 0xC1, 0x03, 0x00, 0xB4, 0xF3, 0x03, 0x01, 0xAA, + 0xF5, 0x13, 0x00, 0xF9, 0xF5, 0x03, 0x02, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x04, 0x00, 0x35, + 0x80, 0x02, 0x40, 0xF9, 0xE2, 0x03, 0x15, 0x2A, 0xE1, 0x03, 0x13, 0xAA, 0xE3, 0xD3, 0x00, 0x91, + 0x00, 0xA0, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, 0x13, 0x7C, 0x40, 0x93, + 0x20, 0xC0, 0x01, 0x91, 0x00, 0x00, 0x00, 0x94, 0xE0, 0x37, 0x40, 0xB9, 0x7F, 0x02, 0x00, 0x71, + 0xF5, 0x13, 0x40, 0xF9, 0x00, 0xA0, 0x93, 0x9A, 0x01, 0x41, 0x38, 0xD5, 0xE2, 0x1F, 0x40, 0xF9, + 0x23, 0xCC, 0x42, 0xF9, 0x42, 0x00, 0x03, 0xEB, 0x03, 0x00, 0x80, 0xD2, 0x81, 0x02, 0x00, 0x54, + 0xF3, 0x53, 0x41, 0xA9, 0xFD, 0x7B, 0xC4, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, + 0x00, 0x00, 0x00, 0x94, 0x80, 0x01, 0x00, 0x35, 0x81, 0x02, 0x40, 0xF9, 0x20, 0xC0, 0x01, 0x91, + 0x22, 0x28, 0x40, 0xB9, 0x22, 0x2C, 0x00, 0xB9, 0x00, 0x00, 0x00, 0x94, 0x81, 0x02, 0x40, 0xF9, + 0x22, 0x00, 0x80, 0x52, 0x00, 0x00, 0x80, 0xD2, 0x22, 0x18, 0x00, 0xB9, 0xEB, 0xFF, 0xFF, 0x17, + 0xF5, 0x13, 0x40, 0xF9, 0x60, 0x00, 0x80, 0x92, 0xE8, 0xFF, 0xFF, 0x17, 0xF5, 0x13, 0x00, 0xF9, + 0x00, 0x00, 0x00, 0x94, 0x04, 0x41, 0x38, 0xD5, 0x85, 0x2C, 0x40, 0xB9, 0xE3, 0x03, 0x00, 0xAA, + 0xE0, 0x03, 0x02, 0xAA, 0x45, 0x02, 0xA8, 0x36, 0x62, 0xDC, 0x40, 0x93, 0x62, 0x00, 0x02, 0x8A, + 0x04, 0x10, 0xC0, 0xD2, 0x84, 0x00, 0x00, 0xCB, 0x9F, 0x00, 0x02, 0xEB, 0x63, 0x01, 0x00, 0x54, + 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBF, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0x63, 0xF8, 0x48, 0x92, + 0xE2, 0x03, 0x00, 0xAA, 0xE0, 0x03, 0x03, 0xAA, 0x00, 0x00, 0x00, 0x94, 0xFD, 0x7B, 0xC1, 0xA8, + 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0xC0, 0x03, 0x5F, 0xD6, 0x84, 0x00, 0x40, 0xF9, + 0xE2, 0x03, 0x03, 0xAA, 0x9F, 0x00, 0x06, 0x72, 0xC0, 0xFD, 0xFF, 0x54, 0xEB, 0xFF, 0xFF, 0x17, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0x01, 0x24, 0x40, 0xF9, 0x21, 0x00, 0x40, 0xB9, 0xBF, 0x31, 0x03, 0xD5, 0xE2, 0x03, 0x01, 0x2A, 0x42, 0x00, 0x02, 0xCA, 0x02, 0x00, 0x00, 0xB5, 0x22, 0x04, 0x80, 0x12, 0x21, 0x00, 0x02, 0x0A, 0x02, 0x24, 0x40, 0xF9, @@ -200,7 +201,7 @@ uint8_t smi_stream_dev[] = { 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x00, 0xC0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x68, 0x40, 0xB9, 0x3F, 0x00, 0x13, 0x6B, 0xC0, 0x01, 0x00, 0x54, 0xF7, 0x1B, 0x00, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x79, 0xFD, 0xFF, 0x97, + 0x97, 0x02, 0x40, 0xF9, 0xE0, 0x06, 0x40, 0xF9, 0x00, 0x24, 0x40, 0xF9, 0x75, 0xFD, 0xFF, 0x97, 0x15, 0x00, 0x1E, 0x12, 0xC0, 0x01, 0x10, 0x36, 0xE0, 0xC2, 0x02, 0x91, 0x55, 0x01, 0x80, 0x12, 0x00, 0x00, 0x00, 0x94, 0xF7, 0x1B, 0x40, 0xF9, 0xDD, 0xFF, 0xFF, 0x17, 0x00, 0xC0, 0x02, 0x91, 0x00, 0x00, 0x00, 0x94, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, @@ -287,7 +288,7 @@ uint8_t smi_stream_dev[] = { 0xF5, 0x13, 0x00, 0xF9, 0x15, 0x00, 0x00, 0x90, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0xA0, 0x02, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x02, 0x40, 0xF9, 0x00, 0x04, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xE1, 0x03, 0x00, 0xAA, 0x82, 0x07, 0x80, 0xD2, - 0xE0, 0x03, 0x13, 0xAA, 0xFF, 0xFC, 0xFF, 0x97, 0x80, 0x09, 0x00, 0xB4, 0xA0, 0x02, 0x40, 0xF9, + 0xE0, 0x03, 0x13, 0xAA, 0x00, 0xFD, 0xFF, 0x97, 0x80, 0x09, 0x00, 0xB4, 0xA0, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x14, 0x00, 0x80, 0xD2, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0xF5, 0x13, 0x40, 0xF9, 0x2E, 0xFF, 0xFF, 0x17, 0x20, 0x00, 0x40, 0xF9, 0x1F, 0x00, 0x06, 0x72, 0xE1, 0xF9, 0xFF, 0x54, 0xE0, 0x03, 0x13, 0xAA, 0xCF, 0xFF, 0xFF, 0x17, @@ -295,7 +296,7 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x21, 0xFF, 0xFF, 0x17, 0x14, 0x00, 0x00, 0x90, 0x00, 0x01, 0xA0, 0xD2, 0xE0, 0x1B, 0x00, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x80, 0x02, 0x40, 0xF9, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0xE1, 0xC3, 0x00, 0x91, 0xE0, 0x03, 0x13, 0xAA, 0x02, 0x01, 0x80, 0xD2, 0xDD, 0xFC, 0xFF, 0x97, + 0xE1, 0xC3, 0x00, 0x91, 0xE0, 0x03, 0x13, 0xAA, 0x02, 0x01, 0x80, 0xD2, 0xDE, 0xFC, 0xFF, 0x97, 0x80, 0xF2, 0xFF, 0xB4, 0x80, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x14, 0x00, 0x80, 0xD2, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x0D, 0xFF, 0xFF, 0x17, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0x90, @@ -378,68 +379,68 @@ uint8_t smi_stream_dev[] = { 0xF9, 0x6B, 0x44, 0xA9, 0xFD, 0x7B, 0xCB, 0xA8, 0xBF, 0x23, 0x03, 0xD5, 0xC0, 0x03, 0x5F, 0xD6, 0x1F, 0x20, 0x03, 0xD5, 0x1F, 0x20, 0x03, 0xD5, 0x3F, 0x23, 0x03, 0xD5, 0xFD, 0x7B, 0xBB, 0xA9, 0xFD, 0x03, 0x00, 0x91, 0xF3, 0x53, 0x01, 0xA9, 0xF3, 0x03, 0x00, 0xAA, 0xF5, 0x5B, 0x02, 0xA9, - 0xF7, 0x63, 0x03, 0xA9, 0xF7, 0x03, 0x02, 0xAA, 0xF8, 0x03, 0x01, 0x2A, 0xF9, 0x23, 0x00, 0xF9, - 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, - 0x60, 0x06, 0x40, 0xF9, 0x21, 0x00, 0x80, 0x52, 0x61, 0x6A, 0x03, 0x39, 0x00, 0x00, 0x00, 0x94, - 0x61, 0x06, 0x40, 0xF9, 0xE0, 0x00, 0x00, 0x34, 0x20, 0x00, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, - 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x80, 0x12, 0xAF, 0x00, 0x00, 0x14, - 0x20, 0x24, 0x40, 0xF9, 0x00, 0x10, 0x00, 0x91, 0xBF, 0x32, 0x03, 0xD5, 0x1F, 0x00, 0x00, 0xB9, - 0x9F, 0x3F, 0x03, 0xD5, 0x60, 0x06, 0x40, 0xF9, 0x15, 0x00, 0x00, 0x90, 0x02, 0xC0, 0x02, 0x91, - 0x1F, 0x88, 0x0A, 0xA9, 0x02, 0x5C, 0x00, 0xF9, 0x60, 0x06, 0x40, 0xF9, 0x00, 0xE0, 0x05, 0x91, - 0x00, 0x00, 0x00, 0x94, 0xA0, 0x02, 0x40, 0xF9, 0x01, 0x00, 0x00, 0x90, 0x21, 0x00, 0x00, 0x91, - 0x76, 0x06, 0x40, 0xF9, 0x00, 0x00, 0x40, 0xF9, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0x90, - 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x94, 0xA0, 0x02, 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0x4E, 0x55, 0x00, 0x83, 0x60, 0xC2, 0xE5, 0x66, 0x77, 0xC1, 0x1C, + 0xC1, 0x86, 0x63, 0xA3, 0xEC, 0x00, 0x24, 0x78, 0x14, 0x9F, 0x97, 0xA1, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x4C, 0x69, 0x6E, 0x75, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x4C, 0x69, 0x6E, 0x75, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -916,6 +922,8 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x6D, 0x69, 0x5F, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6D, 0x5F, 0x64, 0x65, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1024,26 +1032,26 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x78, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, + 0xA0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 0x02, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x00, 0x02, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xD3, 0x05, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xD3, 0x05, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x94, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBF, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xD0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xD0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x90, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xED, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0x20, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0B, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x50, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0B, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x60, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x01, 0x00, 0x00, 0x02, 0x00, 0x07, 0x00, - 0xC8, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x28, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0xF4, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xCC, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x28, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x04, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x01, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, - 0x14, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x24, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x01, 0x00, 0x00, 0x01, 0x00, 0x0C, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1145,7 +1153,7 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x05, 0x00, 0x00, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x92, 0x05, 0x00, 0x00, 0x12, 0x00, 0x01, 0x00, - 0x70, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAB, 0x05, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB3, 0x05, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1161,9 +1169,9 @@ uint8_t smi_stream_dev[] = { 0x0D, 0x06, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2A, 0x06, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x38, 0x06, 0x00, 0x00, 0x12, 0x00, 0x01, 0x00, 0xB4, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x38, 0x06, 0x00, 0x00, 0x12, 0x00, 0x01, 0x00, 0xC4, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4D, 0x06, 0x00, 0x00, 0x12, 0x00, 0x07, 0x00, - 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x06, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x06, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1190,7 +1198,7 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x07, 0x00, 0x00, 0x11, 0x00, 0x0C, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB7, 0x07, 0x00, 0x00, 0x12, 0x00, 0x01, 0x00, - 0xC0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xD0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCC, 0x07, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0x07, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1364,858 +1372,865 @@ uint8_t smi_stream_dev[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x00, 0x00, 0x6F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x01, 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extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-03-14 - * Time: 23:08:06 + * Date: 2024-03-15 + * Time: 03:49:31 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 6, - .tm_min = 8, - .tm_hour = 23, - .tm_mday = 14, + .tm_sec = 31, + .tm_min = 49, + .tm_hour = 3, + .tm_mday = 15, .tm_mon = 2, /* +1 */ .tm_year = 124, /* +1900 */ }; @@ -38,384 +38,384 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -428,20 +428,20 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, 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0x9A, 0xD4, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x00, 0x18, 0x38, 0x00, 0x00, + 0x00, 0x0B, 0x05, 0x04, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xFE, 0x2D, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8D, 0x0D, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/software/libcariboulite/src/cariboulite_radio.c b/software/libcariboulite/src/cariboulite_radio.c index 6992478..03beb83 100644 --- a/software/libcariboulite/src/cariboulite_radio.c +++ b/software/libcariboulite/src/cariboulite_radio.c @@ -1134,7 +1134,7 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, { modem_iq_config.radio09_mode = at86rf215_baseband_mode; modem_iq_config.radio24_mode = at86rf215_iq_if_mode; - modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_2_906ns; + modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_4_906ns; smi_state = smi_stream_rx_channel_1; } @@ -1220,6 +1220,7 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, // apply the state caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_tx_channel); caribou_fpga_set_smi_ctrl_data_direction (&radio->sys->fpga, 0); + //cariboulite_radio_set_modem_state(radio, cariboulite_radio_state_cmd_tx); } }