bug fix spi + smi integration (firmware)

firmware/spi_slave.v

@@ -25,7 +25,7 @@ module spi_slave
 
   // Purpose: Recover SPI Byte in SPI Clock Domain
   // Samples line on correct edge of SPI Clock
-  /*always @(posedge i_spi_sck or posedge i_spi_cs_b)
+  always @(posedge i_spi_sck/* or posedge i_spi_cs_b*/)
   begin
     if (i_spi_cs_b) begin
       r_rx_bit_count <= 0;
@@ -42,8 +42,8 @@ module spi_slave
       end
     end
   end
-  */
-  always @(posedge i_sys_clk)
+  
+  /*always @(posedge i_sys_clk)
   begin
     if (i_spi_cs_b) begin
       r_rx_bit_count <= 0;
@@ -59,7 +59,7 @@ module spi_slave
         r_rx_done <= 1'b0;
       end
     end
-  end
+  end*/
 
   // Purpose: Cross from SPI Clock Domain to main FPGA clock domain
   // Assert o_rx_data_valid for 1 clock cycle when o_rx_byte has valid data.

firmware/top.v

@@ -159,12 +159,12 @@ module top(
    // CONBINATORIAL ASSIGNMENTS
    //=========================================================================
    //assign w_clock_spi = r_counter[0];
-   //assign w_clock_sys = r_counter[0];
+   assign w_clock_sys = r_counter;
 
-   SB_GB sys_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
+   /*SB_GB sys_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
                                     // a global high-fanout buffer
       .USER_SIGNAL_TO_GLOBAL_BUFFER (r_counter),
-      .GLOBAL_BUFFER_OUTPUT(w_clock_sys) );
+      .GLOBAL_BUFFER_OUTPUT(w_clock_sys) );*/
 
    //=========================================================================
    // CLOCK AND DATA-FLOW
@@ -172,15 +172,12 @@ module top(
    always @(posedge i_glob_clock)
    begin
       r_counter <= !r_counter;
-   end
 
-   always @(posedge w_clock_sys)
-   begin
       case (w_cs)
          4'b0001: r_tx_data <= w_tx_data_sys;
          4'b0010: r_tx_data <= w_tx_data_io;
          4'b0100: r_tx_data <= w_tx_data_smi;
-         4'b1000: r_tx_data <= 8'b10100101;  // reserved
+         4'b1000: r_tx_data <= 8'b10100101;  // 0xA5: reserved
          4'b0000: r_tx_data <= 8'b00000000;  // no module selected
       endcase
    end

software/libcariboulite/src/caribou_fpga/caribou_fpga.c

@@ -119,7 +119,7 @@ int caribou_fpga_init(caribou_fpga_st* dev, io_utils_spi_st* io_spi)
     ZF_LOGI("Initializing io_utils_spi");
     io_utils_hard_spi_st hard_dev_fpga = {  .spi_dev_id = dev->spi_dev,
                                             .spi_dev_channel = dev->spi_channel, };
-	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 4000000, 0, 0,
+	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 2000000, 0, 0,
                         						io_utils_spi_chip_type_fpga_comm,
                                                 &hard_dev_fpga);
 

software/libcariboulite/src/caribou_smi/test_caribou_smi.c

@@ -120,7 +120,7 @@ void print_iq(uint32_t* array, int len)
         if (i_val >= 0x1000) i_val-=0x2000;
         float fi = i_val, fq = q_val;
         float mod = sqrt(fi*fi + fq*fq);
-        float arg = atan(fq / fi);
+        float arg = atan2(fq, fi);
         printf("%d, %d, %d, %.4f, %.2f\n", cnt, i_val, q_val, mod, arg);
         last_cnt = cnt;
     }