smi driver experimenting

firmware/smi_ctrl.v

@@ -9,7 +9,7 @@ module smi_ctrl
         input               i_cs,
         input               i_fetch_cmd,
         input               i_load_cmd,
-        
+
         // FIFO INTERFACE 0.9 GHz
         output              o_fifo_09_pull,
         input [31:0]        i_fifo_09_pulled_data,
@@ -31,7 +31,8 @@ module smi_ctrl
         output              o_smi_read_req,
         output              o_smi_write_req,
         output              o_smi_writing,
-        
+        input               i_smi_test,
+
         // Errors
         output reg          o_address_error );
 
@@ -56,14 +57,14 @@ module smi_ctrl
         smi_address_read_res1 = 3'b100,
         smi_address_read_900 = 3'b101,
         smi_address_read_2400 = 3'b110,
-        smi_address_read_res = 3'b111;        
-    
+        smi_address_read_res = 3'b111;
+
     always @(posedge i_sys_clk)
     begin
         if (i_reset) begin
             o_address_error <= 1'b0;
             // put the initial states here
-        end else begin        
+        end else begin
             if (i_cs == 1'b1) begin
                 if (i_fetch_cmd == 1'b1) begin
                     case (i_ioc)
@@ -81,40 +82,53 @@ module smi_ctrl
 
                     endcase
                 end
-            end 
+            end
         end
     end
 
     // Tell the RPI that data is pending in either of the two fifos
-    assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty;
+    assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty || i_smi_test;
 
-    reg r_last_soe;
+    reg r_last_soe_1;
+    reg r_last_soe_2;
     reg [5:0] int_cnt_09;
     reg [5:0] int_cnt_24;
     reg r_fifo_09_pull;
     reg r_fifo_24_pull;
+    reg [7:0] r_smi_test_count_09;
+    reg [7:0] r_smi_test_count_24;
 
     always @(posedge i_sys_clk)
     begin
         if (i_reset) begin
             int_cnt_09 <= 6'd32;
             int_cnt_24 <= 6'd32;
-            r_last_soe <= 1'b1;
+            r_last_soe_1 <= 1'b1;
+            r_last_soe_2 <= 1'b1;
             r_fifo_09_pull <= 1'b0;
             r_fifo_24_pull <= 1'b0;
-        end else begin            
+            r_smi_test_count_09 <= 8'b00000000;
+            r_smi_test_count_24 <= 8'b00000000;
+        end else begin
             //==========================
             //  0.9 GHz Data Sender
             //==========================
             if (i_smi_a == smi_address_read_900) begin
-                if (r_last_soe != i_smi_soe_se) begin
+                if (r_last_soe_2 == 1'b0 && r_last_soe_1 == 1'b1) begin
+                    o_smi_data_out <= r_smi_test_count_09;
+                    r_smi_test_count_09 <= r_smi_test_count_09 + 1'b1;
+                end
+                /*if (r_last_soe != i_smi_soe_se) begin
                     if (int_cnt_09 > 8) int_cnt_09 <= int_cnt_09 - 8;
-                    if (r_fifo_09_pull) begin
+
+                    if (i_smi_test) begin
+                        r_smi_test_count_09 <= r_smi_test_count_09 + 1'b1;
+                        o_smi_data_out <= r_smi_test_count_09;
+                    end else if (r_fifo_09_pull) begin
                         r_fifo_09_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09-1:int_cnt_09-8];
                     end
-                end
-                else if (i_smi_soe_se == 1'b1) begin
+                end else if (i_smi_soe_se == 1'b1) begin
                     if (int_cnt_09 > 0) begin
                         r_fifo_09_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09-1:int_cnt_09-8];
@@ -122,20 +136,27 @@ module smi_ctrl
                         r_fifo_09_pull <=1'b1;
                         int_cnt_09 <= 6'd32;
                     end
-                end
+                end*/
             end
             //==========================
             //  2.4 GHz Data Sender
             //==========================
             else if (i_smi_a == smi_address_read_2400) begin
-                if (r_last_soe != i_smi_soe_se) begin
+                if (r_last_soe_2 == 1'b0 && i_smi_soe_se == 1'b1) begin
+                    o_smi_data_out <= r_smi_test_count_24;
+                    r_smi_test_count_24 <= r_smi_test_count_24 + 1'b1;
+                end
+                /*if (r_last_soe != i_smi_soe_se) begin
                     if (int_cnt_24 > 8) int_cnt_24 <= int_cnt_24 - 8;
-                    if (r_fifo_24_pull) begin
+
+                    if (i_smi_test) begin
+                        r_smi_test_count_24 <= r_smi_test_count_24 + 1'b1;
+                        o_smi_data_out <= r_smi_test_count_24;
+                    end else if (r_fifo_24_pull) begin
                         r_fifo_24_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24-1:int_cnt_24-8];
                     end
-                end
-                else if (i_smi_soe_se == 1'b1) begin
+                end else if (i_smi_soe_se == 1'b1) begin
                     if (int_cnt_24 > 0) begin
                         r_fifo_24_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24-1:int_cnt_24-8];
@@ -143,17 +164,20 @@ module smi_ctrl
                         r_fifo_24_pull <=1'b1;
                         int_cnt_24 <= 6'd32;
                     end
-                end
+                end*/
             end
             else begin
+                o_smi_data_out <= 8'b00000000;
                 // error with address
                 o_address_error <= 1'b1;
             end
 
-            r_last_soe <= i_smi_soe_se;
+            r_last_soe_2 <= r_last_soe_1;
+            r_last_soe_1 <= i_smi_soe_se;
         end
     end
 
+    //assign o_smi_data_out = 8'b01011010;
     assign o_fifo_09_pull = r_fifo_09_pull;
     assign o_fifo_24_pull = r_fifo_24_pull;
     assign o_smi_writing = i_smi_a[2];

firmware/top.v

@@ -296,7 +296,7 @@ module top(
    smi_ctrl smi_ctrl_ins
    (
       .i_reset (w_soft_reset),
-      .i_sys_clk (w_clock_sys),
+      .i_sys_clk (i_glob_clock),
       .i_ioc (w_ioc),
       .i_data_in (w_rx_data),
       .o_data_out (w_tx_data_smi),
@@ -322,6 +322,7 @@ module top(
       .o_smi_read_req (w_smi_read_req),
       .o_smi_write_req (w_smi_write_req),
       .o_smi_writing (w_smi_writing),
+      .i_smi_test (w_smi_test),
       .o_address_error ()
    );
 
@@ -331,14 +332,16 @@ module top(
    wire w_smi_read_req;
    wire w_smi_write_req;
    wire w_smi_writing;
+   wire w_smi_test;
 
+   //assign w_smi_data_output = 8'b10100101;
+   assign w_smi_test = 1'b1;
    assign w_smi_addr = {i_smi_a3, i_smi_a2, i_smi_a1};
    assign io_smi_data = (w_smi_writing)?w_smi_data_output:1'bZ;
    assign w_smi_data_input = io_smi_data;
    assign o_smi_write_req = (w_smi_writing)?w_smi_write_req:1'bZ;
    assign o_smi_read_req = (w_smi_writing)?w_smi_read_req:1'bZ;
 
-
    // Testing - output the clock signal (positive and negative) to the PMOD
    assign io_pmod[0] = (w_smi_writing)?w_smi_read_req:1'bZ;
    assign io_pmod[1] = (w_smi_writing)?w_smi_write_req:1'bZ;

software/kernel/test.c

@@ -8,7 +8,7 @@
 #include <sys/stat.h>
 #include <unistd.h>
 
-static void print_smi_settings(struct smi_settings *settings) 
+static void print_smi_settings(struct smi_settings *settings)
 {
   printf("width: %d\n", settings->data_width);
   printf("pack: %c\n", settings->pack_data ? 'Y' : 'N');
@@ -19,35 +19,65 @@ static void print_smi_settings(struct smi_settings *settings)
   printf("dma panic threshold read: %d, write: %d\n", settings->dma_panic_read_thresh, settings->dma_panic_write_thresh);
 }
 
-static void setup_settings (struct smi_settings *settings) 
+static void setup_settings (struct smi_settings *settings)
 {
   settings->read_setup_time = 1;
-  settings->read_strobe_time = 1;
+  settings->read_strobe_time = 3;
   settings->read_hold_time = 1;
-  settings->read_pace_time = 1;
+  settings->read_pace_time = 2;
   settings->write_setup_time = 1;
 	settings->write_hold_time = 1;
-	settings->write_pace_time = 1;
-	settings->write_strobe_time = 1;
+	settings->write_pace_time = 2;
+	settings->write_strobe_time = 3;
   settings->data_width = SMI_WIDTH_8BIT;
   settings->dma_enable = 1;
   settings->pack_data = 1;
   settings->dma_passthrough_enable = 1;
 }
 
-int main(int argc, char **argv) 
+void DumpHex(const void* data, size_t size)
+{
+	char ascii[17];
+	size_t i, j;
+	ascii[16] = '\0';
+	for (i = 0; i < size; ++i) {
+		printf("%02X ", ((unsigned char*)data)[i]);
+		if (((unsigned char*)data)[i] >= ' ' && ((unsigned char*)data)[i] <= '~') {
+			ascii[i % 16] = ((unsigned char*)data)[i];
+		} else {
+			ascii[i % 16] = '.';
+		}
+		if ((i+1) % 8 == 0 || i+1 == size) {
+			printf(" ");
+			if ((i+1) % 16 == 0) {
+				printf("|  %s \n", ascii);
+			} else if (i+1 == size) {
+				ascii[(i+1) % 16] = '\0';
+				if ((i+1) % 16 <= 8) {
+					printf(" ");
+				}
+				for (j = (i+1) % 16; j < 16; ++j) {
+					printf("   ");
+				}
+				printf("|  %s \n", ascii);
+			}
+		}
+	}
+}
+
+int main(int argc, char **argv)
 {
   int fd = open("/dev/smi", O_RDWR);
-  if (fd < 0) 
+  if (fd < 0)
   {
-    perror("cant open");
+    perror("can't open");
     exit(1);
   }
 
   struct smi_settings settings;
 
   int ret = ioctl(fd, BCM2835_SMI_IOC_GET_SETTINGS, &settings);
-  if (ret != 0) 
+  if (ret != 0)
   {
     perror("ioctl 1");
     close (fd);
@@ -60,13 +90,15 @@ int main(int argc, char **argv)
   setup_settings(&settings);
 
   ret = ioctl(fd, BCM2835_SMI_IOC_WRITE_SETTINGS, &settings);
-  if (ret != 0) 
+  if (ret != 0)
   {
     perror("ioctl 1");
     close (fd);
     exit(1);
   }
-  
+
+  ret = ioctl(fd, BCM2835_SMI_IOC_ADDRESS, (5<<1));
+
   printf("\n\nNEW settings:\n");
   print_smi_settings(&settings);
 
@@ -74,26 +106,47 @@ int main(int argc, char **argv)
   bool writeMode = false;
   //    writeMode = true;
 
-  int count = 512;
-  uint32_t buffer[512];   // 512 samples
-  if (writeMode) 
+  int count = 4096*32;
+  uint32_t buffer[count];
+  uint8_t* b8 = (uint8_t*)buffer;
+  if (writeMode)
   {
-    for (int i=0; i<count; i++) 
+    for (int i=0; i<count; i++)
     {
       buffer[i] = i;
     }
 
     write(fd, buffer, count*sizeof(uint32_t));
-  } 
-  else 
+  }
+  else
   {
-    read(fd, buffer, count*sizeof(uint32_t));
-    
-    printf("\n\nread words:\n");
-    for (int i=0; i<count; i++) 
+    int hist[256] = {0};
+    for (int j = 0; j < 1000; j++)
     {
-      printf("%02x ", buffer[i]);
+      read(fd, buffer, count*sizeof(uint32_t));
+
+      for (int i = 1; i<count*sizeof(uint32_t); i++)
+      {
+        hist[(uint8_t)(b8[i] - b8[i-1])] ++;
+      }
     }
+
+    printf("Histogram\n");
+    int error_bytes = 0;
+    int total_bytes = 0;
+    for (int i =0; i<256; i++)
+    {
+      if (hist[i]>0)
+      {
+        if (i != 1) error_bytes += hist[i];
+        total_bytes += hist[i];
+        printf("  %d: %d\n", i, hist[i]);
+      }
+    }
+    printf(" Byte Error Rate: %.10g, %d total, %d errors\n", (float)(error_bytes) / (float)(total_bytes), total_bytes, error_bytes);
+
+
+    //DumpHex(buffer, count*sizeof(uint32_t));
     puts("\n");
   }