# CaribouLite Hardware

## CaribouLite Hardware Revisions

CaribouLite board has two revisions:

1. Rev1: A prototyping revision (the red board).
2. Rev2: Production revision (currently R2.5 is the production-grade version).
   1. Rev2_r2.4: pre-production revision

This documentation shall cover the production-grade board (rev2).

## System Diagram

<table>
  <tr>
    <td><img src="https://github.com/cariboulabs/cariboulite_hw/blob/main/doc/system/system_view.png" alt="Top View"></td>
  </tr>
  <tr>
    <td>CaribouLite SDR System Diagram</td>
  </tr>
</table>

The **RF chart** in the 6GHz channel was inspired by the **RF front-end of HackRF-One by @greatscottgadgets** (an amazing ground breaking work still relevant today) with a few changes:
1. Usage of DPDTs instead of SPDTs in the filter-bank section. Usage of less switches in general.
2. Using higher attenuation stop-band filtering for a slightly better image rejection.
3. Mixer balun's according according to the requirements of the mixer IC.
4. LNA / PA slight improvements.

Possibilities exist to replace the 6GHz by a other types of components by Qorvo that are pin2pin compatible with the RFFC5072.

### Power Distribution

To simplify the board and its interfacing to the Raspberry Pi computer, all components on board operate with 3.3V. The FPGA further requires also 1.2V and 2.5V voltages. Two LDO components have been used to derive these voltages from the RPI 5V output voltage.

The usage of LDOs provides high level of voltage isolation, low emitted noise, and design simplicity. The downside of such choice it the dissipated heat from the LDOs. This heat is controlled by providing descent heat sinking to the board through the power planes and adjacent metallic elements (i.g. connectors).

The power distribution provides high frequency isolation of the RF components from the digital components (memory, RPI and FPGA) at frequencies lower than 10 MHz. Above 100 MHz additional isolation is provided by using ferrite beads with high impedance (>500 Ohms) at 100MHz. A set of filtering bypass capacitors have been chosen to further suppress noise generated by components on their power lines at mid-range frequencies (10 to 100 MHz) - the set contains 1nF, 100 nF and 4.7uF capacitors bypassing power and data lines effective at the said frequency ranges.

### RPI HAT EEPROM

An I2C EEPROM device is assembled on CaribouLite to support for the requirements of RPI HATs as described in [RPI HAT Requirements](https://github.com/raspberrypi/hats).
Production application helps to perform the EEPROM configuration process (coming soon)

### Clocking

The FPGA is externally clocked by a crystal oscillator of 125MHz located in the bottom side of the board.
Clocking the FPGA from the RPI GPCLK (GPIO4 / GPCLK0 / SMI_SA1) is also possible but not recommanded as it may cause substantial increase in the board EMI. For that reason, the GPCLK option is possible but not used in the mainline hardware version. Hacking the possibility to clock from the RPI is a good idea though.

The MODEM (AT86RF215) is clocked from a 26MHz TCXO (bottom layer). This device provides a stable and low phase noise clock reference to the receivers and transmitters within the IC. The MODEM further outputs a buffered version of the input clock (typically 26MHz, but other possibilities exist as well), to the MIXER input. A capacitor divider circuit adapts the LVCMOS output from the MODEM to the input levels of the MIXER.

The MIXER can also be clocked from a separate dedicated TCXO (not assembled), or an external coherent clock source.
<table>
  <tr>
    <td><img src="https://github.com/cariboulabs/cariboulite_hw/blob/main/doc/system/instructions_clocking_mixer.png" alt="Top View" height=200></td>
  </tr>
  <tr>
    <td>MIXER clocking options, other than the default MODEM provided reference clock</td>
  </tr>
</table>
To enable the above clocking schemes, the MODEM clock input jumper should be cut, and the appropriate jumpers need to be shorted. Consult the schematics to learn more.

### PMOD Connector

Coming soon:

* Synchronization
* GPS PPS Signaling
* Peripherals
* Maximal current

### FPGA and LVDS

Coming soon - LVDS calculations

### Calibrations & Testing

Coming soon

## License

<a rel="license" href="http://creativecommons.org/licenses/by/4.0/"><img alt="Creative Commons License" style="border-width:0" src="https://i.creativecommons.org/l/by/4.0/88x31.png" /></a><br />This work is licensed under a <a rel="license" href="http://creativecommons.org/licenses/by/4.0/">Creative Commons Attribution 4.0 International License</a>.
