141 wiersze
3.7 KiB
C
141 wiersze
3.7 KiB
C
/**
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@Company
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Microchip Technology Inc.
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@Description
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This Source file provides APIs.
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Generation Information :
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Driver Version : 1.0.0
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*/
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/*
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(c) 2018 Microchip Technology Inc. and its subsidiaries.
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Subject to your compliance with these terms, you may use Microchip software and any
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derivatives exclusively with Microchip products. It is your responsibility to comply with third party
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license terms applicable to your use of third party software (including open source software) that
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may accompany Microchip software.
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THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY
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IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS
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FOR A PARTICULAR PURPOSE.
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IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP
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HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO
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THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT
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OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS
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SOFTWARE.
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*/
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#include "../include/ccl.h"
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int8_t CCL_Initialize()
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{
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//INTMODE3 INTDISABLE; INTMODE2 INTDISABLE; INTMODE1 INTDISABLE; INTMODE0 INTDISABLE;
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CCL.INTCTRL0 = 0x00;
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//INTMODE5 INTDISABLE; INTMODE4 INTDISABLE;
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CCL.INTCTRL1 = 0x00;
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//INT5 disabled; INT4 disabled; INT3 disabled; INT2 disabled; INT1 disabled; INT0 disabled;
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CCL.INTFLAGS = 0x00;
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//INSEL1 SPI0; INSEL0 TCA0;
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CCL.LUT0CTRLB = 0x9A;
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//INSEL2 TCA0;
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CCL.LUT0CTRLC = 0x0A;
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//INSEL1 MASK; INSEL0 MASK;
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CCL.LUT1CTRLB = 0x00;
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//INSEL2 MASK;
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CCL.LUT1CTRLC = 0x00;
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//INSEL1 MASK; INSEL0 MASK;
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CCL.LUT2CTRLB = 0x00;
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//INSEL2 MASK;
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CCL.LUT2CTRLC = 0x00;
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//INSEL1 MASK; INSEL0 MASK;
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CCL.LUT3CTRLB = 0x00;
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//INSEL2 MASK;
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CCL.LUT3CTRLC = 0x00;
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//INSEL1 MASK; INSEL0 MASK;
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CCL.LUT4CTRLB = 0x00;
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//INSEL2 MASK;
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CCL.LUT4CTRLC = 0x00;
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//INSEL1 MASK; INSEL0 MASK;
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CCL.LUT5CTRLB = 0x00;
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//INSEL2 MASK;
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CCL.LUT5CTRLC = 0x00;
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//SEQSEL0 DISABLE;
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CCL.SEQCTRL0 = 0x00;
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//SEQSEL1 DISABLE;
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CCL.SEQCTRL1 = 0x00;
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//SEQSEL2 DISABLE;
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CCL.SEQCTRL2 = 0x00;
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//
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CCL.TRUTH0 = 0xE0;
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//
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CCL.TRUTH1 = 0x00;
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//
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CCL.TRUTH2 = 0x00;
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//
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CCL.TRUTH3 = 0x00;
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//
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CCL.TRUTH4 = 0x00;
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//
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CCL.TRUTH5 = 0x00;
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//EDGEDET DIS; OUTEN enabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE enabled;
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CCL.LUT0CTRLA = 0x41;
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//EDGEDET DIS; OUTEN disabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE disabled;
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CCL.LUT1CTRLA = 0x00;
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//EDGEDET DIS; OUTEN disabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE disabled;
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CCL.LUT2CTRLA = 0x00;
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//EDGEDET DIS; OUTEN disabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE disabled;
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CCL.LUT3CTRLA = 0x00;
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//EDGEDET DIS; OUTEN disabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE disabled;
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CCL.LUT4CTRLA = 0x00;
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//EDGEDET DIS; OUTEN disabled; FILTSEL DISABLE; CLKSRC CLKPER; ENABLE disabled;
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CCL.LUT5CTRLA = 0x00;
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//RUNSTDBY disabled; ENABLE enabled;
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CCL.CTRLA = 0x01;
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return 0;
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}
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ISR(CCL_CCL_vect)
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{
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/*
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* Insert your CCL interrupt handling code
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*
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* Interrupt flag can be cleared by writing 1 to its bit location
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* in the INTFLAGS register
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*/
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} |