kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
220 wiersze
12 KiB
Bash
220 wiersze
12 KiB
Bash
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# (C) 2001-2021 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 18.1 625 win32 2021.02.12.17:11:14
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# ----------------------------------------
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# ncsim - auto-generated simulation script
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# ----------------------------------------
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# This script provides commands to simulate the following IP detected in
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# your Quartus project:
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# rx_ciccomp
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#
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# Altera recommends that you source this Quartus-generated IP simulation
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# script from your own customized top-level script, and avoid editing this
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# generated script.
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#
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# To write a top-level shell script that compiles Altera simulation libraries
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# and the Quartus-generated IP in your project, along with your design and
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# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
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# into a new file, e.g. named "ncsim.sh", and modify text as directed.
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#
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# You can also modify the simulation flow to suit your needs. Set the
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# following variables to 1 to disable their corresponding processes:
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# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
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# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
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# - SKIP_COM: skip compiling Quartus-generated IP simulation files
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# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
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#
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# ----------------------------------------
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# # TOP-LEVEL TEMPLATE - BEGIN
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# #
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# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
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# # construct paths to the files required to simulate the IP in your Quartus
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# # project. By default, the IP script assumes that you are launching the
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# # simulator from the IP script location. If launching from another
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# # location, set QSYS_SIMDIR to the output directory you specified when you
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# # generated the IP script, relative to the directory from which you launch
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# # the simulator. In this case, you must also copy the generated files
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# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
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# # into the location from which you launch the simulator, or incorporate
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# # into any existing library setup.
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# #
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# # Run Quartus-generated IP simulation script once to compile Quartus EDA
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# # simulation libraries and Quartus-generated IP simulation files, and copy
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# # any ROM/RAM initialization files to the simulation directory.
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# # - If necessary, specify any compilation options:
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# # USER_DEFINED_COMPILE_OPTIONS
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# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
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# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
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# #
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# source <script generation output directory>/cadence/ncsim_setup.sh \
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# SKIP_ELAB=1 \
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# SKIP_SIM=1 \
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# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
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# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
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# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
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# QSYS_SIMDIR=<script generation output directory>
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# #
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# # Compile all design files and testbench files, including the top level.
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# # (These are all the files required for simulation other than the files
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# # compiled by the IP script)
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# #
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# ncvlog <compilation options> <design and testbench files>
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# #
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# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
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# # testbench module/entity name.
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# #
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# # Run the IP script again to elaborate and simulate the top level:
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# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
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# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
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# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
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# #
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# source <script generation output directory>/cadence/ncsim_setup.sh \
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# SKIP_FILE_COPY=1 \
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# SKIP_DEV_COM=1 \
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# SKIP_COM=1 \
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# TOP_LEVEL_NAME=<simulation top> \
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# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
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# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
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# #
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# # TOP-LEVEL TEMPLATE - END
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# ----------------------------------------
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#
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# IP SIMULATION SCRIPT
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# ----------------------------------------
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# If rx_ciccomp is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Altera IP
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# within the Quartus project, and generate a unified
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# script which supports all the Altera IP within the design.
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# ----------------------------------------
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# ACDS 18.1 625 win32 2021.02.12.17:11:14
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# ----------------------------------------
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# initialize variables
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TOP_LEVEL_NAME="rx_ciccomp"
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QSYS_SIMDIR="./../"
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QUARTUS_INSTALL_DIR="C:/intelfpga/18.1/quartus/"
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SKIP_FILE_COPY=0
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SKIP_DEV_COM=0
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SKIP_COM=0
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SKIP_ELAB=0
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SKIP_SIM=0
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USER_DEFINED_ELAB_OPTIONS=""
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USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
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# ----------------------------------------
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# overwrite variables - DO NOT MODIFY!
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# This block evaluates each command line argument, typically used for
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# overwriting variables. An example usage:
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# sh <simulator>_setup.sh SKIP_SIM=1
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for expression in "$@"; do
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eval $expression
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if [ $? -ne 0 ]; then
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echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
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exit $?
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fi
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done
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# ----------------------------------------
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# initialize simulation properties - DO NOT MODIFY!
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ELAB_OPTIONS=""
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SIM_OPTIONS=""
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if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
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:
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else
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:
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fi
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# ----------------------------------------
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# create compilation libraries
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mkdir -p ./libraries/work/
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mkdir -p ./libraries/altera_ver/
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mkdir -p ./libraries/lpm_ver/
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mkdir -p ./libraries/sgate_ver/
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mkdir -p ./libraries/altera_mf_ver/
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mkdir -p ./libraries/cycloneive_ver/
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mkdir -p ./libraries/altera/
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mkdir -p ./libraries/lpm/
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mkdir -p ./libraries/sgate/
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mkdir -p ./libraries/altera_mf/
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mkdir -p ./libraries/altera_lnsim/
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mkdir -p ./libraries/cycloneive/
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# ----------------------------------------
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# copy RAM/ROM files to simulation directory
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# ----------------------------------------
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# compile device library files
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if [ $SKIP_DEV_COM -eq 0 ]; then
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
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ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.vhd" -work cycloneive
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_components.vhd" -work cycloneive
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fi
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# ----------------------------------------
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# compile design files in correct order
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if [ $SKIP_COM -eq 0 ]; then
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
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ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_rtl_core.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_ast.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp.vhd"
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ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_tb.vhd"
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fi
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# ----------------------------------------
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# elaborate top level design
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if [ $SKIP_ELAB -eq 0 ]; then
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export GENERIC_PARAM_COMPAT_CHECK=1
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ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
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fi
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# ----------------------------------------
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# simulate
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if [ $SKIP_SIM -eq 0 ]; then
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eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
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fi
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