kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
309 wiersze
16 KiB
Tcl
309 wiersze
16 KiB
Tcl
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# (C) 2001-2021 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 18.1 625 win32 2021.02.12.17:11:14
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# ----------------------------------------
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# Auto-generated simulation script rivierapro_setup.tcl
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# ----------------------------------------
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# This script provides commands to simulate the following IP detected in
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# your Quartus project:
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# rx_ciccomp
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#
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# Altera recommends that you source this Quartus-generated IP simulation
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# script from your own customized top-level script, and avoid editing this
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# generated script.
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#
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# To write a top-level script that compiles Altera simulation libraries and
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# the Quartus-generated IP in your project, along with your design and
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# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
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# into a new file, e.g. named "aldec.do", and modify the text as directed.
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#
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# ----------------------------------------
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# # TOP-LEVEL TEMPLATE - BEGIN
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# #
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# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
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# # construct paths to the files required to simulate the IP in your Quartus
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# # project. By default, the IP script assumes that you are launching the
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# # simulator from the IP script location. If launching from another
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# # location, set QSYS_SIMDIR to the output directory you specified when you
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# # generated the IP script, relative to the directory from which you launch
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# # the simulator.
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# #
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# set QSYS_SIMDIR <script generation output directory>
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# #
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# # Source the generated IP simulation script.
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# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
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# #
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# # Set any compilation options you require (this is unusual).
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# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
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# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
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# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
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# #
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# # Call command to compile the Quartus EDA simulation library.
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# dev_com
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# #
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# # Call command to compile the Quartus-generated IP simulation files.
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# com
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# #
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# # Add commands to compile all design files and testbench files, including
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# # the top level. (These are all the files required for simulation other
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# # than the files compiled by the Quartus-generated IP simulation script)
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# #
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# vlog -sv2k5 <your compilation options> <design and testbench files>
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# #
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# # Set the top-level simulation or testbench module/entity name, which is
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# # used by the elab command to elaborate the top level.
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# #
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# set TOP_LEVEL_NAME <simulation top>
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# #
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# # Set any elaboration options you require.
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# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
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# #
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# # Call command to elaborate your design and testbench.
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# elab
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# #
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# # Run the simulation.
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# run
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# #
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# # Report success to the shell.
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# exit -code 0
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# #
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# # TOP-LEVEL TEMPLATE - END
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# ----------------------------------------
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#
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# IP SIMULATION SCRIPT
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# ----------------------------------------
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# If rx_ciccomp is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Altera IP
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# within the Quartus project, and generate a unified
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# script which supports all the Altera IP within the design.
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# ----------------------------------------
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# ----------------------------------------
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# Initialize variables
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if ![info exists SYSTEM_INSTANCE_NAME] {
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set SYSTEM_INSTANCE_NAME ""
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} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
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set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
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}
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if ![info exists TOP_LEVEL_NAME] {
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set TOP_LEVEL_NAME "rx_ciccomp"
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}
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if ![info exists QSYS_SIMDIR] {
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set QSYS_SIMDIR "./../"
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}
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if ![info exists QUARTUS_INSTALL_DIR] {
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set QUARTUS_INSTALL_DIR "C:/intelfpga/18.1/quartus/"
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}
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if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
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set USER_DEFINED_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
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set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
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set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_ELAB_OPTIONS] {
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set USER_DEFINED_ELAB_OPTIONS ""
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}
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# ----------------------------------------
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# Initialize simulation properties - DO NOT MODIFY!
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set ELAB_OPTIONS ""
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set SIM_OPTIONS ""
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if ![ string match "*-64 vsim*" [ vsim -version ] ] {
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} else {
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}
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set Aldec "Riviera"
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if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
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set Aldec "Active"
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}
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if { [ string match "Active" $Aldec ] } {
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scripterconf -tcl
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createdesign "$TOP_LEVEL_NAME" "."
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opendesign "$TOP_LEVEL_NAME"
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}
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# ----------------------------------------
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# Copy ROM/RAM files to simulation directory
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alias file_copy {
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echo "\[exec\] file_copy"
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}
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# ----------------------------------------
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# Create compilation libraries
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proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
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ensure_lib ./libraries
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ensure_lib ./libraries/work
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vmap work ./libraries/work
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ensure_lib ./libraries/altera_ver
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vmap altera_ver ./libraries/altera_ver
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ensure_lib ./libraries/lpm_ver
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vmap lpm_ver ./libraries/lpm_ver
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ensure_lib ./libraries/sgate_ver
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vmap sgate_ver ./libraries/sgate_ver
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ensure_lib ./libraries/altera_mf_ver
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vmap altera_mf_ver ./libraries/altera_mf_ver
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ensure_lib ./libraries/altera_lnsim_ver
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vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
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ensure_lib ./libraries/cycloneive_ver
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vmap cycloneive_ver ./libraries/cycloneive_ver
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ensure_lib ./libraries/altera
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vmap altera ./libraries/altera
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ensure_lib ./libraries/lpm
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vmap lpm ./libraries/lpm
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ensure_lib ./libraries/sgate
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vmap sgate ./libraries/sgate
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ensure_lib ./libraries/altera_mf
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vmap altera_mf ./libraries/altera_mf
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ensure_lib ./libraries/altera_lnsim
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vmap altera_lnsim ./libraries/altera_lnsim
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ensure_lib ./libraries/cycloneive
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vmap cycloneive ./libraries/cycloneive
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# ----------------------------------------
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# Compile device library files
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alias dev_com {
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echo "\[exec\] dev_com"
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eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
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vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
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vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
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vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
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vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
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vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
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vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.vhd" -work cycloneive
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vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_components.vhd" -work cycloneive
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}
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# ----------------------------------------
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# Compile the design files in correct order
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alias com {
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echo "\[exec\] com"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
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eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_rtl_core.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_ast.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp.vhd"
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eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rx_ciccomp_tb.vhd"
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}
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# ----------------------------------------
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# Elaborate top level design
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alias elab {
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echo "\[exec\] elab"
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eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Elaborate the top level design with -dbg -O2 option
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alias elab_debug {
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echo "\[exec\] elab_debug"
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eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design
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alias ld "
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dev_com
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com
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elab
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"
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design with -dbg -O2
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alias ld_debug "
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dev_com
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com
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elab_debug
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"
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# ----------------------------------------
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# Print out user commmand line aliases
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alias h {
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echo "List Of Command Line Aliases"
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echo
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echo "file_copy -- Copy ROM/RAM files to simulation directory"
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echo
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echo "dev_com -- Compile device library files"
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echo
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echo "com -- Compile the design files in correct order"
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echo
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echo "elab -- Elaborate top level design"
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echo
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echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
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echo
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echo "ld -- Compile all the design files and elaborate the top level design"
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echo
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echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
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echo
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echo
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echo
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echo "List Of Variables"
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echo
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echo "TOP_LEVEL_NAME -- Top level module name."
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echo " For most designs, this should be overridden"
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echo " to enable the elab/elab_debug aliases."
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echo
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echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
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echo
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echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
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echo
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echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
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echo
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echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
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echo
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echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
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echo
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echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
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echo
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echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
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}
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file_copy
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h
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