kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
6913 wiersze
1.5 MiB
6913 wiersze
1.5 MiB
Analysis & Synthesis report for WOLF-LITE
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Thu Jan 07 18:19:59 2021
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Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
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; Table of Contents ;
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis IP Cores Summary
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7. Partition Status Summary
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8. Dependent File Changes for Partition Top
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9. Partition for Top-Level Resource Utilization by Entity
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10. State Machine - |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state
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11. State Machine - |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state
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12. State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state
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13. State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state
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14. Registers Protected by Synthesis
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15. Registers Removed During Synthesis
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16. Removed Registers Triggering Further Register Optimizations
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17. Multiplexer Restructuring Statistics (No Restructuring Performed)
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18. Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst
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19. Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core
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20. Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated
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21. Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst
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22. Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core
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23. Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated
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24. Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst
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25. Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core
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26. Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated
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27. Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst
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28. Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core
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29. Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated
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30. Source assignments for DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst
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31. Parameter Settings for User Entity Instance: tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component
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32. Parameter Settings for User Entity Instance: tx_pll:TX_PLL|altpll:altpll_component
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33. Parameter Settings for User Entity Instance: tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component
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34. Parameter Settings for User Entity Instance: tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0
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35. Parameter Settings for User Entity Instance: data_shifter:TX_CICCOMP_GAINER
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36. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst
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37. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink
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38. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source
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39. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread
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40. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute
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41. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14
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42. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15
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43. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13
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44. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13
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45. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem
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46. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component
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47. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16
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48. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16
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49. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16
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50. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17
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51. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk
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52. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst
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53. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink
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54. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source
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55. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread
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56. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute
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57. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14
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58. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15
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59. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13
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60. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13
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61. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem
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62. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component
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63. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16
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64. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16
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65. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16
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66. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17
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67. Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk
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68. Parameter Settings for User Entity Instance: tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0
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69. Parameter Settings for User Entity Instance: tx_mixer:TX_MIXER_Q|lpm_mult:lpm_mult_component
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70. Parameter Settings for User Entity Instance: tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0
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71. Parameter Settings for User Entity Instance: data_shifter:RX_CICFIR_GAINER
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72. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst
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73. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink
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74. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source
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75. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread
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76. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute
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77. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14
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78. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15
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79. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13
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80. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13
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81. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem
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82. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component
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83. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk
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84. Parameter Settings for User Entity Instance: data_shifter:CIC_GAINER
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85. Parameter Settings for User Entity Instance: rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0
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86. Parameter Settings for User Entity Instance: nco:RX_NCO|nco_nco_ii_0:nco_ii_0
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87. Parameter Settings for User Entity Instance: mixer:RX_MIXER_I|lpm_mult:lpm_mult_component
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88. Parameter Settings for User Entity Instance: rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0
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89. Parameter Settings for User Entity Instance: mixer:RX_MIXER_Q|lpm_mult:lpm_mult_component
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90. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst
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91. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink
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92. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source
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93. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread
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94. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute
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95. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14
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96. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15
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97. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13
|
|
98. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13
|
|
99. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem
|
|
100. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component
|
|
101. Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk
|
|
102. Parameter Settings for User Entity Instance: MAIN_PLL:MAIN_PLL|altpll:altpll_component
|
|
103. Parameter Settings for User Entity Instance: mux14:DAC_MUX|lpm_mux:LPM_MUX_component
|
|
104. Parameter Settings for User Entity Instance: dac_null:DAC_IDLE|lpm_constant:LPM_CONSTANT_component
|
|
105. Parameter Settings for User Entity Instance: DAC_corrector:DAC_CORRECTOR
|
|
106. Parameter Settings for User Entity Instance: DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0
|
|
107. Parameter Settings for User Entity Instance: DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl
|
|
108. Partition Dependent Files
|
|
109. Post-Synthesis Netlist Statistics for Top Partition
|
|
110. Partition "sld_hub:auto_hub" Resource Utilization by Entity
|
|
111. Multiplexer Restructuring Statistics (No Restructuring Performed)
|
|
112. Post-Synthesis Netlist Statistics for Partition sld_hub:auto_hub
|
|
113. Port Connectivity Checks: "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl"
|
|
114. Port Connectivity Checks: "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0"
|
|
115. Port Connectivity Checks: "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core"
|
|
116. Port Connectivity Checks: "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core"
|
|
117. Port Connectivity Checks: "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0"
|
|
118. Port Connectivity Checks: "clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component"
|
|
119. Elapsed Time Per Partition
|
|
120. Analysis & Synthesis Messages
|
|
121. Analysis & Synthesis Suppressed Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
Your use of Intel Corporation's design tools, logic functions
|
|
and other software and tools, and its AMPP partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Intel Program License
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
|
agreement, including, without limitation, that your use is for
|
|
the sole purpose of programming logic devices manufactured by
|
|
Intel and sold by Intel or its authorized distributors. Please
|
|
refer to the applicable agreement for further details.
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Summary ;
|
|
+------------------------------------+-------------------------------------------------+
|
|
; Analysis & Synthesis Status ; Successful - Thu Jan 07 18:19:59 2021 ;
|
|
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ;
|
|
; Revision Name ; WOLF-LITE ;
|
|
; Top-level Entity Name ; WOLF-LITE ;
|
|
; Family ; Cyclone IV E ;
|
|
; Total logic elements ; N/A until Partition Merge ;
|
|
; Total combinational functions ; N/A until Partition Merge ;
|
|
; Dedicated logic registers ; N/A until Partition Merge ;
|
|
; Total registers ; N/A until Partition Merge ;
|
|
; Total pins ; N/A until Partition Merge ;
|
|
; Total virtual pins ; N/A until Partition Merge ;
|
|
; Total memory bits ; N/A until Partition Merge ;
|
|
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
|
|
; Total PLLs ; N/A until Partition Merge ;
|
|
+------------------------------------+-------------------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Settings ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
; Option ; Setting ; Default Value ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
; Device ; EP4CE10E22C8 ; ;
|
|
; Top-level entity name ; WOLF-LITE ; WOLF-LITE ;
|
|
; Family name ; Cyclone IV E ; Cyclone V ;
|
|
; Use smart compilation ; On ; Off ;
|
|
; Maximum processors allowed for parallel compilation ; All ; ;
|
|
; Restructure Multiplexers ; Off ; Auto ;
|
|
; Preserve fewer node names ; Off ; On ;
|
|
; Intel FPGA IP Evaluation Mode ; Disable ; Enable ;
|
|
; Optimization Technique ; Speed ; Balanced ;
|
|
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
|
|
; Auto RAM to Logic Cell Conversion ; On ; Off ;
|
|
; Auto Gated Clock Conversion ; On ; Off ;
|
|
; Pre-Mapping Resynthesis Optimization ; On ; Off ;
|
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
|
; Enable compact report table ; Off ; Off ;
|
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
|
; State Machine Processing ; Auto ; Auto ;
|
|
; Safe State Machine ; Off ; Off ;
|
|
; Extract Verilog State Machines ; On ; On ;
|
|
; Extract VHDL State Machines ; On ; On ;
|
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
|
; Infer RAMs from Raw Logic ; On ; On ;
|
|
; Parallel Synthesis ; On ; On ;
|
|
; DSP Block Balancing ; Auto ; Auto ;
|
|
; NOT Gate Push-Back ; On ; On ;
|
|
; Power-Up Don't Care ; On ; On ;
|
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
|
; Remove Duplicate Registers ; On ; On ;
|
|
; Ignore CARRY Buffers ; Off ; Off ;
|
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore LCELL Buffers ; Off ; Off ;
|
|
; Ignore SOFT Buffers ; On ; On ;
|
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
|
; Carry Chain Length ; 70 ; 70 ;
|
|
; Auto Carry Chains ; On ; On ;
|
|
; Auto Open-Drain Pins ; On ; On ;
|
|
; Auto ROM Replacement ; On ; On ;
|
|
; Auto RAM Replacement ; On ; On ;
|
|
; Auto DSP Block Replacement ; On ; On ;
|
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
|
; Auto Clock Enable Replacement ; On ; On ;
|
|
; Strict RAM Replacement ; Off ; Off ;
|
|
; Allow Synchronous Control Signals ; On ; On ;
|
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
|
; Auto RAM Block Balancing ; On ; On ;
|
|
; Auto Resource Sharing ; Off ; Off ;
|
|
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
|
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
|
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
|
; Timing-Driven Synthesis ; On ; On ;
|
|
; Report Parameter Settings ; On ; On ;
|
|
; Report Source Assignments ; On ; On ;
|
|
; Report Connectivity Checks ; On ; On ;
|
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
|
; HDL message level ; Level2 ; Level2 ;
|
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Clock MUX Protection ; On ; On ;
|
|
; Block Design Naming ; Auto ; Auto ;
|
|
; SDC constraint protection ; Off ; Off ;
|
|
; Synthesis Effort ; Auto ; Auto ;
|
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
|
; Resource Aware Inference For Block RAM ; On ; On ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
|
|
|
|
+------------------------------------------+
|
|
; Parallel Compilation ;
|
|
+----------------------------+-------------+
|
|
; Processors ; Number ;
|
|
+----------------------------+-------------+
|
|
; Number detected on machine ; 8 ;
|
|
; Maximum allowed ; 4 ;
|
|
; ; ;
|
|
; Average used ; 1.00 ;
|
|
; Maximum used ; 4 ;
|
|
; ; ;
|
|
; Usage by Processor ; % Time Used ;
|
|
; Processor 1 ; 100.0% ;
|
|
; Processor 2 ; 0.1% ;
|
|
; Processor 3 ; 0.1% ;
|
|
; Processor 4 ; 0.1% ;
|
|
+----------------------------+-------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Source Files Read ;
|
|
+--------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+
|
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
|
+--------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+
|
|
; WOLF-LITE.bdf ; yes ; User Block Diagram/Schematic File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/WOLF-LITE.bdf ; ;
|
|
; DAC_corrector.v ; yes ; User Verilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/DAC_corrector.v ; ;
|
|
; spi_interface.v ; yes ; User Verilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/spi_interface.v ; ;
|
|
; stm32_interface.v ; yes ; User Verilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/stm32_interface.v ; ;
|
|
; data_shifter.v ; yes ; User Verilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v ; ;
|
|
; mixer.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mixer.v ; ;
|
|
; MAIN_PLL.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/MAIN_PLL.v ; ;
|
|
; mux14.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux14.v ; ;
|
|
; tx_mixer.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_mixer.v ; ;
|
|
; tx_summator.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_summator.v ; ;
|
|
; dac_null.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dac_null.v ; ;
|
|
; rx_ciccomp.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp.v ; rx_ciccomp ;
|
|
; rx_ciccomp/dspba_library_package.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library_package.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/dspba_library.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/altera_avalon_sc_fifo.v ; yes ; User Verilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/altera_avalon_sc_fifo.v ; rx_ciccomp ;
|
|
; rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/rx_ciccomp_0002_ast.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd ; rx_ciccomp ;
|
|
; rx_ciccomp/rx_ciccomp_0002.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd ; rx_ciccomp ;
|
|
; tx_ciccomp.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp.v ; tx_ciccomp ;
|
|
; tx_ciccomp/dspba_library_package.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library_package.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/dspba_library.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/tx_ciccomp_0002_ast.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd ; tx_ciccomp ;
|
|
; tx_ciccomp/tx_ciccomp_0002.vhd ; yes ; User VHDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd ; tx_ciccomp ;
|
|
; tx_pll.v ; yes ; User Wizard-Generated File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_pll.v ; ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/clock_buffer/clock_buffer.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/clock_buffer/clock_buffer.v ; clock_buffer ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v ; clock_buffer ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/rx_cic.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/rx_cic.v ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_cic_core.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_cic_core.sv ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_delay.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_delay.vhd ; rx_cic ;
|
|
; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_downsample.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_downsample.sv ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/counter_module.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/counter_module.sv ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv ; yes ; Auto-Found SystemVerilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv ; rx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_cic_core.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_cic_core.sv ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_cic_int_siso.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_cic_int_siso.sv ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_delay.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_delay.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd ; yes ; Auto-Found VHDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/counter_module.sv ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/counter_module.sv ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv ; yes ; Auto-Found SystemVerilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/tx_cic.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_cic/tx_cic.v ; tx_cic ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_altqmcpipe.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_altqmcpipe.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_gam_dp.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_gam_dp.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_derot.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_derot.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_isdr.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_isdr.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_madx_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_madx_cen.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_mady_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_mady_cen.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_mob_w.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/asj_nco_mob_w.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_cos_f.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_cos_f.hex ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_sin_c.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_sin_c.hex ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_sin_f.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_sin_f.hex ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/tx_nco.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/tx_nco/tx_nco.v ; tx_nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/nco.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/nco.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_altqmcpipe.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_altqmcpipe.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_gam_dp.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_gam_dp.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_as_m_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_as_m_cen.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_derot.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_derot.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_isdr.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_isdr.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_madx_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_madx_cen.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_mady_cen.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_mady_cen.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_mob_w.v ; yes ; Encrypted Altera IP File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/asj_nco_mob_w.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0.v ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_cos_f.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_cos_f.hex ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_sin_c.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_sin_c.hex ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_sin_f.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/nco/submodules/nco_nco_ii_0_sin_f.hex ; nco ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/debug/debug.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/debug/debug.v ; DEBUG ;
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; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/debug/submodules/altsource_probe_top.v ; yes ; Auto-Found Verilog HDL File ; d:/dropbox/develop/projects/wolf-lite/fpga/db/ip/debug/submodules/altsource_probe_top.v ; DEBUG ;
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; lpm_add_sub.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ;
|
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; addcore.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/addcore.inc ; ;
|
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; look_add.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/look_add.inc ; ;
|
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; bypassff.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/bypassff.inc ; ;
|
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; altshift.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.inc ; ;
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; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ;
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; aglobal181.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ;
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|
; db/add_sub_1vk.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_1vk.tdf ; ;
|
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; altpll.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf ; ;
|
|
; stratix_pll.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
|
|
; stratixii_pll.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
|
|
; cycloneii_pll.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
|
|
; db/tx_pll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/tx_pll_altpll.v ; ;
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; lpm_mult.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ;
|
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; lpm_add_sub.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
|
|
; multcore.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.inc ; ;
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|
; db/mult_abt.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_abt.tdf ; ;
|
|
; scfifo.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf ; ;
|
|
; a_regfifo.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_regfifo.inc ; ;
|
|
; a_dpfifo.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ;
|
|
; a_i2fifo.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ;
|
|
; a_fffifo.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_fffifo.inc ; ;
|
|
; a_f2fifo.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ;
|
|
; db/scfifo_gf71.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_gf71.tdf ; ;
|
|
; db/a_dpfifo_1lv.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf ; ;
|
|
; db/altsyncram_l7h1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_l7h1.tdf ; ;
|
|
; db/cmpr_gs8.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_gs8.tdf ; ;
|
|
; db/cntr_r9b.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_r9b.tdf ; ;
|
|
; db/cntr_8a7.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_8a7.tdf ; ;
|
|
; db/cntr_s9b.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_s9b.tdf ; ;
|
|
; db/scfifo_ci71.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ci71.tdf ; ;
|
|
; db/a_dpfifo_9qv.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf ; ;
|
|
; db/altsyncram_hah1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_hah1.tdf ; ;
|
|
; db/cmpr_is8.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_is8.tdf ; ;
|
|
; db/cntr_t9b.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_t9b.tdf ; ;
|
|
; db/cntr_aa7.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_aa7.tdf ; ;
|
|
; db/cntr_u9b.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_u9b.tdf ; ;
|
|
; altsyncram.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
|
|
; stratix_ram_block.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
|
|
; lpm_mux.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
|
|
; lpm_decode.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
|
|
; a_rdenreg.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
|
|
; altrom.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altrom.inc ; ;
|
|
; altram.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altram.inc ; ;
|
|
; altdpram.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altdpram.inc ; ;
|
|
; db/altsyncram_0mn3.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_0mn3.tdf ; ;
|
|
; db/mult_ncu.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_ncu.tdf ; ;
|
|
; db/add_sub_u4i.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_u4i.tdf ; ;
|
|
; db/altsyncram_4k82.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_4k82.tdf ; ;
|
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; db/altsyncram_u8a1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_u8a1.tdf ; ;
|
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; db/altsyncram_p8a1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_p8a1.tdf ; ;
|
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; db/add_sub_jpk.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_jpk.tdf ; ;
|
|
; lpm_counter.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
|
; lpm_constant.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
|
|
; cmpconst.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/cmpconst.inc ; ;
|
|
; lpm_compare.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
|
|
; lpm_counter.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
|
|
; dffeea.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/dffeea.inc ; ;
|
|
; alt_counter_stratix.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
|
|
; db/cntr_asi.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_asi.tdf ; ;
|
|
; db/scfifo_ef71.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ef71.tdf ; ;
|
|
; db/a_dpfifo_vkv.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_vkv.tdf ; ;
|
|
; db/altsyncram_h7h1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_h7h1.tdf ; ;
|
|
; db/scfifo_ji71.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ji71.tdf ; ;
|
|
; db/a_dpfifo_gqv.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_gqv.tdf ; ;
|
|
; db/altsyncram_vah1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_vah1.tdf ; ;
|
|
; db/scfifo_qm51.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_qm51.tdf ; ;
|
|
; db/a_dpfifo_5ku.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf ; ;
|
|
; db/altsyncram_m7h1.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf ; ;
|
|
; db/cmpr_fs8.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_fs8.tdf ; ;
|
|
; db/cntr_q9b.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_q9b.tdf ; ;
|
|
; db/cntr_7a7.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_7a7.tdf ; ;
|
|
; db/altsyncram_h982.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_h982.tdf ; ;
|
|
; db/altsyncram_fu91.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_fu91.tdf ; ;
|
|
; db/altsyncram_au91.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_au91.tdf ; ;
|
|
; db/add_sub_fpk.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_fpk.tdf ; ;
|
|
; db/mult_jnp.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_jnp.tdf ; ;
|
|
; db/main_pll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/main_pll_altpll.v ; ;
|
|
; lpm_mux.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.tdf ; ;
|
|
; muxlut.inc ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/muxlut.inc ; ;
|
|
; db/mux_rsc.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mux_rsc.tdf ; ;
|
|
; lpm_constant.tdf ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_constant.tdf ; ;
|
|
; altsource_probe.v ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v ; ;
|
|
; sld_jtag_endpoint_adapter.vhd ; yes ; Encrypted Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd ; ;
|
|
; sld_jtag_endpoint_adapter_impl.sv ; yes ; Encrypted Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv ; ;
|
|
; altsource_probe_body.vhd ; yes ; Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd ; ;
|
|
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ;
|
|
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_hub.vhd ; altera_sld ;
|
|
; db/ip/sld0b974a4e/alt_sld_fab.v ; yes ; Encrypted Altera IP File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/alt_sld_fab.v ; alt_sld_fab ;
|
|
; db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v ; yes ; Encrypted Altera IP File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v ; alt_sld_fab ;
|
|
; db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv ; yes ; Auto-Found SystemVerilog HDL File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv ; alt_sld_fab ;
|
|
; db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv ; yes ; Encrypted Altera IP File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv ; alt_sld_fab ;
|
|
; db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; yes ; Encrypted Altera IP File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; alt_sld_fab ;
|
|
; db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv ; yes ; Encrypted Altera IP File ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv ; alt_sld_fab ;
|
|
; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ;
|
|
; db/mult_36t.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_36t.tdf ; ;
|
|
; db/mult_t5t.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_t5t.tdf ; ;
|
|
; db/altsyncram_nci3.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_nci3.tdf ; ;
|
|
; db/decode_msa.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/decode_msa.tdf ; ;
|
|
; db/mux_sob.tdf ; yes ; Auto-Generated Megafunction ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mux_sob.tdf ; ;
|
|
+--------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis IP Cores Summary ;
|
|
+--------+---------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+
|
|
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
|
+--------+---------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; ;
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; ;
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit ; ;
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; ;
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter ; ;
|
|
; Altera ; LPM_CONSTANT ; 18.1 ; N/A ; N/A ; |WOLF-LITE|dac_null:DAC_IDLE ; dac_null.v ;
|
|
; Altera ; LPM_MUX ; 18.1 ; N/A ; N/A ; |WOLF-LITE|mux14:DAC_MUX ; mux14.v ;
|
|
; N/A ; altera_in_system_sources_probes ; 18.1 ; N/A ; N/A ; |WOLF-LITE|DEBUG:DBG_ADC ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/DEBUG.qsys ;
|
|
; Altera ; ALTPLL ; 18.1 ; N/A ; N/A ; |WOLF-LITE|MAIN_PLL:MAIN_PLL ; MAIN_PLL.v ;
|
|
; N/A ; altera_cic_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|rx_cic:RX_CIC_I ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_cic.qsys ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; ;
|
|
; N/A ; altera_cic_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|rx_cic:RX_CIC_Q ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_cic.qsys ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; ;
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|
; Altera ; altera_fir_compiler_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I ; rx_ciccomp.v ;
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|
; Altera ; altera_fir_compiler_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q ; rx_ciccomp.v ;
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|
; Altera ; LPM_MULT ; 18.1 ; N/A ; N/A ; |WOLF-LITE|mixer:RX_MIXER_I ; mixer.v ;
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|
; Altera ; LPM_MULT ; 18.1 ; N/A ; N/A ; |WOLF-LITE|mixer:RX_MIXER_Q ; mixer.v ;
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|
; N/A ; altera_nco_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|nco:RX_NCO ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/nco.qsys ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_derot:ux0136 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr ; ;
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|
; N/A ; altclkctrl ; 18.1 ; N/A ; N/A ; |WOLF-LITE|clock_buffer:SYSCLK_BUFFER ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/clock_buffer.qsys ;
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|
; N/A ; altera_cic_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_cic:TX_CIC_I ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_cic.qsys ;
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|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_upsample:first_upsample ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; ;
|
|
; N/A ; altera_cic_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_cic:TX_CIC_Q ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_cic.qsys ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_upsample:first_upsample ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst ; ;
|
|
; Altera ; CIC Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; ;
|
|
; Altera ; altera_fir_compiler_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I ; tx_ciccomp.v ;
|
|
; Altera ; altera_fir_compiler_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q ; tx_ciccomp.v ;
|
|
; Altera ; LPM_MULT ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_mixer:TX_MIXER_I ; tx_mixer.v ;
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; Altera ; LPM_MULT ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_mixer:TX_MIXER_Q ; tx_mixer.v ;
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; N/A ; altera_nco_ii ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_nco:TX_NCO ; D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_nco.qsys ;
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; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0 ; ;
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|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_derot:ux0136 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220 ; ;
|
|
; Altera ; NCO Compiler ; N/A ; N/A ; Licensed ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr ; ;
|
|
; Altera ; ALTPLL ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_pll:TX_PLL ; tx_pll.v ;
|
|
; Altera ; LPM_ADD_SUB ; 18.1 ; N/A ; N/A ; |WOLF-LITE|tx_summator:TX_SUMMATOR ; tx_summator.v ;
|
|
+--------+---------------------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+
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|
|
|
|
|
+----------------------------------------------------------+
|
|
; Partition Status Summary ;
|
|
+------------------+-------------+-------------------------+
|
|
; Partition Name ; Synthesized ; Reason ;
|
|
+------------------+-------------+-------------------------+
|
|
; Top ; yes ; Dependent files changed ;
|
|
; sld_hub:auto_hub ; no ; No relevant changes ;
|
|
+------------------+-------------+-------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Dependent File Changes for Partition Top ;
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-------------------+----------+----------------------------------+----------------------------------+
|
|
; Hierarchy ; File Name ; Relative Location ; Change ; Old ; New ;
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-------------------+----------+----------------------------------+----------------------------------+
|
|
; rx_ciccomp:rx_ciccomp_i ; rx_ciccomp.v ; Project Directory ; Checksum ; 7423f4eff8d3271138202712ab3a170c ; 90c4f6896871ade19c6e0c1e93b0d2ce ;
|
|
; rx_ciccomp:rx_ciccomp_i|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd ; Project Directory ; Checksum ; 1356d784d5205083fa0401f28e6d6ead ; b65eb122d938b69287827e8058ee15a1 ;
|
|
; rx_ciccomp:rx_cicomp_q ; rx_ciccomp.v ; Project Directory ; Checksum ; 7423f4eff8d3271138202712ab3a170c ; 90c4f6896871ade19c6e0c1e93b0d2ce ;
|
|
; rx_ciccomp:rx_cicomp_q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd ; Project Directory ; Checksum ; 1356d784d5205083fa0401f28e6d6ead ; b65eb122d938b69287827e8058ee15a1 ;
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|
; | ; WOLF-LITE.bdf ; Project Directory ; Checksum ; 698ffaee2877d3d135ca59baaaf493a4 ; 3b66629c45fef02be52ad5d1aa4d8023 ;
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-------------------+----------+----------------------------------+----------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Partition for Top-Level Resource Utilization by Entity ;
|
|
+----------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
|
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
|
+----------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
|
; |WOLF-LITE ; 7258 (1) ; 7440 (0) ; 183280 ; 32 ; 0 ; 16 ; 0 ; 0 ; |WOLF-LITE ; WOLF-LITE ; work ;
|
|
; |DAC_corrector:DAC_CORRECTOR| ; 142 (142) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DAC_corrector:DAC_CORRECTOR ; DAC_corrector ; work ;
|
|
; |DEBUG:DBG_ADC| ; 41 (0) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC ; DEBUG ; DEBUG ;
|
|
; |altsource_probe_top:in_system_sources_probes_0| ; 41 (0) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0 ; altsource_probe_top ; DEBUG ;
|
|
; |altsource_probe:issp_impl| ; 41 (0) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl ; altsource_probe ; work ;
|
|
; |altsource_probe_body:altsource_probe_body_inst| ; 41 (3) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst ; altsource_probe_body ; work ;
|
|
; |altsource_probe_impl:\wider_probe_gen:wider_probe_inst| ; 38 (21) ; 22 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst ; altsource_probe_impl ; work ;
|
|
; |sld_rom_sr:\instance_id_gen:rom_info_inst| ; 17 (17) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst|sld_rom_sr:\instance_id_gen:rom_info_inst ; sld_rom_sr ; work ;
|
|
; |MAIN_PLL:MAIN_PLL| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|MAIN_PLL:MAIN_PLL ; MAIN_PLL ; work ;
|
|
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|MAIN_PLL:MAIN_PLL|altpll:altpll_component ; altpll ; work ;
|
|
; |MAIN_PLL_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|MAIN_PLL:MAIN_PLL|altpll:altpll_component|MAIN_PLL_altpll:auto_generated ; MAIN_PLL_altpll ; work ;
|
|
; |clock_buffer:SYSCLK_BUFFER| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|clock_buffer:SYSCLK_BUFFER ; clock_buffer ; clock_buffer ;
|
|
; |clock_buffer_altclkctrl_0:altclkctrl_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0 ; clock_buffer_altclkctrl_0 ; clock_buffer ;
|
|
; |clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component ; clock_buffer_altclkctrl_0_sub ; clock_buffer ;
|
|
; |data_shifter:CIC_GAINER| ; 834 (834) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|data_shifter:CIC_GAINER ; data_shifter ; work ;
|
|
; |data_shifter:RX_CICFIR_GAINER| ; 283 (283) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|data_shifter:RX_CICFIR_GAINER ; data_shifter ; work ;
|
|
; |data_shifter:TX_CICCOMP_GAINER| ; 291 (291) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER ; data_shifter ; work ;
|
|
; |mixer:RX_MIXER_I| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_I ; mixer ; work ;
|
|
; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_I|lpm_mult:lpm_mult_component ; lpm_mult ; work ;
|
|
; |mult_jnp:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_I|lpm_mult:lpm_mult_component|mult_jnp:auto_generated ; mult_jnp ; work ;
|
|
; |mixer:RX_MIXER_Q| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_Q ; mixer ; work ;
|
|
; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_Q|lpm_mult:lpm_mult_component ; lpm_mult ; work ;
|
|
; |mult_jnp:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|mixer:RX_MIXER_Q|lpm_mult:lpm_mult_component|mult_jnp:auto_generated ; mult_jnp ; work ;
|
|
; |mux14:DAC_MUX| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|mux14:DAC_MUX ; mux14 ; work ;
|
|
; |lpm_mux:LPM_MUX_component| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|mux14:DAC_MUX|lpm_mux:LPM_MUX_component ; lpm_mux ; work ;
|
|
; |mux_rsc:auto_generated| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|mux14:DAC_MUX|lpm_mux:LPM_MUX_component|mux_rsc:auto_generated ; mux_rsc ; work ;
|
|
; |nco:RX_NCO| ; 181 (0) ; 149 (0) ; 73728 ; 8 ; 0 ; 4 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO ; nco ; nco ;
|
|
; |nco_nco_ii_0:nco_ii_0| ; 181 (0) ; 149 (0) ; 73728 ; 8 ; 0 ; 4 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0 ; nco_nco_ii_0 ; nco ;
|
|
; |asj_altqmcpipe:ux000| ; 44 (22) ; 44 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000 ; asj_altqmcpipe ; nco ;
|
|
; |lpm_add_sub:acc| ; 22 (0) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc ; lpm_add_sub ; work ;
|
|
; |add_sub_u4i:auto_generated| ; 22 (22) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated ; add_sub_u4i ; work ;
|
|
; |asj_gam_dp:ux008| ; 24 (24) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008 ; asj_gam_dp ; nco ;
|
|
; |asj_nco_as_m_cen:ux0122| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122 ; asj_nco_as_m_cen ; nco ;
|
|
; |altsyncram:altsyncram_component0| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0 ; altsyncram ; work ;
|
|
; |altsyncram_fu91:auto_generated| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_fu91:auto_generated ; altsyncram_fu91 ; work ;
|
|
; |asj_nco_as_m_cen:ux0123| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123 ; asj_nco_as_m_cen ; nco ;
|
|
; |altsyncram:altsyncram_component0| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0 ; altsyncram ; work ;
|
|
; |altsyncram_au91:auto_generated| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_au91:auto_generated ; altsyncram_au91 ; work ;
|
|
; |asj_nco_as_m_dp_cen:ux0220| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220 ; asj_nco_as_m_dp_cen ; nco ;
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component ; altsyncram ; work ;
|
|
; |altsyncram_h982:auto_generated| ; 0 (0) ; 0 (0) ; 24576 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_h982:auto_generated ; altsyncram_h982 ; work ;
|
|
; |asj_nco_isdr:ux710isdr| ; 6 (2) ; 5 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr ; asj_nco_isdr ; nco ;
|
|
; |lpm_counter:lpm_counter_component| ; 4 (0) ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component ; lpm_counter ; work ;
|
|
; |cntr_asi:auto_generated| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component|cntr_asi:auto_generated ; cntr_asi ; work ;
|
|
; |asj_nco_madx_cen:m1| ; 24 (24) ; 13 (13) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1 ; asj_nco_madx_cen ; nco ;
|
|
; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0 ; lpm_mult ; work ;
|
|
; |mult_t5t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_t5t:auto_generated ; mult_t5t ; work ;
|
|
; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1 ; lpm_mult ; work ;
|
|
; |mult_t5t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_t5t:auto_generated ; mult_t5t ; work ;
|
|
; |asj_nco_mady_cen:m0| ; 24 (24) ; 13 (13) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0 ; asj_nco_mady_cen ; nco ;
|
|
; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0 ; lpm_mult ; work ;
|
|
; |mult_t5t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_t5t:auto_generated ; mult_t5t ; work ;
|
|
; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1 ; lpm_mult ; work ;
|
|
; |mult_t5t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_t5t:auto_generated ; mult_t5t ; work ;
|
|
; |asj_nco_mob_w:blk0| ; 30 (18) ; 25 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0 ; asj_nco_mob_w ; nco ;
|
|
; |lpm_add_sub:lpm_add_sub_component| ; 12 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component ; lpm_add_sub ; work ;
|
|
; |add_sub_fpk:auto_generated| ; 12 (12) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_fpk:auto_generated ; add_sub_fpk ; work ;
|
|
; |asj_nco_mob_w:blk1| ; 29 (17) ; 25 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1 ; asj_nco_mob_w ; nco ;
|
|
; |lpm_add_sub:lpm_add_sub_component| ; 12 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1|lpm_add_sub:lpm_add_sub_component ; lpm_add_sub ; work ;
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; |add_sub_fpk:auto_generated| ; 12 (12) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1|lpm_add_sub:lpm_add_sub_component|add_sub_fpk:auto_generated ; add_sub_fpk ; work ;
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; |rx_cic:RX_CIC_I| ; 1399 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I ; rx_cic ; rx_cic ;
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; |rx_cic_cic_ii_0:cic_ii_0| ; 1399 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0 ; rx_cic_cic_ii_0 ; rx_cic ;
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; |alt_cic_core:core| ; 1399 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; alt_cic_core ; rx_cic ;
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; |alt_cic_dec_siso:dec_one| ; 1292 (8) ; 2191 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one ; alt_cic_dec_siso ; rx_cic ;
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; |auk_dspip_channel_buffer:fifo_regulator| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator ; auk_dspip_channel_buffer ; rx_cic ;
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; |scfifo:buffer_FIFO| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO ; scfifo ; work ;
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; |scfifo_qm51:auto_generated| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated ; scfifo_qm51 ; work ;
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; |a_dpfifo_5ku:dpfifo| ; 204 (20) ; 617 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo ; a_dpfifo_5ku ; work ;
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; |altsyncram_m7h1:FIFOram| ; 176 (0) ; 605 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram ; altsyncram_m7h1 ; work ;
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; |altsyncram:ram_block1a0| ; 176 (0) ; 605 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0 ; altsyncram ; work ;
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; |altsyncram_nci3:auto_generated| ; 176 (0) ; 605 (605) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated ; altsyncram_nci3 ; work ;
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; |decode_msa:address_decoder| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated|decode_msa:address_decoder ; decode_msa ; work ;
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; |mux_sob:output_mux| ; 172 (172) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated|mux_sob:output_mux ; mux_sob ; work ;
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; |cntr_7a7:usedw_counter| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_7a7:usedw_counter ; cntr_7a7 ; work ;
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; |cntr_q9b:rd_ptr_msb| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_q9b:rd_ptr_msb ; cntr_q9b ; work ;
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; |cntr_r9b:wr_ptr| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_r9b:wr_ptr ; cntr_r9b ; work ;
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; |auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff| ; 90 (90) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_downsample:vrc_en_0.first_dsample| ; 22 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample ; auk_dspip_downsample ; rx_cic ;
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; |counter_module:counter_fs_inst| ; 22 (22) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst ; counter_module ; rx_cic ;
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; |auk_dspip_integrator:integrator[0].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[1].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[2].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[3].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[4].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[5].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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|
; |counter_module:latency_cnt_inst| ; 7 (7) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst ; counter_module ; rx_cic ;
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; |auk_dspip_avalon_streaming_controller:avalon_controller| ; 33 (7) ; 16 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; auk_dspip_avalon_streaming_controller ; rx_cic ;
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; |auk_dspip_avalon_streaming_small_fifo:ready_FIFO| ; 26 (26) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; auk_dspip_avalon_streaming_small_fifo ; rx_cic ;
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; |auk_dspip_avalon_streaming_sink:input_sink| ; 33 (0) ; 17 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; auk_dspip_avalon_streaming_sink ; rx_cic ;
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; |scfifo:sink_FIFO| ; 33 (0) ; 17 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO ; scfifo ; work ;
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; |scfifo_ef71:auto_generated| ; 33 (2) ; 17 (1) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated ; scfifo_ef71 ; work ;
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; |a_dpfifo_vkv:dpfifo| ; 31 (20) ; 16 (8) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo ; a_dpfifo_vkv ; work ;
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; |altsyncram_h7h1:FIFOram| ; 0 (0) ; 0 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram ; altsyncram_h7h1 ; work ;
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; |cntr_8a7:usedw_counter| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_8a7:usedw_counter ; cntr_8a7 ; work ;
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; |cntr_r9b:rd_ptr_msb| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_r9b:rd_ptr_msb ; cntr_r9b ; work ;
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; |cntr_s9b:wr_ptr| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_s9b:wr_ptr ; cntr_s9b ; work ;
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; |auk_dspip_avalon_streaming_source:output_source_0| ; 41 (1) ; 25 (1) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; auk_dspip_avalon_streaming_source ; rx_cic ;
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; |scfifo:source_FIFO| ; 40 (0) ; 24 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO ; scfifo ; work ;
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; |scfifo_ji71:auto_generated| ; 40 (0) ; 24 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated ; scfifo_ji71 ; work ;
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; |a_dpfifo_gqv:dpfifo| ; 40 (23) ; 24 (10) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo ; a_dpfifo_gqv ; work ;
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; |altsyncram_vah1:FIFOram| ; 0 (0) ; 0 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|altsyncram_vah1:FIFOram ; altsyncram_vah1 ; work ;
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; |cntr_aa7:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_aa7:usedw_counter ; cntr_aa7 ; work ;
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; |cntr_t9b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_t9b:rd_ptr_msb ; cntr_t9b ; work ;
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; |cntr_u9b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_u9b:wr_ptr ; cntr_u9b ; work ;
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; |rx_cic:RX_CIC_Q| ; 1402 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q ; rx_cic ; rx_cic ;
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; |rx_cic_cic_ii_0:cic_ii_0| ; 1402 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0 ; rx_cic_cic_ii_0 ; rx_cic ;
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; |alt_cic_core:core| ; 1402 (0) ; 2249 (0) ; 2936 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; alt_cic_core ; rx_cic ;
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; |alt_cic_dec_siso:dec_one| ; 1292 (8) ; 2191 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one ; alt_cic_dec_siso ; rx_cic ;
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; |auk_dspip_channel_buffer:fifo_regulator| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator ; auk_dspip_channel_buffer ; rx_cic ;
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; |scfifo:buffer_FIFO| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO ; scfifo ; work ;
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; |scfifo_qm51:auto_generated| ; 204 (0) ; 617 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated ; scfifo_qm51 ; work ;
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; |a_dpfifo_5ku:dpfifo| ; 204 (20) ; 617 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo ; a_dpfifo_5ku ; work ;
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; |altsyncram_m7h1:FIFOram| ; 176 (0) ; 605 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram ; altsyncram_m7h1 ; work ;
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; |altsyncram:ram_block1a0| ; 176 (0) ; 605 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0 ; altsyncram ; work ;
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; |altsyncram_nci3:auto_generated| ; 176 (0) ; 605 (605) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated ; altsyncram_nci3 ; work ;
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; |decode_msa:address_decoder| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated|decode_msa:address_decoder ; decode_msa ; work ;
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; |mux_sob:output_mux| ; 172 (172) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0|altsyncram_nci3:auto_generated|mux_sob:output_mux ; mux_sob ; work ;
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; |cntr_7a7:usedw_counter| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_7a7:usedw_counter ; cntr_7a7 ; work ;
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; |cntr_q9b:rd_ptr_msb| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_q9b:rd_ptr_msb ; cntr_q9b ; work ;
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; |cntr_r9b:wr_ptr| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_r9b:wr_ptr ; cntr_r9b ; work ;
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; |auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff| ; 90 (90) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff| ; 89 (89) ; 173 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff ; auk_dspip_differentiator ; rx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_downsample:vrc_en_0.first_dsample| ; 22 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample ; auk_dspip_downsample ; rx_cic ;
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; |counter_module:counter_fs_inst| ; 22 (22) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst ; counter_module ; rx_cic ;
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; |auk_dspip_integrator:integrator[0].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[1].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[2].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[3].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[4].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |auk_dspip_integrator:integrator[5].integration| ; 86 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration ; auk_dspip_integrator ; rx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 86 (86) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; rx_cic ;
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; |counter_module:latency_cnt_inst| ; 7 (7) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst ; counter_module ; rx_cic ;
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; |auk_dspip_avalon_streaming_controller:avalon_controller| ; 33 (7) ; 16 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; auk_dspip_avalon_streaming_controller ; rx_cic ;
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; |auk_dspip_avalon_streaming_small_fifo:ready_FIFO| ; 26 (26) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; auk_dspip_avalon_streaming_small_fifo ; rx_cic ;
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; |auk_dspip_avalon_streaming_sink:input_sink| ; 36 (0) ; 17 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; auk_dspip_avalon_streaming_sink ; rx_cic ;
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; |scfifo:sink_FIFO| ; 36 (0) ; 17 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO ; scfifo ; work ;
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; |scfifo_ef71:auto_generated| ; 36 (2) ; 17 (1) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated ; scfifo_ef71 ; work ;
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; |a_dpfifo_vkv:dpfifo| ; 34 (23) ; 16 (8) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo ; a_dpfifo_vkv ; work ;
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; |altsyncram_h7h1:FIFOram| ; 0 (0) ; 0 (0) ; 184 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram ; altsyncram_h7h1 ; work ;
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; |cntr_8a7:usedw_counter| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_8a7:usedw_counter ; cntr_8a7 ; work ;
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; |cntr_r9b:rd_ptr_msb| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_r9b:rd_ptr_msb ; cntr_r9b ; work ;
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; |cntr_s9b:wr_ptr| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|cntr_s9b:wr_ptr ; cntr_s9b ; work ;
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; |auk_dspip_avalon_streaming_source:output_source_0| ; 41 (1) ; 25 (1) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; auk_dspip_avalon_streaming_source ; rx_cic ;
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; |scfifo:source_FIFO| ; 40 (0) ; 24 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO ; scfifo ; work ;
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; |scfifo_ji71:auto_generated| ; 40 (0) ; 24 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated ; scfifo_ji71 ; work ;
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; |a_dpfifo_gqv:dpfifo| ; 40 (23) ; 24 (10) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo ; a_dpfifo_gqv ; work ;
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; |altsyncram_vah1:FIFOram| ; 0 (0) ; 0 (0) ; 2752 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|altsyncram_vah1:FIFOram ; altsyncram_vah1 ; work ;
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; |cntr_aa7:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_aa7:usedw_counter ; cntr_aa7 ; work ;
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; |cntr_t9b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_t9b:rd_ptr_msb ; cntr_t9b ; work ;
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; |cntr_u9b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|cntr_u9b:wr_ptr ; cntr_u9b ; work ;
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; |rx_ciccomp:RX_CICCOMP_I| ; 166 (0) ; 183 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I ; rx_ciccomp ; rx_ciccomp ;
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; |rx_ciccomp_0002:rx_ciccomp_inst| ; 166 (0) ; 183 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst ; rx_ciccomp_0002 ; rx_ciccomp ;
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; |rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst| ; 166 (0) ; 183 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ; rx_ciccomp_0002_ast ; rx_ciccomp ;
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; |auk_dspip_avalon_streaming_source_hpfir:source| ; 0 (0) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ; auk_dspip_avalon_streaming_source_hpfir ; rx_ciccomp ;
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; |rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core| ; 166 (166) ; 153 (96) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; rx_ciccomp_0002_rtl_core ; rx_ciccomp ;
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; |altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ; altsyncram ; work ;
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; |altsyncram_0mn3:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ; altsyncram_0mn3 ; work ;
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; |dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_14| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_15| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_xIn_0_13| ; 0 (0) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_compute| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_memread| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ; dspba_delay ; rx_ciccomp ;
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; |lpm_mult:u0_m0_wo0_mtree_mult1_0_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ; lpm_mult ; work ;
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; |mult_ncu:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated ; mult_ncu ; work ;
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; |rx_ciccomp:RX_CICOMP_Q| ; 193 (0) ; 195 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q ; rx_ciccomp ; rx_ciccomp ;
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; |rx_ciccomp_0002:rx_ciccomp_inst| ; 193 (0) ; 195 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst ; rx_ciccomp_0002 ; rx_ciccomp ;
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; |rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst| ; 193 (0) ; 195 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ; rx_ciccomp_0002_ast ; rx_ciccomp ;
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; |auk_dspip_avalon_streaming_source_hpfir:source| ; 0 (0) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ; auk_dspip_avalon_streaming_source_hpfir ; rx_ciccomp ;
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; |rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core| ; 193 (193) ; 164 (107) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; rx_ciccomp_0002_rtl_core ; rx_ciccomp ;
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; |altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ; altsyncram ; work ;
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; |altsyncram_0mn3:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ; altsyncram_0mn3 ; work ;
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; |dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_14| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_15| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:d_xIn_0_13| ; 0 (0) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_compute| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ; dspba_delay ; rx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_memread| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ; dspba_delay ; rx_ciccomp ;
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; |lpm_mult:u0_m0_wo0_mtree_mult1_0_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ; lpm_mult ; work ;
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; |mult_ncu:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated ; mult_ncu ; work ;
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; |spi_interface:FLASH| ; 75 (75) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|spi_interface:FLASH ; spi_interface ; work ;
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; |stm32_interface:STM32_INTERFACE| ; 309 (309) ; 238 (238) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|stm32_interface:STM32_INTERFACE ; stm32_interface ; work ;
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; |tx_cic:TX_CIC_I| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I ; tx_cic ; tx_cic ;
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; |tx_cic_cic_ii_0:cic_ii_0| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0 ; tx_cic_cic_ii_0 ; tx_cic ;
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; |alt_cic_core:core| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; alt_cic_core ; tx_cic ;
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; |alt_cic_int_siso:int_one| ; 619 (4) ; 697 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one ; alt_cic_int_siso ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff| ; 18 (18) ; 34 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff| ; 19 (19) ; 36 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff| ; 20 (20) ; 38 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff| ; 21 (21) ; 40 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff| ; 22 (22) ; 42 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff| ; 23 (23) ; 44 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[0].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[1].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[2].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[3].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[4].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_integrator:integrator_loop[5].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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|
; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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|
; |auk_dspip_upsample:first_upsample| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_upsample:first_upsample ; auk_dspip_upsample ; tx_cic ;
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|
; |counter_module:counter_fs_inst| ; 20 (20) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst ; counter_module ; tx_cic ;
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|
; |auk_dspip_avalon_streaming_controller:avalon_controller| ; 34 (5) ; 16 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; auk_dspip_avalon_streaming_controller ; tx_cic ;
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|
; |auk_dspip_avalon_streaming_small_fifo:ready_FIFO| ; 29 (29) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; auk_dspip_avalon_streaming_small_fifo ; tx_cic ;
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|
; |auk_dspip_avalon_streaming_sink:input_sink| ; 26 (0) ; 18 (1) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; auk_dspip_avalon_streaming_sink ; tx_cic ;
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|
; |scfifo:sink_FIFO| ; 26 (0) ; 17 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO ; scfifo ; work ;
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; |scfifo_gf71:auto_generated| ; 26 (2) ; 17 (1) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated ; scfifo_gf71 ; work ;
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; |a_dpfifo_1lv:dpfifo| ; 24 (16) ; 16 (8) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo ; a_dpfifo_1lv ; work ;
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; |altsyncram_l7h1:FIFOram| ; 0 (0) ; 0 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram ; altsyncram_l7h1 ; work ;
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; |cntr_8a7:usedw_counter| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_8a7:usedw_counter ; cntr_8a7 ; work ;
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; |cntr_r9b:rd_ptr_msb| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_r9b:rd_ptr_msb ; cntr_r9b ; work ;
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; |cntr_s9b:wr_ptr| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_s9b:wr_ptr ; cntr_s9b ; work ;
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; |auk_dspip_avalon_streaming_source:output_source_0| ; 36 (1) ; 26 (1) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; auk_dspip_avalon_streaming_source ; tx_cic ;
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|
; |scfifo:source_FIFO| ; 35 (0) ; 25 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO ; scfifo ; work ;
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; |scfifo_ci71:auto_generated| ; 35 (3) ; 25 (1) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated ; scfifo_ci71 ; work ;
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; |a_dpfifo_9qv:dpfifo| ; 32 (18) ; 24 (10) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo ; a_dpfifo_9qv ; work ;
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|
; |altsyncram_hah1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram ; altsyncram_hah1 ; work ;
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|
; |cntr_aa7:usedw_counter| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_aa7:usedw_counter ; cntr_aa7 ; work ;
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|
; |cntr_t9b:rd_ptr_msb| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_t9b:rd_ptr_msb ; cntr_t9b ; work ;
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|
; |cntr_u9b:wr_ptr| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_u9b:wr_ptr ; cntr_u9b ; work ;
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|
; |tx_cic:TX_CIC_Q| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q ; tx_cic ; tx_cic ;
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|
; |tx_cic_cic_ii_0:cic_ii_0| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0 ; tx_cic_cic_ii_0 ; tx_cic ;
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|
; |alt_cic_core:core| ; 715 (0) ; 757 (0) ; 640 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core ; alt_cic_core ; tx_cic ;
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; |alt_cic_int_siso:int_one| ; 619 (4) ; 697 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one ; alt_cic_int_siso ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff| ; 18 (18) ; 34 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff| ; 19 (19) ; 36 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff| ; 20 (20) ; 38 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff| ; 21 (21) ; 40 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff| ; 22 (22) ; 42 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff| ; 23 (23) ; 44 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff ; auk_dspip_differentiator ; tx_cic ;
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; |auk_dspip_delay:\glogic:u0| ; 0 (0) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[0].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[1].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[1].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[2].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[2].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[3].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[3].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[4].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[4].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_integrator:integrator_loop[5].auK_integrator| ; 75 (0) ; 75 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator ; auk_dspip_integrator ; tx_cic ;
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; |auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1| ; 75 (75) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[5].auK_integrator|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1 ; auk_dspip_delay ; tx_cic ;
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; |auk_dspip_upsample:first_upsample| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_upsample:first_upsample ; auk_dspip_upsample ; tx_cic ;
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; |counter_module:counter_fs_inst| ; 20 (20) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst ; counter_module ; tx_cic ;
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; |auk_dspip_avalon_streaming_controller:avalon_controller| ; 34 (5) ; 16 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller ; auk_dspip_avalon_streaming_controller ; tx_cic ;
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; |auk_dspip_avalon_streaming_small_fifo:ready_FIFO| ; 29 (29) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO ; auk_dspip_avalon_streaming_small_fifo ; tx_cic ;
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; |auk_dspip_avalon_streaming_sink:input_sink| ; 26 (0) ; 18 (1) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink ; auk_dspip_avalon_streaming_sink ; tx_cic ;
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; |scfifo:sink_FIFO| ; 26 (0) ; 17 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO ; scfifo ; work ;
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; |scfifo_gf71:auto_generated| ; 26 (2) ; 17 (1) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated ; scfifo_gf71 ; work ;
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; |a_dpfifo_1lv:dpfifo| ; 24 (16) ; 16 (8) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo ; a_dpfifo_1lv ; work ;
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; |altsyncram_l7h1:FIFOram| ; 0 (0) ; 0 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram ; altsyncram_l7h1 ; work ;
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; |cntr_8a7:usedw_counter| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_8a7:usedw_counter ; cntr_8a7 ; work ;
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; |cntr_r9b:rd_ptr_msb| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_r9b:rd_ptr_msb ; cntr_r9b ; work ;
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; |cntr_s9b:wr_ptr| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_s9b:wr_ptr ; cntr_s9b ; work ;
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; |auk_dspip_avalon_streaming_source:output_source_0| ; 36 (2) ; 26 (1) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0 ; auk_dspip_avalon_streaming_source ; tx_cic ;
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; |scfifo:source_FIFO| ; 34 (0) ; 25 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO ; scfifo ; work ;
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; |scfifo_ci71:auto_generated| ; 34 (3) ; 25 (1) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated ; scfifo_ci71 ; work ;
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; |a_dpfifo_9qv:dpfifo| ; 31 (17) ; 24 (10) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo ; a_dpfifo_9qv ; work ;
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; |altsyncram_hah1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram ; altsyncram_hah1 ; work ;
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; |cntr_aa7:usedw_counter| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_aa7:usedw_counter ; cntr_aa7 ; work ;
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; |cntr_t9b:rd_ptr_msb| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_t9b:rd_ptr_msb ; cntr_t9b ; work ;
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; |cntr_u9b:wr_ptr| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_u9b:wr_ptr ; cntr_u9b ; work ;
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; |tx_ciccomp:TX_CICCOMP_I| ; 196 (0) ; 222 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I ; tx_ciccomp ; tx_ciccomp ;
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; |tx_ciccomp_0002:tx_ciccomp_inst| ; 196 (0) ; 222 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst ; tx_ciccomp_0002 ; tx_ciccomp ;
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; |tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst| ; 196 (0) ; 222 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ; tx_ciccomp_0002_ast ; tx_ciccomp ;
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; |auk_dspip_avalon_streaming_source_hpfir:source| ; 0 (0) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ; auk_dspip_avalon_streaming_source_hpfir ; tx_ciccomp ;
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; |tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core| ; 196 (196) ; 191 (108) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; tx_ciccomp_0002_rtl_core ; tx_ciccomp ;
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; |altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ; altsyncram ; work ;
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; |altsyncram_0mn3:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ; altsyncram_0mn3 ; work ;
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; |dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17| ; 0 (0) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_aseq_q_16| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_14| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_15| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_compute_q_16| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_xIn_0_13| ; 0 (0) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_compute| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:u0_m0_wo0_memread| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ; dspba_delay ; tx_ciccomp ;
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; |lpm_mult:u0_m0_wo0_mtree_mult1_0_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ; lpm_mult ; work ;
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; |mult_ncu:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated ; mult_ncu ; work ;
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; |tx_ciccomp:TX_CICCOMP_Q| ; 122 (0) ; 178 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q ; tx_ciccomp ; tx_ciccomp ;
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; |tx_ciccomp_0002:tx_ciccomp_inst| ; 122 (0) ; 178 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst ; tx_ciccomp_0002 ; tx_ciccomp ;
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; |tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst| ; 122 (0) ; 178 (0) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ; tx_ciccomp_0002_ast ; tx_ciccomp ;
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; |auk_dspip_avalon_streaming_source_hpfir:source| ; 0 (0) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ; auk_dspip_avalon_streaming_source_hpfir ; tx_ciccomp ;
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; |tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core| ; 122 (122) ; 148 (76) ; 1024 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ; tx_ciccomp_0002_rtl_core ; tx_ciccomp ;
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; |altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ; altsyncram ; work ;
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; |altsyncram_0mn3:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ; altsyncram_0mn3 ; work ;
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; |dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17| ; 0 (0) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 ; dspba_delay ; tx_ciccomp ;
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; |dspba_delay:d_xIn_0_13| ; 0 (0) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ; dspba_delay ; tx_ciccomp ;
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; |lpm_mult:u0_m0_wo0_mtree_mult1_0_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ; lpm_mult ; work ;
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; |mult_ncu:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated ; mult_ncu ; work ;
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; |tx_mixer:TX_MIXER_I| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_I ; tx_mixer ; work ;
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; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component ; lpm_mult ; work ;
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; |mult_abt:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component|mult_abt:auto_generated ; mult_abt ; work ;
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; |tx_mixer:TX_MIXER_Q| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_Q ; tx_mixer ; work ;
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; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_Q|lpm_mult:lpm_mult_component ; lpm_mult ; work ;
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; |mult_abt:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_mixer:TX_MIXER_Q|lpm_mult:lpm_mult_component|mult_abt:auto_generated ; mult_abt ; work ;
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; |tx_nco:TX_NCO| ; 145 (0) ; 168 (0) ; 98304 ; 8 ; 0 ; 4 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO ; tx_nco ; tx_nco ;
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; |tx_nco_nco_ii_0:nco_ii_0| ; 145 (0) ; 168 (0) ; 98304 ; 8 ; 0 ; 4 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0 ; tx_nco_nco_ii_0 ; tx_nco ;
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; |asj_altqmcpipe:ux000| ; 33 (11) ; 44 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000 ; asj_altqmcpipe ; tx_nco ;
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; |lpm_add_sub:acc| ; 22 (0) ; 22 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc ; lpm_add_sub ; work ;
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; |add_sub_u4i:auto_generated| ; 22 (22) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated ; add_sub_u4i ; work ;
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; |asj_gam_dp:ux008| ; 2 (2) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008 ; asj_gam_dp ; tx_nco ;
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; |asj_nco_as_m_cen:ux0122| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122 ; asj_nco_as_m_cen ; tx_nco ;
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; |altsyncram:altsyncram_component0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0 ; altsyncram ; work ;
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; |altsyncram_u8a1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_u8a1:auto_generated ; altsyncram_u8a1 ; work ;
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; |asj_nco_as_m_cen:ux0123| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123 ; asj_nco_as_m_cen ; tx_nco ;
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; |altsyncram:altsyncram_component0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0 ; altsyncram ; work ;
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; |altsyncram_p8a1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_p8a1:auto_generated ; altsyncram_p8a1 ; work ;
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; |asj_nco_as_m_dp_cen:ux0220| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220 ; asj_nco_as_m_dp_cen ; tx_nco ;
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; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component ; altsyncram ; work ;
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; |altsyncram_4k82:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4k82:auto_generated ; altsyncram_4k82 ; work ;
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; |asj_nco_madx_cen:m1| ; 32 (32) ; 17 (17) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1 ; asj_nco_madx_cen ; tx_nco ;
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; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0 ; lpm_mult ; work ;
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; |mult_36t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_36t:auto_generated ; mult_36t ; work ;
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; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1 ; lpm_mult ; work ;
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; |mult_36t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_36t:auto_generated ; mult_36t ; work ;
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; |asj_nco_mady_cen:m0| ; 32 (32) ; 17 (17) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0 ; asj_nco_mady_cen ; tx_nco ;
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; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0 ; lpm_mult ; work ;
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; |mult_36t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_36t:auto_generated ; mult_36t ; work ;
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; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1 ; lpm_mult ; work ;
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; |mult_36t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_36t:auto_generated ; mult_36t ; work ;
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; |asj_nco_mob_w:blk0| ; 23 (7) ; 33 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0 ; asj_nco_mob_w ; tx_nco ;
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; |lpm_add_sub:lpm_add_sub_component| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component ; lpm_add_sub ; work ;
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; |add_sub_jpk:auto_generated| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_jpk:auto_generated ; add_sub_jpk ; work ;
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; |asj_nco_mob_w:blk1| ; 23 (7) ; 33 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1 ; asj_nco_mob_w ; tx_nco ;
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; |lpm_add_sub:lpm_add_sub_component| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1|lpm_add_sub:lpm_add_sub_component ; lpm_add_sub ; work ;
|
|
; |add_sub_jpk:auto_generated| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1|lpm_add_sub:lpm_add_sub_component|add_sub_jpk:auto_generated ; add_sub_jpk ; work ;
|
|
; |tx_pll:TX_PLL| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_pll:TX_PLL ; tx_pll ; work ;
|
|
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_pll:TX_PLL|altpll:altpll_component ; altpll ; work ;
|
|
; |tx_pll_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_pll:TX_PLL|altpll:altpll_component|tx_pll_altpll:auto_generated ; tx_pll_altpll ; work ;
|
|
; |tx_summator:TX_SUMMATOR| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_summator:TX_SUMMATOR ; tx_summator ; work ;
|
|
; |lpm_add_sub:LPM_ADD_SUB_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component ; lpm_add_sub ; work ;
|
|
; |add_sub_1vk:auto_generated| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component|add_sub_1vk:auto_generated ; add_sub_1vk ; work ;
|
|
+----------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
|
|
|
|
|
Encoding Type: One-Hot
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; State Machine - |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+---------------------------------------------------------------------------------------+
|
|
; Name ; sink_state.end1 ; sink_state.st_err ; sink_state.run1 ; sink_state.stall ; sink_state.start ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+---------------------------------------------------------------------------------------+
|
|
; sink_state.start ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
; sink_state.stall ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
|
; sink_state.run1 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
|
; sink_state.st_err ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
|
; sink_state.end1 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
Encoding Type: One-Hot
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; State Machine - |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; Name ; sink_state.end1 ; sink_state.st_err ; sink_state.run1 ; sink_state.stall ; sink_state.start ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; sink_state.start ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
; sink_state.stall ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
|
; sink_state.run1 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
|
; sink_state.st_err ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
|
; sink_state.end1 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
|
|
|
|
Encoding Type: One-Hot
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; Name ; sink_state.end1 ; sink_state.st_err ; sink_state.run1 ; sink_state.stall ; sink_state.start ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; sink_state.start ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
; sink_state.stall ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
|
; sink_state.run1 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
|
; sink_state.st_err ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
|
; sink_state.end1 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
|
|
|
|
Encoding Type: One-Hot
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; Name ; sink_state.end1 ; sink_state.st_err ; sink_state.run1 ; sink_state.stall ; sink_state.start ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
; sink_state.start ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
; sink_state.stall ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
|
; sink_state.run1 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
|
; sink_state.st_err ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
|
; sink_state.end1 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
|
+-------------------+-----------------+-------------------+-----------------+------------------+----------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Registers Protected by Synthesis ;
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
|
|
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ; yes ; yes ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ; yes ; yes ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ; yes ; yes ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ; yes ; yes ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ; yes ; yes ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ; yes ; yes ;
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; Total number of protected registers is 124 ; ; ;
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Register name ; Reason for Removal ;
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component|cntr_asi:auto_generated|counter_reg_bit[0..3] ; Lost fanout ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[16..28] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|first_in_ready ; Stuck at VCC due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[1..15] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[0] ; Stuck at VCC due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[29..31] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[16..28] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|first_in_ready ; Stuck at VCC due to stuck port data_in ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[1..15] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[0] ; Stuck at VCC due to stuck port data_in ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[29..31] ; Stuck at GND due to stuck port data_in ;
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; stm32_interface:STM32_INTERFACE|TX_CICFIR_GAIN[5..7] ; Lost fanout ;
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; stm32_interface:STM32_INTERFACE|CICFIR_GAIN[5..7] ; Lost fanout ;
|
|
; stm32_interface:STM32_INTERFACE|CIC_GAIN[7] ; Lost fanout ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst|count[0] ; Stuck at GND due to stuck port data_in ;
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|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst|count[0] ; Stuck at GND due to stuck port data_in ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_q[0] ; Merged with rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_q[0] ; Merged with rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[16,18] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[8,20,22] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[2] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[11,27] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[3] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[12,28,30] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[4] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[14,23,31] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[5] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[7,15,19] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[6] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[17,21] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[9] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[24,26] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[10] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[25,29] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[13] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[4,11,19] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[27] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[2] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[5,6,8] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[3] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[15,23,31] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[7] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[13,17,21] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[9] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[12,14,16] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[10] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[20,22,24] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[18] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[29] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[25] ;
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|
; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[28,30] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[26] ;
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|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[3,4,6,8,10,12,14,16,18,20,22,24,26,28,30,31] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[9,13,17,21,25,29] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[5] ;
|
|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[11,15,19,23,27] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[7] ;
|
|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[9,17,25] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[4,6,8,10,12,14,16,18,20,22,24,26,28,30] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[2] ;
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|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[7,11,15,19,23,27,31] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[3] ;
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|
; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[13,21,29] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[5] ;
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|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_q[0] ; Merged with rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[10] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[2] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[4] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[3] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[2,3,7] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[26] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[9] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[25] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[10] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[2] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[7] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[5] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[3] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[13] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[5] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[3] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[9] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[6] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[18] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[10] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[5] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[6] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[3] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[5] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[9,10] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[0..3] ; Lost fanout ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[0..3] ; Lost fanout ;
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; stm32_interface:STM32_INTERFACE|k[11..15] ; Merged with stm32_interface:STM32_INTERFACE|k[10] ;
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; spi_interface:FLASH|spi_stage[4,7] ; Merged with spi_interface:FLASH|spi_stage[3] ;
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; spi_interface:FLASH|spi_stage[6] ; Merged with spi_interface:FLASH|spi_stage[5] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[2] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_gated_reg_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_gated_reg_q[0] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[0] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[0] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[1] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[1] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[2] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[2] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[3] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[3] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[4] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[4] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[5] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[5] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[6] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[6] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[7] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[7] ;
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; tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[8] ; Merged with tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[8] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_eq ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_eq ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[0][0] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[2,3] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[1][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[1][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[1][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[1][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_q[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_q[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[1] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_enableQ[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_enableQ[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_eq ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_eq ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[0][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[0][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[1][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[1][0] ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[2][0] ; Merged with tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[2][0] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[0] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[0] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[1] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[1] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[2] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[2] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[3] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[3] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[4] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[4] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[5] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[5] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[6] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[6] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[7] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[7] ;
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; nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cs[8] ; Merged with nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008|rom_add_cc_temp[8] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst|count[0] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|dffe_af ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|sample_state[1] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|state[1] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst|count[0] ; Stuck at GND due to stuck port data_in ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|dffe_af ; Stuck at GND due to stuck port data_in ;
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; spi_interface:FLASH|spi_stage[3] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|dout[17..74] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|dout[16] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|dout[17..74] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|dout[16] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; stm32_interface:STM32_INTERFACE|k[10] ; Stuck at GND due to stuck port data_in ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|dout[17..73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|dout[17..73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|dout[18..73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|dout[18..73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.start ; Lost fanout ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost fanout ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.run1 ; Lost fanout ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.st_err ; Lost fanout ;
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; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ; Lost fanout ;
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; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.start ; Lost fanout ;
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; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost fanout ;
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; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.run1 ; Lost fanout ;
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; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.st_err ; Lost fanout ;
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; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.start ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.run1 ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.st_err ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.start ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.run1 ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.st_err ; Lost fanout ;
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; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ; Lost fanout ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|dout[20..74] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|dout[19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[2] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[2] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[1] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[1] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[0] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[0] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[3] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[3] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[4] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[4] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[5] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[5] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[6] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[6] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[7] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[7] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[8] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[8] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[9] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[9] ;
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; rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[10] ; Merged with rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[10] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|dout[20..74] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff|dout[19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[2] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[2] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[1] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[1] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[0] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[0] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[3] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[3] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[4] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[4] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[5] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[5] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[6] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[6] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[7] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[7] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[8] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[8] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[9] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[9] ;
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; rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[10] ; Merged with rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[10] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|dout[20..73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|dout[20..73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff|dout[74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
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|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|dout[21..73] ; Merged with tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|dout[74] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|dout[21..73] ; Merged with tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff|dout[74] ;
|
|
; Total Number of Removed Registers = 1680 ; ;
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Removed Registers Triggering Further Register Optimizations ;
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|first_in_ready ; Stuck at VCC ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[15], ;
|
|
; ; due to stuck port data_in ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[14], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[13], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[12], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[11], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[10], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[9], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[8], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[7], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[6], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[5], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[4], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[3], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[2], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[1], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[0], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[29], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[30], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[31] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|first_in_ready ; Stuck at VCC ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[15], ;
|
|
; ; due to stuck port data_in ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[14], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[13], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[12], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[11], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[10], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[9], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[8], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[7], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[6], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[5], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[4], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[3], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[2], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[1], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[0], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[29], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[30], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[31] ;
|
|
; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[28] ; Stuck at GND ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[1], ;
|
|
; ; due to stuck port data_in ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[0], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[2], ;
|
|
; ; ; tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[3] ;
|
|
; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|state[28] ; Stuck at GND ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[1], ;
|
|
; ; due to stuck port data_in ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[0], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[2], ;
|
|
; ; ; tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst|count[3] ;
|
|
; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost Fanouts ; rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ;
|
|
; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost Fanouts ; rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ;
|
|
; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost Fanouts ; tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ;
|
|
; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.stall ; Lost Fanouts ; tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state.end1 ;
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; 3:1 ; 72 bits ; 144 LEs ; 72 LEs ; 72 LEs ; Yes ; |WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk1|data_tmp[9] ;
|
|
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|I_HOLD[3] ;
|
|
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|I_HOLD[12] ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|fifo_usedw[1] ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|fifo_usedw[1] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|dout[37] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|dout[58] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|dout[82] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|dout[70] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|dout[19] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|dout[59] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|dout[37] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|dout[78] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|dout[28] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|dout[66] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|dout[21] ;
|
|
; 3:1 ; 86 bits ; 172 LEs ; 86 LEs ; 86 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|dout[46] ;
|
|
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|Q_HOLD[13] ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|fifo_rdreq ;
|
|
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|fifo_rdreq ;
|
|
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|dout_valid ;
|
|
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|dout_valid ;
|
|
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|word_counter[0] ;
|
|
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst|count[3] ;
|
|
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst|count[1] ;
|
|
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|rd_addr_ptr[2] ;
|
|
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|fifo_usedw[1] ;
|
|
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|rd_addr_ptr[0] ;
|
|
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|fifo_usedw[1] ;
|
|
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|wr_addr_ptr[0] ;
|
|
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO|wr_addr_ptr[0] ;
|
|
; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[3] ;
|
|
; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst|count[1] ;
|
|
; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[2] ;
|
|
; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst|count[10] ;
|
|
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |WOLF-LITE|spi_interface:FLASH|spi_stage[0] ;
|
|
; 5:1 ; 11 bits ; 33 LEs ; 22 LEs ; 11 LEs ; Yes ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst|shift_reg[2] ;
|
|
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |WOLF-LITE|spi_interface:FLASH|spi_bit_position[3] ;
|
|
; 5:1 ; 8 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|Q_HOLD[2] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 42 LEs ; 2 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[14] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_I[15] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 24 LEs ; 20 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[0] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 28 LEs ; 16 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[1] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 28 LEs ; 16 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[2] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 32 LEs ; 12 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[3] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[4] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[5] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_I[6] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[7] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[8] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[9] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[10] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_Q[11] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_I[12] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 42 LEs ; 2 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|REG_RX_I[13] ;
|
|
; 19:1 ; 2 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |WOLF-LITE|spi_interface:FLASH|spi_stage[5] ;
|
|
; 17:1 ; 4 bits ; 44 LEs ; 32 LEs ; 12 LEs ; Yes ; |WOLF-LITE|DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst|sld_rom_sr:\instance_id_gen:rom_info_inst|WORD_SR[0] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][0] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][1] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][2] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][3] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 120 LEs ; 52 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][4] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][5] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][6] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][7] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][8] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][9] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 118 LEs ; 54 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][10] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][11] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][12] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][13] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][14] ;
|
|
; 129:1 ; 2 bits ; 172 LEs ; 116 LEs ; 56 LEs ; Yes ; |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][15] ;
|
|
; 38:1 ; 9 bits ; 225 LEs ; 207 LEs ; 18 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|k[7] ;
|
|
; 5:1 ; 3 bits ; 9 LEs ; 3 LEs ; 6 LEs ; Yes ; |WOLF-LITE|spi_interface:FLASH|spi_bit_position[1] ;
|
|
; 12:1 ; 4 bits ; 32 LEs ; 24 LEs ; 8 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|DATA_BUS_OUT[5] ;
|
|
; 13:1 ; 2 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|DATA_BUS_OUT[3] ;
|
|
; 14:1 ; 2 bits ; 18 LEs ; 16 LEs ; 2 LEs ; Yes ; |WOLF-LITE|stm32_interface:STM32_INTERFACE|DATA_BUS_OUT[1] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 42 LEs ; 2 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[14] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[15] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 24 LEs ; 20 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[0] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 28 LEs ; 16 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[1] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 28 LEs ; 16 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[2] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 32 LEs ; 12 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[3] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[4] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_I[5] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_I[6] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_I[7] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 34 LEs ; 10 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[8] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 36 LEs ; 8 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[9] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[10] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_I[11] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 40 LEs ; 4 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_Q[12] ;
|
|
; 33:1 ; 2 bits ; 44 LEs ; 42 LEs ; 2 LEs ; No ; |WOLF-LITE|data_shifter:TX_CICCOMP_GAINER|data_out_I[13] ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
|
|
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; ON ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10037 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 113007 ; - ; - ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[0] ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
|
|
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; ON ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10037 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 113007 ; - ; - ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[0] ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
+-----------------+-------+------+--------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
|
|
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; ON ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10037 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 113007 ; - ; - ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[0] ;
|
|
+-----------------------------------------+--------+------+-----------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ;
|
|
+-----------------+-------+------+-------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------+-------+------+-------------------------------------------------------------------------------------------+
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
+-----------------+-------+------+-------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core ;
|
|
+-----------------------------------------+--------+------+----------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+-----------------------------------------+--------+------+----------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
|
|
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; ON ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10037 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 15400 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14130 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 10036 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12020 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12030 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12010 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 12110 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 14320 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
|
; MESSAGE_DISABLE ; 113007 ; - ; - ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count1_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_ra0_count0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_wi0_r0_wa0_i[0] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[5] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[4] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[3] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[2] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[1] ;
|
|
; PRESERVE_REGISTER ; on ; - ; u0_m0_wo0_ca0_i[0] ;
|
|
+-----------------------------------------+--------+------+----------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated ;
|
|
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Source assignments for DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst ;
|
|
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; NOT_GATE_PUSH_BACK ; OFF ; - ; - ;
|
|
; POWER_UP_LEVEL ; LOW ; - ; - ;
|
|
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
|
|
; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; hold_reg[0] ;
|
|
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component ;
|
|
+------------------------+--------------+----------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------+--------------+----------------------------------------------------------------+
|
|
; LPM_WIDTH ; 32 ; Signed Integer ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_DIRECTION ; ADD ; Untyped ;
|
|
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
|
|
; LPM_PIPELINE ; 1 ; Signed Integer ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; REGISTERED_AT_END ; 0 ; Untyped ;
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
|
; USE_CS_BUFFERS ; 1 ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; USE_WYS ; OFF ; Untyped ;
|
|
; STYLE ; FAST ; Untyped ;
|
|
; CBXI_PARAMETER ; add_sub_1vk ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
+------------------------+--------------+----------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_pll:TX_PLL|altpll:altpll_component ;
|
|
+-------------------------------+--------------------------+-------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------------------+--------------------------+-------------------------+
|
|
; OPERATION_MODE ; NORMAL ; Untyped ;
|
|
; PLL_TYPE ; AUTO ; Untyped ;
|
|
; LPM_HINT ; CBX_MODULE_PREFIX=tx_pll ; Untyped ;
|
|
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
|
|
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
|
|
; SCAN_CHAIN ; LONG ; Untyped ;
|
|
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
|
|
; INCLK0_INPUT_FREQUENCY ; 15547 ; Signed Integer ;
|
|
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
|
|
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
|
|
; LOCK_HIGH ; 1 ; Untyped ;
|
|
; LOCK_LOW ; 1 ; Untyped ;
|
|
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
|
|
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
|
|
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
|
|
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
|
|
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
|
|
; SKIP_VCO ; OFF ; Untyped ;
|
|
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
|
|
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
|
|
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
|
|
; BANDWIDTH ; 0 ; Untyped ;
|
|
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
|
|
; SPREAD_FREQUENCY ; 0 ; Untyped ;
|
|
; DOWN_SPREAD ; 0 ; Untyped ;
|
|
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
|
|
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
|
|
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK0_MULTIPLY_BY ; 5 ; Signed Integer ;
|
|
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK1_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK0_DIVIDE_BY ; 2 ; Signed Integer ;
|
|
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK5_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK4_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK3_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK2_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK1_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK0_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
|
|
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
|
|
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
|
|
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
|
|
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
|
|
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; DPA_DIVIDE_BY ; 1 ; Untyped ;
|
|
; DPA_DIVIDER ; 0 ; Untyped ;
|
|
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; VCO_DIVIDE_BY ; 0 ; Untyped ;
|
|
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; VCO_MIN ; 0 ; Untyped ;
|
|
; VCO_MAX ; 0 ; Untyped ;
|
|
; VCO_CENTER ; 0 ; Untyped ;
|
|
; PFD_MIN ; 0 ; Untyped ;
|
|
; PFD_MAX ; 0 ; Untyped ;
|
|
; M_INITIAL ; 0 ; Untyped ;
|
|
; M ; 0 ; Untyped ;
|
|
; N ; 1 ; Untyped ;
|
|
; M2 ; 1 ; Untyped ;
|
|
; N2 ; 1 ; Untyped ;
|
|
; SS ; 1 ; Untyped ;
|
|
; C0_HIGH ; 0 ; Untyped ;
|
|
; C1_HIGH ; 0 ; Untyped ;
|
|
; C2_HIGH ; 0 ; Untyped ;
|
|
; C3_HIGH ; 0 ; Untyped ;
|
|
; C4_HIGH ; 0 ; Untyped ;
|
|
; C5_HIGH ; 0 ; Untyped ;
|
|
; C6_HIGH ; 0 ; Untyped ;
|
|
; C7_HIGH ; 0 ; Untyped ;
|
|
; C8_HIGH ; 0 ; Untyped ;
|
|
; C9_HIGH ; 0 ; Untyped ;
|
|
; C0_LOW ; 0 ; Untyped ;
|
|
; C1_LOW ; 0 ; Untyped ;
|
|
; C2_LOW ; 0 ; Untyped ;
|
|
; C3_LOW ; 0 ; Untyped ;
|
|
; C4_LOW ; 0 ; Untyped ;
|
|
; C5_LOW ; 0 ; Untyped ;
|
|
; C6_LOW ; 0 ; Untyped ;
|
|
; C7_LOW ; 0 ; Untyped ;
|
|
; C8_LOW ; 0 ; Untyped ;
|
|
; C9_LOW ; 0 ; Untyped ;
|
|
; C0_INITIAL ; 0 ; Untyped ;
|
|
; C1_INITIAL ; 0 ; Untyped ;
|
|
; C2_INITIAL ; 0 ; Untyped ;
|
|
; C3_INITIAL ; 0 ; Untyped ;
|
|
; C4_INITIAL ; 0 ; Untyped ;
|
|
; C5_INITIAL ; 0 ; Untyped ;
|
|
; C6_INITIAL ; 0 ; Untyped ;
|
|
; C7_INITIAL ; 0 ; Untyped ;
|
|
; C8_INITIAL ; 0 ; Untyped ;
|
|
; C9_INITIAL ; 0 ; Untyped ;
|
|
; C0_MODE ; BYPASS ; Untyped ;
|
|
; C1_MODE ; BYPASS ; Untyped ;
|
|
; C2_MODE ; BYPASS ; Untyped ;
|
|
; C3_MODE ; BYPASS ; Untyped ;
|
|
; C4_MODE ; BYPASS ; Untyped ;
|
|
; C5_MODE ; BYPASS ; Untyped ;
|
|
; C6_MODE ; BYPASS ; Untyped ;
|
|
; C7_MODE ; BYPASS ; Untyped ;
|
|
; C8_MODE ; BYPASS ; Untyped ;
|
|
; C9_MODE ; BYPASS ; Untyped ;
|
|
; C0_PH ; 0 ; Untyped ;
|
|
; C1_PH ; 0 ; Untyped ;
|
|
; C2_PH ; 0 ; Untyped ;
|
|
; C3_PH ; 0 ; Untyped ;
|
|
; C4_PH ; 0 ; Untyped ;
|
|
; C5_PH ; 0 ; Untyped ;
|
|
; C6_PH ; 0 ; Untyped ;
|
|
; C7_PH ; 0 ; Untyped ;
|
|
; C8_PH ; 0 ; Untyped ;
|
|
; C9_PH ; 0 ; Untyped ;
|
|
; L0_HIGH ; 1 ; Untyped ;
|
|
; L1_HIGH ; 1 ; Untyped ;
|
|
; G0_HIGH ; 1 ; Untyped ;
|
|
; G1_HIGH ; 1 ; Untyped ;
|
|
; G2_HIGH ; 1 ; Untyped ;
|
|
; G3_HIGH ; 1 ; Untyped ;
|
|
; E0_HIGH ; 1 ; Untyped ;
|
|
; E1_HIGH ; 1 ; Untyped ;
|
|
; E2_HIGH ; 1 ; Untyped ;
|
|
; E3_HIGH ; 1 ; Untyped ;
|
|
; L0_LOW ; 1 ; Untyped ;
|
|
; L1_LOW ; 1 ; Untyped ;
|
|
; G0_LOW ; 1 ; Untyped ;
|
|
; G1_LOW ; 1 ; Untyped ;
|
|
; G2_LOW ; 1 ; Untyped ;
|
|
; G3_LOW ; 1 ; Untyped ;
|
|
; E0_LOW ; 1 ; Untyped ;
|
|
; E1_LOW ; 1 ; Untyped ;
|
|
; E2_LOW ; 1 ; Untyped ;
|
|
; E3_LOW ; 1 ; Untyped ;
|
|
; L0_INITIAL ; 1 ; Untyped ;
|
|
; L1_INITIAL ; 1 ; Untyped ;
|
|
; G0_INITIAL ; 1 ; Untyped ;
|
|
; G1_INITIAL ; 1 ; Untyped ;
|
|
; G2_INITIAL ; 1 ; Untyped ;
|
|
; G3_INITIAL ; 1 ; Untyped ;
|
|
; E0_INITIAL ; 1 ; Untyped ;
|
|
; E1_INITIAL ; 1 ; Untyped ;
|
|
; E2_INITIAL ; 1 ; Untyped ;
|
|
; E3_INITIAL ; 1 ; Untyped ;
|
|
; L0_MODE ; BYPASS ; Untyped ;
|
|
; L1_MODE ; BYPASS ; Untyped ;
|
|
; G0_MODE ; BYPASS ; Untyped ;
|
|
; G1_MODE ; BYPASS ; Untyped ;
|
|
; G2_MODE ; BYPASS ; Untyped ;
|
|
; G3_MODE ; BYPASS ; Untyped ;
|
|
; E0_MODE ; BYPASS ; Untyped ;
|
|
; E1_MODE ; BYPASS ; Untyped ;
|
|
; E2_MODE ; BYPASS ; Untyped ;
|
|
; E3_MODE ; BYPASS ; Untyped ;
|
|
; L0_PH ; 0 ; Untyped ;
|
|
; L1_PH ; 0 ; Untyped ;
|
|
; G0_PH ; 0 ; Untyped ;
|
|
; G1_PH ; 0 ; Untyped ;
|
|
; G2_PH ; 0 ; Untyped ;
|
|
; G3_PH ; 0 ; Untyped ;
|
|
; E0_PH ; 0 ; Untyped ;
|
|
; E1_PH ; 0 ; Untyped ;
|
|
; E2_PH ; 0 ; Untyped ;
|
|
; E3_PH ; 0 ; Untyped ;
|
|
; M_PH ; 0 ; Untyped ;
|
|
; C1_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C2_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C3_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C4_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C5_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C6_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C7_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C8_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C9_USE_CASC_IN ; OFF ; Untyped ;
|
|
; CLK0_COUNTER ; G0 ; Untyped ;
|
|
; CLK1_COUNTER ; G0 ; Untyped ;
|
|
; CLK2_COUNTER ; G0 ; Untyped ;
|
|
; CLK3_COUNTER ; G0 ; Untyped ;
|
|
; CLK4_COUNTER ; G0 ; Untyped ;
|
|
; CLK5_COUNTER ; G0 ; Untyped ;
|
|
; CLK6_COUNTER ; E0 ; Untyped ;
|
|
; CLK7_COUNTER ; E1 ; Untyped ;
|
|
; CLK8_COUNTER ; E2 ; Untyped ;
|
|
; CLK9_COUNTER ; E3 ; Untyped ;
|
|
; L0_TIME_DELAY ; 0 ; Untyped ;
|
|
; L1_TIME_DELAY ; 0 ; Untyped ;
|
|
; G0_TIME_DELAY ; 0 ; Untyped ;
|
|
; G1_TIME_DELAY ; 0 ; Untyped ;
|
|
; G2_TIME_DELAY ; 0 ; Untyped ;
|
|
; G3_TIME_DELAY ; 0 ; Untyped ;
|
|
; E0_TIME_DELAY ; 0 ; Untyped ;
|
|
; E1_TIME_DELAY ; 0 ; Untyped ;
|
|
; E2_TIME_DELAY ; 0 ; Untyped ;
|
|
; E3_TIME_DELAY ; 0 ; Untyped ;
|
|
; M_TIME_DELAY ; 0 ; Untyped ;
|
|
; N_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK3_COUNTER ; E3 ; Untyped ;
|
|
; EXTCLK2_COUNTER ; E2 ; Untyped ;
|
|
; EXTCLK1_COUNTER ; E1 ; Untyped ;
|
|
; EXTCLK0_COUNTER ; E0 ; Untyped ;
|
|
; ENABLE0_COUNTER ; L0 ; Untyped ;
|
|
; ENABLE1_COUNTER ; L0 ; Untyped ;
|
|
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
|
|
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
|
|
; LOOP_FILTER_C ; 5 ; Untyped ;
|
|
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
|
|
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
|
|
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
|
|
; VCO_POST_SCALE ; 0 ; Untyped ;
|
|
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK0 ; PORT_USED ; Untyped ;
|
|
; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
|
|
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_INCLK0 ; PORT_USED ; Untyped ;
|
|
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
|
|
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
|
|
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
|
|
; M_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C0_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C1_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C2_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C3_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C4_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C5_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C6_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C7_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C8_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C9_TEST_SOURCE ; 5 ; Untyped ;
|
|
; CBXI_PARAMETER ; tx_pll_altpll ; Untyped ;
|
|
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
|
|
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
|
|
; WIDTH_CLOCK ; 5 ; Signed Integer ;
|
|
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
|
|
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
|
|
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
+-------------------------------+--------------------------+-------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 32 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Untyped ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 1 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 9 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_abt ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0 ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; FILTER_TYPE ; interpolator ; String ;
|
|
; STAGES ; 6 ; Signed Integer ;
|
|
; D_DELAY ; 1 ; Signed Integer ;
|
|
; VRC_EN ; 0 ; Signed Integer ;
|
|
; RCF_MAX ; 3350 ; Signed Integer ;
|
|
; RCF_MIN ; 3350 ; Signed Integer ;
|
|
; INTERFACES ; 1 ; Signed Integer ;
|
|
; CH_PER_INT ; 1 ; Signed Integer ;
|
|
; INT_USE_MEM ; false ; String ;
|
|
; INT_MEM ; auto ; String ;
|
|
; DIF_USE_MEM ; false ; String ;
|
|
; DIF_MEM ; auto ; String ;
|
|
; IN_WIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH ; 16 ; Signed Integer ;
|
|
; ROUND_TYPE ; TRUNCATE ; String ;
|
|
; PIPELINING ; 0 ; Signed Integer ;
|
|
; C_STAGE_0_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_1_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_2_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_3_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_4_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_5_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_6_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_7_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_8_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_9_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_10_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_11_WIDTH ; 75 ; Signed Integer ;
|
|
; MAX_C_STAGE_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_0_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_1_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_2_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_3_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_4_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_5_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_6_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_7_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_8_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_9_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_10_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_11_WIDTH ; 75 ; Signed Integer ;
|
|
; MAX_I_STAGE_WIDTH ; 75 ; Signed Integer ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: data_shifter:TX_CICCOMP_GAINER ;
|
|
+----------------+-------+----------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+----------------------------------------------------+
|
|
; in_width ; 30 ; Signed Integer ;
|
|
; out_width ; 16 ; Signed Integer ;
|
|
+----------------+-------+----------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; INWIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH_UNTRIMMED ; 30 ; Signed Integer ;
|
|
; BANKINWIDTH ; 0 ; Signed Integer ;
|
|
; REM_LSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_LSB_TYPE_g ; trunc ; String ;
|
|
; REM_MSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_MSB_TYPE_g ; trunc ; String ;
|
|
; PHYSCHANIN ; 1 ; Signed Integer ;
|
|
; PHYSCHANOUT ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYIN ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; OUTPUTFIFODEPTH ; 4 ; Signed Integer ;
|
|
; USE_PACKETS ; 0 ; Signed Integer ;
|
|
; MODE_WIDTH ; 0 ; Signed Integer ;
|
|
; ENABLE_BACKPRESSURE ; false ; Enumerated ;
|
|
; LOG2_CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; NUMCHANS ; 1 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; COMPLEX_CONST ; 1 ; Signed Integer ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 16 ; Signed Integer ;
|
|
; data_width ; 16 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 30 ; Signed Integer ;
|
|
; data_width ; 30 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
; fifo_depth_g ; 4 ; Signed Integer ;
|
|
; have_counter_g ; false ; Enumerated ;
|
|
; counter_limit_g ; 1 ; Signed Integer ;
|
|
; use_packets ; 0 ; Signed Integer ;
|
|
; enable_backpressure_g ; false ; Enumerated ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 16 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
|
|
; WIDTH_A ; 16 ; Signed Integer ;
|
|
; WIDTHAD_A ; 6 ; Signed Integer ;
|
|
; NUMWORDS_A ; 64 ; Signed Integer ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 16 ; Signed Integer ;
|
|
; WIDTHAD_B ; 6 ; Signed Integer ;
|
|
; NUMWORDS_B ; 64 ; Signed Integer ;
|
|
; INDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK0 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; OUTDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK0 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Signed Integer ;
|
|
; RAM_BLOCK_TYPE ; M9K ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Signed Integer ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; UNUSED ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Signed Integer ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_0mn3 ; Untyped ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 8 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Signed Integer ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 2 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_ncu ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16 ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 24 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 19 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; in_width_g ; 30 ; Signed Integer ;
|
|
; rem_lsb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_lsb_type_g ; trunc ; String ;
|
|
; rem_msb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_msb_type_g ; trunc ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; INWIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH_UNTRIMMED ; 30 ; Signed Integer ;
|
|
; BANKINWIDTH ; 0 ; Signed Integer ;
|
|
; REM_LSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_LSB_TYPE_g ; trunc ; String ;
|
|
; REM_MSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_MSB_TYPE_g ; trunc ; String ;
|
|
; PHYSCHANIN ; 1 ; Signed Integer ;
|
|
; PHYSCHANOUT ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYIN ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; OUTPUTFIFODEPTH ; 4 ; Signed Integer ;
|
|
; USE_PACKETS ; 0 ; Signed Integer ;
|
|
; MODE_WIDTH ; 0 ; Signed Integer ;
|
|
; ENABLE_BACKPRESSURE ; false ; Enumerated ;
|
|
; LOG2_CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; NUMCHANS ; 1 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; COMPLEX_CONST ; 1 ; Signed Integer ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 16 ; Signed Integer ;
|
|
; data_width ; 16 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 30 ; Signed Integer ;
|
|
; data_width ; 30 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
; fifo_depth_g ; 4 ; Signed Integer ;
|
|
; have_counter_g ; false ; Enumerated ;
|
|
; counter_limit_g ; 1 ; Signed Integer ;
|
|
; use_packets ; 0 ; Signed Integer ;
|
|
; enable_backpressure_g ; false ; Enumerated ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 16 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
|
|
; WIDTH_A ; 16 ; Signed Integer ;
|
|
; WIDTHAD_A ; 6 ; Signed Integer ;
|
|
; NUMWORDS_A ; 64 ; Signed Integer ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 16 ; Signed Integer ;
|
|
; WIDTHAD_B ; 6 ; Signed Integer ;
|
|
; NUMWORDS_B ; 64 ; Signed Integer ;
|
|
; INDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK0 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; OUTDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK0 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Signed Integer ;
|
|
; RAM_BLOCK_TYPE ; M9K ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Signed Integer ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; UNUSED ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Signed Integer ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_0mn3 ; Untyped ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 8 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Signed Integer ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 2 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_ncu ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16 ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 24 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 19 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; in_width_g ; 30 ; Signed Integer ;
|
|
; rem_lsb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_lsb_type_g ; trunc ; String ;
|
|
; rem_msb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_msb_type_g ; trunc ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0 ;
|
|
+----------------+---------------------------+----------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+---------------------------+----------------------------------------+
|
|
; mpr ; 16 ; Signed Integer ;
|
|
; opr ; 32 ; Signed Integer ;
|
|
; apr ; 22 ; Signed Integer ;
|
|
; apri ; 22 ; Signed Integer ;
|
|
; aprf ; 32 ; Signed Integer ;
|
|
; aprp ; 16 ; Signed Integer ;
|
|
; aprid ; 27 ; Signed Integer ;
|
|
; dpri ; 4 ; Signed Integer ;
|
|
; rdw ; 16 ; Signed Integer ;
|
|
; rawc ; 11 ; Signed Integer ;
|
|
; rnwc ; 2048 ; Signed Integer ;
|
|
; rawf ; 11 ; Signed Integer ;
|
|
; rnwf ; 2048 ; Signed Integer ;
|
|
; Pn ; 1048576 ; Signed Integer ;
|
|
; mxnbc ; 32768 ; Signed Integer ;
|
|
; mxnbf ; 32768 ; Signed Integer ;
|
|
; rsfc ; tx_nco_nco_ii_0_sin_c.hex ; String ;
|
|
; rsff ; tx_nco_nco_ii_0_sin_f.hex ; String ;
|
|
; rcfc ; tx_nco_nco_ii_0_cos_c.hex ; String ;
|
|
; rcff ; tx_nco_nco_ii_0_cos_f.hex ; String ;
|
|
; nc ; 1 ; Signed Integer ;
|
|
; log2nc ; 0 ; Signed Integer ;
|
|
; outselinit ; 0 ; Signed Integer ;
|
|
; paci0 ; 0 ; Signed Integer ;
|
|
; paci1 ; 0 ; Signed Integer ;
|
|
; paci2 ; 0 ; Signed Integer ;
|
|
; paci3 ; 0 ; Signed Integer ;
|
|
; paci4 ; 0 ; Signed Integer ;
|
|
; paci5 ; 0 ; Signed Integer ;
|
|
; paci6 ; 0 ; Signed Integer ;
|
|
; paci7 ; 0 ; Signed Integer ;
|
|
; hyper_pipeline ; 0 ; Signed Integer ;
|
|
+----------------+---------------------------+----------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_mixer:TX_MIXER_Q|lpm_mult:lpm_mult_component ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 32 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Untyped ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 1 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 9 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_abt ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0 ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; FILTER_TYPE ; interpolator ; String ;
|
|
; STAGES ; 6 ; Signed Integer ;
|
|
; D_DELAY ; 1 ; Signed Integer ;
|
|
; VRC_EN ; 0 ; Signed Integer ;
|
|
; RCF_MAX ; 3350 ; Signed Integer ;
|
|
; RCF_MIN ; 3350 ; Signed Integer ;
|
|
; INTERFACES ; 1 ; Signed Integer ;
|
|
; CH_PER_INT ; 1 ; Signed Integer ;
|
|
; INT_USE_MEM ; false ; String ;
|
|
; INT_MEM ; auto ; String ;
|
|
; DIF_USE_MEM ; false ; String ;
|
|
; DIF_MEM ; auto ; String ;
|
|
; IN_WIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH ; 16 ; Signed Integer ;
|
|
; ROUND_TYPE ; TRUNCATE ; String ;
|
|
; PIPELINING ; 0 ; Signed Integer ;
|
|
; C_STAGE_0_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_1_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_2_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_3_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_4_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_5_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_6_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_7_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_8_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_9_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_10_WIDTH ; 75 ; Signed Integer ;
|
|
; C_STAGE_11_WIDTH ; 75 ; Signed Integer ;
|
|
; MAX_C_STAGE_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_0_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_1_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_2_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_3_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_4_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_5_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_6_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_7_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_8_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_9_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_10_WIDTH ; 75 ; Signed Integer ;
|
|
; I_STAGE_11_WIDTH ; 75 ; Signed Integer ;
|
|
; MAX_I_STAGE_WIDTH ; 75 ; Signed Integer ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: data_shifter:RX_CICFIR_GAINER ;
|
|
+----------------+-------+---------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------+
|
|
; in_width ; 30 ; Signed Integer ;
|
|
; out_width ; 16 ; Signed Integer ;
|
|
+----------------+-------+---------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
; INWIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH_UNTRIMMED ; 30 ; Signed Integer ;
|
|
; BANKINWIDTH ; 0 ; Signed Integer ;
|
|
; REM_LSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_LSB_TYPE_g ; round ; String ;
|
|
; REM_MSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_MSB_TYPE_g ; trunc ; String ;
|
|
; PHYSCHANIN ; 1 ; Signed Integer ;
|
|
; PHYSCHANOUT ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYIN ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; OUTPUTFIFODEPTH ; 4 ; Signed Integer ;
|
|
; USE_PACKETS ; 0 ; Signed Integer ;
|
|
; MODE_WIDTH ; 0 ; Signed Integer ;
|
|
; ENABLE_BACKPRESSURE ; false ; Enumerated ;
|
|
; LOG2_CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; NUMCHANS ; 1 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; COMPLEX_CONST ; 1 ; Signed Integer ;
|
|
+---------------------+--------------+--------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 16 ; Signed Integer ;
|
|
; data_width ; 16 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
+-----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 30 ; Signed Integer ;
|
|
; data_width ; 30 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
; fifo_depth_g ; 4 ; Signed Integer ;
|
|
; have_counter_g ; false ; Enumerated ;
|
|
; counter_limit_g ; 1 ; Signed Integer ;
|
|
; use_packets ; 0 ; Signed Integer ;
|
|
; enable_backpressure_g ; false ; Enumerated ;
|
|
+-----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 16 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
|
|
; WIDTH_A ; 16 ; Signed Integer ;
|
|
; WIDTHAD_A ; 6 ; Signed Integer ;
|
|
; NUMWORDS_A ; 64 ; Signed Integer ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 16 ; Signed Integer ;
|
|
; WIDTHAD_B ; 6 ; Signed Integer ;
|
|
; NUMWORDS_B ; 64 ; Signed Integer ;
|
|
; INDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK0 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; OUTDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK0 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Signed Integer ;
|
|
; RAM_BLOCK_TYPE ; M9K ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Signed Integer ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; UNUSED ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Signed Integer ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_0mn3 ; Untyped ;
|
|
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 8 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Signed Integer ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 2 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_ncu ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; in_width_g ; 30 ; Signed Integer ;
|
|
; rem_lsb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_lsb_type_g ; round ; String ;
|
|
; rem_msb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_msb_type_g ; trunc ; String ;
|
|
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: data_shifter:CIC_GAINER ;
|
|
+----------------+-------+---------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+---------------------------------------------+
|
|
; in_width ; 86 ; Signed Integer ;
|
|
; out_width ; 16 ; Signed Integer ;
|
|
+----------------+-------+---------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0 ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; FILTER_TYPE ; decimator ; String ;
|
|
; STAGES ; 6 ; Signed Integer ;
|
|
; D_DELAY ; 1 ; Signed Integer ;
|
|
; VRC_EN ; 0 ; Signed Integer ;
|
|
; RCF_MAX ; 1340 ; Signed Integer ;
|
|
; RCF_MIN ; 1340 ; Signed Integer ;
|
|
; INTERFACES ; 1 ; Signed Integer ;
|
|
; CH_PER_INT ; 1 ; Signed Integer ;
|
|
; INT_USE_MEM ; false ; String ;
|
|
; INT_MEM ; auto ; String ;
|
|
; DIF_USE_MEM ; false ; String ;
|
|
; DIF_MEM ; auto ; String ;
|
|
; IN_WIDTH ; 23 ; Signed Integer ;
|
|
; OUT_WIDTH ; 86 ; Signed Integer ;
|
|
; ROUND_TYPE ; NONE ; String ;
|
|
; PIPELINING ; 0 ; Signed Integer ;
|
|
; C_STAGE_0_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_1_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_2_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_3_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_4_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_5_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_6_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_7_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_8_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_9_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_10_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_11_WIDTH ; 86 ; Signed Integer ;
|
|
; MAX_C_STAGE_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_0_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_1_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_2_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_3_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_4_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_5_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_6_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_7_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_8_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_9_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_10_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_11_WIDTH ; 86 ; Signed Integer ;
|
|
; MAX_I_STAGE_WIDTH ; 86 ; Signed Integer ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: nco:RX_NCO|nco_nco_ii_0:nco_ii_0 ;
|
|
+----------------+------------------------+-------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+------------------------+-------------------------------------+
|
|
; mpr ; 12 ; Signed Integer ;
|
|
; opr ; 24 ; Signed Integer ;
|
|
; apr ; 22 ; Signed Integer ;
|
|
; apri ; 22 ; Signed Integer ;
|
|
; aprf ; 32 ; Signed Integer ;
|
|
; aprp ; 16 ; Signed Integer ;
|
|
; aprid ; 27 ; Signed Integer ;
|
|
; dpri ; 10 ; Signed Integer ;
|
|
; rdw ; 12 ; Signed Integer ;
|
|
; rawc ; 11 ; Signed Integer ;
|
|
; rnwc ; 2048 ; Signed Integer ;
|
|
; rawf ; 11 ; Signed Integer ;
|
|
; rnwf ; 2048 ; Signed Integer ;
|
|
; Pn ; 1048576 ; Signed Integer ;
|
|
; mxnbc ; 24576 ; Signed Integer ;
|
|
; mxnbf ; 24576 ; Signed Integer ;
|
|
; rsfc ; nco_nco_ii_0_sin_c.hex ; String ;
|
|
; rsff ; nco_nco_ii_0_sin_f.hex ; String ;
|
|
; rcfc ; nco_nco_ii_0_cos_c.hex ; String ;
|
|
; rcff ; nco_nco_ii_0_cos_f.hex ; String ;
|
|
; nc ; 1 ; Signed Integer ;
|
|
; log2nc ; 0 ; Signed Integer ;
|
|
; outselinit ; 0 ; Signed Integer ;
|
|
; paci0 ; 0 ; Signed Integer ;
|
|
; paci1 ; 0 ; Signed Integer ;
|
|
; paci2 ; 0 ; Signed Integer ;
|
|
; paci3 ; 0 ; Signed Integer ;
|
|
; paci4 ; 0 ; Signed Integer ;
|
|
; paci5 ; 0 ; Signed Integer ;
|
|
; paci6 ; 0 ; Signed Integer ;
|
|
; paci7 ; 0 ; Signed Integer ;
|
|
; hyper_pipeline ; 0 ; Signed Integer ;
|
|
+----------------+------------------------+-------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: mixer:RX_MIXER_I|lpm_mult:lpm_mult_component ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 12 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 12 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Untyped ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 1 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_jnp ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0 ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; FILTER_TYPE ; decimator ; String ;
|
|
; STAGES ; 6 ; Signed Integer ;
|
|
; D_DELAY ; 1 ; Signed Integer ;
|
|
; VRC_EN ; 0 ; Signed Integer ;
|
|
; RCF_MAX ; 1340 ; Signed Integer ;
|
|
; RCF_MIN ; 1340 ; Signed Integer ;
|
|
; INTERFACES ; 1 ; Signed Integer ;
|
|
; CH_PER_INT ; 1 ; Signed Integer ;
|
|
; INT_USE_MEM ; false ; String ;
|
|
; INT_MEM ; auto ; String ;
|
|
; DIF_USE_MEM ; false ; String ;
|
|
; DIF_MEM ; auto ; String ;
|
|
; IN_WIDTH ; 23 ; Signed Integer ;
|
|
; OUT_WIDTH ; 86 ; Signed Integer ;
|
|
; ROUND_TYPE ; NONE ; String ;
|
|
; PIPELINING ; 0 ; Signed Integer ;
|
|
; C_STAGE_0_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_1_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_2_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_3_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_4_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_5_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_6_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_7_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_8_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_9_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_10_WIDTH ; 86 ; Signed Integer ;
|
|
; C_STAGE_11_WIDTH ; 86 ; Signed Integer ;
|
|
; MAX_C_STAGE_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_0_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_1_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_2_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_3_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_4_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_5_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_6_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_7_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_8_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_9_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_10_WIDTH ; 86 ; Signed Integer ;
|
|
; I_STAGE_11_WIDTH ; 86 ; Signed Integer ;
|
|
; MAX_I_STAGE_WIDTH ; 86 ; Signed Integer ;
|
|
+-------------------+--------------+----------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: mixer:RX_MIXER_Q|lpm_mult:lpm_mult_component ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 12 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 12 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Untyped ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 1 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_jnp ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+---------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst ;
|
|
+---------------------+--------------+-------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+---------------------+--------------+-------------------------------------------------------------------------------------------------------------+
|
|
; INWIDTH ; 16 ; Signed Integer ;
|
|
; OUT_WIDTH_UNTRIMMED ; 30 ; Signed Integer ;
|
|
; BANKINWIDTH ; 0 ; Signed Integer ;
|
|
; REM_LSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_LSB_TYPE_g ; round ; String ;
|
|
; REM_MSB_BIT_g ; 0 ; Signed Integer ;
|
|
; REM_MSB_TYPE_g ; trunc ; String ;
|
|
; PHYSCHANIN ; 1 ; Signed Integer ;
|
|
; PHYSCHANOUT ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYIN ; 1 ; Signed Integer ;
|
|
; CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; OUTPUTFIFODEPTH ; 4 ; Signed Integer ;
|
|
; USE_PACKETS ; 0 ; Signed Integer ;
|
|
; MODE_WIDTH ; 0 ; Signed Integer ;
|
|
; ENABLE_BACKPRESSURE ; false ; Enumerated ;
|
|
; LOG2_CHANSPERPHYOUT ; 1 ; Signed Integer ;
|
|
; NUMCHANS ; 1 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; String ;
|
|
; COMPLEX_CONST ; 1 ; Signed Integer ;
|
|
+---------------------+--------------+-------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink ;
|
|
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 16 ; Signed Integer ;
|
|
; data_width ; 16 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source ;
|
|
+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width_g ; 30 ; Signed Integer ;
|
|
; data_width ; 30 ; Signed Integer ;
|
|
; data_port_count ; 1 ; Signed Integer ;
|
|
; packet_size_g ; 1 ; Signed Integer ;
|
|
; fifo_depth_g ; 4 ; Signed Integer ;
|
|
; have_counter_g ; false ; Enumerated ;
|
|
; counter_limit_g ; 1 ; Signed Integer ;
|
|
; use_packets ; 0 ; Signed Integer ;
|
|
; enable_backpressure_g ; false ; Enumerated ;
|
|
+-----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14 ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 2 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15 ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 1 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13 ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 16 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; width ; 1 ; Signed Integer ;
|
|
; depth ; 3 ; Signed Integer ;
|
|
; reset_high ; '1' ; Enumerated ;
|
|
; reset_kind ; ASYNC ; String ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem ;
|
|
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
|
|
; WIDTH_A ; 16 ; Signed Integer ;
|
|
; WIDTHAD_A ; 6 ; Signed Integer ;
|
|
; NUMWORDS_A ; 64 ; Signed Integer ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 16 ; Signed Integer ;
|
|
; WIDTHAD_B ; 6 ; Signed Integer ;
|
|
; NUMWORDS_B ; 64 ; Signed Integer ;
|
|
; INDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK0 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; OUTDATA_REG_B ; CLOCK0 ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK0 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Signed Integer ;
|
|
; RAM_BLOCK_TYPE ; M9K ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Signed Integer ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; UNUSED ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Signed Integer ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Signed Integer ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_0mn3 ; Untyped ;
|
|
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component ;
|
|
+------------------------------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTHA ; 8 ; Signed Integer ;
|
|
; LPM_WIDTHB ; 16 ; Signed Integer ;
|
|
; LPM_WIDTHP ; 24 ; Signed Integer ;
|
|
; LPM_WIDTHR ; 0 ; Untyped ;
|
|
; LPM_WIDTHS ; 1 ; Signed Integer ;
|
|
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
|
|
; LPM_PIPELINE ; 2 ; Signed Integer ;
|
|
; LATENCY ; 0 ; Untyped ;
|
|
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
|
|
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
|
|
; USE_EAB ; OFF ; Untyped ;
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
|
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
|
|
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mult_ncu ; Untyped ;
|
|
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
|
|
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
|
|
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
|
|
+------------------------------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; in_width_g ; 30 ; Signed Integer ;
|
|
; rem_lsb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_lsb_type_g ; round ; String ;
|
|
; rem_msb_bit_g ; 0 ; Signed Integer ;
|
|
; rem_msb_type_g ; trunc ; String ;
|
|
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: MAIN_PLL:MAIN_PLL|altpll:altpll_component ;
|
|
+-------------------------------+----------------------------+---------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------------------+----------------------------+---------------------------+
|
|
; OPERATION_MODE ; NORMAL ; Untyped ;
|
|
; PLL_TYPE ; AUTO ; Untyped ;
|
|
; LPM_HINT ; CBX_MODULE_PREFIX=MAIN_PLL ; Untyped ;
|
|
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
|
|
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
|
|
; SCAN_CHAIN ; LONG ; Untyped ;
|
|
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
|
|
; INCLK0_INPUT_FREQUENCY ; 15547 ; Signed Integer ;
|
|
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
|
|
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
|
|
; LOCK_HIGH ; 1 ; Untyped ;
|
|
; LOCK_LOW ; 1 ; Untyped ;
|
|
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
|
|
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
|
|
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
|
|
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
|
|
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
|
|
; SKIP_VCO ; OFF ; Untyped ;
|
|
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
|
|
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
|
|
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
|
|
; BANDWIDTH ; 0 ; Untyped ;
|
|
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
|
|
; SPREAD_FREQUENCY ; 0 ; Untyped ;
|
|
; DOWN_SPREAD ; 0 ; Untyped ;
|
|
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
|
|
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
|
|
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; CLK1_MULTIPLY_BY ; 1 ; Signed Integer ;
|
|
; CLK0_MULTIPLY_BY ; 64 ; Signed Integer ;
|
|
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
|
|
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
|
|
; CLK1_DIVIDE_BY ; 1340 ; Signed Integer ;
|
|
; CLK0_DIVIDE_BY ; 335 ; Signed Integer ;
|
|
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; CLK5_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK4_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK3_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK2_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK1_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK0_TIME_DELAY ; 0 ; Untyped ;
|
|
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
|
|
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
|
|
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
|
|
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
|
|
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
|
|
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
|
|
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
|
|
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
|
|
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; DPA_DIVIDE_BY ; 1 ; Untyped ;
|
|
; DPA_DIVIDER ; 0 ; Untyped ;
|
|
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
|
|
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
|
|
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
|
|
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
|
|
; VCO_DIVIDE_BY ; 0 ; Untyped ;
|
|
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
|
|
; VCO_MIN ; 0 ; Untyped ;
|
|
; VCO_MAX ; 0 ; Untyped ;
|
|
; VCO_CENTER ; 0 ; Untyped ;
|
|
; PFD_MIN ; 0 ; Untyped ;
|
|
; PFD_MAX ; 0 ; Untyped ;
|
|
; M_INITIAL ; 0 ; Untyped ;
|
|
; M ; 0 ; Untyped ;
|
|
; N ; 1 ; Untyped ;
|
|
; M2 ; 1 ; Untyped ;
|
|
; N2 ; 1 ; Untyped ;
|
|
; SS ; 1 ; Untyped ;
|
|
; C0_HIGH ; 0 ; Untyped ;
|
|
; C1_HIGH ; 0 ; Untyped ;
|
|
; C2_HIGH ; 0 ; Untyped ;
|
|
; C3_HIGH ; 0 ; Untyped ;
|
|
; C4_HIGH ; 0 ; Untyped ;
|
|
; C5_HIGH ; 0 ; Untyped ;
|
|
; C6_HIGH ; 0 ; Untyped ;
|
|
; C7_HIGH ; 0 ; Untyped ;
|
|
; C8_HIGH ; 0 ; Untyped ;
|
|
; C9_HIGH ; 0 ; Untyped ;
|
|
; C0_LOW ; 0 ; Untyped ;
|
|
; C1_LOW ; 0 ; Untyped ;
|
|
; C2_LOW ; 0 ; Untyped ;
|
|
; C3_LOW ; 0 ; Untyped ;
|
|
; C4_LOW ; 0 ; Untyped ;
|
|
; C5_LOW ; 0 ; Untyped ;
|
|
; C6_LOW ; 0 ; Untyped ;
|
|
; C7_LOW ; 0 ; Untyped ;
|
|
; C8_LOW ; 0 ; Untyped ;
|
|
; C9_LOW ; 0 ; Untyped ;
|
|
; C0_INITIAL ; 0 ; Untyped ;
|
|
; C1_INITIAL ; 0 ; Untyped ;
|
|
; C2_INITIAL ; 0 ; Untyped ;
|
|
; C3_INITIAL ; 0 ; Untyped ;
|
|
; C4_INITIAL ; 0 ; Untyped ;
|
|
; C5_INITIAL ; 0 ; Untyped ;
|
|
; C6_INITIAL ; 0 ; Untyped ;
|
|
; C7_INITIAL ; 0 ; Untyped ;
|
|
; C8_INITIAL ; 0 ; Untyped ;
|
|
; C9_INITIAL ; 0 ; Untyped ;
|
|
; C0_MODE ; BYPASS ; Untyped ;
|
|
; C1_MODE ; BYPASS ; Untyped ;
|
|
; C2_MODE ; BYPASS ; Untyped ;
|
|
; C3_MODE ; BYPASS ; Untyped ;
|
|
; C4_MODE ; BYPASS ; Untyped ;
|
|
; C5_MODE ; BYPASS ; Untyped ;
|
|
; C6_MODE ; BYPASS ; Untyped ;
|
|
; C7_MODE ; BYPASS ; Untyped ;
|
|
; C8_MODE ; BYPASS ; Untyped ;
|
|
; C9_MODE ; BYPASS ; Untyped ;
|
|
; C0_PH ; 0 ; Untyped ;
|
|
; C1_PH ; 0 ; Untyped ;
|
|
; C2_PH ; 0 ; Untyped ;
|
|
; C3_PH ; 0 ; Untyped ;
|
|
; C4_PH ; 0 ; Untyped ;
|
|
; C5_PH ; 0 ; Untyped ;
|
|
; C6_PH ; 0 ; Untyped ;
|
|
; C7_PH ; 0 ; Untyped ;
|
|
; C8_PH ; 0 ; Untyped ;
|
|
; C9_PH ; 0 ; Untyped ;
|
|
; L0_HIGH ; 1 ; Untyped ;
|
|
; L1_HIGH ; 1 ; Untyped ;
|
|
; G0_HIGH ; 1 ; Untyped ;
|
|
; G1_HIGH ; 1 ; Untyped ;
|
|
; G2_HIGH ; 1 ; Untyped ;
|
|
; G3_HIGH ; 1 ; Untyped ;
|
|
; E0_HIGH ; 1 ; Untyped ;
|
|
; E1_HIGH ; 1 ; Untyped ;
|
|
; E2_HIGH ; 1 ; Untyped ;
|
|
; E3_HIGH ; 1 ; Untyped ;
|
|
; L0_LOW ; 1 ; Untyped ;
|
|
; L1_LOW ; 1 ; Untyped ;
|
|
; G0_LOW ; 1 ; Untyped ;
|
|
; G1_LOW ; 1 ; Untyped ;
|
|
; G2_LOW ; 1 ; Untyped ;
|
|
; G3_LOW ; 1 ; Untyped ;
|
|
; E0_LOW ; 1 ; Untyped ;
|
|
; E1_LOW ; 1 ; Untyped ;
|
|
; E2_LOW ; 1 ; Untyped ;
|
|
; E3_LOW ; 1 ; Untyped ;
|
|
; L0_INITIAL ; 1 ; Untyped ;
|
|
; L1_INITIAL ; 1 ; Untyped ;
|
|
; G0_INITIAL ; 1 ; Untyped ;
|
|
; G1_INITIAL ; 1 ; Untyped ;
|
|
; G2_INITIAL ; 1 ; Untyped ;
|
|
; G3_INITIAL ; 1 ; Untyped ;
|
|
; E0_INITIAL ; 1 ; Untyped ;
|
|
; E1_INITIAL ; 1 ; Untyped ;
|
|
; E2_INITIAL ; 1 ; Untyped ;
|
|
; E3_INITIAL ; 1 ; Untyped ;
|
|
; L0_MODE ; BYPASS ; Untyped ;
|
|
; L1_MODE ; BYPASS ; Untyped ;
|
|
; G0_MODE ; BYPASS ; Untyped ;
|
|
; G1_MODE ; BYPASS ; Untyped ;
|
|
; G2_MODE ; BYPASS ; Untyped ;
|
|
; G3_MODE ; BYPASS ; Untyped ;
|
|
; E0_MODE ; BYPASS ; Untyped ;
|
|
; E1_MODE ; BYPASS ; Untyped ;
|
|
; E2_MODE ; BYPASS ; Untyped ;
|
|
; E3_MODE ; BYPASS ; Untyped ;
|
|
; L0_PH ; 0 ; Untyped ;
|
|
; L1_PH ; 0 ; Untyped ;
|
|
; G0_PH ; 0 ; Untyped ;
|
|
; G1_PH ; 0 ; Untyped ;
|
|
; G2_PH ; 0 ; Untyped ;
|
|
; G3_PH ; 0 ; Untyped ;
|
|
; E0_PH ; 0 ; Untyped ;
|
|
; E1_PH ; 0 ; Untyped ;
|
|
; E2_PH ; 0 ; Untyped ;
|
|
; E3_PH ; 0 ; Untyped ;
|
|
; M_PH ; 0 ; Untyped ;
|
|
; C1_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C2_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C3_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C4_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C5_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C6_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C7_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C8_USE_CASC_IN ; OFF ; Untyped ;
|
|
; C9_USE_CASC_IN ; OFF ; Untyped ;
|
|
; CLK0_COUNTER ; G0 ; Untyped ;
|
|
; CLK1_COUNTER ; G0 ; Untyped ;
|
|
; CLK2_COUNTER ; G0 ; Untyped ;
|
|
; CLK3_COUNTER ; G0 ; Untyped ;
|
|
; CLK4_COUNTER ; G0 ; Untyped ;
|
|
; CLK5_COUNTER ; G0 ; Untyped ;
|
|
; CLK6_COUNTER ; E0 ; Untyped ;
|
|
; CLK7_COUNTER ; E1 ; Untyped ;
|
|
; CLK8_COUNTER ; E2 ; Untyped ;
|
|
; CLK9_COUNTER ; E3 ; Untyped ;
|
|
; L0_TIME_DELAY ; 0 ; Untyped ;
|
|
; L1_TIME_DELAY ; 0 ; Untyped ;
|
|
; G0_TIME_DELAY ; 0 ; Untyped ;
|
|
; G1_TIME_DELAY ; 0 ; Untyped ;
|
|
; G2_TIME_DELAY ; 0 ; Untyped ;
|
|
; G3_TIME_DELAY ; 0 ; Untyped ;
|
|
; E0_TIME_DELAY ; 0 ; Untyped ;
|
|
; E1_TIME_DELAY ; 0 ; Untyped ;
|
|
; E2_TIME_DELAY ; 0 ; Untyped ;
|
|
; E3_TIME_DELAY ; 0 ; Untyped ;
|
|
; M_TIME_DELAY ; 0 ; Untyped ;
|
|
; N_TIME_DELAY ; 0 ; Untyped ;
|
|
; EXTCLK3_COUNTER ; E3 ; Untyped ;
|
|
; EXTCLK2_COUNTER ; E2 ; Untyped ;
|
|
; EXTCLK1_COUNTER ; E1 ; Untyped ;
|
|
; EXTCLK0_COUNTER ; E0 ; Untyped ;
|
|
; ENABLE0_COUNTER ; L0 ; Untyped ;
|
|
; ENABLE1_COUNTER ; L0 ; Untyped ;
|
|
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
|
|
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
|
|
; LOOP_FILTER_C ; 5 ; Untyped ;
|
|
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
|
|
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
|
|
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
|
|
; VCO_POST_SCALE ; 0 ; Untyped ;
|
|
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
|
|
; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK0 ; PORT_USED ; Untyped ;
|
|
; PORT_CLK1 ; PORT_USED ; Untyped ;
|
|
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
|
|
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
|
|
; PORT_INCLK0 ; PORT_USED ; Untyped ;
|
|
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
|
|
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
|
|
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
|
|
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
|
|
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
|
|
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
|
|
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
|
|
; M_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C0_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C1_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C2_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C3_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C4_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C5_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C6_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C7_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C8_TEST_SOURCE ; 5 ; Untyped ;
|
|
; C9_TEST_SOURCE ; 5 ; Untyped ;
|
|
; CBXI_PARAMETER ; MAIN_PLL_altpll ; Untyped ;
|
|
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
|
|
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
|
|
; WIDTH_CLOCK ; 5 ; Signed Integer ;
|
|
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
|
|
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
|
|
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
+-------------------------------+----------------------------+---------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: mux14:DAC_MUX|lpm_mux:LPM_MUX_component ;
|
|
+------------------------+--------------+----------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------+--------------+----------------------------------------------+
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; LPM_WIDTH ; 14 ; Signed Integer ;
|
|
; LPM_SIZE ; 2 ; Signed Integer ;
|
|
; LPM_WIDTHS ; 1 ; Signed Integer ;
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
|
; CBXI_PARAMETER ; mux_rsc ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
|
|
+------------------------+--------------+----------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: dac_null:DAC_IDLE|lpm_constant:LPM_CONSTANT_component ;
|
|
+--------------------+------------------+------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+--------------------+------------------+------------------------------------------------------------+
|
|
; LPM_WIDTH ; 14 ; Signed Integer ;
|
|
; LPM_CVALUE ; 8192 ; Signed Integer ;
|
|
; ENABLE_RUNTIME_MOD ; NO ; Untyped ;
|
|
; CBXI_PARAMETER ; lpm_constant_9k6 ; Untyped ;
|
|
+--------------------+------------------+------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+--------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: DAC_corrector:DAC_CORRECTOR ;
|
|
+----------------+-------+-------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+-------------------------------------------------+
|
|
; in_width ; 32 ; Signed Integer ;
|
|
; out_width ; 14 ; Signed Integer ;
|
|
+----------------+-------+-------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0 ;
|
|
+-------------------------+-----------------+---------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------------+-----------------+---------------------------------------------------------------+
|
|
; lpm_type ; altsource_probe ; String ;
|
|
; lpm_hint ; UNUSED ; String ;
|
|
; sld_auto_instance_index ; YES ; String ;
|
|
; sld_instance_index ; 0 ; Signed Integer ;
|
|
; sld_node_info_parameter ; 4746752 ; Signed Integer ;
|
|
; sld_ir_width ; 4 ; Signed Integer ;
|
|
; instance_id ; ADC ; String ;
|
|
; probe_width ; 12 ; Signed Integer ;
|
|
; source_width ; 0 ; Signed Integer ;
|
|
; source_initial_value ; 0 ; String ;
|
|
; enable_metastability ; NO ; String ;
|
|
+-------------------------+-----------------+---------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl ;
|
|
+-------------------------+-----------------+-----------------------------------------------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+-------------------------+-----------------+-----------------------------------------------------------------------------------------+
|
|
; lpm_type ; altsource_probe ; String ;
|
|
; lpm_hint ; UNUSED ; String ;
|
|
; sld_auto_instance_index ; YES ; String ;
|
|
; sld_instance_index ; 0 ; Signed Integer ;
|
|
; SLD_NODE_INFO ; 4746752 ; Signed Integer ;
|
|
; sld_ir_width ; 4 ; Signed Integer ;
|
|
; instance_id ; ADC ; String ;
|
|
; probe_width ; 12 ; Signed Integer ;
|
|
; source_width ; 0 ; Signed Integer ;
|
|
; source_initial_value ; 0 ; String ;
|
|
; enable_metastability ; NO ; String ;
|
|
+-------------------------+-----------------+-----------------------------------------------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Partition Dependent Files ;
|
|
+-------------------------------------------------------------------+-----------------------+--------------+----------------------------------+
|
|
; File ; Location ; Library ; Checksum ;
|
|
+-------------------------------------------------------------------+-----------------------+--------------+----------------------------------+
|
|
; db/ip/clock_buffer/clock_buffer.v ; Project Directory ; clock_buffer ; 7c0a52d86aeffe2045a9a1cab1d370dc ;
|
|
; db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v ; Project Directory ; clock_buffer ; f0ac8af5fa42f9e4fa5149de7d42dc36 ;
|
|
; db/ip/debug/debug.v ; Project Directory ; DEBUG ; b33d97b47dd5f82e548fc7c5fd7dc5b7 ;
|
|
; db/ip/debug/submodules/altsource_probe_top.v ; Project Directory ; DEBUG ; 8182cb5c4ba5f0cdb49c6cc302ad1bcd ;
|
|
; db/ip/nco/nco.v ; Project Directory ; nco ; b3f0eabb8bad8e7285ef557ae20209b2 ;
|
|
; db/ip/nco/submodules/asj_altqmcpipe.v ; Project Directory ; nco ; 00f65b3e88b7010a0d50484bcfd8578f ;
|
|
; db/ip/nco/submodules/asj_gam_dp.v ; Project Directory ; nco ; 8cbba52abdb4c8ff5d4eac560c3ffe30 ;
|
|
; db/ip/nco/submodules/asj_nco_as_m_cen.v ; Project Directory ; nco ; f01c79c88d88841a05d482e816d47744 ;
|
|
; db/ip/nco/submodules/asj_nco_as_m_dp_cen.v ; Project Directory ; nco ; 25a6271af28fcc5d28e28d90011f677d ;
|
|
; db/ip/nco/submodules/asj_nco_derot.v ; Project Directory ; nco ; d4b0c4b5939a039a3f0bea113634247c ;
|
|
; db/ip/nco/submodules/asj_nco_isdr.v ; Project Directory ; nco ; c69cceb1a24ad72662733037a9b27260 ;
|
|
; db/ip/nco/submodules/asj_nco_madx_cen.v ; Project Directory ; nco ; f3b7995262994ca047d8e883d7211515 ;
|
|
; db/ip/nco/submodules/asj_nco_mady_cen.v ; Project Directory ; nco ; 3c04305587a1789a54b25a387bb07792 ;
|
|
; db/ip/nco/submodules/asj_nco_mob_w.v ; Project Directory ; nco ; 65b296bf78abd2f4ba34b7fc62051bb5 ;
|
|
; db/ip/nco/submodules/nco_nco_ii_0.v ; Project Directory ; nco ; fa5e93b775a2d0afa395ade6629ff503 ;
|
|
; db/ip/rx_cic/rx_cic.v ; Project Directory ; rx_cic ; 692956d599b0cc90891101c778764a7b ;
|
|
; db/ip/rx_cic/submodules/alt_cic_core.sv ; Project Directory ; rx_cic ; 2c24d6f21651f165b9216975ed235423 ;
|
|
; db/ip/rx_cic/submodules/alt_cic_dec_siso.sv ; Project Directory ; rx_cic ; a9b733de207909177edb27c94897f32b ;
|
|
; db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv ; Project Directory ; rx_cic ; 949e75652d6ce83bdb84073bc9681459 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; Project Directory ; rx_cic ; 1a8943cbbf293815d2e650e297f1c47f ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; Project Directory ; rx_cic ; 853bc9033582b9f69e1851a6c4c80764 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; Project Directory ; rx_cic ; d690330101b19cfdeda86c89465207d6 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; Project Directory ; rx_cic ; 6ae204fc306fc9155383ebebdb81e301 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd ; Project Directory ; rx_cic ; efe3866ccd9e534a3aed1502c8adf01d ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_delay.vhd ; Project Directory ; rx_cic ; 0a25b7d53b8593124295baecd819dabd ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd ; Project Directory ; rx_cic ; 93fd39a11edb95c16e01436f71e2288f ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_downsample.sv ; Project Directory ; rx_cic ; f08ad9edbd9feda497e43af7dab02d69 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_integrator.vhd ; Project Directory ; rx_cic ; 40c1ca40cd78a9e4520f30cc0b757f33 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd ; Project Directory ; rx_cic ; 7774b9a194ac6eeb4b71faa70f4e23f9 ;
|
|
; db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd ; Project Directory ; rx_cic ; 3a2113061195e3d22de25838e4eabe16 ;
|
|
; db/ip/rx_cic/submodules/counter_module.sv ; Project Directory ; rx_cic ; c714f8c7e341c690f49beeb9236106be ;
|
|
; db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv ; Project Directory ; rx_cic ; 9e578de92e747fe23011d7dbdbd21fdc ;
|
|
; rx_ciccomp.v ; Project Directory ; rx_ciccomp ; 90c4f6896871ade19c6e0c1e93b0d2ce ;
|
|
; rx_ciccomp/altera_avalon_sc_fifo.v ; Project Directory ; rx_ciccomp ; 7ca9ebf5ee0927cc581c8ed8ca74d204 ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; Project Directory ; rx_ciccomp ; b53bccfea67a565c722899c60bd1075e ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; Project Directory ; rx_ciccomp ; f7cd2f36483fa9f4453ae2ad481d4f1f ;
|
|
; rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; Project Directory ; rx_ciccomp ; 9e961ecfb9781b619ab46688a85204fb ;
|
|
; rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; Project Directory ; rx_ciccomp ; 0a5ad8c00e30d4b34a8a89d574a5c067 ;
|
|
; rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; Project Directory ; rx_ciccomp ; e062585cd2ad3354c1b959702d01fd0f ;
|
|
; rx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; Project Directory ; rx_ciccomp ; 9ca5a604cf7afe7c95ee7f498591dbb4 ;
|
|
; rx_ciccomp/dspba_library.vhd ; Project Directory ; rx_ciccomp ; 3732ac4ab84e4d37d685aef65b8115dd ;
|
|
; rx_ciccomp/dspba_library_package.vhd ; Project Directory ; rx_ciccomp ; a30dba2928918de51a7de9d6ad22283d ;
|
|
; rx_ciccomp/rx_ciccomp_0002.vhd ; Project Directory ; rx_ciccomp ; c35486cedf1d4c29140364908fb72416 ;
|
|
; rx_ciccomp/rx_ciccomp_0002_ast.vhd ; Project Directory ; rx_ciccomp ; 0462480c129deb84524efe912d81d7c4 ;
|
|
; rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd ; Project Directory ; rx_ciccomp ; b65eb122d938b69287827e8058ee15a1 ;
|
|
; db/ip/tx_cic/submodules/alt_cic_core.sv ; Project Directory ; tx_cic ; 2c24d6f21651f165b9216975ed235423 ;
|
|
; db/ip/tx_cic/submodules/alt_cic_int_siso.sv ; Project Directory ; tx_cic ; e45af7f52eef0c37faa1eab493fa9e62 ;
|
|
; db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv ; Project Directory ; tx_cic ; 949e75652d6ce83bdb84073bc9681459 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd ; Project Directory ; tx_cic ; 1a8943cbbf293815d2e650e297f1c47f ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd ; Project Directory ; tx_cic ; 853bc9033582b9f69e1851a6c4c80764 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd ; Project Directory ; tx_cic ; d690330101b19cfdeda86c89465207d6 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd ; Project Directory ; tx_cic ; 6ae204fc306fc9155383ebebdb81e301 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_delay.vhd ; Project Directory ; tx_cic ; 0a25b7d53b8593124295baecd819dabd ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd ; Project Directory ; tx_cic ; 93fd39a11edb95c16e01436f71e2288f ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_integrator.vhd ; Project Directory ; tx_cic ; 40c1ca40cd78a9e4520f30cc0b757f33 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd ; Project Directory ; tx_cic ; 7774b9a194ac6eeb4b71faa70f4e23f9 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd ; Project Directory ; tx_cic ; 3a2113061195e3d22de25838e4eabe16 ;
|
|
; db/ip/tx_cic/submodules/auk_dspip_upsample.vhd ; Project Directory ; tx_cic ; 58ac0be4fbfff201416b2a6bf51ea5c7 ;
|
|
; db/ip/tx_cic/submodules/counter_module.sv ; Project Directory ; tx_cic ; c714f8c7e341c690f49beeb9236106be ;
|
|
; db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv ; Project Directory ; tx_cic ; 716f10793531f588e924409e19fbc610 ;
|
|
; db/ip/tx_cic/tx_cic.v ; Project Directory ; tx_cic ; 3055c4fe40959167f30f8ffafb32e1b8 ;
|
|
; tx_ciccomp.v ; Project Directory ; tx_ciccomp ; 5147630acebf38a7ee31aff59b9a3d4b ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd ; Project Directory ; tx_ciccomp ; b53bccfea67a565c722899c60bd1075e ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd ; Project Directory ; tx_ciccomp ; f7cd2f36483fa9f4453ae2ad481d4f1f ;
|
|
; tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd ; Project Directory ; tx_ciccomp ; 9e961ecfb9781b619ab46688a85204fb ;
|
|
; tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd ; Project Directory ; tx_ciccomp ; 0a5ad8c00e30d4b34a8a89d574a5c067 ;
|
|
; tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd ; Project Directory ; tx_ciccomp ; e062585cd2ad3354c1b959702d01fd0f ;
|
|
; tx_ciccomp/auk_dspip_roundsat_hpfir.vhd ; Project Directory ; tx_ciccomp ; 9ca5a604cf7afe7c95ee7f498591dbb4 ;
|
|
; tx_ciccomp/dspba_library.vhd ; Project Directory ; tx_ciccomp ; 3732ac4ab84e4d37d685aef65b8115dd ;
|
|
; tx_ciccomp/dspba_library_package.vhd ; Project Directory ; tx_ciccomp ; a30dba2928918de51a7de9d6ad22283d ;
|
|
; tx_ciccomp/tx_ciccomp_0002.vhd ; Project Directory ; tx_ciccomp ; 27b92bbdbfbca5fca40a337552ed1690 ;
|
|
; tx_ciccomp/tx_ciccomp_0002_ast.vhd ; Project Directory ; tx_ciccomp ; 515b104e039a07858836749a21fdf9a0 ;
|
|
; tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd ; Project Directory ; tx_ciccomp ; 299ce585a886a18a09ec09b98db70548 ;
|
|
; db/ip/tx_nco/submodules/asj_altqmcpipe.v ; Project Directory ; tx_nco ; 00f65b3e88b7010a0d50484bcfd8578f ;
|
|
; db/ip/tx_nco/submodules/asj_gam_dp.v ; Project Directory ; tx_nco ; 8cbba52abdb4c8ff5d4eac560c3ffe30 ;
|
|
; db/ip/tx_nco/submodules/asj_nco_as_m_cen.v ; Project Directory ; tx_nco ; f01c79c88d88841a05d482e816d47744 ;
|
|
; db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v ; Project Directory ; tx_nco ; 25a6271af28fcc5d28e28d90011f677d ;
|
|
; db/ip/tx_nco/submodules/asj_nco_derot.v ; Project Directory ; tx_nco ; d4b0c4b5939a039a3f0bea113634247c ;
|
|
; db/ip/tx_nco/submodules/asj_nco_isdr.v ; Project Directory ; tx_nco ; c69cceb1a24ad72662733037a9b27260 ;
|
|
; db/ip/tx_nco/submodules/asj_nco_madx_cen.v ; Project Directory ; tx_nco ; f3b7995262994ca047d8e883d7211515 ;
|
|
; db/ip/tx_nco/submodules/asj_nco_mady_cen.v ; Project Directory ; tx_nco ; 3c04305587a1789a54b25a387bb07792 ;
|
|
; db/ip/tx_nco/submodules/asj_nco_mob_w.v ; Project Directory ; tx_nco ; 65b296bf78abd2f4ba34b7fc62051bb5 ;
|
|
; db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v ; Project Directory ; tx_nco ; 51108a412915a42724252c82e3f182e2 ;
|
|
; db/ip/tx_nco/tx_nco.v ; Project Directory ; tx_nco ; ea442ef4c3a9b3b23d06e40f89159c5f ;
|
|
; libraries/megafunctions/a_dpfifo.inc ; Quartus Prime Install ; work ; 37c2d0bb70d5a3f83a4aa09e62c75080 ;
|
|
; libraries/megafunctions/a_f2fifo.inc ; Quartus Prime Install ; work ; cebe3836bad826c95e765f77477e8a8b ;
|
|
; libraries/megafunctions/a_fffifo.inc ; Quartus Prime Install ; work ; aa34dd03c645beef0c31a3e4ef186db4 ;
|
|
; libraries/megafunctions/a_i2fifo.inc ; Quartus Prime Install ; work ; bfe272f05af0cf849bd8b4748efceffe ;
|
|
; libraries/megafunctions/a_rdenreg.inc ; Quartus Prime Install ; work ; 3fcdce7559590d5a8afbe64788d201fb ;
|
|
; libraries/megafunctions/a_regfifo.inc ; Quartus Prime Install ; work ; 8b2977668c08752c10a1f1977c9b9ee6 ;
|
|
; libraries/megafunctions/addcore.inc ; Quartus Prime Install ; work ; e15993f131a5367862d60283fbb5a133 ;
|
|
; libraries/megafunctions/aglobal181.inc ; Quartus Prime Install ; work ; 5e51ccbc7a52298c3a01f3b5bfb59350 ;
|
|
; libraries/megafunctions/alt_counter_stratix.inc ; Quartus Prime Install ; work ; 3e1db420f0a6e888a1525f4eff14d5be ;
|
|
; libraries/megafunctions/alt_stratix_add_sub.inc ; Quartus Prime Install ; work ; 16df31198e4f1dce2b8df944fbafaefe ;
|
|
; libraries/megafunctions/altdpram.inc ; Quartus Prime Install ; work ; 229c034d72d6c571b2f9af0f2aa5d997 ;
|
|
; libraries/megafunctions/altpll.tdf ; Quartus Prime Install ; work ; aa98bacc177fec4e0c987adf93460f0d ;
|
|
; libraries/megafunctions/altram.inc ; Quartus Prime Install ; work ; ad5518b39ffd3cf1df377e6360d1c9b6 ;
|
|
; libraries/megafunctions/altrom.inc ; Quartus Prime Install ; work ; 192b74eafa8debf2248ea73881e77f91 ;
|
|
; libraries/megafunctions/altshift.inc ; Quartus Prime Install ; work ; 5c767a29f11db3f131fc886ea42a52bd ;
|
|
; libraries/megafunctions/altsource_probe.v ; Quartus Prime Install ; work ; 859bad2c48edeeb6b2440eb6a7861700 ;
|
|
; libraries/megafunctions/altsource_probe_body.vhd ; Quartus Prime Install ; work ; 3e16a83c4eaa7bb7d04965b85160815c ;
|
|
; libraries/megafunctions/altsyncram.tdf ; Quartus Prime Install ; work ; 48fbb9e7300eb083732aeb85f77fd8a1 ;
|
|
; libraries/megafunctions/bypassff.inc ; Quartus Prime Install ; work ; 42d08f243d3471f724fd61ea21a0eb9f ;
|
|
; libraries/megafunctions/cmpconst.inc ; Quartus Prime Install ; work ; fe4bfdfa5310384231b99c696fe2e348 ;
|
|
; libraries/megafunctions/cycloneii_pll.inc ; Quartus Prime Install ; work ; c2ee779f089b03bc181df753ea85b3ef ;
|
|
; libraries/megafunctions/dffeea.inc ; Quartus Prime Install ; work ; 0f11711657cd42ee78437f4349496034 ;
|
|
; libraries/megafunctions/look_add.inc ; Quartus Prime Install ; work ; 9091c394592369a07bdf7fbf1ce9ced6 ;
|
|
; libraries/megafunctions/lpm_add_sub.inc ; Quartus Prime Install ; work ; 144a73b61081a2a03554ff5acc5e8842 ;
|
|
; libraries/megafunctions/lpm_add_sub.tdf ; Quartus Prime Install ; work ; 3150e15c2f23aaab40af6eafa1167811 ;
|
|
; libraries/megafunctions/lpm_compare.inc ; Quartus Prime Install ; work ; bbd3e8c93afb7320934629e5fb011566 ;
|
|
; libraries/megafunctions/lpm_constant.inc ; Quartus Prime Install ; work ; 97ffb7e3fef9ce9fce4eff08455d5da5 ;
|
|
; libraries/megafunctions/lpm_constant.tdf ; Quartus Prime Install ; work ; a44f5bd0fe95ce950545f72fd2b9885f ;
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; libraries/megafunctions/lpm_counter.inc ; Quartus Prime Install ; work ; c5cfeeabc5f2ab60b3453f6abbc42b41 ;
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; libraries/megafunctions/lpm_counter.tdf ; Quartus Prime Install ; work ; a05d770c5e6d8572a561b92f5c917b0c ;
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; libraries/megafunctions/lpm_decode.inc ; Quartus Prime Install ; work ; 10da69a8bbd590d66779e7a142f73790 ;
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; libraries/megafunctions/lpm_mult.tdf ; Quartus Prime Install ; work ; 1fd119a616af49c2150e94f8c332f689 ;
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; libraries/megafunctions/lpm_mux.inc ; Quartus Prime Install ; work ; dd87bed90959d6126db09970164b7ba6 ;
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; libraries/megafunctions/lpm_mux.tdf ; Quartus Prime Install ; work ; 0fbcf24465c57ef24781de183839e69b ;
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; libraries/megafunctions/multcore.inc ; Quartus Prime Install ; work ; ee598ea39a3d6bdc35b167eefc3ee3da ;
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; libraries/megafunctions/muxlut.inc ; Quartus Prime Install ; work ; 301e88484af1e80d67bcd099bb975882 ;
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; libraries/megafunctions/scfifo.tdf ; Quartus Prime Install ; work ; 652ae8117a8bf29f3cb57aa20e025615 ;
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; libraries/megafunctions/sld_jtag_endpoint_adapter.vhd ; Quartus Prime Install ; work ; c9470442b497e59f424c132aaa5f1c62 ;
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; libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv ; Quartus Prime Install ; work ; 5c888fd693c6d8dd940c5fb354eeafd0 ;
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; libraries/megafunctions/sld_rom_sr.vhd ; Quartus Prime Install ; work ; 1e4ae87ce53228110f53ff06bf3d4798 ;
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; libraries/megafunctions/stratix_pll.inc ; Quartus Prime Install ; work ; a9a94c5b0e18105f7ae8c218a67ec9f7 ;
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; libraries/megafunctions/stratix_ram_block.inc ; Quartus Prime Install ; work ; e3a03868917f0b3dd57b6ed1dd195f22 ;
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; libraries/megafunctions/stratixii_pll.inc ; Quartus Prime Install ; work ; 6797ab505ed700f1a221e4a213e106a6 ;
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; DAC_corrector.v ; Project Directory ; work ; 7cb7109e7e1cc4ad44e834e7db595a8f ;
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; dac_null.v ; Project Directory ; work ; ce27439a46221dffae508bb2fea0129d ;
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; data_shifter.v ; Project Directory ; work ; 97e6634b739c31535a9ced452c10894b ;
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; db/a_dpfifo_1lv.tdf ; Project Directory ; work ; dd62f4e26b46e84b7b7b1100e903fcd9 ;
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; db/a_dpfifo_5ku.tdf ; Project Directory ; work ; af539fd72d37289585d2f87290875cb8 ;
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; db/a_dpfifo_9qv.tdf ; Project Directory ; work ; 9a9f892bc3e00d15a4a9c8c932bc65f2 ;
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; db/a_dpfifo_gqv.tdf ; Project Directory ; work ; 9ca39e88bacdf9c01835a13ee8a56164 ;
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; db/a_dpfifo_vkv.tdf ; Project Directory ; work ; 47b928cb4ef9e67e5fa2e99a2e1393fd ;
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; db/add_sub_1vk.tdf ; Project Directory ; work ; 8c5455796c7aec4a848d8845e8708dfe ;
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; db/add_sub_fpk.tdf ; Project Directory ; work ; 2cbae54dde466df56ba4d0e5858aa5e7 ;
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; db/add_sub_jpk.tdf ; Project Directory ; work ; b58d83701676a5eed410dfb902d7af85 ;
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; db/add_sub_u4i.tdf ; Project Directory ; work ; c4acfb859223380ae0e9065b86c17574 ;
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; db/altsyncram_0mn3.tdf ; Project Directory ; work ; 66dcf65b37c25810d8e894a481f5e967 ;
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; db/altsyncram_4k82.tdf ; Project Directory ; work ; 9697611adefc3e2b32ab05b9c04d5444 ;
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; db/altsyncram_au91.tdf ; Project Directory ; work ; 7977279b6802ba7066352bfdd96973f1 ;
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; db/altsyncram_fu91.tdf ; Project Directory ; work ; 75315acc77851719110c194767a8fde1 ;
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; db/altsyncram_h7h1.tdf ; Project Directory ; work ; 6042dddceedfe6f8201e8e3560877767 ;
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; db/altsyncram_h982.tdf ; Project Directory ; work ; 1462fc8be7af0ccffda08835995f3f93 ;
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; db/altsyncram_hah1.tdf ; Project Directory ; work ; f054c14b5f3c12f6de832de3ea96c63d ;
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; db/altsyncram_l7h1.tdf ; Project Directory ; work ; 6768192c5243fdde798641605a652422 ;
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; db/altsyncram_m7h1.tdf ; Project Directory ; work ; ccd82b05875ddaf5ee071599f9fbfcab ;
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; db/altsyncram_p8a1.tdf ; Project Directory ; work ; b067974080254aa244d765014182464b ;
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; db/altsyncram_u8a1.tdf ; Project Directory ; work ; f0b65ab0a80077009894541bc2d06b7f ;
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; db/altsyncram_vah1.tdf ; Project Directory ; work ; 797667213e5335730b5d988ccb2c93f3 ;
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; db/cmpr_fs8.tdf ; Project Directory ; work ; fba5a7acea8cbae7e405bd2e0de680e3 ;
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; db/cmpr_gs8.tdf ; Project Directory ; work ; fba0739ce563bb0a117b163bcb06b211 ;
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; db/cmpr_is8.tdf ; Project Directory ; work ; 5be45ee6f88fd52e7f9cd4846b422a95 ;
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; db/cntr_7a7.tdf ; Project Directory ; work ; a487826c6194d62466bcb39776240d75 ;
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; db/cntr_8a7.tdf ; Project Directory ; work ; 8fb9fbcb3f0a94bb57182debd6cdf97f ;
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; db/cntr_aa7.tdf ; Project Directory ; work ; e2862114d4c3b457321c9bece5dab731 ;
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; db/cntr_asi.tdf ; Project Directory ; work ; cffbc3d918c3f3327f3dd42b88343226 ;
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; db/cntr_q9b.tdf ; Project Directory ; work ; 9b4183716ce613a14f9a8704742ad8e1 ;
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; db/cntr_r9b.tdf ; Project Directory ; work ; 9b12d11680cde46b9a7e42044c439d2b ;
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; db/cntr_s9b.tdf ; Project Directory ; work ; f42c2793afdffb1683284e4a4c60647c ;
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; db/cntr_t9b.tdf ; Project Directory ; work ; f9735a6004f7e481f017f95143faaf3f ;
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; db/cntr_u9b.tdf ; Project Directory ; work ; 572f4b0254b35f9d613d935033b2ca6a ;
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; db/main_pll_altpll.v ; Project Directory ; work ; 30d0bc64c7ecaedadd9aa3cfe0cf8812 ;
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; db/mult_abt.tdf ; Project Directory ; work ; df4cbb78ac0a80a240542b2313c5f2ed ;
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; db/mult_jnp.tdf ; Project Directory ; work ; bf7dd3983426a6d7ad97bed807204d63 ;
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; db/mult_ncu.tdf ; Project Directory ; work ; be30b1ebd46228241f4a1665ddecc3e3 ;
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; db/mux_rsc.tdf ; Project Directory ; work ; 53d4a0e87e72834ade78722fc162354b ;
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; db/scfifo_ci71.tdf ; Project Directory ; work ; e30c6e1571f7bc17d73caa3bbc78f410 ;
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; db/scfifo_ef71.tdf ; Project Directory ; work ; 0dc2312709cca9c07ea329cc5bf13402 ;
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; db/scfifo_gf71.tdf ; Project Directory ; work ; 2d1936077762ff16e1e622e6c1dc6444 ;
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; db/scfifo_ji71.tdf ; Project Directory ; work ; f1659460690412bda15c014ee50bacdb ;
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; db/scfifo_qm51.tdf ; Project Directory ; work ; 9d819510c3f6b1527fbdc8671f90530c ;
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; db/tx_pll_altpll.v ; Project Directory ; work ; 3ed1f7e548c3d1d27b2dbd4373cd98d9 ;
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; MAIN_PLL.v ; Project Directory ; work ; f5544cc8e566a5bf3e5cfdcb54b90544 ;
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; mixer.v ; Project Directory ; work ; 2c76efedf2c42bc471fbb92015b3ae8d ;
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; mux14.v ; Project Directory ; work ; 4f144eae417b604e07a2c32b3ab317f4 ;
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; spi_interface.v ; Project Directory ; work ; 80d5a26aa07dfb4482f6fb768a4df406 ;
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; stm32_interface.v ; Project Directory ; work ; 2f6911709afb86c0afcdf183fc74d020 ;
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; tx_mixer.v ; Project Directory ; work ; 91ac864ba70cc2c35b5d293afd02b3b0 ;
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; tx_pll.v ; Project Directory ; work ; 7c08022af9aa68156a9d5ffba0d4c456 ;
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; tx_summator.v ; Project Directory ; work ; cf1bf4119540af0eb2e3e61a20d45e27 ;
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; WOLF-LITE.bdf ; Project Directory ; work ; 3b66629c45fef02be52ad5d1aa4d8023 ;
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+-------------------------------------------------------------------+-----------------------+--------------+----------------------------------+
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+-----------------------------------------------------+
|
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; Post-Synthesis Netlist Statistics for Top Partition ;
|
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+-----------------------+-----------------------------+
|
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; Type ; Count ;
|
|
+-----------------------+-----------------------------+
|
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; boundary_port ; 82 ;
|
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; cycloneiii_clkctrl ; 1 ;
|
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; cycloneiii_ff ; 7440 ;
|
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; CLR ; 442 ;
|
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; CLR SCLR ; 32 ;
|
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; ENA ; 2763 ;
|
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; ENA CLR ; 2208 ;
|
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; ENA CLR SLD ; 195 ;
|
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; ENA SCLR ; 1056 ;
|
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; ENA SLD ; 62 ;
|
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; SCLR ; 156 ;
|
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; SCLR SLD ; 2 ;
|
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; SLD ; 39 ;
|
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; plain ; 485 ;
|
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; cycloneiii_io_obuf ; 8 ;
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; cycloneiii_lcell_comb ; 7258 ;
|
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; arith ; 3894 ;
|
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; 1 data inputs ; 2 ;
|
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; 2 data inputs ; 355 ;
|
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; 3 data inputs ; 3537 ;
|
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; normal ; 3364 ;
|
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; 0 data inputs ; 5 ;
|
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; 1 data inputs ; 195 ;
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; 2 data inputs ; 303 ;
|
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; 3 data inputs ; 417 ;
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; 4 data inputs ; 2444 ;
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; cycloneiii_mac_mult ; 16 ;
|
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; cycloneiii_mac_out ; 16 ;
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; cycloneiii_pll ; 2 ;
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; cycloneiii_ram_block ; 430 ;
|
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; ; ;
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; Max LUT depth ; 9.50 ;
|
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; Average LUT depth ; 4.52 ;
|
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+-----------------------+-----------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Partition "sld_hub:auto_hub" Resource Utilization by Entity ;
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+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
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; |WOLF-LITE ; 119 (0) ; 79 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE ; WOLF-LITE ; work ;
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; |sld_hub:auto_hub| ; 119 (1) ; 79 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub ; sld_hub ; altera_sld ;
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; |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 118 (0) ; 79 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric ; alt_sld_fab_with_jtag_input ; altera_sld ;
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; |alt_sld_fab:instrumentation_fabric| ; 118 (0) ; 79 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab:alt_sld_fab| ; 118 (1) ; 79 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; alt_sld_fab_alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab_ident:ident| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_ident:ident ; alt_sld_fab_alt_sld_fab_ident ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric| ; 105 (0) ; 74 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab ;
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; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub| ; 105 (65) ; 74 (46) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; sld_jtag_hub ; work ;
|
|
; |sld_rom_sr:hub_info_reg| ; 22 (22) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ; sld_rom_sr ; work ;
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|
; |sld_shadow_jsm:shadow_jsm| ; 18 (18) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm ; altera_sld ;
|
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+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
|
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+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
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+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[2] ;
|
|
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_minor_ver_reg[1] ;
|
|
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[3] ;
|
|
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4] ;
|
|
; 34:1 ; 4 bits ; 88 LEs ; 60 LEs ; 28 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[0] ;
|
|
; 20:1 ; 4 bits ; 52 LEs ; 36 LEs ; 16 LEs ; Yes ; |WOLF-LITE|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[0] ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
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|
|
|
|
+------------------------------------------------------------------+
|
|
; Post-Synthesis Netlist Statistics for Partition sld_hub:auto_hub ;
|
|
+-----------------------+------------------------------------------+
|
|
; Type ; Count ;
|
|
+-----------------------+------------------------------------------+
|
|
; boundary_port ; 95 ;
|
|
; cycloneiii_ff ; 79 ;
|
|
; CLR ; 4 ;
|
|
; ENA ; 21 ;
|
|
; ENA CLR ; 21 ;
|
|
; ENA CLR SLD ; 1 ;
|
|
; ENA SLD ; 5 ;
|
|
; SCLR ; 7 ;
|
|
; SLD ; 4 ;
|
|
; plain ; 16 ;
|
|
; cycloneiii_lcell_comb ; 119 ;
|
|
; arith ; 8 ;
|
|
; 2 data inputs ; 8 ;
|
|
; normal ; 111 ;
|
|
; 0 data inputs ; 1 ;
|
|
; 1 data inputs ; 6 ;
|
|
; 2 data inputs ; 20 ;
|
|
; 3 data inputs ; 27 ;
|
|
; 4 data inputs ; 57 ;
|
|
; ; ;
|
|
; Max LUT depth ; 4.00 ;
|
|
; Average LUT depth ; 1.89 ;
|
|
+-----------------------+------------------------------------------+
|
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|
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|
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl" ;
|
|
+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_e1dr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_cir ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_uir ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; jtag_state_tlr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
|
|
; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
|
|
+-----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0" ;
|
|
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; source ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
|
|
; source_clk ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
; source_ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
|
|
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core" ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; rate ; Input ; Info ; Stuck at GND ;
|
|
; in_startofpacket ; Input ; Info ; Stuck at VCC ;
|
|
; in_endofpacket ; Input ; Info ; Stuck at VCC ;
|
|
; out_channel ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
; out_startofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
; out_endofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core" ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; rate ; Input ; Info ; Stuck at GND ;
|
|
; in_startofpacket ; Input ; Info ; Stuck at VCC ;
|
|
; in_endofpacket ; Input ; Info ; Stuck at VCC ;
|
|
; out_channel ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
; out_startofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
; out_endofpacket ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0" ;
|
|
+-------+-------+----------+-------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+-------+-------+----------+-------------------------------------------+
|
|
; clken ; Input ; Info ; Stuck at VCC ;
|
|
+-------+-------+----------+-------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component" ;
|
|
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------+
|
|
; ena ; Input ; Info ; Stuck at VCC ;
|
|
; inclk[3..1] ; Input ; Info ; Stuck at GND ;
|
|
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Elapsed Time Per Partition ;
|
|
+----------------+--------------+
|
|
; Partition Name ; Elapsed Time ;
|
|
+----------------+--------------+
|
|
; Top ; 00:00:23 ;
|
|
+----------------+--------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
|
Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
|
Info: Processing started: Thu Jan 07 18:17:14 2021
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE
|
|
Info (16303): Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
|
Info (12248): Elaborating Platform Designer system entity "clock_buffer.qsys"
|
|
Info (12250): 2021.01.07.19:17:33 Progress: Loading FPGA/clock_buffer.qsys
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Adding altclkctrl_0 [altclkctrl 18.1]
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Parameterizing module altclkctrl_0
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:17:34 Progress: Validating
|
|
Info (12250): 2021.01.07.19:17:35 Progress: Done reading input file
|
|
Info (12250): 2021.01.07.19:17:36 : clock_buffer.altclkctrl_0: Targeting device family: Cyclone IV E.
|
|
Info (12250): 2021.01.07.19:17:36 : clock_buffer.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
|
|
Info (12250): Clock_buffer: Generating clock_buffer "clock_buffer" for QUARTUS_SYNTH
|
|
Info (12250): Altclkctrl_0: Generating top-level entity clock_buffer_altclkctrl_0.
|
|
Info (12250): Altclkctrl_0: "clock_buffer" instantiated altclkctrl "altclkctrl_0"
|
|
Info (12250): Clock_buffer: Done "clock_buffer" with 2 modules, 2 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "clock_buffer.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "rx_cic.qsys"
|
|
Info (12250): 2021.01.07.19:17:44 Progress: Loading FPGA/rx_cic.qsys
|
|
Info (12250): 2021.01.07.19:17:44 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:17:45 Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
|
|
Info (12250): 2021.01.07.19:17:45 Progress: Parameterizing module cic_ii_0
|
|
Info (12250): 2021.01.07.19:17:45 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:17:45 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:17:45 Progress: Validating
|
|
Info (12250): 2021.01.07.19:17:46 Progress: Done reading input file
|
|
Warning (12251): Rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release
|
|
Info (12250): Rx_cic: Generating rx_cic "rx_cic" for QUARTUS_SYNTH
|
|
Info (12250): Cic_ii_0: "rx_cic" instantiated altera_cic_ii "cic_ii_0"
|
|
Info (12250): Rx_cic: Done "rx_cic" with 2 modules, 30 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "rx_cic.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "tx_cic.qsys"
|
|
Info (12250): 2021.01.07.19:17:54 Progress: Loading FPGA/tx_cic.qsys
|
|
Info (12250): 2021.01.07.19:17:55 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:17:55 Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
|
|
Info (12250): 2021.01.07.19:17:56 Progress: Parameterizing module cic_ii_0
|
|
Info (12250): 2021.01.07.19:17:56 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:17:56 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:17:56 Progress: Validating
|
|
Info (12250): 2021.01.07.19:17:57 Progress: Done reading input file
|
|
Info (12250): Tx_cic: Generating tx_cic "tx_cic" for QUARTUS_SYNTH
|
|
Info (12250): Cic_ii_0: "tx_cic" instantiated altera_cic_ii "cic_ii_0"
|
|
Info (12250): Tx_cic: Done "tx_cic" with 2 modules, 30 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "tx_cic.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "tx_nco.qsys"
|
|
Info (12250): 2021.01.07.19:18:05 Progress: Loading FPGA/tx_nco.qsys
|
|
Info (12250): 2021.01.07.19:18:06 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:18:06 Progress: Adding nco_ii_0 [altera_nco_ii 18.1]
|
|
Info (12250): 2021.01.07.19:18:06 Progress: Parameterizing module nco_ii_0
|
|
Info (12250): 2021.01.07.19:18:06 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:18:06 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:18:07 Progress: Validating
|
|
Info (12250): 2021.01.07.19:18:08 Progress: Done reading input file
|
|
Info (12250): Tx_nco: Generating tx_nco "tx_nco" for QUARTUS_SYNTH
|
|
Info (12250): Nco_ii_0: "tx_nco" instantiated altera_nco_ii "nco_ii_0"
|
|
Info (12250): Tx_nco: Done "tx_nco" with 2 modules, 18 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "tx_nco.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "nco.qsys"
|
|
Info (12250): 2021.01.07.19:18:16 Progress: Loading FPGA/nco.qsys
|
|
Info (12250): 2021.01.07.19:18:17 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:18:17 Progress: Adding nco_ii_0 [altera_nco_ii 18.1]
|
|
Info (12250): 2021.01.07.19:18:17 Progress: Parameterizing module nco_ii_0
|
|
Info (12250): 2021.01.07.19:18:17 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:18:17 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:18:18 Progress: Validating
|
|
Info (12250): 2021.01.07.19:18:19 Progress: Done reading input file
|
|
Info (12250): Nco: Generating nco "nco" for QUARTUS_SYNTH
|
|
Info (12250): Nco_ii_0: "nco" instantiated altera_nco_ii "nco_ii_0"
|
|
Info (12250): Nco: Done "nco" with 2 modules, 18 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "nco.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "DEBUG.qsys"
|
|
Info (12250): 2021.01.07.19:18:27 Progress: Loading FPGA/DEBUG.qsys
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Parameterizing module in_system_sources_probes_0
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:18:28 Progress: Validating
|
|
Info (12250): 2021.01.07.19:18:29 Progress: Done reading input file
|
|
Info (12250): DEBUG: Generating DEBUG "DEBUG" for QUARTUS_SYNTH
|
|
Info (12250): In_system_sources_probes_0: "DEBUG" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
|
|
Info (12250): DEBUG: Done "DEBUG" with 2 modules, 2 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "DEBUG.qsys"
|
|
Info (12248): Elaborating Platform Designer system entity "DEBUG2.qsys"
|
|
Info (12250): 2021.01.07.19:18:37 Progress: Loading FPGA/DEBUG2.qsys
|
|
Info (12250): 2021.01.07.19:18:38 Progress: Reading input file
|
|
Info (12250): 2021.01.07.19:18:38 Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
|
Info (12250): 2021.01.07.19:18:39 Progress: Parameterizing module in_system_sources_probes_0
|
|
Info (12250): 2021.01.07.19:18:39 Progress: Building connections
|
|
Info (12250): 2021.01.07.19:18:39 Progress: Parameterizing connections
|
|
Info (12250): 2021.01.07.19:18:39 Progress: Validating
|
|
Info (12250): 2021.01.07.19:18:40 Progress: Done reading input file
|
|
Info (12250): DEBUG2: Generating DEBUG2 "DEBUG2" for QUARTUS_SYNTH
|
|
Info (12250): In_system_sources_probes_0: "DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
|
|
Info (12250): DEBUG2: Done "DEBUG2" with 2 modules, 2 files
|
|
Info (12249): Finished elaborating Platform Designer system entity "DEBUG2.qsys"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file wolf-lite.bdf
|
|
Info (12023): Found entity 1: WOLF-LITE
|
|
Info (12021): Found 1 design units, including 1 entities, in source file dac_corrector.v
|
|
Info (12023): Found entity 1: DAC_corrector File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/DAC_corrector.v Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file spi_interface.v
|
|
Info (12023): Found entity 1: spi_interface File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/spi_interface.v Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file stm32_interface.v
|
|
Info (12023): Found entity 1: stm32_interface File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/stm32_interface.v Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file data_shifter.v
|
|
Info (12023): Found entity 1: data_shifter File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file vcxo_controller.v
|
|
Info (12023): Found entity 1: vcxo_controller File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/vcxo_controller.v Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file mixer.v
|
|
Info (12023): Found entity 1: mixer File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mixer.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file mux16.v
|
|
Info (12023): Found entity 1: mux16 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux16.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file main_pll.v
|
|
Info (12023): Found entity 1: MAIN_PLL File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/MAIN_PLL.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file mux14.v
|
|
Info (12023): Found entity 1: mux14 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux14.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file mux1.v
|
|
Info (12023): Found entity 1: mux1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux1.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file tx_mixer.v
|
|
Info (12023): Found entity 1: tx_mixer File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_mixer.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file tx_summator.v
|
|
Info (12023): Found entity 1: tx_summator File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_summator.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file adc_latch.v
|
|
Info (12023): Found entity 1: ADC_Latch File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/ADC_Latch.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file dac_null.v
|
|
Info (12023): Found entity 1: dac_null File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dac_null.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file rx_ciccomp.v
|
|
Info (12023): Found entity 1: rx_ciccomp File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp.v Line: 8
|
|
Info (12021): Found 1 design units, including 0 entities, in source file rx_ciccomp/dspba_library_package.vhd
|
|
Info (12022): Found design unit 1: dspba_library_package (rx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library_package.vhd Line: 17
|
|
Info (12021): Found 6 design units, including 3 entities, in source file rx_ciccomp/dspba_library.vhd
|
|
Info (12022): Found design unit 1: dspba_delay-delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 34
|
|
Info (12022): Found design unit 2: dspba_sync_reg-sync_reg File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 117
|
|
Info (12022): Found design unit 3: dspba_pipe-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 356
|
|
Info (12023): Found entity 1: dspba_delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 18
|
|
Info (12023): Found entity 2: dspba_sync_reg File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 93
|
|
Info (12023): Found entity 3: dspba_pipe File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/dspba_library.vhd Line: 343
|
|
Info (12021): Found 2 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_math_pkg_hpfir (rx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd Line: 54
|
|
Info (12022): Found design unit 2: auk_dspip_math_pkg_hpfir-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd Line: 131
|
|
Info (12021): Found 1 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_lib_pkg_hpfir (rx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd Line: 22
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd Line: 64
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_controller_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd Line: 41
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd Line: 106
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_sink_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd Line: 56
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd Line: 109
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_source_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd Line: 70
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_roundsat_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_roundsat_hpfir-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd Line: 57
|
|
Info (12023): Found entity 1: auk_dspip_roundsat_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file rx_ciccomp/altera_avalon_sc_fifo.v
|
|
Info (12023): Found entity 1: altera_avalon_sc_fifo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/altera_avalon_sc_fifo.v Line: 21
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd
|
|
Info (12022): Found design unit 1: rx_ciccomp_0002_rtl_core-normal File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 47
|
|
Info (12023): Found entity 1: rx_ciccomp_0002_rtl_core File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 34
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_ast.vhd
|
|
Info (12022): Found design unit 1: rx_ciccomp_0002_ast-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 55
|
|
Info (12023): Found entity 1: rx_ciccomp_0002_ast File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 9
|
|
Info (12021): Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002.vhd
|
|
Info (12022): Found design unit 1: rx_ciccomp_0002-syn File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd Line: 33
|
|
Info (12023): Found entity 1: rx_ciccomp_0002 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd Line: 19
|
|
Info (12021): Found 1 design units, including 1 entities, in source file tx_ciccomp.v
|
|
Info (12023): Found entity 1: tx_ciccomp File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp.v Line: 8
|
|
Info (12021): Found 1 design units, including 0 entities, in source file tx_ciccomp/dspba_library_package.vhd
|
|
Info (12022): Found design unit 1: dspba_library_package (tx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library_package.vhd Line: 17
|
|
Info (12021): Found 6 design units, including 3 entities, in source file tx_ciccomp/dspba_library.vhd
|
|
Info (12022): Found design unit 1: dspba_delay-delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 34
|
|
Info (12022): Found design unit 2: dspba_sync_reg-sync_reg File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 117
|
|
Info (12022): Found design unit 3: dspba_pipe-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 356
|
|
Info (12023): Found entity 1: dspba_delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 18
|
|
Info (12023): Found entity 2: dspba_sync_reg File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 93
|
|
Info (12023): Found entity 3: dspba_pipe File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/dspba_library.vhd Line: 343
|
|
Info (12021): Found 2 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_math_pkg_hpfir (tx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd Line: 54
|
|
Info (12022): Found design unit 2: auk_dspip_math_pkg_hpfir-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd Line: 131
|
|
Info (12021): Found 1 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_lib_pkg_hpfir (tx_ciccomp) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd Line: 22
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd Line: 64
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_controller_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd Line: 41
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd Line: 106
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_sink_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd Line: 56
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd Line: 109
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_source_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd Line: 70
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_roundsat_hpfir.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_roundsat_hpfir-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd Line: 57
|
|
Info (12023): Found entity 1: auk_dspip_roundsat_hpfir File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file tx_ciccomp/altera_avalon_sc_fifo.v
|
|
Info (12023): Found entity 1: altera_avalon_sc_fifo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/altera_avalon_sc_fifo.v Line: 21
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd
|
|
Info (12022): Found design unit 1: tx_ciccomp_0002_rtl_core-normal File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 47
|
|
Info (12023): Found entity 1: tx_ciccomp_0002_rtl_core File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 34
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_ast.vhd
|
|
Info (12022): Found design unit 1: tx_ciccomp_0002_ast-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 55
|
|
Info (12023): Found entity 1: tx_ciccomp_0002_ast File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 9
|
|
Info (12021): Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002.vhd
|
|
Info (12022): Found design unit 1: tx_ciccomp_0002-syn File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd Line: 33
|
|
Info (12023): Found entity 1: tx_ciccomp_0002 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd Line: 19
|
|
Info (12021): Found 2 design units, including 2 entities, in source file diffclock_buff.v
|
|
Info (12023): Found entity 1: diffclock_buff_iobuf_in_k0j File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/diffclock_buff.v Line: 46
|
|
Info (12023): Found entity 2: diffclock_buff File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/diffclock_buff.v Line: 82
|
|
Info (12021): Found 1 design units, including 1 entities, in source file dcdc_pll.v
|
|
Info (12023): Found entity 1: dcdc_pll File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dcdc_pll.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file tx_pll.v
|
|
Info (12023): Found entity 1: tx_pll File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_pll.v Line: 39
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/clock_buffer/clock_buffer.v
|
|
Info (12023): Found entity 1: clock_buffer File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/clock_buffer/clock_buffer.v Line: 6
|
|
Info (12021): Found 2 design units, including 2 entities, in source file db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v
|
|
Info (12023): Found entity 1: clock_buffer_altclkctrl_0_sub File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v Line: 28
|
|
Info (12023): Found entity 2: clock_buffer_altclkctrl_0 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v Line: 89
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/rx_cic.v
|
|
Info (12023): Found entity 1: rx_cic File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/rx_cic.v Line: 6
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_core.sv
|
|
Info (12023): Found entity 1: alt_cic_core File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv Line: 27
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_miso.sv
|
|
Info (12023): Found entity 1: alt_cic_dec_miso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_miso.sv Line: 21
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_siso.sv
|
|
Info (12023): Found entity 1: alt_cic_dec_siso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 18
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_simo.sv
|
|
Info (12023): Found entity 1: alt_cic_int_simo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_int_simo.sv Line: 19
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_siso.sv
|
|
Info (12023): Found entity 1: alt_cic_int_siso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_int_siso.sv Line: 19
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv
|
|
Info (12022): Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (rx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv Line: 14
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_controller-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 53
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_controller File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_sink-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 64
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_sink File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd Line: 50
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_small_fifo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd Line: 27
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_source-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 57
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_source File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_channel_buffer-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 47
|
|
Info (12023): Found entity 1: auk_dspip_channel_buffer File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 26
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_cic_lib_pkg (rx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd Line: 23
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_delay.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_delay-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd Line: 79
|
|
Info (12023): Found entity 1: auk_dspip_delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd Line: 52
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_differentiator-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd Line: 82
|
|
Info (12023): Found entity 1: auk_dspip_differentiator File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd Line: 57
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_downsample.sv
|
|
Info (12023): Found entity 1: auk_dspip_downsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 14
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_fastadd-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd Line: 36
|
|
Info (12023): Found entity 1: auk_dspip_fastadd File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd Line: 19
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_fastaddsub-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd Line: 87
|
|
Info (12023): Found entity 1: auk_dspip_fastaddsub File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd Line: 69
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_integrator.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_integrator-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd Line: 74
|
|
Info (12023): Found entity 1: auk_dspip_integrator File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd Line: 53
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_lib_pkg (rx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd Line: 28
|
|
Info (12021): Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_math_pkg (rx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd Line: 51
|
|
Info (12022): Found design unit 2: auk_dspip_math_pkg-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd Line: 128
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_pipelined_adder-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd Line: 80
|
|
Info (12023): Found entity 1: auk_dspip_pipelined_adder File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd Line: 57
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_roundsat-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd Line: 61
|
|
Info (12023): Found entity 1: auk_dspip_roundsat File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd Line: 45
|
|
Info (12021): Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_text_pkg (rx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd Line: 60
|
|
Info (12022): Found design unit 2: auk_dspip_text_pkg-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd Line: 76
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_upsample.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_upsample-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd Line: 59
|
|
Info (12023): Found entity 1: auk_dspip_upsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd Line: 44
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv
|
|
Info (12023): Found entity 1: auk_dspip_variable_downsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv Line: 14
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/counter_module.sv
|
|
Info (12023): Found entity 1: counter_module File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/counter_module.sv Line: 17
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/hyper_pipeline_interface.v
|
|
Info (12023): Found entity 1: hyper_pipeline_interface File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/hyper_pipeline_interface.v Line: 20
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv
|
|
Info (12023): Found entity 1: rx_cic_cic_ii_0 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv Line: 15
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_core.sv
|
|
Info (12023): Found entity 1: alt_cic_core File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv Line: 27
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_miso.sv
|
|
Info (12023): Found entity 1: alt_cic_dec_miso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_miso.sv Line: 21
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_siso.sv
|
|
Info (12023): Found entity 1: alt_cic_dec_siso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_siso.sv Line: 18
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_simo.sv
|
|
Info (12023): Found entity 1: alt_cic_int_simo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_simo.sv Line: 19
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_siso.sv
|
|
Info (12023): Found entity 1: alt_cic_int_siso File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 19
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv
|
|
Info (12022): Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (tx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv Line: 14
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_controller-struct File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 53
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_controller File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_sink-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 64
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_sink File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd Line: 50
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_small_fifo File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd Line: 27
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_avalon_streaming_source-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 57
|
|
Info (12023): Found entity 1: auk_dspip_avalon_streaming_source File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 26
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_channel_buffer-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 47
|
|
Info (12023): Found entity 1: auk_dspip_channel_buffer File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 26
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_cic_lib_pkg (tx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd Line: 23
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_delay.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_delay-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd Line: 79
|
|
Info (12023): Found entity 1: auk_dspip_delay File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd Line: 52
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_differentiator-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd Line: 82
|
|
Info (12023): Found entity 1: auk_dspip_differentiator File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd Line: 57
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_downsample.sv
|
|
Info (12023): Found entity 1: auk_dspip_downsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_downsample.sv Line: 14
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_fastadd-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd Line: 36
|
|
Info (12023): Found entity 1: auk_dspip_fastadd File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd Line: 19
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_fastaddsub-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd Line: 87
|
|
Info (12023): Found entity 1: auk_dspip_fastaddsub File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd Line: 69
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_integrator.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_integrator-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd Line: 74
|
|
Info (12023): Found entity 1: auk_dspip_integrator File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd Line: 53
|
|
Info (12021): Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_lib_pkg (tx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd Line: 28
|
|
Info (12021): Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_math_pkg (tx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd Line: 51
|
|
Info (12022): Found design unit 2: auk_dspip_math_pkg-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd Line: 128
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_pipelined_adder-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd Line: 80
|
|
Info (12023): Found entity 1: auk_dspip_pipelined_adder File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd Line: 57
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_roundsat-beh File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd Line: 61
|
|
Info (12023): Found entity 1: auk_dspip_roundsat File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd Line: 45
|
|
Info (12021): Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_text_pkg (tx_cic) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd Line: 60
|
|
Info (12022): Found design unit 2: auk_dspip_text_pkg-body File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd Line: 76
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_upsample.vhd
|
|
Info (12022): Found design unit 1: auk_dspip_upsample-SYN File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd Line: 59
|
|
Info (12023): Found entity 1: auk_dspip_upsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd Line: 44
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv
|
|
Info (12023): Found entity 1: auk_dspip_variable_downsample File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv Line: 14
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/counter_module.sv
|
|
Info (12023): Found entity 1: counter_module File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/counter_module.sv Line: 17
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/hyper_pipeline_interface.v
|
|
Info (12023): Found entity 1: hyper_pipeline_interface File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/hyper_pipeline_interface.v Line: 20
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv
|
|
Info (12023): Found entity 1: tx_cic_cic_ii_0 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv Line: 15
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_cic/tx_cic.v
|
|
Info (12023): Found entity 1: tx_cic File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/tx_cic.v Line: 6
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_altqmcpipe.v
|
|
Info (12023): Found entity 1: asj_altqmcpipe File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v Line: 28
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_gam_dp.v
|
|
Info (12023): Found entity 1: asj_gam_dp File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_gam_dp.v Line: 45
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_cen.v
|
|
Info (12023): Found entity 1: asj_nco_as_m_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v
|
|
Info (12023): Found entity 1: asj_nco_as_m_dp_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v Line: 63
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_derot.v
|
|
Info (12023): Found entity 1: asj_nco_derot File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_derot.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_isdr.v
|
|
Info (12023): Found entity 1: asj_nco_isdr File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_madx_cen.v
|
|
Info (12023): Found entity 1: asj_nco_madx_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v Line: 14
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mady_cen.v
|
|
Info (12023): Found entity 1: asj_nco_mady_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v Line: 15
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mob_w.v
|
|
Info (12023): Found entity 1: asj_nco_mob_w File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v
|
|
Info (12023): Found entity 1: tx_nco_nco_ii_0 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 23
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/tx_nco/tx_nco.v
|
|
Info (12023): Found entity 1: tx_nco File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/tx_nco.v Line: 6
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/nco.v
|
|
Info (12023): Found entity 1: nco File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/nco.v Line: 6
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_altqmcpipe.v
|
|
Info (12023): Found entity 1: asj_altqmcpipe File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v Line: 28
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_gam_dp.v
|
|
Info (12023): Found entity 1: asj_gam_dp File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_gam_dp.v Line: 45
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_cen.v
|
|
Info (12023): Found entity 1: asj_nco_as_m_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_dp_cen.v
|
|
Info (12023): Found entity 1: asj_nco_as_m_dp_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v Line: 63
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_derot.v
|
|
Info (12023): Found entity 1: asj_nco_derot File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_derot.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_isdr.v
|
|
Info (12023): Found entity 1: asj_nco_isdr File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_isdr.v Line: 41
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_madx_cen.v
|
|
Info (12023): Found entity 1: asj_nco_madx_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v Line: 14
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mady_cen.v
|
|
Info (12023): Found entity 1: asj_nco_mady_cen File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v Line: 15
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mob_w.v
|
|
Info (12023): Found entity 1: asj_nco_mob_w File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v Line: 41
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/nco_nco_ii_0.v
|
|
Info (12023): Found entity 1: nco_nco_ii_0 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 23
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/debug/debug.v
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|
Info (12023): Found entity 1: DEBUG File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/debug.v Line: 6
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/debug/submodules/altsource_probe_top.v
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|
Info (12023): Found entity 1: altsource_probe_top File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/submodules/altsource_probe_top.v Line: 14
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/debug2/debug2.v
|
|
Info (12023): Found entity 1: DEBUG2 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug2/debug2.v Line: 6
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/debug2/submodules/altsource_probe_top.v
|
|
Info (12023): Found entity 1: altsource_probe_top File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug2/submodules/altsource_probe_top.v Line: 14
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|
Info (12127): Elaborating entity "WOLF-LITE" for the top level hierarchy
|
|
Info (12128): Elaborating entity "stm32_interface" for hierarchy "stm32_interface:STM32_INTERFACE"
|
|
Info (12128): Elaborating entity "tx_summator" for hierarchy "tx_summator:TX_SUMMATOR"
|
|
Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_summator.v Line: 73
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|
Info (12130): Elaborated megafunction instantiation "tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_summator.v Line: 73
|
|
Info (12133): Instantiated megafunction "tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_summator.v Line: 73
|
|
Info (12134): Parameter "lpm_direction" = "ADD"
|
|
Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
|
|
Info (12134): Parameter "lpm_pipeline" = "1"
|
|
Info (12134): Parameter "lpm_representation" = "SIGNED"
|
|
Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB"
|
|
Info (12134): Parameter "lpm_width" = "32"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_1vk.tdf
|
|
Info (12023): Found entity 1: add_sub_1vk File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_1vk.tdf Line: 22
|
|
Info (12128): Elaborating entity "add_sub_1vk" for hierarchy "tx_summator:TX_SUMMATOR|lpm_add_sub:LPM_ADD_SUB_component|add_sub_1vk:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 118
|
|
Info (12128): Elaborating entity "tx_pll" for hierarchy "tx_pll:TX_PLL"
|
|
Info (12128): Elaborating entity "altpll" for hierarchy "tx_pll:TX_PLL|altpll:altpll_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_pll.v Line: 90
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|
Info (12130): Elaborated megafunction instantiation "tx_pll:TX_PLL|altpll:altpll_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_pll.v Line: 90
|
|
Info (12133): Instantiated megafunction "tx_pll:TX_PLL|altpll:altpll_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_pll.v Line: 90
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|
Info (12134): Parameter "bandwidth_type" = "AUTO"
|
|
Info (12134): Parameter "clk0_divide_by" = "2"
|
|
Info (12134): Parameter "clk0_duty_cycle" = "50"
|
|
Info (12134): Parameter "clk0_multiply_by" = "5"
|
|
Info (12134): Parameter "clk0_phase_shift" = "0"
|
|
Info (12134): Parameter "compensate_clock" = "CLK0"
|
|
Info (12134): Parameter "inclk0_input_frequency" = "15547"
|
|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
|
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=tx_pll"
|
|
Info (12134): Parameter "lpm_type" = "altpll"
|
|
Info (12134): Parameter "operation_mode" = "NORMAL"
|
|
Info (12134): Parameter "pll_type" = "AUTO"
|
|
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_inclk0" = "PORT_USED"
|
|
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_locked" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk0" = "PORT_USED"
|
|
Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "width_clock" = "5"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/tx_pll_altpll.v
|
|
Info (12023): Found entity 1: tx_pll_altpll File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/tx_pll_altpll.v Line: 29
|
|
Info (12128): Elaborating entity "tx_pll_altpll" for hierarchy "tx_pll:TX_PLL|altpll:altpll_component|tx_pll_altpll:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 897
|
|
Info (12128): Elaborating entity "clock_buffer" for hierarchy "clock_buffer:SYSCLK_BUFFER"
|
|
Info (12128): Elaborating entity "clock_buffer_altclkctrl_0" for hierarchy "clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/clock_buffer/clock_buffer.v Line: 14
|
|
Info (12128): Elaborating entity "clock_buffer_altclkctrl_0_sub" for hierarchy "clock_buffer:SYSCLK_BUFFER|clock_buffer_altclkctrl_0:altclkctrl_0|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v Line: 112
|
|
Info (12128): Elaborating entity "tx_mixer" for hierarchy "tx_mixer:TX_MIXER_I"
|
|
Info (12128): Elaborating entity "lpm_mult" for hierarchy "tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_mixer.v Line: 63
|
|
Info (12130): Elaborated megafunction instantiation "tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_mixer.v Line: 63
|
|
Info (12133): Instantiated megafunction "tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_mixer.v Line: 63
|
|
Info (12134): Parameter "lpm_hint" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
|
|
Info (12134): Parameter "lpm_pipeline" = "1"
|
|
Info (12134): Parameter "lpm_representation" = "SIGNED"
|
|
Info (12134): Parameter "lpm_type" = "LPM_MULT"
|
|
Info (12134): Parameter "lpm_widtha" = "16"
|
|
Info (12134): Parameter "lpm_widthb" = "16"
|
|
Info (12134): Parameter "lpm_widthp" = "32"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_abt.tdf
|
|
Info (12023): Found entity 1: mult_abt File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_abt.tdf Line: 28
|
|
Info (12128): Elaborating entity "mult_abt" for hierarchy "tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component|mult_abt:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 376
|
|
Info (12128): Elaborating entity "tx_cic" for hierarchy "tx_cic:TX_CIC_I"
|
|
Info (12128): Elaborating entity "tx_cic_cic_ii_0" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/tx_cic.v Line: 31
|
|
Info (12128): Elaborating entity "alt_cic_core" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv Line: 213
|
|
Info (12128): Elaborating entity "auk_dspip_avalon_streaming_sink" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv Line: 326
|
|
Info (12128): Elaborating entity "scfifo" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
|
|
Info (12130): Elaborated megafunction instantiation "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
|
|
Info (12133): Instantiated megafunction "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
|
|
Info (12134): Parameter "add_ram_output_register" = "ON"
|
|
Info (12134): Parameter "allow_rwcycle_when_full" = "OFF"
|
|
Info (12134): Parameter "almost_empty_value" = "4"
|
|
Info (12134): Parameter "almost_full_value" = "0"
|
|
Info (12134): Parameter "lpm_numwords" = "8"
|
|
Info (12134): Parameter "lpm_showahead" = "OFF"
|
|
Info (12134): Parameter "lpm_width" = "18"
|
|
Info (12134): Parameter "lpm_widthu" = "3"
|
|
Info (12134): Parameter "overflow_checking" = "ON"
|
|
Info (12134): Parameter "underflow_checking" = "ON"
|
|
Info (12134): Parameter "use_eab" = "ON"
|
|
Info (12134): Parameter "lpm_hint" = "UNUSED"
|
|
Info (12134): Parameter "lpm_type" = "scfifo"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_gf71.tdf
|
|
Info (12023): Found entity 1: scfifo_gf71 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_gf71.tdf Line: 24
|
|
Info (12128): Elaborating entity "scfifo_gf71" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_1lv.tdf
|
|
Info (12023): Found entity 1: a_dpfifo_1lv File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 32
|
|
Info (12128): Elaborating entity "a_dpfifo_1lv" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_gf71.tdf Line: 36
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_l7h1.tdf
|
|
Info (12023): Found entity 1: altsyncram_l7h1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_l7h1.tdf Line: 27
|
|
Info (12128): Elaborating entity "altsyncram_l7h1" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 44
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_gs8.tdf
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|
Info (12023): Found entity 1: cmpr_gs8 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_gs8.tdf Line: 22
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|
Info (12128): Elaborating entity "cmpr_gs8" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cmpr_gs8:almost_full_comparer" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 52
|
|
Info (12128): Elaborating entity "cmpr_gs8" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cmpr_gs8:two_comparison" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 53
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_r9b.tdf
|
|
Info (12023): Found entity 1: cntr_r9b File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_r9b.tdf Line: 25
|
|
Info (12128): Elaborating entity "cntr_r9b" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_r9b:rd_ptr_msb" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 54
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_8a7.tdf
|
|
Info (12023): Found entity 1: cntr_8a7 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_8a7.tdf Line: 25
|
|
Info (12128): Elaborating entity "cntr_8a7" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_8a7:usedw_counter" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 55
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_s9b.tdf
|
|
Info (12023): Found entity 1: cntr_s9b File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_s9b.tdf Line: 25
|
|
Info (12128): Elaborating entity "cntr_s9b" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|cntr_s9b:wr_ptr" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_1lv.tdf Line: 56
|
|
Info (12128): Elaborating entity "auk_dspip_avalon_streaming_source" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv Line: 358
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|
Info (12128): Elaborating entity "scfifo" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
|
|
Info (12130): Elaborated megafunction instantiation "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
|
|
Info (12133): Instantiated megafunction "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
|
|
Info (12134): Parameter "add_ram_output_register" = "ON"
|
|
Info (12134): Parameter "allow_rwcycle_when_full" = "OFF"
|
|
Info (12134): Parameter "almost_empty_value" = "0"
|
|
Info (12134): Parameter "almost_full_value" = "13"
|
|
Info (12134): Parameter "lpm_numwords" = "21"
|
|
Info (12134): Parameter "lpm_showahead" = "OFF"
|
|
Info (12134): Parameter "lpm_width" = "17"
|
|
Info (12134): Parameter "lpm_widthu" = "5"
|
|
Info (12134): Parameter "overflow_checking" = "ON"
|
|
Info (12134): Parameter "underflow_checking" = "ON"
|
|
Info (12134): Parameter "use_eab" = "ON"
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Info (12134): Parameter "lpm_hint" = "UNUSED"
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Info (12134): Parameter "lpm_type" = "scfifo"
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Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ci71.tdf
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Info (12023): Found entity 1: scfifo_ci71 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ci71.tdf Line: 24
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Info (12128): Elaborating entity "scfifo_ci71" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299
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Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_9qv.tdf
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Info (12023): Found entity 1: a_dpfifo_9qv File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 32
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Info (12128): Elaborating entity "a_dpfifo_9qv" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ci71.tdf Line: 36
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hah1.tdf
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Info (12023): Found entity 1: altsyncram_hah1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_hah1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_hah1" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 44
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Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_is8.tdf
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Info (12023): Found entity 1: cmpr_is8 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_is8.tdf Line: 22
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Info (12128): Elaborating entity "cmpr_is8" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cmpr_is8:almost_full_comparer" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 52
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Info (12128): Elaborating entity "cmpr_is8" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cmpr_is8:two_comparison" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 53
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Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_t9b.tdf
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Info (12023): Found entity 1: cntr_t9b File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_t9b.tdf Line: 25
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Info (12128): Elaborating entity "cntr_t9b" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_t9b:rd_ptr_msb" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 54
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Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_aa7.tdf
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Info (12023): Found entity 1: cntr_aa7 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_aa7.tdf Line: 25
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Info (12128): Elaborating entity "cntr_aa7" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_aa7:usedw_counter" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 55
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Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_u9b.tdf
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Info (12023): Found entity 1: cntr_u9b File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_u9b.tdf Line: 25
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Info (12128): Elaborating entity "cntr_u9b" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|cntr_u9b:wr_ptr" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_9qv.tdf Line: 56
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_controller" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv Line: 408
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_small_fifo" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 196
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Info (12128): Elaborating entity "alt_cic_int_siso" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv Line: 540
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Info (12128): Elaborating entity "counter_module" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 270
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Info (12128): Elaborating entity "counter_module" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 298
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Info (12128): Elaborating entity "counter_module" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 313
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Info (12128): Elaborating entity "auk_dspip_differentiator" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 361
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Info (12128): Elaborating entity "auk_dspip_delay" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd Line: 135
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Info (12128): Elaborating entity "auk_dspip_upsample" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_upsample:first_upsample" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 379
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Info (12128): Elaborating entity "auk_dspip_integrator" for hierarchy "tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|auk_dspip_integrator:integrator_loop[0].auK_integrator" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 408
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Info (12128): Elaborating entity "data_shifter" for hierarchy "data_shifter:TX_CICCOMP_GAINER"
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 18
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 19
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 20
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 21
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Info (12128): Elaborating entity "tx_ciccomp" for hierarchy "tx_ciccomp:TX_CICCOMP_I"
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Info (12128): Elaborating entity "tx_ciccomp_0002" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp.v Line: 28
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Info (12128): Elaborating entity "tx_ciccomp_0002_ast" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd Line: 62
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_sink_hpfir" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 89
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_source_hpfir" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 109
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_controller_hpfir" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 137
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Info (12128): Elaborating entity "tx_ciccomp_0002_rtl_core" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 218
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 175
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 180
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 286
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 291
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Info (12128): Elaborating entity "altsyncram" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 313
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Info (12130): Elaborated megafunction instantiation "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 313
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Info (12133): Instantiated megafunction "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 313
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Info (12134): Parameter "address_aclr_a" = "UNUSED"
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|
Info (12134): Parameter "address_aclr_b" = "NONE"
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|
Info (12134): Parameter "address_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "byte_size" = "8"
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Info (12134): Parameter "byteena_aclr_a" = "UNUSED"
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Info (12134): Parameter "byteena_aclr_b" = "NONE"
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|
Info (12134): Parameter "byteena_reg_b" = "CLOCK0"
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Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN"
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Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN"
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|
Info (12134): Parameter "clock_enable_input_a" = "NORMAL"
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|
Info (12134): Parameter "clock_enable_input_b" = "NORMAL"
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|
Info (12134): Parameter "clock_enable_output_a" = "NORMAL"
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|
Info (12134): Parameter "clock_enable_output_b" = "NORMAL"
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|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE"
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Info (12134): Parameter "enable_ecc" = "FALSE"
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Info (12134): Parameter "implement_in_les" = "OFF"
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Info (12134): Parameter "indata_aclr_a" = "UNUSED"
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Info (12134): Parameter "indata_aclr_b" = "NONE"
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Info (12134): Parameter "indata_reg_b" = "CLOCK0"
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Info (12134): Parameter "init_file" = "UNUSED"
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Info (12134): Parameter "init_file_layout" = "PORT_A"
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Info (12134): Parameter "maximum_depth" = "0"
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Info (12134): Parameter "numwords_a" = "64"
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Info (12134): Parameter "numwords_b" = "64"
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Info (12134): Parameter "operation_mode" = "DUAL_PORT"
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Info (12134): Parameter "outdata_aclr_a" = "NONE"
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Info (12134): Parameter "outdata_aclr_b" = "NONE"
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Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
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Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
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Info (12134): Parameter "power_up_uninitialized" = "FALSE"
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Info (12134): Parameter "ram_block_type" = "M9K"
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Info (12134): Parameter "rdcontrol_aclr_b" = "NONE"
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Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0"
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Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
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Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
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Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON"
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|
Info (12134): Parameter "width_a" = "16"
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|
Info (12134): Parameter "width_b" = "16"
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|
Info (12134): Parameter "width_byteena_a" = "1"
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Info (12134): Parameter "width_byteena_b" = "1"
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|
Info (12134): Parameter "width_eccstatus" = "3"
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Info (12134): Parameter "widthad_a" = "6"
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Info (12134): Parameter "widthad_b" = "6"
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|
Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED"
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|
Info (12134): Parameter "wrcontrol_aclr_b" = "NONE"
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Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
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Info (12134): Parameter "lpm_hint" = "UNUSED"
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Info (12134): Parameter "lpm_type" = "altsyncram"
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0mn3.tdf
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Info (12023): Found entity 1: altsyncram_0mn3 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_0mn3.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_0mn3" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem|altsyncram_0mn3:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "lpm_mult" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 446
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Info (12130): Elaborated megafunction instantiation "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 446
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Info (12133): Instantiated megafunction "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 446
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Info (12134): Parameter "LPM_WIDTHA" = "8"
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Info (12134): Parameter "LPM_WIDTHB" = "16"
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Info (12134): Parameter "LPM_WIDTHS" = "1"
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Info (12134): Parameter "LPM_WIDTHP" = "24"
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Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
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Info (12134): Parameter "LPM_PIPELINE" = "2"
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Info (12134): Parameter "LPM_TYPE" = "LPM_MULT"
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Info (12134): Parameter "LPM_HINT" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5"
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Info (12021): Found 1 design units, including 1 entities, in source file db/mult_ncu.tdf
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Info (12023): Found entity 1: mult_ncu File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_ncu.tdf Line: 28
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Info (12128): Elaborating entity "mult_ncu" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 376
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 502
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd Line: 537
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Info (12128): Elaborating entity "auk_dspip_roundsat_hpfir" for hierarchy "tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 244
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Info (12128): Elaborating entity "tx_nco" for hierarchy "tx_nco:TX_NCO"
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Info (12128): Elaborating entity "tx_nco_nco_ii_0" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/tx_nco.v Line: 24
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Info (12128): Elaborating entity "asj_altqmcpipe" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 304
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Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12134): Parameter "lpm_direction" = "ADD"
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Info (12134): Parameter "lpm_width" = "22"
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Info (12134): Parameter "lpm_pipeline" = "1"
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Info (12134): Parameter "lpm_representation" = "UNSIGNED"
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Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_u4i.tdf
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Info (12023): Found entity 1: add_sub_u4i File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_u4i.tdf Line: 22
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Info (12128): Elaborating entity "add_sub_u4i" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 118
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Info (12128): Elaborating entity "asj_gam_dp" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 326
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Info (12128): Elaborating entity "asj_nco_as_m_dp_cen" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 338
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Info (12128): Elaborating entity "altsyncram" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
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Info (12134): Parameter "width_a" = "16"
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Info (12134): Parameter "widthad_a" = "11"
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Info (12134): Parameter "numwords_a" = "2048"
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Info (12134): Parameter "width_b" = "16"
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Info (12134): Parameter "widthad_b" = "11"
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Info (12134): Parameter "numwords_b" = "2048"
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Info (12134): Parameter "lpm_type" = "altsyncram"
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Info (12134): Parameter "width_byteena_a" = "1"
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|
Info (12134): Parameter "width_byteena_b" = "1"
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|
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
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Info (12134): Parameter "outdata_aclr_a" = "NONE"
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|
Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "indata_aclr_a" = "NONE"
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|
Info (12134): Parameter "wrcontrol_aclr_a" = "NONE"
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|
Info (12134): Parameter "address_aclr_a" = "NONE"
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|
Info (12134): Parameter "indata_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "address_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "indata_aclr_b" = "NONE"
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|
Info (12134): Parameter "wrcontrol_aclr_b" = "NONE"
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|
Info (12134): Parameter "address_aclr_b" = "NONE"
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|
Info (12134): Parameter "outdata_aclr_b" = "NONE"
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|
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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|
Info (12134): Parameter "ram_block_type" = "AUTO"
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|
Info (12134): Parameter "init_file" = "tx_nco_nco_ii_0_sin_c.hex"
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|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4k82.tdf
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Info (12023): Found entity 1: altsyncram_4k82 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_4k82.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_4k82" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4k82:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_as_m_cen" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 350
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Info (12128): Elaborating entity "altsyncram" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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|
Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12134): Parameter "operation_mode" = "ROM"
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|
Info (12134): Parameter "width_a" = "16"
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|
Info (12134): Parameter "widthad_a" = "11"
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|
Info (12134): Parameter "numwords_a" = "2048"
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Info (12134): Parameter "width_byteena_a" = "1"
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|
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
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|
Info (12134): Parameter "outdata_aclr_a" = "NONE"
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|
Info (12134): Parameter "address_aclr_a" = "NONE"
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|
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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|
Info (12134): Parameter "ram_block_type" = "AUTO"
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|
Info (12134): Parameter "init_file" = "tx_nco_nco_ii_0_sin_f.hex"
|
|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_u8a1.tdf
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Info (12023): Found entity 1: altsyncram_u8a1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_u8a1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_u8a1" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_u8a1:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_as_m_cen" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 362
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Info (12128): Elaborating entity "altsyncram" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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|
Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v Line: 65
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|
Info (12134): Parameter "operation_mode" = "ROM"
|
|
Info (12134): Parameter "width_a" = "16"
|
|
Info (12134): Parameter "widthad_a" = "11"
|
|
Info (12134): Parameter "numwords_a" = "2048"
|
|
Info (12134): Parameter "width_byteena_a" = "1"
|
|
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
|
|
Info (12134): Parameter "outdata_aclr_a" = "NONE"
|
|
Info (12134): Parameter "address_aclr_a" = "NONE"
|
|
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
|
|
Info (12134): Parameter "ram_block_type" = "AUTO"
|
|
Info (12134): Parameter "init_file" = "tx_nco_nco_ii_0_cos_f.hex"
|
|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_p8a1.tdf
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|
Info (12023): Found entity 1: altsyncram_p8a1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_p8a1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_p8a1" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_p8a1:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_madx_cen" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 377
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|
Info (12128): Elaborating entity "asj_nco_mady_cen" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 389
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Info (12128): Elaborating entity "asj_nco_derot" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_derot:ux0136" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 402
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Info (12128): Elaborating entity "asj_nco_mob_w" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 410
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Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v Line: 75
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|
Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v Line: 75
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|
Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v Line: 75
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|
Info (12134): Parameter "lpm_width" = "16"
|
|
Info (12134): Parameter "lpm_direction" = "ADD"
|
|
Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB"
|
|
Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO"
|
|
Info (12134): Parameter "lpm_pipeline" = "1"
|
|
Info (12134): Parameter "lpm_representation" = "SIGNED"
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_jpk.tdf
|
|
Info (12023): Found entity 1: add_sub_jpk File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_jpk.tdf Line: 22
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|
Info (12128): Elaborating entity "add_sub_jpk" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_jpk:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 118
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|
Info (12128): Elaborating entity "asj_nco_isdr" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v Line: 428
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|
Info (12128): Elaborating entity "lpm_counter" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v Line: 59
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|
Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v Line: 59
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|
Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v Line: 59
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|
Info (12134): Parameter "lpm_width" = "4"
|
|
Info (12134): Parameter "lpm_type" = "LPM_COUNTER"
|
|
Info (12134): Parameter "lpm_direction" = "UP"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_asi.tdf
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|
Info (12023): Found entity 1: cntr_asi File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_asi.tdf Line: 25
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|
Info (12128): Elaborating entity "cntr_asi" for hierarchy "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component|cntr_asi:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_counter.tdf Line: 258
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|
Info (12128): Elaborating entity "spi_interface" for hierarchy "spi_interface:FLASH"
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|
Info (12128): Elaborating entity "rx_ciccomp" for hierarchy "rx_ciccomp:RX_CICCOMP_I"
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Info (12128): Elaborating entity "rx_ciccomp_0002" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp.v Line: 28
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|
Info (12128): Elaborating entity "rx_ciccomp_0002_ast" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd Line: 62
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_sink_hpfir" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 89
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_source_hpfir" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 109
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_controller_hpfir" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 137
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Info (12128): Elaborating entity "rx_ciccomp_0002_rtl_core" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 218
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 159
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 164
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 270
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Info (12128): Elaborating entity "dspba_delay" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 275
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Info (12128): Elaborating entity "auk_dspip_roundsat_hpfir" for hierarchy "rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_roundsat_hpfir:\real_passthrough:gen_outp_blk:0:outp_blk" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 244
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Info (12128): Elaborating entity "data_shifter" for hierarchy "data_shifter:CIC_GAINER"
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 18
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 19
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 20
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Warning (10230): Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16) File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/data_shifter.v Line: 21
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Info (12128): Elaborating entity "rx_cic" for hierarchy "rx_cic:RX_CIC_I"
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Info (12128): Elaborating entity "rx_cic_cic_ii_0" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/rx_cic.v Line: 32
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Info (12128): Elaborating entity "alt_cic_core" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv Line: 213
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_sink" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv Line: 326
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Info (12128): Elaborating entity "scfifo" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
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Info (12130): Elaborated megafunction instantiation "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
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Info (12133): Instantiated megafunction "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd Line: 123
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Info (12134): Parameter "add_ram_output_register" = "ON"
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Info (12134): Parameter "allow_rwcycle_when_full" = "OFF"
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Info (12134): Parameter "almost_empty_value" = "4"
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Info (12134): Parameter "almost_full_value" = "0"
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Info (12134): Parameter "lpm_numwords" = "8"
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Info (12134): Parameter "lpm_showahead" = "OFF"
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Info (12134): Parameter "lpm_width" = "25"
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Info (12134): Parameter "lpm_widthu" = "3"
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Info (12134): Parameter "overflow_checking" = "ON"
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Info (12134): Parameter "underflow_checking" = "ON"
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Info (12134): Parameter "use_eab" = "ON"
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Info (12134): Parameter "lpm_hint" = "UNUSED"
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Info (12134): Parameter "lpm_type" = "scfifo"
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Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ef71.tdf
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Info (12023): Found entity 1: scfifo_ef71 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ef71.tdf Line: 24
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Info (12128): Elaborating entity "scfifo_ef71" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299
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Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_vkv.tdf
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Info (12023): Found entity 1: a_dpfifo_vkv File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_vkv.tdf Line: 32
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Info (12128): Elaborating entity "a_dpfifo_vkv" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ef71.tdf Line: 36
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h7h1.tdf
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Info (12023): Found entity 1: altsyncram_h7h1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_h7h1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_h7h1" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_vkv.tdf Line: 44
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_source" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv Line: 358
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Info (12128): Elaborating entity "scfifo" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
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Info (12130): Elaborated megafunction instantiation "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
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Info (12133): Instantiated megafunction "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd Line: 116
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Info (12134): Parameter "add_ram_output_register" = "ON"
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Info (12134): Parameter "allow_rwcycle_when_full" = "OFF"
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Info (12134): Parameter "almost_empty_value" = "0"
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Info (12134): Parameter "almost_full_value" = "13"
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Info (12134): Parameter "lpm_numwords" = "21"
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Info (12134): Parameter "lpm_showahead" = "OFF"
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Info (12134): Parameter "lpm_width" = "87"
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Info (12134): Parameter "lpm_widthu" = "5"
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Info (12134): Parameter "overflow_checking" = "ON"
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Info (12134): Parameter "underflow_checking" = "ON"
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Info (12134): Parameter "use_eab" = "ON"
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Info (12134): Parameter "lpm_hint" = "UNUSED"
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Info (12134): Parameter "lpm_type" = "scfifo"
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Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ji71.tdf
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Info (12023): Found entity 1: scfifo_ji71 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ji71.tdf Line: 24
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Info (12128): Elaborating entity "scfifo_ji71" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299
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Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_gqv.tdf
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Info (12023): Found entity 1: a_dpfifo_gqv File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_gqv.tdf Line: 32
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Info (12128): Elaborating entity "a_dpfifo_gqv" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_ji71.tdf Line: 36
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vah1.tdf
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Info (12023): Found entity 1: altsyncram_vah1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_vah1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_vah1" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ji71:auto_generated|a_dpfifo_gqv:dpfifo|altsyncram_vah1:FIFOram" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_gqv.tdf Line: 44
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_controller" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv Line: 408
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Info (12128): Elaborating entity "auk_dspip_avalon_streaming_small_fifo" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_controller:avalon_controller|auk_dspip_avalon_streaming_small_fifo:ready_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd Line: 196
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Info (12128): Elaborating entity "alt_cic_dec_siso" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv Line: 475
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Info (12128): Elaborating entity "auk_dspip_integrator" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 275
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Info (12128): Elaborating entity "auk_dspip_delay" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd Line: 97
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Info (12128): Elaborating entity "auk_dspip_downsample" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 330
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Info (12128): Elaborating entity "counter_module" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 50
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Info (12128): Elaborating entity "counter_module" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 79
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Info (12128): Elaborating entity "auk_dspip_channel_buffer" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 367
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Info (12128): Elaborating entity "scfifo" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 89
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Info (12130): Elaborated megafunction instantiation "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 89
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Info (12133): Instantiated megafunction "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd Line: 89
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Info (12134): Parameter "add_ram_output_register" = "ON"
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Info (12134): Parameter "allow_rwcycle_when_full" = "OFF"
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Info (12134): Parameter "almost_empty_value" = "0"
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Info (12134): Parameter "almost_full_value" = "0"
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Info (12134): Parameter "lpm_numwords" = "3"
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Info (12134): Parameter "lpm_showahead" = "OFF"
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Info (12134): Parameter "lpm_width" = "86"
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Info (12134): Parameter "lpm_widthu" = "2"
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Info (12134): Parameter "overflow_checking" = "ON"
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Info (12134): Parameter "underflow_checking" = "ON"
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Info (12134): Parameter "use_eab" = "ON"
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Info (12134): Parameter "lpm_hint" = "UNUSED"
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Info (12134): Parameter "lpm_type" = "scfifo"
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Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_qm51.tdf
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Info (12023): Found entity 1: scfifo_qm51 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_qm51.tdf Line: 24
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Info (12128): Elaborating entity "scfifo_qm51" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299
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Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_5ku.tdf
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Info (12023): Found entity 1: a_dpfifo_5ku File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 32
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Info (12128): Elaborating entity "a_dpfifo_5ku" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/scfifo_qm51.tdf Line: 34
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m7h1.tdf
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Info (12023): Found entity 1: altsyncram_m7h1 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_m7h1" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 42
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Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_fs8.tdf
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Info (12023): Found entity 1: cmpr_fs8 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cmpr_fs8.tdf Line: 22
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Info (12128): Elaborating entity "cmpr_fs8" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cmpr_fs8:almost_full_comparer" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 50
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Info (12128): Elaborating entity "cmpr_fs8" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cmpr_fs8:two_comparison" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 51
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Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_q9b.tdf
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Info (12023): Found entity 1: cntr_q9b File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_q9b.tdf Line: 25
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Info (12128): Elaborating entity "cntr_q9b" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_q9b:rd_ptr_msb" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 52
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_7a7.tdf
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Info (12023): Found entity 1: cntr_7a7 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/cntr_7a7.tdf Line: 25
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Info (12128): Elaborating entity "cntr_7a7" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|cntr_7a7:usedw_counter" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/a_dpfifo_5ku.tdf Line: 53
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Info (12128): Elaborating entity "counter_module" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 419
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Info (12128): Elaborating entity "counter_module" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 432
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Info (12128): Elaborating entity "auk_dspip_differentiator" for hierarchy "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 658
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Info (12128): Elaborating entity "nco" for hierarchy "nco:RX_NCO"
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Info (12128): Elaborating entity "nco_nco_ii_0" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/nco.v Line: 24
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Info (12128): Elaborating entity "asj_altqmcpipe" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 304
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Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v Line: 63
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Info (12134): Parameter "lpm_direction" = "ADD"
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Info (12134): Parameter "lpm_width" = "22"
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Info (12134): Parameter "lpm_pipeline" = "1"
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Info (12134): Parameter "lpm_representation" = "UNSIGNED"
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Info (12128): Elaborating entity "asj_gam_dp" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_gam_dp:ux008" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 326
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Info (12128): Elaborating entity "asj_nco_as_m_dp_cen" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 338
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Info (12128): Elaborating entity "altsyncram" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v Line: 109
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Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
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Info (12134): Parameter "width_a" = "12"
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Info (12134): Parameter "widthad_a" = "11"
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Info (12134): Parameter "numwords_a" = "2048"
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Info (12134): Parameter "width_b" = "12"
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Info (12134): Parameter "widthad_b" = "11"
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Info (12134): Parameter "numwords_b" = "2048"
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Info (12134): Parameter "lpm_type" = "altsyncram"
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Info (12134): Parameter "width_byteena_a" = "1"
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Info (12134): Parameter "width_byteena_b" = "1"
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Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
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Info (12134): Parameter "outdata_aclr_a" = "NONE"
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Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
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Info (12134): Parameter "indata_aclr_a" = "NONE"
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Info (12134): Parameter "wrcontrol_aclr_a" = "NONE"
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Info (12134): Parameter "address_aclr_a" = "NONE"
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Info (12134): Parameter "indata_reg_b" = "CLOCK0"
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Info (12134): Parameter "address_reg_b" = "CLOCK0"
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Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
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|
Info (12134): Parameter "indata_aclr_b" = "NONE"
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|
Info (12134): Parameter "wrcontrol_aclr_b" = "NONE"
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Info (12134): Parameter "address_aclr_b" = "NONE"
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|
Info (12134): Parameter "outdata_aclr_b" = "NONE"
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Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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|
Info (12134): Parameter "ram_block_type" = "AUTO"
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Info (12134): Parameter "init_file" = "nco_nco_ii_0_sin_c.hex"
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Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h982.tdf
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Info (12023): Found entity 1: altsyncram_h982 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_h982.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_h982" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_h982:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_as_m_cen" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 350
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Info (12128): Elaborating entity "altsyncram" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12134): Parameter "operation_mode" = "ROM"
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|
Info (12134): Parameter "width_a" = "12"
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|
Info (12134): Parameter "widthad_a" = "11"
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Info (12134): Parameter "numwords_a" = "2048"
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|
Info (12134): Parameter "width_byteena_a" = "1"
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|
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
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|
Info (12134): Parameter "outdata_aclr_a" = "NONE"
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|
Info (12134): Parameter "address_aclr_a" = "NONE"
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Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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|
Info (12134): Parameter "ram_block_type" = "AUTO"
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|
Info (12134): Parameter "init_file" = "nco_nco_ii_0_sin_f.hex"
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|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fu91.tdf
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Info (12023): Found entity 1: altsyncram_fu91 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_fu91.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_fu91" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_fu91:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_as_m_cen" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 362
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Info (12128): Elaborating entity "altsyncram" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v Line: 65
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Info (12134): Parameter "operation_mode" = "ROM"
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|
Info (12134): Parameter "width_a" = "12"
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|
Info (12134): Parameter "widthad_a" = "11"
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|
Info (12134): Parameter "numwords_a" = "2048"
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|
Info (12134): Parameter "width_byteena_a" = "1"
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|
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
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Info (12134): Parameter "outdata_aclr_a" = "NONE"
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|
Info (12134): Parameter "address_aclr_a" = "NONE"
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|
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
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|
Info (12134): Parameter "ram_block_type" = "AUTO"
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|
Info (12134): Parameter "init_file" = "nco_nco_ii_0_cos_f.hex"
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|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_au91.tdf
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Info (12023): Found entity 1: altsyncram_au91 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_au91.tdf Line: 27
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Info (12128): Elaborating entity "altsyncram_au91" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_au91:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
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Info (12128): Elaborating entity "asj_nco_madx_cen" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 377
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Info (12128): Elaborating entity "asj_nco_mady_cen" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 389
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Info (12128): Elaborating entity "asj_nco_derot" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_derot:ux0136" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 402
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Info (12128): Elaborating entity "asj_nco_mob_w" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 410
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Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v Line: 75
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v Line: 75
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v Line: 75
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Info (12134): Parameter "lpm_width" = "12"
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|
Info (12134): Parameter "lpm_direction" = "ADD"
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|
Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB"
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|
Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO"
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|
Info (12134): Parameter "lpm_pipeline" = "1"
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|
Info (12134): Parameter "lpm_representation" = "SIGNED"
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_fpk.tdf
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|
Info (12023): Found entity 1: add_sub_fpk File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/add_sub_fpk.tdf Line: 22
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Info (12128): Elaborating entity "add_sub_fpk" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_fpk:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 118
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Info (12128): Elaborating entity "asj_nco_isdr" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v Line: 428
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Info (12128): Elaborating entity "lpm_counter" for hierarchy "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_isdr.v Line: 59
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Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_isdr.v Line: 59
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Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_isdr.v Line: 59
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Info (12134): Parameter "lpm_width" = "4"
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|
Info (12134): Parameter "lpm_type" = "LPM_COUNTER"
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|
Info (12134): Parameter "lpm_direction" = "UP"
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|
Info (12128): Elaborating entity "mixer" for hierarchy "mixer:RX_MIXER_I"
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Info (12128): Elaborating entity "lpm_mult" for hierarchy "mixer:RX_MIXER_I|lpm_mult:lpm_mult_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mixer.v Line: 63
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Info (12130): Elaborated megafunction instantiation "mixer:RX_MIXER_I|lpm_mult:lpm_mult_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mixer.v Line: 63
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Info (12133): Instantiated megafunction "mixer:RX_MIXER_I|lpm_mult:lpm_mult_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mixer.v Line: 63
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Info (12134): Parameter "lpm_hint" = "MAXIMIZE_SPEED=5"
|
|
Info (12134): Parameter "lpm_pipeline" = "1"
|
|
Info (12134): Parameter "lpm_representation" = "SIGNED"
|
|
Info (12134): Parameter "lpm_type" = "LPM_MULT"
|
|
Info (12134): Parameter "lpm_widtha" = "12"
|
|
Info (12134): Parameter "lpm_widthb" = "12"
|
|
Info (12134): Parameter "lpm_widthp" = "24"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_jnp.tdf
|
|
Info (12023): Found entity 1: mult_jnp File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_jnp.tdf Line: 28
|
|
Info (12128): Elaborating entity "mult_jnp" for hierarchy "mixer:RX_MIXER_I|lpm_mult:lpm_mult_component|mult_jnp:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 376
|
|
Info (12128): Elaborating entity "MAIN_PLL" for hierarchy "MAIN_PLL:MAIN_PLL"
|
|
Info (12128): Elaborating entity "altpll" for hierarchy "MAIN_PLL:MAIN_PLL|altpll:altpll_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/MAIN_PLL.v Line: 94
|
|
Info (12130): Elaborated megafunction instantiation "MAIN_PLL:MAIN_PLL|altpll:altpll_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/MAIN_PLL.v Line: 94
|
|
Info (12133): Instantiated megafunction "MAIN_PLL:MAIN_PLL|altpll:altpll_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/MAIN_PLL.v Line: 94
|
|
Info (12134): Parameter "bandwidth_type" = "AUTO"
|
|
Info (12134): Parameter "clk0_divide_by" = "335"
|
|
Info (12134): Parameter "clk0_duty_cycle" = "50"
|
|
Info (12134): Parameter "clk0_multiply_by" = "64"
|
|
Info (12134): Parameter "clk0_phase_shift" = "0"
|
|
Info (12134): Parameter "clk1_divide_by" = "1340"
|
|
Info (12134): Parameter "clk1_duty_cycle" = "50"
|
|
Info (12134): Parameter "clk1_multiply_by" = "1"
|
|
Info (12134): Parameter "clk1_phase_shift" = "0"
|
|
Info (12134): Parameter "compensate_clock" = "CLK0"
|
|
Info (12134): Parameter "inclk0_input_frequency" = "15547"
|
|
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
|
|
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=MAIN_PLL"
|
|
Info (12134): Parameter "lpm_type" = "altpll"
|
|
Info (12134): Parameter "operation_mode" = "NORMAL"
|
|
Info (12134): Parameter "pll_type" = "AUTO"
|
|
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_inclk0" = "PORT_USED"
|
|
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_locked" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk0" = "PORT_USED"
|
|
Info (12134): Parameter "port_clk1" = "PORT_USED"
|
|
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
|
|
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
|
|
Info (12134): Parameter "width_clock" = "5"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/main_pll_altpll.v
|
|
Info (12023): Found entity 1: MAIN_PLL_altpll File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/main_pll_altpll.v Line: 29
|
|
Info (12128): Elaborating entity "MAIN_PLL_altpll" for hierarchy "MAIN_PLL:MAIN_PLL|altpll:altpll_component|MAIN_PLL_altpll:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 897
|
|
Info (12128): Elaborating entity "mux14" for hierarchy "mux14:DAC_MUX"
|
|
Info (12128): Elaborating entity "lpm_mux" for hierarchy "mux14:DAC_MUX|lpm_mux:LPM_MUX_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux14.v Line: 68
|
|
Info (12130): Elaborated megafunction instantiation "mux14:DAC_MUX|lpm_mux:LPM_MUX_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux14.v Line: 68
|
|
Info (12133): Instantiated megafunction "mux14:DAC_MUX|lpm_mux:LPM_MUX_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/mux14.v Line: 68
|
|
Info (12134): Parameter "lpm_size" = "2"
|
|
Info (12134): Parameter "lpm_type" = "LPM_MUX"
|
|
Info (12134): Parameter "lpm_width" = "14"
|
|
Info (12134): Parameter "lpm_widths" = "1"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf
|
|
Info (12023): Found entity 1: mux_rsc File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mux_rsc.tdf Line: 22
|
|
Info (12128): Elaborating entity "mux_rsc" for hierarchy "mux14:DAC_MUX|lpm_mux:LPM_MUX_component|mux_rsc:auto_generated" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.tdf Line: 86
|
|
Info (12128): Elaborating entity "dac_null" for hierarchy "dac_null:DAC_IDLE"
|
|
Info (12128): Elaborating entity "lpm_constant" for hierarchy "dac_null:DAC_IDLE|lpm_constant:LPM_CONSTANT_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dac_null.v Line: 48
|
|
Info (12130): Elaborated megafunction instantiation "dac_null:DAC_IDLE|lpm_constant:LPM_CONSTANT_component" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dac_null.v Line: 48
|
|
Info (12133): Instantiated megafunction "dac_null:DAC_IDLE|lpm_constant:LPM_CONSTANT_component" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/dac_null.v Line: 48
|
|
Info (12134): Parameter "lpm_cvalue" = "8192"
|
|
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
|
|
Info (12134): Parameter "lpm_type" = "LPM_CONSTANT"
|
|
Info (12134): Parameter "lpm_width" = "14"
|
|
Info (12128): Elaborating entity "DAC_corrector" for hierarchy "DAC_corrector:DAC_CORRECTOR"
|
|
Info (12128): Elaborating entity "DEBUG" for hierarchy "DEBUG:DBG_ADC"
|
|
Info (12128): Elaborating entity "altsource_probe_top" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/debug.v Line: 19
|
|
Info (12128): Elaborating entity "altsource_probe" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/submodules/altsource_probe_top.v Line: 55
|
|
Info (12130): Elaborated megafunction instantiation "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/submodules/altsource_probe_top.v Line: 55
|
|
Info (12133): Instantiated megafunction "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/debug/submodules/altsource_probe_top.v Line: 55
|
|
Info (12134): Parameter "lpm_type" = "altsource_probe"
|
|
Info (12134): Parameter "lpm_hint" = "UNUSED"
|
|
Info (12134): Parameter "sld_auto_instance_index" = "YES"
|
|
Info (12134): Parameter "sld_instance_index" = "0"
|
|
Info (12134): Parameter "SLD_NODE_INFO" = "4746752"
|
|
Info (12134): Parameter "sld_ir_width" = "4"
|
|
Info (12134): Parameter "instance_id" = "ADC"
|
|
Info (12134): Parameter "probe_width" = "12"
|
|
Info (12134): Parameter "source_width" = "0"
|
|
Info (12134): Parameter "source_initial_value" = "0"
|
|
Info (12134): Parameter "enable_metastability" = "NO"
|
|
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|sld_jtag_endpoint_adapter:jtag_signal_adapter" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v Line: 168
|
|
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232
|
|
Info (12128): Elaborating entity "altsource_probe_body" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v Line: 280
|
|
Info (12128): Elaborating entity "altsource_probe_impl" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd Line: 507
|
|
Info (12128): Elaborating entity "sld_rom_sr" for hierarchy "DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl|altsource_probe_body:altsource_probe_body_inst|altsource_probe_impl:\wider_probe_gen:wider_probe_inst|sld_rom_sr:\instance_id_gen:rom_info_inst" File: c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd Line: 755
|
|
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
|
|
Info (11172): 2021.01.07.19:19:16 Progress: Loading sld0b974a4e/alt_sld_fab_wrapper_hw.tcl
|
|
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
|
|
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
|
|
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
|
|
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
|
|
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
|
|
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
|
|
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
|
|
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
|
|
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/alt_sld_fab.v
|
|
Info (12023): Found entity 1: alt_sld_fab File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/alt_sld_fab.v Line: 9
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v Line: 9
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
|
|
Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 102
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3
|
|
Info (12205): 1 design partition requires Analysis and Synthesis
|
|
Info (12211): Partition "Top" requires synthesis because there were changes to its dependent source files
|
|
Info (12207): 1 design partition does not require synthesis
|
|
Info (12229): Partition "sld_hub:auto_hub" does not require synthesis because there were no relevant design changes
|
|
Info (278001): Inferred 8 megafunctions from design logic
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|Mult0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v Line: 50
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v Line: 52
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|Mult0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v Line: 51
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|Mult0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v Line: 50
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v Line: 52
|
|
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|Mult0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v Line: 51
|
|
Info (12130): Elaborated megafunction instantiation "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (12133): Instantiated megafunction "tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (12134): Parameter "LPM_WIDTHA" = "16"
|
|
Info (12134): Parameter "LPM_WIDTHB" = "16"
|
|
Info (12134): Parameter "LPM_WIDTHP" = "32"
|
|
Info (12134): Parameter "LPM_WIDTHR" = "32"
|
|
Info (12134): Parameter "LPM_WIDTHS" = "1"
|
|
Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
|
|
Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
|
|
Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
|
|
Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_36t.tdf
|
|
Info (12023): Found entity 1: mult_36t File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_36t.tdf Line: 28
|
|
Info (12130): Elaborated megafunction instantiation "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (12133): Instantiated megafunction "nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v Line: 51
|
|
Info (12134): Parameter "LPM_WIDTHA" = "12"
|
|
Info (12134): Parameter "LPM_WIDTHB" = "12"
|
|
Info (12134): Parameter "LPM_WIDTHP" = "24"
|
|
Info (12134): Parameter "LPM_WIDTHR" = "24"
|
|
Info (12134): Parameter "LPM_WIDTHS" = "1"
|
|
Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
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Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
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Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
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Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
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Info (12021): Found 1 design units, including 1 entities, in source file db/mult_t5t.tdf
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Info (12023): Found entity 1: mult_t5t File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mult_t5t.tdf Line: 28
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Info (270023): Converted the following 2 logical RAM block slices to logic cells
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Info (270022): Converted the following logical RAM block "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ALTSYNCRAM" slices to logic cells
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a10" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 359
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a9" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 327
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a8" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 295
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a11" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 391
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a5" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 199
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a6" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 231
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a4" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 167
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a7" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 263
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a2" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 103
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 71
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 39
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a3" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 135
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 455
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a14" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 487
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a12" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 423
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a15" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 519
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a21" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 711
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a22" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 743
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a20" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 679
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a23" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 775
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a26" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 871
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a25" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 839
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a24" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 807
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a27" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 903
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a18" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 615
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a17" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 583
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a16" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 551
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a19" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 647
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a29" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 967
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a30" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 999
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a28" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 935
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a31" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1031
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a42" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1383
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a41" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1351
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a40" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1319
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a43" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1415
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a37" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1223
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a38" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1255
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a36" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1191
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a39" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1287
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a34" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1127
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a33" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1095
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a32" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1063
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a35" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1159
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a45" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1479
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a46" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1511
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a44" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1447
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a47" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1543
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a53" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1735
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a54" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1767
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a52" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1703
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a55" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1799
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a58" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1895
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a57" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1863
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a56" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1831
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a59" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1927
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a50" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1639
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a49" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1607
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a48" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1575
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a51" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1671
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a61" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1991
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a62" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2023
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a60" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1959
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a63" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2055
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a74" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2407
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a73" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2375
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a72" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2343
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a75" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2439
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a69" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2247
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a70" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2279
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a68" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2215
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a71" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2311
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a66" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2151
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a65" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2119
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a64" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2087
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a67" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2183
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a77" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2503
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a78" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2535
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a76" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2471
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a79" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2567
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a82" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2663
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a81" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2631
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a80" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2599
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a83" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2695
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a84" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2727
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Info (270019): RAM block slice "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a85" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2759
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Info (270022): Converted the following logical RAM block "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ALTSYNCRAM" slices to logic cells
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a5" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 199
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a6" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 231
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a4" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 167
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a7" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 263
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a10" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 359
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a9" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 327
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a8" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 295
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a11" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 391
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a2" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 103
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a1" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 71
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 39
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a3" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 135
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a13" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 455
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a14" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 487
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a12" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 423
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a15" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 519
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a26" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 871
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a25" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 839
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a24" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 807
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a27" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 903
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a21" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 711
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a22" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 743
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a20" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 679
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a23" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 775
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a18" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 615
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a17" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 583
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a16" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 551
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a19" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 647
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a29" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 967
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a30" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 999
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a28" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 935
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a31" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1031
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a37" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1223
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a38" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1255
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a36" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1191
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a39" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1287
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a42" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1383
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a41" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1351
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a40" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1319
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a43" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1415
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a34" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1127
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a33" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1095
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a32" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1063
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a35" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1159
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a45" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1479
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a46" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1511
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a44" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1447
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a47" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1543
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a58" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1895
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a57" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1863
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a56" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1831
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a59" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1927
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a53" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1735
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a54" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1767
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a52" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1703
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a55" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1799
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a50" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1639
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a49" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1607
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a48" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1575
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a51" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1671
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a61" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1991
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a62" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2023
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a60" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 1959
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a63" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2055
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a69" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2247
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a70" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2279
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a68" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2215
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a71" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2311
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a74" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2407
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a73" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2375
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a72" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2343
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a75" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2439
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a66" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2151
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a65" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2119
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a64" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2087
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a67" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2183
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a77" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2503
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a78" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2535
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a76" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2471
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a79" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2567
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a81" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2631
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a82" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2663
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a80" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2599
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a83" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2695
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a84" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2727
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Info (270019): RAM block slice "rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|ram_block1a85" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 2759
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Info (12130): Elaborated megafunction instantiation "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 39
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Info (12133): Instantiated megafunction "rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_channel_buffer:fifo_regulator|scfifo:buffer_FIFO|scfifo_qm51:auto_generated|a_dpfifo_5ku:dpfifo|altsyncram_m7h1:FIFOram|altsyncram:ram_block1a0" with the following parameter: File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_m7h1.tdf Line: 39
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Info (12134): Parameter "LPM_TYPE" = "altsyncram"
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Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
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Info (12134): Parameter "WIDTH_A" = "86"
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Info (12134): Parameter "WIDTHAD_A" = "2"
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Info (12134): Parameter "NUMWORDS_A" = "4"
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Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
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Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
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Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
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Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
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Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
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Info (12134): Parameter "BYTEENA_ACLR_A" = "NONE"
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Info (12134): Parameter "CLOCK_ENABLE_INPUT_A" = "BYPASS"
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Info (12134): Parameter "CLOCK_ENABLE_OUTPUT_A" = "BYPASS"
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Info (12134): Parameter "WIDTH_B" = "86"
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Info (12134): Parameter "WIDTHAD_B" = "2"
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Info (12134): Parameter "NUMWORDS_B" = "4"
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Info (12134): Parameter "INDATA_REG_B" = "UNUSED"
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Info (12134): Parameter "WRCONTROL_WRADDRESS_REG_B" = "CLOCK1"
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Info (12134): Parameter "RDCONTROL_REG_B" = "CLOCK1"
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Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
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Info (12134): Parameter "BYTEENA_REG_B" = "UNUSED"
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Info (12134): Parameter "OUTDATA_REG_B" = "CLOCK1"
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Info (12134): Parameter "INDATA_ACLR_B" = "NONE"
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Info (12134): Parameter "WRCONTROL_ACLR_B" = "NONE"
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Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
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Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
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Info (12134): Parameter "RDCONTROL_ACLR_B" = "NONE"
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Info (12134): Parameter "BYTEENA_ACLR_B" = "NONE"
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Info (12134): Parameter "CLOCK_ENABLE_INPUT_B" = "BYPASS"
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Info (12134): Parameter "CLOCK_ENABLE_OUTPUT_B" = "NORMAL"
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Info (12134): Parameter "WIDTH_BYTEENA_A" = "1"
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Info (12134): Parameter "WIDTH_BYTEENA_B" = "1"
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Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
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Info (12134): Parameter "BYTE_SIZE" = "8"
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Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "DONT_CARE"
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Info (12134): Parameter "INIT_FILE" = ""
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Info (12134): Parameter "INIT_FILE_LAYOUT" = "PORT_B"
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Info (12134): Parameter "MAXIMUM_DEPTH" = "4"
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Info (12134): Parameter "ENABLE_RUNTIME_MOD" = "NO"
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Info (12134): Parameter "INSTANCE_NAME" = "UNUSED"
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Info (12134): Parameter "ENABLE_ECC" = "FALSE"
|
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Info (12134): Parameter "ECCSTATUS_REG" = "UNREGISTERED"
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Info (12134): Parameter "CLOCK_ENABLE_CORE_A" = "BYPASS"
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Info (12134): Parameter "CLOCK_ENABLE_CORE_B" = "BYPASS"
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Info (12134): Parameter "READ_DURING_WRITE_MODE_PORT_A" = "NEW_DATA_WITH_NBE_READ"
|
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Info (12134): Parameter "READ_DURING_WRITE_MODE_PORT_B" = "NEW_DATA_WITH_NBE_READ"
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Info (12134): Parameter "CLOCK_ENABLE_ECC_STATUS" = "NORMAL"
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Info (12134): Parameter "IMPLEMENT_IN_LES" = "ON"
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Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nci3.tdf
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Info (12023): Found entity 1: altsyncram_nci3 File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/altsyncram_nci3.tdf Line: 28
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|
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
|
|
Info (12023): Found entity 1: decode_msa File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/decode_msa.tdf Line: 22
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_sob.tdf
|
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Info (12023): Found entity 1: mux_sob File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/mux_sob.tdf Line: 22
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|
Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
|
Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition
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Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "speed" technology mapper which leaves 102 WYSIWYG logic cells and I/Os untouched
|
|
Info (13000): Registers with preset signals will power-up high File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd Line: 283
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Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
|
|
Info (286031): Timing-Driven Synthesis is running on partition "Top"
|
|
Info (17049): 39 registers lost all their fanouts during netlist optimizations.
|
|
Info (128000): Starting physical synthesis optimizations for speed
|
|
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
|
|
Info (332111): Found 5 clocks
|
|
Info (332111): Period Clock Name
|
|
Info (332111): ======== ============
|
|
Info (332111): 15.547 clk_sys
|
|
Info (332111): 40.000 clock_stm32
|
|
Info (332111): 81.378 MAIN_PLL|altpll_component|auto_generated|pll1|clk[0]
|
|
Info (332111): 20832.980 MAIN_PLL|altpll_component|auto_generated|pll1|clk[1]
|
|
Info (332111): 6.218 TX_PLL|altpll_component|auto_generated|pll1|clk[0]
|
|
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
|
|
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
|
|
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:02
|
|
Info (21057): Implemented 10677 device resources after synthesis - the final resource count might be different
|
|
Info (21058): Implemented 33 input pins
|
|
Info (21059): Implemented 41 output pins
|
|
Info (21060): Implemented 8 bidirectional pins
|
|
Info (21061): Implemented 10130 logic cells
|
|
Info (21064): Implemented 430 RAM segments
|
|
Info (21065): Implemented 2 PLLs
|
|
Info (21062): Implemented 32 DSP elements
|
|
Warning (20013): Ignored 16 assignments for entity "DEBUG2" -- entity does not exist in design
|
|
Info (144001): Generated suppressed messages file D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/output_files/WOLF-LITE.map.smsg
|
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 11 warnings
|
|
Info: Peak virtual memory: 5011 megabytes
|
|
Info: Processing ended: Thu Jan 07 18:20:02 2021
|
|
Info: Elapsed time: 00:02:48
|
|
Info: Total CPU time (on all processors): 00:04:43
|
|
|
|
|
|
+------------------------------------------+
|
|
; Analysis & Synthesis Suppressed Messages ;
|
|
+------------------------------------------+
|
|
The suppressed messages can be found in D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/output_files/WOLF-LITE.map.smsg.
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