kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
83 wiersze
2.7 KiB
VHDL
83 wiersze
2.7 KiB
VHDL
-- (C) 2001-2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files from any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License Subscription
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-- Agreement, Intel FPGA IP License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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library IEEE;
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use IEEE.std_logic_1164.all;
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use work.auk_dspip_lib_pkg_hpfir.all;
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use work.auk_dspip_math_pkg_hpfir.all;
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entity tx_ciccomp_0002 is
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port (
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clk : in STD_LOGIC;
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reset_n : in STD_LOGIC;
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ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
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ast_sink_valid : in STD_LOGIC;
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ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
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ast_source_data : out STD_LOGIC_VECTOR(30 * 1*1 - 1 downto 0);
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ast_source_valid : out STD_LOGIC;
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ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
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);
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end tx_ciccomp_0002;
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architecture syn of tx_ciccomp_0002 is
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component tx_ciccomp_0002_ast
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port (
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clk : in STD_LOGIC;
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reset_n : in STD_LOGIC;
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ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
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ast_sink_valid : in STD_LOGIC;
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ast_sink_ready : out STD_LOGIC;
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ast_sink_sop : in STD_LOGIC;
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ast_sink_eop : in STD_LOGIC;
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ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
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ast_source_data : out STD_LOGIC_VECTOR(1*30 * 1 - 1 downto 0);
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ast_source_ready : in STD_LOGIC;
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ast_source_valid : out STD_LOGIC;
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ast_source_sop : out STD_LOGIC;
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ast_source_eop : out STD_LOGIC;
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ast_source_channel : out STD_LOGIC_VECTOR(log2_ceil_one(1) - 1 downto 0);
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ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
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);
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end component;
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signal coeff_in_read_sig : std_logic;
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begin
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coeff_in_read_sig <= '1';
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tx_ciccomp_0002_ast_inst : tx_ciccomp_0002_ast
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port map (
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clk => clk,
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reset_n => reset_n,
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ast_sink_data => ast_sink_data,
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ast_source_data => ast_source_data,
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ast_sink_valid => ast_sink_valid,
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ast_sink_ready => open,
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ast_source_ready => '1',
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ast_source_valid => ast_source_valid,
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ast_sink_sop => '0',
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ast_sink_eop => '0',
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ast_sink_error => ast_sink_error,
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ast_source_sop => open,
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ast_source_eop => open,
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ast_source_channel => open,
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ast_source_error => ast_source_error
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);
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end syn;
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