kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
73 wiersze
2.6 KiB
VHDL
73 wiersze
2.6 KiB
VHDL
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing device programming or simulation files), and
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-- any associated documentation or information are expressly subject to the
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-- terms and conditions of the Intel FPGA Software License Agreement,
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-- Intel MegaCore Function License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for the sole
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-- purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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library IEEE;
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use IEEE.std_logic_1164.all;
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package dspba_library_package is
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component dspba_delay is
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generic (
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width : natural := 8;
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depth : natural := 1;
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reset_high : std_logic := '1';
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reset_kind : string := "ASYNC"
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);
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port (
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clk : in std_logic;
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aclr : in std_logic;
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ena : in std_logic := '1';
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xin : in std_logic_vector(width-1 downto 0);
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xout : out std_logic_vector(width-1 downto 0)
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);
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end component;
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component dspba_sync_reg is
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generic (
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width1 : natural := 8;
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width2 : natural := 8;
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depth : natural := 2;
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init_value : std_logic_vector;
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pulse_multiplier : natural := 1;
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counter_width : natural := 8;
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reset1_high : std_logic := '1';
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reset2_high : std_logic := '1';
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reset_kind : string := "ASYNC"
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);
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port (
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clk1 : in std_logic;
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aclr1 : in std_logic;
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ena : in std_logic_vector(0 downto 0);
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xin : in std_logic_vector(width1-1 downto 0);
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xout : out std_logic_vector(width1-1 downto 0);
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clk2 : in std_logic;
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aclr2 : in std_logic;
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sxout : out std_logic_vector(width2-1 downto 0)
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);
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end component;
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component dspba_pipe is
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generic(
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num_bits : positive;
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num_stages : natural;
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init_value : std_logic := 'X'
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);
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port(
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clk: in std_logic;
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d : in std_logic_vector(num_bits-1 downto 0);
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q : out std_logic_vector(num_bits-1 downto 0)
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);
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end component dspba_pipe;
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end dspba_library_package;
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