kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
32 wiersze
1.5 KiB
XML
32 wiersze
1.5 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file path="tx_ciccomp_sim/dspba_library_package.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/dspba_library.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/auk_dspip_math_pkg_hpfir.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/auk_dspip_lib_pkg_hpfir.vhd" type="VHDL" />
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<file
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path="tx_ciccomp_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"
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type="VHDL" />
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<file
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path="tx_ciccomp_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd"
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type="VHDL" />
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<file
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path="tx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"
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type="VHDL" />
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<file path="tx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/altera_avalon_sc_fifo.v" type="VERILOG" />
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<file path="tx_ciccomp_sim/tx_ciccomp_rtl_core.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/tx_ciccomp_ast.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/tx_ciccomp.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/tx_ciccomp_nativelink.tcl" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_msim.tcl" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_tb.vhd" type="VHDL" />
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<file path="tx_ciccomp_sim/tx_ciccomp_mlab.m" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_model.m" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_coef_int.txt" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_input.txt" type="OTHER" />
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<file path="tx_ciccomp_sim/tx_ciccomp_param.txt" type="OTHER" />
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<topLevel name="tx_ciccomp" />
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<deviceFamily name="cycloneive" />
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</simPackage>
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