kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
386 wiersze
6.9 KiB
Verilog
386 wiersze
6.9 KiB
Verilog
module stm32_interface(
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clk_in,
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RX_I,
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RX_Q,
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DATA_SYNC,
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ADC_OTR,
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DAC_OTR,
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ADC_IN,
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adcclk_in,
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FLASH_data_in,
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FLASH_busy,
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IQ_valid,
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DATA_BUS,
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NCO_freq,
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preamp_enable,
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rx,
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tx,
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TX_I,
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TX_Q,
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reset_n,
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stage_debug,
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FLASH_data_out,
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FLASH_enable,
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FLASH_continue_read,
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CIC_GAIN,
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CICFIR_GAIN,
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TX_CICFIR_GAIN,
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DAC_GAIN,
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tx_iq_valid,
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TX_NCO_freq,
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ATT_05,
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ATT_1,
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ATT_2,
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ATT_4,
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ATT_8,
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ATT_16,
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BPF_A,
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BPF_B,
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BPF_OE1,
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BPF_OE2,
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LPF_1,
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LPF_2,
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LPF_3
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);
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input clk_in;
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input signed [15:0] RX_I;
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input signed [15:0] RX_Q;
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input DATA_SYNC;
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input ADC_OTR;
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input DAC_OTR;
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input signed [11:0] ADC_IN;
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input adcclk_in;
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input unsigned [7:0] FLASH_data_in;
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input FLASH_busy;
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input IQ_valid;
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output reg unsigned [21:0] NCO_freq = 242347;
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output reg unsigned [21:0] TX_NCO_freq = 242347;
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output reg preamp_enable = 0;
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output reg rx = 1;
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output reg tx = 0;
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output reg reset_n = 1;
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output reg signed [15:0] TX_I = 'd0;
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output reg signed [15:0] TX_Q = 'd0;
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output reg [15:0] stage_debug = 0;
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output reg unsigned [7:0] FLASH_data_out = 0;
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output reg FLASH_enable = 0;
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output reg FLASH_continue_read = 0;
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output reg unsigned [7:0] CIC_GAIN = 32;
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output reg unsigned [7:0] CICFIR_GAIN = 32;
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output reg unsigned [7:0] TX_CICFIR_GAIN = 32;
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output reg unsigned [7:0] DAC_GAIN = 32;
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output reg tx_iq_valid = 0;
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output reg ATT_05 = 0;
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output reg ATT_1 = 0;
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output reg ATT_2 = 0;
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output reg ATT_4 = 0;
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output reg ATT_8 = 0;
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output reg ATT_16 = 0;
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output reg BPF_A = 0;
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output reg BPF_B = 0;
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output reg BPF_OE1 = 0;
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output reg BPF_OE2 = 0;
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output reg LPF_1 = 0;
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output reg LPF_2 = 0;
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output reg LPF_3 = 0;
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inout [7:0] DATA_BUS;
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reg [7:0] DATA_BUS_OUT;
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reg DATA_BUS_OE; // 1 - out 0 - in
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assign DATA_BUS = DATA_BUS_OE ? DATA_BUS_OUT : 8'bZ ;
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parameter rx_buffer_length = (8 - 1);
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reg signed [15:0] BUFFER_RX_I [0:rx_buffer_length];
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reg signed [15:0] BUFFER_RX_Q [0:rx_buffer_length];
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reg signed [15:0] BUFFER_RX_head = 'd0;
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reg signed [15:0] BUFFER_RX_tail = 'd0;
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reg signed [15:0] k = 'd1;
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reg signed [15:0] REG_RX_I;
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reg signed [15:0] REG_RX_Q;
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reg signed [15:0] I_HOLD;
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reg signed [15:0] Q_HOLD;
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reg signed [11:0] ADC_MIN;
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reg signed [11:0] ADC_MAX;
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reg ADC_MINMAX_RESET;
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reg sync_reset_n = 1;
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always @ (posedge IQ_valid)
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begin
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BUFFER_RX_I[BUFFER_RX_head][15:0] = RX_I[15:0];
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BUFFER_RX_Q[BUFFER_RX_head][15:0] = RX_Q[15:0];
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if(BUFFER_RX_head >= rx_buffer_length)
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BUFFER_RX_head = 0;
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else
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BUFFER_RX_head = BUFFER_RX_head + 16'd1;
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end
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always @ (posedge clk_in)
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begin
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//начало передачи
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if (DATA_SYNC == 1)
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begin
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DATA_BUS_OE = 0;
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ADC_MINMAX_RESET = 0;
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FLASH_continue_read = 0;
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if(DATA_BUS[7:0] == 'd0) //BUS TEST
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begin
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k = 500;
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end
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else if(DATA_BUS[7:0] == 'd1) //GET PARAMS
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begin
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k = 100;
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end
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else if(DATA_BUS[7:0] == 'd2) //SEND PARAMS
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begin
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DATA_BUS_OE = 1;
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k = 200;
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end
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else if(DATA_BUS[7:0] == 'd3) //TX IQ
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begin
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tx_iq_valid = 0;
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k = 300;
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end
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else if(DATA_BUS[7:0] == 'd4) //RX IQ
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begin
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DATA_BUS_OE = 1;
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k = 400;
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end
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else if(DATA_BUS[7:0] == 'd5) //RESET ON
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begin
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sync_reset_n = 0;
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k = 999;
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end
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else if(DATA_BUS[7:0] == 'd6) //RESET OFF
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begin
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sync_reset_n = 1;
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k = 999;
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end
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else if(DATA_BUS[7:0] == 'd7) //FPGA FLASH READ
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begin
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FLASH_enable = 0;
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k = 700;
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end
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end
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else if (k == 100) //GET PARAMS
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begin
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rx = DATA_BUS[0:0];
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tx = !rx;
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preamp_enable = DATA_BUS[1:1];
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ATT_05 = DATA_BUS[2:2];
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ATT_1 = DATA_BUS[3:3];
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ATT_2 = DATA_BUS[4:4];
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ATT_4 = DATA_BUS[5:5];
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ATT_8 = DATA_BUS[6:6];
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ATT_16 = DATA_BUS[7:7];
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k = 101;
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end
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else if (k == 101)
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begin
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NCO_freq[21:16] = DATA_BUS[5:0];
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k = 102;
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end
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else if (k == 102)
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begin
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NCO_freq[15:8] = DATA_BUS[7:0];
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k = 103;
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end
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else if (k == 103)
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begin
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NCO_freq[7:0] = DATA_BUS[7:0];
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k = 104;
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end
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else if (k == 104)
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begin
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CIC_GAIN[7:0] = DATA_BUS[7:0];
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k = 105;
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end
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else if (k == 105)
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begin
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CICFIR_GAIN[7:0] = DATA_BUS[7:0];
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k = 106;
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end
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else if (k == 106)
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begin
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TX_CICFIR_GAIN[7:0] = DATA_BUS[7:0];
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k = 107;
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end
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else if (k == 107)
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begin
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DAC_GAIN[7:0] = DATA_BUS[7:0];
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k = 108;
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end
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else if (k == 108)
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begin
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TX_NCO_freq[21:16] = DATA_BUS[5:0];
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k = 109;
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end
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else if (k == 109)
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begin
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TX_NCO_freq[15:8] = DATA_BUS[7:0];
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k = 110;
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end
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else if (k == 110)
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begin
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TX_NCO_freq[7:0] = DATA_BUS[7:0];
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k = 111;
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end
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else if (k == 111)
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begin
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BPF_A = DATA_BUS[0:0];
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BPF_B = DATA_BUS[1:1];
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BPF_OE1 = DATA_BUS[2:2];
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BPF_OE2 = DATA_BUS[3:3];
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LPF_1 = DATA_BUS[4:4];
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LPF_2 = DATA_BUS[5:5];
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LPF_3 = DATA_BUS[6:6];
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k = 999;
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end
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else if (k == 200) //SEND PARAMS
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begin
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DATA_BUS_OUT[0:0] = ADC_OTR;
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DATA_BUS_OUT[1:1] = DAC_OTR;
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k = 201;
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end
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else if (k == 201)
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begin
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DATA_BUS_OUT[3:0] = ADC_MIN[11:8];
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k = 202;
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end
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else if (k == 202)
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begin
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DATA_BUS_OUT[7:0] = ADC_MIN[7:0];
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k = 203;
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end
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else if (k == 203)
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begin
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DATA_BUS_OUT[3:0] = ADC_MAX[11:8];
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k = 204;
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end
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else if (k == 204)
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begin
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DATA_BUS_OUT[7:0] = ADC_MAX[7:0];
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ADC_MINMAX_RESET=1;
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k = 999;
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end
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else if (k == 300) //TX IQ
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begin
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Q_HOLD[15:8] = DATA_BUS[7:0];
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k = 301;
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end
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else if (k == 301)
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begin
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Q_HOLD[7:0] = DATA_BUS[7:0];
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k = 302;
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end
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else if (k == 302)
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begin
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I_HOLD[15:8] = DATA_BUS[7:0];
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k = 303;
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end
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else if (k == 303)
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begin
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I_HOLD[7:0] = DATA_BUS[7:0];
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TX_I[15:0] = I_HOLD[15:0];
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TX_Q[15:0] = Q_HOLD[15:0];
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tx_iq_valid = 1;
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k = 999;
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end
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else if (k == 400) //RX IQ
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begin
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if(BUFFER_RX_tail == BUFFER_RX_head) //догнал буффер
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begin
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REG_RX_I[15:0] = 'd0;
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REG_RX_Q[15:0] = 'd0;
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end
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else
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begin
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REG_RX_I[15:0] = BUFFER_RX_I[BUFFER_RX_tail][15:0];
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REG_RX_Q[15:0] = BUFFER_RX_Q[BUFFER_RX_tail][15:0];
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if(BUFFER_RX_tail >= rx_buffer_length)
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BUFFER_RX_tail = 0;
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else
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BUFFER_RX_tail = BUFFER_RX_tail + 16'd1;
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end
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I_HOLD = REG_RX_I;
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Q_HOLD = REG_RX_Q;
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DATA_BUS_OUT[7:0] = Q_HOLD[15:8];
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k = 401;
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end
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else if (k == 401)
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begin
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DATA_BUS_OUT[7:0] = Q_HOLD[7:0];
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k = 402;
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end
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else if (k == 402)
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begin
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DATA_BUS_OUT[7:0] = I_HOLD[15:8];
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k = 403;
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end
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else if (k == 403)
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begin
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DATA_BUS_OUT[7:0] = I_HOLD[7:0];
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k = 999;
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end
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else if (k == 500) //BUS TEST
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begin
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Q_HOLD[7:0] = DATA_BUS[7:0];
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DATA_BUS_OE = 1;
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DATA_BUS_OUT[7:0] = Q_HOLD[7:0];
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k = 999;
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end
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else if (k == 700) //FPGA FLASH READ - SEND COMMAND
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begin
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DATA_BUS_OE = 0;
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FLASH_data_out[7:0] = DATA_BUS[7:0];
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if(FLASH_enable == 0)
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FLASH_enable = 1;
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else
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FLASH_continue_read = 1;
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k = 701;
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end
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else if (k == 701) //FPGA FLASH READ - READ ANSWER
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begin
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FLASH_continue_read = 0;
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DATA_BUS_OE = 1;
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if(FLASH_busy)
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DATA_BUS_OUT[7:0] = 'd255;
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else
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DATA_BUS_OUT[7:0] = FLASH_data_in[7:0];
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k = 700;
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end
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stage_debug=k;
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end
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always @ (posedge adcclk_in)
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begin
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//ADC MIN-MAX
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if(ADC_MINMAX_RESET == 1)
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begin
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ADC_MIN = 'd2000;
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ADC_MAX = -12'd2000;
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end
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if(ADC_MAX<ADC_IN)
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begin
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ADC_MAX=ADC_IN;
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end
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if(ADC_MIN>ADC_IN)
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begin
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ADC_MIN=ADC_IN;
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end
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end
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always @ (negedge adcclk_in)
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begin
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//RESET SYNC
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reset_n = sync_reset_n;
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end
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endmodule
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