Wolf-LITE/FPGA/rx_ciccomp_sim/synopsys/vcsmx/synopsys_sim.setup

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WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cycloneive_ver: ./libraries/cycloneive_ver/
altera: ./libraries/altera/
lpm: ./libraries/lpm/
sgate: ./libraries/sgate/
altera_mf: ./libraries/altera_mf/
altera_lnsim: ./libraries/altera_lnsim/
cycloneive: ./libraries/cycloneive/
LIBRARY_SCAN = TRUE