kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
581 wiersze
28 KiB
VHDL
581 wiersze
28 KiB
VHDL
-- -------------------------------------------------------------------------
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-- High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #625)
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-- Quartus Prime development tool and MATLAB/Simulink Interface
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--
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-- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly
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-- subject to the terms and conditions of the Intel FPGA Software License
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-- Agreement, Intel MegaCore Function License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by Intel
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-- and sold by Intel or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- ---------------------------------------------------------------------------
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-- VHDL created from rx_ciccomp_0002_rtl_core
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-- VHDL created on Fri Feb 12 16:11:12 2021
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.MATH_REAL.all;
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use std.TextIO.all;
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use work.dspba_library_package.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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LIBRARY lpm;
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USE lpm.lpm_components.all;
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entity rx_ciccomp_0002_rtl_core is
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port (
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xIn_v : in std_logic_vector(0 downto 0); -- sfix1
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xIn_c : in std_logic_vector(7 downto 0); -- sfix8
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xIn_0 : in std_logic_vector(31 downto 0); -- sfix32
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xOut_v : out std_logic_vector(0 downto 0); -- ufix1
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xOut_c : out std_logic_vector(7 downto 0); -- ufix8
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xOut_0 : out std_logic_vector(45 downto 0); -- sfix46
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clk : in std_logic;
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areset : in std_logic
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);
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end rx_ciccomp_0002_rtl_core;
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architecture normal of rx_ciccomp_0002_rtl_core is
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attribute altera_attribute : string;
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attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
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signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
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signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
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signal d_xIn_0_13_q : STD_LOGIC_VECTOR (31 downto 0);
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signal d_in0_m0_wi0_wo0_assign_id1_q_13_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0);
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signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_run_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_run_out : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_run_enableQ : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0);
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signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0);
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signal d_u0_m0_wo0_compute_q_15_q : STD_LOGIC_VECTOR (0 downto 0);
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signal d_u0_m0_wo0_compute_q_16_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0);
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attribute preserve : boolean;
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attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_inner_i : signal is true;
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signal u0_m0_wo0_wi0_r0_ra0_count0_q : STD_LOGIC_VECTOR (6 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_count0_i : UNSIGNED (5 downto 0);
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attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_i : signal is true;
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signal u0_m0_wo0_wi0_r0_ra0_count1_q : STD_LOGIC_VECTOR (6 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_count1_i : UNSIGNED (5 downto 0);
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attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_i : signal is true;
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signal u0_m0_wo0_wi0_r0_ra0_add_0_0_a : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_add_0_0_b : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_add_0_0_o : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_add_0_0_q : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_wi0_r0_wa0_q : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (5 downto 0);
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attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true;
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signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic;
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signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0);
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signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0);
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signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0);
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signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_ca0_i : UNSIGNED (5 downto 0);
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attribute preserve of u0_m0_wo0_ca0_i : signal is true;
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signal u0_m0_wo0_cm0_q : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_aseq_eq : std_logic;
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signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (45 downto 0);
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signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (45 downto 0);
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signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (45 downto 0);
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signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (45 downto 0);
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signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (45 downto 0);
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signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_oseq_eq : std_logic;
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signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im0_reset : std_logic;
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signal u0_m0_wo0_mtree_mult1_0_im0_q : STD_LOGIC_VECTOR (25 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im4_a0 : STD_LOGIC_VECTOR (14 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im4_b0 : STD_LOGIC_VECTOR (7 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im4_s1 : STD_LOGIC_VECTOR (22 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_im4_reset : std_logic;
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signal u0_m0_wo0_mtree_mult1_0_im4_q : STD_LOGIC_VECTOR (22 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_a : STD_LOGIC_VECTOR (40 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_b : STD_LOGIC_VECTOR (40 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_o : STD_LOGIC_VECTOR (40 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (5 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_align_8_qint : STD_LOGIC_VECTOR (39 downto 0);
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signal u0_m0_wo0_mtree_mult1_0_bjB3_q : STD_LOGIC_VECTOR (17 downto 0);
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begin
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-- VCC(CONSTANT,1)@0
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VCC_q <= "1";
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-- u0_m0_wo0_run(ENABLEGENERATOR,13)@10 + 2
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u0_m0_wo0_run_ctrl <= u0_m0_wo0_run_out & xIn_v & u0_m0_wo0_run_enableQ;
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u0_m0_wo0_run_clkproc: PROCESS (clk, areset)
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variable u0_m0_wo0_run_enable_c : SIGNED(6 downto 0);
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variable u0_m0_wo0_run_inc : SIGNED(1 downto 0);
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BEGIN
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IF (areset = '1') THEN
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u0_m0_wo0_run_q <= "0";
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u0_m0_wo0_run_enable_c := TO_SIGNED(62, 7);
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u0_m0_wo0_run_enableQ <= "0";
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u0_m0_wo0_run_count <= "00";
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u0_m0_wo0_run_inc := (others => '0');
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ELSIF (clk'EVENT AND clk = '1') THEN
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IF (u0_m0_wo0_run_out = "1") THEN
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IF (u0_m0_wo0_run_enable_c(6) = '1') THEN
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u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-63);
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ELSE
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u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1);
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END IF;
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u0_m0_wo0_run_enableQ <= STD_LOGIC_VECTOR(u0_m0_wo0_run_enable_c(6 downto 6));
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ELSE
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u0_m0_wo0_run_enableQ <= "0";
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END IF;
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CASE (u0_m0_wo0_run_ctrl) IS
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WHEN "000" | "001" => u0_m0_wo0_run_inc := "00";
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WHEN "010" | "011" => u0_m0_wo0_run_inc := "11";
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WHEN "100" => u0_m0_wo0_run_inc := "00";
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WHEN "101" => u0_m0_wo0_run_inc := "01";
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WHEN "110" => u0_m0_wo0_run_inc := "11";
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WHEN "111" => u0_m0_wo0_run_inc := "00";
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WHEN OTHERS =>
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END CASE;
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u0_m0_wo0_run_count <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_run_count) + SIGNED(u0_m0_wo0_run_inc));
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u0_m0_wo0_run_q <= u0_m0_wo0_run_out;
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END IF;
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END PROCESS;
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u0_m0_wo0_run_preEnaQ <= u0_m0_wo0_run_count(1 downto 1);
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u0_m0_wo0_run_out <= u0_m0_wo0_run_preEnaQ and VCC_q;
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-- u0_m0_wo0_memread(DELAY,14)@12
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u0_m0_wo0_memread : dspba_delay
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GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
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PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset );
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-- u0_m0_wo0_compute(DELAY,16)@12
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u0_m0_wo0_compute : dspba_delay
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GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
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PORT MAP ( xin => u0_m0_wo0_memread_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset );
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-- d_u0_m0_wo0_compute_q_15(DELAY,57)@12 + 3
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d_u0_m0_wo0_compute_q_15 : dspba_delay
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GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
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PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset );
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-- u0_m0_wo0_aseq(SEQUENCE,33)@15 + 1
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u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset)
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variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0);
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BEGIN
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IF (areset = '1') THEN
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u0_m0_wo0_aseq_c := "000000000";
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u0_m0_wo0_aseq_q <= "0";
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u0_m0_wo0_aseq_eq <= '0';
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ELSIF (clk'EVENT AND clk = '1') THEN
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IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
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IF (u0_m0_wo0_aseq_c = "000000000") THEN
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u0_m0_wo0_aseq_eq <= '1';
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ELSE
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u0_m0_wo0_aseq_eq <= '0';
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END IF;
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IF (u0_m0_wo0_aseq_eq = '1') THEN
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u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 63;
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ELSE
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u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1;
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END IF;
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u0_m0_wo0_aseq_q <= STD_LOGIC_VECTOR(u0_m0_wo0_aseq_c(8 downto 8));
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END IF;
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END IF;
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END PROCESS;
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-- d_u0_m0_wo0_compute_q_16(DELAY,58)@15 + 1
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d_u0_m0_wo0_compute_q_16 : dspba_delay
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GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
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PORT MAP ( xin => d_u0_m0_wo0_compute_q_15_q, xout => d_u0_m0_wo0_compute_q_16_q, clk => clk, aclr => areset );
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-- u0_m0_wo0_ca0(COUNTER,27)@12
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-- low=0, high=63, step=1, init=0
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u0_m0_wo0_ca0_clkproc: PROCESS (clk, areset)
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BEGIN
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IF (areset = '1') THEN
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u0_m0_wo0_ca0_i <= TO_UNSIGNED(0, 6);
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ELSIF (clk'EVENT AND clk = '1') THEN
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IF (u0_m0_wo0_compute_q = "1") THEN
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u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1;
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END IF;
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END IF;
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END PROCESS;
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u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i, 6)));
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-- u0_m0_wo0_cm0(LOOKUP,31)@12 + 1
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u0_m0_wo0_cm0_clkproc: PROCESS (clk, areset)
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BEGIN
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IF (areset = '1') THEN
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u0_m0_wo0_cm0_q <= "00000000";
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ELSIF (clk'EVENT AND clk = '1') THEN
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CASE (u0_m0_wo0_ca0_q) IS
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WHEN "000000" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000001" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000010" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000011" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000100" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000101" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000110" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "000111" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001000" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001001" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001010" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001011" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001100" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001101" => u0_m0_wo0_cm0_q <= "00000000";
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WHEN "001110" => u0_m0_wo0_cm0_q <= "11111111";
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WHEN "001111" => u0_m0_wo0_cm0_q <= "00000010";
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WHEN "010000" => u0_m0_wo0_cm0_q <= "11111101";
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WHEN "010001" => u0_m0_wo0_cm0_q <= "00000100";
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WHEN "010010" => u0_m0_wo0_cm0_q <= "11111010";
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WHEN "010011" => u0_m0_wo0_cm0_q <= "00001001";
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WHEN "010100" => u0_m0_wo0_cm0_q <= "11110100";
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WHEN "010101" => u0_m0_wo0_cm0_q <= "00001111";
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WHEN "010110" => u0_m0_wo0_cm0_q <= "11101100";
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WHEN "010111" => u0_m0_wo0_cm0_q <= "00011010";
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WHEN "011000" => u0_m0_wo0_cm0_q <= "11011110";
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WHEN "011001" => u0_m0_wo0_cm0_q <= "00101011";
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WHEN "011010" => u0_m0_wo0_cm0_q <= "11001010";
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WHEN "011011" => u0_m0_wo0_cm0_q <= "01000101";
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WHEN "011100" => u0_m0_wo0_cm0_q <= "10101010";
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WHEN "011101" => u0_m0_wo0_cm0_q <= "01101100";
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WHEN "011110" => u0_m0_wo0_cm0_q <= "10000000";
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WHEN "011111" => u0_m0_wo0_cm0_q <= "01110010";
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WHEN "100000" => u0_m0_wo0_cm0_q <= "01110010";
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WHEN "100001" => u0_m0_wo0_cm0_q <= "10000000";
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WHEN "100010" => u0_m0_wo0_cm0_q <= "01101100";
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WHEN "100011" => u0_m0_wo0_cm0_q <= "10101010";
|
|
WHEN "100100" => u0_m0_wo0_cm0_q <= "01000101";
|
|
WHEN "100101" => u0_m0_wo0_cm0_q <= "11001010";
|
|
WHEN "100110" => u0_m0_wo0_cm0_q <= "00101011";
|
|
WHEN "100111" => u0_m0_wo0_cm0_q <= "11011110";
|
|
WHEN "101000" => u0_m0_wo0_cm0_q <= "00011010";
|
|
WHEN "101001" => u0_m0_wo0_cm0_q <= "11101100";
|
|
WHEN "101010" => u0_m0_wo0_cm0_q <= "00001111";
|
|
WHEN "101011" => u0_m0_wo0_cm0_q <= "11110100";
|
|
WHEN "101100" => u0_m0_wo0_cm0_q <= "00001001";
|
|
WHEN "101101" => u0_m0_wo0_cm0_q <= "11111010";
|
|
WHEN "101110" => u0_m0_wo0_cm0_q <= "00000100";
|
|
WHEN "101111" => u0_m0_wo0_cm0_q <= "11111101";
|
|
WHEN "110000" => u0_m0_wo0_cm0_q <= "00000010";
|
|
WHEN "110001" => u0_m0_wo0_cm0_q <= "11111111";
|
|
WHEN "110010" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "110011" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "110100" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "110101" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "110110" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "110111" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111000" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111001" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111010" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111011" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111100" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111101" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111110" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN "111111" => u0_m0_wo0_cm0_q <= "00000000";
|
|
WHEN OTHERS => -- unreachable
|
|
u0_m0_wo0_cm0_q <= (others => '-');
|
|
END CASE;
|
|
END IF;
|
|
END PROCESS;
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,22)@12
|
|
-- low=0, high=63, step=1, init=0
|
|
u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(0, 6);
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (u0_m0_wo0_memread_q = "1") THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7)));
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@12
|
|
-- low=-1, high=62, step=-1, init=62
|
|
u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(62, 7);
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (u0_m0_wo0_memread_q = "1") THEN
|
|
IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 65;
|
|
ELSE
|
|
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1;
|
|
END IF;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7)));
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@12
|
|
u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6));
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@12
|
|
-- low=0, high=63, step=1, init=0
|
|
u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 6);
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (u0_m0_wo0_memread_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN
|
|
u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 7)));
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,23)@12 + 1
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q);
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_q);
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= (others => '0');
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b));
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(7 downto 0);
|
|
|
|
-- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,24)@13
|
|
u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(5 downto 0));
|
|
u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(5 downto 0));
|
|
|
|
-- d_xIn_0_13(DELAY,55)@10 + 3
|
|
d_xIn_0_13 : dspba_delay
|
|
GENERIC MAP ( width => 32, depth => 3, reset_kind => "ASYNC" )
|
|
PORT MAP ( xin => xIn_0, xout => d_xIn_0_13_q, clk => clk, aclr => areset );
|
|
|
|
-- d_in0_m0_wi0_wo0_assign_id1_q_13(DELAY,56)@10 + 3
|
|
d_in0_m0_wi0_wo0_assign_id1_q_13 : dspba_delay
|
|
GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
|
|
PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_13_q, clk => clk, aclr => areset );
|
|
|
|
-- u0_m0_wo0_wi0_r0_wa0(COUNTER,25)@13
|
|
-- low=0, high=63, step=1, init=63
|
|
u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(63, 6);
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (d_in0_m0_wi0_wo0_assign_id1_q_13_q = "1") THEN
|
|
u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 6)));
|
|
|
|
-- u0_m0_wo0_wi0_r0_memr0(DUALMEM,26)@13
|
|
u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_13_q);
|
|
u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q;
|
|
u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b;
|
|
u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram
|
|
GENERIC MAP (
|
|
ram_block_type => "M9K",
|
|
operation_mode => "DUAL_PORT",
|
|
width_a => 32,
|
|
widthad_a => 6,
|
|
numwords_a => 64,
|
|
width_b => 32,
|
|
widthad_b => 6,
|
|
numwords_b => 64,
|
|
lpm_type => "altsyncram",
|
|
width_byteena_a => 1,
|
|
address_reg_b => "CLOCK0",
|
|
indata_reg_b => "CLOCK0",
|
|
wrcontrol_wraddress_reg_b => "CLOCK0",
|
|
rdcontrol_reg_b => "CLOCK0",
|
|
byteena_reg_b => "CLOCK0",
|
|
outdata_reg_b => "CLOCK0",
|
|
outdata_aclr_b => "NONE",
|
|
clock_enable_input_a => "NORMAL",
|
|
clock_enable_input_b => "NORMAL",
|
|
clock_enable_output_b => "NORMAL",
|
|
read_during_write_mode_mixed_ports => "DONT_CARE",
|
|
power_up_uninitialized => "FALSE",
|
|
init_file => "UNUSED",
|
|
intended_device_family => "Cyclone IV E"
|
|
)
|
|
PORT MAP (
|
|
clocken0 => '1',
|
|
clock0 => clk,
|
|
address_a => u0_m0_wo0_wi0_r0_memr0_aa,
|
|
data_a => u0_m0_wo0_wi0_r0_memr0_ia,
|
|
wren_a => d_in0_m0_wi0_wo0_assign_id1_q_13_q(0),
|
|
address_b => u0_m0_wo0_wi0_r0_memr0_ab,
|
|
q_b => u0_m0_wo0_wi0_r0_memr0_iq
|
|
);
|
|
u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0);
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,54)@13
|
|
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0));
|
|
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17));
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_im4(MULT,47)@13 + 2
|
|
u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c);
|
|
u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q);
|
|
u0_m0_wo0_mtree_mult1_0_im4_reset <= areset;
|
|
u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult
|
|
GENERIC MAP (
|
|
lpm_widtha => 15,
|
|
lpm_widthb => 8,
|
|
lpm_widthp => 23,
|
|
lpm_widths => 1,
|
|
lpm_type => "LPM_MULT",
|
|
lpm_representation => "SIGNED",
|
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
|
|
lpm_pipeline => 2
|
|
)
|
|
PORT MAP (
|
|
dataa => u0_m0_wo0_mtree_mult1_0_im4_a0,
|
|
datab => u0_m0_wo0_mtree_mult1_0_im4_b0,
|
|
clken => VCC_q(0),
|
|
aclr => u0_m0_wo0_mtree_mult1_0_im4_reset,
|
|
clock => clk,
|
|
result => u0_m0_wo0_mtree_mult1_0_im4_s1
|
|
);
|
|
u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1;
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,51)@15
|
|
u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000";
|
|
u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0);
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,46)@13
|
|
u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b;
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_im0(MULT,43)@13 + 2
|
|
u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q);
|
|
u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q);
|
|
u0_m0_wo0_mtree_mult1_0_im0_reset <= areset;
|
|
u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult
|
|
GENERIC MAP (
|
|
lpm_widtha => 18,
|
|
lpm_widthb => 8,
|
|
lpm_widthp => 26,
|
|
lpm_widths => 1,
|
|
lpm_type => "LPM_MULT",
|
|
lpm_representation => "SIGNED",
|
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
|
|
lpm_pipeline => 2
|
|
)
|
|
PORT MAP (
|
|
dataa => u0_m0_wo0_mtree_mult1_0_im0_a0,
|
|
datab => u0_m0_wo0_mtree_mult1_0_im0_b0,
|
|
clken => VCC_q(0),
|
|
aclr => u0_m0_wo0_mtree_mult1_0_im0_reset,
|
|
clock => clk,
|
|
result => u0_m0_wo0_mtree_mult1_0_im0_s1
|
|
);
|
|
u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1;
|
|
|
|
-- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,53)@15 + 1
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q));
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q));
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_o <= (others => '0');
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_mtree_mult1_0_result_add_0_0_a) + SIGNED(u0_m0_wo0_mtree_mult1_0_result_add_0_0_b));
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0);
|
|
|
|
-- u0_m0_wo0_accum(ADD,34)@16 + 1
|
|
u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((45 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q));
|
|
u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q);
|
|
u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a;
|
|
u0_m0_wo0_accum_clkproc: PROCESS (clk, areset)
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_accum_o <= (others => '0');
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (d_u0_m0_wo0_compute_q_16_q = "1") THEN
|
|
IF (u0_m0_wo0_aseq_q = "1") THEN
|
|
u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i;
|
|
ELSE
|
|
u0_m0_wo0_accum_o <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_accum_a) + SIGNED(u0_m0_wo0_accum_b));
|
|
END IF;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(45 downto 0);
|
|
|
|
-- GND(CONSTANT,0)@0
|
|
GND_q <= "0";
|
|
|
|
-- u0_m0_wo0_oseq(SEQUENCE,35)@15 + 1
|
|
u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset)
|
|
variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0);
|
|
BEGIN
|
|
IF (areset = '1') THEN
|
|
u0_m0_wo0_oseq_c := "000111111";
|
|
u0_m0_wo0_oseq_q <= "0";
|
|
u0_m0_wo0_oseq_eq <= '0';
|
|
ELSIF (clk'EVENT AND clk = '1') THEN
|
|
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
|
|
IF (u0_m0_wo0_oseq_c = "000000000") THEN
|
|
u0_m0_wo0_oseq_eq <= '1';
|
|
ELSE
|
|
u0_m0_wo0_oseq_eq <= '0';
|
|
END IF;
|
|
IF (u0_m0_wo0_oseq_eq = '1') THEN
|
|
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 63;
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ELSE
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u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1;
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END IF;
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u0_m0_wo0_oseq_q <= STD_LOGIC_VECTOR(u0_m0_wo0_oseq_c(8 downto 8));
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END IF;
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END IF;
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END PROCESS;
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-- u0_m0_wo0_oseq_gated(LOGICAL,36)@16
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u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_16_q;
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-- u0_m0_wo0_oseq_gated_reg(REG,37)@16 + 1
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u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset)
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BEGIN
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IF (areset = '1') THEN
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u0_m0_wo0_oseq_gated_reg_q <= "0";
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ELSIF (clk'EVENT AND clk = '1') THEN
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u0_m0_wo0_oseq_gated_reg_q <= STD_LOGIC_VECTOR(u0_m0_wo0_oseq_gated_q);
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END IF;
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END PROCESS;
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-- xOut(PORTOUT,42)@17 + 1
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xOut_v <= u0_m0_wo0_oseq_gated_reg_q;
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|
xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q);
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xOut_0 <= u0_m0_wo0_accum_q;
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END normal;
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