kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
26 wiersze
3.1 KiB
Plaintext
26 wiersze
3.1 KiB
Plaintext
set_global_assignment -entity "rx_ciccomp" -library "lib_rx_ciccomp" -name IP_TOOL_NAME "altera_fir_compiler_ii"
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set_global_assignment -entity "rx_ciccomp" -library "lib_rx_ciccomp" -name IP_TOOL_VERSION "18.1"
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set_global_assignment -entity "rx_ciccomp" -library "lib_rx_ciccomp" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "lib_rx_ciccomp" -name SPD_FILE [file join $::quartus(sip_path) "rx_ciccomp.spd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/dspba_library_package.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/dspba_library.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_math_pkg_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_lib_pkg_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/altera_avalon_sc_fifo.v"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_ast.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_nativelink.tcl"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_msim.tcl"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_tb.vhd"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_mlab.m"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_model.m"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_coef_int.txt"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_input.txt"]
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set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_param.txt"]
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