kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
31 wiersze
1.6 KiB
Plaintext
31 wiersze
1.6 KiB
Plaintext
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
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Progress: Loading FPGA/rx_cic.qsys
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Progress: Reading input file
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Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
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Progress: Parameterizing module cic_ii_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Warning: rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
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Progress: Loading FPGA/rx_cic.qsys
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Progress: Reading input file
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Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
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Progress: Parameterizing module cic_ii_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Warning: rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release
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Info: rx_cic: Generating rx_cic "rx_cic" for QUARTUS_SYNTH
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Info: cic_ii_0: "rx_cic" instantiated altera_cic_ii "cic_ii_0"
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Info: rx_cic: Done "rx_cic" with 2 modules, 30 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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