kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
17 wiersze
922 B
Plaintext
17 wiersze
922 B
Plaintext
component rx_cic is
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port (
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in_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
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in_valid : in std_logic := 'X'; -- valid
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in_ready : out std_logic; -- ready
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in_data : in std_logic_vector(22 downto 0) := (others => 'X'); -- in_data
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out_data : out std_logic_vector(31 downto 0); -- out_data
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out_error : out std_logic_vector(1 downto 0); -- error
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out_valid : out std_logic; -- valid
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out_ready : in std_logic := 'X'; -- ready
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clken : in std_logic := 'X'; -- clken
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clk : in std_logic := 'X'; -- clk
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reset_n : in std_logic := 'X' -- reset_n
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);
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end component rx_cic;
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