kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
98 wiersze
3.7 KiB
XML
98 wiersze
3.7 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element cic_ii_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="EP4CE10E22C8" />
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<parameter name="deviceFamily" value="Cyclone IV E" />
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<parameter name="deviceSpeedGrade" value="8" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="WOLF-LITE.qpf" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="av_st_in" internal="cic_ii_0.av_st_in" type="conduit" dir="end">
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<port name="in_error" internal="in_error" />
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<port name="in_valid" internal="in_valid" />
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<port name="in_ready" internal="in_ready" />
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<port name="in_data" internal="in_data" />
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</interface>
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<interface
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name="av_st_out"
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internal="cic_ii_0.av_st_out"
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type="conduit"
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dir="end">
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<port name="out_data" internal="out_data" />
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<port name="out_error" internal="out_error" />
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<port name="out_valid" internal="out_valid" />
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<port name="out_ready" internal="out_ready" />
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</interface>
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<interface name="clken" internal="cic_ii_0.clken" type="conduit" dir="end">
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<port name="clken" internal="clken" />
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</interface>
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<interface name="clock" internal="cic_ii_0.clock" type="clock" dir="end">
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<port name="clk" internal="clk" />
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</interface>
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<interface name="rate" internal="cic_ii_0.rate" />
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<interface name="reset" internal="cic_ii_0.reset" type="reset" dir="end">
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<port name="reset_n" internal="reset_n" />
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</interface>
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<module
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name="cic_ii_0"
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kind="altera_cic_ii"
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version="18.1"
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enabled="1"
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autoexport="1">
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<parameter name="CH_PER_INT" value="1" />
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<parameter name="CLK_EN_PORT" value="true" />
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<parameter name="D_DELAY" value="1" />
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<parameter name="FILTER_TYPE" value="decimator" />
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<parameter name="INTERFACES" value="1" />
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<parameter name="IN_WIDTH" value="23" />
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<parameter name="RCF_FIX" value="1340" />
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<parameter name="RCF_LB" value="8" />
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<parameter name="RCF_UB" value="21" />
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<parameter name="REQ_DIF_MEM" value="logic_element" />
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<parameter name="REQ_INT_MEM" value="logic_element" />
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<parameter name="REQ_OUT_WIDTH" value="32" />
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<parameter name="REQ_PIPELINE" value="0" />
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<parameter name="ROUND_TYPE" value="TRUNCATE" />
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<parameter name="STAGES" value="6" />
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<parameter name="VRC_EN" value="0" />
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<parameter name="design_env" value="NATIVE" />
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<parameter name="hyper_opt_select" value="0" />
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<parameter name="selected_device_family" value="Cyclone IV E" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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