kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
104 wiersze
3.7 KiB
Verilog
104 wiersze
3.7 KiB
Verilog
// megafunction wizard: %LPM_MUX%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_MUX
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// ============================================================
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// File Name: mux14.v
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// Megafunction Name(s):
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// LPM_MUX
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module mux14 (
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data0x,
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data1x,
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sel,
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result);
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input [13:0] data0x;
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input [13:0] data1x;
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input sel;
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output [13:0] result;
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wire [13:0] sub_wire5;
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wire [13:0] sub_wire2 = data1x[13:0];
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wire [13:0] sub_wire0 = data0x[13:0];
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wire [27:0] sub_wire1 = {sub_wire2, sub_wire0};
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wire sub_wire3 = sel;
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wire sub_wire4 = sub_wire3;
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wire [13:0] result = sub_wire5[13:0];
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lpm_mux LPM_MUX_component (
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.data (sub_wire1),
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.sel (sub_wire4),
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.result (sub_wire5)
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// synopsys translate_off
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,
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.aclr (),
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.clken (),
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.clock ()
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// synopsys translate_on
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);
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defparam
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LPM_MUX_component.lpm_size = 2,
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LPM_MUX_component.lpm_type = "LPM_MUX",
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LPM_MUX_component.lpm_width = 14,
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LPM_MUX_component.lpm_widths = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
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// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
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// Retrieval info: USED_PORT: data0x 0 0 14 0 INPUT NODEFVAL "data0x[13..0]"
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// Retrieval info: USED_PORT: data1x 0 0 14 0 INPUT NODEFVAL "data1x[13..0]"
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// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
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// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
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// Retrieval info: CONNECT: @data 0 0 14 0 data0x 0 0 14 0
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// Retrieval info: CONNECT: @data 0 0 14 14 data1x 0 0 14 0
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// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
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// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL mux14_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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