kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
24 wiersze
707 B
Verilog
24 wiersze
707 B
Verilog
module data_shifter(
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input wire [(in_width-1):0] data_in_I,
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input wire data_valid_I,
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input wire [(in_width-1):0] data_in_Q,
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input wire data_valid_Q,
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input unsigned [7:0] distance,
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input wire enabled,
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output wire [(out_width-1):0] data_out_I,
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output wire data_valid_out_I,
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output wire [(out_width-1):0] data_out_Q,
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output wire data_valid_out_Q
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);
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parameter in_width = 88;
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parameter out_width = 32;
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assign data_valid_out_I = enabled ? data_valid_I : 0;
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assign data_valid_out_Q = enabled ? data_valid_Q : 0;
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assign data_out_I[(out_width-1):0] = enabled ? data_in_I[(distance-1) -: out_width] : 0;
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assign data_out_Q[(out_width-1):0] = enabled ? data_in_Q[(distance-1) -: out_width] : 0;
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endmodule
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