Wolf-LITE/FPGA/clock_buffer/clock_buffer.xml

<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2019.11.10.03:26:30"
 outputDirectory="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Cyclone IV E"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="EP4CE22E22C8"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="8"
     onHdl="0"
     affectsHdl="1" />
  <interface name="altclkctrl_input" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="inclk" direction="input" role="inclk" width="1" />
  </interface>
  <interface name="altclkctrl_output" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="outclk" direction="output" role="outclk" width="1" />
  </interface>
 </perimeter>
 <entity
   path=""
   parameterizationKey="clock_buffer:1.0:AUTO_DEVICE=EP4CE22E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1573341989,AUTO_UNIQUE_ID=(altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
   instancePathKey="clock_buffer"
   kind="clock_buffer"
   version="1.0"
   name="clock_buffer">
  <parameter name="AUTO_GENERATION_ID" value="1573341989" />
  <parameter name="AUTO_DEVICE" value="EP4CE22E22C8" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
  <generatedFiles>
   <file
       path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/clock_buffer.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
       type="VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer.qsys" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Debug" culprit="clock_buffer">queue size: 0 starting:clock_buffer "clock_buffer"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="clock_buffer"><![CDATA["<b>clock_buffer</b>" reuses <b>altclkctrl</b> "<b>submodules/clock_buffer_altclkctrl_0</b>"]]></message>
   <message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
   instancePathKey="clock_buffer:.:altclkctrl_0"
   kind="altclkctrl"
   version="18.1"
   name="clock_buffer_altclkctrl_0">
  <parameter name="NUMBER_OF_CLOCKS" value="1" />
  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
  <parameter name="GUI_USE_ENA" value="false" />
  <parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
  <parameter name="ENA_REGISTER_MODE" value="1" />
  <parameter name="CLOCK_TYPE" value="1" />
  <generatedFiles>
   <file
       path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
       type="VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="clock_buffer" as="altclkctrl_0" />
  <messages>
   <message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  </messages>
 </entity>
</deploy>