kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
73 wiersze
2.5 KiB
XML
73 wiersze
2.5 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element altclkctrl_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="EP4CE22E22C8" />
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<parameter name="deviceFamily" value="Cyclone IV E" />
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<parameter name="deviceSpeedGrade" value="8" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="altclkctrl_input"
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internal="altclkctrl_0.altclkctrl_input"
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type="conduit"
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dir="end">
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<port name="inclk" internal="inclk" />
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</interface>
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<interface
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name="altclkctrl_output"
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internal="altclkctrl_0.altclkctrl_output"
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type="conduit"
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dir="end">
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<port name="outclk" internal="outclk" />
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</interface>
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<module
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name="altclkctrl_0"
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kind="altclkctrl"
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version="18.1"
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enabled="1"
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autoexport="1">
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<parameter name="CLOCK_TYPE" value="1" />
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<parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="ENA_REGISTER_MODE" value="1" />
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<parameter name="GUI_USE_ENA" value="false" />
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<parameter name="NUMBER_OF_CLOCKS" value="1" />
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<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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