Wolf-LITE/FPGA/MAIN_PLL.qip

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MAIN_PLL.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MAIN_PLL.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MAIN_PLL.ppf"]