kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
29 wiersze
1.6 KiB
Plaintext
29 wiersze
1.6 KiB
Plaintext
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG --family="Cyclone IV E" --part=EP4CE10E22C8
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Progress: Loading FPGA/DEBUG.qsys
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Progress: Reading input file
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Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
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Progress: Parameterizing module in_system_sources_probes_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
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Progress: Loading FPGA/DEBUG.qsys
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Progress: Reading input file
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Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
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Progress: Parameterizing module in_system_sources_probes_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: DEBUG: Generating DEBUG "DEBUG" for QUARTUS_SYNTH
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Info: in_system_sources_probes_0: "DEBUG" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
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Info: DEBUG: Done "DEBUG" with 2 modules, 2 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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