kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
128 wiersze
5.9 KiB
XML
128 wiersze
5.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2020.10.21.00:22:13"
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outputDirectory="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="Cyclone IV E"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="EP4CE10E22C8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="8"
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onHdl="0"
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affectsHdl="1" />
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<interface name="probes" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="probe" direction="input" role="probe" width="12" />
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</interface>
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</perimeter>
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<entity
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path=""
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parameterizationKey="DEBUG:1.0:AUTO_DEVICE=EP4CE10E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1603225332,AUTO_UNIQUE_ID=(altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=ADC,probe_width=12,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0)"
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instancePathKey="DEBUG"
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kind="DEBUG"
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version="1.0"
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name="DEBUG">
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<parameter name="AUTO_GENERATION_ID" value="1603225332" />
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<parameter name="AUTO_DEVICE" value="EP4CE10E22C8" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<generatedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/DEBUG.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/submodules/altsource_probe_top.v"
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type="VERILOG"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="DEBUG">queue size: 0 starting:DEBUG "DEBUG"</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug">Transform: CustomInstructionTransform</message>
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<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="DEBUG"><![CDATA["<b>DEBUG</b>" reuses <b>altera_in_system_sources_probes</b> "<b>submodules/altsource_probe_top</b>"]]></message>
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<message level="Debug" culprit="DEBUG">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
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<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=ADC,probe_width=12,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0"
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instancePathKey="DEBUG:.:in_system_sources_probes_0"
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kind="altera_in_system_sources_probes"
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version="18.1"
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name="altsource_probe_top">
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<parameter name="create_source_clock" value="false" />
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<parameter name="instance_id" value="ADC" />
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<parameter name="source_initial_value" value="0" />
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<parameter name="sld_auto_instance_index" value="YES" />
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<parameter name="sld_instance_index" value="0" />
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<parameter name="probe_width" value="12" />
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<parameter name="source_width" value="0" />
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<parameter name="create_source_clock_enable" value="false" />
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<parameter name="device_family" value="Cyclone IV E" />
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<parameter name="enable_metastability" value="NO" />
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<parameter name="gui_use_auto_index" value="true" />
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<generatedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/submodules/altsource_probe_top.v"
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type="VERILOG"
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attributes="" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="DEBUG" as="in_system_sources_probes_0" />
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<messages>
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<message level="Debug" culprit="DEBUG">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
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<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
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</messages>
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</entity>
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</deploy>
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