kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
128 wiersze
4.9 KiB
Verilog
128 wiersze
4.9 KiB
Verilog
// megafunction wizard: %LPM_ADD_SUB%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_ADD_SUB
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// ============================================================
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// File Name: ADC_Latch.v
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// Megafunction Name(s):
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// LPM_ADD_SUB
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module ADC_Latch (
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clken,
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clock,
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dataa,
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datab,
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result);
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input clken;
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input clock;
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input [11:0] dataa;
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input [11:0] datab;
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output [11:0] result;
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wire [11:0] sub_wire0;
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wire [11:0] result = sub_wire0[11:0];
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lpm_add_sub LPM_ADD_SUB_component (
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.clken (clken),
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.clock (clock),
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.dataa (dataa),
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.datab (datab),
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.result (sub_wire0)
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// synopsys translate_off
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,
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.aclr (),
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.add_sub (),
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.cin (),
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.cout (),
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.overflow ()
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// synopsys translate_on
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);
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defparam
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LPM_ADD_SUB_component.lpm_direction = "ADD",
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LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
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LPM_ADD_SUB_component.lpm_pipeline = 1,
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LPM_ADD_SUB_component.lpm_representation = "SIGNED",
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LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
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LPM_ADD_SUB_component.lpm_width = 12;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
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// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
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// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
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// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
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// Retrieval info: PRIVATE: Function NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
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// Retrieval info: PRIVATE: Latency NUMERIC "1"
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// Retrieval info: PRIVATE: Overflow NUMERIC "0"
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// Retrieval info: PRIVATE: RadixA NUMERIC "10"
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// Retrieval info: PRIVATE: RadixB NUMERIC "10"
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// Retrieval info: PRIVATE: Representation NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
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// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
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// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
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// Retrieval info: PRIVATE: aclr NUMERIC "0"
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// Retrieval info: PRIVATE: clken NUMERIC "1"
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// Retrieval info: PRIVATE: nBit NUMERIC "12"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
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// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
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// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
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// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: dataa 0 0 12 0 INPUT NODEFVAL "dataa[11..0]"
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// Retrieval info: USED_PORT: datab 0 0 12 0 INPUT NODEFVAL "datab[11..0]"
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// Retrieval info: USED_PORT: result 0 0 12 0 OUTPUT NODEFVAL "result[11..0]"
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// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @dataa 0 0 12 0 dataa 0 0 12 0
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// Retrieval info: CONNECT: @datab 0 0 12 0 datab 0 0 12 0
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// Retrieval info: CONNECT: result 0 0 12 0 @result 0 0 12 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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