Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\tx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\tx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/tx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
Progress: Parameterizing module cic_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\tx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\tx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/tx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
Progress: Parameterizing module cic_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: tx_cic: Generating tx_cic "tx_cic" for QUARTUS_SYNTH
Info: cic_ii_0: "tx_cic" instantiated altera_cic_ii "cic_ii_0"
Info: tx_cic: Done "tx_cic" with 2 modules, 30 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis