Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\nco.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\nco --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/nco.qsys
Progress: Reading input file
Progress: Adding nco_ii_0 [altera_nco_ii 18.1]
Progress: Parameterizing module nco_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\nco.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\nco\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/nco.qsys
Progress: Reading input file
Progress: Adding nco_ii_0 [altera_nco_ii 18.1]
Progress: Parameterizing module nco_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: nco: Generating nco "nco" for QUARTUS_SYNTH
Info: nco_ii_0: "nco" instantiated altera_nco_ii "nco_ii_0"
Info: nco: Done "nco" with 2 modules, 18 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis